From 4d338ee40ba89e508c5d3e1b4af956af7cb5e12e Mon Sep 17 00:00:00 2001 From: Howard Chiu Date: Fri, 1 Apr 2022 06:59:06 +0000 Subject: ARM: dts: aspeed: ast2600-evb: Enable RX delay for MAC0/MAC1 Since mac0/1 and mac2/3 are physically located on different die, they have different properties by nature, which is mac0/1 has smaller delay step. The property 'phy-mode' on ast2600 mac0 and mac1 is recommended to set to 'rgmii-rxid' which enables the RX interface delay from the PHY chip. Refer page 45 of SDK User Guide v08.00 https://github.com/AspeedTech-BMC/openbmc/releases/download/v08.00/SDK_User_Guide_v08.00.pdf Fixes: 2ca5646b5c2f ("ARM: dts: aspeed: Add AST2600 and EVB") Signed-off-by: Howard Chiu Link: https://lore.kernel.org/r/SG2PR06MB23152A548AAE81140B57DD69E6E09@SG2PR06MB2315.apcprd06.prod.outlook.com Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-ast2600-evb.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/aspeed-ast2600-evb.dts b/arch/arm/boot/dts/aspeed-ast2600-evb.dts index b7eb552640cb..788448cdd6b3 100644 --- a/arch/arm/boot/dts/aspeed-ast2600-evb.dts +++ b/arch/arm/boot/dts/aspeed-ast2600-evb.dts @@ -103,7 +103,7 @@ &mac0 { status = "okay"; - phy-mode = "rgmii"; + phy-mode = "rgmii-rxid"; phy-handle = <ðphy0>; pinctrl-names = "default"; @@ -114,7 +114,7 @@ &mac1 { status = "okay"; - phy-mode = "rgmii"; + phy-mode = "rgmii-rxid"; phy-handle = <ðphy1>; pinctrl-names = "default"; -- cgit v1.2.3-59-g8ed1b From 651b79e8c9e208e84e2cfb4291e262f87b97c333 Mon Sep 17 00:00:00 2001 From: Cédric Le Goater Date: Mon, 9 May 2022 19:56:06 +0200 Subject: ARM: dts: aspeed: Adjust "reg" property of FMC/SPI controllers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This is compatible with the current driver and addresses issues when running 'make dt_binding_check'. Cc: Chin-Ting Kuo Tested-by: Joel Stanley Tested-by: Tao Ren Tested-by: Jae Hyun Yoo Signed-off-by: Cédric Le Goater Link: https://lore.kernel.org/r/20220509175616.1089346-2-clg@kaod.org Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-g4.dtsi | 6 ++---- arch/arm/boot/dts/aspeed-g5.dtsi | 9 +++------ arch/arm/boot/dts/aspeed-g6.dtsi | 9 +++------ 3 files changed, 8 insertions(+), 16 deletions(-) diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi index fa8b581c3d6c..3b7b98e787e7 100644 --- a/arch/arm/boot/dts/aspeed-g4.dtsi +++ b/arch/arm/boot/dts/aspeed-g4.dtsi @@ -54,8 +54,7 @@ ranges; fmc: spi@1e620000 { - reg = < 0x1e620000 0x94 - 0x20000000 0x10000000 >; + reg = <0x1e620000 0x94>, <0x20000000 0x10000000>; #address-cells = <1>; #size-cells = <0>; compatible = "aspeed,ast2400-fmc"; @@ -91,8 +90,7 @@ }; spi: spi@1e630000 { - reg = < 0x1e630000 0x18 - 0x30000000 0x10000000 >; + reg = <0x1e630000 0x18>, <0x30000000 0x10000000>; #address-cells = <1>; #size-cells = <0>; compatible = "aspeed,ast2400-spi"; diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi index 4147b397c883..1e727cbaab14 100644 --- a/arch/arm/boot/dts/aspeed-g5.dtsi +++ b/arch/arm/boot/dts/aspeed-g5.dtsi @@ -55,8 +55,7 @@ ranges; fmc: spi@1e620000 { - reg = < 0x1e620000 0xc4 - 0x20000000 0x10000000 >; + reg = <0x1e620000 0xc4>, <0x20000000 0x10000000>; #address-cells = <1>; #size-cells = <0>; compatible = "aspeed,ast2500-fmc"; @@ -84,8 +83,7 @@ }; spi1: spi@1e630000 { - reg = < 0x1e630000 0xc4 - 0x30000000 0x08000000 >; + reg = <0x1e630000 0xc4>, <0x30000000 0x08000000>; #address-cells = <1>; #size-cells = <0>; compatible = "aspeed,ast2500-spi"; @@ -106,8 +104,7 @@ }; spi2: spi@1e631000 { - reg = < 0x1e631000 0xc4 - 0x38000000 0x08000000 >; + reg = <0x1e631000 0xc4>, <0x38000000 0x08000000>; #address-cells = <1>; #size-cells = <0>; compatible = "aspeed,ast2500-spi"; diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed-g6.dtsi index 9d2a0ce4ca06..ff76c29965e1 100644 --- a/arch/arm/boot/dts/aspeed-g6.dtsi +++ b/arch/arm/boot/dts/aspeed-g6.dtsi @@ -95,8 +95,7 @@ }; fmc: spi@1e620000 { - reg = < 0x1e620000 0xc4 - 0x20000000 0x10000000 >; + reg = <0x1e620000 0xc4>, <0x20000000 0x10000000>; #address-cells = <1>; #size-cells = <0>; compatible = "aspeed,ast2600-fmc"; @@ -124,8 +123,7 @@ }; spi1: spi@1e630000 { - reg = < 0x1e630000 0xc4 - 0x30000000 0x10000000 >; + reg = <0x1e630000 0xc4>, <0x30000000 0x10000000>; #address-cells = <1>; #size-cells = <0>; compatible = "aspeed,ast2600-spi"; @@ -146,8 +144,7 @@ }; spi2: spi@1e631000 { - reg = < 0x1e631000 0xc4 - 0x50000000 0x10000000 >; + reg = <0x1e631000 0xc4>, <0x50000000 0x10000000>; #address-cells = <1>; #size-cells = <0>; compatible = "aspeed,ast2600-spi"; -- cgit v1.2.3-59-g8ed1b From 4a92d02fce73af8e9932126dabd82a0c07e78290 Mon Sep 17 00:00:00 2001 From: Cédric Le Goater Date: Mon, 9 May 2022 19:56:14 +0200 Subject: ARM: dts: aspeed: Enable Dual SPI RX transfers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit All these controllers support at least Dual SPI. Update the DTs. Reviewed-by: Joel Stanley Tested-by: Joel Stanley Tested-by: Tao Ren Tested-by: Jae Hyun Yoo Signed-off-by: Cédric Le Goater Link: https://lore.kernel.org/r/20220509175616.1089346-10-clg@kaod.org Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-g4.dtsi | 6 ++++++ arch/arm/boot/dts/aspeed-g5.dtsi | 7 +++++++ arch/arm/boot/dts/aspeed-g6.dtsi | 8 ++++++++ 3 files changed, 21 insertions(+) diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi index 3b7b98e787e7..1c6354cec9f2 100644 --- a/arch/arm/boot/dts/aspeed-g4.dtsi +++ b/arch/arm/boot/dts/aspeed-g4.dtsi @@ -64,27 +64,32 @@ flash@0 { reg = < 0 >; compatible = "jedec,spi-nor"; + spi-rx-bus-width = <2>; spi-max-frequency = <50000000>; status = "disabled"; }; flash@1 { reg = < 1 >; compatible = "jedec,spi-nor"; + spi-rx-bus-width = <2>; status = "disabled"; }; flash@2 { reg = < 2 >; compatible = "jedec,spi-nor"; + spi-rx-bus-width = <2>; status = "disabled"; }; flash@3 { reg = < 3 >; compatible = "jedec,spi-nor"; + spi-rx-bus-width = <2>; status = "disabled"; }; flash@4 { reg = < 4 >; compatible = "jedec,spi-nor"; + spi-rx-bus-width = <2>; status = "disabled"; }; }; @@ -100,6 +105,7 @@ reg = < 0 >; compatible = "jedec,spi-nor"; spi-max-frequency = <50000000>; + spi-rx-bus-width = <2>; status = "disabled"; }; }; diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi index 1e727cbaab14..c89092c3905b 100644 --- a/arch/arm/boot/dts/aspeed-g5.dtsi +++ b/arch/arm/boot/dts/aspeed-g5.dtsi @@ -66,18 +66,21 @@ reg = < 0 >; compatible = "jedec,spi-nor"; spi-max-frequency = <50000000>; + spi-rx-bus-width = <2>; status = "disabled"; }; flash@1 { reg = < 1 >; compatible = "jedec,spi-nor"; spi-max-frequency = <50000000>; + spi-rx-bus-width = <2>; status = "disabled"; }; flash@2 { reg = < 2 >; compatible = "jedec,spi-nor"; spi-max-frequency = <50000000>; + spi-rx-bus-width = <2>; status = "disabled"; }; }; @@ -93,12 +96,14 @@ reg = < 0 >; compatible = "jedec,spi-nor"; spi-max-frequency = <50000000>; + spi-rx-bus-width = <2>; status = "disabled"; }; flash@1 { reg = < 1 >; compatible = "jedec,spi-nor"; spi-max-frequency = <50000000>; + spi-rx-bus-width = <2>; status = "disabled"; }; }; @@ -114,12 +119,14 @@ reg = < 0 >; compatible = "jedec,spi-nor"; spi-max-frequency = <50000000>; + spi-rx-bus-width = <2>; status = "disabled"; }; flash@1 { reg = < 1 >; compatible = "jedec,spi-nor"; spi-max-frequency = <50000000>; + spi-rx-bus-width = <2>; status = "disabled"; }; }; diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed-g6.dtsi index ff76c29965e1..19c15e7fde60 100644 --- a/arch/arm/boot/dts/aspeed-g6.dtsi +++ b/arch/arm/boot/dts/aspeed-g6.dtsi @@ -106,18 +106,21 @@ reg = < 0 >; compatible = "jedec,spi-nor"; spi-max-frequency = <50000000>; + spi-rx-bus-width = <2>; status = "disabled"; }; flash@1 { reg = < 1 >; compatible = "jedec,spi-nor"; spi-max-frequency = <50000000>; + spi-rx-bus-width = <2>; status = "disabled"; }; flash@2 { reg = < 2 >; compatible = "jedec,spi-nor"; spi-max-frequency = <50000000>; + spi-rx-bus-width = <2>; status = "disabled"; }; }; @@ -133,12 +136,14 @@ reg = < 0 >; compatible = "jedec,spi-nor"; spi-max-frequency = <50000000>; + spi-rx-bus-width = <2>; status = "disabled"; }; flash@1 { reg = < 1 >; compatible = "jedec,spi-nor"; spi-max-frequency = <50000000>; + spi-rx-bus-width = <2>; status = "disabled"; }; }; @@ -154,18 +159,21 @@ reg = < 0 >; compatible = "jedec,spi-nor"; spi-max-frequency = <50000000>; + spi-rx-bus-width = <2>; status = "disabled"; }; flash@1 { reg = < 1 >; compatible = "jedec,spi-nor"; spi-max-frequency = <50000000>; + spi-rx-bus-width = <2>; status = "disabled"; }; flash@2 { reg = < 2 >; compatible = "jedec,spi-nor"; spi-max-frequency = <50000000>; + spi-rx-bus-width = <2>; status = "disabled"; }; }; -- cgit v1.2.3-59-g8ed1b From f3e5996218b6d81be5a503922793900dac3b1f99 Mon Sep 17 00:00:00 2001 From: Tao Ren Date: Mon, 9 May 2022 19:56:15 +0200 Subject: ARM: dts: aspeed-g4: Set spi-max-frequency for all flashes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Set "spi-max-frequency" to 50 MHz for all the flashes under the FMC controller to ensure the clock frequency is calculated correctly. Suggested-by: Cédric Le Goater Tested-by: Jae Hyun Yoo Signed-off-by: Tao Ren Signed-off-by: Cédric Le Goater Link: https://lore.kernel.org/r/20220509175616.1089346-11-clg@kaod.org Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-g4.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi index 1c6354cec9f2..530491ae5eb2 100644 --- a/arch/arm/boot/dts/aspeed-g4.dtsi +++ b/arch/arm/boot/dts/aspeed-g4.dtsi @@ -72,24 +72,28 @@ reg = < 1 >; compatible = "jedec,spi-nor"; spi-rx-bus-width = <2>; + spi-max-frequency = <50000000>; status = "disabled"; }; flash@2 { reg = < 2 >; compatible = "jedec,spi-nor"; spi-rx-bus-width = <2>; + spi-max-frequency = <50000000>; status = "disabled"; }; flash@3 { reg = < 3 >; compatible = "jedec,spi-nor"; spi-rx-bus-width = <2>; + spi-max-frequency = <50000000>; status = "disabled"; }; flash@4 { reg = < 4 >; compatible = "jedec,spi-nor"; spi-rx-bus-width = <2>; + spi-max-frequency = <50000000>; status = "disabled"; }; }; -- cgit v1.2.3-59-g8ed1b From c9cb67c3a650ef880ddbfc5906e2b9f51726dd5c Mon Sep 17 00:00:00 2001 From: Neal Liu Date: Wed, 18 May 2022 14:20:42 +0800 Subject: ARM: dts: aspeed: Add USB2.0 device controller node Add USB2.0 device controller(udc) node to device tree for AST2600. Signed-off-by: Neal Liu Link: https://lore.kernel.org/r/20220518062043.1075360-3-neal_liu@aspeedtech.com Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-g6.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed-g6.dtsi index 19c15e7fde60..7de9d1d5ae46 100644 --- a/arch/arm/boot/dts/aspeed-g6.dtsi +++ b/arch/arm/boot/dts/aspeed-g6.dtsi @@ -303,6 +303,16 @@ status = "disabled"; }; + udc: usb@1e6a2000 { + compatible = "aspeed,ast2600-udc"; + reg = <0x1e6a2000 0x300>; + interrupts = ; + clocks = <&syscon ASPEED_CLK_GATE_USBPORT2CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb2bd_default>; + status = "disabled"; + }; + apb { compatible = "simple-bus"; #address-cells = <1>; -- cgit v1.2.3-59-g8ed1b From ad0e053b5b97282f241b32f0896e6090efe0cacb Mon Sep 17 00:00:00 2001 From: Potin Lai Date: Mon, 9 May 2022 23:11:13 +0800 Subject: ARM: dts: aspeed: bletchley: enable ehci0 device node Enable ehci0 node for USB2 host feature Signed-off-by: Potin Lai Reviewed-by: Patrick Williams Reviewed-by: Joel Stanley Link: https://lore.kernel.org/r/20220509151118.4899-2-potin.lai.pt@gmail.com Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-facebook-bletchley.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-bletchley.dts b/arch/arm/boot/dts/aspeed-bmc-facebook-bletchley.dts index eaf1bc261ee3..258996f915a0 100644 --- a/arch/arm/boot/dts/aspeed-bmc-facebook-bletchley.dts +++ b/arch/arm/boot/dts/aspeed-bmc-facebook-bletchley.dts @@ -838,3 +838,7 @@ status = "okay"; /* TODO: Add Marvell 88X3310 */ }; + +&ehci0 { + status = "okay"; +}; -- cgit v1.2.3-59-g8ed1b From cc82dc2673e5ba6065732bbead74a9cb8e19e6c9 Mon Sep 17 00:00:00 2001 From: Potin Lai Date: Mon, 9 May 2022 23:11:14 +0800 Subject: ARM: dts: aspeed: bletchley: switch spi2 driver to aspeed-smc Due to DVT schematic has stable spi signal, switch back to aspeed-smc driver for improving performance. Signed-off-by: Potin Lai Reviewed-by: Patrick Williams Reviewed-by: Joel Stanley Link: https://lore.kernel.org/r/20220509151118.4899-3-potin.lai.pt@gmail.com Signed-off-by: Joel Stanley --- .../arm/boot/dts/aspeed-bmc-facebook-bletchley.dts | 33 +++++++++------------- 1 file changed, 13 insertions(+), 20 deletions(-) diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-bletchley.dts b/arch/arm/boot/dts/aspeed-bmc-facebook-bletchley.dts index 258996f915a0..c234264b174b 100644 --- a/arch/arm/boot/dts/aspeed-bmc-facebook-bletchley.dts +++ b/arch/arm/boot/dts/aspeed-bmc-facebook-bletchley.dts @@ -51,26 +51,6 @@ }; }; - spi2_gpio: spi2-gpio { - compatible = "spi-gpio"; - #address-cells = <1>; - #size-cells = <0>; - - gpio-sck = <&gpio0 ASPEED_GPIO(X, 3) GPIO_ACTIVE_HIGH>; - gpio-mosi = <&gpio0 ASPEED_GPIO(X, 4) GPIO_ACTIVE_HIGH>; - gpio-miso = <&gpio0 ASPEED_GPIO(X, 5) GPIO_ACTIVE_HIGH>; - num-chipselects = <1>; - cs-gpios = <&gpio0 ASPEED_GPIO(X, 0) GPIO_ACTIVE_LOW>; - - flash@0 { - reg = <0>; - compatible = "jedec,spi-nor"; - m25p,fast-read; - label = "pnor"; - spi-max-frequency = <100000000>; - }; - }; - switchphy: ethernet-phy@0 { // Fixed link }; @@ -242,6 +222,19 @@ }; }; +&spi2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi2_default>; + + flash@0 { + status = "okay"; + m25p,fast-read; + label = "pnor"; + spi-max-frequency = <50000000>; + }; +}; + &i2c0 { status = "okay"; ina230@45 { -- cgit v1.2.3-59-g8ed1b From 86ec3af52d91292a457247f3e48bacd5d587a9d6 Mon Sep 17 00:00:00 2001 From: Potin Lai Date: Mon, 9 May 2022 23:11:15 +0800 Subject: ARM: dts: aspeed: bletchley: Enable mdio0 bus Enable mdio0 bus based on DVT schematic. TODO: Add Marvell 88E6191 Switch Signed-off-by: Potin Lai Reviewed-by: Patrick Williams Reviewed-by: Joel Stanley Link: https://lore.kernel.org/r/20220509151118.4899-4-potin.lai.pt@gmail.com Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-facebook-bletchley.dts | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-bletchley.dts b/arch/arm/boot/dts/aspeed-bmc-facebook-bletchley.dts index c234264b174b..91f02a8c1fc2 100644 --- a/arch/arm/boot/dts/aspeed-bmc-facebook-bletchley.dts +++ b/arch/arm/boot/dts/aspeed-bmc-facebook-bletchley.dts @@ -827,6 +827,11 @@ &pinctrl_adc14_default &pinctrl_adc15_default>; }; +&mdio0 { + status = "okay"; + /* TODO: Add Marvell 88E6191X */ +}; + &mdio3 { status = "okay"; /* TODO: Add Marvell 88X3310 */ -- cgit v1.2.3-59-g8ed1b From 60280a214a41d896093daf162e7273338ebd396c Mon Sep 17 00:00:00 2001 From: Potin Lai Date: Mon, 9 May 2022 23:11:16 +0800 Subject: ARM: dts: aspeed: bletchley: update gpio0 line names Update GPIO line names based on DVT schematic Signed-off-by: Potin Lai Reviewed-by: Patrick Williams Reviewed-by: Joel Stanley Link: https://lore.kernel.org/r/20220509151118.4899-5-potin.lai.pt@gmail.com Signed-off-by: Joel Stanley --- .../arm/boot/dts/aspeed-bmc-facebook-bletchley.dts | 42 ++++++++++++++-------- 1 file changed, 27 insertions(+), 15 deletions(-) diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-bletchley.dts b/arch/arm/boot/dts/aspeed-bmc-facebook-bletchley.dts index 91f02a8c1fc2..56a2de702968 100644 --- a/arch/arm/boot/dts/aspeed-bmc-facebook-bletchley.dts +++ b/arch/arm/boot/dts/aspeed-bmc-facebook-bletchley.dts @@ -764,43 +764,55 @@ &gpio0 { gpio-line-names = /*A0-A7*/ "","","","","","","","", - /*B0-B7*/ "","","SEL_SPI2_MUX","SPI2_MUX1", - "SPI2_MUX2","SPI2_MUX3","","", + /*B0-B7*/ "FUSB302_SLED1_INT_N","FUSB302_SLED2_INT_N", + "SEL_SPI2_MUX","SPI2_MUX1", + "SPI2_MUX2","SPI2_MUX3", + "","FUSB302_SLED3_INT_N", /*C0-C7*/ "","","","","","","","", /*D0-D7*/ "","","","","","","","", /*E0-E7*/ "","","","","","","","", - /*F0-F7*/ "","","","","","","","", - /*G0-G7*/ "BSM_FRU_WP","SWITCH_FRU_MUX","","", + /*F0-F7*/ "BMC_SLED1_STCK","BMC_SLED2_STCK", + "BMC_SLED3_STCK","BMC_SLED4_STCK", + "BMC_SLED5_STCK","BMC_SLED6_STCK", + "","", + /*G0-G7*/ "BSM_FRU_WP","SWITCH_FRU_MUX","","FM_SOL_UART_CH_SEL", "PWRGD_P1V05_VDDCORE","PWRGD_P1V5_VDD","","", /*H0-H7*/ "presence-riser1","presence-riser2", "presence-sled1","presence-sled2", "presence-sled3","presence-sled4", "presence-sled5","presence-sled6", - /*I0-I7*/ "REV_ID0","","REV_ID1","REV_ID2", - "","BSM_FLASH_WP_STATUS","BMC_TPM_PRES","", + /*I0-I7*/ "REV_ID0","", + "REV_ID1","REV_ID2", + "","BSM_FLASH_WP_STATUS", + "BMC_TPM_PRES_N","FUSB302_SLED6_INT_N", /*J0-J7*/ "","","","","","","","", /*K0-K7*/ "","","","","","","","", /*L0-L7*/ "","","","","","BMC_RTC_INT","","", - /*M0-M7*/ "ALERT_SLED1","ALERT_SLED2", - "ALERT_SLED3","ALERT_SLED4", - "ALERT_SLED5","ALERT_SLED6", - "P12V_AUX_ALERT1","", - /*N0-N7*/ "","","","","","","","", + /*M0-M7*/ "ALERT_SLED1_N","ALERT_SLED2_N", + "ALERT_SLED3_N","ALERT_SLED4_N", + "ALERT_SLED5_N","ALERT_SLED6_N", + "","", + /*N0-N7*/ "LED_POSTCODE_0","LED_POSTCODE_1", + "LED_POSTCODE_2","LED_POSTCODE_3", + "LED_POSTCODE_4","LED_POSTCODE_5", + "LED_POSTCODE_5","LED_POSTCODE_7", /*O0-O7*/ "","","","", "","BOARD_ID0","BOARD_ID1","BOARD_ID2", /*P0-P7*/ "","","","","","","","BMC_HEARTBEAT", /*Q0-Q7*/ "","","","","","","","", /*R0-R7*/ "","","","","","","","", /*S0-S7*/ "","","","BAT_DETECT", - "BMC_BT_WP0","BMC_BT_WP1","","", + "BMC_BT_WP0_N","BMC_BT_WP1_N","","FUSB302_SLED4_INT_N", /*T0-T7*/ "","","","","","","","", /*U0-U7*/ "","","","","","","","", - /*V0-V7*/ "PWRGD_CNS_PSU","RST_BMC_MVL","","PSU_PRSNT", + /*V0-V7*/ "PWRGD_CNS_PSU","RST_BMC_MVL_N", + "P12V_AUX_ALERT1_N","PSU_PRSNT", "USB2_SEL0_A","USB2_SEL1_A", "USB2_SEL0_B","USB2_SEL1_B", - /*W0-W7*/ "RST_FRONT_IOEXP","","","","","","","", + /*W0-W7*/ "RST_FRONT_IOEXP_N","","","","","","","", /*X0-X7*/ "","","","","","","","", - /*Y0-Y7*/ "BMC_SELF_HW_RST","BSM_PRSNT","BSM_FLASH_LATCH","", + /*Y0-Y7*/ "BMC_SELF_HW_RST","BSM_PRSNT_N", + "BSM_FLASH_LATCH_N","FUSB302_SLED5_INT_N", "","","","", /*Z0-Z7*/ "","","","","","","",""; }; -- cgit v1.2.3-59-g8ed1b From 9495c6d570600e275253036aa993735db8bd2451 Mon Sep 17 00:00:00 2001 From: Potin Lai Date: Mon, 9 May 2022 23:11:17 +0800 Subject: ARM: dts: aspeed: bletchley: add pca9536 node on each sled Add an ioexp node on each sled baseed on DVT schematic, address at 0x41. P0: SLEDX_SWD_MUX P1: SLEDX_XRES_SWD_N P2: SLEDX_CLKREQ_N P3: SLEDX_PCIE_PWR_EN Signed-off-by: Potin Lai Reviewed-by: Patrick Williams Reviewed-by: Joel Stanley Link: https://lore.kernel.org/r/20220509151118.4899-6-potin.lai.pt@gmail.com Signed-off-by: Joel Stanley --- .../arm/boot/dts/aspeed-bmc-facebook-bletchley.dts | 66 ++++++++++++++++++++++ 1 file changed, 66 insertions(+) diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-bletchley.dts b/arch/arm/boot/dts/aspeed-bmc-facebook-bletchley.dts index 56a2de702968..3a5b9fbb7c99 100644 --- a/arch/arm/boot/dts/aspeed-bmc-facebook-bletchley.dts +++ b/arch/arm/boot/dts/aspeed-bmc-facebook-bletchley.dts @@ -253,6 +253,17 @@ reg = <0x4f>; }; + sled1_ioexp41: pca9536@41 { + compatible = "nxp,pca9536"; + reg = <0x41>; + gpio-controller; + #gpio-cells = <2>; + + gpio-line-names = + "SLED1_SWD_MUX", "SLED1_XRES_SWD_N", + "SLED1_CLKREQ_N", "SLED1_PCIE_PWR_EN"; + }; + sled1_ioexp: pca9539@76 { compatible = "nxp,pca9539"; reg = <0x76>; @@ -323,6 +334,17 @@ reg = <0x4f>; }; + sled2_ioexp41: pca9536@41 { + compatible = "nxp,pca9536"; + reg = <0x41>; + gpio-controller; + #gpio-cells = <2>; + + gpio-line-names = + "SLED2_SWD_MUX", "SLED2_XRES_SWD_N", + "SLED2_CLKREQ_N", "SLED2_PCIE_PWR_EN"; + }; + sled2_ioexp: pca9539@76 { compatible = "nxp,pca9539"; reg = <0x76>; @@ -393,6 +415,17 @@ reg = <0x4f>; }; + sled3_ioexp41: pca9536@41 { + compatible = "nxp,pca9536"; + reg = <0x41>; + gpio-controller; + #gpio-cells = <2>; + + gpio-line-names = + "SLED3_SWD_MUX", "SLED3_XRES_SWD_N", + "SLED3_CLKREQ_N", "SLED3_PCIE_PWR_EN"; + }; + sled3_ioexp: pca9539@76 { compatible = "nxp,pca9539"; reg = <0x76>; @@ -463,6 +496,17 @@ reg = <0x4f>; }; + sled4_ioexp41: pca9536@41 { + compatible = "nxp,pca9536"; + reg = <0x41>; + gpio-controller; + #gpio-cells = <2>; + + gpio-line-names = + "SLED4_SWD_MUX", "SLED4_XRES_SWD_N", + "SLED4_CLKREQ_N", "SLED4_PCIE_PWR_EN"; + }; + sled4_ioexp: pca9539@76 { compatible = "nxp,pca9539"; reg = <0x76>; @@ -533,6 +577,17 @@ reg = <0x4f>; }; + sled5_ioexp41: pca9536@41 { + compatible = "nxp,pca9536"; + reg = <0x41>; + gpio-controller; + #gpio-cells = <2>; + + gpio-line-names = + "SLED5_SWD_MUX", "SLED5_XRES_SWD_N", + "SLED5_CLKREQ_N", "SLED5_PCIE_PWR_EN"; + }; + sled5_ioexp: pca9539@76 { compatible = "nxp,pca9539"; reg = <0x76>; @@ -603,6 +658,17 @@ reg = <0x4f>; }; + sled6_ioexp41: pca9536@41 { + compatible = "nxp,pca9536"; + reg = <0x41>; + gpio-controller; + #gpio-cells = <2>; + + gpio-line-names = + "SLED6_SWD_MUX", "SLED6_XRES_SWD_N", + "SLED6_CLKREQ_N", "SLED6_PCIE_PWR_EN"; + }; + sled6_ioexp: pca9539@76 { compatible = "nxp,pca9539"; reg = <0x76>; -- cgit v1.2.3-59-g8ed1b From 8c9e3743877812b7721a506fac056e4a71e11b66 Mon Sep 17 00:00:00 2001 From: Potin Lai Date: Mon, 9 May 2022 23:11:18 +0800 Subject: ARM: dts: aspeed: bletchley: add eeprom node on each sled Add eeprom (24c26) on each sled for storing sled fru information. Signed-off-by: Potin Lai Reviewed-by: Patrick Williams Reviewed-by: Joel Stanley Link: https://lore.kernel.org/r/20220509151118.4899-7-potin.lai.pt@gmail.com Signed-off-by: Joel Stanley --- .../arm/boot/dts/aspeed-bmc-facebook-bletchley.dts | 30 ++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-bletchley.dts b/arch/arm/boot/dts/aspeed-bmc-facebook-bletchley.dts index 3a5b9fbb7c99..3e962fe4d5f3 100644 --- a/arch/arm/boot/dts/aspeed-bmc-facebook-bletchley.dts +++ b/arch/arm/boot/dts/aspeed-bmc-facebook-bletchley.dts @@ -314,6 +314,11 @@ op-sink-microwatt = <10000000>; }; }; + + eeprom@54 { + compatible = "atmel,24c64"; + reg = <0x54>; + }; }; &i2c1 { @@ -395,6 +400,11 @@ op-sink-microwatt = <10000000>; }; }; + + eeprom@54 { + compatible = "atmel,24c64"; + reg = <0x54>; + }; }; &i2c2 { @@ -476,6 +486,11 @@ op-sink-microwatt = <10000000>; }; }; + + eeprom@54 { + compatible = "atmel,24c64"; + reg = <0x54>; + }; }; &i2c3 { @@ -557,6 +572,11 @@ op-sink-microwatt = <10000000>; }; }; + + eeprom@54 { + compatible = "atmel,24c64"; + reg = <0x54>; + }; }; &i2c4 { @@ -638,6 +658,11 @@ op-sink-microwatt = <10000000>; }; }; + + eeprom@54 { + compatible = "atmel,24c64"; + reg = <0x54>; + }; }; &i2c5 { @@ -719,6 +744,11 @@ op-sink-microwatt = <10000000>; }; }; + + eeprom@54 { + compatible = "atmel,24c64"; + reg = <0x54>; + }; }; &i2c6 { -- cgit v1.2.3-59-g8ed1b From 244839d0fe6f9d1317ae4f415447e86baf943e9c Mon Sep 17 00:00:00 2001 From: Potin Lai Date: Mon, 18 Apr 2022 17:48:27 +0800 Subject: ARM: dts: aspeed: bletchley: add sample averaging for ADM1278 set number of sample averaging to 128 for both PWR_AVG and VI_AVG Signed-off-by: Potin Lai Reviewed-by: Patrick Williams Link: https://lore.kernel.org/r/20220418094827.6185-1-potin.lai@quantatw.com Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-facebook-bletchley.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-bletchley.dts b/arch/arm/boot/dts/aspeed-bmc-facebook-bletchley.dts index 3e962fe4d5f3..41d2b1535d9a 100644 --- a/arch/arm/boot/dts/aspeed-bmc-facebook-bletchley.dts +++ b/arch/arm/boot/dts/aspeed-bmc-facebook-bletchley.dts @@ -821,6 +821,8 @@ compatible = "adi,adm1278"; reg = <0x11>; shunt-resistor-micro-ohms = <300>; + adi,volt-curr-sample-average = <128>; + adi,power-sample-average = <128>; }; tmp421@4c { -- cgit v1.2.3-59-g8ed1b From 7b46aa7c008d2becd5df46c174d8cb4239e24659 Mon Sep 17 00:00:00 2001 From: Graeme Gregory Date: Fri, 25 Mar 2022 12:02:47 -0700 Subject: ARM: dts: aspeed: Add Nuvia DC-SCM BMC Add initial version of device tree for Nuvia DC-SCM BMC which is equipped with Aspeed AST2600 BMC SoC. Signed-off-by: Graeme Gregory Signed-off-by: Jae Hyun Yoo Link: https://lore.kernel.org/r/20220325190247.468079-1-quic_jaehyoo@quicinc.com Signed-off-by: Joel Stanley --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/aspeed-bmc-nuvia-dc-scm.dts | 190 ++++++++++++++++++++++++++ 2 files changed, 191 insertions(+) create mode 100644 arch/arm/boot/dts/aspeed-bmc-nuvia-dc-scm.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 7c16f8a2b738..e63cd6ed0faa 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1546,6 +1546,7 @@ dtb-$(CONFIG_ARCH_ASPEED) += \ aspeed-bmc-lenovo-hr630.dtb \ aspeed-bmc-lenovo-hr855xg2.dtb \ aspeed-bmc-microsoft-olympus.dtb \ + aspeed-bmc-nuvia-dc-scm.dtb \ aspeed-bmc-opp-lanyang.dtb \ aspeed-bmc-opp-mihawk.dtb \ aspeed-bmc-opp-mowgli.dtb \ diff --git a/arch/arm/boot/dts/aspeed-bmc-nuvia-dc-scm.dts b/arch/arm/boot/dts/aspeed-bmc-nuvia-dc-scm.dts new file mode 100644 index 000000000000..f4a97cfb0f23 --- /dev/null +++ b/arch/arm/boot/dts/aspeed-bmc-nuvia-dc-scm.dts @@ -0,0 +1,190 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +// Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. + +/dts-v1/; + +#include "aspeed-g6.dtsi" + +/ { + model = "Nuvia DC-SCM BMC"; + compatible = "nuvia,dc-scm-bmc", "aspeed,ast2600"; + + aliases { + serial4 = &uart5; + }; + + chosen { + stdout-path = &uart5; + bootargs = "console=ttyS4,115200n8"; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x40000000>; + }; +}; + +&mdio3 { + status = "okay"; + + ethphy3: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; +}; + +&mac2 { + status = "okay"; + + /* Bootloader sets up the MAC to insert delay */ + phy-mode = "rgmii"; + phy-handle = <ðphy3>; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgmii3_default>; +}; + +&mac3 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rmii4_default>; + + use-ncsi; +}; + +&rtc { + status = "okay"; +}; + +&fmc { + status = "okay"; + + flash@0 { + status = "okay"; + m25p,fast-read; + label = "bmc"; + spi-max-frequency = <133000000>; +#include "openbmc-flash-layout-64.dtsi" + }; + + flash@1 { + status = "okay"; + m25p,fast-read; + label = "alt-bmc"; + spi-max-frequency = <133000000>; +#include "openbmc-flash-layout-64-alt.dtsi" + }; +}; + +&spi1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi1_default>; + + flash@0 { + status = "okay"; + m25p,fast-read; + label = "bios"; + spi-max-frequency = <133000000>; + }; +}; + +&gpio0 { + gpio-line-names = + /*A0-A7*/ "","","","","","","","", + /*B0-B7*/ "BMC_FLASH_MUX_SEL","","","","","","","", + /*C0-C7*/ "","","","","","","","", + /*D0-D7*/ "","","","","","","","", + /*E0-E7*/ "","","","","","","","", + /*F0-F7*/ "","","","","","","","", + /*G0-G7*/ "","","","","","","","", + /*H0-H7*/ "","","","","","","","", + /*I0-I7*/ "","","","","","","","", + /*J0-J7*/ "","","","","","","","", + /*K0-K7*/ "","","","","","","","", + /*L0-L7*/ "","","","","","","","", + /*M0-M7*/ "","","","","","","","", + /*N0-N7*/ "BMC_FWSPI_RST_N","","GPIO_1_BMC_3V3","","","","","", + /*O0-O7*/ "JTAG_MUX_A","JTAG_MUX_B","","","","","","", + /*P0-P7*/ "","","","","","","","", + /*Q0-Q7*/ "","","","","","","","", + /*R0-R7*/ "","","","","","","","", + /*S0-S7*/ "","","","","","","","", + /*T0-T7*/ "","","","","","","","", + /*U0-U7*/ "","","","","","","","", + /*V0-V7*/ "","","","SCMFPGA_SPARE_GPIO1_3V3", + "SCMFPGA_SPARE_GPIO2_3V3","SCMFPGA_SPARE_GPIO3_3V3", + "SCMFPGA_SPARE_GPIO4_3V3","SCMFPGA_SPARE_GPIO5_3V3", + /*W0-W7*/ "","","","","","","","", + /*X0-X7*/ "","","","","","","","", + /*Y0-Y7*/ "","","","","","","","", + /*Z0-Z7*/ "","","","","","","","", + /*AA0-AA7*/ "","","","","","","","", + /*AB0-AB7*/ "","","","","","","","", + /*AC0-AC7*/ "","","","","","","",""; +}; + +&gpio1 { + gpio-line-names = + /*A0-A7*/ "GPI_1_BMC_1V8","","","","","", + "SCMFPGA_SPARE_GPIO1_1V8","SCMFPGA_SPARE_GPIO2_1V8", + /*B0-B7*/ "SCMFPGA_SPARE_GPIO3_1V8","SCMFPGA_SPARE_GPIO4_1V8", + "SCMFPGA_SPARE_GPIO5_1V8","","","","","", + /*C0-C7*/ "","","","","","","","", + /*D0-D7*/ "","BMC_SPI1_RST_N","BIOS_FLASH_MUX_SEL","", + "","TPM2_PIRQ_N","TPM2_RST_N","", + /*E0-E7*/ "","","","","","","",""; +}; + +&i2c2 { + status = "okay"; +}; + +&i2c4 { + status = "okay"; +}; + +&i2c5 { + status = "okay"; +}; + +&i2c6 { + status = "okay"; +}; + +&i2c7 { + status = "okay"; +}; + +&i2c8 { + status = "okay"; +}; + +&i2c9 { + status = "okay"; +}; + +&i2c10 { + status = "okay"; +}; + +&i2c12 { + status = "okay"; +}; + +&i2c13 { + status = "okay"; +}; + +&i2c14 { + status = "okay"; +}; + +&i2c15 { + status = "okay"; +}; + +&vhub { + status = "okay"; +}; -- cgit v1.2.3-59-g8ed1b From f6b67950047bc34f08c33132f5614525459fbe8e Mon Sep 17 00:00:00 2001 From: Brandon Wyman Date: Thu, 21 Apr 2022 21:36:38 +0000 Subject: ARM: dts: aspeed: everest, rainier: Add power-ffs-sync-history GPIO The IBM Everest and Rainier systems have a GPIO line that goes to the power supplies. It has a dual function: 1) Fans Full Speed, and 2) Sync input history. Signed-off-by: Brandon Wyman Link: https://lore.kernel.org/r/20220421213638.1151193-1-bjwyman@gmail.com Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts | 2 +- arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts b/arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts index 578f9e2fc7ed..382da7934eaa 100644 --- a/arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts +++ b/arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts @@ -283,7 +283,7 @@ /*P0-P7*/ "","","","","led-pcieslot-power","","","", /*Q0-Q7*/ "","","regulator-standby-faulted","","","","","", /*R0-R7*/ "bmc-tpm-reset","power-chassis-control","power-chassis-good","","","I2C_FLASH_MICRO_N","","", - /*S0-S7*/ "","","","","","","","", + /*S0-S7*/ "","","","","power-ffs-sync-history","","","", /*T0-T7*/ "","","","","","","","", /*U0-U7*/ "","","","","","","","", /*V0-V7*/ "","BMC_3RESTART_ATTEMPT_P","","","","","","", diff --git a/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts b/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts index 528b49e2c0f8..7213434695bf 100644 --- a/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts +++ b/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts @@ -265,7 +265,7 @@ /*Q0-Q7*/ "cfam-reset","","regulator-standby-faulted","","","","","", /*R0-R7*/ "bmc-tpm-reset","power-chassis-control","power-chassis-good","","","","","", /*S0-S7*/ "presence-ps0","presence-ps1","presence-ps2","presence-ps3", - "","","","", + "power-ffs-sync-history","","","", /*T0-T7*/ "","","","","","","","", /*U0-U7*/ "","","","","","","","", /*V0-V7*/ "","","","","","","","", -- cgit v1.2.3-59-g8ed1b From 08daf2c89186452b4986b8a5f014f6478fe7e769 Mon Sep 17 00:00:00 2001 From: Howard Chiu Date: Tue, 29 Mar 2022 03:24:03 +0000 Subject: ARM: dts: aspeed: ast2600-evb: Enable video engine Enable video engine and reserve memory for it. Signed-off-by: Howard Chiu Link: https://lore.kernel.org/r/SG2PR06MB23159B914BF7EF937FEDD2B5E61E9@SG2PR06MB2315.apcprd06.prod.outlook.com Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-ast2600-evb.dts | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm/boot/dts/aspeed-ast2600-evb.dts b/arch/arm/boot/dts/aspeed-ast2600-evb.dts index 788448cdd6b3..6fcd9406987b 100644 --- a/arch/arm/boot/dts/aspeed-ast2600-evb.dts +++ b/arch/arm/boot/dts/aspeed-ast2600-evb.dts @@ -23,6 +23,19 @@ reg = <0x80000000 0x80000000>; }; + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + video_engine_memory: video { + size = <0x04000000>; + alignment = <0x01000000>; + compatible = "shared-dma-pool"; + reusable; + }; + }; + vcc_sdhci0: regulator-vcc-sdhci0 { compatible = "regulator-fixed"; regulator-name = "SDHCI0 Vcc"; @@ -300,3 +313,8 @@ vqmmc-supply = <&vccq_sdhci1>; clk-phase-sd-hs = <7>, <200>; }; + +&video { + status = "okay"; + memory-region = <&video_engine_memory>; +}; -- cgit v1.2.3-59-g8ed1b From 0ef77237c5243aa620528daeaad0ba92094b5720 Mon Sep 17 00:00:00 2001 From: Howard Chiu Date: Tue, 29 Mar 2022 03:24:10 +0000 Subject: ARM: dts: aspeed: ast2600-evb: Enable virtual hub Enable Aspeed VHub for HID emulation Signed-off-by: Howard Chiu Link: https://lore.kernel.org/r/SG2PR06MB23155E8A6193118544A7DBF3E61E9@SG2PR06MB2315.apcprd06.prod.outlook.com Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-ast2600-evb.dts | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/aspeed-ast2600-evb.dts b/arch/arm/boot/dts/aspeed-ast2600-evb.dts index 6fcd9406987b..55b1d3a81700 100644 --- a/arch/arm/boot/dts/aspeed-ast2600-evb.dts +++ b/arch/arm/boot/dts/aspeed-ast2600-evb.dts @@ -314,6 +314,11 @@ clk-phase-sd-hs = <7>, <200>; }; +&vhub { + status = "okay"; + pinctrl-names = "default"; +}; + &video { status = "okay"; memory-region = <&video_engine_memory>; -- cgit v1.2.3-59-g8ed1b From 4fa40bfa255df35f8ea5e4e03d05a8e8b221a117 Mon Sep 17 00:00:00 2001 From: Joel Stanley Date: Wed, 2 Mar 2022 10:49:26 +0800 Subject: ARM: dts: aspeed: Add GFX node to AST2600 The GFX device is present in the AST2600 SoC. Signed-off-by: Joel Stanley Signed-off-by: Tommy Haung Reviewed-by: Joel Stanley Link: https://lore.kernel.org/r/20220302024930.18758-2-tommy_huang@aspeedtech.com Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-g6.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed-g6.dtsi index 7de9d1d5ae46..b071e2c00455 100644 --- a/arch/arm/boot/dts/aspeed-g6.dtsi +++ b/arch/arm/boot/dts/aspeed-g6.dtsi @@ -366,6 +366,17 @@ quality = <100>; }; + gfx: display@1e6e6000 { + compatible = "aspeed,ast2600-gfx", "syscon"; + reg = <0x1e6e6000 0x1000>; + reg-io-width = <4>; + clocks = <&syscon ASPEED_CLK_GATE_D1CLK>; + resets = <&syscon ASPEED_RESET_GRAPHICS>; + syscon = <&syscon>; + status = "disabled"; + interrupts = ; + }; + xdma: xdma@1e6e7000 { compatible = "aspeed,ast2600-xdma"; reg = <0x1e6e7000 0x100>; -- cgit v1.2.3-59-g8ed1b From 8dc7aa0a7246ad0f718d91d09b4d48460508627b Mon Sep 17 00:00:00 2001 From: Joel Stanley Date: Wed, 2 Mar 2022 10:49:27 +0800 Subject: ARM: dts: aspeed: ast2600-evb: Enable GFX device Enable the GFX device with a framebuffer memory region. Signed-off-by: Joel Stanley Signed-off-by: Tommy Haung Reviewed-by: Joel Stanley Link: https://lore.kernel.org/r/20220302024930.18758-3-tommy_huang@aspeedtech.com Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-ast2600-evb.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm/boot/dts/aspeed-ast2600-evb.dts b/arch/arm/boot/dts/aspeed-ast2600-evb.dts index 55b1d3a81700..5a6063bd4508 100644 --- a/arch/arm/boot/dts/aspeed-ast2600-evb.dts +++ b/arch/arm/boot/dts/aspeed-ast2600-evb.dts @@ -34,6 +34,13 @@ compatible = "shared-dma-pool"; reusable; }; + + gfx_memory: framebuffer { + size = <0x01000000>; + alignment = <0x01000000>; + compatible = "shared-dma-pool"; + reusable; + }; }; vcc_sdhci0: regulator-vcc-sdhci0 { @@ -323,3 +330,8 @@ status = "okay"; memory-region = <&video_engine_memory>; }; + +&gfx { + status = "okay"; + memory-region = <&gfx_memory>; +}; -- cgit v1.2.3-59-g8ed1b