From 7f3e2919c9fe0a86292c012f72c8b5d14f2c1a8a Mon Sep 17 00:00:00 2001 From: Bhawanpreet Lakha Date: Thu, 21 May 2020 15:35:27 -0400 Subject: drm/amd/display: Remove Unused Registers Signed-off-by: Bhawanpreet Lakha Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c | 17 ----------------- drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h | 12 ------------ .../gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h | 3 +-- 3 files changed, 1 insertion(+), 31 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c index 1b1ae9ce2799..3c6ecfe141bb 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c @@ -717,22 +717,5 @@ static void dsc_write_to_registers(struct display_stream_compressor *dsc, const RANGE_MAX_QP14, reg_vals->pps.rc_range_params[14].range_max_qp, RANGE_BPG_OFFSET14, reg_vals->pps.rc_range_params[14].range_bpg_offset); - if (IS_FPGA_MAXIMUS_DC(dsc20->base.ctx->dce_environment)) { - /* It's safe to do this as long as debug bus is not being used in DAL Diag environment. - * - * This is because DSCC_PPS_CONFIG4.INITIAL_DEC_DELAY is a read-only register field (because it's a decoder - * value not required by DSC encoder). However, since decoding fails when this value is missing from PPS, it's - * required to communicate this value to the PPS header. When testing on FPGA, the values for PPS header are - * being read from Diag register dump. The register below is used in place of a scratch register to make - * 'initial_dec_delay' available. - */ - - temp_int = reg_vals->pps.initial_dec_delay; - REG_SET_4(DSCC_TEST_DEBUG_BUS_ROTATE, 0, - DSCC_TEST_DEBUG_BUS0_ROTATE, temp_int & 0x1f, - DSCC_TEST_DEBUG_BUS1_ROTATE, temp_int >> 5 & 0x1f, - DSCC_TEST_DEBUG_BUS2_ROTATE, temp_int >> 10 & 0x1f, - DSCC_TEST_DEBUG_BUS3_ROTATE, temp_int >> 15 & 0x1); - } } diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h index 9855a7ed0387..667640c4b288 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h @@ -78,7 +78,6 @@ SRI(DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL, DSCC, id),\ SRI(DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL, DSCC, id),\ SRI(DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL, DSCC, id),\ - SRI(DSCC_TEST_DEBUG_BUS_ROTATE, DSCC, id),\ SRI(DSCCIF_CONFIG0, DSCCIF, id),\ SRI(DSCCIF_CONFIG1, DSCCIF, id),\ SRI(DSCRM_DSC_FORWARD_CONFIG, DSCRM, id) @@ -95,8 +94,6 @@ DSC_SF(DSC_TOP0_DSC_TOP_CONTROL, DSC_CLOCK_EN, mask_sh), \ DSC_SF(DSC_TOP0_DSC_TOP_CONTROL, DSC_DISPCLK_R_GATE_DIS, mask_sh), \ DSC_SF(DSC_TOP0_DSC_TOP_CONTROL, DSC_DSCCLK_R_GATE_DIS, mask_sh), \ - DSC_SF(DSC_TOP0_DSC_DEBUG_CONTROL, DSC_DBG_EN, mask_sh), \ - DSC_SF(DSC_TOP0_DSC_DEBUG_CONTROL, DSC_TEST_CLOCK_MUX_SEL, mask_sh), \ DSC_SF(DSCC0_DSCC_CONFIG0, ICH_RESET_AT_END_OF_LINE, mask_sh), \ DSC_SF(DSCC0_DSCC_CONFIG0, NUMBER_OF_SLICES_PER_LINE, mask_sh), \ DSC_SF(DSCC0_DSCC_CONFIG0, ALTERNATE_ICH_ENCODING_EN, mask_sh), \ @@ -249,10 +246,6 @@ DSC_SF(DSCC0_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL, DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL, mask_sh), \ DSC_SF(DSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL, DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL, mask_sh), \ DSC_SF(DSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL, DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL, mask_sh), \ - DSC_SF(DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE, DSCC_TEST_DEBUG_BUS0_ROTATE, mask_sh), \ - DSC_SF(DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE, DSCC_TEST_DEBUG_BUS1_ROTATE, mask_sh), \ - DSC_SF(DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE, DSCC_TEST_DEBUG_BUS2_ROTATE, mask_sh), \ - DSC_SF(DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE, DSCC_TEST_DEBUG_BUS3_ROTATE, mask_sh), \ DSC_SF(DSCCIF0_DSCCIF_CONFIG0, INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN, mask_sh), \ DSC_SF(DSCCIF0_DSCCIF_CONFIG0, INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN, mask_sh), \ DSC_SF(DSCCIF0_DSCCIF_CONFIG0, INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS, mask_sh), \ @@ -427,10 +420,6 @@ type DSCC_UPDATE_PENDING_STATUS; \ type DSCC_UPDATE_TAKEN_STATUS; \ type DSCC_UPDATE_TAKEN_ACK; \ - type DSCC_TEST_DEBUG_BUS0_ROTATE; \ - type DSCC_TEST_DEBUG_BUS1_ROTATE; \ - type DSCC_TEST_DEBUG_BUS2_ROTATE; \ - type DSCC_TEST_DEBUG_BUS3_ROTATE; \ type DSCC_RATE_BUFFER0_FULLNESS_LEVEL; \ type DSCC_RATE_BUFFER1_FULLNESS_LEVEL; \ type DSCC_RATE_BUFFER2_FULLNESS_LEVEL; \ @@ -503,7 +492,6 @@ struct dcn20_dsc_registers { uint32_t DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL; uint32_t DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL; uint32_t DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL; - uint32_t DSCC_TEST_DEBUG_BUS_ROTATE; uint32_t DSCCIF_CONFIG0; uint32_t DSCCIF_CONFIG1; uint32_t DSCRM_DSC_FORWARD_CONFIG; diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h index a6c8493001a6..db09f40075c2 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h @@ -147,8 +147,7 @@ LE_SF(DPCSTX0_DPCSTX_TX_CNTL, DPCS_TX_DATA_SWAP, mask_sh),\ LE_SF(DPCSTX0_DPCSTX_TX_CNTL, DPCS_TX_DATA_ORDER_INVERT, mask_sh),\ LE_SF(DPCSTX0_DPCSTX_TX_CNTL, DPCS_TX_FIFO_EN, mask_sh),\ - LE_SF(DPCSTX0_DPCSTX_TX_CNTL, DPCS_TX_FIFO_RD_START_DELAY, mask_sh),\ - LE_SF(DPCSTX0_DPCSTX_DEBUG_CONFIG, DPCS_DBG_CBUS_DIS, mask_sh) + LE_SF(DPCSTX0_DPCSTX_TX_CNTL, DPCS_TX_FIFO_RD_START_DELAY, mask_sh) #define DPCS_DCN2_MASK_SH_LIST(mask_sh)\ DPCS_MASK_SH_LIST(mask_sh),\ -- cgit v1.2.3-59-g8ed1b