From 84bcd469592eadbf731c07ed7f6654dc71bbe059 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Mon, 11 May 2015 22:01:55 +0200 Subject: drm/radeon/tn/si: enable/disable vce cg when encoding v2 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Some of the vce clocks are automatic, others need to be manually enabled. For ease, just disable cg when vce is active. v2: rebased, call vce_v1_0_enable_mgcg directly Signed-off-by: Alex Deucher Signed-off-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/radeon/si_dpm.c | 9 ++++++++- drivers/gpu/drm/radeon/trinity_dpm.c | 9 ++++++++- 2 files changed, 16 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/radeon/si_dpm.c b/drivers/gpu/drm/radeon/si_dpm.c index 69cd4ca91685..1dbdf3230dae 100644 --- a/drivers/gpu/drm/radeon/si_dpm.c +++ b/drivers/gpu/drm/radeon/si_dpm.c @@ -1740,6 +1740,7 @@ struct ni_power_info *ni_get_pi(struct radeon_device *rdev); struct ni_ps *ni_get_ps(struct radeon_ps *rps); extern int si_mc_load_microcode(struct radeon_device *rdev); +extern void vce_v1_0_enable_mgcg(struct radeon_device *rdev, bool enable); static int si_populate_voltage_value(struct radeon_device *rdev, const struct atom_voltage_table *table, @@ -5932,8 +5933,14 @@ static void si_set_vce_clock(struct radeon_device *rdev, struct radeon_ps *old_rps) { if ((old_rps->evclk != new_rps->evclk) || - (old_rps->ecclk != new_rps->ecclk)) + (old_rps->ecclk != new_rps->ecclk)) { + /* turn the clocks on when encoding, off otherwise */ + if (new_rps->evclk || new_rps->ecclk) + vce_v1_0_enable_mgcg(rdev, false); + else + vce_v1_0_enable_mgcg(rdev, true); radeon_set_vce_clocks(rdev, new_rps->evclk, new_rps->ecclk); + } } void si_dpm_setup_asic(struct radeon_device *rdev) diff --git a/drivers/gpu/drm/radeon/trinity_dpm.c b/drivers/gpu/drm/radeon/trinity_dpm.c index e0d07802a906..d34bfcdab9be 100644 --- a/drivers/gpu/drm/radeon/trinity_dpm.c +++ b/drivers/gpu/drm/radeon/trinity_dpm.c @@ -336,6 +336,7 @@ static const u32 trinity_override_mgpg_sequences[] = 0x00000204, 0x00000000, }; +extern void vce_v1_0_enable_mgcg(struct radeon_device *rdev, bool enable); static void trinity_program_clk_gating_hw_sequence(struct radeon_device *rdev, const u32 *seq, u32 count); static void trinity_override_dynamic_mg_powergating(struct radeon_device *rdev); @@ -990,8 +991,14 @@ static void trinity_set_vce_clock(struct radeon_device *rdev, struct radeon_ps *old_rps) { if ((old_rps->evclk != new_rps->evclk) || - (old_rps->ecclk != new_rps->ecclk)) + (old_rps->ecclk != new_rps->ecclk)) { + /* turn the clocks on when encoding, off otherwise */ + if (new_rps->evclk || new_rps->ecclk) + vce_v1_0_enable_mgcg(rdev, false); + else + vce_v1_0_enable_mgcg(rdev, true); radeon_set_vce_clocks(rdev, new_rps->evclk, new_rps->ecclk); + } } static void trinity_program_ttt(struct radeon_device *rdev) -- cgit v1.2.3-59-g8ed1b