From 8e8e9a0b7df0194e95bb1d657f9edbdc6363f082 Mon Sep 17 00:00:00 2001 From: Alexander Duyck Date: Mon, 2 Nov 2015 17:09:35 -0800 Subject: ixgbe: Fix SR-IOV VLAN pool configuration The code for checking the PF bit in ixgbe_set_vf_vlan_msg was using the wrong offset and as a result it was pulling the VLAN off of the PF even if there were VFs numbered greater than 40 that still had the VLAN enabled. Signed-off-by: Alexander Duyck Tested-by: Phil Schmitt Signed-off-by: Jeff Kirsher --- drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c index 31de6cf7adb0..61a054ace56d 100644 --- a/drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c +++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c @@ -887,10 +887,10 @@ static int ixgbe_set_vf_vlan_msg(struct ixgbe_adapter *adapter, bits = IXGBE_READ_REG(hw, IXGBE_VLVFB(reg_ndx * 2)); bits &= ~(1 << VMDQ_P(0)); bits |= IXGBE_READ_REG(hw, - IXGBE_VLVFB(reg_ndx * 2) + 1); + IXGBE_VLVFB(reg_ndx * 2 + 1)); } else { bits = IXGBE_READ_REG(hw, - IXGBE_VLVFB(reg_ndx * 2) + 1); + IXGBE_VLVFB(reg_ndx * 2 + 1)); bits &= ~(1 << (VMDQ_P(0) - 32)); bits |= IXGBE_READ_REG(hw, IXGBE_VLVFB(reg_ndx * 2)); } -- cgit v1.2.3-59-g8ed1b