From 15a1c2d80ae192261b5e4759d8d987ab30f6c3f4 Mon Sep 17 00:00:00 2001 From: Sumit Gupta Date: Tue, 5 Apr 2022 18:31:16 +0530 Subject: dt-bindings: Document Tegra CCPLEX Cluster The Tegra CPU COMPLEX CLUSTER area contains memory-mapped registers that initiate CPU frequency/voltage transitions. Signed-off-by: Sumit Gupta Reviewed-by: Rob Herring Signed-off-by: Viresh Kumar --- .../arm/tegra/nvidia,tegra-ccplex-cluster.yaml | 52 ++++++++++++++++++++++ 1 file changed, 52 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/tegra/nvidia,tegra-ccplex-cluster.yaml diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra-ccplex-cluster.yaml b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra-ccplex-cluster.yaml new file mode 100644 index 000000000000..8c6543b5c0dc --- /dev/null +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra-ccplex-cluster.yaml @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/arm/tegra/nvidia,tegra-ccplex-cluster.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: NVIDIA Tegra CPU COMPLEX CLUSTER area device tree bindings + +maintainers: + - Sumit Gupta + - Mikko Perttunen + - Jon Hunter + - Thierry Reding + +description: |+ + The Tegra CPU COMPLEX CLUSTER area contains memory-mapped + registers that initiate CPU frequency/voltage transitions. + +properties: + $nodename: + pattern: "ccplex@([0-9a-f]+)$" + + compatible: + enum: + - nvidia,tegra186-ccplex-cluster + - nvidia,tegra234-ccplex-cluster + + reg: + maxItems: 1 + + nvidia,bpmp: + $ref: '/schemas/types.yaml#/definitions/phandle' + description: | + Specifies the BPMP node that needs to be queried to get + operating point data for all CPUs. + +additionalProperties: false + +required: + - compatible + - reg + - nvidia,bpmp + - status + +examples: + - | + ccplex@e000000 { + compatible = "nvidia,tegra234-ccplex-cluster"; + reg = <0x0e000000 0x5ffff>; + nvidia,bpmp = <&bpmp>; + status = "okay"; + }; -- cgit v1.2.3-59-g8ed1b From 0839ed1fd7aca2cc67fbe19b8c6394e8a6e58453 Mon Sep 17 00:00:00 2001 From: Sumit Gupta Date: Tue, 5 Apr 2022 18:31:17 +0530 Subject: cpufreq: tegra194: add soc data to support multiple soc Adding SoC data and ops to support multiple SoC's in same driver. Signed-off-by: Sumit Gupta Signed-off-by: Viresh Kumar --- drivers/cpufreq/tegra194-cpufreq.c | 142 +++++++++++++++++++++++++++---------- 1 file changed, 105 insertions(+), 37 deletions(-) diff --git a/drivers/cpufreq/tegra194-cpufreq.c b/drivers/cpufreq/tegra194-cpufreq.c index ac381db25dbe..2d59b2bd0e1d 100644 --- a/drivers/cpufreq/tegra194-cpufreq.c +++ b/drivers/cpufreq/tegra194-cpufreq.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved + * Copyright (c) 2020 - 2022, NVIDIA CORPORATION. All rights reserved */ #include @@ -35,12 +35,6 @@ enum cluster { MAX_CLUSTERS, }; -struct tegra194_cpufreq_data { - void __iomem *regs; - size_t num_clusters; - struct cpufreq_frequency_table **tables; -}; - struct tegra_cpu_ctr { u32 cpu; u32 coreclk_cnt, last_coreclk_cnt; @@ -52,13 +46,42 @@ struct read_counters_work { struct tegra_cpu_ctr c; }; +struct tegra_cpufreq_ops { + void (*read_counters)(struct tegra_cpu_ctr *c); + void (*set_cpu_ndiv)(struct cpufreq_policy *policy, u64 ndiv); + void (*get_cpu_cluster_id)(u32 cpu, u32 *cpuid, u32 *clusterid); + int (*get_cpu_ndiv)(u32 cpu, u32 cpuid, u32 clusterid, u64 *ndiv); +}; + +struct tegra_cpufreq_soc { + struct tegra_cpufreq_ops *ops; + int maxcpus_per_cluster; +}; + +struct tegra194_cpufreq_data { + void __iomem *regs; + size_t num_clusters; + struct cpufreq_frequency_table **tables; + const struct tegra_cpufreq_soc *soc; +}; + static struct workqueue_struct *read_counters_wq; -static void get_cpu_cluster(void *cluster) +static void tegra_get_cpu_mpidr(void *mpidr) { - u64 mpidr = read_cpuid_mpidr() & MPIDR_HWID_BITMASK; + *((u64 *)mpidr) = read_cpuid_mpidr() & MPIDR_HWID_BITMASK; +} + +static void tegra194_get_cpu_cluster_id(u32 cpu, u32 *cpuid, u32 *clusterid) +{ + u64 mpidr; + + smp_call_function_single(cpu, tegra_get_cpu_mpidr, &mpidr, true); - *((uint32_t *)cluster) = MPIDR_AFFINITY_LEVEL(mpidr, 1); + if (cpuid) + *cpuid = MPIDR_AFFINITY_LEVEL(mpidr, 0); + if (clusterid) + *clusterid = MPIDR_AFFINITY_LEVEL(mpidr, 1); } /* @@ -85,11 +108,24 @@ static inline u32 map_ndiv_to_freq(struct mrq_cpu_ndiv_limits_response return nltbl->ref_clk_hz / KHZ * ndiv / (nltbl->pdiv * nltbl->mdiv); } +static void tegra194_read_counters(struct tegra_cpu_ctr *c) +{ + u64 val; + + val = read_freq_feedback(); + c->last_refclk_cnt = lower_32_bits(val); + c->last_coreclk_cnt = upper_32_bits(val); + udelay(US_DELAY); + val = read_freq_feedback(); + c->refclk_cnt = lower_32_bits(val); + c->coreclk_cnt = upper_32_bits(val); +} + static void tegra_read_counters(struct work_struct *work) { + struct tegra194_cpufreq_data *data = cpufreq_get_driver_data(); struct read_counters_work *read_counters_work; struct tegra_cpu_ctr *c; - u64 val; /* * ref_clk_counter(32 bit counter) runs on constant clk, @@ -107,13 +143,7 @@ static void tegra_read_counters(struct work_struct *work) work); c = &read_counters_work->c; - val = read_freq_feedback(); - c->last_refclk_cnt = lower_32_bits(val); - c->last_coreclk_cnt = upper_32_bits(val); - udelay(US_DELAY); - val = read_freq_feedback(); - c->refclk_cnt = lower_32_bits(val); - c->coreclk_cnt = upper_32_bits(val); + data->soc->ops->read_counters(c); } /* @@ -177,7 +207,7 @@ static unsigned int tegra194_calculate_speed(u32 cpu) return (rate_mhz * KHZ); /* in KHz */ } -static void get_cpu_ndiv(void *ndiv) +static void tegra194_get_cpu_ndiv_sysreg(void *ndiv) { u64 ndiv_val; @@ -186,30 +216,43 @@ static void get_cpu_ndiv(void *ndiv) *(u64 *)ndiv = ndiv_val; } -static void set_cpu_ndiv(void *data) +static int tegra194_get_cpu_ndiv(u32 cpu, u32 cpuid, u32 clusterid, u64 *ndiv) +{ + int ret; + + ret = smp_call_function_single(cpu, tegra194_get_cpu_ndiv_sysreg, &ndiv, true); + + return ret; +} + +static void tegra194_set_cpu_ndiv_sysreg(void *data) { - struct cpufreq_frequency_table *tbl = data; - u64 ndiv_val = (u64)tbl->driver_data; + u64 ndiv_val = *(u64 *)data; asm volatile("msr s3_0_c15_c0_4, %0" : : "r" (ndiv_val)); } +static void tegra194_set_cpu_ndiv(struct cpufreq_policy *policy, u64 ndiv) +{ + on_each_cpu_mask(policy->cpus, tegra194_set_cpu_ndiv_sysreg, &ndiv, true); +} + static unsigned int tegra194_get_speed(u32 cpu) { struct tegra194_cpufreq_data *data = cpufreq_get_driver_data(); struct cpufreq_frequency_table *pos; + u32 cpuid, clusterid; unsigned int rate; u64 ndiv; int ret; - u32 cl; - smp_call_function_single(cpu, get_cpu_cluster, &cl, true); + data->soc->ops->get_cpu_cluster_id(cpu, &cpuid, &clusterid); /* reconstruct actual cpu freq using counters */ rate = tegra194_calculate_speed(cpu); /* get last written ndiv value */ - ret = smp_call_function_single(cpu, get_cpu_ndiv, &ndiv, true); + ret = data->soc->ops->get_cpu_ndiv(cpu, cpuid, clusterid, &ndiv); if (WARN_ON_ONCE(ret)) return rate; @@ -219,7 +262,7 @@ static unsigned int tegra194_get_speed(u32 cpu) * to the last written ndiv value from freq_table. This is * done to return consistent value. */ - cpufreq_for_each_valid_entry(pos, data->tables[cl]) { + cpufreq_for_each_valid_entry(pos, data->tables[clusterid]) { if (pos->driver_data != ndiv) continue; @@ -237,19 +280,22 @@ static unsigned int tegra194_get_speed(u32 cpu) static int tegra194_cpufreq_init(struct cpufreq_policy *policy) { struct tegra194_cpufreq_data *data = cpufreq_get_driver_data(); - u32 cpu; - u32 cl; + int maxcpus_per_cluster = data->soc->maxcpus_per_cluster; + u32 start_cpu, cpu; + u32 clusterid; - smp_call_function_single(policy->cpu, get_cpu_cluster, &cl, true); + data->soc->ops->get_cpu_cluster_id(policy->cpu, NULL, &clusterid); - if (cl >= data->num_clusters || !data->tables[cl]) + if (clusterid >= data->num_clusters || !data->tables[clusterid]) return -EINVAL; + start_cpu = rounddown(policy->cpu, maxcpus_per_cluster); /* set same policy for all cpus in a cluster */ - for (cpu = (cl * 2); cpu < ((cl + 1) * 2); cpu++) - cpumask_set_cpu(cpu, policy->cpus); - - policy->freq_table = data->tables[cl]; + for (cpu = start_cpu; cpu < (start_cpu + maxcpus_per_cluster); cpu++) { + if (cpu_possible(cpu)) + cpumask_set_cpu(cpu, policy->cpus); + } + policy->freq_table = data->tables[clusterid]; policy->cpuinfo.transition_latency = TEGRA_CPUFREQ_TRANSITION_LATENCY; return 0; @@ -259,13 +305,14 @@ static int tegra194_cpufreq_set_target(struct cpufreq_policy *policy, unsigned int index) { struct cpufreq_frequency_table *tbl = policy->freq_table + index; + struct tegra194_cpufreq_data *data = cpufreq_get_driver_data(); /* * Each core writes frequency in per core register. Then both cores * in a cluster run at same frequency which is the maximum frequency * request out of the values requested by both cores in that cluster. */ - on_each_cpu_mask(policy->cpus, set_cpu_ndiv, tbl, true); + data->soc->ops->set_cpu_ndiv(policy, (u64)tbl->driver_data); return 0; } @@ -280,6 +327,18 @@ static struct cpufreq_driver tegra194_cpufreq_driver = { .attr = cpufreq_generic_attr, }; +static struct tegra_cpufreq_ops tegra194_cpufreq_ops = { + .read_counters = tegra194_read_counters, + .get_cpu_cluster_id = tegra194_get_cpu_cluster_id, + .get_cpu_ndiv = tegra194_get_cpu_ndiv, + .set_cpu_ndiv = tegra194_set_cpu_ndiv, +}; + +const struct tegra_cpufreq_soc tegra194_cpufreq_soc = { + .ops = &tegra194_cpufreq_ops, + .maxcpus_per_cluster = 2, +}; + static void tegra194_cpufreq_free_resources(void) { destroy_workqueue(read_counters_wq); @@ -359,6 +418,7 @@ init_freq_table(struct platform_device *pdev, struct tegra_bpmp *bpmp, static int tegra194_cpufreq_probe(struct platform_device *pdev) { + const struct tegra_cpufreq_soc *soc; struct tegra194_cpufreq_data *data; struct tegra_bpmp *bpmp; int err, i; @@ -367,6 +427,15 @@ static int tegra194_cpufreq_probe(struct platform_device *pdev) if (!data) return -ENOMEM; + soc = of_device_get_match_data(&pdev->dev); + + if (soc->ops && soc->maxcpus_per_cluster) { + data->soc = soc; + } else { + dev_err(&pdev->dev, "soc data missing\n"); + return -EINVAL; + } + data->num_clusters = MAX_CLUSTERS; data->tables = devm_kcalloc(&pdev->dev, data->num_clusters, sizeof(*data->tables), GFP_KERNEL); @@ -416,10 +485,9 @@ static int tegra194_cpufreq_remove(struct platform_device *pdev) } static const struct of_device_id tegra194_cpufreq_of_match[] = { - { .compatible = "nvidia,tegra194-ccplex", }, + { .compatible = "nvidia,tegra194-ccplex", .data = &tegra194_cpufreq_soc }, { /* sentinel */ } }; -MODULE_DEVICE_TABLE(of, tegra194_cpufreq_of_match); static struct platform_driver tegra194_ccplex_driver = { .driver = { -- cgit v1.2.3-59-g8ed1b From 273bc890a2a83ba8c7d8eee50b74138f5a5834d1 Mon Sep 17 00:00:00 2001 From: Sumit Gupta Date: Tue, 5 Apr 2022 18:31:18 +0530 Subject: cpufreq: tegra194: Add support for Tegra234 This patch adds driver support for Tegra234 cpufreq. Tegra234 has per core MMIO registers instead of system registers for cpu frequency requests and to read the counters for re-constructing the cpu frequency. Also, MPIDR affinity info in Tegra234 is different from Tegra194. Added ops hooks and soc data for Tegra234. This will help to easily add variants of Tegra234 and future SoC's which use similar logic to {get|set} the cpu frequency. Signed-off-by: Sumit Gupta Signed-off-by: Viresh Kumar --- drivers/cpufreq/tegra194-cpufreq.c | 104 +++++++++++++++++++++++++++++++++++++ 1 file changed, 104 insertions(+) diff --git a/drivers/cpufreq/tegra194-cpufreq.c b/drivers/cpufreq/tegra194-cpufreq.c index 2d59b2bd0e1d..2a6a98764a8c 100644 --- a/drivers/cpufreq/tegra194-cpufreq.c +++ b/drivers/cpufreq/tegra194-cpufreq.c @@ -24,6 +24,17 @@ #define CPUFREQ_TBL_STEP_HZ (50 * KHZ * KHZ) #define MAX_CNT ~0U +#define NDIV_MASK 0x1FF + +#define CORE_OFFSET(cpu) (cpu * 8) +#define CMU_CLKS_BASE 0x2000 +#define SCRATCH_FREQ_CORE_REG(data, cpu) (data->regs + CMU_CLKS_BASE + CORE_OFFSET(cpu)) + +#define MMCRAB_CLUSTER_BASE(cl) (0x30000 + (cl * 0x10000)) +#define CLUSTER_ACTMON_BASE(data, cl) \ + (data->regs + (MMCRAB_CLUSTER_BASE(cl) + data->soc->actmon_cntr_base)) +#define CORE_ACTMON_CNTR_REG(data, cl, cpu) (CLUSTER_ACTMON_BASE(data, cl) + CORE_OFFSET(cpu)) + /* cpufreq transisition latency */ #define TEGRA_CPUFREQ_TRANSITION_LATENCY (300 * 1000) /* unit in nanoseconds */ @@ -56,6 +67,7 @@ struct tegra_cpufreq_ops { struct tegra_cpufreq_soc { struct tegra_cpufreq_ops *ops; int maxcpus_per_cluster; + phys_addr_t actmon_cntr_base; }; struct tegra194_cpufreq_data { @@ -72,6 +84,90 @@ static void tegra_get_cpu_mpidr(void *mpidr) *((u64 *)mpidr) = read_cpuid_mpidr() & MPIDR_HWID_BITMASK; } +static void tegra234_get_cpu_cluster_id(u32 cpu, u32 *cpuid, u32 *clusterid) +{ + u64 mpidr; + + smp_call_function_single(cpu, tegra_get_cpu_mpidr, &mpidr, true); + + if (cpuid) + *cpuid = MPIDR_AFFINITY_LEVEL(mpidr, 1); + if (clusterid) + *clusterid = MPIDR_AFFINITY_LEVEL(mpidr, 2); +} + +static int tegra234_get_cpu_ndiv(u32 cpu, u32 cpuid, u32 clusterid, u64 *ndiv) +{ + struct tegra194_cpufreq_data *data = cpufreq_get_driver_data(); + void __iomem *freq_core_reg; + u64 mpidr_id; + + /* use physical id to get address of per core frequency register */ + mpidr_id = (clusterid * data->soc->maxcpus_per_cluster) + cpuid; + freq_core_reg = SCRATCH_FREQ_CORE_REG(data, mpidr_id); + + *ndiv = readl(freq_core_reg) & NDIV_MASK; + + return 0; +} + +static void tegra234_set_cpu_ndiv(struct cpufreq_policy *policy, u64 ndiv) +{ + struct tegra194_cpufreq_data *data = cpufreq_get_driver_data(); + void __iomem *freq_core_reg; + u32 cpu, cpuid, clusterid; + u64 mpidr_id; + + for_each_cpu_and(cpu, policy->cpus, cpu_online_mask) { + data->soc->ops->get_cpu_cluster_id(cpu, &cpuid, &clusterid); + + /* use physical id to get address of per core frequency register */ + mpidr_id = (clusterid * data->soc->maxcpus_per_cluster) + cpuid; + freq_core_reg = SCRATCH_FREQ_CORE_REG(data, mpidr_id); + + writel(ndiv, freq_core_reg); + } +} + +/* + * This register provides access to two counter values with a single + * 64-bit read. The counter values are used to determine the average + * actual frequency a core has run at over a period of time. + * [63:32] PLLP counter: Counts at fixed frequency (408 MHz) + * [31:0] Core clock counter: Counts on every core clock cycle + */ +static void tegra234_read_counters(struct tegra_cpu_ctr *c) +{ + struct tegra194_cpufreq_data *data = cpufreq_get_driver_data(); + void __iomem *actmon_reg; + u32 cpuid, clusterid; + u64 val; + + data->soc->ops->get_cpu_cluster_id(c->cpu, &cpuid, &clusterid); + actmon_reg = CORE_ACTMON_CNTR_REG(data, clusterid, cpuid); + + val = readq(actmon_reg); + c->last_refclk_cnt = upper_32_bits(val); + c->last_coreclk_cnt = lower_32_bits(val); + udelay(US_DELAY); + val = readq(actmon_reg); + c->refclk_cnt = upper_32_bits(val); + c->coreclk_cnt = lower_32_bits(val); +} + +static struct tegra_cpufreq_ops tegra234_cpufreq_ops = { + .read_counters = tegra234_read_counters, + .get_cpu_cluster_id = tegra234_get_cpu_cluster_id, + .get_cpu_ndiv = tegra234_get_cpu_ndiv, + .set_cpu_ndiv = tegra234_set_cpu_ndiv, +}; + +const struct tegra_cpufreq_soc tegra234_cpufreq_soc = { + .ops = &tegra234_cpufreq_ops, + .actmon_cntr_base = 0x9000, + .maxcpus_per_cluster = 4, +}; + static void tegra194_get_cpu_cluster_id(u32 cpu, u32 *cpuid, u32 *clusterid) { u64 mpidr; @@ -442,6 +538,13 @@ static int tegra194_cpufreq_probe(struct platform_device *pdev) if (!data->tables) return -ENOMEM; + if (soc->actmon_cntr_base) { + /* mmio registers are used for frequency request and re-construction */ + data->regs = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(data->regs)) + return PTR_ERR(data->regs); + } + platform_set_drvdata(pdev, data); bpmp = tegra_bpmp_get(&pdev->dev); @@ -486,6 +589,7 @@ static int tegra194_cpufreq_remove(struct platform_device *pdev) static const struct of_device_id tegra194_cpufreq_of_match[] = { { .compatible = "nvidia,tegra194-ccplex", .data = &tegra194_cpufreq_soc }, + { .compatible = "nvidia,tegra234-ccplex-cluster", .data = &tegra234_cpufreq_soc }, { /* sentinel */ } }; -- cgit v1.2.3-59-g8ed1b From 7e6719ad5d1d308c207fb42c19be7495cccb2079 Mon Sep 17 00:00:00 2001 From: Sumit Gupta Date: Tue, 5 Apr 2022 18:31:19 +0530 Subject: arm64: tegra: add node for tegra234 cpufreq Adding cclpex node to represent Tegra234 cpufreq. Tegra234 uses some of the CRAB (Control Register Access Bus) registers for cpu frequency requests. These registers are memory mapped to CCPLEX_MMCRAB_ARM region. In this node, mapping the range of MMCRAB registers required only for cpu frequency info. Signed-off-by: Sumit Gupta Signed-off-by: Viresh Kumar --- arch/arm64/boot/dts/nvidia/tegra234.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi index aaace605bdaa..610207f3f967 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi @@ -1258,6 +1258,13 @@ }; }; + ccplex@e000000 { + compatible = "nvidia,tegra234-ccplex-cluster"; + reg = <0x0 0x0e000000 0x0 0x5ffff>; + nvidia,bpmp = <&bpmp>; + status = "okay"; + }; + sram@40000000 { compatible = "nvidia,tegra234-sysram", "mmio-sram"; reg = <0x0 0x40000000 0x0 0x80000>; -- cgit v1.2.3-59-g8ed1b From b7070187c81cb90549d7561c0e750d7c7eb751f4 Mon Sep 17 00:00:00 2001 From: Jia-Wei Chang Date: Fri, 8 Apr 2022 12:58:55 +0800 Subject: cpufreq: mediatek: Use module_init and add module_exit - Use module_init instead of device_initcall. - Add a function for module_exit to unregister driver. Signed-off-by: Jia-Wei Chang Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Viresh Kumar --- drivers/cpufreq/mediatek-cpufreq.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/cpufreq/mediatek-cpufreq.c b/drivers/cpufreq/mediatek-cpufreq.c index 866163883b48..9d7d9c8dc184 100644 --- a/drivers/cpufreq/mediatek-cpufreq.c +++ b/drivers/cpufreq/mediatek-cpufreq.c @@ -580,7 +580,13 @@ static int __init mtk_cpufreq_driver_init(void) return 0; } -device_initcall(mtk_cpufreq_driver_init); +module_init(mtk_cpufreq_driver_init) + +static void __exit mtk_cpufreq_driver_exit(void) +{ + platform_driver_unregister(&mtk_cpufreq_platdrv); +} +module_exit(mtk_cpufreq_driver_exit) MODULE_DESCRIPTION("MediaTek CPUFreq driver"); MODULE_AUTHOR("Pi-Cheng Chen "); -- cgit v1.2.3-59-g8ed1b From 396dee972a1c6161ad8daca867e5a95d95aac61a Mon Sep 17 00:00:00 2001 From: Jia-Wei Chang Date: Fri, 8 Apr 2022 12:58:56 +0800 Subject: cpufreq: mediatek: Cleanup variables and error handling in mtk_cpu_dvfs_info_init() - Remove several unnecessary varaibles in mtk_cpu_dvfs_info_init(). - Unify error message format and use dev_err_probe() if possible. Signed-off-by: Jia-Wei Chang Signed-off-by: Rex-BC Chen Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Viresh Kumar --- drivers/cpufreq/mediatek-cpufreq.c | 89 +++++++++++++++----------------------- 1 file changed, 34 insertions(+), 55 deletions(-) diff --git a/drivers/cpufreq/mediatek-cpufreq.c b/drivers/cpufreq/mediatek-cpufreq.c index 9d7d9c8dc184..e0545aca7e41 100644 --- a/drivers/cpufreq/mediatek-cpufreq.c +++ b/drivers/cpufreq/mediatek-cpufreq.c @@ -300,96 +300,75 @@ static int mtk_cpufreq_set_target(struct cpufreq_policy *policy, static int mtk_cpu_dvfs_info_init(struct mtk_cpu_dvfs_info *info, int cpu) { struct device *cpu_dev; - struct regulator *proc_reg = ERR_PTR(-ENODEV); - struct regulator *sram_reg = ERR_PTR(-ENODEV); - struct clk *cpu_clk = ERR_PTR(-ENODEV); - struct clk *inter_clk = ERR_PTR(-ENODEV); struct dev_pm_opp *opp; unsigned long rate; int ret; cpu_dev = get_cpu_device(cpu); if (!cpu_dev) { - pr_err("failed to get cpu%d device\n", cpu); + dev_err(cpu_dev, "failed to get cpu%d device\n", cpu); return -ENODEV; } + info->cpu_dev = cpu_dev; - cpu_clk = clk_get(cpu_dev, "cpu"); - if (IS_ERR(cpu_clk)) { - if (PTR_ERR(cpu_clk) == -EPROBE_DEFER) - pr_warn("cpu clk for cpu%d not ready, retry.\n", cpu); - else - pr_err("failed to get cpu clk for cpu%d\n", cpu); - - ret = PTR_ERR(cpu_clk); - return ret; + info->cpu_clk = clk_get(cpu_dev, "cpu"); + if (IS_ERR(info->cpu_clk)) { + ret = PTR_ERR(info->cpu_clk); + return dev_err_probe(cpu_dev, ret, + "cpu%d: failed to get cpu clk\n", cpu); } - inter_clk = clk_get(cpu_dev, "intermediate"); - if (IS_ERR(inter_clk)) { - if (PTR_ERR(inter_clk) == -EPROBE_DEFER) - pr_warn("intermediate clk for cpu%d not ready, retry.\n", - cpu); - else - pr_err("failed to get intermediate clk for cpu%d\n", - cpu); - - ret = PTR_ERR(inter_clk); + info->inter_clk = clk_get(cpu_dev, "intermediate"); + if (IS_ERR(info->inter_clk)) { + ret = PTR_ERR(info->inter_clk); + dev_err_probe(cpu_dev, ret, + "cpu%d: failed to get intermediate clk\n", cpu); goto out_free_resources; } - proc_reg = regulator_get_optional(cpu_dev, "proc"); - if (IS_ERR(proc_reg)) { - if (PTR_ERR(proc_reg) == -EPROBE_DEFER) - pr_warn("proc regulator for cpu%d not ready, retry.\n", - cpu); - else - pr_err("failed to get proc regulator for cpu%d\n", - cpu); - - ret = PTR_ERR(proc_reg); + info->proc_reg = regulator_get_optional(cpu_dev, "proc"); + if (IS_ERR(info->proc_reg)) { + ret = PTR_ERR(info->proc_reg); + dev_err_probe(cpu_dev, ret, + "cpu%d: failed to get proc regulator\n", cpu); goto out_free_resources; } /* Both presence and absence of sram regulator are valid cases. */ - sram_reg = regulator_get_exclusive(cpu_dev, "sram"); + info->sram_reg = regulator_get_exclusive(cpu_dev, "sram"); + if (IS_ERR(info->sram_reg)) + info->sram_reg = NULL; /* Get OPP-sharing information from "operating-points-v2" bindings */ ret = dev_pm_opp_of_get_sharing_cpus(cpu_dev, &info->cpus); if (ret) { - pr_err("failed to get OPP-sharing information for cpu%d\n", - cpu); + dev_err(cpu_dev, + "cpu%d: failed to get OPP-sharing information\n", cpu); goto out_free_resources; } ret = dev_pm_opp_of_cpumask_add_table(&info->cpus); if (ret) { - pr_warn("no OPP table for cpu%d\n", cpu); + dev_warn(cpu_dev, "cpu%d: no OPP table\n", cpu); goto out_free_resources; } /* Search a safe voltage for intermediate frequency. */ - rate = clk_get_rate(inter_clk); + rate = clk_get_rate(info->inter_clk); opp = dev_pm_opp_find_freq_ceil(cpu_dev, &rate); if (IS_ERR(opp)) { - pr_err("failed to get intermediate opp for cpu%d\n", cpu); + dev_err(cpu_dev, "cpu%d: failed to get intermediate opp\n", cpu); ret = PTR_ERR(opp); goto out_free_opp_table; } info->intermediate_voltage = dev_pm_opp_get_voltage(opp); dev_pm_opp_put(opp); - info->cpu_dev = cpu_dev; - info->proc_reg = proc_reg; - info->sram_reg = IS_ERR(sram_reg) ? NULL : sram_reg; - info->cpu_clk = cpu_clk; - info->inter_clk = inter_clk; - /* * If SRAM regulator is present, software "voltage tracking" is needed * for this CPU power domain. */ - info->need_voltage_tracking = !IS_ERR(sram_reg); + info->need_voltage_tracking = (info->sram_reg != NULL); return 0; @@ -397,14 +376,14 @@ out_free_opp_table: dev_pm_opp_of_cpumask_remove_table(&info->cpus); out_free_resources: - if (!IS_ERR(proc_reg)) - regulator_put(proc_reg); - if (!IS_ERR(sram_reg)) - regulator_put(sram_reg); - if (!IS_ERR(cpu_clk)) - clk_put(cpu_clk); - if (!IS_ERR(inter_clk)) - clk_put(inter_clk); + if (!IS_ERR(info->proc_reg)) + regulator_put(info->proc_reg); + if (!IS_ERR(info->sram_reg)) + regulator_put(info->sram_reg); + if (!IS_ERR(info->cpu_clk)) + clk_put(info->cpu_clk); + if (!IS_ERR(info->inter_clk)) + clk_put(info->inter_clk); return ret; } -- cgit v1.2.3-59-g8ed1b From ad975857818b0135bf13b72f66045e2699de5ba0 Mon Sep 17 00:00:00 2001 From: Jia-Wei Chang Date: Fri, 8 Apr 2022 12:58:57 +0800 Subject: cpufreq: mediatek: Remove unused headers Remove unused headers. Signed-off-by: Jia-Wei Chang Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Viresh Kumar --- drivers/cpufreq/mediatek-cpufreq.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/cpufreq/mediatek-cpufreq.c b/drivers/cpufreq/mediatek-cpufreq.c index e0545aca7e41..2a2859dbc5e0 100644 --- a/drivers/cpufreq/mediatek-cpufreq.c +++ b/drivers/cpufreq/mediatek-cpufreq.c @@ -13,8 +13,6 @@ #include #include #include -#include -#include #define MIN_VOLT_SHIFT (100000) #define MAX_VOLT_SHIFT (200000) -- cgit v1.2.3-59-g8ed1b From 4b9ceb757bbb4e8e5769eb1f1ba84bd631e63a43 Mon Sep 17 00:00:00 2001 From: Jia-Wei Chang Date: Fri, 8 Apr 2022 12:58:58 +0800 Subject: cpufreq: mediatek: Enable clocks and regulators We need to enable regulators so that the max and min requested values will be recorded. The intermediate clock is not always enabled by CCF in different projects, so we should enable it in the cpufreq driver. Signed-off-by: Andrew-sh.Cheng Signed-off-by: Jia-Wei Chang Signed-off-by: Rex-BC Chen Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Viresh Kumar --- drivers/cpufreq/mediatek-cpufreq.c | 50 ++++++++++++++++++++++++++++++++++---- 1 file changed, 45 insertions(+), 5 deletions(-) diff --git a/drivers/cpufreq/mediatek-cpufreq.c b/drivers/cpufreq/mediatek-cpufreq.c index 2a2859dbc5e0..dc4a87e68940 100644 --- a/drivers/cpufreq/mediatek-cpufreq.c +++ b/drivers/cpufreq/mediatek-cpufreq.c @@ -332,10 +332,23 @@ static int mtk_cpu_dvfs_info_init(struct mtk_cpu_dvfs_info *info, int cpu) goto out_free_resources; } + ret = regulator_enable(info->proc_reg); + if (ret) { + dev_warn(cpu_dev, "cpu%d: failed to enable vproc\n", cpu); + goto out_free_resources; + } + /* Both presence and absence of sram regulator are valid cases. */ info->sram_reg = regulator_get_exclusive(cpu_dev, "sram"); if (IS_ERR(info->sram_reg)) info->sram_reg = NULL; + else { + ret = regulator_enable(info->sram_reg); + if (ret) { + dev_warn(cpu_dev, "cpu%d: failed to enable vsram\n", cpu); + goto out_free_resources; + } + } /* Get OPP-sharing information from "operating-points-v2" bindings */ ret = dev_pm_opp_of_get_sharing_cpus(cpu_dev, &info->cpus); @@ -351,13 +364,21 @@ static int mtk_cpu_dvfs_info_init(struct mtk_cpu_dvfs_info *info, int cpu) goto out_free_resources; } + ret = clk_prepare_enable(info->cpu_clk); + if (ret) + goto out_free_opp_table; + + ret = clk_prepare_enable(info->inter_clk); + if (ret) + goto out_disable_mux_clock; + /* Search a safe voltage for intermediate frequency. */ rate = clk_get_rate(info->inter_clk); opp = dev_pm_opp_find_freq_ceil(cpu_dev, &rate); if (IS_ERR(opp)) { dev_err(cpu_dev, "cpu%d: failed to get intermediate opp\n", cpu); ret = PTR_ERR(opp); - goto out_free_opp_table; + goto out_disable_inter_clock; } info->intermediate_voltage = dev_pm_opp_get_voltage(opp); dev_pm_opp_put(opp); @@ -370,10 +391,21 @@ static int mtk_cpu_dvfs_info_init(struct mtk_cpu_dvfs_info *info, int cpu) return 0; +out_disable_inter_clock: + clk_disable_unprepare(info->inter_clk); + +out_disable_mux_clock: + clk_disable_unprepare(info->cpu_clk); + out_free_opp_table: dev_pm_opp_of_cpumask_remove_table(&info->cpus); out_free_resources: + if (regulator_is_enabled(info->proc_reg)) + regulator_disable(info->proc_reg); + if (info->sram_reg && regulator_is_enabled(info->sram_reg)) + regulator_disable(info->sram_reg); + if (!IS_ERR(info->proc_reg)) regulator_put(info->proc_reg); if (!IS_ERR(info->sram_reg)) @@ -388,14 +420,22 @@ out_free_resources: static void mtk_cpu_dvfs_info_release(struct mtk_cpu_dvfs_info *info) { - if (!IS_ERR(info->proc_reg)) + if (!IS_ERR(info->proc_reg)) { + regulator_disable(info->proc_reg); regulator_put(info->proc_reg); - if (!IS_ERR(info->sram_reg)) + } + if (!IS_ERR(info->sram_reg)) { + regulator_disable(info->sram_reg); regulator_put(info->sram_reg); - if (!IS_ERR(info->cpu_clk)) + } + if (!IS_ERR(info->cpu_clk)) { + clk_disable_unprepare(info->cpu_clk); clk_put(info->cpu_clk); - if (!IS_ERR(info->inter_clk)) + } + if (!IS_ERR(info->inter_clk)) { + clk_disable_unprepare(info->inter_clk); clk_put(info->inter_clk); + } dev_pm_opp_of_cpumask_remove_table(&info->cpus); } -- cgit v1.2.3-59-g8ed1b From 9acc0f7a6edd8d886782d3ac35c8ce8b0d35475b Mon Sep 17 00:00:00 2001 From: Rex-BC Chen Date: Fri, 22 Apr 2022 15:52:27 +0800 Subject: cpufreq: mediatek: Use device print to show logs - Replace pr_* with dev_* to show logs. - Remove usage of __func__. Signed-off-by: Rex-BC Chen Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Viresh Kumar --- drivers/cpufreq/mediatek-cpufreq.c | 54 ++++++++++++++++++++------------------ 1 file changed, 28 insertions(+), 26 deletions(-) diff --git a/drivers/cpufreq/mediatek-cpufreq.c b/drivers/cpufreq/mediatek-cpufreq.c index dc4a87e68940..e040f3574af9 100644 --- a/drivers/cpufreq/mediatek-cpufreq.c +++ b/drivers/cpufreq/mediatek-cpufreq.c @@ -65,7 +65,8 @@ static int mtk_cpufreq_voltage_tracking(struct mtk_cpu_dvfs_info *info, old_vproc = regulator_get_voltage(proc_reg); if (old_vproc < 0) { - pr_err("%s: invalid Vproc value: %d\n", __func__, old_vproc); + dev_err(info->cpu_dev, + "invalid Vproc value: %d\n", old_vproc); return old_vproc; } /* Vsram should not exceed the maximum allowed voltage of SoC. */ @@ -81,14 +82,14 @@ static int mtk_cpufreq_voltage_tracking(struct mtk_cpu_dvfs_info *info, do { old_vsram = regulator_get_voltage(sram_reg); if (old_vsram < 0) { - pr_err("%s: invalid Vsram value: %d\n", - __func__, old_vsram); + dev_err(info->cpu_dev, + "invalid Vsram value: %d\n", old_vsram); return old_vsram; } old_vproc = regulator_get_voltage(proc_reg); if (old_vproc < 0) { - pr_err("%s: invalid Vproc value: %d\n", - __func__, old_vproc); + dev_err(info->cpu_dev, + "invalid Vproc value: %d\n", old_vproc); return old_vproc; } @@ -136,14 +137,14 @@ static int mtk_cpufreq_voltage_tracking(struct mtk_cpu_dvfs_info *info, do { old_vproc = regulator_get_voltage(proc_reg); if (old_vproc < 0) { - pr_err("%s: invalid Vproc value: %d\n", - __func__, old_vproc); + dev_err(info->cpu_dev, + "invalid Vproc value: %d\n", old_vproc); return old_vproc; } old_vsram = regulator_get_voltage(sram_reg); if (old_vsram < 0) { - pr_err("%s: invalid Vsram value: %d\n", - __func__, old_vsram); + dev_err(info->cpu_dev, + "invalid Vsram value: %d\n", old_vsram); return old_vsram; } @@ -214,7 +215,7 @@ static int mtk_cpufreq_set_target(struct cpufreq_policy *policy, old_freq_hz = clk_get_rate(cpu_clk); old_vproc = regulator_get_voltage(info->proc_reg); if (old_vproc < 0) { - pr_err("%s: invalid Vproc value: %d\n", __func__, old_vproc); + dev_err(cpu_dev, "invalid Vproc value: %d\n", old_vproc); return old_vproc; } @@ -222,8 +223,8 @@ static int mtk_cpufreq_set_target(struct cpufreq_policy *policy, opp = dev_pm_opp_find_freq_ceil(cpu_dev, &freq_hz); if (IS_ERR(opp)) { - pr_err("cpu%d: failed to find OPP for %ld\n", - policy->cpu, freq_hz); + dev_err(cpu_dev, "cpu%d: failed to find OPP for %ld\n", + policy->cpu, freq_hz); return PTR_ERR(opp); } vproc = dev_pm_opp_get_voltage(opp); @@ -237,8 +238,8 @@ static int mtk_cpufreq_set_target(struct cpufreq_policy *policy, if (old_vproc < target_vproc) { ret = mtk_cpufreq_set_voltage(info, target_vproc); if (ret) { - pr_err("cpu%d: failed to scale up voltage!\n", - policy->cpu); + dev_err(cpu_dev, + "cpu%d: failed to scale up voltage!\n", policy->cpu); mtk_cpufreq_set_voltage(info, old_vproc); return ret; } @@ -247,8 +248,8 @@ static int mtk_cpufreq_set_target(struct cpufreq_policy *policy, /* Reparent the CPU clock to intermediate clock. */ ret = clk_set_parent(cpu_clk, info->inter_clk); if (ret) { - pr_err("cpu%d: failed to re-parent cpu clock!\n", - policy->cpu); + dev_err(cpu_dev, + "cpu%d: failed to re-parent cpu clock!\n", policy->cpu); mtk_cpufreq_set_voltage(info, old_vproc); WARN_ON(1); return ret; @@ -257,8 +258,8 @@ static int mtk_cpufreq_set_target(struct cpufreq_policy *policy, /* Set the original PLL to target rate. */ ret = clk_set_rate(armpll, freq_hz); if (ret) { - pr_err("cpu%d: failed to scale cpu clock rate!\n", - policy->cpu); + dev_err(cpu_dev, + "cpu%d: failed to scale cpu clock rate!\n", policy->cpu); clk_set_parent(cpu_clk, armpll); mtk_cpufreq_set_voltage(info, old_vproc); return ret; @@ -267,8 +268,8 @@ static int mtk_cpufreq_set_target(struct cpufreq_policy *policy, /* Set parent of CPU clock back to the original PLL. */ ret = clk_set_parent(cpu_clk, armpll); if (ret) { - pr_err("cpu%d: failed to re-parent cpu clock!\n", - policy->cpu); + dev_err(cpu_dev, + "cpu%d: failed to re-parent cpu clock!\n", policy->cpu); mtk_cpufreq_set_voltage(info, inter_vproc); WARN_ON(1); return ret; @@ -281,8 +282,8 @@ static int mtk_cpufreq_set_target(struct cpufreq_policy *policy, if (vproc < inter_vproc || vproc < old_vproc) { ret = mtk_cpufreq_set_voltage(info, vproc); if (ret) { - pr_err("cpu%d: failed to scale down voltage!\n", - policy->cpu); + dev_err(cpu_dev, + "cpu%d: failed to scale down voltage!\n", policy->cpu); clk_set_parent(cpu_clk, info->inter_clk); clk_set_rate(armpll, old_freq_hz); clk_set_parent(cpu_clk, armpll); @@ -448,15 +449,16 @@ static int mtk_cpufreq_init(struct cpufreq_policy *policy) info = mtk_cpu_dvfs_info_lookup(policy->cpu); if (!info) { - pr_err("dvfs info for cpu%d is not initialized.\n", - policy->cpu); + dev_err(info->cpu_dev, + "dvfs info for cpu%d is not initialized.\n", policy->cpu); return -EINVAL; } ret = dev_pm_opp_init_cpufreq_table(info->cpu_dev, &freq_table); if (ret) { - pr_err("failed to init cpufreq table for cpu%d: %d\n", - policy->cpu, ret); + dev_err(info->cpu_dev, + "failed to init cpufreq table for cpu%d: %d\n", + policy->cpu, ret); return ret; } -- cgit v1.2.3-59-g8ed1b From 4aef4aeaf1dd47b2242ba78857b2773b7a5b5b05 Mon Sep 17 00:00:00 2001 From: Rex-BC Chen Date: Fri, 22 Apr 2022 15:52:28 +0800 Subject: cpufreq: mediatek: Replace old_* with pre_* To make driver more readable, replace old_* with pre_*. Signed-off-by: Rex-BC Chen Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Viresh Kumar --- drivers/cpufreq/mediatek-cpufreq.c | 84 +++++++++++++++++++------------------- 1 file changed, 42 insertions(+), 42 deletions(-) diff --git a/drivers/cpufreq/mediatek-cpufreq.c b/drivers/cpufreq/mediatek-cpufreq.c index e040f3574af9..ff27f77e8ee6 100644 --- a/drivers/cpufreq/mediatek-cpufreq.c +++ b/drivers/cpufreq/mediatek-cpufreq.c @@ -61,18 +61,18 @@ static int mtk_cpufreq_voltage_tracking(struct mtk_cpu_dvfs_info *info, { struct regulator *proc_reg = info->proc_reg; struct regulator *sram_reg = info->sram_reg; - int old_vproc, old_vsram, new_vsram, vsram, vproc, ret; + int pre_vproc, pre_vsram, new_vsram, vsram, vproc, ret; - old_vproc = regulator_get_voltage(proc_reg); - if (old_vproc < 0) { + pre_vproc = regulator_get_voltage(proc_reg); + if (pre_vproc < 0) { dev_err(info->cpu_dev, - "invalid Vproc value: %d\n", old_vproc); - return old_vproc; + "invalid Vproc value: %d\n", pre_vproc); + return pre_vproc; } /* Vsram should not exceed the maximum allowed voltage of SoC. */ new_vsram = min(new_vproc + MIN_VOLT_SHIFT, MAX_VOLT_LIMIT); - if (old_vproc < new_vproc) { + if (pre_vproc < new_vproc) { /* * When scaling up voltages, Vsram and Vproc scale up step * by step. At each step, set Vsram to (Vproc + 200mV) first, @@ -80,20 +80,20 @@ static int mtk_cpufreq_voltage_tracking(struct mtk_cpu_dvfs_info *info, * Keep doing it until Vsram and Vproc hit target voltages. */ do { - old_vsram = regulator_get_voltage(sram_reg); - if (old_vsram < 0) { + pre_vsram = regulator_get_voltage(sram_reg); + if (pre_vsram < 0) { dev_err(info->cpu_dev, - "invalid Vsram value: %d\n", old_vsram); - return old_vsram; + "invalid Vsram value: %d\n", pre_vsram); + return pre_vsram; } - old_vproc = regulator_get_voltage(proc_reg); - if (old_vproc < 0) { + pre_vproc = regulator_get_voltage(proc_reg); + if (pre_vproc < 0) { dev_err(info->cpu_dev, - "invalid Vproc value: %d\n", old_vproc); - return old_vproc; + "invalid Vproc value: %d\n", pre_vproc); + return pre_vproc; } - vsram = min(new_vsram, old_vproc + MAX_VOLT_SHIFT); + vsram = min(new_vsram, pre_vproc + MAX_VOLT_SHIFT); if (vsram + VOLT_TOL >= MAX_VOLT_LIMIT) { vsram = MAX_VOLT_LIMIT; @@ -122,12 +122,12 @@ static int mtk_cpufreq_voltage_tracking(struct mtk_cpu_dvfs_info *info, ret = regulator_set_voltage(proc_reg, vproc, vproc + VOLT_TOL); if (ret) { - regulator_set_voltage(sram_reg, old_vsram, - old_vsram); + regulator_set_voltage(sram_reg, pre_vsram, + pre_vsram); return ret; } } while (vproc < new_vproc || vsram < new_vsram); - } else if (old_vproc > new_vproc) { + } else if (pre_vproc > new_vproc) { /* * When scaling down voltages, Vsram and Vproc scale down step * by step. At each step, set Vproc to (Vsram - 200mV) first, @@ -135,20 +135,20 @@ static int mtk_cpufreq_voltage_tracking(struct mtk_cpu_dvfs_info *info, * Keep doing it until Vsram and Vproc hit target voltages. */ do { - old_vproc = regulator_get_voltage(proc_reg); - if (old_vproc < 0) { + pre_vproc = regulator_get_voltage(proc_reg); + if (pre_vproc < 0) { dev_err(info->cpu_dev, - "invalid Vproc value: %d\n", old_vproc); - return old_vproc; + "invalid Vproc value: %d\n", pre_vproc); + return pre_vproc; } - old_vsram = regulator_get_voltage(sram_reg); - if (old_vsram < 0) { + pre_vsram = regulator_get_voltage(sram_reg); + if (pre_vsram < 0) { dev_err(info->cpu_dev, - "invalid Vsram value: %d\n", old_vsram); - return old_vsram; + "invalid Vsram value: %d\n", pre_vsram); + return pre_vsram; } - vproc = max(new_vproc, old_vsram - MAX_VOLT_SHIFT); + vproc = max(new_vproc, pre_vsram - MAX_VOLT_SHIFT); ret = regulator_set_voltage(proc_reg, vproc, vproc + VOLT_TOL); if (ret) @@ -178,8 +178,8 @@ static int mtk_cpufreq_voltage_tracking(struct mtk_cpu_dvfs_info *info, } if (ret) { - regulator_set_voltage(proc_reg, old_vproc, - old_vproc); + regulator_set_voltage(proc_reg, pre_vproc, + pre_vproc); return ret; } } while (vproc > new_vproc + VOLT_TOL || @@ -207,16 +207,16 @@ static int mtk_cpufreq_set_target(struct cpufreq_policy *policy, struct mtk_cpu_dvfs_info *info = policy->driver_data; struct device *cpu_dev = info->cpu_dev; struct dev_pm_opp *opp; - long freq_hz, old_freq_hz; - int vproc, old_vproc, inter_vproc, target_vproc, ret; + long freq_hz, pre_freq_hz; + int vproc, pre_vproc, inter_vproc, target_vproc, ret; inter_vproc = info->intermediate_voltage; - old_freq_hz = clk_get_rate(cpu_clk); - old_vproc = regulator_get_voltage(info->proc_reg); - if (old_vproc < 0) { - dev_err(cpu_dev, "invalid Vproc value: %d\n", old_vproc); - return old_vproc; + pre_freq_hz = clk_get_rate(cpu_clk); + pre_vproc = regulator_get_voltage(info->proc_reg); + if (pre_vproc < 0) { + dev_err(cpu_dev, "invalid Vproc value: %d\n", pre_vproc); + return pre_vproc; } freq_hz = freq_table[index].frequency * 1000; @@ -235,12 +235,12 @@ static int mtk_cpufreq_set_target(struct cpufreq_policy *policy, * current voltage, scale up voltage first. */ target_vproc = (inter_vproc > vproc) ? inter_vproc : vproc; - if (old_vproc < target_vproc) { + if (pre_vproc < target_vproc) { ret = mtk_cpufreq_set_voltage(info, target_vproc); if (ret) { dev_err(cpu_dev, "cpu%d: failed to scale up voltage!\n", policy->cpu); - mtk_cpufreq_set_voltage(info, old_vproc); + mtk_cpufreq_set_voltage(info, pre_vproc); return ret; } } @@ -250,7 +250,7 @@ static int mtk_cpufreq_set_target(struct cpufreq_policy *policy, if (ret) { dev_err(cpu_dev, "cpu%d: failed to re-parent cpu clock!\n", policy->cpu); - mtk_cpufreq_set_voltage(info, old_vproc); + mtk_cpufreq_set_voltage(info, pre_vproc); WARN_ON(1); return ret; } @@ -261,7 +261,7 @@ static int mtk_cpufreq_set_target(struct cpufreq_policy *policy, dev_err(cpu_dev, "cpu%d: failed to scale cpu clock rate!\n", policy->cpu); clk_set_parent(cpu_clk, armpll); - mtk_cpufreq_set_voltage(info, old_vproc); + mtk_cpufreq_set_voltage(info, pre_vproc); return ret; } @@ -279,13 +279,13 @@ static int mtk_cpufreq_set_target(struct cpufreq_policy *policy, * If the new voltage is lower than the intermediate voltage or the * original voltage, scale down to the new voltage. */ - if (vproc < inter_vproc || vproc < old_vproc) { + if (vproc < inter_vproc || vproc < pre_vproc) { ret = mtk_cpufreq_set_voltage(info, vproc); if (ret) { dev_err(cpu_dev, "cpu%d: failed to scale down voltage!\n", policy->cpu); clk_set_parent(cpu_clk, info->inter_clk); - clk_set_rate(armpll, old_freq_hz); + clk_set_rate(armpll, pre_freq_hz); clk_set_parent(cpu_clk, armpll); return ret; } -- cgit v1.2.3-59-g8ed1b From bffcd33313dcfaf6357753c25c8ef8b4c628e46b Mon Sep 17 00:00:00 2001 From: Jia-Wei Chang Date: Fri, 22 Apr 2022 15:52:29 +0800 Subject: cpufreq: mediatek: Record previous target vproc value We found the buck voltage may not be exactly the same with what we set because CPU may share the same buck with other module. Therefore, we need to record the previous desired value instead of reading it from regulators. Signed-off-by: Andrew-sh.Cheng Signed-off-by: Jia-Wei Chang Signed-off-by: Rex-BC Chen Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Viresh Kumar --- drivers/cpufreq/mediatek-cpufreq.c | 20 ++++++++++++++++---- 1 file changed, 16 insertions(+), 4 deletions(-) diff --git a/drivers/cpufreq/mediatek-cpufreq.c b/drivers/cpufreq/mediatek-cpufreq.c index ff27f77e8ee6..1688cf68849c 100644 --- a/drivers/cpufreq/mediatek-cpufreq.c +++ b/drivers/cpufreq/mediatek-cpufreq.c @@ -40,6 +40,7 @@ struct mtk_cpu_dvfs_info { struct list_head list_head; int intermediate_voltage; bool need_voltage_tracking; + int pre_vproc; }; static LIST_HEAD(dvfs_info_list); @@ -191,11 +192,17 @@ static int mtk_cpufreq_voltage_tracking(struct mtk_cpu_dvfs_info *info, static int mtk_cpufreq_set_voltage(struct mtk_cpu_dvfs_info *info, int vproc) { + int ret; + if (info->need_voltage_tracking) - return mtk_cpufreq_voltage_tracking(info, vproc); + ret = mtk_cpufreq_voltage_tracking(info, vproc); else - return regulator_set_voltage(info->proc_reg, vproc, - vproc + VOLT_TOL); + ret = regulator_set_voltage(info->proc_reg, vproc, + MAX_VOLT_LIMIT); + if (!ret) + info->pre_vproc = vproc; + + return ret; } static int mtk_cpufreq_set_target(struct cpufreq_policy *policy, @@ -213,7 +220,12 @@ static int mtk_cpufreq_set_target(struct cpufreq_policy *policy, inter_vproc = info->intermediate_voltage; pre_freq_hz = clk_get_rate(cpu_clk); - pre_vproc = regulator_get_voltage(info->proc_reg); + + if (unlikely(info->pre_vproc <= 0)) + pre_vproc = regulator_get_voltage(info->proc_reg); + else + pre_vproc = info->pre_vproc; + if (pre_vproc < 0) { dev_err(cpu_dev, "invalid Vproc value: %d\n", pre_vproc); return pre_vproc; -- cgit v1.2.3-59-g8ed1b From ffa7bdf7f344477ad817504c87d8d2db5316a8b6 Mon Sep 17 00:00:00 2001 From: Jia-Wei Chang Date: Fri, 22 Apr 2022 15:52:33 +0800 Subject: cpufreq: mediatek: Make sram regulator optional For some MediaTek SoCs, like MT8186, it's possible that the sram regulator is shared between CPU and CCI. We hope regulator framework can return error for error handling rather than a dummy handler from regulator_get api. Therefore, we choose to use regulator_get_optional. Signed-off-by: Jia-Wei Chang Signed-off-by: Rex-BC Chen Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Viresh Kumar --- drivers/cpufreq/mediatek-cpufreq.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/cpufreq/mediatek-cpufreq.c b/drivers/cpufreq/mediatek-cpufreq.c index 1688cf68849c..bcabb3726a5b 100644 --- a/drivers/cpufreq/mediatek-cpufreq.c +++ b/drivers/cpufreq/mediatek-cpufreq.c @@ -352,7 +352,7 @@ static int mtk_cpu_dvfs_info_init(struct mtk_cpu_dvfs_info *info, int cpu) } /* Both presence and absence of sram regulator are valid cases. */ - info->sram_reg = regulator_get_exclusive(cpu_dev, "sram"); + info->sram_reg = regulator_get_optional(cpu_dev, "sram"); if (IS_ERR(info->sram_reg)) info->sram_reg = NULL; else { -- cgit v1.2.3-59-g8ed1b From a3b8d1b12c6bc3655332f19af84d0780ba88a578 Mon Sep 17 00:00:00 2001 From: Wan Jiabing Date: Tue, 26 Apr 2022 19:17:14 +0800 Subject: cpufreq: mediatek: Fix NULL pointer dereference in mediatek-cpufreq Fix following coccicheck error: drivers/cpufreq/mediatek-cpufreq.c:464:16-23: ERROR: info is NULL but dereferenced. Use pr_err instead of dev_err to avoid dereferring a NULL pointer. Fixes: f52b16ba9fe4 ("cpufreq: mediatek: Use device print to show logs") Signed-off-by: Wan Jiabing Reviewed-by: Matthias Brugger Signed-off-by: Viresh Kumar --- drivers/cpufreq/mediatek-cpufreq.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/cpufreq/mediatek-cpufreq.c b/drivers/cpufreq/mediatek-cpufreq.c index bcabb3726a5b..901042e9a240 100644 --- a/drivers/cpufreq/mediatek-cpufreq.c +++ b/drivers/cpufreq/mediatek-cpufreq.c @@ -461,8 +461,8 @@ static int mtk_cpufreq_init(struct cpufreq_policy *policy) info = mtk_cpu_dvfs_info_lookup(policy->cpu); if (!info) { - dev_err(info->cpu_dev, - "dvfs info for cpu%d is not initialized.\n", policy->cpu); + pr_err("dvfs info for cpu%d is not initialized.\n", + policy->cpu); return -EINVAL; } -- cgit v1.2.3-59-g8ed1b From f126fbadce92b92c3a7be41e4abc1fbae93ae2ef Mon Sep 17 00:00:00 2001 From: Rex-BC Chen Date: Thu, 5 May 2022 19:52:18 +0800 Subject: cpufreq: mediatek: Unregister platform device on exit We register the platform device when driver inits. However, we do not unregister it when driver exits. To resolve this, we declare the platform data to be a global static variable and rename it to be "cpufreq_pdev". With this global variable, we can do platform_device_unregister() when driver exits. Fixes: 501c574f4e3a ("cpufreq: mediatek: Add support of cpufreq to MT2701/MT7623 SoC") Signed-off-by: Rex-BC Chen [ Viresh: Commit log and Subject ] Signed-off-by: Viresh Kumar --- drivers/cpufreq/mediatek-cpufreq.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/cpufreq/mediatek-cpufreq.c b/drivers/cpufreq/mediatek-cpufreq.c index 901042e9a240..d15cbef4a72e 100644 --- a/drivers/cpufreq/mediatek-cpufreq.c +++ b/drivers/cpufreq/mediatek-cpufreq.c @@ -43,6 +43,8 @@ struct mtk_cpu_dvfs_info { int pre_vproc; }; +static struct platform_device *cpufreq_pdev; + static LIST_HEAD(dvfs_info_list); static struct mtk_cpu_dvfs_info *mtk_cpu_dvfs_info_lookup(int cpu) @@ -578,7 +580,6 @@ static int __init mtk_cpufreq_driver_init(void) { struct device_node *np; const struct of_device_id *match; - struct platform_device *pdev; int err; np = of_find_node_by_path("/"); @@ -602,11 +603,11 @@ static int __init mtk_cpufreq_driver_init(void) * and the device registration codes are put here to handle defer * probing. */ - pdev = platform_device_register_simple("mtk-cpufreq", -1, NULL, 0); - if (IS_ERR(pdev)) { + cpufreq_pdev = platform_device_register_simple("mtk-cpufreq", -1, NULL, 0); + if (IS_ERR(cpufreq_pdev)) { pr_err("failed to register mtk-cpufreq platform device\n"); platform_driver_unregister(&mtk_cpufreq_platdrv); - return PTR_ERR(pdev); + return PTR_ERR(cpufreq_pdev); } return 0; @@ -615,6 +616,7 @@ module_init(mtk_cpufreq_driver_init) static void __exit mtk_cpufreq_driver_exit(void) { + platform_device_unregister(cpufreq_pdev); platform_driver_unregister(&mtk_cpufreq_platdrv); } module_exit(mtk_cpufreq_driver_exit) -- cgit v1.2.3-59-g8ed1b From ead858bd128d4ecfb2107115190d52d50416ec45 Mon Sep 17 00:00:00 2001 From: Rex-BC Chen Date: Thu, 5 May 2022 19:52:19 +0800 Subject: cpufreq: mediatek: Move voltage limits to platform data Voltages and shifts are defined as macros originally. There are different requirements of these values for each MediaTek SoCs. Therefore, we add the platform data and move these values into it. Signed-off-by: Jia-Wei Chang Signed-off-by: Rex-BC Chen Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Viresh Kumar --- drivers/cpufreq/mediatek-cpufreq.c | 84 ++++++++++++++++++++++++++------------ 1 file changed, 58 insertions(+), 26 deletions(-) diff --git a/drivers/cpufreq/mediatek-cpufreq.c b/drivers/cpufreq/mediatek-cpufreq.c index d15cbef4a72e..0b6c3479c8cc 100644 --- a/drivers/cpufreq/mediatek-cpufreq.c +++ b/drivers/cpufreq/mediatek-cpufreq.c @@ -10,15 +10,21 @@ #include #include #include +#include #include #include #include -#define MIN_VOLT_SHIFT (100000) -#define MAX_VOLT_SHIFT (200000) -#define MAX_VOLT_LIMIT (1150000) #define VOLT_TOL (10000) +struct mtk_cpufreq_platform_data { + int min_volt_shift; + int max_volt_shift; + int proc_max_volt; + int sram_min_volt; + int sram_max_volt; +}; + /* * The struct mtk_cpu_dvfs_info holds necessary information for doing CPU DVFS * on each CPU power/clock domain of Mediatek SoCs. Each CPU cluster in @@ -41,6 +47,7 @@ struct mtk_cpu_dvfs_info { int intermediate_voltage; bool need_voltage_tracking; int pre_vproc; + const struct mtk_cpufreq_platform_data *soc_data; }; static struct platform_device *cpufreq_pdev; @@ -62,6 +69,7 @@ static struct mtk_cpu_dvfs_info *mtk_cpu_dvfs_info_lookup(int cpu) static int mtk_cpufreq_voltage_tracking(struct mtk_cpu_dvfs_info *info, int new_vproc) { + const struct mtk_cpufreq_platform_data *soc_data = info->soc_data; struct regulator *proc_reg = info->proc_reg; struct regulator *sram_reg = info->sram_reg; int pre_vproc, pre_vsram, new_vsram, vsram, vproc, ret; @@ -73,7 +81,8 @@ static int mtk_cpufreq_voltage_tracking(struct mtk_cpu_dvfs_info *info, return pre_vproc; } /* Vsram should not exceed the maximum allowed voltage of SoC. */ - new_vsram = min(new_vproc + MIN_VOLT_SHIFT, MAX_VOLT_LIMIT); + new_vsram = min(new_vproc + soc_data->min_volt_shift, + soc_data->sram_max_volt); if (pre_vproc < new_vproc) { /* @@ -96,10 +105,11 @@ static int mtk_cpufreq_voltage_tracking(struct mtk_cpu_dvfs_info *info, return pre_vproc; } - vsram = min(new_vsram, pre_vproc + MAX_VOLT_SHIFT); + vsram = min(new_vsram, + pre_vproc + soc_data->min_volt_shift); - if (vsram + VOLT_TOL >= MAX_VOLT_LIMIT) { - vsram = MAX_VOLT_LIMIT; + if (vsram + VOLT_TOL >= soc_data->sram_max_volt) { + vsram = soc_data->sram_max_volt; /* * If the target Vsram hits the maximum voltage, @@ -117,7 +127,7 @@ static int mtk_cpufreq_voltage_tracking(struct mtk_cpu_dvfs_info *info, ret = regulator_set_voltage(sram_reg, vsram, vsram + VOLT_TOL); - vproc = vsram - MIN_VOLT_SHIFT; + vproc = vsram - soc_data->min_volt_shift; } if (ret) return ret; @@ -151,7 +161,8 @@ static int mtk_cpufreq_voltage_tracking(struct mtk_cpu_dvfs_info *info, return pre_vsram; } - vproc = max(new_vproc, pre_vsram - MAX_VOLT_SHIFT); + vproc = max(new_vproc, + pre_vsram - soc_data->max_volt_shift); ret = regulator_set_voltage(proc_reg, vproc, vproc + VOLT_TOL); if (ret) @@ -160,10 +171,11 @@ static int mtk_cpufreq_voltage_tracking(struct mtk_cpu_dvfs_info *info, if (vproc == new_vproc) vsram = new_vsram; else - vsram = max(new_vsram, vproc + MIN_VOLT_SHIFT); + vsram = max(new_vsram, + vproc + soc_data->min_volt_shift); - if (vsram + VOLT_TOL >= MAX_VOLT_LIMIT) { - vsram = MAX_VOLT_LIMIT; + if (vsram + VOLT_TOL >= soc_data->sram_max_volt) { + vsram = soc_data->sram_max_volt; /* * If the target Vsram hits the maximum voltage, @@ -194,13 +206,14 @@ static int mtk_cpufreq_voltage_tracking(struct mtk_cpu_dvfs_info *info, static int mtk_cpufreq_set_voltage(struct mtk_cpu_dvfs_info *info, int vproc) { + const struct mtk_cpufreq_platform_data *soc_data = info->soc_data; int ret; if (info->need_voltage_tracking) ret = mtk_cpufreq_voltage_tracking(info, vproc); else ret = regulator_set_voltage(info->proc_reg, vproc, - MAX_VOLT_LIMIT); + soc_data->proc_max_volt); if (!ret) info->pre_vproc = vproc; @@ -509,9 +522,17 @@ static struct cpufreq_driver mtk_cpufreq_driver = { static int mtk_cpufreq_probe(struct platform_device *pdev) { + const struct mtk_cpufreq_platform_data *data; struct mtk_cpu_dvfs_info *info, *tmp; int cpu, ret; + data = dev_get_platdata(&pdev->dev); + if (!data) { + dev_err(&pdev->dev, + "failed to get mtk cpufreq platform data\n"); + return -ENODEV; + } + for_each_possible_cpu(cpu) { info = mtk_cpu_dvfs_info_lookup(cpu); if (info) @@ -523,6 +544,7 @@ static int mtk_cpufreq_probe(struct platform_device *pdev) goto release_dvfs_info_list; } + info->soc_data = data; ret = mtk_cpu_dvfs_info_init(info, cpu); if (ret) { dev_err(&pdev->dev, @@ -558,20 +580,27 @@ static struct platform_driver mtk_cpufreq_platdrv = { .probe = mtk_cpufreq_probe, }; +static const struct mtk_cpufreq_platform_data mt2701_platform_data = { + .min_volt_shift = 100000, + .max_volt_shift = 200000, + .proc_max_volt = 1150000, + .sram_min_volt = 0, + .sram_max_volt = 1150000, +}; + /* List of machines supported by this driver */ static const struct of_device_id mtk_cpufreq_machines[] __initconst = { - { .compatible = "mediatek,mt2701", }, - { .compatible = "mediatek,mt2712", }, - { .compatible = "mediatek,mt7622", }, - { .compatible = "mediatek,mt7623", }, - { .compatible = "mediatek,mt8167", }, - { .compatible = "mediatek,mt817x", }, - { .compatible = "mediatek,mt8173", }, - { .compatible = "mediatek,mt8176", }, - { .compatible = "mediatek,mt8183", }, - { .compatible = "mediatek,mt8365", }, - { .compatible = "mediatek,mt8516", }, - + { .compatible = "mediatek,mt2701", .data = &mt2701_platform_data }, + { .compatible = "mediatek,mt2712", .data = &mt2701_platform_data }, + { .compatible = "mediatek,mt7622", .data = &mt2701_platform_data }, + { .compatible = "mediatek,mt7623", .data = &mt2701_platform_data }, + { .compatible = "mediatek,mt8167", .data = &mt2701_platform_data }, + { .compatible = "mediatek,mt817x", .data = &mt2701_platform_data }, + { .compatible = "mediatek,mt8173", .data = &mt2701_platform_data }, + { .compatible = "mediatek,mt8176", .data = &mt2701_platform_data }, + { .compatible = "mediatek,mt8183", .data = &mt2701_platform_data }, + { .compatible = "mediatek,mt8365", .data = &mt2701_platform_data }, + { .compatible = "mediatek,mt8516", .data = &mt2701_platform_data }, { } }; MODULE_DEVICE_TABLE(of, mtk_cpufreq_machines); @@ -580,6 +609,7 @@ static int __init mtk_cpufreq_driver_init(void) { struct device_node *np; const struct of_device_id *match; + const struct mtk_cpufreq_platform_data *data; int err; np = of_find_node_by_path("/"); @@ -592,6 +622,7 @@ static int __init mtk_cpufreq_driver_init(void) pr_debug("Machine is not compatible with mtk-cpufreq\n"); return -ENODEV; } + data = match->data; err = platform_driver_register(&mtk_cpufreq_platdrv); if (err) @@ -603,7 +634,8 @@ static int __init mtk_cpufreq_driver_init(void) * and the device registration codes are put here to handle defer * probing. */ - cpufreq_pdev = platform_device_register_simple("mtk-cpufreq", -1, NULL, 0); + cpufreq_pdev = platform_device_register_data(NULL, "mtk-cpufreq", -1, + data, sizeof(*data)); if (IS_ERR(cpufreq_pdev)) { pr_err("failed to register mtk-cpufreq platform device\n"); platform_driver_unregister(&mtk_cpufreq_platdrv); -- cgit v1.2.3-59-g8ed1b From 6a17b3876bc8303612d7ad59ecf7cbc0db418bcd Mon Sep 17 00:00:00 2001 From: Jia-Wei Chang Date: Thu, 5 May 2022 19:52:20 +0800 Subject: cpufreq: mediatek: Refine mtk_cpufreq_voltage_tracking() Because the difference of sram and proc should in a range of min_volt_shift and max_volt_shift. We need to adjust the sram and proc step by step. We replace VOLT_TOL (voltage tolerance) with the platform data and update the logic to determine the voltage boundary and invoking regulator_set_voltage. - Use 'sram_min_volt' and 'sram_max_volt' to determine the voltage boundary of sram regulator. - Use (sram_min_volt - min_volt_shift) and 'proc_max_volt' to determine the voltage boundary of vproc regulator. Moreover, to prevent infinite loop when tracking voltage, we calculate the maximum value for each platform data. We assume min voltage is 0 and tracking target voltage using min_volt_shift for each iteration. The retry_max is 3 times of expeted iteration count. Signed-off-by: Jia-Wei Chang Signed-off-by: Rex-BC Chen Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Viresh Kumar --- drivers/cpufreq/mediatek-cpufreq.c | 147 +++++++++++++------------------------ 1 file changed, 51 insertions(+), 96 deletions(-) diff --git a/drivers/cpufreq/mediatek-cpufreq.c b/drivers/cpufreq/mediatek-cpufreq.c index 0b6c3479c8cc..fe205eca657d 100644 --- a/drivers/cpufreq/mediatek-cpufreq.c +++ b/drivers/cpufreq/mediatek-cpufreq.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -15,8 +16,6 @@ #include #include -#define VOLT_TOL (10000) - struct mtk_cpufreq_platform_data { int min_volt_shift; int max_volt_shift; @@ -48,6 +47,7 @@ struct mtk_cpu_dvfs_info { bool need_voltage_tracking; int pre_vproc; const struct mtk_cpufreq_platform_data *soc_data; + int vtrack_max; }; static struct platform_device *cpufreq_pdev; @@ -73,6 +73,7 @@ static int mtk_cpufreq_voltage_tracking(struct mtk_cpu_dvfs_info *info, struct regulator *proc_reg = info->proc_reg; struct regulator *sram_reg = info->sram_reg; int pre_vproc, pre_vsram, new_vsram, vsram, vproc, ret; + int retry = info->vtrack_max; pre_vproc = regulator_get_voltage(proc_reg); if (pre_vproc < 0) { @@ -80,91 +81,44 @@ static int mtk_cpufreq_voltage_tracking(struct mtk_cpu_dvfs_info *info, "invalid Vproc value: %d\n", pre_vproc); return pre_vproc; } - /* Vsram should not exceed the maximum allowed voltage of SoC. */ - new_vsram = min(new_vproc + soc_data->min_volt_shift, - soc_data->sram_max_volt); - - if (pre_vproc < new_vproc) { - /* - * When scaling up voltages, Vsram and Vproc scale up step - * by step. At each step, set Vsram to (Vproc + 200mV) first, - * then set Vproc to (Vsram - 100mV). - * Keep doing it until Vsram and Vproc hit target voltages. - */ - do { - pre_vsram = regulator_get_voltage(sram_reg); - if (pre_vsram < 0) { - dev_err(info->cpu_dev, - "invalid Vsram value: %d\n", pre_vsram); - return pre_vsram; - } - pre_vproc = regulator_get_voltage(proc_reg); - if (pre_vproc < 0) { - dev_err(info->cpu_dev, - "invalid Vproc value: %d\n", pre_vproc); - return pre_vproc; - } - - vsram = min(new_vsram, - pre_vproc + soc_data->min_volt_shift); - if (vsram + VOLT_TOL >= soc_data->sram_max_volt) { - vsram = soc_data->sram_max_volt; + pre_vsram = regulator_get_voltage(sram_reg); + if (pre_vsram < 0) { + dev_err(info->cpu_dev, "invalid Vsram value: %d\n", pre_vsram); + return pre_vsram; + } - /* - * If the target Vsram hits the maximum voltage, - * try to set the exact voltage value first. - */ - ret = regulator_set_voltage(sram_reg, vsram, - vsram); - if (ret) - ret = regulator_set_voltage(sram_reg, - vsram - VOLT_TOL, - vsram); + new_vsram = clamp(new_vproc + soc_data->min_volt_shift, + soc_data->sram_min_volt, soc_data->sram_max_volt); - vproc = new_vproc; - } else { - ret = regulator_set_voltage(sram_reg, vsram, - vsram + VOLT_TOL); + do { + if (pre_vproc <= new_vproc) { + vsram = clamp(pre_vproc + soc_data->max_volt_shift, + soc_data->sram_min_volt, new_vsram); + ret = regulator_set_voltage(sram_reg, vsram, + soc_data->sram_max_volt); - vproc = vsram - soc_data->min_volt_shift; - } if (ret) return ret; + if (vsram == soc_data->sram_max_volt || + new_vsram == soc_data->sram_min_volt) + vproc = new_vproc; + else + vproc = vsram - soc_data->min_volt_shift; + ret = regulator_set_voltage(proc_reg, vproc, - vproc + VOLT_TOL); + soc_data->proc_max_volt); if (ret) { regulator_set_voltage(sram_reg, pre_vsram, - pre_vsram); + soc_data->sram_max_volt); return ret; } - } while (vproc < new_vproc || vsram < new_vsram); - } else if (pre_vproc > new_vproc) { - /* - * When scaling down voltages, Vsram and Vproc scale down step - * by step. At each step, set Vproc to (Vsram - 200mV) first, - * then set Vproc to (Vproc + 100mV). - * Keep doing it until Vsram and Vproc hit target voltages. - */ - do { - pre_vproc = regulator_get_voltage(proc_reg); - if (pre_vproc < 0) { - dev_err(info->cpu_dev, - "invalid Vproc value: %d\n", pre_vproc); - return pre_vproc; - } - pre_vsram = regulator_get_voltage(sram_reg); - if (pre_vsram < 0) { - dev_err(info->cpu_dev, - "invalid Vsram value: %d\n", pre_vsram); - return pre_vsram; - } - + } else if (pre_vproc > new_vproc) { vproc = max(new_vproc, pre_vsram - soc_data->max_volt_shift); ret = regulator_set_voltage(proc_reg, vproc, - vproc + VOLT_TOL); + soc_data->proc_max_volt); if (ret) return ret; @@ -174,32 +128,24 @@ static int mtk_cpufreq_voltage_tracking(struct mtk_cpu_dvfs_info *info, vsram = max(new_vsram, vproc + soc_data->min_volt_shift); - if (vsram + VOLT_TOL >= soc_data->sram_max_volt) { - vsram = soc_data->sram_max_volt; - - /* - * If the target Vsram hits the maximum voltage, - * try to set the exact voltage value first. - */ - ret = regulator_set_voltage(sram_reg, vsram, - vsram); - if (ret) - ret = regulator_set_voltage(sram_reg, - vsram - VOLT_TOL, - vsram); - } else { - ret = regulator_set_voltage(sram_reg, vsram, - vsram + VOLT_TOL); - } - + ret = regulator_set_voltage(sram_reg, vsram, + soc_data->sram_max_volt); if (ret) { regulator_set_voltage(proc_reg, pre_vproc, - pre_vproc); + soc_data->proc_max_volt); return ret; } - } while (vproc > new_vproc + VOLT_TOL || - vsram > new_vsram + VOLT_TOL); - } + } + + pre_vproc = vproc; + pre_vsram = vsram; + + if (--retry < 0) { + dev_err(info->cpu_dev, + "over loop count, failed to set voltage\n"); + return -EINVAL; + } + } while (vproc != new_vproc || vsram != new_vsram); return 0; } @@ -261,8 +207,8 @@ static int mtk_cpufreq_set_target(struct cpufreq_policy *policy, * If the new voltage or the intermediate voltage is higher than the * current voltage, scale up voltage first. */ - target_vproc = (inter_vproc > vproc) ? inter_vproc : vproc; - if (pre_vproc < target_vproc) { + target_vproc = max(inter_vproc, vproc); + if (pre_vproc <= target_vproc) { ret = mtk_cpufreq_set_voltage(info, target_vproc); if (ret) { dev_err(cpu_dev, @@ -417,6 +363,15 @@ static int mtk_cpu_dvfs_info_init(struct mtk_cpu_dvfs_info *info, int cpu) */ info->need_voltage_tracking = (info->sram_reg != NULL); + /* + * We assume min voltage is 0 and tracking target voltage using + * min_volt_shift for each iteration. + * The vtrack_max is 3 times of expeted iteration count. + */ + info->vtrack_max = 3 * DIV_ROUND_UP(max(info->soc_data->sram_max_volt, + info->soc_data->proc_max_volt), + info->soc_data->min_volt_shift); + return 0; out_disable_inter_clock: -- cgit v1.2.3-59-g8ed1b From c210063b40acab74bb7262d2bfae557171884ff2 Mon Sep 17 00:00:00 2001 From: Rex-BC Chen Date: Thu, 5 May 2022 19:52:21 +0800 Subject: cpufreq: mediatek: Add opp notification support From this opp notifier, cpufreq should listen to opp notification and do proper actions when receiving events of disable and voltage adjustment. One of the user for this opp notifier is MediaTek SVS. The MediaTek Smart Voltage Scaling (SVS) is a hardware which calculates suitable SVS bank voltages to OPP voltage table. Signed-off-by: Andrew-sh.Cheng Signed-off-by: Jia-Wei Chang Signed-off-by: Rex-BC Chen Reviewed-by: AngeloGioacchino Del Regno [ Viresh: Renamed opp_freq as current_freq and moved its initialization ] Signed-off-by: Viresh Kumar --- drivers/cpufreq/mediatek-cpufreq.c | 90 ++++++++++++++++++++++++++++++++++---- 1 file changed, 82 insertions(+), 8 deletions(-) diff --git a/drivers/cpufreq/mediatek-cpufreq.c b/drivers/cpufreq/mediatek-cpufreq.c index fe205eca657d..75bf21ddf61f 100644 --- a/drivers/cpufreq/mediatek-cpufreq.c +++ b/drivers/cpufreq/mediatek-cpufreq.c @@ -46,6 +46,11 @@ struct mtk_cpu_dvfs_info { int intermediate_voltage; bool need_voltage_tracking; int pre_vproc; + /* Avoid race condition for regulators between notify and policy */ + struct mutex reg_lock; + struct notifier_block opp_nb; + unsigned int opp_cpu; + unsigned long current_freq; const struct mtk_cpufreq_platform_data *soc_data; int vtrack_max; }; @@ -182,6 +187,8 @@ static int mtk_cpufreq_set_target(struct cpufreq_policy *policy, pre_freq_hz = clk_get_rate(cpu_clk); + mutex_lock(&info->reg_lock); + if (unlikely(info->pre_vproc <= 0)) pre_vproc = regulator_get_voltage(info->proc_reg); else @@ -214,7 +221,7 @@ static int mtk_cpufreq_set_target(struct cpufreq_policy *policy, dev_err(cpu_dev, "cpu%d: failed to scale up voltage!\n", policy->cpu); mtk_cpufreq_set_voltage(info, pre_vproc); - return ret; + goto out; } } @@ -224,8 +231,7 @@ static int mtk_cpufreq_set_target(struct cpufreq_policy *policy, dev_err(cpu_dev, "cpu%d: failed to re-parent cpu clock!\n", policy->cpu); mtk_cpufreq_set_voltage(info, pre_vproc); - WARN_ON(1); - return ret; + goto out; } /* Set the original PLL to target rate. */ @@ -235,7 +241,7 @@ static int mtk_cpufreq_set_target(struct cpufreq_policy *policy, "cpu%d: failed to scale cpu clock rate!\n", policy->cpu); clk_set_parent(cpu_clk, armpll); mtk_cpufreq_set_voltage(info, pre_vproc); - return ret; + goto out; } /* Set parent of CPU clock back to the original PLL. */ @@ -244,8 +250,7 @@ static int mtk_cpufreq_set_target(struct cpufreq_policy *policy, dev_err(cpu_dev, "cpu%d: failed to re-parent cpu clock!\n", policy->cpu); mtk_cpufreq_set_voltage(info, inter_vproc); - WARN_ON(1); - return ret; + goto out; } /* @@ -260,15 +265,72 @@ static int mtk_cpufreq_set_target(struct cpufreq_policy *policy, clk_set_parent(cpu_clk, info->inter_clk); clk_set_rate(armpll, pre_freq_hz); clk_set_parent(cpu_clk, armpll); - return ret; + goto out; } } - return 0; + info->current_freq = freq_hz; + +out: + mutex_unlock(&info->reg_lock); + + return ret; } #define DYNAMIC_POWER "dynamic-power-coefficient" +static int mtk_cpufreq_opp_notifier(struct notifier_block *nb, + unsigned long event, void *data) +{ + struct dev_pm_opp *opp = data; + struct dev_pm_opp *new_opp; + struct mtk_cpu_dvfs_info *info; + unsigned long freq, volt; + struct cpufreq_policy *policy; + int ret = 0; + + info = container_of(nb, struct mtk_cpu_dvfs_info, opp_nb); + + if (event == OPP_EVENT_ADJUST_VOLTAGE) { + freq = dev_pm_opp_get_freq(opp); + + mutex_lock(&info->reg_lock); + if (info->current_freq == freq) { + volt = dev_pm_opp_get_voltage(opp); + ret = mtk_cpufreq_set_voltage(info, volt); + if (ret) + dev_err(info->cpu_dev, + "failed to scale voltage: %d\n", ret); + } + mutex_unlock(&info->reg_lock); + } else if (event == OPP_EVENT_DISABLE) { + freq = dev_pm_opp_get_freq(opp); + + /* case of current opp item is disabled */ + if (info->current_freq == freq) { + freq = 1; + new_opp = dev_pm_opp_find_freq_ceil(info->cpu_dev, + &freq); + if (IS_ERR(new_opp)) { + dev_err(info->cpu_dev, + "all opp items are disabled\n"); + ret = PTR_ERR(new_opp); + return notifier_from_errno(ret); + } + + dev_pm_opp_put(new_opp); + policy = cpufreq_cpu_get(info->opp_cpu); + if (policy) { + cpufreq_driver_target(policy, freq / 1000, + CPUFREQ_RELATION_L); + cpufreq_cpu_put(policy); + } + } + } + + return notifier_from_errno(ret); +} + static int mtk_cpu_dvfs_info_init(struct mtk_cpu_dvfs_info *info, int cpu) { struct device *cpu_dev; @@ -357,6 +419,17 @@ static int mtk_cpu_dvfs_info_init(struct mtk_cpu_dvfs_info *info, int cpu) info->intermediate_voltage = dev_pm_opp_get_voltage(opp); dev_pm_opp_put(opp); + mutex_init(&info->reg_lock); + info->current_freq = clk_get_rate(info->cpu_clk); + + info->opp_cpu = cpu; + info->opp_nb.notifier_call = mtk_cpufreq_opp_notifier; + ret = dev_pm_opp_register_notifier(cpu_dev, &info->opp_nb); + if (ret) { + dev_err(cpu_dev, "cpu%d: failed to register opp notifier\n", cpu); + goto out_disable_inter_clock; + } + /* * If SRAM regulator is present, software "voltage tracking" is needed * for this CPU power domain. @@ -421,6 +494,7 @@ static void mtk_cpu_dvfs_info_release(struct mtk_cpu_dvfs_info *info) } dev_pm_opp_of_cpumask_remove_table(&info->cpus); + dev_pm_opp_unregister_notifier(info->cpu_dev, &info->opp_nb); } static int mtk_cpufreq_init(struct cpufreq_policy *policy) -- cgit v1.2.3-59-g8ed1b From 85f5b3c437c927526ab2c4af962dceec08ae58c6 Mon Sep 17 00:00:00 2001 From: Wan Jiabing Date: Tue, 10 May 2022 17:05:31 +0800 Subject: cpufreq: mediatek: Fix potential deadlock problem in mtk_cpufreq_set_target Fix following coccichek error: ./drivers/cpufreq/mediatek-cpufreq.c:199:2-8: preceding lock on line ./drivers/cpufreq/mediatek-cpufreq.c:208:2-8: preceding lock on line mutex_lock is acquired but not released before return. Use 'goto out' to help releasing the mutex_lock. Fixes: c210063b40ac ("cpufreq: mediatek: Add opp notification support") Signed-off-by: Wan Jiabing Reviewed-by: Rex-BC Chen Signed-off-by: Viresh Kumar --- drivers/cpufreq/mediatek-cpufreq.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/cpufreq/mediatek-cpufreq.c b/drivers/cpufreq/mediatek-cpufreq.c index 75bf21ddf61f..4c6d53c99d79 100644 --- a/drivers/cpufreq/mediatek-cpufreq.c +++ b/drivers/cpufreq/mediatek-cpufreq.c @@ -196,7 +196,8 @@ static int mtk_cpufreq_set_target(struct cpufreq_policy *policy, if (pre_vproc < 0) { dev_err(cpu_dev, "invalid Vproc value: %d\n", pre_vproc); - return pre_vproc; + ret = pre_vproc; + goto out; } freq_hz = freq_table[index].frequency * 1000; @@ -205,7 +206,8 @@ static int mtk_cpufreq_set_target(struct cpufreq_policy *policy, if (IS_ERR(opp)) { dev_err(cpu_dev, "cpu%d: failed to find OPP for %ld\n", policy->cpu, freq_hz); - return PTR_ERR(opp); + ret = PTR_ERR(opp); + goto out; } vproc = dev_pm_opp_get_voltage(opp); dev_pm_opp_put(opp); -- cgit v1.2.3-59-g8ed1b From 818c8321d8def50971188b8b33ef2a43ca1e2511 Mon Sep 17 00:00:00 2001 From: Rex-BC Chen Date: Thu, 5 May 2022 19:52:17 +0800 Subject: dt-bindings: cpufreq: mediatek: Add MediaTek CCI property MediaTek Cache Coherent Interconnect (CCI) uses software devfreq module for scaling clock frequency and adjust voltage. The phandle could be linked between CPU and MediaTek CCI for some MediaTek SoCs, like MT8183 and MT8186. The reason we need the link status between cpufreq and MediaTek cci is cpufreq and mediatek cci could share the same regulator in some MediaTek SoCs. Therefore, to prevent the issue of high frequency and low voltage, we need to use this to make sure mediatek cci is ready. Signed-off-by: Rex-BC Chen Reviewed-by: AngeloGioacchino Del Regno Acked-by: Rob Herring Signed-off-by: Viresh Kumar --- Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek.txt | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek.txt b/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek.txt index b8233ec91d3d..e0a4ba599abc 100644 --- a/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek.txt +++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek.txt @@ -20,6 +20,13 @@ Optional properties: Vsram to fit SoC specific needs. When absent, the voltage scaling flow is handled by hardware, hence no software "voltage tracking" is needed. +- mediatek,cci: + Used to confirm the link status between cpufreq and mediatek cci. Because + cpufreq and mediatek cci could share the same regulator in some MediaTek SoCs. + To prevent the issue of high frequency and low voltage, we need to use this + property to make sure mediatek cci is ready. + For details of mediatek cci, please refer to + Documentation/devicetree/bindings/interconnect/mediatek,cci.yaml - #cooling-cells: For details, please refer to Documentation/devicetree/bindings/thermal/thermal-cooling-devices.yaml -- cgit v1.2.3-59-g8ed1b From 0daa47325baee6bb1412498462fd0a0477c32cc6 Mon Sep 17 00:00:00 2001 From: Rex-BC Chen Date: Thu, 5 May 2022 19:52:22 +0800 Subject: cpufreq: mediatek: Link CCI device to CPU In some MediaTek SoCs, like MT8183, CPU and CCI share the same power supplies. Cpufreq needs to check if CCI devfreq exists and wait until CCI devfreq ready before scaling frequency. Before CCI devfreq is ready, we record the voltage when booting to kernel and use the max(cpu target voltage, booting voltage) to prevent cpufreq adjust to the lower voltage which will cause the CCI crash because of high frequency and low voltage. - Add is_ccifreq_ready() to link CCI device to CPI, and CPU will start DVFS when CCI is ready. - Add platform data for MT8183. Signed-off-by: Jia-Wei Chang Signed-off-by: Rex-BC Chen Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Kevin Hilman Signed-off-by: Viresh Kumar --- drivers/cpufreq/mediatek-cpufreq.c | 82 +++++++++++++++++++++++++++++++++++++- 1 file changed, 81 insertions(+), 1 deletion(-) diff --git a/drivers/cpufreq/mediatek-cpufreq.c b/drivers/cpufreq/mediatek-cpufreq.c index 4c6d53c99d79..fe168338d651 100644 --- a/drivers/cpufreq/mediatek-cpufreq.c +++ b/drivers/cpufreq/mediatek-cpufreq.c @@ -22,6 +22,7 @@ struct mtk_cpufreq_platform_data { int proc_max_volt; int sram_min_volt; int sram_max_volt; + bool ccifreq_supported; }; /* @@ -38,6 +39,7 @@ struct mtk_cpufreq_platform_data { struct mtk_cpu_dvfs_info { struct cpumask cpus; struct device *cpu_dev; + struct device *cci_dev; struct regulator *proc_reg; struct regulator *sram_reg; struct clk *cpu_clk; @@ -45,6 +47,7 @@ struct mtk_cpu_dvfs_info { struct list_head list_head; int intermediate_voltage; bool need_voltage_tracking; + int vproc_on_boot; int pre_vproc; /* Avoid race condition for regulators between notify and policy */ struct mutex reg_lock; @@ -53,6 +56,7 @@ struct mtk_cpu_dvfs_info { unsigned long current_freq; const struct mtk_cpufreq_platform_data *soc_data; int vtrack_max; + bool ccifreq_bound; }; static struct platform_device *cpufreq_pdev; @@ -171,6 +175,28 @@ static int mtk_cpufreq_set_voltage(struct mtk_cpu_dvfs_info *info, int vproc) return ret; } +static bool is_ccifreq_ready(struct mtk_cpu_dvfs_info *info) +{ + struct device_link *sup_link; + + if (info->ccifreq_bound) + return true; + + sup_link = device_link_add(info->cpu_dev, info->cci_dev, + DL_FLAG_AUTOREMOVE_CONSUMER); + if (!sup_link) { + dev_err(info->cpu_dev, "cpu%d: sup_link is NULL\n", info->opp_cpu); + return false; + } + + if (sup_link->supplier->links.status != DL_DEV_DRIVER_BOUND) + return false; + + info->ccifreq_bound = true; + + return true; +} + static int mtk_cpufreq_set_target(struct cpufreq_policy *policy, unsigned int index) { @@ -212,6 +238,14 @@ static int mtk_cpufreq_set_target(struct cpufreq_policy *policy, vproc = dev_pm_opp_get_voltage(opp); dev_pm_opp_put(opp); + /* + * If MediaTek cci is supported but is not ready, we will use the value + * of max(target cpu voltage, booting voltage) to prevent high freqeuncy + * low voltage crash. + */ + if (info->soc_data->ccifreq_supported && !is_ccifreq_ready(info)) + vproc = max(vproc, info->vproc_on_boot); + /* * If the new voltage or the intermediate voltage is higher than the * current voltage, scale up voltage first. @@ -333,6 +367,23 @@ static int mtk_cpufreq_opp_notifier(struct notifier_block *nb, return notifier_from_errno(ret); } +static struct device *of_get_cci(struct device *cpu_dev) +{ + struct device_node *np; + struct platform_device *pdev; + + np = of_parse_phandle(cpu_dev->of_node, "mediatek,cci", 0); + if (IS_ERR_OR_NULL(np)) + return NULL; + + pdev = of_find_device_by_node(np); + of_node_put(np); + if (IS_ERR_OR_NULL(pdev)) + return NULL; + + return &pdev->dev; +} + static int mtk_cpu_dvfs_info_init(struct mtk_cpu_dvfs_info *info, int cpu) { struct device *cpu_dev; @@ -347,6 +398,16 @@ static int mtk_cpu_dvfs_info_init(struct mtk_cpu_dvfs_info *info, int cpu) } info->cpu_dev = cpu_dev; + info->ccifreq_bound = false; + if (info->soc_data->ccifreq_supported) { + info->cci_dev = of_get_cci(info->cpu_dev); + if (IS_ERR_OR_NULL(info->cci_dev)) { + ret = PTR_ERR(info->cci_dev); + dev_err(cpu_dev, "cpu%d: failed to get cci device\n", cpu); + return -ENODEV; + } + } + info->cpu_clk = clk_get(cpu_dev, "cpu"); if (IS_ERR(info->cpu_clk)) { ret = PTR_ERR(info->cpu_clk); @@ -410,6 +471,15 @@ static int mtk_cpu_dvfs_info_init(struct mtk_cpu_dvfs_info *info, int cpu) if (ret) goto out_disable_mux_clock; + if (info->soc_data->ccifreq_supported) { + info->vproc_on_boot = regulator_get_voltage(info->proc_reg); + if (info->vproc_on_boot < 0) { + dev_err(info->cpu_dev, + "invalid Vproc value: %d\n", info->vproc_on_boot); + goto out_disable_inter_clock; + } + } + /* Search a safe voltage for intermediate frequency. */ rate = clk_get_rate(info->inter_clk); opp = dev_pm_opp_find_freq_ceil(cpu_dev, &rate); @@ -617,6 +687,16 @@ static const struct mtk_cpufreq_platform_data mt2701_platform_data = { .proc_max_volt = 1150000, .sram_min_volt = 0, .sram_max_volt = 1150000, + .ccifreq_supported = false, +}; + +static const struct mtk_cpufreq_platform_data mt8183_platform_data = { + .min_volt_shift = 100000, + .max_volt_shift = 200000, + .proc_max_volt = 1150000, + .sram_min_volt = 0, + .sram_max_volt = 1150000, + .ccifreq_supported = true, }; /* List of machines supported by this driver */ @@ -629,7 +709,7 @@ static const struct of_device_id mtk_cpufreq_machines[] __initconst = { { .compatible = "mediatek,mt817x", .data = &mt2701_platform_data }, { .compatible = "mediatek,mt8173", .data = &mt2701_platform_data }, { .compatible = "mediatek,mt8176", .data = &mt2701_platform_data }, - { .compatible = "mediatek,mt8183", .data = &mt2701_platform_data }, + { .compatible = "mediatek,mt8183", .data = &mt8183_platform_data }, { .compatible = "mediatek,mt8365", .data = &mt2701_platform_data }, { .compatible = "mediatek,mt8516", .data = &mt2701_platform_data }, { } -- cgit v1.2.3-59-g8ed1b From 39b360102f3ac6b12cafac9db25762071eb0418c Mon Sep 17 00:00:00 2001 From: Jia-Wei Chang Date: Thu, 5 May 2022 19:52:23 +0800 Subject: cpufreq: mediatek: Add support for MT8186 The platform data of MT8186 is different from previous MediaTek SoCs, so we add a new compatible and platform data for it. Signed-off-by: Jia-Wei Chang Signed-off-by: Rex-BC Chen Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Viresh Kumar --- drivers/cpufreq/mediatek-cpufreq.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/cpufreq/mediatek-cpufreq.c b/drivers/cpufreq/mediatek-cpufreq.c index fe168338d651..37a1eb20f5ba 100644 --- a/drivers/cpufreq/mediatek-cpufreq.c +++ b/drivers/cpufreq/mediatek-cpufreq.c @@ -699,6 +699,15 @@ static const struct mtk_cpufreq_platform_data mt8183_platform_data = { .ccifreq_supported = true, }; +static const struct mtk_cpufreq_platform_data mt8186_platform_data = { + .min_volt_shift = 100000, + .max_volt_shift = 250000, + .proc_max_volt = 1118750, + .sram_min_volt = 850000, + .sram_max_volt = 1118750, + .ccifreq_supported = true, +}; + /* List of machines supported by this driver */ static const struct of_device_id mtk_cpufreq_machines[] __initconst = { { .compatible = "mediatek,mt2701", .data = &mt2701_platform_data }, @@ -710,6 +719,7 @@ static const struct of_device_id mtk_cpufreq_machines[] __initconst = { { .compatible = "mediatek,mt8173", .data = &mt2701_platform_data }, { .compatible = "mediatek,mt8176", .data = &mt2701_platform_data }, { .compatible = "mediatek,mt8183", .data = &mt8183_platform_data }, + { .compatible = "mediatek,mt8186", .data = &mt8186_platform_data }, { .compatible = "mediatek,mt8365", .data = &mt2701_platform_data }, { .compatible = "mediatek,mt8516", .data = &mt2701_platform_data }, { } -- cgit v1.2.3-59-g8ed1b