From b873c122fef06905f58399a07121a09bfcf4289d Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Fri, 10 Jan 2020 09:14:11 +0100 Subject: dt-bindings: Convert Faraday FTIDE010 to DT schema This uses the new pata-common.yaml schema to convert the Faraday FTIDE010 to DT schema. Cc: Rob Herring Cc: devicetree@vger.kernel.org Signed-off-by: Linus Walleij Signed-off-by: Rob Herring --- .../devicetree/bindings/ata/faraday,ftide010.txt | 38 --------- .../devicetree/bindings/ata/faraday,ftide010.yaml | 89 ++++++++++++++++++++++ 2 files changed, 89 insertions(+), 38 deletions(-) delete mode 100644 Documentation/devicetree/bindings/ata/faraday,ftide010.txt create mode 100644 Documentation/devicetree/bindings/ata/faraday,ftide010.yaml diff --git a/Documentation/devicetree/bindings/ata/faraday,ftide010.txt b/Documentation/devicetree/bindings/ata/faraday,ftide010.txt deleted file mode 100644 index a0c64a29104d..000000000000 --- a/Documentation/devicetree/bindings/ata/faraday,ftide010.txt +++ /dev/null @@ -1,38 +0,0 @@ -* Faraday Technology FTIDE010 PATA controller - -This controller is the first Faraday IDE interface block, used in the -StorLink SL2312 and SL3516, later known as the Cortina Systems Gemini -platform. The controller can do PIO modes 0 through 4, Multi-word DMA -(MWDM)modes 0 through 2 and Ultra DMA modes 0 through 6. - -On the Gemini platform, this PATA block is accompanied by a PATA to -SATA bridge in order to support SATA. This is why a phandle to that -controller is compulsory on that platform. - -The timing properties are unique per-SoC, not per-board. - -Required properties: -- compatible: should be one of - "cortina,gemini-pata", "faraday,ftide010" - "faraday,ftide010" -- interrupts: interrupt for the block -- reg: registers and size for the block - -Optional properties: -- clocks: a SoC clock running the peripheral. -- clock-names: should be set to "PCLK" for the peripheral clock. - -Required properties for "cortina,gemini-pata" compatible: -- sata: a phande to the Gemini PATA to SATA bridge, see - cortina,gemini-sata-bridge.txt for details. - -Example: - -ata@63000000 { - compatible = "cortina,gemini-pata", "faraday,ftide010"; - reg = <0x63000000 0x100>; - interrupts = <4 IRQ_TYPE_EDGE_RISING>; - clocks = <&gcc GEMINI_CLK_GATE_IDE>; - clock-names = "PCLK"; - sata = <&sata>; -}; diff --git a/Documentation/devicetree/bindings/ata/faraday,ftide010.yaml b/Documentation/devicetree/bindings/ata/faraday,ftide010.yaml new file mode 100644 index 000000000000..bfc6357476fd --- /dev/null +++ b/Documentation/devicetree/bindings/ata/faraday,ftide010.yaml @@ -0,0 +1,89 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/ata/faraday,ftide010.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Faraday Technology FTIDE010 PATA controller + +maintainers: + - Linus Walleij + +description: | + This controller is the first Faraday IDE interface block, used in the + StorLink SL3512 and SL3516, later known as the Cortina Systems Gemini + platform. The controller can do PIO modes 0 through 4, Multi-word DMA + (MWDM) modes 0 through 2 and Ultra DMA modes 0 through 6. + + On the Gemini platform, this PATA block is accompanied by a PATA to + SATA bridge in order to support SATA. This is why a phandle to that + controller is compulsory on that platform. + + The timing properties are unique per-SoC, not per-board. + +properties: + compatible: + oneOf: + - const: faraday,ftide010 + - items: + - const: cortina,gemini-pata + - const: faraday,ftide010 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + minItems: 1 + + clock-names: + const: PCLK + + sata: + description: + phandle to the Gemini PATA to SATA bridge, if available + $ref: /schemas/types.yaml#/definitions/phandle + +required: + - compatible + - reg + - interrupts + +allOf: + - $ref: pata-common.yaml# + + - if: + properties: + compatible: + contains: + const: cortina,gemini-pata + + then: + required: + - sata + +examples: + - | + #include + #include + + ide@63000000 { + compatible = "cortina,gemini-pata", "faraday,ftide010"; + reg = <0x63000000 0x100>; + interrupts = <4 IRQ_TYPE_EDGE_RISING>; + clocks = <&gcc GEMINI_CLK_GATE_IDE>; + clock-names = "PCLK"; + sata = <&sata>; + #address-cells = <1>; + #size-cells = <0>; + ide-port@0 { + reg = <0>; + }; + ide-port@1 { + reg = <1>; + }; + }; + +... -- cgit v1.2.3-59-g8ed1b