From 87a85b683de3e833cf022c5d1502e0ed338473d7 Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Fri, 10 Jan 2014 11:20:18 +0200 Subject: ARM: DRA7XX/AM43XX: randconfig fixes DRA7XX and AM43XX were missing common clock code from the Makefile, which causes build breakage in DRA7XX / AM43XX only builds once clock support for these SoCs is added. Add the missing entries to the Makefile as preparation of this. Signed-off-by: Tero Kristo Acked-by: Tony Lindgren Signed-off-by: Mike Turquette --- arch/arm/mach-omap2/Makefile | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index adcef406ff0a..8ad6fb0d4ac9 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -192,6 +192,9 @@ obj-$(CONFIG_SOC_AM33XX) += $(clock-common) dpll3xxx.o obj-$(CONFIG_SOC_AM33XX) += cclock33xx_data.o obj-$(CONFIG_SOC_OMAP5) += $(clock-common) obj-$(CONFIG_SOC_OMAP5) += dpll3xxx.o dpll44xx.o +obj-$(CONFIG_SOC_DRA7XX) += $(clock-common) +obj-$(CONFIG_SOC_DRA7XX) += dpll3xxx.o dpll44xx.o +obj-$(CONFIG_SOC_AM43XX) += $(clock-common) dpll3xxx.o # OMAP2 clock rate set data (old "OPP" data) obj-$(CONFIG_SOC_OMAP2420) += opp2420_data.o -- cgit v1.2.3-59-g8ed1b From 68b9f608679424ea08e6fbead5dc82599bfe667f Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Fri, 10 Jan 2014 11:25:28 +0200 Subject: ARM: DRA7XX: Add support for DRA7XX only build SOC_DRA7XX was under wrong menu within Kconfig file, which prevented DRA7XX only build. Fixed the kconfig options for this SoC as we are there. voltage.c needs to be added to the DRA7XX build also, otherwise DRA7XX only build will fail. Signed-off-by: Tero Kristo Acked-by: Tony Lindgren Signed-off-by: Mike Turquette --- arch/arm/mach-omap2/Kconfig | 18 ++++++++++-------- arch/arm/mach-omap2/Makefile | 1 + 2 files changed, 11 insertions(+), 8 deletions(-) diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index dc21df166161..e65948a9aa0e 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig @@ -76,6 +76,16 @@ config SOC_AM43XX select ARM_GIC select MACH_OMAP_GENERIC +config SOC_DRA7XX + bool "TI DRA7XX" + depends on ARCH_MULTI_V7 + select ARCH_OMAP2PLUS + select ARM_CPU_SUSPEND if PM + select ARM_GIC + select CPU_V7 + select HAVE_SMP + select HAVE_ARM_ARCH_TIMER + config ARCH_OMAP2PLUS bool select ARCH_HAS_BANDGAP @@ -128,14 +138,6 @@ config SOC_HAS_REALTIME_COUNTER depends on SOC_OMAP5 || SOC_DRA7XX default y -config SOC_DRA7XX - bool "TI DRA7XX" - select ARM_ARCH_TIMER - select CPU_V7 - select ARM_GIC - select HAVE_SMP - select COMMON_CLK - comment "OMAP Core Type" depends on ARCH_OMAP2 diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index 8ad6fb0d4ac9..3d9c121305f4 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -132,6 +132,7 @@ obj-$(CONFIG_SOC_AM33XX) += $(voltagedomain-common) obj-$(CONFIG_SOC_AM43XX) += $(voltagedomain-common) obj-$(CONFIG_SOC_OMAP5) += $(voltagedomain-common) obj-$(CONFIG_SOC_OMAP5) += voltagedomains54xx_data.o +obj-$(CONFIG_SOC_DRA7XX) += $(voltagedomain-common) # OMAP powerdomain framework powerdomain-common += powerdomain.o powerdomain-common.o -- cgit v1.2.3-59-g8ed1b From a8aceccb4d5db0acb476b74051525fb26f57f8ae Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Thu, 18 Jul 2013 11:52:33 +0300 Subject: CLK: TI: add DT alias clock registration mechanism Some devices require their clocks to be available with a specific dev-id con-id mapping. With DT, the clocks can be found by default only with their name, or alternatively through the device node of the consumer. With drivers, that don't support DT fully yet, add mechanism to register specific clock names. Signed-off-by: Tero Kristo Acked-by: Tony Lindgren Signed-off-by: Mike Turquette --- drivers/clk/Makefile | 1 + drivers/clk/ti/Makefile | 3 +++ drivers/clk/ti/clk.c | 55 +++++++++++++++++++++++++++++++++++++++++++++++++ include/linux/clk/ti.h | 42 +++++++++++++++++++++++++++++++++++++ 4 files changed, 101 insertions(+) create mode 100644 drivers/clk/ti/Makefile create mode 100644 drivers/clk/ti/clk.c create mode 100644 include/linux/clk/ti.h diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index 972da894baa1..13c1e91a86bc 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -38,6 +38,7 @@ obj-$(CONFIG_PLAT_SAMSUNG) += samsung/ obj-$(CONFIG_COMMON_CLK_XGENE) += clk-xgene.o obj-$(CONFIG_COMMON_CLK_KEYSTONE) += keystone/ obj-$(CONFIG_ARCH_SHMOBILE_MULTI) += shmobile/ +obj-$(CONFIG_ARCH_OMAP2PLUS) += ti/ obj-$(CONFIG_X86) += x86/ diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile new file mode 100644 index 000000000000..1825f7f4bdc0 --- /dev/null +++ b/drivers/clk/ti/Makefile @@ -0,0 +1,3 @@ +ifneq ($(CONFIG_OF),) +obj-y += clk.o +endif diff --git a/drivers/clk/ti/clk.c b/drivers/clk/ti/clk.c new file mode 100644 index 000000000000..ef1a7cdecfd9 --- /dev/null +++ b/drivers/clk/ti/clk.c @@ -0,0 +1,55 @@ +/* + * TI clock support + * + * Copyright (C) 2013 Texas Instruments, Inc. + * + * Tero Kristo + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include + +#undef pr_fmt +#define pr_fmt(fmt) "%s: " fmt, __func__ + +/** + * ti_dt_clocks_register - register DT alias clocks during boot + * @oclks: list of clocks to register + * + * Register alias or non-standard DT clock entries during boot. By + * default, DT clocks are found based on their node name. If any + * additional con-id / dev-id -> clock mapping is required, use this + * function to list these. + */ +void __init ti_dt_clocks_register(struct ti_dt_clk oclks[]) +{ + struct ti_dt_clk *c; + struct device_node *node; + struct clk *clk; + struct of_phandle_args clkspec; + + for (c = oclks; c->node_name != NULL; c++) { + node = of_find_node_by_name(NULL, c->node_name); + clkspec.np = node; + clk = of_clk_get_from_provider(&clkspec); + + if (!IS_ERR(clk)) { + c->lk.clk = clk; + clkdev_add(&c->lk); + } else { + pr_warn("failed to lookup clock node %s\n", + c->node_name); + } + } +} diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h new file mode 100644 index 000000000000..df94c243205e --- /dev/null +++ b/include/linux/clk/ti.h @@ -0,0 +1,42 @@ +/* + * TI clock drivers support + * + * Copyright (C) 2013 Texas Instruments, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#ifndef __LINUX_CLK_TI_H__ +#define __LINUX_CLK_TI_H__ + +#include + +/** + * struct ti_dt_clk - OMAP DT clock alias declarations + * @lk: clock lookup definition + * @node_name: clock DT node to map to + */ +struct ti_dt_clk { + struct clk_lookup lk; + char *node_name; +}; + +#define DT_CLK(dev, con, name) \ + { \ + .lk = { \ + .dev_id = dev, \ + .con_id = con, \ + }, \ + .node_name = name, \ + } + + +void ti_dt_clocks_register(struct ti_dt_clk *oclks); + +#endif -- cgit v1.2.3-59-g8ed1b From 819b4861c18d602463cfe815041d11fd81002654 Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Tue, 22 Oct 2013 11:39:36 +0300 Subject: CLK: ti: add init support for clock IP blocks ti_dt_clk_init_provider() can now be used to initialize the contents of a single clock IP block. This parses all the clocks under the IP block and calls the corresponding init function for them. This patch also introduces a helper function for the TI clock drivers to get register info from DT and append the master IP info to this. Signed-off-by: Tero Kristo Acked-by: Tony Lindgren Signed-off-by: Mike Turquette --- drivers/clk/clk.c | 4 +- drivers/clk/ti/clk.c | 112 +++++++++++++++++++++++++++++++++++++++++++ include/linux/clk-provider.h | 2 + include/linux/clk/ti.h | 35 ++++++++++++++ 4 files changed, 150 insertions(+), 3 deletions(-) diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c index 2b38dc99063f..077106732550 100644 --- a/drivers/clk/clk.c +++ b/drivers/clk/clk.c @@ -2373,8 +2373,6 @@ struct of_clk_provider { void *data; }; -extern struct of_device_id __clk_of_table[]; - static const struct of_device_id __clk_of_table_sentinel __used __section(__clk_of_table_end); @@ -2534,7 +2532,7 @@ void __init of_clk_init(const struct of_device_id *matches) struct device_node *np; if (!matches) - matches = __clk_of_table; + matches = &__clk_of_table; for_each_matching_node_and_match(np, matches, &match) { of_clk_init_cb_t clk_init_cb = match->data; diff --git a/drivers/clk/ti/clk.c b/drivers/clk/ti/clk.c index ef1a7cdecfd9..b1a6f7144f3f 100644 --- a/drivers/clk/ti/clk.c +++ b/drivers/clk/ti/clk.c @@ -19,10 +19,15 @@ #include #include #include +#include +#include #undef pr_fmt #define pr_fmt(fmt) "%s: " fmt, __func__ +static int ti_dt_clk_memmap_index; +struct ti_clk_ll_ops *ti_clk_ll_ops; + /** * ti_dt_clocks_register - register DT alias clocks during boot * @oclks: list of clocks to register @@ -53,3 +58,110 @@ void __init ti_dt_clocks_register(struct ti_dt_clk oclks[]) } } } + +struct clk_init_item { + struct device_node *node; + struct clk_hw *hw; + ti_of_clk_init_cb_t func; + struct list_head link; +}; + +static LIST_HEAD(retry_list); + +/** + * ti_clk_retry_init - retries a failed clock init at later phase + * @node: device not for the clock + * @hw: partially initialized clk_hw struct for the clock + * @func: init function to be called for the clock + * + * Adds a failed clock init to the retry list. The retry list is parsed + * once all the other clocks have been initialized. + */ +int __init ti_clk_retry_init(struct device_node *node, struct clk_hw *hw, + ti_of_clk_init_cb_t func) +{ + struct clk_init_item *retry; + + pr_debug("%s: adding to retry list...\n", node->name); + retry = kzalloc(sizeof(*retry), GFP_KERNEL); + if (!retry) + return -ENOMEM; + + retry->node = node; + retry->func = func; + retry->hw = hw; + list_add(&retry->link, &retry_list); + + return 0; +} + +/** + * ti_clk_get_reg_addr - get register address for a clock register + * @node: device node for the clock + * @index: register index from the clock node + * + * Builds clock register address from device tree information. This + * is a struct of type clk_omap_reg. + */ +void __iomem *ti_clk_get_reg_addr(struct device_node *node, int index) +{ + struct clk_omap_reg *reg; + u32 val; + u32 tmp; + + reg = (struct clk_omap_reg *)&tmp; + reg->index = ti_dt_clk_memmap_index; + + if (of_property_read_u32_index(node, "reg", index, &val)) { + pr_err("%s must have reg[%d]!\n", node->name, index); + return NULL; + } + + reg->offset = val; + + return (void __iomem *)tmp; +} + +/** + * ti_dt_clk_init_provider - init master clock provider + * @parent: master node + * @index: internal index for clk_reg_ops + * + * Initializes a master clock IP block and its child clock nodes. + * Regmap is provided for accessing the register space for the + * IP block and all the clocks under it. + */ +void ti_dt_clk_init_provider(struct device_node *parent, int index) +{ + const struct of_device_id *match; + struct device_node *np; + struct device_node *clocks; + of_clk_init_cb_t clk_init_cb; + struct clk_init_item *retry; + struct clk_init_item *tmp; + + ti_dt_clk_memmap_index = index; + + /* get clocks for this parent */ + clocks = of_get_child_by_name(parent, "clocks"); + if (!clocks) { + pr_err("%s missing 'clocks' child node.\n", parent->name); + return; + } + + for_each_child_of_node(clocks, np) { + match = of_match_node(&__clk_of_table, np); + if (!match) + continue; + clk_init_cb = (of_clk_init_cb_t)match->data; + pr_debug("%s: initializing: %s\n", __func__, np->name); + clk_init_cb(np); + } + + list_for_each_entry_safe(retry, tmp, &retry_list, link) { + pr_debug("retry-init: %s\n", retry->node->name); + retry->func(retry->hw, retry->node); + list_del(&retry->link); + kfree(retry); + } +} diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index 999b28ba38f7..448b2294820f 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -488,6 +488,8 @@ struct clk_onecell_data { unsigned int clk_num; }; +extern struct of_device_id __clk_of_table; + #define CLK_OF_DECLARE(name, compat, fn) \ static const struct of_device_id __clk_of_table_##name \ __used __section(__clk_of_table) \ diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h index df94c243205e..c6eded5eea76 100644 --- a/include/linux/clk/ti.h +++ b/include/linux/clk/ti.h @@ -36,7 +36,42 @@ struct ti_dt_clk { .node_name = name, \ } +/* Maximum number of clock memmaps */ +#define CLK_MAX_MEMMAPS 4 +typedef void (*ti_of_clk_init_cb_t)(struct clk_hw *, struct device_node *); + +/** + * struct clk_omap_reg - OMAP register declaration + * @offset: offset from the master IP module base address + * @index: index of the master IP module + */ +struct clk_omap_reg { + u16 offset; + u16 index; +}; + +/** + * struct ti_clk_ll_ops - low-level register access ops for a clock + * @clk_readl: pointer to register read function + * @clk_writel: pointer to register write function + * + * Low-level register access ops are generally used by the basic clock types + * (clk-gate, clk-mux, clk-divider etc.) to provide support for various + * low-level hardware interfaces (direct MMIO, regmap etc.), but can also be + * used by other hardware-specific clock drivers if needed. + */ +struct ti_clk_ll_ops { + u32 (*clk_readl)(void __iomem *reg); + void (*clk_writel)(u32 val, void __iomem *reg); +}; + +extern struct ti_clk_ll_ops *ti_clk_ll_ops; + +void __iomem *ti_clk_get_reg_addr(struct device_node *node, int index); void ti_dt_clocks_register(struct ti_dt_clk *oclks); +void ti_dt_clk_init_provider(struct device_node *np, int index); +int ti_clk_retry_init(struct device_node *node, struct clk_hw *hw, + ti_of_clk_init_cb_t func); #endif -- cgit v1.2.3-59-g8ed1b From f38b0dd63f0d0cca753bf0997eefdfb23dcc9518 Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Wed, 12 Jun 2013 16:04:34 +0300 Subject: CLK: TI: Add DPLL clock support The OMAP clock driver now supports DPLL clock type. This patch also adds support for DT DPLL nodes. Signed-off-by: Tero Kristo Acked-by: Tony Lindgren Signed-off-by: Mike Turquette --- .../devicetree/bindings/clock/ti/dpll.txt | 75 +++ arch/arm/mach-omap2/clock.h | 164 +----- arch/arm/mach-omap2/clock3xxx.h | 2 - drivers/clk/ti/Makefile | 1 + drivers/clk/ti/dpll.c | 558 +++++++++++++++++++++ include/linux/clk/ti.h | 172 +++++++ 6 files changed, 807 insertions(+), 165 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/ti/dpll.txt create mode 100644 drivers/clk/ti/dpll.c diff --git a/Documentation/devicetree/bindings/clock/ti/dpll.txt b/Documentation/devicetree/bindings/clock/ti/dpll.txt new file mode 100644 index 000000000000..30bfdb7c9f18 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/ti/dpll.txt @@ -0,0 +1,75 @@ +Binding for Texas Instruments DPLL clock. + +Binding status: Unstable - ABI compatibility may be broken in the future + +This binding uses the common clock binding[1]. It assumes a +register-mapped DPLL with usually two selectable input clocks +(reference clock and bypass clock), with digital phase locked +loop logic for multiplying the input clock to a desired output +clock. This clock also typically supports different operation +modes (locked, low power stop etc.) This binding has several +sub-types, which effectively result in slightly different setup +for the actual DPLL clock. + +[1] Documentation/devicetree/bindings/clock/clock-bindings.txt + +Required properties: +- compatible : shall be one of: + "ti,omap3-dpll-clock", + "ti,omap3-dpll-core-clock", + "ti,omap3-dpll-per-clock", + "ti,omap3-dpll-per-j-type-clock", + "ti,omap4-dpll-clock", + "ti,omap4-dpll-x2-clock", + "ti,omap4-dpll-core-clock", + "ti,omap4-dpll-m4xen-clock", + "ti,omap4-dpll-j-type-clock", + "ti,am3-dpll-no-gate-clock", + "ti,am3-dpll-j-type-clock", + "ti,am3-dpll-no-gate-j-type-clock", + "ti,am3-dpll-clock", + "ti,am3-dpll-core-clock", + "ti,am3-dpll-x2-clock", + +- #clock-cells : from common clock binding; shall be set to 0. +- clocks : link phandles of parent clocks, first entry lists reference clock + and second entry bypass clock +- reg : offsets for the register set for controlling the DPLL. + Registers are listed in following order: + "control" - contains the control register base address + "idlest" - contains the idle status register base address + "mult-div1" - contains the multiplier / divider register base address + "autoidle" - contains the autoidle register base address (optional) + ti,am3-* dpll types do not have autoidle register + +Optional properties: +- DPLL mode setting - defining any one or more of the following overrides + default setting. + - ti,low-power-stop : DPLL supports low power stop mode, gating output + - ti,low-power-bypass : DPLL output matches rate of parent bypass clock + - ti,lock : DPLL locks in programmed rate + +Examples: + dpll_core_ck: dpll_core_ck@44e00490 { + #clock-cells = <0>; + compatible = "ti,omap4-dpll-core-clock"; + clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; + reg = <0x490>, <0x45c>, <0x488>, <0x468>; + }; + + dpll2_ck: dpll2_ck@48004004 { + #clock-cells = <0>; + compatible = "ti,omap3-dpll-clock"; + clocks = <&sys_ck>, <&dpll2_fck>; + ti,low-power-stop; + ti,low-power-bypass; + ti,lock; + reg = <0x4>, <0x24>, <0x34>, <0x40>; + }; + + dpll_core_ck: dpll_core_ck@44e00490 { + #clock-cells = <0>; + compatible = "ti,am3-dpll-core-clock"; + clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; + reg = <0x90>, <0x5c>, <0x68>; + }; diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h index 82916cc82c92..b345f3ea8617 100644 --- a/arch/arm/mach-omap2/clock.h +++ b/arch/arm/mach-omap2/clock.h @@ -21,6 +21,7 @@ #include #include +#include struct omap_clk { u16 cpu; @@ -37,7 +38,6 @@ struct omap_clk { } struct clockdomain; -#define to_clk_hw_omap(_hw) container_of(_hw, struct clk_hw_omap, hw) #define DEFINE_STRUCT_CLK(_name, _parent_array_name, _clkops_name) \ static struct clk _name = { \ @@ -178,141 +178,6 @@ struct clksel { const struct clksel_rate *rates; }; -/** - * struct dpll_data - DPLL registers and integration data - * @mult_div1_reg: register containing the DPLL M and N bitfields - * @mult_mask: mask of the DPLL M bitfield in @mult_div1_reg - * @div1_mask: mask of the DPLL N bitfield in @mult_div1_reg - * @clk_bypass: struct clk pointer to the clock's bypass clock input - * @clk_ref: struct clk pointer to the clock's reference clock input - * @control_reg: register containing the DPLL mode bitfield - * @enable_mask: mask of the DPLL mode bitfield in @control_reg - * @last_rounded_rate: cache of the last rate result of omap2_dpll_round_rate() - * @last_rounded_m: cache of the last M result of omap2_dpll_round_rate() - * @last_rounded_m4xen: cache of the last M4X result of - * omap4_dpll_regm4xen_round_rate() - * @last_rounded_lpmode: cache of the last lpmode result of - * omap4_dpll_lpmode_recalc() - * @max_multiplier: maximum valid non-bypass multiplier value (actual) - * @last_rounded_n: cache of the last N result of omap2_dpll_round_rate() - * @min_divider: minimum valid non-bypass divider value (actual) - * @max_divider: maximum valid non-bypass divider value (actual) - * @modes: possible values of @enable_mask - * @autoidle_reg: register containing the DPLL autoidle mode bitfield - * @idlest_reg: register containing the DPLL idle status bitfield - * @autoidle_mask: mask of the DPLL autoidle mode bitfield in @autoidle_reg - * @freqsel_mask: mask of the DPLL jitter correction bitfield in @control_reg - * @idlest_mask: mask of the DPLL idle status bitfield in @idlest_reg - * @lpmode_mask: mask of the DPLL low-power mode bitfield in @control_reg - * @m4xen_mask: mask of the DPLL M4X multiplier bitfield in @control_reg - * @auto_recal_bit: bitshift of the driftguard enable bit in @control_reg - * @recal_en_bit: bitshift of the PRM_IRQENABLE_* bit for recalibration IRQs - * @recal_st_bit: bitshift of the PRM_IRQSTATUS_* bit for recalibration IRQs - * @flags: DPLL type/features (see below) - * - * Possible values for @flags: - * DPLL_J_TYPE: "J-type DPLL" (only some 36xx, 4xxx DPLLs) - * - * @freqsel_mask is only used on the OMAP34xx family and AM35xx. - * - * XXX Some DPLLs have multiple bypass inputs, so it's not technically - * correct to only have one @clk_bypass pointer. - * - * XXX The runtime-variable fields (@last_rounded_rate, @last_rounded_m, - * @last_rounded_n) should be separated from the runtime-fixed fields - * and placed into a different structure, so that the runtime-fixed data - * can be placed into read-only space. - */ -struct dpll_data { - void __iomem *mult_div1_reg; - u32 mult_mask; - u32 div1_mask; - struct clk *clk_bypass; - struct clk *clk_ref; - void __iomem *control_reg; - u32 enable_mask; - unsigned long last_rounded_rate; - u16 last_rounded_m; - u8 last_rounded_m4xen; - u8 last_rounded_lpmode; - u16 max_multiplier; - u8 last_rounded_n; - u8 min_divider; - u16 max_divider; - u8 modes; - void __iomem *autoidle_reg; - void __iomem *idlest_reg; - u32 autoidle_mask; - u32 freqsel_mask; - u32 idlest_mask; - u32 dco_mask; - u32 sddiv_mask; - u32 lpmode_mask; - u32 m4xen_mask; - u8 auto_recal_bit; - u8 recal_en_bit; - u8 recal_st_bit; - u8 flags; -}; - -/* - * struct clk.flags possibilities - * - * XXX document the rest of the clock flags here - * - * CLOCK_CLKOUTX2: (OMAP4 only) DPLL CLKOUT and CLKOUTX2 GATE_CTRL - * bits share the same register. This flag allows the - * omap4_dpllmx*() code to determine which GATE_CTRL bit field - * should be used. This is a temporary solution - a better approach - * would be to associate clock type-specific data with the clock, - * similar to the struct dpll_data approach. - */ -#define ENABLE_REG_32BIT (1 << 0) /* Use 32-bit access */ -#define CLOCK_IDLE_CONTROL (1 << 1) -#define CLOCK_NO_IDLE_PARENT (1 << 2) -#define ENABLE_ON_INIT (1 << 3) /* Enable upon framework init */ -#define INVERT_ENABLE (1 << 4) /* 0 enables, 1 disables */ -#define CLOCK_CLKOUTX2 (1 << 5) - -/** - * struct clk_hw_omap - OMAP struct clk - * @node: list_head connecting this clock into the full clock list - * @enable_reg: register to write to enable the clock (see @enable_bit) - * @enable_bit: bitshift to write to enable/disable the clock (see @enable_reg) - * @flags: see "struct clk.flags possibilities" above - * @clksel_reg: for clksel clks, register va containing src/divisor select - * @clksel_mask: bitmask in @clksel_reg for the src/divisor selector - * @clksel: for clksel clks, pointer to struct clksel for this clock - * @dpll_data: for DPLLs, pointer to struct dpll_data for this clock - * @clkdm_name: clockdomain name that this clock is contained in - * @clkdm: pointer to struct clockdomain, resolved from @clkdm_name at runtime - * @rate_offset: bitshift for rate selection bitfield (OMAP1 only) - * @src_offset: bitshift for source selection bitfield (OMAP1 only) - * - * XXX @rate_offset, @src_offset should probably be removed and OMAP1 - * clock code converted to use clksel. - * - */ - -struct clk_hw_omap_ops; - -struct clk_hw_omap { - struct clk_hw hw; - struct list_head node; - unsigned long fixed_rate; - u8 fixed_div; - void __iomem *enable_reg; - u8 enable_bit; - u8 flags; - void __iomem *clksel_reg; - u32 clksel_mask; - const struct clksel *clksel; - struct dpll_data *dpll_data; - const char *clkdm_name; - struct clockdomain *clkdm; - const struct clk_hw_omap_ops *ops; -}; - struct clk_hw_omap_ops { void (*find_idlest)(struct clk_hw_omap *oclk, void __iomem **idlest_reg, @@ -348,36 +213,13 @@ unsigned long omap_fixed_divisor_recalc(struct clk_hw *hw, #define OMAP4XXX_EN_DPLL_FRBYPASS 0x6 #define OMAP4XXX_EN_DPLL_LOCKED 0x7 -/* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */ -#define DPLL_LOW_POWER_STOP 0x1 -#define DPLL_LOW_POWER_BYPASS 0x5 -#define DPLL_LOCKED 0x7 - -/* DPLL Type and DCO Selection Flags */ -#define DPLL_J_TYPE 0x1 - -long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate, - unsigned long *parent_rate); -unsigned long omap3_dpll_recalc(struct clk_hw *hw, unsigned long parent_rate); -int omap3_noncore_dpll_enable(struct clk_hw *hw); -void omap3_noncore_dpll_disable(struct clk_hw *hw); -int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate, - unsigned long parent_rate); u32 omap3_dpll_autoidle_read(struct clk_hw_omap *clk); void omap3_dpll_allow_idle(struct clk_hw_omap *clk); void omap3_dpll_deny_idle(struct clk_hw_omap *clk); -unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw, - unsigned long parent_rate); int omap4_dpllmx_gatectrl_read(struct clk_hw_omap *clk); void omap4_dpllmx_allow_gatectrl(struct clk_hw_omap *clk); void omap4_dpllmx_deny_gatectrl(struct clk_hw_omap *clk); -unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw, - unsigned long parent_rate); -long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw, - unsigned long target_rate, - unsigned long *parent_rate); -void omap2_init_clk_clkdm(struct clk_hw *clk); void __init omap2_clk_disable_clkdm_control(void); /* clkt_clksel.c public functions */ @@ -396,7 +238,6 @@ int omap2_clksel_set_parent(struct clk_hw *hw, u8 field_val); extern void omap2_clkt_iclk_allow_idle(struct clk_hw_omap *clk); extern void omap2_clkt_iclk_deny_idle(struct clk_hw_omap *clk); -u8 omap2_init_dpll_parent(struct clk_hw *hw); unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk); int omap2_dflt_clk_enable(struct clk_hw *hw); @@ -408,7 +249,6 @@ void omap2_clk_dflt_find_companion(struct clk_hw_omap *clk, void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk, void __iomem **idlest_reg, u8 *idlest_bit, u8 *idlest_val); -void omap2_init_clk_hw_omap_clocks(struct clk *clk); int omap2_clk_enable_autoidle_all(void); int omap2_clk_disable_autoidle_all(void); int omap2_clk_allow_idle(struct clk *clk); @@ -433,10 +273,8 @@ extern const struct clksel_rate gfx_l3_rates[]; extern const struct clksel_rate dsp_ick_rates[]; extern struct clk dummy_ck; -extern const struct clk_hw_omap_ops clkhwops_omap3_dpll; extern const struct clk_hw_omap_ops clkhwops_iclk_wait; extern const struct clk_hw_omap_ops clkhwops_wait; -extern const struct clk_hw_omap_ops clkhwops_omap4_dpllmx; extern const struct clk_hw_omap_ops clkhwops_iclk; extern const struct clk_hw_omap_ops clkhwops_omap3430es2_ssi_wait; extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_ssi_wait; diff --git a/arch/arm/mach-omap2/clock3xxx.h b/arch/arm/mach-omap2/clock3xxx.h index 8cd4b0a882ae..dab90e281aeb 100644 --- a/arch/arm/mach-omap2/clock3xxx.h +++ b/arch/arm/mach-omap2/clock3xxx.h @@ -9,8 +9,6 @@ #define __ARCH_ARM_MACH_OMAP2_CLOCK3XXX_H int omap3xxx_clk_init(void); -int omap3_dpll4_set_rate(struct clk_hw *clk, unsigned long rate, - unsigned long parent_rate); int omap3_core_dpll_m2_set_rate(struct clk_hw *clk, unsigned long rate, unsigned long parent_rate); void omap3_clk_lock_dpll5(void); diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile index 1825f7f4bdc0..3dbb78dc9fca 100644 --- a/drivers/clk/ti/Makefile +++ b/drivers/clk/ti/Makefile @@ -1,3 +1,4 @@ ifneq ($(CONFIG_OF),) obj-y += clk.o +clk-common = dpll.o endif diff --git a/drivers/clk/ti/dpll.c b/drivers/clk/ti/dpll.c new file mode 100644 index 000000000000..7e498a44f97d --- /dev/null +++ b/drivers/clk/ti/dpll.c @@ -0,0 +1,558 @@ +/* + * OMAP DPLL clock support + * + * Copyright (C) 2013 Texas Instruments, Inc. + * + * Tero Kristo + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include + +#undef pr_fmt +#define pr_fmt(fmt) "%s: " fmt, __func__ + +#define DPLL_HAS_AUTOIDLE 0x1 + +#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \ + defined(CONFIG_SOC_DRA7XX) +static const struct clk_ops dpll_m4xen_ck_ops = { + .enable = &omap3_noncore_dpll_enable, + .disable = &omap3_noncore_dpll_disable, + .recalc_rate = &omap4_dpll_regm4xen_recalc, + .round_rate = &omap4_dpll_regm4xen_round_rate, + .set_rate = &omap3_noncore_dpll_set_rate, + .get_parent = &omap2_init_dpll_parent, +}; +#endif + +static const struct clk_ops dpll_core_ck_ops = { + .recalc_rate = &omap3_dpll_recalc, + .get_parent = &omap2_init_dpll_parent, +}; + +#ifdef CONFIG_ARCH_OMAP3 +static const struct clk_ops omap3_dpll_core_ck_ops = { + .get_parent = &omap2_init_dpll_parent, + .recalc_rate = &omap3_dpll_recalc, + .round_rate = &omap2_dpll_round_rate, +}; +#endif + +static const struct clk_ops dpll_ck_ops = { + .enable = &omap3_noncore_dpll_enable, + .disable = &omap3_noncore_dpll_disable, + .recalc_rate = &omap3_dpll_recalc, + .round_rate = &omap2_dpll_round_rate, + .set_rate = &omap3_noncore_dpll_set_rate, + .get_parent = &omap2_init_dpll_parent, +}; + +static const struct clk_ops dpll_no_gate_ck_ops = { + .recalc_rate = &omap3_dpll_recalc, + .get_parent = &omap2_init_dpll_parent, + .round_rate = &omap2_dpll_round_rate, + .set_rate = &omap3_noncore_dpll_set_rate, +}; + +#ifdef CONFIG_ARCH_OMAP3 +static const struct clk_ops omap3_dpll_ck_ops = { + .enable = &omap3_noncore_dpll_enable, + .disable = &omap3_noncore_dpll_disable, + .get_parent = &omap2_init_dpll_parent, + .recalc_rate = &omap3_dpll_recalc, + .set_rate = &omap3_noncore_dpll_set_rate, + .round_rate = &omap2_dpll_round_rate, +}; + +static const struct clk_ops omap3_dpll_per_ck_ops = { + .enable = &omap3_noncore_dpll_enable, + .disable = &omap3_noncore_dpll_disable, + .get_parent = &omap2_init_dpll_parent, + .recalc_rate = &omap3_dpll_recalc, + .set_rate = &omap3_dpll4_set_rate, + .round_rate = &omap2_dpll_round_rate, +}; +#endif + +static const struct clk_ops dpll_x2_ck_ops = { + .recalc_rate = &omap3_clkoutx2_recalc, +}; + +/** + * ti_clk_register_dpll - low level registration of a DPLL clock + * @hw: hardware clock definition for the clock + * @node: device node for the clock + * + * Finalizes DPLL registration process. In case a failure (clk-ref or + * clk-bypass is missing), the clock is added to retry list and + * the initialization is retried on later stage. + */ +static void __init ti_clk_register_dpll(struct clk_hw *hw, + struct device_node *node) +{ + struct clk_hw_omap *clk_hw = to_clk_hw_omap(hw); + struct dpll_data *dd = clk_hw->dpll_data; + struct clk *clk; + + dd->clk_ref = of_clk_get(node, 0); + dd->clk_bypass = of_clk_get(node, 1); + + if (IS_ERR(dd->clk_ref) || IS_ERR(dd->clk_bypass)) { + pr_debug("clk-ref or clk-bypass missing for %s, retry later\n", + node->name); + if (!ti_clk_retry_init(node, hw, ti_clk_register_dpll)) + return; + + goto cleanup; + } + + /* register the clock */ + clk = clk_register(NULL, &clk_hw->hw); + + if (!IS_ERR(clk)) { + omap2_init_clk_hw_omap_clocks(clk); + of_clk_add_provider(node, of_clk_src_simple_get, clk); + kfree(clk_hw->hw.init->parent_names); + kfree(clk_hw->hw.init); + return; + } + +cleanup: + kfree(clk_hw->dpll_data); + kfree(clk_hw->hw.init->parent_names); + kfree(clk_hw->hw.init); + kfree(clk_hw); +} + +#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \ + defined(CONFIG_SOC_DRA7XX) || defined(CONFIG_SOC_AM33XX) +/** + * ti_clk_register_dpll_x2 - Registers a DPLLx2 clock + * @node: device node for this clock + * @ops: clk_ops for this clock + * @hw_ops: clk_hw_ops for this clock + * + * Initializes a DPLL x 2 clock from device tree data. + */ +static void ti_clk_register_dpll_x2(struct device_node *node, + const struct clk_ops *ops, + const struct clk_hw_omap_ops *hw_ops) +{ + struct clk *clk; + struct clk_init_data init = { NULL }; + struct clk_hw_omap *clk_hw; + const char *name = node->name; + const char *parent_name; + + parent_name = of_clk_get_parent_name(node, 0); + if (!parent_name) { + pr_err("%s must have parent\n", node->name); + return; + } + + clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL); + if (!clk_hw) + return; + + clk_hw->ops = hw_ops; + clk_hw->hw.init = &init; + + init.name = name; + init.ops = ops; + init.parent_names = &parent_name; + init.num_parents = 1; + + /* register the clock */ + clk = clk_register(NULL, &clk_hw->hw); + + if (IS_ERR(clk)) { + kfree(clk_hw); + } else { + omap2_init_clk_hw_omap_clocks(clk); + of_clk_add_provider(node, of_clk_src_simple_get, clk); + } +} +#endif + +/** + * of_ti_dpll_setup - Setup function for OMAP DPLL clocks + * @node: device node containing the DPLL info + * @ops: ops for the DPLL + * @ddt: DPLL data template to use + * @init_flags: flags for controlling init types + * + * Initializes a DPLL clock from device tree data. + */ +static void __init of_ti_dpll_setup(struct device_node *node, + const struct clk_ops *ops, + const struct dpll_data *ddt, + u8 init_flags) +{ + struct clk_hw_omap *clk_hw = NULL; + struct clk_init_data *init = NULL; + const char **parent_names = NULL; + struct dpll_data *dd = NULL; + int i; + u8 dpll_mode = 0; + + dd = kzalloc(sizeof(*dd), GFP_KERNEL); + clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL); + init = kzalloc(sizeof(*init), GFP_KERNEL); + if (!dd || !clk_hw || !init) + goto cleanup; + + memcpy(dd, ddt, sizeof(*dd)); + + clk_hw->dpll_data = dd; + clk_hw->ops = &clkhwops_omap3_dpll; + clk_hw->hw.init = init; + clk_hw->flags = MEMMAP_ADDRESSING; + + init->name = node->name; + init->ops = ops; + + init->num_parents = of_clk_get_parent_count(node); + if (init->num_parents < 1) { + pr_err("%s must have parent(s)\n", node->name); + goto cleanup; + } + + parent_names = kzalloc(sizeof(char *) * init->num_parents, GFP_KERNEL); + if (!parent_names) + goto cleanup; + + for (i = 0; i < init->num_parents; i++) + parent_names[i] = of_clk_get_parent_name(node, i); + + init->parent_names = parent_names; + + dd->control_reg = ti_clk_get_reg_addr(node, 0); + dd->idlest_reg = ti_clk_get_reg_addr(node, 1); + dd->mult_div1_reg = ti_clk_get_reg_addr(node, 2); + + if (!dd->control_reg || !dd->idlest_reg || !dd->mult_div1_reg) + goto cleanup; + + if (init_flags & DPLL_HAS_AUTOIDLE) { + dd->autoidle_reg = ti_clk_get_reg_addr(node, 3); + if (!dd->autoidle_reg) + goto cleanup; + } + + if (of_property_read_bool(node, "ti,low-power-stop")) + dpll_mode |= 1 << DPLL_LOW_POWER_STOP; + + if (of_property_read_bool(node, "ti,low-power-bypass")) + dpll_mode |= 1 << DPLL_LOW_POWER_BYPASS; + + if (of_property_read_bool(node, "ti,lock")) + dpll_mode |= 1 << DPLL_LOCKED; + + if (dpll_mode) + dd->modes = dpll_mode; + + ti_clk_register_dpll(&clk_hw->hw, node); + return; + +cleanup: + kfree(dd); + kfree(parent_names); + kfree(init); + kfree(clk_hw); +} + +#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \ + defined(CONFIG_SOC_DRA7XX) +static void __init of_ti_omap4_dpll_x2_setup(struct device_node *node) +{ + ti_clk_register_dpll_x2(node, &dpll_x2_ck_ops, &clkhwops_omap4_dpllmx); +} +CLK_OF_DECLARE(ti_omap4_dpll_x2_clock, "ti,omap4-dpll-x2-clock", + of_ti_omap4_dpll_x2_setup); +#endif + +#ifdef CONFIG_SOC_AM33XX +static void __init of_ti_am3_dpll_x2_setup(struct device_node *node) +{ + ti_clk_register_dpll_x2(node, &dpll_x2_ck_ops, NULL); +} +CLK_OF_DECLARE(ti_am3_dpll_x2_clock, "ti,am3-dpll-x2-clock", + of_ti_am3_dpll_x2_setup); +#endif + +#ifdef CONFIG_ARCH_OMAP3 +static void __init of_ti_omap3_dpll_setup(struct device_node *node) +{ + const struct dpll_data dd = { + .idlest_mask = 0x1, + .enable_mask = 0x7, + .autoidle_mask = 0x7, + .mult_mask = 0x7ff << 8, + .div1_mask = 0x7f, + .max_multiplier = 2047, + .max_divider = 128, + .min_divider = 1, + .freqsel_mask = 0xf0, + .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), + }; + + of_ti_dpll_setup(node, &omap3_dpll_ck_ops, &dd, DPLL_HAS_AUTOIDLE); +} +CLK_OF_DECLARE(ti_omap3_dpll_clock, "ti,omap3-dpll-clock", + of_ti_omap3_dpll_setup); + +static void __init of_ti_omap3_core_dpll_setup(struct device_node *node) +{ + const struct dpll_data dd = { + .idlest_mask = 0x1, + .enable_mask = 0x7, + .autoidle_mask = 0x7, + .mult_mask = 0x7ff << 16, + .div1_mask = 0x7f << 8, + .max_multiplier = 2047, + .max_divider = 128, + .min_divider = 1, + .freqsel_mask = 0xf0, + }; + + of_ti_dpll_setup(node, &omap3_dpll_core_ck_ops, &dd, DPLL_HAS_AUTOIDLE); +} +CLK_OF_DECLARE(ti_omap3_core_dpll_clock, "ti,omap3-dpll-core-clock", + of_ti_omap3_core_dpll_setup); + +static void __init of_ti_omap3_per_dpll_setup(struct device_node *node) +{ + const struct dpll_data dd = { + .idlest_mask = 0x1 << 1, + .enable_mask = 0x7 << 16, + .autoidle_mask = 0x7 << 3, + .mult_mask = 0x7ff << 8, + .div1_mask = 0x7f, + .max_multiplier = 2047, + .max_divider = 128, + .min_divider = 1, + .freqsel_mask = 0xf00000, + .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED), + }; + + of_ti_dpll_setup(node, &omap3_dpll_per_ck_ops, &dd, DPLL_HAS_AUTOIDLE); +} +CLK_OF_DECLARE(ti_omap3_per_dpll_clock, "ti,omap3-dpll-per-clock", + of_ti_omap3_per_dpll_setup); + +static void __init of_ti_omap3_per_jtype_dpll_setup(struct device_node *node) +{ + const struct dpll_data dd = { + .idlest_mask = 0x1 << 1, + .enable_mask = 0x7 << 16, + .autoidle_mask = 0x7 << 3, + .mult_mask = 0xfff << 8, + .div1_mask = 0x7f, + .max_multiplier = 4095, + .max_divider = 128, + .min_divider = 1, + .sddiv_mask = 0xff << 24, + .dco_mask = 0xe << 20, + .flags = DPLL_J_TYPE, + .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED), + }; + + of_ti_dpll_setup(node, &omap3_dpll_per_ck_ops, &dd, DPLL_HAS_AUTOIDLE); +} +CLK_OF_DECLARE(ti_omap3_per_jtype_dpll_clock, "ti,omap3-dpll-per-j-type-clock", + of_ti_omap3_per_jtype_dpll_setup); +#endif + +static void __init of_ti_omap4_dpll_setup(struct device_node *node) +{ + const struct dpll_data dd = { + .idlest_mask = 0x1, + .enable_mask = 0x7, + .autoidle_mask = 0x7, + .mult_mask = 0x7ff << 8, + .div1_mask = 0x7f, + .max_multiplier = 2047, + .max_divider = 128, + .min_divider = 1, + .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), + }; + + of_ti_dpll_setup(node, &dpll_ck_ops, &dd, DPLL_HAS_AUTOIDLE); +} +CLK_OF_DECLARE(ti_omap4_dpll_clock, "ti,omap4-dpll-clock", + of_ti_omap4_dpll_setup); + +static void __init of_ti_omap4_core_dpll_setup(struct device_node *node) +{ + const struct dpll_data dd = { + .idlest_mask = 0x1, + .enable_mask = 0x7, + .autoidle_mask = 0x7, + .mult_mask = 0x7ff << 8, + .div1_mask = 0x7f, + .max_multiplier = 2047, + .max_divider = 128, + .min_divider = 1, + .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), + }; + + of_ti_dpll_setup(node, &dpll_core_ck_ops, &dd, DPLL_HAS_AUTOIDLE); +} +CLK_OF_DECLARE(ti_omap4_core_dpll_clock, "ti,omap4-dpll-core-clock", + of_ti_omap4_core_dpll_setup); + +#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \ + defined(CONFIG_SOC_DRA7XX) +static void __init of_ti_omap4_m4xen_dpll_setup(struct device_node *node) +{ + const struct dpll_data dd = { + .idlest_mask = 0x1, + .enable_mask = 0x7, + .autoidle_mask = 0x7, + .mult_mask = 0x7ff << 8, + .div1_mask = 0x7f, + .max_multiplier = 2047, + .max_divider = 128, + .min_divider = 1, + .m4xen_mask = 0x800, + .lpmode_mask = 1 << 10, + .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), + }; + + of_ti_dpll_setup(node, &dpll_m4xen_ck_ops, &dd, DPLL_HAS_AUTOIDLE); +} +CLK_OF_DECLARE(ti_omap4_m4xen_dpll_clock, "ti,omap4-dpll-m4xen-clock", + of_ti_omap4_m4xen_dpll_setup); + +static void __init of_ti_omap4_jtype_dpll_setup(struct device_node *node) +{ + const struct dpll_data dd = { + .idlest_mask = 0x1, + .enable_mask = 0x7, + .autoidle_mask = 0x7, + .mult_mask = 0xfff << 8, + .div1_mask = 0xff, + .max_multiplier = 4095, + .max_divider = 256, + .min_divider = 1, + .sddiv_mask = 0xff << 24, + .flags = DPLL_J_TYPE, + .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), + }; + + of_ti_dpll_setup(node, &dpll_m4xen_ck_ops, &dd, DPLL_HAS_AUTOIDLE); +} +CLK_OF_DECLARE(ti_omap4_jtype_dpll_clock, "ti,omap4-dpll-j-type-clock", + of_ti_omap4_jtype_dpll_setup); +#endif + +static void __init of_ti_am3_no_gate_dpll_setup(struct device_node *node) +{ + const struct dpll_data dd = { + .idlest_mask = 0x1, + .enable_mask = 0x7, + .autoidle_mask = 0x7, + .mult_mask = 0x7ff << 8, + .div1_mask = 0x7f, + .max_multiplier = 2047, + .max_divider = 128, + .min_divider = 1, + .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), + }; + + of_ti_dpll_setup(node, &dpll_no_gate_ck_ops, &dd, 0); +} +CLK_OF_DECLARE(ti_am3_no_gate_dpll_clock, "ti,am3-dpll-no-gate-clock", + of_ti_am3_no_gate_dpll_setup); + +static void __init of_ti_am3_jtype_dpll_setup(struct device_node *node) +{ + const struct dpll_data dd = { + .idlest_mask = 0x1, + .enable_mask = 0x7, + .autoidle_mask = 0x7, + .mult_mask = 0x7ff << 8, + .div1_mask = 0x7f, + .max_multiplier = 4095, + .max_divider = 256, + .min_divider = 2, + .flags = DPLL_J_TYPE, + .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), + }; + + of_ti_dpll_setup(node, &dpll_ck_ops, &dd, 0); +} +CLK_OF_DECLARE(ti_am3_jtype_dpll_clock, "ti,am3-dpll-j-type-clock", + of_ti_am3_jtype_dpll_setup); + +static void __init of_ti_am3_no_gate_jtype_dpll_setup(struct device_node *node) +{ + const struct dpll_data dd = { + .idlest_mask = 0x1, + .enable_mask = 0x7, + .autoidle_mask = 0x7, + .mult_mask = 0x7ff << 8, + .div1_mask = 0x7f, + .max_multiplier = 2047, + .max_divider = 128, + .min_divider = 1, + .flags = DPLL_J_TYPE, + .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), + }; + + of_ti_dpll_setup(node, &dpll_no_gate_ck_ops, &dd, 0); +} +CLK_OF_DECLARE(ti_am3_no_gate_jtype_dpll_clock, + "ti,am3-dpll-no-gate-j-type-clock", + of_ti_am3_no_gate_jtype_dpll_setup); + +static void __init of_ti_am3_dpll_setup(struct device_node *node) +{ + const struct dpll_data dd = { + .idlest_mask = 0x1, + .enable_mask = 0x7, + .autoidle_mask = 0x7, + .mult_mask = 0x7ff << 8, + .div1_mask = 0x7f, + .max_multiplier = 2047, + .max_divider = 128, + .min_divider = 1, + .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), + }; + + of_ti_dpll_setup(node, &dpll_ck_ops, &dd, 0); +} +CLK_OF_DECLARE(ti_am3_dpll_clock, "ti,am3-dpll-clock", of_ti_am3_dpll_setup); + +static void __init of_ti_am3_core_dpll_setup(struct device_node *node) +{ + const struct dpll_data dd = { + .idlest_mask = 0x1, + .enable_mask = 0x7, + .autoidle_mask = 0x7, + .mult_mask = 0x7ff << 8, + .div1_mask = 0x7f, + .max_multiplier = 2047, + .max_divider = 128, + .min_divider = 1, + .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), + }; + + of_ti_dpll_setup(node, &dpll_core_ck_ops, &dd, 0); +} +CLK_OF_DECLARE(ti_am3_core_dpll_clock, "ti,am3-dpll-core-clock", + of_ti_am3_core_dpll_setup); diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h index c6eded5eea76..3f9de3973582 100644 --- a/include/linux/clk/ti.h +++ b/include/linux/clk/ti.h @@ -17,6 +17,153 @@ #include +/** + * struct dpll_data - DPLL registers and integration data + * @mult_div1_reg: register containing the DPLL M and N bitfields + * @mult_mask: mask of the DPLL M bitfield in @mult_div1_reg + * @div1_mask: mask of the DPLL N bitfield in @mult_div1_reg + * @clk_bypass: struct clk pointer to the clock's bypass clock input + * @clk_ref: struct clk pointer to the clock's reference clock input + * @control_reg: register containing the DPLL mode bitfield + * @enable_mask: mask of the DPLL mode bitfield in @control_reg + * @last_rounded_rate: cache of the last rate result of omap2_dpll_round_rate() + * @last_rounded_m: cache of the last M result of omap2_dpll_round_rate() + * @last_rounded_m4xen: cache of the last M4X result of + * omap4_dpll_regm4xen_round_rate() + * @last_rounded_lpmode: cache of the last lpmode result of + * omap4_dpll_lpmode_recalc() + * @max_multiplier: maximum valid non-bypass multiplier value (actual) + * @last_rounded_n: cache of the last N result of omap2_dpll_round_rate() + * @min_divider: minimum valid non-bypass divider value (actual) + * @max_divider: maximum valid non-bypass divider value (actual) + * @modes: possible values of @enable_mask + * @autoidle_reg: register containing the DPLL autoidle mode bitfield + * @idlest_reg: register containing the DPLL idle status bitfield + * @autoidle_mask: mask of the DPLL autoidle mode bitfield in @autoidle_reg + * @freqsel_mask: mask of the DPLL jitter correction bitfield in @control_reg + * @idlest_mask: mask of the DPLL idle status bitfield in @idlest_reg + * @lpmode_mask: mask of the DPLL low-power mode bitfield in @control_reg + * @m4xen_mask: mask of the DPLL M4X multiplier bitfield in @control_reg + * @auto_recal_bit: bitshift of the driftguard enable bit in @control_reg + * @recal_en_bit: bitshift of the PRM_IRQENABLE_* bit for recalibration IRQs + * @recal_st_bit: bitshift of the PRM_IRQSTATUS_* bit for recalibration IRQs + * @flags: DPLL type/features (see below) + * + * Possible values for @flags: + * DPLL_J_TYPE: "J-type DPLL" (only some 36xx, 4xxx DPLLs) + * + * @freqsel_mask is only used on the OMAP34xx family and AM35xx. + * + * XXX Some DPLLs have multiple bypass inputs, so it's not technically + * correct to only have one @clk_bypass pointer. + * + * XXX The runtime-variable fields (@last_rounded_rate, @last_rounded_m, + * @last_rounded_n) should be separated from the runtime-fixed fields + * and placed into a different structure, so that the runtime-fixed data + * can be placed into read-only space. + */ +struct dpll_data { + void __iomem *mult_div1_reg; + u32 mult_mask; + u32 div1_mask; + struct clk *clk_bypass; + struct clk *clk_ref; + void __iomem *control_reg; + u32 enable_mask; + unsigned long last_rounded_rate; + u16 last_rounded_m; + u8 last_rounded_m4xen; + u8 last_rounded_lpmode; + u16 max_multiplier; + u8 last_rounded_n; + u8 min_divider; + u16 max_divider; + u8 modes; + void __iomem *autoidle_reg; + void __iomem *idlest_reg; + u32 autoidle_mask; + u32 freqsel_mask; + u32 idlest_mask; + u32 dco_mask; + u32 sddiv_mask; + u32 lpmode_mask; + u32 m4xen_mask; + u8 auto_recal_bit; + u8 recal_en_bit; + u8 recal_st_bit; + u8 flags; +}; + +struct clk_hw_omap_ops; + +/** + * struct clk_hw_omap - OMAP struct clk + * @node: list_head connecting this clock into the full clock list + * @enable_reg: register to write to enable the clock (see @enable_bit) + * @enable_bit: bitshift to write to enable/disable the clock (see @enable_reg) + * @flags: see "struct clk.flags possibilities" above + * @clksel_reg: for clksel clks, register va containing src/divisor select + * @clksel_mask: bitmask in @clksel_reg for the src/divisor selector + * @clksel: for clksel clks, pointer to struct clksel for this clock + * @dpll_data: for DPLLs, pointer to struct dpll_data for this clock + * @clkdm_name: clockdomain name that this clock is contained in + * @clkdm: pointer to struct clockdomain, resolved from @clkdm_name at runtime + * @ops: clock ops for this clock + */ +struct clk_hw_omap { + struct clk_hw hw; + struct list_head node; + unsigned long fixed_rate; + u8 fixed_div; + void __iomem *enable_reg; + u8 enable_bit; + u8 flags; + void __iomem *clksel_reg; + u32 clksel_mask; + const struct clksel *clksel; + struct dpll_data *dpll_data; + const char *clkdm_name; + struct clockdomain *clkdm; + const struct clk_hw_omap_ops *ops; +}; + +/* + * struct clk_hw_omap.flags possibilities + * + * XXX document the rest of the clock flags here + * + * ENABLE_REG_32BIT: (OMAP1 only) clock control register must be accessed + * with 32bit ops, by default OMAP1 uses 16bit ops. + * CLOCK_IDLE_CONTROL: (OMAP1 only) clock has autoidle support. + * CLOCK_NO_IDLE_PARENT: (OMAP1 only) when clock is enabled, its parent + * clock is put to no-idle mode. + * ENABLE_ON_INIT: Clock is enabled on init. + * INVERT_ENABLE: By default, clock enable bit behavior is '1' enable, '0' + * disable. This inverts the behavior making '0' enable and '1' disable. + * CLOCK_CLKOUTX2: (OMAP4 only) DPLL CLKOUT and CLKOUTX2 GATE_CTRL + * bits share the same register. This flag allows the + * omap4_dpllmx*() code to determine which GATE_CTRL bit field + * should be used. This is a temporary solution - a better approach + * would be to associate clock type-specific data with the clock, + * similar to the struct dpll_data approach. + * MEMMAP_ADDRESSING: Use memmap addressing to access clock registers. + */ +#define ENABLE_REG_32BIT (1 << 0) /* Use 32-bit access */ +#define CLOCK_IDLE_CONTROL (1 << 1) +#define CLOCK_NO_IDLE_PARENT (1 << 2) +#define ENABLE_ON_INIT (1 << 3) /* Enable upon framework init */ +#define INVERT_ENABLE (1 << 4) /* 0 enables, 1 disables */ +#define CLOCK_CLKOUTX2 (1 << 5) +#define MEMMAP_ADDRESSING (1 << 6) + +/* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */ +#define DPLL_LOW_POWER_STOP 0x1 +#define DPLL_LOW_POWER_BYPASS 0x5 +#define DPLL_LOCKED 0x7 + +/* DPLL Type and DCO Selection Flags */ +#define DPLL_J_TYPE 0x1 + /** * struct ti_dt_clk - OMAP DT clock alias declarations * @lk: clock lookup definition @@ -68,10 +215,35 @@ struct ti_clk_ll_ops { extern struct ti_clk_ll_ops *ti_clk_ll_ops; +#define to_clk_hw_omap(_hw) container_of(_hw, struct clk_hw_omap, hw) + +void omap2_init_clk_hw_omap_clocks(struct clk *clk); +int omap3_noncore_dpll_enable(struct clk_hw *hw); +void omap3_noncore_dpll_disable(struct clk_hw *hw); +int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate); +unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw, + unsigned long parent_rate); +long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw, + unsigned long target_rate, + unsigned long *parent_rate); +u8 omap2_init_dpll_parent(struct clk_hw *hw); +unsigned long omap3_dpll_recalc(struct clk_hw *hw, unsigned long parent_rate); +long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate, + unsigned long *parent_rate); +void omap2_init_clk_clkdm(struct clk_hw *clk); +unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw, + unsigned long parent_rate); +int omap3_dpll4_set_rate(struct clk_hw *clk, unsigned long rate, + unsigned long parent_rate); + void __iomem *ti_clk_get_reg_addr(struct device_node *node, int index); void ti_dt_clocks_register(struct ti_dt_clk *oclks); void ti_dt_clk_init_provider(struct device_node *np, int index); int ti_clk_retry_init(struct device_node *node, struct clk_hw *hw, ti_of_clk_init_cb_t func); +extern const struct clk_hw_omap_ops clkhwops_omap3_dpll; +extern const struct clk_hw_omap_ops clkhwops_omap4_dpllmx; + #endif -- cgit v1.2.3-59-g8ed1b From b1a07b478b63f0a8f971b3a82ce34a67a9324547 Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Tue, 18 Jun 2013 16:27:57 +0300 Subject: CLK: TI: add autoidle support TI clk driver now routes some of the basic clocks through own registration routine to allow autoidle support. This routine just checks a couple of device node properties and adds autoidle support if required, and just passes the registration forward to basic clocks. Signed-off-by: Tero Kristo Acked-by: Tony Lindgren Signed-off-by: Mike Turquette --- .../devicetree/bindings/clock/ti/autoidle.txt | 39 ++++++ arch/arm/mach-omap2/clock.c | 6 + drivers/clk/ti/Makefile | 2 +- drivers/clk/ti/autoidle.c | 133 +++++++++++++++++++++ include/linux/clk/ti.h | 9 ++ 5 files changed, 188 insertions(+), 1 deletion(-) create mode 100644 Documentation/devicetree/bindings/clock/ti/autoidle.txt create mode 100644 drivers/clk/ti/autoidle.c diff --git a/Documentation/devicetree/bindings/clock/ti/autoidle.txt b/Documentation/devicetree/bindings/clock/ti/autoidle.txt new file mode 100644 index 000000000000..7c735dde9fe9 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/ti/autoidle.txt @@ -0,0 +1,39 @@ +Binding for Texas Instruments autoidle clock. + +Binding status: Unstable - ABI compatibility may be broken in the future + +This binding uses the common clock binding[1]. It assumes a register mapped +clock which can be put to idle automatically by hardware based on the usage +and a configuration bit setting. Autoidle clock is never an individual +clock, it is always a derivative of some basic clock like a gate, divider, +or fixed-factor. + +[1] Documentation/devicetree/bindings/clock/clock-bindings.txt + +Required properties: +- reg : offset for the register controlling the autoidle +- ti,autoidle-shift : bit shift of the autoidle enable bit +- ti,invert-autoidle-bit : autoidle is enabled by setting the bit to 0 + +Examples: + dpll_core_m4_ck: dpll_core_m4_ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll_core_x2_ck>; + ti,max-div = <31>; + ti,autoidle-shift = <8>; + reg = <0x2d38>; + ti,index-starts-at-one; + ti,invert-autoidle-bit; + }; + + dpll_usb_clkdcoldo_ck: dpll_usb_clkdcoldo_ck { + #clock-cells = <0>; + compatible = "ti,fixed-factor-clock"; + clocks = <&dpll_usb_ck>; + ti,clock-div = <1>; + ti,autoidle-shift = <8>; + reg = <0x01b4>; + ti,clock-mult = <1>; + ti,invert-autoidle-bit; + }; diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c index c7c5d31e9082..238be3f1ddce 100644 --- a/arch/arm/mach-omap2/clock.c +++ b/arch/arm/mach-omap2/clock.c @@ -520,6 +520,9 @@ int omap2_clk_enable_autoidle_all(void) list_for_each_entry(c, &clk_hw_omap_clocks, node) if (c->ops && c->ops->allow_idle) c->ops->allow_idle(c); + + of_ti_clk_allow_autoidle_all(); + return 0; } @@ -539,6 +542,9 @@ int omap2_clk_disable_autoidle_all(void) list_for_each_entry(c, &clk_hw_omap_clocks, node) if (c->ops && c->ops->deny_idle) c->ops->deny_idle(c); + + of_ti_clk_deny_autoidle_all(); + return 0; } diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile index 3dbb78dc9fca..7fa1a48df4f3 100644 --- a/drivers/clk/ti/Makefile +++ b/drivers/clk/ti/Makefile @@ -1,4 +1,4 @@ ifneq ($(CONFIG_OF),) -obj-y += clk.o +obj-y += clk.o autoidle.o clk-common = dpll.o endif diff --git a/drivers/clk/ti/autoidle.c b/drivers/clk/ti/autoidle.c new file mode 100644 index 000000000000..8912ff80af34 --- /dev/null +++ b/drivers/clk/ti/autoidle.c @@ -0,0 +1,133 @@ +/* + * TI clock autoidle support + * + * Copyright (C) 2013 Texas Instruments, Inc. + * + * Tero Kristo + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include + +struct clk_ti_autoidle { + void __iomem *reg; + u8 shift; + u8 flags; + const char *name; + struct list_head node; +}; + +#define AUTOIDLE_LOW 0x1 + +static LIST_HEAD(autoidle_clks); + +static void ti_allow_autoidle(struct clk_ti_autoidle *clk) +{ + u32 val; + + val = ti_clk_ll_ops->clk_readl(clk->reg); + + if (clk->flags & AUTOIDLE_LOW) + val &= ~(1 << clk->shift); + else + val |= (1 << clk->shift); + + ti_clk_ll_ops->clk_writel(val, clk->reg); +} + +static void ti_deny_autoidle(struct clk_ti_autoidle *clk) +{ + u32 val; + + val = ti_clk_ll_ops->clk_readl(clk->reg); + + if (clk->flags & AUTOIDLE_LOW) + val |= (1 << clk->shift); + else + val &= ~(1 << clk->shift); + + ti_clk_ll_ops->clk_writel(val, clk->reg); +} + +/** + * of_ti_clk_allow_autoidle_all - enable autoidle for all clocks + * + * Enables hardware autoidle for all registered DT clocks, which have + * the feature. + */ +void of_ti_clk_allow_autoidle_all(void) +{ + struct clk_ti_autoidle *c; + + list_for_each_entry(c, &autoidle_clks, node) + ti_allow_autoidle(c); +} + +/** + * of_ti_clk_deny_autoidle_all - disable autoidle for all clocks + * + * Disables hardware autoidle for all registered DT clocks, which have + * the feature. + */ +void of_ti_clk_deny_autoidle_all(void) +{ + struct clk_ti_autoidle *c; + + list_for_each_entry(c, &autoidle_clks, node) + ti_deny_autoidle(c); +} + +/** + * of_ti_clk_autoidle_setup - sets up hardware autoidle for a clock + * @node: pointer to the clock device node + * + * Checks if a clock has hardware autoidle support or not (check + * for presence of 'ti,autoidle-shift' property in the device tree + * node) and sets up the hardware autoidle feature for the clock + * if available. If autoidle is available, the clock is also added + * to the autoidle list for later processing. Returns 0 on success, + * negative error value on failure. + */ +int __init of_ti_clk_autoidle_setup(struct device_node *node) +{ + u32 shift; + struct clk_ti_autoidle *clk; + + /* Check if this clock has autoidle support or not */ + if (of_property_read_u32(node, "ti,autoidle-shift", &shift)) + return 0; + + clk = kzalloc(sizeof(*clk), GFP_KERNEL); + + if (!clk) + return -ENOMEM; + + clk->shift = shift; + clk->name = node->name; + clk->reg = ti_clk_get_reg_addr(node, 0); + + if (!clk->reg) { + kfree(clk); + return -EINVAL; + } + + if (of_property_read_bool(node, "ti,invert-autoidle-bit")) + clk->flags |= AUTOIDLE_LOW; + + list_add(&clk->node, &autoidle_clks); + + return 0; +} diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h index 3f9de3973582..ca38ee3620b1 100644 --- a/include/linux/clk/ti.h +++ b/include/linux/clk/ti.h @@ -242,6 +242,15 @@ void ti_dt_clocks_register(struct ti_dt_clk *oclks); void ti_dt_clk_init_provider(struct device_node *np, int index); int ti_clk_retry_init(struct device_node *node, struct clk_hw *hw, ti_of_clk_init_cb_t func); +int of_ti_clk_autoidle_setup(struct device_node *node); + +#ifdef CONFIG_OF +void of_ti_clk_allow_autoidle_all(void); +void of_ti_clk_deny_autoidle_all(void); +#else +static inline void of_ti_clk_allow_autoidle_all(void) { } +static inline void of_ti_clk_deny_autoidle_all(void) { } +#endif extern const struct clk_hw_omap_ops clkhwops_omap3_dpll; extern const struct clk_hw_omap_ops clkhwops_omap4_dpllmx; -- cgit v1.2.3-59-g8ed1b From 975e15487d5abfd5f33fea9c1ba0b987604f0d0f Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Mon, 9 Sep 2013 15:46:45 +0300 Subject: clk: ti: add composite clock support This is a multipurpose clock node, which contains support for multiple sub-clocks. Uses basic composite clock type to implement the actual functionality, and TI specific gate, mux and divider clocks. Signed-off-by: Tero Kristo Acked-by: Tony Lindgren Signed-off-by: Mike Turquette --- .../devicetree/bindings/clock/ti/composite.txt | 54 +++++ arch/arm/mach-omap2/clock.h | 3 - drivers/clk/ti/Makefile | 2 +- drivers/clk/ti/composite.c | 269 +++++++++++++++++++++ include/linux/clk/ti.h | 12 + 5 files changed, 336 insertions(+), 4 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/ti/composite.txt create mode 100644 drivers/clk/ti/composite.c diff --git a/Documentation/devicetree/bindings/clock/ti/composite.txt b/Documentation/devicetree/bindings/clock/ti/composite.txt new file mode 100644 index 000000000000..5f43c4706b09 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/ti/composite.txt @@ -0,0 +1,54 @@ +Binding for TI composite clock. + +Binding status: Unstable - ABI compatibility may be broken in the future + +This binding uses the common clock binding[1]. It assumes a +register-mapped composite clock with multiple different sub-types; + +a multiplexer clock with multiple input clock signals or parents, one +of which can be selected as output, this behaves exactly as [2] + +an adjustable clock rate divider, this behaves exactly as [3] + +a gating function which can be used to enable and disable the output +clock, this behaves exactly as [4] + +The binding must provide a list of the component clocks that shall be +merged to this clock. The component clocks shall be of one of the +"ti,*composite*-clock" types. + +[1] Documentation/devicetree/bindings/clock/clock-bindings.txt +[2] Documentation/devicetree/bindings/clock/ti/mux.txt +[3] Documentation/devicetree/bindings/clock/ti/divider.txt +[4] Documentation/devicetree/bindings/clock/ti/gate.txt + +Required properties: +- compatible : shall be: "ti,composite-clock" +- clocks : link phandles of component clocks +- #clock-cells : from common clock binding; shall be set to 0. + +Examples: + +usb_l4_gate_ick: usb_l4_gate_ick { + #clock-cells = <0>; + compatible = "ti,composite-interface-clock"; + clocks = <&l4_ick>; + ti,bit-shift = <5>; + reg = <0x0a10>; +}; + +usb_l4_div_ick: usb_l4_div_ick { + #clock-cells = <0>; + compatible = "ti,composite-divider-clock"; + clocks = <&l4_ick>; + ti,bit-shift = <4>; + ti,max-div = <1>; + reg = <0x0a40>; + ti,index-starts-at-one; +}; + +usb_l4_ick: usb_l4_ick { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&usb_l4_gate_ick>, <&usb_l4_div_ick>; +}; diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h index b345f3ea8617..6bd72b53e4d4 100644 --- a/arch/arm/mach-omap2/clock.h +++ b/arch/arm/mach-omap2/clock.h @@ -240,9 +240,6 @@ extern void omap2_clkt_iclk_deny_idle(struct clk_hw_omap *clk); unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk); -int omap2_dflt_clk_enable(struct clk_hw *hw); -void omap2_dflt_clk_disable(struct clk_hw *hw); -int omap2_dflt_clk_is_enabled(struct clk_hw *hw); void omap2_clk_dflt_find_companion(struct clk_hw_omap *clk, void __iomem **other_reg, u8 *other_bit); diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile index 7fa1a48df4f3..ac4ea50672ed 100644 --- a/drivers/clk/ti/Makefile +++ b/drivers/clk/ti/Makefile @@ -1,4 +1,4 @@ ifneq ($(CONFIG_OF),) obj-y += clk.o autoidle.o -clk-common = dpll.o +clk-common = dpll.o composite.o endif diff --git a/drivers/clk/ti/composite.c b/drivers/clk/ti/composite.c new file mode 100644 index 000000000000..6539b650cae0 --- /dev/null +++ b/drivers/clk/ti/composite.c @@ -0,0 +1,269 @@ +/* + * TI composite clock support + * + * Copyright (C) 2013 Texas Instruments, Inc. + * + * Tero Kristo + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include + +#undef pr_fmt +#define pr_fmt(fmt) "%s: " fmt, __func__ + +#define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw) + +static unsigned long ti_composite_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + return clk_divider_ops.recalc_rate(hw, parent_rate); +} + +static long ti_composite_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *prate) +{ + return -EINVAL; +} + +static int ti_composite_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + return -EINVAL; +} + +static const struct clk_ops ti_composite_divider_ops = { + .recalc_rate = &ti_composite_recalc_rate, + .round_rate = &ti_composite_round_rate, + .set_rate = &ti_composite_set_rate, +}; + +static const struct clk_ops ti_composite_gate_ops = { + .enable = &omap2_dflt_clk_enable, + .disable = &omap2_dflt_clk_disable, + .is_enabled = &omap2_dflt_clk_is_enabled, +}; + +struct component_clk { + int num_parents; + const char **parent_names; + struct device_node *node; + int type; + struct clk_hw *hw; + struct list_head link; +}; + +static const char * __initconst component_clk_types[] = { + "gate", "divider", "mux" +}; + +static LIST_HEAD(component_clks); + +static struct device_node *_get_component_node(struct device_node *node, int i) +{ + int rc; + struct of_phandle_args clkspec; + + rc = of_parse_phandle_with_args(node, "clocks", "#clock-cells", i, + &clkspec); + if (rc) + return NULL; + + return clkspec.np; +} + +static struct component_clk *_lookup_component(struct device_node *node) +{ + struct component_clk *comp; + + list_for_each_entry(comp, &component_clks, link) { + if (comp->node == node) + return comp; + } + return NULL; +} + +struct clk_hw_omap_comp { + struct clk_hw hw; + struct device_node *comp_nodes[CLK_COMPONENT_TYPE_MAX]; + struct component_clk *comp_clks[CLK_COMPONENT_TYPE_MAX]; +}; + +static inline struct clk_hw *_get_hw(struct clk_hw_omap_comp *clk, int idx) +{ + if (!clk) + return NULL; + + if (!clk->comp_clks[idx]) + return NULL; + + return clk->comp_clks[idx]->hw; +} + +#define to_clk_hw_comp(_hw) container_of(_hw, struct clk_hw_omap_comp, hw) + +static void __init ti_clk_register_composite(struct clk_hw *hw, + struct device_node *node) +{ + struct clk *clk; + struct clk_hw_omap_comp *cclk = to_clk_hw_comp(hw); + struct component_clk *comp; + int num_parents = 0; + const char **parent_names = NULL; + int i; + + /* Check for presence of each component clock */ + for (i = 0; i < CLK_COMPONENT_TYPE_MAX; i++) { + if (!cclk->comp_nodes[i]) + continue; + + comp = _lookup_component(cclk->comp_nodes[i]); + if (!comp) { + pr_debug("component %s not ready for %s, retry\n", + cclk->comp_nodes[i]->name, node->name); + if (!ti_clk_retry_init(node, hw, + ti_clk_register_composite)) + return; + + goto cleanup; + } + if (cclk->comp_clks[comp->type] != NULL) { + pr_err("duplicate component types for %s (%s)!\n", + node->name, component_clk_types[comp->type]); + goto cleanup; + } + + cclk->comp_clks[comp->type] = comp; + + /* Mark this node as found */ + cclk->comp_nodes[i] = NULL; + } + + /* All components exists, proceed with registration */ + for (i = CLK_COMPONENT_TYPE_MAX - 1; i >= 0; i--) { + comp = cclk->comp_clks[i]; + if (!comp) + continue; + if (comp->num_parents) { + num_parents = comp->num_parents; + parent_names = comp->parent_names; + break; + } + } + + if (!num_parents) { + pr_err("%s: no parents found for %s!\n", __func__, node->name); + goto cleanup; + } + + clk = clk_register_composite(NULL, node->name, + parent_names, num_parents, + _get_hw(cclk, CLK_COMPONENT_TYPE_MUX), + &clk_mux_ops, + _get_hw(cclk, CLK_COMPONENT_TYPE_DIVIDER), + &ti_composite_divider_ops, + _get_hw(cclk, CLK_COMPONENT_TYPE_GATE), + &ti_composite_gate_ops, 0); + + if (!IS_ERR(clk)) + of_clk_add_provider(node, of_clk_src_simple_get, clk); + +cleanup: + /* Free component clock list entries */ + for (i = 0; i < CLK_COMPONENT_TYPE_MAX; i++) { + if (!cclk->comp_clks[i]) + continue; + list_del(&cclk->comp_clks[i]->link); + kfree(cclk->comp_clks[i]); + } + + kfree(cclk); +} + +static void __init of_ti_composite_clk_setup(struct device_node *node) +{ + int num_clks; + int i; + struct clk_hw_omap_comp *cclk; + + /* Number of component clocks to be put inside this clock */ + num_clks = of_clk_get_parent_count(node); + + if (num_clks < 1) { + pr_err("composite clk %s must have component(s)\n", node->name); + return; + } + + cclk = kzalloc(sizeof(*cclk), GFP_KERNEL); + if (!cclk) + return; + + /* Get device node pointers for each component clock */ + for (i = 0; i < num_clks; i++) + cclk->comp_nodes[i] = _get_component_node(node, i); + + ti_clk_register_composite(&cclk->hw, node); +} +CLK_OF_DECLARE(ti_composite_clock, "ti,composite-clock", + of_ti_composite_clk_setup); + +/** + * ti_clk_add_component - add a component clock to the pool + * @node: device node of the component clock + * @hw: hardware clock definition for the component clock + * @type: type of the component clock + * + * Adds a component clock to the list of available components, so that + * it can be registered by a composite clock. + */ +int __init ti_clk_add_component(struct device_node *node, struct clk_hw *hw, + int type) +{ + int num_parents; + const char **parent_names; + struct component_clk *clk; + int i; + + num_parents = of_clk_get_parent_count(node); + + if (num_parents < 1) { + pr_err("component-clock %s must have parent(s)\n", node->name); + return -EINVAL; + } + + parent_names = kzalloc((sizeof(char *) * num_parents), GFP_KERNEL); + if (!parent_names) + return -ENOMEM; + + for (i = 0; i < num_parents; i++) + parent_names[i] = of_clk_get_parent_name(node, i); + + clk = kzalloc(sizeof(*clk), GFP_KERNEL); + if (!clk) { + kfree(parent_names); + return -ENOMEM; + } + + clk->num_parents = num_parents; + clk->parent_names = parent_names; + clk->hw = hw; + clk->node = node; + clk->type = type; + list_add(&clk->link, &component_clks); + + return 0; +} diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h index ca38ee3620b1..c8c591dd3261 100644 --- a/include/linux/clk/ti.h +++ b/include/linux/clk/ti.h @@ -164,6 +164,14 @@ struct clk_hw_omap { /* DPLL Type and DCO Selection Flags */ #define DPLL_J_TYPE 0x1 +/* Composite clock component types */ +enum { + CLK_COMPONENT_TYPE_GATE = 0, + CLK_COMPONENT_TYPE_DIVIDER, + CLK_COMPONENT_TYPE_MUX, + CLK_COMPONENT_TYPE_MAX, +}; + /** * struct ti_dt_clk - OMAP DT clock alias declarations * @lk: clock lookup definition @@ -236,6 +244,9 @@ unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw, unsigned long parent_rate); int omap3_dpll4_set_rate(struct clk_hw *clk, unsigned long rate, unsigned long parent_rate); +int omap2_dflt_clk_enable(struct clk_hw *hw); +void omap2_dflt_clk_disable(struct clk_hw *hw); +int omap2_dflt_clk_is_enabled(struct clk_hw *hw); void __iomem *ti_clk_get_reg_addr(struct device_node *node, int index); void ti_dt_clocks_register(struct ti_dt_clk *oclks); @@ -243,6 +254,7 @@ void ti_dt_clk_init_provider(struct device_node *np, int index); int ti_clk_retry_init(struct device_node *node, struct clk_hw *hw, ti_of_clk_init_cb_t func); int of_ti_clk_autoidle_setup(struct device_node *node); +int ti_clk_add_component(struct device_node *node, struct clk_hw *hw, int type); #ifdef CONFIG_OF void of_ti_clk_allow_autoidle_all(void); -- cgit v1.2.3-59-g8ed1b From b4761198bfaf29649dc58a48e8b123ea4174ba95 Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Fri, 13 Sep 2013 12:02:15 +0300 Subject: CLK: ti: add support for ti divider-clock This patch adds support for TI divider clock binding, which simply uses the basic clock divider to provide the features needed. Signed-off-by: Tero Kristo Acked-by: Tony Lindgren Signed-off-by: Mike Turquette --- .../devicetree/bindings/clock/ti/divider.txt | 114 +++++ drivers/clk/ti/Makefile | 2 +- drivers/clk/ti/composite.c | 2 +- drivers/clk/ti/divider.c | 487 +++++++++++++++++++++ include/linux/clk/ti.h | 2 + 5 files changed, 605 insertions(+), 2 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/ti/divider.txt create mode 100644 drivers/clk/ti/divider.c diff --git a/Documentation/devicetree/bindings/clock/ti/divider.txt b/Documentation/devicetree/bindings/clock/ti/divider.txt new file mode 100644 index 000000000000..35a6f5c7e5c2 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/ti/divider.txt @@ -0,0 +1,114 @@ +Binding for TI divider clock + +Binding status: Unstable - ABI compatibility may be broken in the future + +This binding uses the common clock binding[1]. It assumes a +register-mapped adjustable clock rate divider that does not gate and has +only one input clock or parent. By default the value programmed into +the register is one less than the actual divisor value. E.g: + +register value actual divisor value +0 1 +1 2 +2 3 + +This assumption may be modified by the following optional properties: + +ti,index-starts-at-one - valid divisor values start at 1, not the default +of 0. E.g: +register value actual divisor value +1 1 +2 2 +3 3 + +ti,index-power-of-two - valid divisor values are powers of two. E.g: +register value actual divisor value +0 1 +1 2 +2 4 + +Additionally an array of valid dividers may be supplied like so: + + ti,dividers = <4>, <8>, <0>, <16>; + +Which will map the resulting values to a divisor table by their index: +register value actual divisor value +0 4 +1 8 +2 +3 16 + +Any zero value in this array means the corresponding bit-value is invalid +and must not be used. + +The binding must also provide the register to control the divider and +unless the divider array is provided, min and max dividers. Optionally +the number of bits to shift that mask, if necessary. If the shift value +is missing it is the same as supplying a zero shift. + +This binding can also optionally provide support to the hardware autoidle +feature, see [2]. + +[1] Documentation/devicetree/bindings/clock/clock-bindings.txt +[2] Documentation/devicetree/bindings/clock/ti/autoidle.txt + +Required properties: +- compatible : shall be "ti,divider-clock" or "ti,composite-divider-clock". +- #clock-cells : from common clock binding; shall be set to 0. +- clocks : link to phandle of parent clock +- reg : offset for register controlling adjustable divider + +Optional properties: +- clock-output-names : from common clock binding. +- ti,dividers : array of integers defining divisors +- ti,bit-shift : number of bits to shift the divider value, defaults to 0 +- ti,min-div : min divisor for dividing the input clock rate, only + needed if the first divisor is offset from the default value (1) +- ti,max-div : max divisor for dividing the input clock rate, only needed + if ti,dividers is not defined. +- ti,index-starts-at-one : valid divisor programming starts at 1, not zero, + only valid if ti,dividers is not defined. +- ti,index-power-of-two : valid divisor programming must be a power of two, + only valid if ti,dividers is not defined. +- ti,autoidle-shift : bit shift of the autoidle enable bit for the clock, + see [2] +- ti,invert-autoidle-bit : autoidle is enabled by setting the bit to 0, + see [2] +- ti,set-rate-parent : clk_set_rate is propagated to parent + +Examples: +dpll_usb_m2_ck: dpll_usb_m2_ck@4a008190 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll_usb_ck>; + ti,max-div = <127>; + reg = <0x190>; + ti,index-starts-at-one; +}; + +aess_fclk: aess_fclk@4a004528 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&abe_clk>; + ti,bit-shift = <24>; + reg = <0x528>; + ti,max-div = <2>; +}; + +dpll_core_m3x2_div_ck: dpll_core_m3x2_div_ck { + #clock-cells = <0>; + compatible = "ti,composite-divider-clock"; + clocks = <&dpll_core_x2_ck>; + ti,max-div = <31>; + reg = <0x0134>; + ti,index-starts-at-one; +}; + +ssi_ssr_div_fck_3430es2: ssi_ssr_div_fck_3430es2 { + #clock-cells = <0>; + compatible = "ti,composite-divider-clock"; + clocks = <&corex2_fck>; + ti,bit-shift = <8>; + reg = <0x0a40>; + ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>; +}; diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile index ac4ea50672ed..8690b0b442c0 100644 --- a/drivers/clk/ti/Makefile +++ b/drivers/clk/ti/Makefile @@ -1,4 +1,4 @@ ifneq ($(CONFIG_OF),) obj-y += clk.o autoidle.o -clk-common = dpll.o composite.o +clk-common = dpll.o composite.o divider.o endif diff --git a/drivers/clk/ti/composite.c b/drivers/clk/ti/composite.c index 6539b650cae0..ffb8db4829bf 100644 --- a/drivers/clk/ti/composite.c +++ b/drivers/clk/ti/composite.c @@ -31,7 +31,7 @@ static unsigned long ti_composite_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { - return clk_divider_ops.recalc_rate(hw, parent_rate); + return ti_clk_divider_ops.recalc_rate(hw, parent_rate); } static long ti_composite_round_rate(struct clk_hw *hw, unsigned long rate, diff --git a/drivers/clk/ti/divider.c b/drivers/clk/ti/divider.c new file mode 100644 index 000000000000..a15e445570b2 --- /dev/null +++ b/drivers/clk/ti/divider.c @@ -0,0 +1,487 @@ +/* + * TI Divider Clock + * + * Copyright (C) 2013 Texas Instruments, Inc. + * + * Tero Kristo + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include + +#undef pr_fmt +#define pr_fmt(fmt) "%s: " fmt, __func__ + +#define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw) + +#define div_mask(d) ((1 << ((d)->width)) - 1) + +static unsigned int _get_table_maxdiv(const struct clk_div_table *table) +{ + unsigned int maxdiv = 0; + const struct clk_div_table *clkt; + + for (clkt = table; clkt->div; clkt++) + if (clkt->div > maxdiv) + maxdiv = clkt->div; + return maxdiv; +} + +static unsigned int _get_maxdiv(struct clk_divider *divider) +{ + if (divider->flags & CLK_DIVIDER_ONE_BASED) + return div_mask(divider); + if (divider->flags & CLK_DIVIDER_POWER_OF_TWO) + return 1 << div_mask(divider); + if (divider->table) + return _get_table_maxdiv(divider->table); + return div_mask(divider) + 1; +} + +static unsigned int _get_table_div(const struct clk_div_table *table, + unsigned int val) +{ + const struct clk_div_table *clkt; + + for (clkt = table; clkt->div; clkt++) + if (clkt->val == val) + return clkt->div; + return 0; +} + +static unsigned int _get_div(struct clk_divider *divider, unsigned int val) +{ + if (divider->flags & CLK_DIVIDER_ONE_BASED) + return val; + if (divider->flags & CLK_DIVIDER_POWER_OF_TWO) + return 1 << val; + if (divider->table) + return _get_table_div(divider->table, val); + return val + 1; +} + +static unsigned int _get_table_val(const struct clk_div_table *table, + unsigned int div) +{ + const struct clk_div_table *clkt; + + for (clkt = table; clkt->div; clkt++) + if (clkt->div == div) + return clkt->val; + return 0; +} + +static unsigned int _get_val(struct clk_divider *divider, u8 div) +{ + if (divider->flags & CLK_DIVIDER_ONE_BASED) + return div; + if (divider->flags & CLK_DIVIDER_POWER_OF_TWO) + return __ffs(div); + if (divider->table) + return _get_table_val(divider->table, div); + return div - 1; +} + +static unsigned long ti_clk_divider_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct clk_divider *divider = to_clk_divider(hw); + unsigned int div, val; + + val = ti_clk_ll_ops->clk_readl(divider->reg) >> divider->shift; + val &= div_mask(divider); + + div = _get_div(divider, val); + if (!div) { + WARN(!(divider->flags & CLK_DIVIDER_ALLOW_ZERO), + "%s: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set\n", + __clk_get_name(hw->clk)); + return parent_rate; + } + + return parent_rate / div; +} + +/* + * The reverse of DIV_ROUND_UP: The maximum number which + * divided by m is r + */ +#define MULT_ROUND_UP(r, m) ((r) * (m) + (m) - 1) + +static bool _is_valid_table_div(const struct clk_div_table *table, + unsigned int div) +{ + const struct clk_div_table *clkt; + + for (clkt = table; clkt->div; clkt++) + if (clkt->div == div) + return true; + return false; +} + +static bool _is_valid_div(struct clk_divider *divider, unsigned int div) +{ + if (divider->flags & CLK_DIVIDER_POWER_OF_TWO) + return is_power_of_2(div); + if (divider->table) + return _is_valid_table_div(divider->table, div); + return true; +} + +static int ti_clk_divider_bestdiv(struct clk_hw *hw, unsigned long rate, + unsigned long *best_parent_rate) +{ + struct clk_divider *divider = to_clk_divider(hw); + int i, bestdiv = 0; + unsigned long parent_rate, best = 0, now, maxdiv; + unsigned long parent_rate_saved = *best_parent_rate; + + if (!rate) + rate = 1; + + maxdiv = _get_maxdiv(divider); + + if (!(__clk_get_flags(hw->clk) & CLK_SET_RATE_PARENT)) { + parent_rate = *best_parent_rate; + bestdiv = DIV_ROUND_UP(parent_rate, rate); + bestdiv = bestdiv == 0 ? 1 : bestdiv; + bestdiv = bestdiv > maxdiv ? maxdiv : bestdiv; + return bestdiv; + } + + /* + * The maximum divider we can use without overflowing + * unsigned long in rate * i below + */ + maxdiv = min(ULONG_MAX / rate, maxdiv); + + for (i = 1; i <= maxdiv; i++) { + if (!_is_valid_div(divider, i)) + continue; + if (rate * i == parent_rate_saved) { + /* + * It's the most ideal case if the requested rate can be + * divided from parent clock without needing to change + * parent rate, so return the divider immediately. + */ + *best_parent_rate = parent_rate_saved; + return i; + } + parent_rate = __clk_round_rate(__clk_get_parent(hw->clk), + MULT_ROUND_UP(rate, i)); + now = parent_rate / i; + if (now <= rate && now > best) { + bestdiv = i; + best = now; + *best_parent_rate = parent_rate; + } + } + + if (!bestdiv) { + bestdiv = _get_maxdiv(divider); + *best_parent_rate = + __clk_round_rate(__clk_get_parent(hw->clk), 1); + } + + return bestdiv; +} + +static long ti_clk_divider_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *prate) +{ + int div; + div = ti_clk_divider_bestdiv(hw, rate, prate); + + return *prate / div; +} + +static int ti_clk_divider_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct clk_divider *divider = to_clk_divider(hw); + unsigned int div, value; + unsigned long flags = 0; + u32 val; + + div = parent_rate / rate; + value = _get_val(divider, div); + + if (value > div_mask(divider)) + value = div_mask(divider); + + if (divider->lock) + spin_lock_irqsave(divider->lock, flags); + + if (divider->flags & CLK_DIVIDER_HIWORD_MASK) { + val = div_mask(divider) << (divider->shift + 16); + } else { + val = ti_clk_ll_ops->clk_readl(divider->reg); + val &= ~(div_mask(divider) << divider->shift); + } + val |= value << divider->shift; + ti_clk_ll_ops->clk_writel(val, divider->reg); + + if (divider->lock) + spin_unlock_irqrestore(divider->lock, flags); + + return 0; +} + +const struct clk_ops ti_clk_divider_ops = { + .recalc_rate = ti_clk_divider_recalc_rate, + .round_rate = ti_clk_divider_round_rate, + .set_rate = ti_clk_divider_set_rate, +}; + +static struct clk *_register_divider(struct device *dev, const char *name, + const char *parent_name, + unsigned long flags, void __iomem *reg, + u8 shift, u8 width, u8 clk_divider_flags, + const struct clk_div_table *table, + spinlock_t *lock) +{ + struct clk_divider *div; + struct clk *clk; + struct clk_init_data init; + + if (clk_divider_flags & CLK_DIVIDER_HIWORD_MASK) { + if (width + shift > 16) { + pr_warn("divider value exceeds LOWORD field\n"); + return ERR_PTR(-EINVAL); + } + } + + /* allocate the divider */ + div = kzalloc(sizeof(*div), GFP_KERNEL); + if (!div) { + pr_err("%s: could not allocate divider clk\n", __func__); + return ERR_PTR(-ENOMEM); + } + + init.name = name; + init.ops = &ti_clk_divider_ops; + init.flags = flags | CLK_IS_BASIC; + init.parent_names = (parent_name ? &parent_name : NULL); + init.num_parents = (parent_name ? 1 : 0); + + /* struct clk_divider assignments */ + div->reg = reg; + div->shift = shift; + div->width = width; + div->flags = clk_divider_flags; + div->lock = lock; + div->hw.init = &init; + div->table = table; + + /* register the clock */ + clk = clk_register(dev, &div->hw); + + if (IS_ERR(clk)) + kfree(div); + + return clk; +} + +static struct clk_div_table +__init *ti_clk_get_div_table(struct device_node *node) +{ + struct clk_div_table *table; + const __be32 *divspec; + u32 val; + u32 num_div; + u32 valid_div; + int i; + + divspec = of_get_property(node, "ti,dividers", &num_div); + + if (!divspec) + return NULL; + + num_div /= 4; + + valid_div = 0; + + /* Determine required size for divider table */ + for (i = 0; i < num_div; i++) { + of_property_read_u32_index(node, "ti,dividers", i, &val); + if (val) + valid_div++; + } + + if (!valid_div) { + pr_err("no valid dividers for %s table\n", node->name); + return ERR_PTR(-EINVAL); + } + + table = kzalloc(sizeof(*table) * (valid_div + 1), GFP_KERNEL); + + if (!table) + return ERR_PTR(-ENOMEM); + + valid_div = 0; + + for (i = 0; i < num_div; i++) { + of_property_read_u32_index(node, "ti,dividers", i, &val); + if (val) { + table[valid_div].div = val; + table[valid_div].val = i; + valid_div++; + } + } + + return table; +} + +static int _get_divider_width(struct device_node *node, + const struct clk_div_table *table, + u8 flags) +{ + u32 min_div; + u32 max_div; + u32 val = 0; + u32 div; + + if (!table) { + /* Clk divider table not provided, determine min/max divs */ + if (of_property_read_u32(node, "ti,min-div", &min_div)) + min_div = 1; + + if (of_property_read_u32(node, "ti,max-div", &max_div)) { + pr_err("no max-div for %s!\n", node->name); + return -EINVAL; + } + + /* Determine bit width for the field */ + if (flags & CLK_DIVIDER_ONE_BASED) + val = 1; + + div = min_div; + + while (div < max_div) { + if (flags & CLK_DIVIDER_POWER_OF_TWO) + div <<= 1; + else + div++; + val++; + } + } else { + div = 0; + + while (table[div].div) { + val = table[div].val; + div++; + } + } + + return fls(val); +} + +static int __init ti_clk_divider_populate(struct device_node *node, + void __iomem **reg, const struct clk_div_table **table, + u32 *flags, u8 *div_flags, u8 *width, u8 *shift) +{ + u32 val; + + *reg = ti_clk_get_reg_addr(node, 0); + if (!*reg) + return -EINVAL; + + if (!of_property_read_u32(node, "ti,bit-shift", &val)) + *shift = val; + else + *shift = 0; + + *flags = 0; + *div_flags = 0; + + if (of_property_read_bool(node, "ti,index-starts-at-one")) + *div_flags |= CLK_DIVIDER_ONE_BASED; + + if (of_property_read_bool(node, "ti,index-power-of-two")) + *div_flags |= CLK_DIVIDER_POWER_OF_TWO; + + if (of_property_read_bool(node, "ti,set-rate-parent")) + *flags |= CLK_SET_RATE_PARENT; + + *table = ti_clk_get_div_table(node); + + if (IS_ERR(*table)) + return PTR_ERR(*table); + + *width = _get_divider_width(node, *table, *div_flags); + + return 0; +} + +/** + * of_ti_divider_clk_setup - Setup function for simple div rate clock + * @node: device node for this clock + * + * Sets up a basic divider clock. + */ +static void __init of_ti_divider_clk_setup(struct device_node *node) +{ + struct clk *clk; + const char *parent_name; + void __iomem *reg; + u8 clk_divider_flags = 0; + u8 width = 0; + u8 shift = 0; + const struct clk_div_table *table = NULL; + u32 flags = 0; + + parent_name = of_clk_get_parent_name(node, 0); + + if (ti_clk_divider_populate(node, ®, &table, &flags, + &clk_divider_flags, &width, &shift)) + goto cleanup; + + clk = _register_divider(NULL, node->name, parent_name, flags, reg, + shift, width, clk_divider_flags, table, NULL); + + if (!IS_ERR(clk)) { + of_clk_add_provider(node, of_clk_src_simple_get, clk); + of_ti_clk_autoidle_setup(node); + return; + } + +cleanup: + kfree(table); +} +CLK_OF_DECLARE(divider_clk, "ti,divider-clock", of_ti_divider_clk_setup); + +static void __init of_ti_composite_divider_clk_setup(struct device_node *node) +{ + struct clk_divider *div; + u32 val; + + div = kzalloc(sizeof(*div), GFP_KERNEL); + if (!div) + return; + + if (ti_clk_divider_populate(node, &div->reg, &div->table, &val, + &div->flags, &div->width, &div->shift) < 0) + goto cleanup; + + if (!ti_clk_add_component(node, &div->hw, CLK_COMPONENT_TYPE_DIVIDER)) + return; + +cleanup: + kfree(div->table); + kfree(div); +} +CLK_OF_DECLARE(ti_composite_divider_clk, "ti,composite-divider-clock", + of_ti_composite_divider_clk_setup); diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h index c8c591dd3261..17fb49e4ff5e 100644 --- a/include/linux/clk/ti.h +++ b/include/linux/clk/ti.h @@ -223,6 +223,8 @@ struct ti_clk_ll_ops { extern struct ti_clk_ll_ops *ti_clk_ll_ops; +extern const struct clk_ops ti_clk_divider_ops; + #define to_clk_hw_omap(_hw) container_of(_hw, struct clk_hw_omap, hw) void omap2_init_clk_hw_omap_clocks(struct clk *clk); -- cgit v1.2.3-59-g8ed1b From 1f847c65fd569c1d822800ba3e7e18c6411a7d50 Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Fri, 13 Sep 2013 14:57:59 +0300 Subject: clk: ti: add support for TI fixed factor clock This behaves exactly in similar manner to basic fixed-factor-clock, but adds a few properties on top for handling clock hardware autoidling. Signed-off-by: Tero Kristo Acked-by: Tony Lindgren Signed-off-by: Mike Turquette --- .../bindings/clock/ti/fixed-factor-clock.txt | 43 ++++++++++++++ drivers/clk/ti/Makefile | 3 +- drivers/clk/ti/fixed-factor.c | 66 ++++++++++++++++++++++ 3 files changed, 111 insertions(+), 1 deletion(-) create mode 100644 Documentation/devicetree/bindings/clock/ti/fixed-factor-clock.txt create mode 100644 drivers/clk/ti/fixed-factor.c diff --git a/Documentation/devicetree/bindings/clock/ti/fixed-factor-clock.txt b/Documentation/devicetree/bindings/clock/ti/fixed-factor-clock.txt new file mode 100644 index 000000000000..662b36d53bf0 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/ti/fixed-factor-clock.txt @@ -0,0 +1,43 @@ +Binding for TI fixed factor rate clock sources. + +Binding status: Unstable - ABI compatibility may be broken in the future + +This binding uses the common clock binding[1], and also uses the autoidle +support from TI autoidle clock [2]. + +[1] Documentation/devicetree/bindings/clock/clock-bindings.txt +[2] Documentation/devicetree/bindings/clock/ti/autoidle.txt + +Required properties: +- compatible : shall be "ti,fixed-factor-clock". +- #clock-cells : from common clock binding; shall be set to 0. +- ti,clock-div: fixed divider. +- ti,clock-mult: fixed multiplier. +- clocks: parent clock. + +Optional properties: +- ti,autoidle-shift: bit shift of the autoidle enable bit for the clock, + see [2] +- reg: offset for the autoidle register of this clock, see [2] +- ti,invert-autoidle-bit: autoidle is enabled by setting the bit to 0, see [2] +- ti,set-rate-parent: clk_set_rate is propagated to parent + +Example: + clock { + compatible = "ti,fixed-factor-clock"; + clocks = <&parentclk>; + #clock-cells = <0>; + ti,clock-div = <2>; + ti,clock-mult = <1>; + }; + + dpll_usb_clkdcoldo_ck: dpll_usb_clkdcoldo_ck { + #clock-cells = <0>; + compatible = "ti,fixed-factor-clock"; + clocks = <&dpll_usb_ck>; + ti,clock-div = <1>; + ti,autoidle-shift = <8>; + reg = <0x01b4>; + ti,clock-mult = <1>; + ti,invert-autoidle-bit; + }; diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile index 8690b0b442c0..d3586252a391 100644 --- a/drivers/clk/ti/Makefile +++ b/drivers/clk/ti/Makefile @@ -1,4 +1,5 @@ ifneq ($(CONFIG_OF),) obj-y += clk.o autoidle.o -clk-common = dpll.o composite.o divider.o +clk-common = dpll.o composite.o divider.o \ + fixed-factor.o endif diff --git a/drivers/clk/ti/fixed-factor.c b/drivers/clk/ti/fixed-factor.c new file mode 100644 index 000000000000..c2c8a287408c --- /dev/null +++ b/drivers/clk/ti/fixed-factor.c @@ -0,0 +1,66 @@ +/* + * TI Fixed Factor Clock + * + * Copyright (C) 2013 Texas Instruments, Inc. + * + * Tero Kristo + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include + +#undef pr_fmt +#define pr_fmt(fmt) "%s: " fmt, __func__ + +/** + * of_ti_fixed_factor_clk_setup - Setup function for TI fixed factor clock + * @node: device node for this clock + * + * Sets up a simple fixed factor clock based on device tree info. + */ +static void __init of_ti_fixed_factor_clk_setup(struct device_node *node) +{ + struct clk *clk; + const char *clk_name = node->name; + const char *parent_name; + u32 div, mult; + u32 flags = 0; + + if (of_property_read_u32(node, "ti,clock-div", &div)) { + pr_err("%s must have a clock-div property\n", node->name); + return; + } + + if (of_property_read_u32(node, "ti,clock-mult", &mult)) { + pr_err("%s must have a clock-mult property\n", node->name); + return; + } + + if (of_property_read_bool(node, "ti,set-rate-parent")) + flags |= CLK_SET_RATE_PARENT; + + parent_name = of_clk_get_parent_name(node, 0); + + clk = clk_register_fixed_factor(NULL, clk_name, parent_name, flags, + mult, div); + + if (!IS_ERR(clk)) { + of_clk_add_provider(node, of_clk_src_simple_get, clk); + of_ti_clk_autoidle_setup(node); + } +} +CLK_OF_DECLARE(ti_fixed_factor_clk, "ti,fixed-factor-clock", + of_ti_fixed_factor_clk_setup); -- cgit v1.2.3-59-g8ed1b From f60b1ea5ea7ab1aee34a5ba55520b84b6e6d482e Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Tue, 18 Jun 2013 18:55:59 +0300 Subject: CLK: TI: add support for gate clock This patch adds support for TI specific gate clocks. These behave as basic gate-clock, but have different ops / hw-ops for controlling the actual gate, for example waiting until the clock is ready. Several sub-types are supported: - ti,gate-clock: basic gate clock with default ops/hwops - ti,clkdm-gate-clock: clockdomain level gate control - ti,dss-gate-clock: gate clock with DSS specific hardware handling - ti,am35xx-gate-clock: gate clock with AM35xx specific hardware handling - ti,hsdiv-gate-clock: gate clock with OMAP36xx hardware errata handling Signed-off-by: Tero Kristo Acked-by: Tony Lindgren Signed-off-by: Mike Turquette --- .../devicetree/bindings/clock/ti/gate.txt | 85 +++++++ drivers/clk/ti/Makefile | 2 +- drivers/clk/ti/gate.c | 249 +++++++++++++++++++++ include/linux/clk/ti.h | 6 + 4 files changed, 341 insertions(+), 1 deletion(-) create mode 100644 Documentation/devicetree/bindings/clock/ti/gate.txt create mode 100644 drivers/clk/ti/gate.c diff --git a/Documentation/devicetree/bindings/clock/ti/gate.txt b/Documentation/devicetree/bindings/clock/ti/gate.txt new file mode 100644 index 000000000000..125281aaa4ca --- /dev/null +++ b/Documentation/devicetree/bindings/clock/ti/gate.txt @@ -0,0 +1,85 @@ +Binding for Texas Instruments gate clock. + +Binding status: Unstable - ABI compatibility may be broken in the future + +This binding uses the common clock binding[1]. This clock is +quite much similar to the basic gate-clock [2], however, +it supports a number of additional features. If no register +is provided for this clock, the code assumes that a clockdomain +will be controlled instead and the corresponding hw-ops for +that is used. + +[1] Documentation/devicetree/bindings/clock/clock-bindings.txt +[2] Documentation/devicetree/bindings/clock/gate-clock.txt +[3] Documentation/devicetree/bindings/clock/ti/clockdomain.txt + +Required properties: +- compatible : shall be one of: + "ti,gate-clock" - basic gate clock + "ti,wait-gate-clock" - gate clock which waits until clock is active before + returning from clk_enable() + "ti,dss-gate-clock" - gate clock with DSS specific hardware handling + "ti,am35xx-gate-clock" - gate clock with AM35xx specific hardware handling + "ti,clkdm-gate-clock" - clockdomain gate clock, which derives its functional + clock directly from a clockdomain, see [3] how + to map clockdomains properly + "ti,hsdiv-gate-clock" - gate clock with OMAP36xx specific hardware handling, + required for a hardware errata +- #clock-cells : from common clock binding; shall be set to 0 +- clocks : link to phandle of parent clock +- reg : offset for register controlling adjustable gate, not needed for + ti,clkdm-gate-clock type + +Optional properties: +- ti,bit-shift : bit shift for programming the clock gate, invalid for + ti,clkdm-gate-clock type +- ti,set-bit-to-disable : inverts default gate programming. Setting the bit + gates the clock and clearing the bit ungates the clock. + +Examples: + mmchs2_fck: mmchs2_fck@48004a00 { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&core_96m_fck>; + reg = <0x48004a00 0x4>; + ti,bit-shift = <25>; + }; + + uart4_fck_am35xx: uart4_fck_am35xx { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clocks = <&core_48m_fck>; + reg = <0x0a00>; + ti,bit-shift = <23>; + }; + + dss1_alwon_fck_3430es2: dss1_alwon_fck_3430es2@48004e00 { + #clock-cells = <0>; + compatible = "ti,dss-gate-clock"; + clocks = <&dpll4_m4x2_ck>; + reg = <0x48004e00 0x4>; + ti,bit-shift = <0>; + }; + + emac_ick: emac_ick@4800259c { + #clock-cells = <0>; + compatible = "ti,am35xx-gate-clock"; + clocks = <&ipss_ick>; + reg = <0x4800259c 0x4>; + ti,bit-shift = <1>; + }; + + emu_src_ck: emu_src_ck { + #clock-cells = <0>; + compatible = "ti,clkdm-gate-clock"; + clocks = <&emu_src_mux_ck>; + }; + + dpll4_m2x2_ck: dpll4_m2x2_ck@48004d00 { + #clock-cells = <0>; + compatible = "ti,hsdiv-gate-clock"; + clocks = <&dpll4_m2x2_mul_ck>; + ti,bit-shift = <0x1b>; + reg = <0x48004d00 0x4>; + ti,set-bit-to-disable; + }; diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile index d3586252a391..eaa6dc0aeb75 100644 --- a/drivers/clk/ti/Makefile +++ b/drivers/clk/ti/Makefile @@ -1,5 +1,5 @@ ifneq ($(CONFIG_OF),) obj-y += clk.o autoidle.o -clk-common = dpll.o composite.o divider.o \ +clk-common = dpll.o composite.o divider.o gate.o \ fixed-factor.o endif diff --git a/drivers/clk/ti/gate.c b/drivers/clk/ti/gate.c new file mode 100644 index 000000000000..3e2999d11d15 --- /dev/null +++ b/drivers/clk/ti/gate.c @@ -0,0 +1,249 @@ +/* + * OMAP gate clock support + * + * Copyright (C) 2013 Texas Instruments, Inc. + * + * Tero Kristo + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include + +#define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw) + +#undef pr_fmt +#define pr_fmt(fmt) "%s: " fmt, __func__ + +static int omap36xx_gate_clk_enable_with_hsdiv_restore(struct clk_hw *clk); + +static const struct clk_ops omap_gate_clkdm_clk_ops = { + .init = &omap2_init_clk_clkdm, + .enable = &omap2_clkops_enable_clkdm, + .disable = &omap2_clkops_disable_clkdm, +}; + +static const struct clk_ops omap_gate_clk_ops = { + .init = &omap2_init_clk_clkdm, + .enable = &omap2_dflt_clk_enable, + .disable = &omap2_dflt_clk_disable, + .is_enabled = &omap2_dflt_clk_is_enabled, +}; + +static const struct clk_ops omap_gate_clk_hsdiv_restore_ops = { + .init = &omap2_init_clk_clkdm, + .enable = &omap36xx_gate_clk_enable_with_hsdiv_restore, + .disable = &omap2_dflt_clk_disable, + .is_enabled = &omap2_dflt_clk_is_enabled, +}; + +/** + * omap36xx_gate_clk_enable_with_hsdiv_restore - enable clocks suffering + * from HSDivider PWRDN problem Implements Errata ID: i556. + * @clk: DPLL output struct clk + * + * 3630 only: dpll3_m3_ck, dpll4_m2_ck, dpll4_m3_ck, dpll4_m4_ck, + * dpll4_m5_ck & dpll4_m6_ck dividers gets loaded with reset + * valueafter their respective PWRDN bits are set. Any dummy write + * (Any other value different from the Read value) to the + * corresponding CM_CLKSEL register will refresh the dividers. + */ +static int omap36xx_gate_clk_enable_with_hsdiv_restore(struct clk_hw *clk) +{ + struct clk_divider *parent; + struct clk_hw *parent_hw; + u32 dummy_v, orig_v; + int ret; + + /* Clear PWRDN bit of HSDIVIDER */ + ret = omap2_dflt_clk_enable(clk); + + /* Parent is the x2 node, get parent of parent for the m2 div */ + parent_hw = __clk_get_hw(__clk_get_parent(__clk_get_parent(clk->clk))); + parent = to_clk_divider(parent_hw); + + /* Restore the dividers */ + if (!ret) { + orig_v = ti_clk_ll_ops->clk_readl(parent->reg); + dummy_v = orig_v; + + /* Write any other value different from the Read value */ + dummy_v ^= (1 << parent->shift); + ti_clk_ll_ops->clk_writel(dummy_v, parent->reg); + + /* Write the original divider */ + ti_clk_ll_ops->clk_writel(orig_v, parent->reg); + } + + return ret; +} + +static void __init _of_ti_gate_clk_setup(struct device_node *node, + const struct clk_ops *ops, + const struct clk_hw_omap_ops *hw_ops) +{ + struct clk *clk; + struct clk_init_data init = { NULL }; + struct clk_hw_omap *clk_hw; + const char *clk_name = node->name; + const char *parent_name; + u32 val; + + clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL); + if (!clk_hw) + return; + + clk_hw->hw.init = &init; + + init.name = clk_name; + init.ops = ops; + + if (ops != &omap_gate_clkdm_clk_ops) { + clk_hw->enable_reg = ti_clk_get_reg_addr(node, 0); + if (!clk_hw->enable_reg) + goto cleanup; + + if (!of_property_read_u32(node, "ti,bit-shift", &val)) + clk_hw->enable_bit = val; + } + + clk_hw->ops = hw_ops; + + clk_hw->flags = MEMMAP_ADDRESSING; + + if (of_clk_get_parent_count(node) != 1) { + pr_err("%s must have 1 parent\n", clk_name); + goto cleanup; + } + + parent_name = of_clk_get_parent_name(node, 0); + init.parent_names = &parent_name; + init.num_parents = 1; + + if (of_property_read_bool(node, "ti,set-rate-parent")) + init.flags |= CLK_SET_RATE_PARENT; + + if (of_property_read_bool(node, "ti,set-bit-to-disable")) + clk_hw->flags |= INVERT_ENABLE; + + clk = clk_register(NULL, &clk_hw->hw); + + if (!IS_ERR(clk)) { + of_clk_add_provider(node, of_clk_src_simple_get, clk); + return; + } + +cleanup: + kfree(clk_hw); +} + +static void __init +_of_ti_composite_gate_clk_setup(struct device_node *node, + const struct clk_hw_omap_ops *hw_ops) +{ + struct clk_hw_omap *gate; + u32 val = 0; + + gate = kzalloc(sizeof(*gate), GFP_KERNEL); + if (!gate) + return; + + gate->enable_reg = ti_clk_get_reg_addr(node, 0); + if (!gate->enable_reg) + goto cleanup; + + of_property_read_u32(node, "ti,bit-shift", &val); + + gate->enable_bit = val; + gate->ops = hw_ops; + gate->flags = MEMMAP_ADDRESSING; + + if (!ti_clk_add_component(node, &gate->hw, CLK_COMPONENT_TYPE_GATE)) + return; + +cleanup: + kfree(gate); +} + +static void __init +of_ti_composite_no_wait_gate_clk_setup(struct device_node *node) +{ + _of_ti_composite_gate_clk_setup(node, NULL); +} +CLK_OF_DECLARE(ti_composite_no_wait_gate_clk, "ti,composite-no-wait-gate-clock", + of_ti_composite_no_wait_gate_clk_setup); + +#ifdef CONFIG_ARCH_OMAP3 +static void __init of_ti_composite_interface_clk_setup(struct device_node *node) +{ + _of_ti_composite_gate_clk_setup(node, &clkhwops_iclk_wait); +} +CLK_OF_DECLARE(ti_composite_interface_clk, "ti,composite-interface-clock", + of_ti_composite_interface_clk_setup); +#endif + +static void __init of_ti_composite_gate_clk_setup(struct device_node *node) +{ + _of_ti_composite_gate_clk_setup(node, &clkhwops_wait); +} +CLK_OF_DECLARE(ti_composite_gate_clk, "ti,composite-gate-clock", + of_ti_composite_gate_clk_setup); + + +static void __init of_ti_clkdm_gate_clk_setup(struct device_node *node) +{ + _of_ti_gate_clk_setup(node, &omap_gate_clkdm_clk_ops, NULL); +} +CLK_OF_DECLARE(ti_clkdm_gate_clk, "ti,clkdm-gate-clock", + of_ti_clkdm_gate_clk_setup); + +static void __init of_ti_hsdiv_gate_clk_setup(struct device_node *node) +{ + _of_ti_gate_clk_setup(node, &omap_gate_clk_hsdiv_restore_ops, + &clkhwops_wait); +} +CLK_OF_DECLARE(ti_hsdiv_gate_clk, "ti,hsdiv-gate-clock", + of_ti_hsdiv_gate_clk_setup); + +static void __init of_ti_gate_clk_setup(struct device_node *node) +{ + _of_ti_gate_clk_setup(node, &omap_gate_clk_ops, NULL); +} +CLK_OF_DECLARE(ti_gate_clk, "ti,gate-clock", of_ti_gate_clk_setup) + +static void __init of_ti_wait_gate_clk_setup(struct device_node *node) +{ + _of_ti_gate_clk_setup(node, &omap_gate_clk_ops, &clkhwops_wait); +} +CLK_OF_DECLARE(ti_wait_gate_clk, "ti,wait-gate-clock", + of_ti_wait_gate_clk_setup); + +#ifdef CONFIG_ARCH_OMAP3 +static void __init of_ti_am35xx_gate_clk_setup(struct device_node *node) +{ + _of_ti_gate_clk_setup(node, &omap_gate_clk_ops, + &clkhwops_am35xx_ipss_module_wait); +} +CLK_OF_DECLARE(ti_am35xx_gate_clk, "ti,am35xx-gate-clock", + of_ti_am35xx_gate_clk_setup); + +static void __init of_ti_dss_gate_clk_setup(struct device_node *node) +{ + _of_ti_gate_clk_setup(node, &omap_gate_clk_ops, + &clkhwops_omap3430es2_dss_usbhost_wait); +} +CLK_OF_DECLARE(ti_dss_gate_clk, "ti,dss-gate-clock", + of_ti_dss_gate_clk_setup); +#endif diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h index 17fb49e4ff5e..d94feb3b5519 100644 --- a/include/linux/clk/ti.h +++ b/include/linux/clk/ti.h @@ -244,6 +244,8 @@ long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate, void omap2_init_clk_clkdm(struct clk_hw *clk); unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw, unsigned long parent_rate); +int omap2_clkops_enable_clkdm(struct clk_hw *hw); +void omap2_clkops_disable_clkdm(struct clk_hw *hw); int omap3_dpll4_set_rate(struct clk_hw *clk, unsigned long rate, unsigned long parent_rate); int omap2_dflt_clk_enable(struct clk_hw *hw); @@ -268,5 +270,9 @@ static inline void of_ti_clk_deny_autoidle_all(void) { } extern const struct clk_hw_omap_ops clkhwops_omap3_dpll; extern const struct clk_hw_omap_ops clkhwops_omap4_dpllmx; +extern const struct clk_hw_omap_ops clkhwops_wait; +extern const struct clk_hw_omap_ops clkhwops_omap3430es2_dss_usbhost_wait; +extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_module_wait; +extern const struct clk_hw_omap_ops clkhwops_iclk_wait; #endif -- cgit v1.2.3-59-g8ed1b From 3cd4a596224565cff00b69a02d4b5fa7432ea6d3 Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Wed, 21 Aug 2013 19:39:15 +0300 Subject: CLK: TI: add support for clockdomain binding Some OMAP clocks require knowledge about their parent clockdomain for book keeping purposes. This patch creates a new DT binding for TI clockdomains, which act as a collection of device clocks. Clockdomain itself is rather misleading name for the hardware functionality, as at least on OMAP4 / OMAP5 / DRA7 the clockdomains can be collections of either clocks and/or IP blocks, thus idle-domain or such might be more appropriate. For most cases on these SoCs, the kernel doesn't even need the information and the mappings can be ignored. Signed-off-by: Tero Kristo Acked-by: Tony Lindgren Signed-off-by: Mike Turquette --- .../devicetree/bindings/clock/ti/clockdomain.txt | 24 ++++++++ drivers/clk/ti/Makefile | 2 +- drivers/clk/ti/clockdomain.c | 70 ++++++++++++++++++++++ include/linux/clk/ti.h | 1 + 4 files changed, 96 insertions(+), 1 deletion(-) create mode 100644 Documentation/devicetree/bindings/clock/ti/clockdomain.txt create mode 100644 drivers/clk/ti/clockdomain.c diff --git a/Documentation/devicetree/bindings/clock/ti/clockdomain.txt b/Documentation/devicetree/bindings/clock/ti/clockdomain.txt new file mode 100644 index 000000000000..cb76b3f2b341 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/ti/clockdomain.txt @@ -0,0 +1,24 @@ +Binding for Texas Instruments clockdomain. + +Binding status: Unstable - ABI compatibility may be broken in the future + +This binding uses the common clock binding[1] in consumer role. +Every clock on TI SoC belongs to one clockdomain, but software +only needs this information for specific clocks which require +their parent clockdomain to be controlled when the clock is +enabled/disabled. This binding doesn't define a new clock +binding type, it is used to group existing clock nodes under +hardware hierarchy. + +[1] Documentation/devicetree/bindings/clock/clock-bindings.txt + +Required properties: +- compatible : shall be "ti,clockdomain" +- #clock-cells : from common clock binding; shall be set to 0. +- clocks : link phandles of clocks within this domain + +Examples: + dss_clkdm: dss_clkdm { + compatible = "ti,clockdomain"; + clocks = <&dss1_alwon_fck_3430es2>, <&dss_ick_3430es2>; + }; diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile index eaa6dc0aeb75..ae7cd1e91cd2 100644 --- a/drivers/clk/ti/Makefile +++ b/drivers/clk/ti/Makefile @@ -1,5 +1,5 @@ ifneq ($(CONFIG_OF),) -obj-y += clk.o autoidle.o +obj-y += clk.o autoidle.o clockdomain.o clk-common = dpll.o composite.o divider.o gate.o \ fixed-factor.o endif diff --git a/drivers/clk/ti/clockdomain.c b/drivers/clk/ti/clockdomain.c new file mode 100644 index 000000000000..f1e0038d76ac --- /dev/null +++ b/drivers/clk/ti/clockdomain.c @@ -0,0 +1,70 @@ +/* + * OMAP clockdomain support + * + * Copyright (C) 2013 Texas Instruments, Inc. + * + * Tero Kristo + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include + +#undef pr_fmt +#define pr_fmt(fmt) "%s: " fmt, __func__ + +static void __init of_ti_clockdomain_setup(struct device_node *node) +{ + struct clk *clk; + struct clk_hw *clk_hw; + const char *clkdm_name = node->name; + int i; + int num_clks; + + num_clks = of_count_phandle_with_args(node, "clocks", "#clock-cells"); + + for (i = 0; i < num_clks; i++) { + clk = of_clk_get(node, i); + if (__clk_get_flags(clk) & CLK_IS_BASIC) { + pr_warn("can't setup clkdm for basic clk %s\n", + __clk_get_name(clk)); + continue; + } + clk_hw = __clk_get_hw(clk); + to_clk_hw_omap(clk_hw)->clkdm_name = clkdm_name; + omap2_init_clk_clkdm(clk_hw); + } +} + +static struct of_device_id ti_clkdm_match_table[] __initdata = { + { .compatible = "ti,clockdomain" }, + { } +}; + +/** + * ti_dt_clockdomains_setup - setup device tree clockdomains + * + * Initializes clockdomain nodes for a SoC. This parses through all the + * nodes with compatible = "ti,clockdomain", and add the clockdomain + * info for all the clocks listed under these. This function shall be + * called after rest of the DT clock init has completed and all + * clock nodes have been registered. + */ +void __init ti_dt_clockdomains_setup(void) +{ + struct device_node *np; + for_each_matching_node(np, ti_clkdm_match_table) { + of_ti_clockdomain_setup(np); + } +} diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h index d94feb3b5519..a3f89a60de07 100644 --- a/include/linux/clk/ti.h +++ b/include/linux/clk/ti.h @@ -255,6 +255,7 @@ int omap2_dflt_clk_is_enabled(struct clk_hw *hw); void __iomem *ti_clk_get_reg_addr(struct device_node *node, int index); void ti_dt_clocks_register(struct ti_dt_clk *oclks); void ti_dt_clk_init_provider(struct device_node *np, int index); +void ti_dt_clockdomains_setup(void); int ti_clk_retry_init(struct device_node *node, struct clk_hw *hw, ti_of_clk_init_cb_t func); int of_ti_clk_autoidle_setup(struct device_node *node); -- cgit v1.2.3-59-g8ed1b From 6a369c584fbe98264458b9442e780f8078f2f7ad Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Fri, 13 Sep 2013 20:22:27 +0300 Subject: clk: ti: add support for basic mux clock ti,mux-clock provides now a binding for basic mux support. This is just using the basic clock type. Signed-off-by: Tero Kristo Acked-by: Tony Lindgren Signed-off-by: Mike Turquette --- Documentation/devicetree/bindings/clock/ti/mux.txt | 76 +++++++ drivers/clk/ti/Makefile | 2 +- drivers/clk/ti/composite.c | 2 +- drivers/clk/ti/mux.c | 246 +++++++++++++++++++++ include/linux/clk/ti.h | 1 + 5 files changed, 325 insertions(+), 2 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/ti/mux.txt create mode 100644 drivers/clk/ti/mux.c diff --git a/Documentation/devicetree/bindings/clock/ti/mux.txt b/Documentation/devicetree/bindings/clock/ti/mux.txt new file mode 100644 index 000000000000..2d0d170f8001 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/ti/mux.txt @@ -0,0 +1,76 @@ +Binding for TI mux clock. + +Binding status: Unstable - ABI compatibility may be broken in the future + +This binding uses the common clock binding[1]. It assumes a +register-mapped multiplexer with multiple input clock signals or +parents, one of which can be selected as output. This clock does not +gate or adjust the parent rate via a divider or multiplier. + +By default the "clocks" property lists the parents in the same order +as they are programmed into the regster. E.g: + + clocks = <&foo_clock>, <&bar_clock>, <&baz_clock>; + +results in programming the register as follows: + +register value selected parent clock +0 foo_clock +1 bar_clock +2 baz_clock + +Some clock controller IPs do not allow a value of zero to be programmed +into the register, instead indexing begins at 1. The optional property +"index-starts-at-one" modified the scheme as follows: + +register value selected clock parent +1 foo_clock +2 bar_clock +3 baz_clock + +The binding must provide the register to control the mux. Optionally +the number of bits to shift the control field in the register can be +supplied. If the shift value is missing it is the same as supplying +a zero shift. + +[1] Documentation/devicetree/bindings/clock/clock-bindings.txt + +Required properties: +- compatible : shall be "ti,mux-clock" or "ti,composite-mux-clock". +- #clock-cells : from common clock binding; shall be set to 0. +- clocks : link phandles of parent clocks +- reg : register offset for register controlling adjustable mux + +Optional properties: +- ti,bit-shift : number of bits to shift the bit-mask, defaults to + 0 if not present +- ti,index-starts-at-one : valid input select programming starts at 1, not + zero +- ti,set-rate-parent : clk_set_rate is propagated to parent clock, + not supported by the composite-mux-clock subtype + +Examples: + +sys_clkin_ck: sys_clkin_ck@4a306110 { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&virt_12000000_ck>, <&virt_13000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>; + reg = <0x0110>; + ti,index-starts-at-one; +}; + +abe_dpll_bypass_clk_mux_ck: abe_dpll_bypass_clk_mux_ck@4a306108 { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&sys_clkin_ck>, <&sys_32k_ck>; + ti,bit-shift = <24>; + reg = <0x0108>; +}; + +mcbsp5_mux_fck: mcbsp5_mux_fck { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clocks = <&core_96m_fck>, <&mcbsp_clks>; + ti,bit-shift = <4>; + reg = <0x02d8>; +}; diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile index ae7cd1e91cd2..d98a47fb13a4 100644 --- a/drivers/clk/ti/Makefile +++ b/drivers/clk/ti/Makefile @@ -1,5 +1,5 @@ ifneq ($(CONFIG_OF),) obj-y += clk.o autoidle.o clockdomain.o clk-common = dpll.o composite.o divider.o gate.o \ - fixed-factor.o + fixed-factor.o mux.o endif diff --git a/drivers/clk/ti/composite.c b/drivers/clk/ti/composite.c index ffb8db4829bf..19d8980ba458 100644 --- a/drivers/clk/ti/composite.c +++ b/drivers/clk/ti/composite.c @@ -173,7 +173,7 @@ static void __init ti_clk_register_composite(struct clk_hw *hw, clk = clk_register_composite(NULL, node->name, parent_names, num_parents, _get_hw(cclk, CLK_COMPONENT_TYPE_MUX), - &clk_mux_ops, + &ti_clk_mux_ops, _get_hw(cclk, CLK_COMPONENT_TYPE_DIVIDER), &ti_composite_divider_ops, _get_hw(cclk, CLK_COMPONENT_TYPE_GATE), diff --git a/drivers/clk/ti/mux.c b/drivers/clk/ti/mux.c new file mode 100644 index 000000000000..0197a478720c --- /dev/null +++ b/drivers/clk/ti/mux.c @@ -0,0 +1,246 @@ +/* + * TI Multiplexer Clock + * + * Copyright (C) 2013 Texas Instruments, Inc. + * + * Tero Kristo + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include + +#undef pr_fmt +#define pr_fmt(fmt) "%s: " fmt, __func__ + +#define to_clk_mux(_hw) container_of(_hw, struct clk_mux, hw) + +static u8 ti_clk_mux_get_parent(struct clk_hw *hw) +{ + struct clk_mux *mux = to_clk_mux(hw); + int num_parents = __clk_get_num_parents(hw->clk); + u32 val; + + /* + * FIXME need a mux-specific flag to determine if val is bitwise or + * numeric. e.g. sys_clkin_ck's clksel field is 3 bits wide, but ranges + * from 0x1 to 0x7 (index starts at one) + * OTOH, pmd_trace_clk_mux_ck uses a separate bit for each clock, so + * val = 0x4 really means "bit 2, index starts at bit 0" + */ + val = ti_clk_ll_ops->clk_readl(mux->reg) >> mux->shift; + val &= mux->mask; + + if (mux->table) { + int i; + + for (i = 0; i < num_parents; i++) + if (mux->table[i] == val) + return i; + return -EINVAL; + } + + if (val && (mux->flags & CLK_MUX_INDEX_BIT)) + val = ffs(val) - 1; + + if (val && (mux->flags & CLK_MUX_INDEX_ONE)) + val--; + + if (val >= num_parents) + return -EINVAL; + + return val; +} + +static int ti_clk_mux_set_parent(struct clk_hw *hw, u8 index) +{ + struct clk_mux *mux = to_clk_mux(hw); + u32 val; + unsigned long flags = 0; + + if (mux->table) { + index = mux->table[index]; + } else { + if (mux->flags & CLK_MUX_INDEX_BIT) + index = (1 << ffs(index)); + + if (mux->flags & CLK_MUX_INDEX_ONE) + index++; + } + + if (mux->lock) + spin_lock_irqsave(mux->lock, flags); + + if (mux->flags & CLK_MUX_HIWORD_MASK) { + val = mux->mask << (mux->shift + 16); + } else { + val = ti_clk_ll_ops->clk_readl(mux->reg); + val &= ~(mux->mask << mux->shift); + } + val |= index << mux->shift; + ti_clk_ll_ops->clk_writel(val, mux->reg); + + if (mux->lock) + spin_unlock_irqrestore(mux->lock, flags); + + return 0; +} + +const struct clk_ops ti_clk_mux_ops = { + .get_parent = ti_clk_mux_get_parent, + .set_parent = ti_clk_mux_set_parent, + .determine_rate = __clk_mux_determine_rate, +}; + +static struct clk *_register_mux(struct device *dev, const char *name, + const char **parent_names, u8 num_parents, + unsigned long flags, void __iomem *reg, + u8 shift, u32 mask, u8 clk_mux_flags, + u32 *table, spinlock_t *lock) +{ + struct clk_mux *mux; + struct clk *clk; + struct clk_init_data init; + + /* allocate the mux */ + mux = kzalloc(sizeof(*mux), GFP_KERNEL); + if (!mux) { + pr_err("%s: could not allocate mux clk\n", __func__); + return ERR_PTR(-ENOMEM); + } + + init.name = name; + init.ops = &ti_clk_mux_ops; + init.flags = flags | CLK_IS_BASIC; + init.parent_names = parent_names; + init.num_parents = num_parents; + + /* struct clk_mux assignments */ + mux->reg = reg; + mux->shift = shift; + mux->mask = mask; + mux->flags = clk_mux_flags; + mux->lock = lock; + mux->table = table; + mux->hw.init = &init; + + clk = clk_register(dev, &mux->hw); + + if (IS_ERR(clk)) + kfree(mux); + + return clk; +} + +/** + * of_mux_clk_setup - Setup function for simple mux rate clock + * @node: DT node for the clock + * + * Sets up a basic clock multiplexer. + */ +static void of_mux_clk_setup(struct device_node *node) +{ + struct clk *clk; + void __iomem *reg; + int num_parents; + const char **parent_names; + int i; + u8 clk_mux_flags = 0; + u32 mask = 0; + u32 shift = 0; + u32 flags = 0; + + num_parents = of_clk_get_parent_count(node); + if (num_parents < 2) { + pr_err("mux-clock %s must have parents\n", node->name); + return; + } + parent_names = kzalloc((sizeof(char *) * num_parents), GFP_KERNEL); + if (!parent_names) + goto cleanup; + + for (i = 0; i < num_parents; i++) + parent_names[i] = of_clk_get_parent_name(node, i); + + reg = ti_clk_get_reg_addr(node, 0); + + if (!reg) + goto cleanup; + + of_property_read_u32(node, "ti,bit-shift", &shift); + + if (of_property_read_bool(node, "ti,index-starts-at-one")) + clk_mux_flags |= CLK_MUX_INDEX_ONE; + + if (of_property_read_bool(node, "ti,set-rate-parent")) + flags |= CLK_SET_RATE_PARENT; + + /* Generate bit-mask based on parent info */ + mask = num_parents; + if (!(clk_mux_flags & CLK_MUX_INDEX_ONE)) + mask--; + + mask = (1 << fls(mask)) - 1; + + clk = _register_mux(NULL, node->name, parent_names, num_parents, flags, + reg, shift, mask, clk_mux_flags, NULL, NULL); + + if (!IS_ERR(clk)) + of_clk_add_provider(node, of_clk_src_simple_get, clk); + +cleanup: + kfree(parent_names); +} +CLK_OF_DECLARE(mux_clk, "ti,mux-clock", of_mux_clk_setup); + +static void __init of_ti_composite_mux_clk_setup(struct device_node *node) +{ + struct clk_mux *mux; + int num_parents; + u32 val; + + mux = kzalloc(sizeof(*mux), GFP_KERNEL); + if (!mux) + return; + + mux->reg = ti_clk_get_reg_addr(node, 0); + + if (!mux->reg) + goto cleanup; + + if (!of_property_read_u32(node, "ti,bit-shift", &val)) + mux->shift = val; + + if (of_property_read_bool(node, "ti,index-starts-at-one")) + mux->flags |= CLK_MUX_INDEX_ONE; + + num_parents = of_clk_get_parent_count(node); + + if (num_parents < 2) { + pr_err("%s must have parents\n", node->name); + goto cleanup; + } + + mux->mask = num_parents - 1; + mux->mask = (1 << fls(mux->mask)) - 1; + + if (!ti_clk_add_component(node, &mux->hw, CLK_COMPONENT_TYPE_MUX)) + return; + +cleanup: + kfree(mux); +} +CLK_OF_DECLARE(ti_composite_mux_clk_setup, "ti,composite-mux-clock", + of_ti_composite_mux_clk_setup); diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h index a3f89a60de07..6e205b140071 100644 --- a/include/linux/clk/ti.h +++ b/include/linux/clk/ti.h @@ -224,6 +224,7 @@ struct ti_clk_ll_ops { extern struct ti_clk_ll_ops *ti_clk_ll_ops; extern const struct clk_ops ti_clk_divider_ops; +extern const struct clk_ops ti_clk_mux_ops; #define to_clk_hw_omap(_hw) container_of(_hw, struct clk_hw_omap, hw) -- cgit v1.2.3-59-g8ed1b From 21876ea566fedadd56453af5a1a91eb667c25422 Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Thu, 18 Jul 2013 15:57:51 +0300 Subject: CLK: TI: add omap4 clock init file clk-44xx.c now contains the clock init functionality for omap4, including DT clock registration and adding of static clkdev entries. Signed-off-by: Tero Kristo Tested-by: Nishanth Menon Acked-by: Tony Lindgren Signed-off-by: Mike Turquette --- arch/arm/mach-omap2/clock.h | 1 - drivers/clk/ti/Makefile | 1 + drivers/clk/ti/clk-44xx.c | 316 ++++++++++++++++++++++++++++++++++++++++++++ include/linux/clk/ti.h | 3 + 4 files changed, 320 insertions(+), 1 deletion(-) create mode 100644 drivers/clk/ti/clk-44xx.c diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h index 6bd72b53e4d4..b83fca6bc227 100644 --- a/arch/arm/mach-omap2/clock.h +++ b/arch/arm/mach-omap2/clock.h @@ -247,7 +247,6 @@ void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk, void __iomem **idlest_reg, u8 *idlest_bit, u8 *idlest_val); int omap2_clk_enable_autoidle_all(void); -int omap2_clk_disable_autoidle_all(void); int omap2_clk_allow_idle(struct clk *clk); int omap2_clk_deny_idle(struct clk *clk); void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks); diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile index d98a47fb13a4..9abac5e02c26 100644 --- a/drivers/clk/ti/Makefile +++ b/drivers/clk/ti/Makefile @@ -2,4 +2,5 @@ ifneq ($(CONFIG_OF),) obj-y += clk.o autoidle.o clockdomain.o clk-common = dpll.o composite.o divider.o gate.o \ fixed-factor.o mux.o +obj-$(CONFIG_ARCH_OMAP4) += $(clk-common) clk-44xx.o endif diff --git a/drivers/clk/ti/clk-44xx.c b/drivers/clk/ti/clk-44xx.c new file mode 100644 index 000000000000..ae00218b5da3 --- /dev/null +++ b/drivers/clk/ti/clk-44xx.c @@ -0,0 +1,316 @@ +/* + * OMAP4 Clock init + * + * Copyright (C) 2013 Texas Instruments, Inc. + * + * Tero Kristo (t-kristo@ti.com) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include + +/* + * OMAP4 ABE DPLL default frequency. In OMAP4460 TRM version V, section + * "3.6.3.2.3 CM1_ABE Clock Generator" states that the "DPLL_ABE_X2_CLK + * must be set to 196.608 MHz" and hence, the DPLL locked frequency is + * half of this value. + */ +#define OMAP4_DPLL_ABE_DEFFREQ 98304000 + +/* + * OMAP4 USB DPLL default frequency. In OMAP4430 TRM version V, section + * "3.6.3.9.5 DPLL_USB Preferred Settings" shows that the preferred + * locked frequency for the USB DPLL is 960MHz. + */ +#define OMAP4_DPLL_USB_DEFFREQ 960000000 + +static struct ti_dt_clk omap44xx_clks[] = { + DT_CLK(NULL, "extalt_clkin_ck", "extalt_clkin_ck"), + DT_CLK(NULL, "pad_clks_src_ck", "pad_clks_src_ck"), + DT_CLK(NULL, "pad_clks_ck", "pad_clks_ck"), + DT_CLK(NULL, "pad_slimbus_core_clks_ck", "pad_slimbus_core_clks_ck"), + DT_CLK(NULL, "secure_32k_clk_src_ck", "secure_32k_clk_src_ck"), + DT_CLK(NULL, "slimbus_src_clk", "slimbus_src_clk"), + DT_CLK(NULL, "slimbus_clk", "slimbus_clk"), + DT_CLK(NULL, "sys_32k_ck", "sys_32k_ck"), + DT_CLK(NULL, "virt_12000000_ck", "virt_12000000_ck"), + DT_CLK(NULL, "virt_13000000_ck", "virt_13000000_ck"), + DT_CLK(NULL, "virt_16800000_ck", "virt_16800000_ck"), + DT_CLK(NULL, "virt_19200000_ck", "virt_19200000_ck"), + DT_CLK(NULL, "virt_26000000_ck", "virt_26000000_ck"), + DT_CLK(NULL, "virt_27000000_ck", "virt_27000000_ck"), + DT_CLK(NULL, "virt_38400000_ck", "virt_38400000_ck"), + DT_CLK(NULL, "sys_clkin_ck", "sys_clkin_ck"), + DT_CLK(NULL, "tie_low_clock_ck", "tie_low_clock_ck"), + DT_CLK(NULL, "utmi_phy_clkout_ck", "utmi_phy_clkout_ck"), + DT_CLK(NULL, "xclk60mhsp1_ck", "xclk60mhsp1_ck"), + DT_CLK(NULL, "xclk60mhsp2_ck", "xclk60mhsp2_ck"), + DT_CLK(NULL, "xclk60motg_ck", "xclk60motg_ck"), + DT_CLK(NULL, "abe_dpll_bypass_clk_mux_ck", "abe_dpll_bypass_clk_mux_ck"), + DT_CLK(NULL, "abe_dpll_refclk_mux_ck", "abe_dpll_refclk_mux_ck"), + DT_CLK(NULL, "dpll_abe_ck", "dpll_abe_ck"), + DT_CLK(NULL, "dpll_abe_x2_ck", "dpll_abe_x2_ck"), + DT_CLK(NULL, "dpll_abe_m2x2_ck", "dpll_abe_m2x2_ck"), + DT_CLK(NULL, "abe_24m_fclk", "abe_24m_fclk"), + DT_CLK(NULL, "abe_clk", "abe_clk"), + DT_CLK(NULL, "aess_fclk", "aess_fclk"), + DT_CLK(NULL, "dpll_abe_m3x2_ck", "dpll_abe_m3x2_ck"), + DT_CLK(NULL, "core_hsd_byp_clk_mux_ck", "core_hsd_byp_clk_mux_ck"), + DT_CLK(NULL, "dpll_core_ck", "dpll_core_ck"), + DT_CLK(NULL, "dpll_core_x2_ck", "dpll_core_x2_ck"), + DT_CLK(NULL, "dpll_core_m6x2_ck", "dpll_core_m6x2_ck"), + DT_CLK(NULL, "dbgclk_mux_ck", "dbgclk_mux_ck"), + DT_CLK(NULL, "dpll_core_m2_ck", "dpll_core_m2_ck"), + DT_CLK(NULL, "ddrphy_ck", "ddrphy_ck"), + DT_CLK(NULL, "dpll_core_m5x2_ck", "dpll_core_m5x2_ck"), + DT_CLK(NULL, "div_core_ck", "div_core_ck"), + DT_CLK(NULL, "div_iva_hs_clk", "div_iva_hs_clk"), + DT_CLK(NULL, "div_mpu_hs_clk", "div_mpu_hs_clk"), + DT_CLK(NULL, "dpll_core_m4x2_ck", "dpll_core_m4x2_ck"), + DT_CLK(NULL, "dll_clk_div_ck", "dll_clk_div_ck"), + DT_CLK(NULL, "dpll_abe_m2_ck", "dpll_abe_m2_ck"), + DT_CLK(NULL, "dpll_core_m3x2_ck", "dpll_core_m3x2_ck"), + DT_CLK(NULL, "dpll_core_m7x2_ck", "dpll_core_m7x2_ck"), + DT_CLK(NULL, "iva_hsd_byp_clk_mux_ck", "iva_hsd_byp_clk_mux_ck"), + DT_CLK(NULL, "dpll_iva_ck", "dpll_iva_ck"), + DT_CLK(NULL, "dpll_iva_x2_ck", "dpll_iva_x2_ck"), + DT_CLK(NULL, "dpll_iva_m4x2_ck", "dpll_iva_m4x2_ck"), + DT_CLK(NULL, "dpll_iva_m5x2_ck", "dpll_iva_m5x2_ck"), + DT_CLK(NULL, "dpll_mpu_ck", "dpll_mpu_ck"), + DT_CLK(NULL, "dpll_mpu_m2_ck", "dpll_mpu_m2_ck"), + DT_CLK(NULL, "per_hs_clk_div_ck", "per_hs_clk_div_ck"), + DT_CLK(NULL, "per_hsd_byp_clk_mux_ck", "per_hsd_byp_clk_mux_ck"), + DT_CLK(NULL, "dpll_per_ck", "dpll_per_ck"), + DT_CLK(NULL, "dpll_per_m2_ck", "dpll_per_m2_ck"), + DT_CLK(NULL, "dpll_per_x2_ck", "dpll_per_x2_ck"), + DT_CLK(NULL, "dpll_per_m2x2_ck", "dpll_per_m2x2_ck"), + DT_CLK(NULL, "dpll_per_m3x2_ck", "dpll_per_m3x2_ck"), + DT_CLK(NULL, "dpll_per_m4x2_ck", "dpll_per_m4x2_ck"), + DT_CLK(NULL, "dpll_per_m5x2_ck", "dpll_per_m5x2_ck"), + DT_CLK(NULL, "dpll_per_m6x2_ck", "dpll_per_m6x2_ck"), + DT_CLK(NULL, "dpll_per_m7x2_ck", "dpll_per_m7x2_ck"), + DT_CLK(NULL, "usb_hs_clk_div_ck", "usb_hs_clk_div_ck"), + DT_CLK(NULL, "dpll_usb_ck", "dpll_usb_ck"), + DT_CLK(NULL, "dpll_usb_clkdcoldo_ck", "dpll_usb_clkdcoldo_ck"), + DT_CLK(NULL, "dpll_usb_m2_ck", "dpll_usb_m2_ck"), + DT_CLK(NULL, "ducati_clk_mux_ck", "ducati_clk_mux_ck"), + DT_CLK(NULL, "func_12m_fclk", "func_12m_fclk"), + DT_CLK(NULL, "func_24m_clk", "func_24m_clk"), + DT_CLK(NULL, "func_24mc_fclk", "func_24mc_fclk"), + DT_CLK(NULL, "func_48m_fclk", "func_48m_fclk"), + DT_CLK(NULL, "func_48mc_fclk", "func_48mc_fclk"), + DT_CLK(NULL, "func_64m_fclk", "func_64m_fclk"), + DT_CLK(NULL, "func_96m_fclk", "func_96m_fclk"), + DT_CLK(NULL, "init_60m_fclk", "init_60m_fclk"), + DT_CLK(NULL, "l3_div_ck", "l3_div_ck"), + DT_CLK(NULL, "l4_div_ck", "l4_div_ck"), + DT_CLK(NULL, "lp_clk_div_ck", "lp_clk_div_ck"), + DT_CLK(NULL, "l4_wkup_clk_mux_ck", "l4_wkup_clk_mux_ck"), + DT_CLK("smp_twd", NULL, "mpu_periphclk"), + DT_CLK(NULL, "ocp_abe_iclk", "ocp_abe_iclk"), + DT_CLK(NULL, "per_abe_24m_fclk", "per_abe_24m_fclk"), + DT_CLK(NULL, "per_abe_nc_fclk", "per_abe_nc_fclk"), + DT_CLK(NULL, "syc_clk_div_ck", "syc_clk_div_ck"), + DT_CLK(NULL, "aes1_fck", "aes1_fck"), + DT_CLK(NULL, "aes2_fck", "aes2_fck"), + DT_CLK(NULL, "dmic_sync_mux_ck", "dmic_sync_mux_ck"), + DT_CLK(NULL, "func_dmic_abe_gfclk", "func_dmic_abe_gfclk"), + DT_CLK(NULL, "dss_sys_clk", "dss_sys_clk"), + DT_CLK(NULL, "dss_tv_clk", "dss_tv_clk"), + DT_CLK(NULL, "dss_dss_clk", "dss_dss_clk"), + DT_CLK(NULL, "dss_48mhz_clk", "dss_48mhz_clk"), + DT_CLK(NULL, "dss_fck", "dss_fck"), + DT_CLK("omapdss_dss", "ick", "dss_fck"), + DT_CLK(NULL, "fdif_fck", "fdif_fck"), + DT_CLK(NULL, "gpio1_dbclk", "gpio1_dbclk"), + DT_CLK(NULL, "gpio2_dbclk", "gpio2_dbclk"), + DT_CLK(NULL, "gpio3_dbclk", "gpio3_dbclk"), + DT_CLK(NULL, "gpio4_dbclk", "gpio4_dbclk"), + DT_CLK(NULL, "gpio5_dbclk", "gpio5_dbclk"), + DT_CLK(NULL, "gpio6_dbclk", "gpio6_dbclk"), + DT_CLK(NULL, "sgx_clk_mux", "sgx_clk_mux"), + DT_CLK(NULL, "hsi_fck", "hsi_fck"), + DT_CLK(NULL, "iss_ctrlclk", "iss_ctrlclk"), + DT_CLK(NULL, "mcasp_sync_mux_ck", "mcasp_sync_mux_ck"), + DT_CLK(NULL, "func_mcasp_abe_gfclk", "func_mcasp_abe_gfclk"), + DT_CLK(NULL, "mcbsp1_sync_mux_ck", "mcbsp1_sync_mux_ck"), + DT_CLK(NULL, "func_mcbsp1_gfclk", "func_mcbsp1_gfclk"), + DT_CLK(NULL, "mcbsp2_sync_mux_ck", "mcbsp2_sync_mux_ck"), + DT_CLK(NULL, "func_mcbsp2_gfclk", "func_mcbsp2_gfclk"), + DT_CLK(NULL, "mcbsp3_sync_mux_ck", "mcbsp3_sync_mux_ck"), + DT_CLK(NULL, "func_mcbsp3_gfclk", "func_mcbsp3_gfclk"), + DT_CLK(NULL, "mcbsp4_sync_mux_ck", "mcbsp4_sync_mux_ck"), + DT_CLK(NULL, "per_mcbsp4_gfclk", "per_mcbsp4_gfclk"), + DT_CLK(NULL, "hsmmc1_fclk", "hsmmc1_fclk"), + DT_CLK(NULL, "hsmmc2_fclk", "hsmmc2_fclk"), + DT_CLK(NULL, "ocp2scp_usb_phy_phy_48m", "ocp2scp_usb_phy_phy_48m"), + DT_CLK(NULL, "sha2md5_fck", "sha2md5_fck"), + DT_CLK(NULL, "slimbus1_fclk_1", "slimbus1_fclk_1"), + DT_CLK(NULL, "slimbus1_fclk_0", "slimbus1_fclk_0"), + DT_CLK(NULL, "slimbus1_fclk_2", "slimbus1_fclk_2"), + DT_CLK(NULL, "slimbus1_slimbus_clk", "slimbus1_slimbus_clk"), + DT_CLK(NULL, "slimbus2_fclk_1", "slimbus2_fclk_1"), + DT_CLK(NULL, "slimbus2_fclk_0", "slimbus2_fclk_0"), + DT_CLK(NULL, "slimbus2_slimbus_clk", "slimbus2_slimbus_clk"), + DT_CLK(NULL, "smartreflex_core_fck", "smartreflex_core_fck"), + DT_CLK(NULL, "smartreflex_iva_fck", "smartreflex_iva_fck"), + DT_CLK(NULL, "smartreflex_mpu_fck", "smartreflex_mpu_fck"), + DT_CLK(NULL, "dmt1_clk_mux", "dmt1_clk_mux"), + DT_CLK(NULL, "cm2_dm10_mux", "cm2_dm10_mux"), + DT_CLK(NULL, "cm2_dm11_mux", "cm2_dm11_mux"), + DT_CLK(NULL, "cm2_dm2_mux", "cm2_dm2_mux"), + DT_CLK(NULL, "cm2_dm3_mux", "cm2_dm3_mux"), + DT_CLK(NULL, "cm2_dm4_mux", "cm2_dm4_mux"), + DT_CLK(NULL, "timer5_sync_mux", "timer5_sync_mux"), + DT_CLK(NULL, "timer6_sync_mux", "timer6_sync_mux"), + DT_CLK(NULL, "timer7_sync_mux", "timer7_sync_mux"), + DT_CLK(NULL, "timer8_sync_mux", "timer8_sync_mux"), + DT_CLK(NULL, "cm2_dm9_mux", "cm2_dm9_mux"), + DT_CLK(NULL, "usb_host_fs_fck", "usb_host_fs_fck"), + DT_CLK("usbhs_omap", "fs_fck", "usb_host_fs_fck"), + DT_CLK(NULL, "utmi_p1_gfclk", "utmi_p1_gfclk"), + DT_CLK(NULL, "usb_host_hs_utmi_p1_clk", "usb_host_hs_utmi_p1_clk"), + DT_CLK(NULL, "utmi_p2_gfclk", "utmi_p2_gfclk"), + DT_CLK(NULL, "usb_host_hs_utmi_p2_clk", "usb_host_hs_utmi_p2_clk"), + DT_CLK(NULL, "usb_host_hs_utmi_p3_clk", "usb_host_hs_utmi_p3_clk"), + DT_CLK(NULL, "usb_host_hs_hsic480m_p1_clk", "usb_host_hs_hsic480m_p1_clk"), + DT_CLK(NULL, "usb_host_hs_hsic60m_p1_clk", "usb_host_hs_hsic60m_p1_clk"), + DT_CLK(NULL, "usb_host_hs_hsic60m_p2_clk", "usb_host_hs_hsic60m_p2_clk"), + DT_CLK(NULL, "usb_host_hs_hsic480m_p2_clk", "usb_host_hs_hsic480m_p2_clk"), + DT_CLK(NULL, "usb_host_hs_func48mclk", "usb_host_hs_func48mclk"), + DT_CLK(NULL, "usb_host_hs_fck", "usb_host_hs_fck"), + DT_CLK("usbhs_omap", "hs_fck", "usb_host_hs_fck"), + DT_CLK(NULL, "otg_60m_gfclk", "otg_60m_gfclk"), + DT_CLK(NULL, "usb_otg_hs_xclk", "usb_otg_hs_xclk"), + DT_CLK(NULL, "usb_otg_hs_ick", "usb_otg_hs_ick"), + DT_CLK("musb-omap2430", "ick", "usb_otg_hs_ick"), + DT_CLK(NULL, "usb_phy_cm_clk32k", "usb_phy_cm_clk32k"), + DT_CLK(NULL, "usb_tll_hs_usb_ch2_clk", "usb_tll_hs_usb_ch2_clk"), + DT_CLK(NULL, "usb_tll_hs_usb_ch0_clk", "usb_tll_hs_usb_ch0_clk"), + DT_CLK(NULL, "usb_tll_hs_usb_ch1_clk", "usb_tll_hs_usb_ch1_clk"), + DT_CLK(NULL, "usb_tll_hs_ick", "usb_tll_hs_ick"), + DT_CLK("usbhs_omap", "usbtll_ick", "usb_tll_hs_ick"), + DT_CLK("usbhs_tll", "usbtll_ick", "usb_tll_hs_ick"), + DT_CLK(NULL, "usim_ck", "usim_ck"), + DT_CLK(NULL, "usim_fclk", "usim_fclk"), + DT_CLK(NULL, "pmd_stm_clock_mux_ck", "pmd_stm_clock_mux_ck"), + DT_CLK(NULL, "pmd_trace_clk_mux_ck", "pmd_trace_clk_mux_ck"), + DT_CLK(NULL, "stm_clk_div_ck", "stm_clk_div_ck"), + DT_CLK(NULL, "trace_clk_div_ck", "trace_clk_div_ck"), + DT_CLK(NULL, "auxclk0_src_ck", "auxclk0_src_ck"), + DT_CLK(NULL, "auxclk0_ck", "auxclk0_ck"), + DT_CLK(NULL, "auxclkreq0_ck", "auxclkreq0_ck"), + DT_CLK(NULL, "auxclk1_src_ck", "auxclk1_src_ck"), + DT_CLK(NULL, "auxclk1_ck", "auxclk1_ck"), + DT_CLK(NULL, "auxclkreq1_ck", "auxclkreq1_ck"), + DT_CLK(NULL, "auxclk2_src_ck", "auxclk2_src_ck"), + DT_CLK(NULL, "auxclk2_ck", "auxclk2_ck"), + DT_CLK(NULL, "auxclkreq2_ck", "auxclkreq2_ck"), + DT_CLK(NULL, "auxclk3_src_ck", "auxclk3_src_ck"), + DT_CLK(NULL, "auxclk3_ck", "auxclk3_ck"), + DT_CLK(NULL, "auxclkreq3_ck", "auxclkreq3_ck"), + DT_CLK(NULL, "auxclk4_src_ck", "auxclk4_src_ck"), + DT_CLK(NULL, "auxclk4_ck", "auxclk4_ck"), + DT_CLK(NULL, "auxclkreq4_ck", "auxclkreq4_ck"), + DT_CLK(NULL, "auxclk5_src_ck", "auxclk5_src_ck"), + DT_CLK(NULL, "auxclk5_ck", "auxclk5_ck"), + DT_CLK(NULL, "auxclkreq5_ck", "auxclkreq5_ck"), + DT_CLK("50000000.gpmc", "fck", "dummy_ck"), + DT_CLK("omap_i2c.1", "ick", "dummy_ck"), + DT_CLK("omap_i2c.2", "ick", "dummy_ck"), + DT_CLK("omap_i2c.3", "ick", "dummy_ck"), + DT_CLK("omap_i2c.4", "ick", "dummy_ck"), + DT_CLK(NULL, "mailboxes_ick", "dummy_ck"), + DT_CLK("omap_hsmmc.0", "ick", "dummy_ck"), + DT_CLK("omap_hsmmc.1", "ick", "dummy_ck"), + DT_CLK("omap_hsmmc.2", "ick", "dummy_ck"), + DT_CLK("omap_hsmmc.3", "ick", "dummy_ck"), + DT_CLK("omap_hsmmc.4", "ick", "dummy_ck"), + DT_CLK("omap-mcbsp.1", "ick", "dummy_ck"), + DT_CLK("omap-mcbsp.2", "ick", "dummy_ck"), + DT_CLK("omap-mcbsp.3", "ick", "dummy_ck"), + DT_CLK("omap-mcbsp.4", "ick", "dummy_ck"), + DT_CLK("omap2_mcspi.1", "ick", "dummy_ck"), + DT_CLK("omap2_mcspi.2", "ick", "dummy_ck"), + DT_CLK("omap2_mcspi.3", "ick", "dummy_ck"), + DT_CLK("omap2_mcspi.4", "ick", "dummy_ck"), + DT_CLK(NULL, "uart1_ick", "dummy_ck"), + DT_CLK(NULL, "uart2_ick", "dummy_ck"), + DT_CLK(NULL, "uart3_ick", "dummy_ck"), + DT_CLK(NULL, "uart4_ick", "dummy_ck"), + DT_CLK("usbhs_omap", "usbhost_ick", "dummy_ck"), + DT_CLK("usbhs_omap", "usbtll_fck", "dummy_ck"), + DT_CLK("usbhs_tll", "usbtll_fck", "dummy_ck"), + DT_CLK("omap_wdt", "ick", "dummy_ck"), + DT_CLK(NULL, "timer_32k_ck", "sys_32k_ck"), + DT_CLK("omap_timer.1", "timer_sys_ck", "sys_clkin_ck"), + DT_CLK("omap_timer.2", "timer_sys_ck", "sys_clkin_ck"), + DT_CLK("omap_timer.3", "timer_sys_ck", "sys_clkin_ck"), + DT_CLK("omap_timer.4", "timer_sys_ck", "sys_clkin_ck"), + DT_CLK("omap_timer.9", "timer_sys_ck", "sys_clkin_ck"), + DT_CLK("omap_timer.10", "timer_sys_ck", "sys_clkin_ck"), + DT_CLK("omap_timer.11", "timer_sys_ck", "sys_clkin_ck"), + DT_CLK("omap_timer.5", "timer_sys_ck", "syc_clk_div_ck"), + DT_CLK("omap_timer.6", "timer_sys_ck", "syc_clk_div_ck"), + DT_CLK("omap_timer.7", "timer_sys_ck", "syc_clk_div_ck"), + DT_CLK("omap_timer.8", "timer_sys_ck", "syc_clk_div_ck"), + DT_CLK("4a318000.timer", "timer_sys_ck", "sys_clkin_ck"), + DT_CLK("48032000.timer", "timer_sys_ck", "sys_clkin_ck"), + DT_CLK("48034000.timer", "timer_sys_ck", "sys_clkin_ck"), + DT_CLK("48036000.timer", "timer_sys_ck", "sys_clkin_ck"), + DT_CLK("4803e000.timer", "timer_sys_ck", "sys_clkin_ck"), + DT_CLK("48086000.timer", "timer_sys_ck", "sys_clkin_ck"), + DT_CLK("48088000.timer", "timer_sys_ck", "sys_clkin_ck"), + DT_CLK("40138000.timer", "timer_sys_ck", "syc_clk_div_ck"), + DT_CLK("4013a000.timer", "timer_sys_ck", "syc_clk_div_ck"), + DT_CLK("4013c000.timer", "timer_sys_ck", "syc_clk_div_ck"), + DT_CLK("4013e000.timer", "timer_sys_ck", "syc_clk_div_ck"), + DT_CLK(NULL, "cpufreq_ck", "dpll_mpu_ck"), + DT_CLK(NULL, "bandgap_fclk", "bandgap_fclk"), + DT_CLK(NULL, "div_ts_ck", "div_ts_ck"), + DT_CLK(NULL, "bandgap_ts_fclk", "bandgap_ts_fclk"), + { .node_name = NULL }, +}; + +int __init omap4xxx_dt_clk_init(void) +{ + int rc; + struct clk *abe_dpll_ref, *abe_dpll, *sys_32k_ck, *usb_dpll; + + ti_dt_clocks_register(omap44xx_clks); + + omap2_clk_disable_autoidle_all(); + + /* + * Lock USB DPLL on OMAP4 devices so that the L3INIT power + * domain can transition to retention state when not in use. + */ + usb_dpll = clk_get_sys(NULL, "dpll_usb_ck"); + rc = clk_set_rate(usb_dpll, OMAP4_DPLL_USB_DEFFREQ); + if (rc) + pr_err("%s: failed to configure USB DPLL!\n", __func__); + + /* + * On OMAP4460 the ABE DPLL fails to turn on if in idle low-power + * state when turning the ABE clock domain. Workaround this by + * locking the ABE DPLL on boot. + * Lock the ABE DPLL in any case to avoid issues with audio. + */ + abe_dpll_ref = clk_get_sys(NULL, "abe_dpll_refclk_mux_ck"); + sys_32k_ck = clk_get_sys(NULL, "sys_32k_ck"); + rc = clk_set_parent(abe_dpll_ref, sys_32k_ck); + abe_dpll = clk_get_sys(NULL, "dpll_abe_ck"); + if (!rc) + rc = clk_set_rate(abe_dpll, OMAP4_DPLL_ABE_DEFFREQ); + if (rc) + pr_err("%s: failed to configure ABE DPLL!\n", __func__); + + return 0; +} diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h index 6e205b140071..a56ff1216f8d 100644 --- a/include/linux/clk/ti.h +++ b/include/linux/clk/ti.h @@ -247,6 +247,7 @@ unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw, unsigned long parent_rate); int omap2_clkops_enable_clkdm(struct clk_hw *hw); void omap2_clkops_disable_clkdm(struct clk_hw *hw); +int omap2_clk_disable_autoidle_all(void); int omap3_dpll4_set_rate(struct clk_hw *clk, unsigned long rate, unsigned long parent_rate); int omap2_dflt_clk_enable(struct clk_hw *hw); @@ -262,6 +263,8 @@ int ti_clk_retry_init(struct device_node *node, struct clk_hw *hw, int of_ti_clk_autoidle_setup(struct device_node *node); int ti_clk_add_component(struct device_node *node, struct clk_hw *hw, int type); +int omap4xxx_dt_clk_init(void); + #ifdef CONFIG_OF void of_ti_clk_allow_autoidle_all(void); void of_ti_clk_deny_autoidle_all(void); -- cgit v1.2.3-59-g8ed1b From 52b14728dd890f8a62bffce8dfece496434c2b41 Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Thu, 18 Jul 2013 17:15:51 +0300 Subject: CLK: TI: add omap5 clock init file clk-54xx.c now contains the clock init functionality for omap5, including DT clock registration and adding of static clkdev entries. Signed-off-by: Tero Kristo Tested-by: Nishanth Menon Acked-by: Tony Lindgren Signed-off-by: Mike Turquette --- arch/arm/mach-omap2/io.c | 1 + drivers/clk/ti/Makefile | 1 + drivers/clk/ti/clk-54xx.c | 239 ++++++++++++++++++++++++++++++++++++++++++++++ include/linux/clk/ti.h | 1 + 4 files changed, 242 insertions(+) create mode 100644 drivers/clk/ti/clk-54xx.c diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c index cd22262a2cc0..3d9b3fcb1266 100644 --- a/arch/arm/mach-omap2/io.c +++ b/arch/arm/mach-omap2/io.c @@ -666,6 +666,7 @@ void __init omap5_init_early(void) omap54xx_clockdomains_init(); omap54xx_hwmod_init(); omap_hwmod_init_postsetup(); + omap_clk_init = omap5xxx_dt_clk_init; } void __init omap5_init_late(void) diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile index 9abac5e02c26..4a8f846740cb 100644 --- a/drivers/clk/ti/Makefile +++ b/drivers/clk/ti/Makefile @@ -3,4 +3,5 @@ obj-y += clk.o autoidle.o clockdomain.o clk-common = dpll.o composite.o divider.o gate.o \ fixed-factor.o mux.o obj-$(CONFIG_ARCH_OMAP4) += $(clk-common) clk-44xx.o +obj-$(CONFIG_SOC_OMAP5) += $(clk-common) clk-54xx.o endif diff --git a/drivers/clk/ti/clk-54xx.c b/drivers/clk/ti/clk-54xx.c new file mode 100644 index 000000000000..c876e6ee57b3 --- /dev/null +++ b/drivers/clk/ti/clk-54xx.c @@ -0,0 +1,239 @@ +/* + * OMAP5 Clock init + * + * Copyright (C) 2013 Texas Instruments, Inc. + * + * Tero Kristo (t-kristo@ti.com) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include + +#define OMAP5_DPLL_ABE_DEFFREQ 98304000 + +static struct ti_dt_clk omap54xx_clks[] = { + DT_CLK(NULL, "pad_clks_src_ck", "pad_clks_src_ck"), + DT_CLK(NULL, "pad_clks_ck", "pad_clks_ck"), + DT_CLK(NULL, "secure_32k_clk_src_ck", "secure_32k_clk_src_ck"), + DT_CLK(NULL, "slimbus_src_clk", "slimbus_src_clk"), + DT_CLK(NULL, "slimbus_clk", "slimbus_clk"), + DT_CLK(NULL, "sys_32k_ck", "sys_32k_ck"), + DT_CLK(NULL, "virt_12000000_ck", "virt_12000000_ck"), + DT_CLK(NULL, "virt_13000000_ck", "virt_13000000_ck"), + DT_CLK(NULL, "virt_16800000_ck", "virt_16800000_ck"), + DT_CLK(NULL, "virt_19200000_ck", "virt_19200000_ck"), + DT_CLK(NULL, "virt_26000000_ck", "virt_26000000_ck"), + DT_CLK(NULL, "virt_27000000_ck", "virt_27000000_ck"), + DT_CLK(NULL, "virt_38400000_ck", "virt_38400000_ck"), + DT_CLK(NULL, "sys_clkin", "sys_clkin"), + DT_CLK(NULL, "xclk60mhsp1_ck", "xclk60mhsp1_ck"), + DT_CLK(NULL, "xclk60mhsp2_ck", "xclk60mhsp2_ck"), + DT_CLK(NULL, "abe_dpll_bypass_clk_mux", "abe_dpll_bypass_clk_mux"), + DT_CLK(NULL, "abe_dpll_clk_mux", "abe_dpll_clk_mux"), + DT_CLK(NULL, "dpll_abe_ck", "dpll_abe_ck"), + DT_CLK(NULL, "dpll_abe_x2_ck", "dpll_abe_x2_ck"), + DT_CLK(NULL, "dpll_abe_m2x2_ck", "dpll_abe_m2x2_ck"), + DT_CLK(NULL, "abe_24m_fclk", "abe_24m_fclk"), + DT_CLK(NULL, "abe_clk", "abe_clk"), + DT_CLK(NULL, "abe_iclk", "abe_iclk"), + DT_CLK(NULL, "abe_lp_clk_div", "abe_lp_clk_div"), + DT_CLK(NULL, "dpll_abe_m3x2_ck", "dpll_abe_m3x2_ck"), + DT_CLK(NULL, "dpll_core_ck", "dpll_core_ck"), + DT_CLK(NULL, "dpll_core_x2_ck", "dpll_core_x2_ck"), + DT_CLK(NULL, "dpll_core_h21x2_ck", "dpll_core_h21x2_ck"), + DT_CLK(NULL, "c2c_fclk", "c2c_fclk"), + DT_CLK(NULL, "c2c_iclk", "c2c_iclk"), + DT_CLK(NULL, "custefuse_sys_gfclk_div", "custefuse_sys_gfclk_div"), + DT_CLK(NULL, "dpll_core_h11x2_ck", "dpll_core_h11x2_ck"), + DT_CLK(NULL, "dpll_core_h12x2_ck", "dpll_core_h12x2_ck"), + DT_CLK(NULL, "dpll_core_h13x2_ck", "dpll_core_h13x2_ck"), + DT_CLK(NULL, "dpll_core_h14x2_ck", "dpll_core_h14x2_ck"), + DT_CLK(NULL, "dpll_core_h22x2_ck", "dpll_core_h22x2_ck"), + DT_CLK(NULL, "dpll_core_h23x2_ck", "dpll_core_h23x2_ck"), + DT_CLK(NULL, "dpll_core_h24x2_ck", "dpll_core_h24x2_ck"), + DT_CLK(NULL, "dpll_core_m2_ck", "dpll_core_m2_ck"), + DT_CLK(NULL, "dpll_core_m3x2_ck", "dpll_core_m3x2_ck"), + DT_CLK(NULL, "iva_dpll_hs_clk_div", "iva_dpll_hs_clk_div"), + DT_CLK(NULL, "dpll_iva_ck", "dpll_iva_ck"), + DT_CLK(NULL, "dpll_iva_x2_ck", "dpll_iva_x2_ck"), + DT_CLK(NULL, "dpll_iva_h11x2_ck", "dpll_iva_h11x2_ck"), + DT_CLK(NULL, "dpll_iva_h12x2_ck", "dpll_iva_h12x2_ck"), + DT_CLK(NULL, "mpu_dpll_hs_clk_div", "mpu_dpll_hs_clk_div"), + DT_CLK(NULL, "dpll_mpu_ck", "dpll_mpu_ck"), + DT_CLK(NULL, "dpll_mpu_m2_ck", "dpll_mpu_m2_ck"), + DT_CLK(NULL, "per_dpll_hs_clk_div", "per_dpll_hs_clk_div"), + DT_CLK(NULL, "dpll_per_ck", "dpll_per_ck"), + DT_CLK(NULL, "dpll_per_x2_ck", "dpll_per_x2_ck"), + DT_CLK(NULL, "dpll_per_h11x2_ck", "dpll_per_h11x2_ck"), + DT_CLK(NULL, "dpll_per_h12x2_ck", "dpll_per_h12x2_ck"), + DT_CLK(NULL, "dpll_per_h14x2_ck", "dpll_per_h14x2_ck"), + DT_CLK(NULL, "dpll_per_m2_ck", "dpll_per_m2_ck"), + DT_CLK(NULL, "dpll_per_m2x2_ck", "dpll_per_m2x2_ck"), + DT_CLK(NULL, "dpll_per_m3x2_ck", "dpll_per_m3x2_ck"), + DT_CLK(NULL, "dpll_unipro1_ck", "dpll_unipro1_ck"), + DT_CLK(NULL, "dpll_unipro1_clkdcoldo", "dpll_unipro1_clkdcoldo"), + DT_CLK(NULL, "dpll_unipro1_m2_ck", "dpll_unipro1_m2_ck"), + DT_CLK(NULL, "dpll_unipro2_ck", "dpll_unipro2_ck"), + DT_CLK(NULL, "dpll_unipro2_clkdcoldo", "dpll_unipro2_clkdcoldo"), + DT_CLK(NULL, "dpll_unipro2_m2_ck", "dpll_unipro2_m2_ck"), + DT_CLK(NULL, "usb_dpll_hs_clk_div", "usb_dpll_hs_clk_div"), + DT_CLK(NULL, "dpll_usb_ck", "dpll_usb_ck"), + DT_CLK(NULL, "dpll_usb_clkdcoldo", "dpll_usb_clkdcoldo"), + DT_CLK(NULL, "dpll_usb_m2_ck", "dpll_usb_m2_ck"), + DT_CLK(NULL, "dss_syc_gfclk_div", "dss_syc_gfclk_div"), + DT_CLK(NULL, "func_128m_clk", "func_128m_clk"), + DT_CLK(NULL, "func_12m_fclk", "func_12m_fclk"), + DT_CLK(NULL, "func_24m_clk", "func_24m_clk"), + DT_CLK(NULL, "func_48m_fclk", "func_48m_fclk"), + DT_CLK(NULL, "func_96m_fclk", "func_96m_fclk"), + DT_CLK(NULL, "l3_iclk_div", "l3_iclk_div"), + DT_CLK(NULL, "gpu_l3_iclk", "gpu_l3_iclk"), + DT_CLK(NULL, "l3init_60m_fclk", "l3init_60m_fclk"), + DT_CLK(NULL, "wkupaon_iclk_mux", "wkupaon_iclk_mux"), + DT_CLK(NULL, "l3instr_ts_gclk_div", "l3instr_ts_gclk_div"), + DT_CLK(NULL, "l4_root_clk_div", "l4_root_clk_div"), + DT_CLK(NULL, "dss_32khz_clk", "dss_32khz_clk"), + DT_CLK(NULL, "dss_48mhz_clk", "dss_48mhz_clk"), + DT_CLK(NULL, "dss_dss_clk", "dss_dss_clk"), + DT_CLK(NULL, "dss_sys_clk", "dss_sys_clk"), + DT_CLK(NULL, "gpio1_dbclk", "gpio1_dbclk"), + DT_CLK(NULL, "gpio2_dbclk", "gpio2_dbclk"), + DT_CLK(NULL, "gpio3_dbclk", "gpio3_dbclk"), + DT_CLK(NULL, "gpio4_dbclk", "gpio4_dbclk"), + DT_CLK(NULL, "gpio5_dbclk", "gpio5_dbclk"), + DT_CLK(NULL, "gpio6_dbclk", "gpio6_dbclk"), + DT_CLK(NULL, "gpio7_dbclk", "gpio7_dbclk"), + DT_CLK(NULL, "gpio8_dbclk", "gpio8_dbclk"), + DT_CLK(NULL, "iss_ctrlclk", "iss_ctrlclk"), + DT_CLK(NULL, "lli_txphy_clk", "lli_txphy_clk"), + DT_CLK(NULL, "lli_txphy_ls_clk", "lli_txphy_ls_clk"), + DT_CLK(NULL, "mmc1_32khz_clk", "mmc1_32khz_clk"), + DT_CLK(NULL, "sata_ref_clk", "sata_ref_clk"), + DT_CLK(NULL, "slimbus1_slimbus_clk", "slimbus1_slimbus_clk"), + DT_CLK(NULL, "usb_host_hs_hsic480m_p1_clk", "usb_host_hs_hsic480m_p1_clk"), + DT_CLK(NULL, "usb_host_hs_hsic480m_p2_clk", "usb_host_hs_hsic480m_p2_clk"), + DT_CLK(NULL, "usb_host_hs_hsic480m_p3_clk", "usb_host_hs_hsic480m_p3_clk"), + DT_CLK(NULL, "usb_host_hs_hsic60m_p1_clk", "usb_host_hs_hsic60m_p1_clk"), + DT_CLK(NULL, "usb_host_hs_hsic60m_p2_clk", "usb_host_hs_hsic60m_p2_clk"), + DT_CLK(NULL, "usb_host_hs_hsic60m_p3_clk", "usb_host_hs_hsic60m_p3_clk"), + DT_CLK(NULL, "usb_host_hs_utmi_p1_clk", "usb_host_hs_utmi_p1_clk"), + DT_CLK(NULL, "usb_host_hs_utmi_p2_clk", "usb_host_hs_utmi_p2_clk"), + DT_CLK(NULL, "usb_host_hs_utmi_p3_clk", "usb_host_hs_utmi_p3_clk"), + DT_CLK(NULL, "usb_otg_ss_refclk960m", "usb_otg_ss_refclk960m"), + DT_CLK(NULL, "usb_phy_cm_clk32k", "usb_phy_cm_clk32k"), + DT_CLK(NULL, "usb_tll_hs_usb_ch0_clk", "usb_tll_hs_usb_ch0_clk"), + DT_CLK(NULL, "usb_tll_hs_usb_ch1_clk", "usb_tll_hs_usb_ch1_clk"), + DT_CLK(NULL, "usb_tll_hs_usb_ch2_clk", "usb_tll_hs_usb_ch2_clk"), + DT_CLK(NULL, "aess_fclk", "aess_fclk"), + DT_CLK(NULL, "dmic_sync_mux_ck", "dmic_sync_mux_ck"), + DT_CLK(NULL, "dmic_gfclk", "dmic_gfclk"), + DT_CLK(NULL, "fdif_fclk", "fdif_fclk"), + DT_CLK(NULL, "gpu_core_gclk_mux", "gpu_core_gclk_mux"), + DT_CLK(NULL, "gpu_hyd_gclk_mux", "gpu_hyd_gclk_mux"), + DT_CLK(NULL, "hsi_fclk", "hsi_fclk"), + DT_CLK(NULL, "mcasp_sync_mux_ck", "mcasp_sync_mux_ck"), + DT_CLK(NULL, "mcasp_gfclk", "mcasp_gfclk"), + DT_CLK(NULL, "mcbsp1_sync_mux_ck", "mcbsp1_sync_mux_ck"), + DT_CLK(NULL, "mcbsp1_gfclk", "mcbsp1_gfclk"), + DT_CLK(NULL, "mcbsp2_sync_mux_ck", "mcbsp2_sync_mux_ck"), + DT_CLK(NULL, "mcbsp2_gfclk", "mcbsp2_gfclk"), + DT_CLK(NULL, "mcbsp3_sync_mux_ck", "mcbsp3_sync_mux_ck"), + DT_CLK(NULL, "mcbsp3_gfclk", "mcbsp3_gfclk"), + DT_CLK(NULL, "mmc1_fclk_mux", "mmc1_fclk_mux"), + DT_CLK(NULL, "mmc1_fclk", "mmc1_fclk"), + DT_CLK(NULL, "mmc2_fclk_mux", "mmc2_fclk_mux"), + DT_CLK(NULL, "mmc2_fclk", "mmc2_fclk"), + DT_CLK(NULL, "timer10_gfclk_mux", "timer10_gfclk_mux"), + DT_CLK(NULL, "timer11_gfclk_mux", "timer11_gfclk_mux"), + DT_CLK(NULL, "timer1_gfclk_mux", "timer1_gfclk_mux"), + DT_CLK(NULL, "timer2_gfclk_mux", "timer2_gfclk_mux"), + DT_CLK(NULL, "timer3_gfclk_mux", "timer3_gfclk_mux"), + DT_CLK(NULL, "timer4_gfclk_mux", "timer4_gfclk_mux"), + DT_CLK(NULL, "timer5_gfclk_mux", "timer5_gfclk_mux"), + DT_CLK(NULL, "timer6_gfclk_mux", "timer6_gfclk_mux"), + DT_CLK(NULL, "timer7_gfclk_mux", "timer7_gfclk_mux"), + DT_CLK(NULL, "timer8_gfclk_mux", "timer8_gfclk_mux"), + DT_CLK(NULL, "timer9_gfclk_mux", "timer9_gfclk_mux"), + DT_CLK(NULL, "utmi_p1_gfclk", "utmi_p1_gfclk"), + DT_CLK(NULL, "utmi_p2_gfclk", "utmi_p2_gfclk"), + DT_CLK(NULL, "auxclk0_src_ck", "auxclk0_src_ck"), + DT_CLK(NULL, "auxclk0_ck", "auxclk0_ck"), + DT_CLK(NULL, "auxclkreq0_ck", "auxclkreq0_ck"), + DT_CLK(NULL, "auxclk1_src_ck", "auxclk1_src_ck"), + DT_CLK(NULL, "auxclk1_ck", "auxclk1_ck"), + DT_CLK(NULL, "auxclkreq1_ck", "auxclkreq1_ck"), + DT_CLK(NULL, "auxclk2_src_ck", "auxclk2_src_ck"), + DT_CLK(NULL, "auxclk2_ck", "auxclk2_ck"), + DT_CLK(NULL, "auxclkreq2_ck", "auxclkreq2_ck"), + DT_CLK(NULL, "auxclk3_src_ck", "auxclk3_src_ck"), + DT_CLK(NULL, "auxclk3_ck", "auxclk3_ck"), + DT_CLK(NULL, "auxclkreq3_ck", "auxclkreq3_ck"), + DT_CLK(NULL, "gpmc_ck", "dummy_ck"), + DT_CLK("omap_i2c.1", "ick", "dummy_ck"), + DT_CLK("omap_i2c.2", "ick", "dummy_ck"), + DT_CLK("omap_i2c.3", "ick", "dummy_ck"), + DT_CLK("omap_i2c.4", "ick", "dummy_ck"), + DT_CLK(NULL, "mailboxes_ick", "dummy_ck"), + DT_CLK("omap_hsmmc.0", "ick", "dummy_ck"), + DT_CLK("omap_hsmmc.1", "ick", "dummy_ck"), + DT_CLK("omap_hsmmc.2", "ick", "dummy_ck"), + DT_CLK("omap_hsmmc.3", "ick", "dummy_ck"), + DT_CLK("omap_hsmmc.4", "ick", "dummy_ck"), + DT_CLK("omap-mcbsp.1", "ick", "dummy_ck"), + DT_CLK("omap-mcbsp.2", "ick", "dummy_ck"), + DT_CLK("omap-mcbsp.3", "ick", "dummy_ck"), + DT_CLK("omap-mcbsp.4", "ick", "dummy_ck"), + DT_CLK("omap2_mcspi.1", "ick", "dummy_ck"), + DT_CLK("omap2_mcspi.2", "ick", "dummy_ck"), + DT_CLK("omap2_mcspi.3", "ick", "dummy_ck"), + DT_CLK("omap2_mcspi.4", "ick", "dummy_ck"), + DT_CLK(NULL, "uart1_ick", "dummy_ck"), + DT_CLK(NULL, "uart2_ick", "dummy_ck"), + DT_CLK(NULL, "uart3_ick", "dummy_ck"), + DT_CLK(NULL, "uart4_ick", "dummy_ck"), + DT_CLK("usbhs_omap", "usbhost_ick", "dummy_ck"), + DT_CLK("usbhs_omap", "usbtll_fck", "dummy_ck"), + DT_CLK("omap_wdt", "ick", "dummy_ck"), + DT_CLK(NULL, "timer_32k_ck", "sys_32k_ck"), + DT_CLK("omap_timer.1", "sys_ck", "sys_clkin"), + DT_CLK("omap_timer.2", "sys_ck", "sys_clkin"), + DT_CLK("omap_timer.3", "sys_ck", "sys_clkin"), + DT_CLK("omap_timer.4", "sys_ck", "sys_clkin"), + DT_CLK("omap_timer.9", "sys_ck", "sys_clkin"), + DT_CLK("omap_timer.10", "sys_ck", "sys_clkin"), + DT_CLK("omap_timer.11", "sys_ck", "sys_clkin"), + DT_CLK("omap_timer.5", "sys_ck", "dss_syc_gfclk_div"), + DT_CLK("omap_timer.6", "sys_ck", "dss_syc_gfclk_div"), + DT_CLK("omap_timer.7", "sys_ck", "dss_syc_gfclk_div"), + DT_CLK("omap_timer.8", "sys_ck", "dss_syc_gfclk_div"), + { .node_name = NULL }, +}; + +int __init omap5xxx_dt_clk_init(void) +{ + int rc; + struct clk *abe_dpll_ref, *abe_dpll, *sys_32k_ck; + + ti_dt_clocks_register(omap54xx_clks); + + omap2_clk_disable_autoidle_all(); + + abe_dpll_ref = clk_get_sys(NULL, "abe_dpll_clk_mux"); + sys_32k_ck = clk_get_sys(NULL, "sys_32k_ck"); + rc = clk_set_parent(abe_dpll_ref, sys_32k_ck); + abe_dpll = clk_get_sys(NULL, "dpll_abe_ck"); + if (!rc) + rc = clk_set_rate(abe_dpll, OMAP5_DPLL_ABE_DEFFREQ); + if (rc) + pr_err("%s: failed to configure ABE DPLL!\n", __func__); + + return 0; +} diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h index a56ff1216f8d..6647f28b445d 100644 --- a/include/linux/clk/ti.h +++ b/include/linux/clk/ti.h @@ -264,6 +264,7 @@ int of_ti_clk_autoidle_setup(struct device_node *node); int ti_clk_add_component(struct device_node *node, struct clk_hw *hw, int type); int omap4xxx_dt_clk_init(void); +int omap5xxx_dt_clk_init(void); #ifdef CONFIG_OF void of_ti_clk_allow_autoidle_all(void); -- cgit v1.2.3-59-g8ed1b From 62125a46cd717ad8fa6a64d260d46a0a108e6222 Mon Sep 17 00:00:00 2001 From: Roger Quadros Date: Wed, 24 Jul 2013 16:30:55 +0300 Subject: CLK: TI: omap5: Initialize USB_DPLL at boot USB_DPLL must be initialized and locked at boot so that USB modules can work. Signed-off-by: Roger Quadros Signed-off-by: Tero Kristo Tested-by: Nishanth Menon Acked-by: Tony Lindgren Signed-off-by: Mike Turquette --- drivers/clk/ti/clk-54xx.c | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) diff --git a/drivers/clk/ti/clk-54xx.c b/drivers/clk/ti/clk-54xx.c index c876e6ee57b3..0ef9f581286b 100644 --- a/drivers/clk/ti/clk-54xx.c +++ b/drivers/clk/ti/clk-54xx.c @@ -19,6 +19,12 @@ #define OMAP5_DPLL_ABE_DEFFREQ 98304000 +/* + * OMAP543x TRM, section "3.6.3.9.5 DPLL_USB Preferred Settings" + * states it must be at 960MHz + */ +#define OMAP5_DPLL_USB_DEFFREQ 960000000 + static struct ti_dt_clk omap54xx_clks[] = { DT_CLK(NULL, "pad_clks_src_ck", "pad_clks_src_ck"), DT_CLK(NULL, "pad_clks_ck", "pad_clks_ck"), @@ -220,7 +226,7 @@ static struct ti_dt_clk omap54xx_clks[] = { int __init omap5xxx_dt_clk_init(void) { int rc; - struct clk *abe_dpll_ref, *abe_dpll, *sys_32k_ck; + struct clk *abe_dpll_ref, *abe_dpll, *sys_32k_ck, *usb_dpll; ti_dt_clocks_register(omap54xx_clks); @@ -235,5 +241,15 @@ int __init omap5xxx_dt_clk_init(void) if (rc) pr_err("%s: failed to configure ABE DPLL!\n", __func__); + usb_dpll = clk_get_sys(NULL, "dpll_usb_ck"); + rc = clk_set_rate(usb_dpll, OMAP5_DPLL_USB_DEFFREQ); + if (rc) + pr_err("%s: failed to configure USB DPLL!\n", __func__); + + usb_dpll = clk_get_sys(NULL, "dpll_usb_m2_ck"); + rc = clk_set_rate(usb_dpll, OMAP5_DPLL_USB_DEFFREQ/2); + if (rc) + pr_err("%s: failed to set USB_DPLL M2 OUT\n", __func__); + return 0; } -- cgit v1.2.3-59-g8ed1b From 3cf467a9969db8297dcf783c5b09b0df8fda863b Mon Sep 17 00:00:00 2001 From: J Keerthy Date: Tue, 23 Jul 2013 12:05:37 +0530 Subject: CLK: TI: DRA7: Add APLL support The patch adds support for DRA7 PCIe APLL. The APLL sources the optional functional clocks for PCIe module. APLL stands for Analog PLL. This is different when comapred with DPLL meaning Digital PLL, the phase detection is done using an analog circuit. Signed-off-by: J Keerthy Signed-off-by: Tero Kristo Acked-by: Tony Lindgren Signed-off-by: Mike Turquette --- .../devicetree/bindings/clock/ti/apll.txt | 31 +++ drivers/clk/ti/Makefile | 2 +- drivers/clk/ti/apll.c | 223 +++++++++++++++++++++ 3 files changed, 255 insertions(+), 1 deletion(-) create mode 100644 Documentation/devicetree/bindings/clock/ti/apll.txt create mode 100644 drivers/clk/ti/apll.c diff --git a/Documentation/devicetree/bindings/clock/ti/apll.txt b/Documentation/devicetree/bindings/clock/ti/apll.txt new file mode 100644 index 000000000000..7faf5a68b3be --- /dev/null +++ b/Documentation/devicetree/bindings/clock/ti/apll.txt @@ -0,0 +1,31 @@ +Binding for Texas Instruments APLL clock. + +Binding status: Unstable - ABI compatibility may be broken in the future + +This binding uses the common clock binding[1]. It assumes a +register-mapped APLL with usually two selectable input clocks +(reference clock and bypass clock), with analog phase locked +loop logic for multiplying the input clock to a desired output +clock. This clock also typically supports different operation +modes (locked, low power stop etc.) APLL mostly behaves like +a subtype of a DPLL [2], although a simplified one at that. + +[1] Documentation/devicetree/bindings/clock/clock-bindings.txt +[2] Documentation/devicetree/bindings/clock/ti/dpll.txt + +Required properties: +- compatible : shall be "ti,dra7-apll-clock" +- #clock-cells : from common clock binding; shall be set to 0. +- clocks : link phandles of parent clocks (clk-ref and clk-bypass) +- reg : address and length of the register set for controlling the APLL. + It contains the information of registers in the following order: + "control" - contains the control register base address + "idlest" - contains the idlest register base address + +Examples: + apll_pcie_ck: apll_pcie_ck@4a008200 { + #clock-cells = <0>; + clocks = <&apll_pcie_in_clk_mux>, <&dpll_pcie_ref_ck>; + reg = <0x4a00821c 0x4>, <0x4a008220 0x4>; + compatible = "ti,dra7-apll-clock"; + }; diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile index 4a8f846740cb..26e994ac3557 100644 --- a/drivers/clk/ti/Makefile +++ b/drivers/clk/ti/Makefile @@ -1,7 +1,7 @@ ifneq ($(CONFIG_OF),) obj-y += clk.o autoidle.o clockdomain.o clk-common = dpll.o composite.o divider.o gate.o \ - fixed-factor.o mux.o + fixed-factor.o mux.o apll.o obj-$(CONFIG_ARCH_OMAP4) += $(clk-common) clk-44xx.o obj-$(CONFIG_SOC_OMAP5) += $(clk-common) clk-54xx.o endif diff --git a/drivers/clk/ti/apll.c b/drivers/clk/ti/apll.c new file mode 100644 index 000000000000..b986f61f5a77 --- /dev/null +++ b/drivers/clk/ti/apll.c @@ -0,0 +1,223 @@ +/* + * OMAP APLL clock support + * + * Copyright (C) 2013 Texas Instruments, Inc. + * + * J Keerthy + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define APLL_FORCE_LOCK 0x1 +#define APLL_AUTO_IDLE 0x2 +#define MAX_APLL_WAIT_TRIES 1000000 + +#undef pr_fmt +#define pr_fmt(fmt) "%s: " fmt, __func__ + +static int dra7_apll_enable(struct clk_hw *hw) +{ + struct clk_hw_omap *clk = to_clk_hw_omap(hw); + int r = 0, i = 0; + struct dpll_data *ad; + const char *clk_name; + u8 state = 1; + u32 v; + + ad = clk->dpll_data; + if (!ad) + return -EINVAL; + + clk_name = __clk_get_name(clk->hw.clk); + + state <<= __ffs(ad->idlest_mask); + + /* Check is already locked */ + v = ti_clk_ll_ops->clk_readl(ad->idlest_reg); + + if ((v & ad->idlest_mask) == state) + return r; + + v = ti_clk_ll_ops->clk_readl(ad->control_reg); + v &= ~ad->enable_mask; + v |= APLL_FORCE_LOCK << __ffs(ad->enable_mask); + ti_clk_ll_ops->clk_writel(v, ad->control_reg); + + state <<= __ffs(ad->idlest_mask); + + while (1) { + v = ti_clk_ll_ops->clk_readl(ad->idlest_reg); + if ((v & ad->idlest_mask) == state) + break; + if (i > MAX_APLL_WAIT_TRIES) + break; + i++; + udelay(1); + } + + if (i == MAX_APLL_WAIT_TRIES) { + pr_warn("clock: %s failed transition to '%s'\n", + clk_name, (state) ? "locked" : "bypassed"); + } else { + pr_debug("clock: %s transition to '%s' in %d loops\n", + clk_name, (state) ? "locked" : "bypassed", i); + + r = 0; + } + + return r; +} + +static void dra7_apll_disable(struct clk_hw *hw) +{ + struct clk_hw_omap *clk = to_clk_hw_omap(hw); + struct dpll_data *ad; + u8 state = 1; + u32 v; + + ad = clk->dpll_data; + + state <<= __ffs(ad->idlest_mask); + + v = ti_clk_ll_ops->clk_readl(ad->control_reg); + v &= ~ad->enable_mask; + v |= APLL_AUTO_IDLE << __ffs(ad->enable_mask); + ti_clk_ll_ops->clk_writel(v, ad->control_reg); +} + +static int dra7_apll_is_enabled(struct clk_hw *hw) +{ + struct clk_hw_omap *clk = to_clk_hw_omap(hw); + struct dpll_data *ad; + u32 v; + + ad = clk->dpll_data; + + v = ti_clk_ll_ops->clk_readl(ad->control_reg); + v &= ad->enable_mask; + + v >>= __ffs(ad->enable_mask); + + return v == APLL_AUTO_IDLE ? 0 : 1; +} + +static u8 dra7_init_apll_parent(struct clk_hw *hw) +{ + return 0; +} + +static const struct clk_ops apll_ck_ops = { + .enable = &dra7_apll_enable, + .disable = &dra7_apll_disable, + .is_enabled = &dra7_apll_is_enabled, + .get_parent = &dra7_init_apll_parent, +}; + +static void __init omap_clk_register_apll(struct clk_hw *hw, + struct device_node *node) +{ + struct clk_hw_omap *clk_hw = to_clk_hw_omap(hw); + struct dpll_data *ad = clk_hw->dpll_data; + struct clk *clk; + + ad->clk_ref = of_clk_get(node, 0); + ad->clk_bypass = of_clk_get(node, 1); + + if (IS_ERR(ad->clk_ref) || IS_ERR(ad->clk_bypass)) { + pr_debug("clk-ref or clk-bypass for %s not ready, retry\n", + node->name); + if (!ti_clk_retry_init(node, hw, omap_clk_register_apll)) + return; + + goto cleanup; + } + + clk = clk_register(NULL, &clk_hw->hw); + if (!IS_ERR(clk)) { + of_clk_add_provider(node, of_clk_src_simple_get, clk); + kfree(clk_hw->hw.init->parent_names); + kfree(clk_hw->hw.init); + return; + } + +cleanup: + kfree(clk_hw->dpll_data); + kfree(clk_hw->hw.init->parent_names); + kfree(clk_hw->hw.init); + kfree(clk_hw); +} + +static void __init of_dra7_apll_setup(struct device_node *node) +{ + struct dpll_data *ad = NULL; + struct clk_hw_omap *clk_hw = NULL; + struct clk_init_data *init = NULL; + const char **parent_names = NULL; + int i; + + ad = kzalloc(sizeof(*ad), GFP_KERNEL); + clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL); + init = kzalloc(sizeof(*init), GFP_KERNEL); + if (!ad || !clk_hw || !init) + goto cleanup; + + clk_hw->dpll_data = ad; + clk_hw->hw.init = init; + clk_hw->flags = MEMMAP_ADDRESSING; + + init->name = node->name; + init->ops = &apll_ck_ops; + + init->num_parents = of_clk_get_parent_count(node); + if (init->num_parents < 1) { + pr_err("dra7 apll %s must have parent(s)\n", node->name); + goto cleanup; + } + + parent_names = kzalloc(sizeof(char *) * init->num_parents, GFP_KERNEL); + if (!parent_names) + goto cleanup; + + for (i = 0; i < init->num_parents; i++) + parent_names[i] = of_clk_get_parent_name(node, i); + + init->parent_names = parent_names; + + ad->control_reg = ti_clk_get_reg_addr(node, 0); + ad->idlest_reg = ti_clk_get_reg_addr(node, 1); + + if (!ad->control_reg || !ad->idlest_reg) + goto cleanup; + + ad->idlest_mask = 0x1; + ad->enable_mask = 0x3; + + omap_clk_register_apll(&clk_hw->hw, node); + return; + +cleanup: + kfree(parent_names); + kfree(ad); + kfree(clk_hw); + kfree(init); +} +CLK_OF_DECLARE(dra7_apll_clock, "ti,dra7-apll-clock", of_dra7_apll_setup); -- cgit v1.2.3-59-g8ed1b From 251a449dd3290d5af35da1113e155a37bf8b3ece Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Thu, 18 Jul 2013 17:41:00 +0300 Subject: CLK: TI: add dra7 clock init file clk-7xx.c now contains the clock init functionality for dra7, including DT clock registration and adding of static clkdev entries. Signed-off-by: Tero Kristo Tested-by: Nishanth Menon Acked-by: Tony Lindgren Signed-off-by: Mike Turquette --- drivers/clk/ti/Makefile | 1 + drivers/clk/ti/clk-7xx.c | 332 +++++++++++++++++++++++++++++++++++++++++++++++ include/linux/clk/ti.h | 1 + 3 files changed, 334 insertions(+) create mode 100644 drivers/clk/ti/clk-7xx.c diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile index 26e994ac3557..cd445cafcdd9 100644 --- a/drivers/clk/ti/Makefile +++ b/drivers/clk/ti/Makefile @@ -4,4 +4,5 @@ clk-common = dpll.o composite.o divider.o gate.o \ fixed-factor.o mux.o apll.o obj-$(CONFIG_ARCH_OMAP4) += $(clk-common) clk-44xx.o obj-$(CONFIG_SOC_OMAP5) += $(clk-common) clk-54xx.o +obj-$(CONFIG_SOC_DRA7XX) += $(clk-common) clk-7xx.o endif diff --git a/drivers/clk/ti/clk-7xx.c b/drivers/clk/ti/clk-7xx.c new file mode 100644 index 000000000000..9977653f2d63 --- /dev/null +++ b/drivers/clk/ti/clk-7xx.c @@ -0,0 +1,332 @@ +/* + * DRA7 Clock init + * + * Copyright (C) 2013 Texas Instruments, Inc. + * + * Tero Kristo (t-kristo@ti.com) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include + +#define DRA7_DPLL_ABE_DEFFREQ 361267200 +#define DRA7_DPLL_GMAC_DEFFREQ 1000000000 + + +static struct ti_dt_clk dra7xx_clks[] = { + DT_CLK(NULL, "atl_clkin0_ck", "atl_clkin0_ck"), + DT_CLK(NULL, "atl_clkin1_ck", "atl_clkin1_ck"), + DT_CLK(NULL, "atl_clkin2_ck", "atl_clkin2_ck"), + DT_CLK(NULL, "atlclkin3_ck", "atlclkin3_ck"), + DT_CLK(NULL, "hdmi_clkin_ck", "hdmi_clkin_ck"), + DT_CLK(NULL, "mlb_clkin_ck", "mlb_clkin_ck"), + DT_CLK(NULL, "mlbp_clkin_ck", "mlbp_clkin_ck"), + DT_CLK(NULL, "pciesref_acs_clk_ck", "pciesref_acs_clk_ck"), + DT_CLK(NULL, "ref_clkin0_ck", "ref_clkin0_ck"), + DT_CLK(NULL, "ref_clkin1_ck", "ref_clkin1_ck"), + DT_CLK(NULL, "ref_clkin2_ck", "ref_clkin2_ck"), + DT_CLK(NULL, "ref_clkin3_ck", "ref_clkin3_ck"), + DT_CLK(NULL, "rmii_clk_ck", "rmii_clk_ck"), + DT_CLK(NULL, "sdvenc_clkin_ck", "sdvenc_clkin_ck"), + DT_CLK(NULL, "secure_32k_clk_src_ck", "secure_32k_clk_src_ck"), + DT_CLK(NULL, "sys_32k_ck", "sys_32k_ck"), + DT_CLK(NULL, "virt_12000000_ck", "virt_12000000_ck"), + DT_CLK(NULL, "virt_13000000_ck", "virt_13000000_ck"), + DT_CLK(NULL, "virt_16800000_ck", "virt_16800000_ck"), + DT_CLK(NULL, "virt_19200000_ck", "virt_19200000_ck"), + DT_CLK(NULL, "virt_20000000_ck", "virt_20000000_ck"), + DT_CLK(NULL, "virt_26000000_ck", "virt_26000000_ck"), + DT_CLK(NULL, "virt_27000000_ck", "virt_27000000_ck"), + DT_CLK(NULL, "virt_38400000_ck", "virt_38400000_ck"), + DT_CLK(NULL, "sys_clkin1", "sys_clkin1"), + DT_CLK(NULL, "sys_clkin2", "sys_clkin2"), + DT_CLK(NULL, "usb_otg_clkin_ck", "usb_otg_clkin_ck"), + DT_CLK(NULL, "video1_clkin_ck", "video1_clkin_ck"), + DT_CLK(NULL, "video1_m2_clkin_ck", "video1_m2_clkin_ck"), + DT_CLK(NULL, "video2_clkin_ck", "video2_clkin_ck"), + DT_CLK(NULL, "video2_m2_clkin_ck", "video2_m2_clkin_ck"), + DT_CLK(NULL, "abe_dpll_sys_clk_mux", "abe_dpll_sys_clk_mux"), + DT_CLK(NULL, "abe_dpll_bypass_clk_mux", "abe_dpll_bypass_clk_mux"), + DT_CLK(NULL, "abe_dpll_clk_mux", "abe_dpll_clk_mux"), + DT_CLK(NULL, "dpll_abe_ck", "dpll_abe_ck"), + DT_CLK(NULL, "dpll_abe_x2_ck", "dpll_abe_x2_ck"), + DT_CLK(NULL, "dpll_abe_m2x2_ck", "dpll_abe_m2x2_ck"), + DT_CLK(NULL, "abe_24m_fclk", "abe_24m_fclk"), + DT_CLK(NULL, "abe_clk", "abe_clk"), + DT_CLK(NULL, "aess_fclk", "aess_fclk"), + DT_CLK(NULL, "abe_giclk_div", "abe_giclk_div"), + DT_CLK(NULL, "abe_lp_clk_div", "abe_lp_clk_div"), + DT_CLK(NULL, "abe_sys_clk_div", "abe_sys_clk_div"), + DT_CLK(NULL, "adc_gfclk_mux", "adc_gfclk_mux"), + DT_CLK(NULL, "dpll_pcie_ref_ck", "dpll_pcie_ref_ck"), + DT_CLK(NULL, "dpll_pcie_ref_m2ldo_ck", "dpll_pcie_ref_m2ldo_ck"), + DT_CLK(NULL, "apll_pcie_ck", "apll_pcie_ck"), + DT_CLK(NULL, "apll_pcie_clkvcoldo", "apll_pcie_clkvcoldo"), + DT_CLK(NULL, "apll_pcie_clkvcoldo_div", "apll_pcie_clkvcoldo_div"), + DT_CLK(NULL, "apll_pcie_m2_ck", "apll_pcie_m2_ck"), + DT_CLK(NULL, "sys_clk1_dclk_div", "sys_clk1_dclk_div"), + DT_CLK(NULL, "sys_clk2_dclk_div", "sys_clk2_dclk_div"), + DT_CLK(NULL, "dpll_abe_m2_ck", "dpll_abe_m2_ck"), + DT_CLK(NULL, "per_abe_x1_dclk_div", "per_abe_x1_dclk_div"), + DT_CLK(NULL, "dpll_abe_m3x2_ck", "dpll_abe_m3x2_ck"), + DT_CLK(NULL, "dpll_core_ck", "dpll_core_ck"), + DT_CLK(NULL, "dpll_core_x2_ck", "dpll_core_x2_ck"), + DT_CLK(NULL, "dpll_core_h12x2_ck", "dpll_core_h12x2_ck"), + DT_CLK(NULL, "mpu_dpll_hs_clk_div", "mpu_dpll_hs_clk_div"), + DT_CLK(NULL, "dpll_mpu_ck", "dpll_mpu_ck"), + DT_CLK(NULL, "dpll_mpu_m2_ck", "dpll_mpu_m2_ck"), + DT_CLK(NULL, "mpu_dclk_div", "mpu_dclk_div"), + DT_CLK(NULL, "dsp_dpll_hs_clk_div", "dsp_dpll_hs_clk_div"), + DT_CLK(NULL, "dpll_dsp_ck", "dpll_dsp_ck"), + DT_CLK(NULL, "dpll_dsp_m2_ck", "dpll_dsp_m2_ck"), + DT_CLK(NULL, "dsp_gclk_div", "dsp_gclk_div"), + DT_CLK(NULL, "iva_dpll_hs_clk_div", "iva_dpll_hs_clk_div"), + DT_CLK(NULL, "dpll_iva_ck", "dpll_iva_ck"), + DT_CLK(NULL, "dpll_iva_m2_ck", "dpll_iva_m2_ck"), + DT_CLK(NULL, "iva_dclk", "iva_dclk"), + DT_CLK(NULL, "dpll_gpu_ck", "dpll_gpu_ck"), + DT_CLK(NULL, "dpll_gpu_m2_ck", "dpll_gpu_m2_ck"), + DT_CLK(NULL, "gpu_dclk", "gpu_dclk"), + DT_CLK(NULL, "dpll_core_m2_ck", "dpll_core_m2_ck"), + DT_CLK(NULL, "core_dpll_out_dclk_div", "core_dpll_out_dclk_div"), + DT_CLK(NULL, "dpll_ddr_ck", "dpll_ddr_ck"), + DT_CLK(NULL, "dpll_ddr_m2_ck", "dpll_ddr_m2_ck"), + DT_CLK(NULL, "emif_phy_dclk_div", "emif_phy_dclk_div"), + DT_CLK(NULL, "dpll_gmac_ck", "dpll_gmac_ck"), + DT_CLK(NULL, "dpll_gmac_m2_ck", "dpll_gmac_m2_ck"), + DT_CLK(NULL, "gmac_250m_dclk_div", "gmac_250m_dclk_div"), + DT_CLK(NULL, "video2_dclk_div", "video2_dclk_div"), + DT_CLK(NULL, "video1_dclk_div", "video1_dclk_div"), + DT_CLK(NULL, "hdmi_dclk_div", "hdmi_dclk_div"), + DT_CLK(NULL, "per_dpll_hs_clk_div", "per_dpll_hs_clk_div"), + DT_CLK(NULL, "dpll_per_ck", "dpll_per_ck"), + DT_CLK(NULL, "dpll_per_m2_ck", "dpll_per_m2_ck"), + DT_CLK(NULL, "func_96m_aon_dclk_div", "func_96m_aon_dclk_div"), + DT_CLK(NULL, "usb_dpll_hs_clk_div", "usb_dpll_hs_clk_div"), + DT_CLK(NULL, "dpll_usb_ck", "dpll_usb_ck"), + DT_CLK(NULL, "dpll_usb_m2_ck", "dpll_usb_m2_ck"), + DT_CLK(NULL, "l3init_480m_dclk_div", "l3init_480m_dclk_div"), + DT_CLK(NULL, "usb_otg_dclk_div", "usb_otg_dclk_div"), + DT_CLK(NULL, "sata_dclk_div", "sata_dclk_div"), + DT_CLK(NULL, "dpll_pcie_ref_m2_ck", "dpll_pcie_ref_m2_ck"), + DT_CLK(NULL, "pcie2_dclk_div", "pcie2_dclk_div"), + DT_CLK(NULL, "pcie_dclk_div", "pcie_dclk_div"), + DT_CLK(NULL, "emu_dclk_div", "emu_dclk_div"), + DT_CLK(NULL, "secure_32k_dclk_div", "secure_32k_dclk_div"), + DT_CLK(NULL, "eve_dpll_hs_clk_div", "eve_dpll_hs_clk_div"), + DT_CLK(NULL, "dpll_eve_ck", "dpll_eve_ck"), + DT_CLK(NULL, "dpll_eve_m2_ck", "dpll_eve_m2_ck"), + DT_CLK(NULL, "eve_dclk_div", "eve_dclk_div"), + DT_CLK(NULL, "clkoutmux0_clk_mux", "clkoutmux0_clk_mux"), + DT_CLK(NULL, "clkoutmux1_clk_mux", "clkoutmux1_clk_mux"), + DT_CLK(NULL, "clkoutmux2_clk_mux", "clkoutmux2_clk_mux"), + DT_CLK(NULL, "custefuse_sys_gfclk_div", "custefuse_sys_gfclk_div"), + DT_CLK(NULL, "dpll_core_h13x2_ck", "dpll_core_h13x2_ck"), + DT_CLK(NULL, "dpll_core_h14x2_ck", "dpll_core_h14x2_ck"), + DT_CLK(NULL, "dpll_core_h22x2_ck", "dpll_core_h22x2_ck"), + DT_CLK(NULL, "dpll_core_h23x2_ck", "dpll_core_h23x2_ck"), + DT_CLK(NULL, "dpll_core_h24x2_ck", "dpll_core_h24x2_ck"), + DT_CLK(NULL, "dpll_ddr_x2_ck", "dpll_ddr_x2_ck"), + DT_CLK(NULL, "dpll_ddr_h11x2_ck", "dpll_ddr_h11x2_ck"), + DT_CLK(NULL, "dpll_dsp_x2_ck", "dpll_dsp_x2_ck"), + DT_CLK(NULL, "dpll_dsp_m3x2_ck", "dpll_dsp_m3x2_ck"), + DT_CLK(NULL, "dpll_gmac_x2_ck", "dpll_gmac_x2_ck"), + DT_CLK(NULL, "dpll_gmac_h11x2_ck", "dpll_gmac_h11x2_ck"), + DT_CLK(NULL, "dpll_gmac_h12x2_ck", "dpll_gmac_h12x2_ck"), + DT_CLK(NULL, "dpll_gmac_h13x2_ck", "dpll_gmac_h13x2_ck"), + DT_CLK(NULL, "dpll_gmac_m3x2_ck", "dpll_gmac_m3x2_ck"), + DT_CLK(NULL, "dpll_per_x2_ck", "dpll_per_x2_ck"), + DT_CLK(NULL, "dpll_per_h11x2_ck", "dpll_per_h11x2_ck"), + DT_CLK(NULL, "dpll_per_h12x2_ck", "dpll_per_h12x2_ck"), + DT_CLK(NULL, "dpll_per_h13x2_ck", "dpll_per_h13x2_ck"), + DT_CLK(NULL, "dpll_per_h14x2_ck", "dpll_per_h14x2_ck"), + DT_CLK(NULL, "dpll_per_m2x2_ck", "dpll_per_m2x2_ck"), + DT_CLK(NULL, "dpll_usb_clkdcoldo", "dpll_usb_clkdcoldo"), + DT_CLK(NULL, "eve_clk", "eve_clk"), + DT_CLK(NULL, "func_128m_clk", "func_128m_clk"), + DT_CLK(NULL, "func_12m_fclk", "func_12m_fclk"), + DT_CLK(NULL, "func_24m_clk", "func_24m_clk"), + DT_CLK(NULL, "func_48m_fclk", "func_48m_fclk"), + DT_CLK(NULL, "func_96m_fclk", "func_96m_fclk"), + DT_CLK(NULL, "gmii_m_clk_div", "gmii_m_clk_div"), + DT_CLK(NULL, "hdmi_clk2_div", "hdmi_clk2_div"), + DT_CLK(NULL, "hdmi_div_clk", "hdmi_div_clk"), + DT_CLK(NULL, "hdmi_dpll_clk_mux", "hdmi_dpll_clk_mux"), + DT_CLK(NULL, "l3_iclk_div", "l3_iclk_div"), + DT_CLK(NULL, "l3init_60m_fclk", "l3init_60m_fclk"), + DT_CLK(NULL, "l4_root_clk_div", "l4_root_clk_div"), + DT_CLK(NULL, "mlb_clk", "mlb_clk"), + DT_CLK(NULL, "mlbp_clk", "mlbp_clk"), + DT_CLK(NULL, "per_abe_x1_gfclk2_div", "per_abe_x1_gfclk2_div"), + DT_CLK(NULL, "timer_sys_clk_div", "timer_sys_clk_div"), + DT_CLK(NULL, "video1_clk2_div", "video1_clk2_div"), + DT_CLK(NULL, "video1_div_clk", "video1_div_clk"), + DT_CLK(NULL, "video1_dpll_clk_mux", "video1_dpll_clk_mux"), + DT_CLK(NULL, "video2_clk2_div", "video2_clk2_div"), + DT_CLK(NULL, "video2_div_clk", "video2_div_clk"), + DT_CLK(NULL, "video2_dpll_clk_mux", "video2_dpll_clk_mux"), + DT_CLK(NULL, "wkupaon_iclk_mux", "wkupaon_iclk_mux"), + DT_CLK(NULL, "dss_32khz_clk", "dss_32khz_clk"), + DT_CLK(NULL, "dss_48mhz_clk", "dss_48mhz_clk"), + DT_CLK(NULL, "dss_dss_clk", "dss_dss_clk"), + DT_CLK(NULL, "dss_hdmi_clk", "dss_hdmi_clk"), + DT_CLK(NULL, "dss_video1_clk", "dss_video1_clk"), + DT_CLK(NULL, "dss_video2_clk", "dss_video2_clk"), + DT_CLK(NULL, "gpio1_dbclk", "gpio1_dbclk"), + DT_CLK(NULL, "gpio2_dbclk", "gpio2_dbclk"), + DT_CLK(NULL, "gpio3_dbclk", "gpio3_dbclk"), + DT_CLK(NULL, "gpio4_dbclk", "gpio4_dbclk"), + DT_CLK(NULL, "gpio5_dbclk", "gpio5_dbclk"), + DT_CLK(NULL, "gpio6_dbclk", "gpio6_dbclk"), + DT_CLK(NULL, "gpio7_dbclk", "gpio7_dbclk"), + DT_CLK(NULL, "gpio8_dbclk", "gpio8_dbclk"), + DT_CLK(NULL, "mmc1_clk32k", "mmc1_clk32k"), + DT_CLK(NULL, "mmc2_clk32k", "mmc2_clk32k"), + DT_CLK(NULL, "mmc3_clk32k", "mmc3_clk32k"), + DT_CLK(NULL, "mmc4_clk32k", "mmc4_clk32k"), + DT_CLK(NULL, "sata_ref_clk", "sata_ref_clk"), + DT_CLK(NULL, "usb_otg_ss1_refclk960m", "usb_otg_ss1_refclk960m"), + DT_CLK(NULL, "usb_otg_ss2_refclk960m", "usb_otg_ss2_refclk960m"), + DT_CLK(NULL, "usb_phy1_always_on_clk32k", "usb_phy1_always_on_clk32k"), + DT_CLK(NULL, "usb_phy2_always_on_clk32k", "usb_phy2_always_on_clk32k"), + DT_CLK(NULL, "usb_phy3_always_on_clk32k", "usb_phy3_always_on_clk32k"), + DT_CLK(NULL, "atl_dpll_clk_mux", "atl_dpll_clk_mux"), + DT_CLK(NULL, "atl_gfclk_mux", "atl_gfclk_mux"), + DT_CLK(NULL, "dcan1_sys_clk_mux", "dcan1_sys_clk_mux"), + DT_CLK(NULL, "gmac_gmii_ref_clk_div", "gmac_gmii_ref_clk_div"), + DT_CLK(NULL, "gmac_rft_clk_mux", "gmac_rft_clk_mux"), + DT_CLK(NULL, "gpu_core_gclk_mux", "gpu_core_gclk_mux"), + DT_CLK(NULL, "gpu_hyd_gclk_mux", "gpu_hyd_gclk_mux"), + DT_CLK(NULL, "ipu1_gfclk_mux", "ipu1_gfclk_mux"), + DT_CLK(NULL, "l3instr_ts_gclk_div", "l3instr_ts_gclk_div"), + DT_CLK(NULL, "mcasp1_ahclkr_mux", "mcasp1_ahclkr_mux"), + DT_CLK(NULL, "mcasp1_ahclkx_mux", "mcasp1_ahclkx_mux"), + DT_CLK(NULL, "mcasp1_aux_gfclk_mux", "mcasp1_aux_gfclk_mux"), + DT_CLK(NULL, "mcasp2_ahclkr_mux", "mcasp2_ahclkr_mux"), + DT_CLK(NULL, "mcasp2_ahclkx_mux", "mcasp2_ahclkx_mux"), + DT_CLK(NULL, "mcasp2_aux_gfclk_mux", "mcasp2_aux_gfclk_mux"), + DT_CLK(NULL, "mcasp3_ahclkx_mux", "mcasp3_ahclkx_mux"), + DT_CLK(NULL, "mcasp3_aux_gfclk_mux", "mcasp3_aux_gfclk_mux"), + DT_CLK(NULL, "mcasp4_ahclkx_mux", "mcasp4_ahclkx_mux"), + DT_CLK(NULL, "mcasp4_aux_gfclk_mux", "mcasp4_aux_gfclk_mux"), + DT_CLK(NULL, "mcasp5_ahclkx_mux", "mcasp5_ahclkx_mux"), + DT_CLK(NULL, "mcasp5_aux_gfclk_mux", "mcasp5_aux_gfclk_mux"), + DT_CLK(NULL, "mcasp6_ahclkx_mux", "mcasp6_ahclkx_mux"), + DT_CLK(NULL, "mcasp6_aux_gfclk_mux", "mcasp6_aux_gfclk_mux"), + DT_CLK(NULL, "mcasp7_ahclkx_mux", "mcasp7_ahclkx_mux"), + DT_CLK(NULL, "mcasp7_aux_gfclk_mux", "mcasp7_aux_gfclk_mux"), + DT_CLK(NULL, "mcasp8_ahclk_mux", "mcasp8_ahclk_mux"), + DT_CLK(NULL, "mcasp8_aux_gfclk_mux", "mcasp8_aux_gfclk_mux"), + DT_CLK(NULL, "mmc1_fclk_mux", "mmc1_fclk_mux"), + DT_CLK(NULL, "mmc1_fclk_div", "mmc1_fclk_div"), + DT_CLK(NULL, "mmc2_fclk_mux", "mmc2_fclk_mux"), + DT_CLK(NULL, "mmc2_fclk_div", "mmc2_fclk_div"), + DT_CLK(NULL, "mmc3_gfclk_mux", "mmc3_gfclk_mux"), + DT_CLK(NULL, "mmc3_gfclk_div", "mmc3_gfclk_div"), + DT_CLK(NULL, "mmc4_gfclk_mux", "mmc4_gfclk_mux"), + DT_CLK(NULL, "mmc4_gfclk_div", "mmc4_gfclk_div"), + DT_CLK(NULL, "qspi_gfclk_mux", "qspi_gfclk_mux"), + DT_CLK(NULL, "qspi_gfclk_div", "qspi_gfclk_div"), + DT_CLK(NULL, "timer10_gfclk_mux", "timer10_gfclk_mux"), + DT_CLK(NULL, "timer11_gfclk_mux", "timer11_gfclk_mux"), + DT_CLK(NULL, "timer13_gfclk_mux", "timer13_gfclk_mux"), + DT_CLK(NULL, "timer14_gfclk_mux", "timer14_gfclk_mux"), + DT_CLK(NULL, "timer15_gfclk_mux", "timer15_gfclk_mux"), + DT_CLK(NULL, "timer16_gfclk_mux", "timer16_gfclk_mux"), + DT_CLK(NULL, "timer1_gfclk_mux", "timer1_gfclk_mux"), + DT_CLK(NULL, "timer2_gfclk_mux", "timer2_gfclk_mux"), + DT_CLK(NULL, "timer3_gfclk_mux", "timer3_gfclk_mux"), + DT_CLK(NULL, "timer4_gfclk_mux", "timer4_gfclk_mux"), + DT_CLK(NULL, "timer5_gfclk_mux", "timer5_gfclk_mux"), + DT_CLK(NULL, "timer6_gfclk_mux", "timer6_gfclk_mux"), + DT_CLK(NULL, "timer7_gfclk_mux", "timer7_gfclk_mux"), + DT_CLK(NULL, "timer8_gfclk_mux", "timer8_gfclk_mux"), + DT_CLK(NULL, "timer9_gfclk_mux", "timer9_gfclk_mux"), + DT_CLK(NULL, "uart10_gfclk_mux", "uart10_gfclk_mux"), + DT_CLK(NULL, "uart1_gfclk_mux", "uart1_gfclk_mux"), + DT_CLK(NULL, "uart2_gfclk_mux", "uart2_gfclk_mux"), + DT_CLK(NULL, "uart3_gfclk_mux", "uart3_gfclk_mux"), + DT_CLK(NULL, "uart4_gfclk_mux", "uart4_gfclk_mux"), + DT_CLK(NULL, "uart5_gfclk_mux", "uart5_gfclk_mux"), + DT_CLK(NULL, "uart6_gfclk_mux", "uart6_gfclk_mux"), + DT_CLK(NULL, "uart7_gfclk_mux", "uart7_gfclk_mux"), + DT_CLK(NULL, "uart8_gfclk_mux", "uart8_gfclk_mux"), + DT_CLK(NULL, "uart9_gfclk_mux", "uart9_gfclk_mux"), + DT_CLK(NULL, "vip1_gclk_mux", "vip1_gclk_mux"), + DT_CLK(NULL, "vip2_gclk_mux", "vip2_gclk_mux"), + DT_CLK(NULL, "vip3_gclk_mux", "vip3_gclk_mux"), + DT_CLK(NULL, "gpmc_ck", "dummy_ck"), + DT_CLK("omap_i2c.1", "ick", "dummy_ck"), + DT_CLK("omap_i2c.2", "ick", "dummy_ck"), + DT_CLK("omap_i2c.3", "ick", "dummy_ck"), + DT_CLK("omap_i2c.4", "ick", "dummy_ck"), + DT_CLK(NULL, "mailboxes_ick", "dummy_ck"), + DT_CLK("omap_hsmmc.0", "ick", "dummy_ck"), + DT_CLK("omap_hsmmc.1", "ick", "dummy_ck"), + DT_CLK("omap_hsmmc.2", "ick", "dummy_ck"), + DT_CLK("omap_hsmmc.3", "ick", "dummy_ck"), + DT_CLK("omap_hsmmc.4", "ick", "dummy_ck"), + DT_CLK("omap-mcbsp.1", "ick", "dummy_ck"), + DT_CLK("omap-mcbsp.2", "ick", "dummy_ck"), + DT_CLK("omap-mcbsp.3", "ick", "dummy_ck"), + DT_CLK("omap-mcbsp.4", "ick", "dummy_ck"), + DT_CLK("omap2_mcspi.1", "ick", "dummy_ck"), + DT_CLK("omap2_mcspi.2", "ick", "dummy_ck"), + DT_CLK("omap2_mcspi.3", "ick", "dummy_ck"), + DT_CLK("omap2_mcspi.4", "ick", "dummy_ck"), + DT_CLK(NULL, "uart1_ick", "dummy_ck"), + DT_CLK(NULL, "uart2_ick", "dummy_ck"), + DT_CLK(NULL, "uart3_ick", "dummy_ck"), + DT_CLK(NULL, "uart4_ick", "dummy_ck"), + DT_CLK("usbhs_omap", "usbhost_ick", "dummy_ck"), + DT_CLK("usbhs_omap", "usbtll_fck", "dummy_ck"), + DT_CLK("omap_wdt", "ick", "dummy_ck"), + DT_CLK(NULL, "timer_32k_ck", "sys_32k_ck"), + DT_CLK("4ae18000.timer", "timer_sys_ck", "sys_clkin2"), + DT_CLK("48032000.timer", "timer_sys_ck", "sys_clkin2"), + DT_CLK("48034000.timer", "timer_sys_ck", "sys_clkin2"), + DT_CLK("48036000.timer", "timer_sys_ck", "sys_clkin2"), + DT_CLK("4803e000.timer", "timer_sys_ck", "sys_clkin2"), + DT_CLK("48086000.timer", "timer_sys_ck", "sys_clkin2"), + DT_CLK("48088000.timer", "timer_sys_ck", "sys_clkin2"), + DT_CLK("48820000.timer", "timer_sys_ck", "timer_sys_clk_div"), + DT_CLK("48822000.timer", "timer_sys_ck", "timer_sys_clk_div"), + DT_CLK("48824000.timer", "timer_sys_ck", "timer_sys_clk_div"), + DT_CLK("48826000.timer", "timer_sys_ck", "timer_sys_clk_div"), + DT_CLK(NULL, "sys_clkin", "sys_clkin1"), + { .node_name = NULL }, +}; + +int __init dra7xx_dt_clk_init(void) +{ + int rc; + struct clk *abe_dpll_mux, *sys_clkin2, *dpll_ck; + + ti_dt_clocks_register(dra7xx_clks); + + omap2_clk_disable_autoidle_all(); + + abe_dpll_mux = clk_get_sys(NULL, "abe_dpll_sys_clk_mux"); + sys_clkin2 = clk_get_sys(NULL, "sys_clkin2"); + dpll_ck = clk_get_sys(NULL, "dpll_abe_ck"); + + rc = clk_set_parent(abe_dpll_mux, sys_clkin2); + if (!rc) + rc = clk_set_rate(dpll_ck, DRA7_DPLL_ABE_DEFFREQ); + if (rc) + pr_err("%s: failed to configure ABE DPLL!\n", __func__); + + dpll_ck = clk_get_sys(NULL, "dpll_gmac_ck"); + rc = clk_set_rate(dpll_ck, DRA7_DPLL_GMAC_DEFFREQ); + if (rc) + pr_err("%s: failed to configure GMAC DPLL!\n", __func__); + + return rc; +} diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h index 6647f28b445d..506155b1fd1f 100644 --- a/include/linux/clk/ti.h +++ b/include/linux/clk/ti.h @@ -265,6 +265,7 @@ int ti_clk_add_component(struct device_node *node, struct clk_hw *hw, int type); int omap4xxx_dt_clk_init(void); int omap5xxx_dt_clk_init(void); +int dra7xx_dt_clk_init(void); #ifdef CONFIG_OF void of_ti_clk_allow_autoidle_all(void); -- cgit v1.2.3-59-g8ed1b From 45622e2162b6d5907006f4595f2ac862afe1dfb5 Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Fri, 19 Jul 2013 11:36:01 +0300 Subject: CLK: TI: add am33xx clock init file clk-33xx.c now contains the clock init functionality for am33xx, including DT clock registration and adding of static clkdev entries. This patch also moves the omap2_clk_enable_init_clocks declaration to the driver include, as this is needed by the am33xx clock init code. Signed-off-by: Tero Kristo Tested-by: Nishanth Menon Acked-by: Tony Lindgren Signed-off-by: Mike Turquette --- arch/arm/mach-omap2/clock.h | 1 - drivers/clk/ti/Makefile | 1 + drivers/clk/ti/clk-33xx.c | 161 ++++++++++++++++++++++++++++++++++++++++++++ include/linux/clk/ti.h | 2 + 4 files changed, 164 insertions(+), 1 deletion(-) create mode 100644 drivers/clk/ti/clk-33xx.c diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h index b83fca6bc227..1da9dc32fa4e 100644 --- a/arch/arm/mach-omap2/clock.h +++ b/arch/arm/mach-omap2/clock.h @@ -249,7 +249,6 @@ void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk, int omap2_clk_enable_autoidle_all(void); int omap2_clk_allow_idle(struct clk *clk); int omap2_clk_deny_idle(struct clk *clk); -void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks); int omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name); void omap2_clk_print_new_rates(const char *hfclkin_ck_name, const char *core_ck_name, diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile index cd445cafcdd9..51b00f80cc14 100644 --- a/drivers/clk/ti/Makefile +++ b/drivers/clk/ti/Makefile @@ -2,6 +2,7 @@ ifneq ($(CONFIG_OF),) obj-y += clk.o autoidle.o clockdomain.o clk-common = dpll.o composite.o divider.o gate.o \ fixed-factor.o mux.o apll.o +obj-$(CONFIG_SOC_AM33XX) += $(clk-common) clk-33xx.o obj-$(CONFIG_ARCH_OMAP4) += $(clk-common) clk-44xx.o obj-$(CONFIG_SOC_OMAP5) += $(clk-common) clk-54xx.o obj-$(CONFIG_SOC_DRA7XX) += $(clk-common) clk-7xx.o diff --git a/drivers/clk/ti/clk-33xx.c b/drivers/clk/ti/clk-33xx.c new file mode 100644 index 000000000000..776ee4594bd4 --- /dev/null +++ b/drivers/clk/ti/clk-33xx.c @@ -0,0 +1,161 @@ +/* + * AM33XX Clock init + * + * Copyright (C) 2013 Texas Instruments, Inc + * Tero Kristo (t-kristo@ti.com) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include + +static struct ti_dt_clk am33xx_clks[] = { + DT_CLK(NULL, "clk_32768_ck", "clk_32768_ck"), + DT_CLK(NULL, "clk_rc32k_ck", "clk_rc32k_ck"), + DT_CLK(NULL, "virt_19200000_ck", "virt_19200000_ck"), + DT_CLK(NULL, "virt_24000000_ck", "virt_24000000_ck"), + DT_CLK(NULL, "virt_25000000_ck", "virt_25000000_ck"), + DT_CLK(NULL, "virt_26000000_ck", "virt_26000000_ck"), + DT_CLK(NULL, "sys_clkin_ck", "sys_clkin_ck"), + DT_CLK(NULL, "tclkin_ck", "tclkin_ck"), + DT_CLK(NULL, "dpll_core_ck", "dpll_core_ck"), + DT_CLK(NULL, "dpll_core_x2_ck", "dpll_core_x2_ck"), + DT_CLK(NULL, "dpll_core_m4_ck", "dpll_core_m4_ck"), + DT_CLK(NULL, "dpll_core_m5_ck", "dpll_core_m5_ck"), + DT_CLK(NULL, "dpll_core_m6_ck", "dpll_core_m6_ck"), + DT_CLK(NULL, "dpll_mpu_ck", "dpll_mpu_ck"), + DT_CLK("cpu0", NULL, "dpll_mpu_ck"), + DT_CLK(NULL, "dpll_mpu_m2_ck", "dpll_mpu_m2_ck"), + DT_CLK(NULL, "dpll_ddr_ck", "dpll_ddr_ck"), + DT_CLK(NULL, "dpll_ddr_m2_ck", "dpll_ddr_m2_ck"), + DT_CLK(NULL, "dpll_ddr_m2_div2_ck", "dpll_ddr_m2_div2_ck"), + DT_CLK(NULL, "dpll_disp_ck", "dpll_disp_ck"), + DT_CLK(NULL, "dpll_disp_m2_ck", "dpll_disp_m2_ck"), + DT_CLK(NULL, "dpll_per_ck", "dpll_per_ck"), + DT_CLK(NULL, "dpll_per_m2_ck", "dpll_per_m2_ck"), + DT_CLK(NULL, "dpll_per_m2_div4_wkupdm_ck", "dpll_per_m2_div4_wkupdm_ck"), + DT_CLK(NULL, "dpll_per_m2_div4_ck", "dpll_per_m2_div4_ck"), + DT_CLK(NULL, "adc_tsc_fck", "adc_tsc_fck"), + DT_CLK(NULL, "cefuse_fck", "cefuse_fck"), + DT_CLK(NULL, "clkdiv32k_ck", "clkdiv32k_ck"), + DT_CLK(NULL, "clkdiv32k_ick", "clkdiv32k_ick"), + DT_CLK(NULL, "dcan0_fck", "dcan0_fck"), + DT_CLK("481cc000.d_can", NULL, "dcan0_fck"), + DT_CLK(NULL, "dcan1_fck", "dcan1_fck"), + DT_CLK("481d0000.d_can", NULL, "dcan1_fck"), + DT_CLK(NULL, "pruss_ocp_gclk", "pruss_ocp_gclk"), + DT_CLK(NULL, "mcasp0_fck", "mcasp0_fck"), + DT_CLK(NULL, "mcasp1_fck", "mcasp1_fck"), + DT_CLK(NULL, "mmu_fck", "mmu_fck"), + DT_CLK(NULL, "smartreflex0_fck", "smartreflex0_fck"), + DT_CLK(NULL, "smartreflex1_fck", "smartreflex1_fck"), + DT_CLK(NULL, "sha0_fck", "sha0_fck"), + DT_CLK(NULL, "aes0_fck", "aes0_fck"), + DT_CLK(NULL, "rng_fck", "rng_fck"), + DT_CLK(NULL, "timer1_fck", "timer1_fck"), + DT_CLK(NULL, "timer2_fck", "timer2_fck"), + DT_CLK(NULL, "timer3_fck", "timer3_fck"), + DT_CLK(NULL, "timer4_fck", "timer4_fck"), + DT_CLK(NULL, "timer5_fck", "timer5_fck"), + DT_CLK(NULL, "timer6_fck", "timer6_fck"), + DT_CLK(NULL, "timer7_fck", "timer7_fck"), + DT_CLK(NULL, "usbotg_fck", "usbotg_fck"), + DT_CLK(NULL, "ieee5000_fck", "ieee5000_fck"), + DT_CLK(NULL, "wdt1_fck", "wdt1_fck"), + DT_CLK(NULL, "l4_rtc_gclk", "l4_rtc_gclk"), + DT_CLK(NULL, "l3_gclk", "l3_gclk"), + DT_CLK(NULL, "dpll_core_m4_div2_ck", "dpll_core_m4_div2_ck"), + DT_CLK(NULL, "l4hs_gclk", "l4hs_gclk"), + DT_CLK(NULL, "l3s_gclk", "l3s_gclk"), + DT_CLK(NULL, "l4fw_gclk", "l4fw_gclk"), + DT_CLK(NULL, "l4ls_gclk", "l4ls_gclk"), + DT_CLK(NULL, "clk_24mhz", "clk_24mhz"), + DT_CLK(NULL, "sysclk_div_ck", "sysclk_div_ck"), + DT_CLK(NULL, "cpsw_125mhz_gclk", "cpsw_125mhz_gclk"), + DT_CLK(NULL, "cpsw_cpts_rft_clk", "cpsw_cpts_rft_clk"), + DT_CLK(NULL, "gpio0_dbclk_mux_ck", "gpio0_dbclk_mux_ck"), + DT_CLK(NULL, "gpio0_dbclk", "gpio0_dbclk"), + DT_CLK(NULL, "gpio1_dbclk", "gpio1_dbclk"), + DT_CLK(NULL, "gpio2_dbclk", "gpio2_dbclk"), + DT_CLK(NULL, "gpio3_dbclk", "gpio3_dbclk"), + DT_CLK(NULL, "lcd_gclk", "lcd_gclk"), + DT_CLK(NULL, "mmc_clk", "mmc_clk"), + DT_CLK(NULL, "gfx_fclk_clksel_ck", "gfx_fclk_clksel_ck"), + DT_CLK(NULL, "gfx_fck_div_ck", "gfx_fck_div_ck"), + DT_CLK(NULL, "sysclkout_pre_ck", "sysclkout_pre_ck"), + DT_CLK(NULL, "clkout2_div_ck", "clkout2_div_ck"), + DT_CLK(NULL, "timer_32k_ck", "clkdiv32k_ick"), + DT_CLK(NULL, "timer_sys_ck", "sys_clkin_ck"), + DT_CLK(NULL, "dbg_sysclk_ck", "dbg_sysclk_ck"), + DT_CLK(NULL, "dbg_clka_ck", "dbg_clka_ck"), + DT_CLK(NULL, "stm_pmd_clock_mux_ck", "stm_pmd_clock_mux_ck"), + DT_CLK(NULL, "trace_pmd_clk_mux_ck", "trace_pmd_clk_mux_ck"), + DT_CLK(NULL, "stm_clk_div_ck", "stm_clk_div_ck"), + DT_CLK(NULL, "trace_clk_div_ck", "trace_clk_div_ck"), + DT_CLK(NULL, "clkout2_ck", "clkout2_ck"), + DT_CLK("48300200.ehrpwm", "tbclk", "ehrpwm0_tbclk"), + DT_CLK("48302200.ehrpwm", "tbclk", "ehrpwm1_tbclk"), + DT_CLK("48304200.ehrpwm", "tbclk", "ehrpwm2_tbclk"), + { .node_name = NULL }, +}; + +static const char *enable_init_clks[] = { + "dpll_ddr_m2_ck", + "dpll_mpu_m2_ck", + "l3_gclk", + "l4hs_gclk", + "l4fw_gclk", + "l4ls_gclk", + /* Required for external peripherals like, Audio codecs */ + "clkout2_ck", +}; + +int __init am33xx_dt_clk_init(void) +{ + struct clk *clk1, *clk2; + + ti_dt_clocks_register(am33xx_clks); + + omap2_clk_disable_autoidle_all(); + + omap2_clk_enable_init_clocks(enable_init_clks, + ARRAY_SIZE(enable_init_clks)); + + /* TRM ERRATA: Timer 3 & 6 default parent (TCLKIN) may not be always + * physically present, in such a case HWMOD enabling of + * clock would be failure with default parent. And timer + * probe thinks clock is already enabled, this leads to + * crash upon accessing timer 3 & 6 registers in probe. + * Fix by setting parent of both these timers to master + * oscillator clock. + */ + + clk1 = clk_get_sys(NULL, "sys_clkin_ck"); + clk2 = clk_get_sys(NULL, "timer3_fck"); + clk_set_parent(clk2, clk1); + + clk2 = clk_get_sys(NULL, "timer6_fck"); + clk_set_parent(clk2, clk1); + /* + * The On-Chip 32K RC Osc clock is not an accurate clock-source as per + * the design/spec, so as a result, for example, timer which supposed + * to get expired @60Sec, but will expire somewhere ~@40Sec, which is + * not expected by any use-case, so change WDT1 clock source to PRCM + * 32KHz clock. + */ + clk1 = clk_get_sys(NULL, "wdt1_fck"); + clk2 = clk_get_sys(NULL, "clkdiv32k_ick"); + clk_set_parent(clk1, clk2); + + return 0; +} diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h index 506155b1fd1f..0e7c8d956f2b 100644 --- a/include/linux/clk/ti.h +++ b/include/linux/clk/ti.h @@ -248,6 +248,7 @@ unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw, int omap2_clkops_enable_clkdm(struct clk_hw *hw); void omap2_clkops_disable_clkdm(struct clk_hw *hw); int omap2_clk_disable_autoidle_all(void); +void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks); int omap3_dpll4_set_rate(struct clk_hw *clk, unsigned long rate, unsigned long parent_rate); int omap2_dflt_clk_enable(struct clk_hw *hw); @@ -266,6 +267,7 @@ int ti_clk_add_component(struct device_node *node, struct clk_hw *hw, int type); int omap4xxx_dt_clk_init(void); int omap5xxx_dt_clk_init(void); int dra7xx_dt_clk_init(void); +int am33xx_dt_clk_init(void); #ifdef CONFIG_OF void of_ti_clk_allow_autoidle_all(void); -- cgit v1.2.3-59-g8ed1b From 24582b3407775d57f06becfccd8cd202bc01eda6 Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Mon, 15 Jul 2013 13:14:20 +0300 Subject: CLK: TI: add interface clock support for OMAP3 OMAP3 has interface clocks in addition to functional clocks, which require special handling for the autoidle and idle status register offsets mainly. Signed-off-by: Tero Kristo Acked-by: Tony Lindgren Signed-off-by: Mike Turquette --- .../devicetree/bindings/clock/ti/interface.txt | 54 +++++++++ arch/arm/mach-omap2/clock.h | 5 - drivers/clk/ti/Makefile | 1 + drivers/clk/ti/interface.c | 125 +++++++++++++++++++++ include/linux/clk/ti.h | 5 + 5 files changed, 185 insertions(+), 5 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/ti/interface.txt create mode 100644 drivers/clk/ti/interface.c diff --git a/Documentation/devicetree/bindings/clock/ti/interface.txt b/Documentation/devicetree/bindings/clock/ti/interface.txt new file mode 100644 index 000000000000..064e8caccac3 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/ti/interface.txt @@ -0,0 +1,54 @@ +Binding for Texas Instruments interface clock. + +Binding status: Unstable - ABI compatibility may be broken in the future + +This binding uses the common clock binding[1]. This clock is +quite much similar to the basic gate-clock [2], however, +it supports a number of additional features, including +companion clock finding (match corresponding functional gate +clock) and hardware autoidle enable / disable. + +[1] Documentation/devicetree/bindings/clock/clock-bindings.txt +[2] Documentation/devicetree/bindings/clock/gate-clock.txt + +Required properties: +- compatible : shall be one of: + "ti,omap3-interface-clock" - basic OMAP3 interface clock + "ti,omap3-no-wait-interface-clock" - interface clock which has no hardware + capability for waiting clock to be ready + "ti,omap3-hsotgusb-interface-clock" - interface clock with USB specific HW + handling + "ti,omap3-dss-interface-clock" - interface clock with DSS specific HW handling + "ti,omap3-ssi-interface-clock" - interface clock with SSI specific HW handling + "ti,am35xx-interface-clock" - interface clock with AM35xx specific HW handling +- #clock-cells : from common clock binding; shall be set to 0 +- clocks : link to phandle of parent clock +- reg : base address for the control register + +Optional properties: +- ti,bit-shift : bit shift for the bit enabling/disabling the clock (default 0) + +Examples: + aes1_ick: aes1_ick@48004a14 { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&security_l4_ick2>; + reg = <0x48004a14 0x4>; + ti,bit-shift = <3>; + }; + + cam_ick: cam_ick@48004f10 { + #clock-cells = <0>; + compatible = "ti,omap3-no-wait-interface-clock"; + clocks = <&l4_ick>; + reg = <0x48004f10 0x4>; + ti,bit-shift = <0>; + }; + + ssi_ick_3430es2: ssi_ick_3430es2@48004a10 { + #clock-cells = <0>; + compatible = "ti,omap3-ssi-interface-clock"; + clocks = <&ssi_l4_ick>; + reg = <0x48004a10 0x4>; + ti,bit-shift = <0>; + }; diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h index 1da9dc32fa4e..cbe5ff770ec4 100644 --- a/arch/arm/mach-omap2/clock.h +++ b/arch/arm/mach-omap2/clock.h @@ -270,15 +270,10 @@ extern struct clk dummy_ck; extern const struct clk_hw_omap_ops clkhwops_iclk_wait; extern const struct clk_hw_omap_ops clkhwops_wait; -extern const struct clk_hw_omap_ops clkhwops_iclk; extern const struct clk_hw_omap_ops clkhwops_omap3430es2_ssi_wait; -extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_ssi_wait; extern const struct clk_hw_omap_ops clkhwops_omap3430es2_dss_usbhost_wait; -extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_dss_usbhost_wait; -extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_hsotgusb_wait; extern const struct clk_hw_omap_ops clkhwops_omap3430es2_hsotgusb_wait; extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_module_wait; -extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_wait; extern const struct clk_hw_omap_ops clkhwops_apll54; extern const struct clk_hw_omap_ops clkhwops_apll96; extern const struct clk_hw_omap_ops clkhwops_omap2xxx_dpll; diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile index 51b00f80cc14..fff97f6aa8cb 100644 --- a/drivers/clk/ti/Makefile +++ b/drivers/clk/ti/Makefile @@ -3,6 +3,7 @@ obj-y += clk.o autoidle.o clockdomain.o clk-common = dpll.o composite.o divider.o gate.o \ fixed-factor.o mux.o apll.o obj-$(CONFIG_SOC_AM33XX) += $(clk-common) clk-33xx.o +obj-$(CONFIG_ARCH_OMAP3) += $(clk-common) interface.o obj-$(CONFIG_ARCH_OMAP4) += $(clk-common) clk-44xx.o obj-$(CONFIG_SOC_OMAP5) += $(clk-common) clk-54xx.o obj-$(CONFIG_SOC_DRA7XX) += $(clk-common) clk-7xx.o diff --git a/drivers/clk/ti/interface.c b/drivers/clk/ti/interface.c new file mode 100644 index 000000000000..320a2b168bb2 --- /dev/null +++ b/drivers/clk/ti/interface.c @@ -0,0 +1,125 @@ +/* + * OMAP interface clock support + * + * Copyright (C) 2013 Texas Instruments, Inc. + * + * Tero Kristo + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include + +#undef pr_fmt +#define pr_fmt(fmt) "%s: " fmt, __func__ + +static const struct clk_ops ti_interface_clk_ops = { + .init = &omap2_init_clk_clkdm, + .enable = &omap2_dflt_clk_enable, + .disable = &omap2_dflt_clk_disable, + .is_enabled = &omap2_dflt_clk_is_enabled, +}; + +static void __init _of_ti_interface_clk_setup(struct device_node *node, + const struct clk_hw_omap_ops *ops) +{ + struct clk *clk; + struct clk_init_data init = { NULL }; + struct clk_hw_omap *clk_hw; + const char *parent_name; + u32 val; + + clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL); + if (!clk_hw) + return; + + clk_hw->hw.init = &init; + clk_hw->ops = ops; + clk_hw->flags = MEMMAP_ADDRESSING; + + clk_hw->enable_reg = ti_clk_get_reg_addr(node, 0); + if (!clk_hw->enable_reg) + goto cleanup; + + if (!of_property_read_u32(node, "ti,bit-shift", &val)) + clk_hw->enable_bit = val; + + init.name = node->name; + init.ops = &ti_interface_clk_ops; + init.flags = 0; + + parent_name = of_clk_get_parent_name(node, 0); + if (!parent_name) { + pr_err("%s must have a parent\n", node->name); + goto cleanup; + } + + init.num_parents = 1; + init.parent_names = &parent_name; + + clk = clk_register(NULL, &clk_hw->hw); + + if (!IS_ERR(clk)) { + of_clk_add_provider(node, of_clk_src_simple_get, clk); + omap2_init_clk_hw_omap_clocks(clk); + return; + } + +cleanup: + kfree(clk_hw); +} + +static void __init of_ti_interface_clk_setup(struct device_node *node) +{ + _of_ti_interface_clk_setup(node, &clkhwops_iclk_wait); +} +CLK_OF_DECLARE(ti_interface_clk, "ti,omap3-interface-clock", + of_ti_interface_clk_setup); + +static void __init of_ti_no_wait_interface_clk_setup(struct device_node *node) +{ + _of_ti_interface_clk_setup(node, &clkhwops_iclk); +} +CLK_OF_DECLARE(ti_no_wait_interface_clk, "ti,omap3-no-wait-interface-clock", + of_ti_no_wait_interface_clk_setup); + +static void __init of_ti_hsotgusb_interface_clk_setup(struct device_node *node) +{ + _of_ti_interface_clk_setup(node, + &clkhwops_omap3430es2_iclk_hsotgusb_wait); +} +CLK_OF_DECLARE(ti_hsotgusb_interface_clk, "ti,omap3-hsotgusb-interface-clock", + of_ti_hsotgusb_interface_clk_setup); + +static void __init of_ti_dss_interface_clk_setup(struct device_node *node) +{ + _of_ti_interface_clk_setup(node, + &clkhwops_omap3430es2_iclk_dss_usbhost_wait); +} +CLK_OF_DECLARE(ti_dss_interface_clk, "ti,omap3-dss-interface-clock", + of_ti_dss_interface_clk_setup); + +static void __init of_ti_ssi_interface_clk_setup(struct device_node *node) +{ + _of_ti_interface_clk_setup(node, &clkhwops_omap3430es2_iclk_ssi_wait); +} +CLK_OF_DECLARE(ti_ssi_interface_clk, "ti,omap3-ssi-interface-clock", + of_ti_ssi_interface_clk_setup); + +static void __init of_ti_am35xx_interface_clk_setup(struct device_node *node) +{ + _of_ti_interface_clk_setup(node, &clkhwops_am35xx_ipss_wait); +} +CLK_OF_DECLARE(ti_am35xx_interface_clk, "ti,am35xx-interface-clock", + of_ti_am35xx_interface_clk_setup); diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h index 0e7c8d956f2b..17c034ea03ad 100644 --- a/include/linux/clk/ti.h +++ b/include/linux/clk/ti.h @@ -282,6 +282,11 @@ extern const struct clk_hw_omap_ops clkhwops_omap4_dpllmx; extern const struct clk_hw_omap_ops clkhwops_wait; extern const struct clk_hw_omap_ops clkhwops_omap3430es2_dss_usbhost_wait; extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_module_wait; +extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_wait; +extern const struct clk_hw_omap_ops clkhwops_iclk; extern const struct clk_hw_omap_ops clkhwops_iclk_wait; +extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_ssi_wait; +extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_dss_usbhost_wait; +extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_hsotgusb_wait; #endif -- cgit v1.2.3-59-g8ed1b From aafd900cab87d339dc3004c241eebc854005124b Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Fri, 2 Aug 2013 14:04:19 +0300 Subject: CLK: TI: add omap3 clock init file clk-3xxx.c now contains the clock init functionality for omap3, including DT clock registration and adding of static clkdev entries. Signed-off-by: Tero Kristo Tested-by: Nishanth Menon Acked-by: Tony Lindgren Signed-off-by: Mike Turquette --- arch/arm/mach-omap2/clock3xxx.h | 1 - drivers/clk/ti/Makefile | 2 +- drivers/clk/ti/clk-3xxx.c | 401 ++++++++++++++++++++++++++++++++++++++++ include/linux/clk/ti.h | 5 + 4 files changed, 407 insertions(+), 2 deletions(-) create mode 100644 drivers/clk/ti/clk-3xxx.c diff --git a/arch/arm/mach-omap2/clock3xxx.h b/arch/arm/mach-omap2/clock3xxx.h index dab90e281aeb..78d9f562e3ce 100644 --- a/arch/arm/mach-omap2/clock3xxx.h +++ b/arch/arm/mach-omap2/clock3xxx.h @@ -11,7 +11,6 @@ int omap3xxx_clk_init(void); int omap3_core_dpll_m2_set_rate(struct clk_hw *clk, unsigned long rate, unsigned long parent_rate); -void omap3_clk_lock_dpll5(void); extern struct clk *sdrc_ick_p; extern struct clk *arm_fck_p; diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile index fff97f6aa8cb..99ead078b109 100644 --- a/drivers/clk/ti/Makefile +++ b/drivers/clk/ti/Makefile @@ -3,7 +3,7 @@ obj-y += clk.o autoidle.o clockdomain.o clk-common = dpll.o composite.o divider.o gate.o \ fixed-factor.o mux.o apll.o obj-$(CONFIG_SOC_AM33XX) += $(clk-common) clk-33xx.o -obj-$(CONFIG_ARCH_OMAP3) += $(clk-common) interface.o +obj-$(CONFIG_ARCH_OMAP3) += $(clk-common) interface.o clk-3xxx.o obj-$(CONFIG_ARCH_OMAP4) += $(clk-common) clk-44xx.o obj-$(CONFIG_SOC_OMAP5) += $(clk-common) clk-54xx.o obj-$(CONFIG_SOC_DRA7XX) += $(clk-common) clk-7xx.o diff --git a/drivers/clk/ti/clk-3xxx.c b/drivers/clk/ti/clk-3xxx.c new file mode 100644 index 000000000000..d3230234f07b --- /dev/null +++ b/drivers/clk/ti/clk-3xxx.c @@ -0,0 +1,401 @@ +/* + * OMAP3 Clock init + * + * Copyright (C) 2013 Texas Instruments, Inc + * Tero Kristo (t-kristo@ti.com) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include + + +static struct ti_dt_clk omap3xxx_clks[] = { + DT_CLK(NULL, "apb_pclk", "dummy_apb_pclk"), + DT_CLK(NULL, "omap_32k_fck", "omap_32k_fck"), + DT_CLK(NULL, "virt_12m_ck", "virt_12m_ck"), + DT_CLK(NULL, "virt_13m_ck", "virt_13m_ck"), + DT_CLK(NULL, "virt_19200000_ck", "virt_19200000_ck"), + DT_CLK(NULL, "virt_26000000_ck", "virt_26000000_ck"), + DT_CLK(NULL, "virt_38_4m_ck", "virt_38_4m_ck"), + DT_CLK(NULL, "osc_sys_ck", "osc_sys_ck"), + DT_CLK("twl", "fck", "osc_sys_ck"), + DT_CLK(NULL, "sys_ck", "sys_ck"), + DT_CLK(NULL, "omap_96m_alwon_fck", "omap_96m_alwon_fck"), + DT_CLK("etb", "emu_core_alwon_ck", "emu_core_alwon_ck"), + DT_CLK(NULL, "sys_altclk", "sys_altclk"), + DT_CLK(NULL, "mcbsp_clks", "mcbsp_clks"), + DT_CLK(NULL, "sys_clkout1", "sys_clkout1"), + DT_CLK(NULL, "dpll1_ck", "dpll1_ck"), + DT_CLK(NULL, "dpll1_x2_ck", "dpll1_x2_ck"), + DT_CLK(NULL, "dpll1_x2m2_ck", "dpll1_x2m2_ck"), + DT_CLK(NULL, "dpll3_ck", "dpll3_ck"), + DT_CLK(NULL, "core_ck", "core_ck"), + DT_CLK(NULL, "dpll3_x2_ck", "dpll3_x2_ck"), + DT_CLK(NULL, "dpll3_m2_ck", "dpll3_m2_ck"), + DT_CLK(NULL, "dpll3_m2x2_ck", "dpll3_m2x2_ck"), + DT_CLK(NULL, "dpll3_m3_ck", "dpll3_m3_ck"), + DT_CLK(NULL, "dpll3_m3x2_ck", "dpll3_m3x2_ck"), + DT_CLK(NULL, "dpll4_ck", "dpll4_ck"), + DT_CLK(NULL, "dpll4_x2_ck", "dpll4_x2_ck"), + DT_CLK(NULL, "omap_96m_fck", "omap_96m_fck"), + DT_CLK(NULL, "cm_96m_fck", "cm_96m_fck"), + DT_CLK(NULL, "omap_54m_fck", "omap_54m_fck"), + DT_CLK(NULL, "omap_48m_fck", "omap_48m_fck"), + DT_CLK(NULL, "omap_12m_fck", "omap_12m_fck"), + DT_CLK(NULL, "dpll4_m2_ck", "dpll4_m2_ck"), + DT_CLK(NULL, "dpll4_m2x2_ck", "dpll4_m2x2_ck"), + DT_CLK(NULL, "dpll4_m3_ck", "dpll4_m3_ck"), + DT_CLK(NULL, "dpll4_m3x2_ck", "dpll4_m3x2_ck"), + DT_CLK(NULL, "dpll4_m4_ck", "dpll4_m4_ck"), + DT_CLK(NULL, "dpll4_m4x2_ck", "dpll4_m4x2_ck"), + DT_CLK(NULL, "dpll4_m5_ck", "dpll4_m5_ck"), + DT_CLK(NULL, "dpll4_m5x2_ck", "dpll4_m5x2_ck"), + DT_CLK(NULL, "dpll4_m6_ck", "dpll4_m6_ck"), + DT_CLK(NULL, "dpll4_m6x2_ck", "dpll4_m6x2_ck"), + DT_CLK("etb", "emu_per_alwon_ck", "emu_per_alwon_ck"), + DT_CLK(NULL, "clkout2_src_ck", "clkout2_src_ck"), + DT_CLK(NULL, "sys_clkout2", "sys_clkout2"), + DT_CLK(NULL, "corex2_fck", "corex2_fck"), + DT_CLK(NULL, "dpll1_fck", "dpll1_fck"), + DT_CLK(NULL, "mpu_ck", "mpu_ck"), + DT_CLK(NULL, "arm_fck", "arm_fck"), + DT_CLK("etb", "emu_mpu_alwon_ck", "emu_mpu_alwon_ck"), + DT_CLK(NULL, "l3_ick", "l3_ick"), + DT_CLK(NULL, "l4_ick", "l4_ick"), + DT_CLK(NULL, "rm_ick", "rm_ick"), + DT_CLK(NULL, "gpt10_fck", "gpt10_fck"), + DT_CLK(NULL, "gpt11_fck", "gpt11_fck"), + DT_CLK(NULL, "core_96m_fck", "core_96m_fck"), + DT_CLK(NULL, "mmchs2_fck", "mmchs2_fck"), + DT_CLK(NULL, "mmchs1_fck", "mmchs1_fck"), + DT_CLK(NULL, "i2c3_fck", "i2c3_fck"), + DT_CLK(NULL, "i2c2_fck", "i2c2_fck"), + DT_CLK(NULL, "i2c1_fck", "i2c1_fck"), + DT_CLK(NULL, "mcbsp5_fck", "mcbsp5_fck"), + DT_CLK(NULL, "mcbsp1_fck", "mcbsp1_fck"), + DT_CLK(NULL, "core_48m_fck", "core_48m_fck"), + DT_CLK(NULL, "mcspi4_fck", "mcspi4_fck"), + DT_CLK(NULL, "mcspi3_fck", "mcspi3_fck"), + DT_CLK(NULL, "mcspi2_fck", "mcspi2_fck"), + DT_CLK(NULL, "mcspi1_fck", "mcspi1_fck"), + DT_CLK(NULL, "uart2_fck", "uart2_fck"), + DT_CLK(NULL, "uart1_fck", "uart1_fck"), + DT_CLK(NULL, "core_12m_fck", "core_12m_fck"), + DT_CLK("omap_hdq.0", "fck", "hdq_fck"), + DT_CLK(NULL, "hdq_fck", "hdq_fck"), + DT_CLK(NULL, "core_l3_ick", "core_l3_ick"), + DT_CLK(NULL, "sdrc_ick", "sdrc_ick"), + DT_CLK(NULL, "gpmc_fck", "gpmc_fck"), + DT_CLK(NULL, "core_l4_ick", "core_l4_ick"), + DT_CLK("omap_hsmmc.1", "ick", "mmchs2_ick"), + DT_CLK("omap_hsmmc.0", "ick", "mmchs1_ick"), + DT_CLK(NULL, "mmchs2_ick", "mmchs2_ick"), + DT_CLK(NULL, "mmchs1_ick", "mmchs1_ick"), + DT_CLK("omap_hdq.0", "ick", "hdq_ick"), + DT_CLK(NULL, "hdq_ick", "hdq_ick"), + DT_CLK("omap2_mcspi.4", "ick", "mcspi4_ick"), + DT_CLK("omap2_mcspi.3", "ick", "mcspi3_ick"), + DT_CLK("omap2_mcspi.2", "ick", "mcspi2_ick"), + DT_CLK("omap2_mcspi.1", "ick", "mcspi1_ick"), + DT_CLK(NULL, "mcspi4_ick", "mcspi4_ick"), + DT_CLK(NULL, "mcspi3_ick", "mcspi3_ick"), + DT_CLK(NULL, "mcspi2_ick", "mcspi2_ick"), + DT_CLK(NULL, "mcspi1_ick", "mcspi1_ick"), + DT_CLK("omap_i2c.3", "ick", "i2c3_ick"), + DT_CLK("omap_i2c.2", "ick", "i2c2_ick"), + DT_CLK("omap_i2c.1", "ick", "i2c1_ick"), + DT_CLK(NULL, "i2c3_ick", "i2c3_ick"), + DT_CLK(NULL, "i2c2_ick", "i2c2_ick"), + DT_CLK(NULL, "i2c1_ick", "i2c1_ick"), + DT_CLK(NULL, "uart2_ick", "uart2_ick"), + DT_CLK(NULL, "uart1_ick", "uart1_ick"), + DT_CLK(NULL, "gpt11_ick", "gpt11_ick"), + DT_CLK(NULL, "gpt10_ick", "gpt10_ick"), + DT_CLK("omap-mcbsp.5", "ick", "mcbsp5_ick"), + DT_CLK("omap-mcbsp.1", "ick", "mcbsp1_ick"), + DT_CLK(NULL, "mcbsp5_ick", "mcbsp5_ick"), + DT_CLK(NULL, "mcbsp1_ick", "mcbsp1_ick"), + DT_CLK(NULL, "omapctrl_ick", "omapctrl_ick"), + DT_CLK(NULL, "dss_tv_fck", "dss_tv_fck"), + DT_CLK(NULL, "dss_96m_fck", "dss_96m_fck"), + DT_CLK(NULL, "dss2_alwon_fck", "dss2_alwon_fck"), + DT_CLK(NULL, "utmi_p1_gfclk", "dummy_ck"), + DT_CLK(NULL, "utmi_p2_gfclk", "dummy_ck"), + DT_CLK(NULL, "xclk60mhsp1_ck", "dummy_ck"), + DT_CLK(NULL, "xclk60mhsp2_ck", "dummy_ck"), + DT_CLK(NULL, "init_60m_fclk", "dummy_ck"), + DT_CLK(NULL, "gpt1_fck", "gpt1_fck"), + DT_CLK(NULL, "aes2_ick", "aes2_ick"), + DT_CLK(NULL, "wkup_32k_fck", "wkup_32k_fck"), + DT_CLK(NULL, "gpio1_dbck", "gpio1_dbck"), + DT_CLK(NULL, "sha12_ick", "sha12_ick"), + DT_CLK(NULL, "wdt2_fck", "wdt2_fck"), + DT_CLK("omap_wdt", "ick", "wdt2_ick"), + DT_CLK(NULL, "wdt2_ick", "wdt2_ick"), + DT_CLK(NULL, "wdt1_ick", "wdt1_ick"), + DT_CLK(NULL, "gpio1_ick", "gpio1_ick"), + DT_CLK(NULL, "omap_32ksync_ick", "omap_32ksync_ick"), + DT_CLK(NULL, "gpt12_ick", "gpt12_ick"), + DT_CLK(NULL, "gpt1_ick", "gpt1_ick"), + DT_CLK(NULL, "per_96m_fck", "per_96m_fck"), + DT_CLK(NULL, "per_48m_fck", "per_48m_fck"), + DT_CLK(NULL, "uart3_fck", "uart3_fck"), + DT_CLK(NULL, "gpt2_fck", "gpt2_fck"), + DT_CLK(NULL, "gpt3_fck", "gpt3_fck"), + DT_CLK(NULL, "gpt4_fck", "gpt4_fck"), + DT_CLK(NULL, "gpt5_fck", "gpt5_fck"), + DT_CLK(NULL, "gpt6_fck", "gpt6_fck"), + DT_CLK(NULL, "gpt7_fck", "gpt7_fck"), + DT_CLK(NULL, "gpt8_fck", "gpt8_fck"), + DT_CLK(NULL, "gpt9_fck", "gpt9_fck"), + DT_CLK(NULL, "per_32k_alwon_fck", "per_32k_alwon_fck"), + DT_CLK(NULL, "gpio6_dbck", "gpio6_dbck"), + DT_CLK(NULL, "gpio5_dbck", "gpio5_dbck"), + DT_CLK(NULL, "gpio4_dbck", "gpio4_dbck"), + DT_CLK(NULL, "gpio3_dbck", "gpio3_dbck"), + DT_CLK(NULL, "gpio2_dbck", "gpio2_dbck"), + DT_CLK(NULL, "wdt3_fck", "wdt3_fck"), + DT_CLK(NULL, "per_l4_ick", "per_l4_ick"), + DT_CLK(NULL, "gpio6_ick", "gpio6_ick"), + DT_CLK(NULL, "gpio5_ick", "gpio5_ick"), + DT_CLK(NULL, "gpio4_ick", "gpio4_ick"), + DT_CLK(NULL, "gpio3_ick", "gpio3_ick"), + DT_CLK(NULL, "gpio2_ick", "gpio2_ick"), + DT_CLK(NULL, "wdt3_ick", "wdt3_ick"), + DT_CLK(NULL, "uart3_ick", "uart3_ick"), + DT_CLK(NULL, "uart4_ick", "uart4_ick"), + DT_CLK(NULL, "gpt9_ick", "gpt9_ick"), + DT_CLK(NULL, "gpt8_ick", "gpt8_ick"), + DT_CLK(NULL, "gpt7_ick", "gpt7_ick"), + DT_CLK(NULL, "gpt6_ick", "gpt6_ick"), + DT_CLK(NULL, "gpt5_ick", "gpt5_ick"), + DT_CLK(NULL, "gpt4_ick", "gpt4_ick"), + DT_CLK(NULL, "gpt3_ick", "gpt3_ick"), + DT_CLK(NULL, "gpt2_ick", "gpt2_ick"), + DT_CLK("omap-mcbsp.2", "ick", "mcbsp2_ick"), + DT_CLK("omap-mcbsp.3", "ick", "mcbsp3_ick"), + DT_CLK("omap-mcbsp.4", "ick", "mcbsp4_ick"), + DT_CLK(NULL, "mcbsp4_ick", "mcbsp2_ick"), + DT_CLK(NULL, "mcbsp3_ick", "mcbsp3_ick"), + DT_CLK(NULL, "mcbsp2_ick", "mcbsp4_ick"), + DT_CLK(NULL, "mcbsp2_fck", "mcbsp2_fck"), + DT_CLK(NULL, "mcbsp3_fck", "mcbsp3_fck"), + DT_CLK(NULL, "mcbsp4_fck", "mcbsp4_fck"), + DT_CLK("etb", "emu_src_ck", "emu_src_ck"), + DT_CLK(NULL, "emu_src_ck", "emu_src_ck"), + DT_CLK(NULL, "pclk_fck", "pclk_fck"), + DT_CLK(NULL, "pclkx2_fck", "pclkx2_fck"), + DT_CLK(NULL, "atclk_fck", "atclk_fck"), + DT_CLK(NULL, "traceclk_src_fck", "traceclk_src_fck"), + DT_CLK(NULL, "traceclk_fck", "traceclk_fck"), + DT_CLK(NULL, "secure_32k_fck", "secure_32k_fck"), + DT_CLK(NULL, "gpt12_fck", "gpt12_fck"), + DT_CLK(NULL, "wdt1_fck", "wdt1_fck"), + DT_CLK(NULL, "timer_32k_ck", "omap_32k_fck"), + DT_CLK(NULL, "timer_sys_ck", "sys_ck"), + DT_CLK(NULL, "cpufreq_ck", "dpll1_ck"), + { .node_name = NULL }, +}; + +static struct ti_dt_clk omap34xx_omap36xx_clks[] = { + DT_CLK(NULL, "aes1_ick", "aes1_ick"), + DT_CLK("omap_rng", "ick", "rng_ick"), + DT_CLK("omap3-rom-rng", "ick", "rng_ick"), + DT_CLK(NULL, "sha11_ick", "sha11_ick"), + DT_CLK(NULL, "des1_ick", "des1_ick"), + DT_CLK(NULL, "cam_mclk", "cam_mclk"), + DT_CLK(NULL, "cam_ick", "cam_ick"), + DT_CLK(NULL, "csi2_96m_fck", "csi2_96m_fck"), + DT_CLK(NULL, "security_l3_ick", "security_l3_ick"), + DT_CLK(NULL, "pka_ick", "pka_ick"), + DT_CLK(NULL, "icr_ick", "icr_ick"), + DT_CLK("omap-aes", "ick", "aes2_ick"), + DT_CLK("omap-sham", "ick", "sha12_ick"), + DT_CLK(NULL, "des2_ick", "des2_ick"), + DT_CLK(NULL, "mspro_ick", "mspro_ick"), + DT_CLK(NULL, "mailboxes_ick", "mailboxes_ick"), + DT_CLK(NULL, "ssi_l4_ick", "ssi_l4_ick"), + DT_CLK(NULL, "sr1_fck", "sr1_fck"), + DT_CLK(NULL, "sr2_fck", "sr2_fck"), + DT_CLK(NULL, "sr_l4_ick", "sr_l4_ick"), + DT_CLK(NULL, "security_l4_ick2", "security_l4_ick2"), + DT_CLK(NULL, "wkup_l4_ick", "wkup_l4_ick"), + DT_CLK(NULL, "dpll2_fck", "dpll2_fck"), + DT_CLK(NULL, "iva2_ck", "iva2_ck"), + DT_CLK(NULL, "modem_fck", "modem_fck"), + DT_CLK(NULL, "sad2d_ick", "sad2d_ick"), + DT_CLK(NULL, "mad2d_ick", "mad2d_ick"), + DT_CLK(NULL, "mspro_fck", "mspro_fck"), + DT_CLK(NULL, "dpll2_ck", "dpll2_ck"), + DT_CLK(NULL, "dpll2_m2_ck", "dpll2_m2_ck"), + { .node_name = NULL }, +}; + +static struct ti_dt_clk omap36xx_omap3430es2plus_clks[] = { + DT_CLK(NULL, "ssi_ssr_fck", "ssi_ssr_fck_3430es2"), + DT_CLK(NULL, "ssi_sst_fck", "ssi_sst_fck_3430es2"), + DT_CLK("musb-omap2430", "ick", "hsotgusb_ick_3430es2"), + DT_CLK(NULL, "hsotgusb_ick", "hsotgusb_ick_3430es2"), + DT_CLK(NULL, "ssi_ick", "ssi_ick_3430es2"), + DT_CLK(NULL, "usim_fck", "usim_fck"), + DT_CLK(NULL, "usim_ick", "usim_ick"), + { .node_name = NULL }, +}; + +static struct ti_dt_clk omap3430es1_clks[] = { + DT_CLK(NULL, "gfx_l3_ck", "gfx_l3_ck"), + DT_CLK(NULL, "gfx_l3_fck", "gfx_l3_fck"), + DT_CLK(NULL, "gfx_l3_ick", "gfx_l3_ick"), + DT_CLK(NULL, "gfx_cg1_ck", "gfx_cg1_ck"), + DT_CLK(NULL, "gfx_cg2_ck", "gfx_cg2_ck"), + DT_CLK(NULL, "d2d_26m_fck", "d2d_26m_fck"), + DT_CLK(NULL, "fshostusb_fck", "fshostusb_fck"), + DT_CLK(NULL, "ssi_ssr_fck", "ssi_ssr_fck_3430es1"), + DT_CLK(NULL, "ssi_sst_fck", "ssi_sst_fck_3430es1"), + DT_CLK("musb-omap2430", "ick", "hsotgusb_ick_3430es1"), + DT_CLK(NULL, "hsotgusb_ick", "hsotgusb_ick_3430es1"), + DT_CLK(NULL, "fac_ick", "fac_ick"), + DT_CLK(NULL, "ssi_ick", "ssi_ick_3430es1"), + DT_CLK(NULL, "usb_l4_ick", "usb_l4_ick"), + DT_CLK(NULL, "dss1_alwon_fck", "dss1_alwon_fck_3430es1"), + DT_CLK("omapdss_dss", "ick", "dss_ick_3430es1"), + DT_CLK(NULL, "dss_ick", "dss_ick_3430es1"), + { .node_name = NULL }, +}; + +static struct ti_dt_clk omap36xx_am35xx_omap3430es2plus_clks[] = { + DT_CLK(NULL, "virt_16_8m_ck", "virt_16_8m_ck"), + DT_CLK(NULL, "dpll5_ck", "dpll5_ck"), + DT_CLK(NULL, "dpll5_m2_ck", "dpll5_m2_ck"), + DT_CLK(NULL, "sgx_fck", "sgx_fck"), + DT_CLK(NULL, "sgx_ick", "sgx_ick"), + DT_CLK(NULL, "cpefuse_fck", "cpefuse_fck"), + DT_CLK(NULL, "ts_fck", "ts_fck"), + DT_CLK(NULL, "usbtll_fck", "usbtll_fck"), + DT_CLK(NULL, "usbtll_ick", "usbtll_ick"), + DT_CLK("omap_hsmmc.2", "ick", "mmchs3_ick"), + DT_CLK(NULL, "mmchs3_ick", "mmchs3_ick"), + DT_CLK(NULL, "mmchs3_fck", "mmchs3_fck"), + DT_CLK(NULL, "dss1_alwon_fck", "dss1_alwon_fck_3430es2"), + DT_CLK("omapdss_dss", "ick", "dss_ick_3430es2"), + DT_CLK(NULL, "dss_ick", "dss_ick_3430es2"), + DT_CLK(NULL, "usbhost_120m_fck", "usbhost_120m_fck"), + DT_CLK(NULL, "usbhost_48m_fck", "usbhost_48m_fck"), + DT_CLK(NULL, "usbhost_ick", "usbhost_ick"), + { .node_name = NULL }, +}; + +static struct ti_dt_clk am35xx_clks[] = { + DT_CLK(NULL, "ipss_ick", "ipss_ick"), + DT_CLK(NULL, "rmii_ck", "rmii_ck"), + DT_CLK(NULL, "pclk_ck", "pclk_ck"), + DT_CLK(NULL, "emac_ick", "emac_ick"), + DT_CLK(NULL, "emac_fck", "emac_fck"), + DT_CLK("davinci_emac.0", NULL, "emac_ick"), + DT_CLK("davinci_mdio.0", NULL, "emac_fck"), + DT_CLK("vpfe-capture", "master", "vpfe_ick"), + DT_CLK("vpfe-capture", "slave", "vpfe_fck"), + DT_CLK(NULL, "hsotgusb_ick", "hsotgusb_ick_am35xx"), + DT_CLK(NULL, "hsotgusb_fck", "hsotgusb_fck_am35xx"), + DT_CLK(NULL, "hecc_ck", "hecc_ck"), + DT_CLK(NULL, "uart4_ick", "uart4_ick_am35xx"), + DT_CLK(NULL, "uart4_fck", "uart4_fck_am35xx"), + { .node_name = NULL }, +}; + +static struct ti_dt_clk omap36xx_clks[] = { + DT_CLK(NULL, "omap_192m_alwon_fck", "omap_192m_alwon_fck"), + DT_CLK(NULL, "uart4_fck", "uart4_fck"), + { .node_name = NULL }, +}; + +static const char *enable_init_clks[] = { + "sdrc_ick", + "gpmc_fck", + "omapctrl_ick", +}; + +enum { + OMAP3_SOC_AM35XX, + OMAP3_SOC_OMAP3430_ES1, + OMAP3_SOC_OMAP3430_ES2_PLUS, + OMAP3_SOC_OMAP3630, + OMAP3_SOC_TI81XX, +}; + +static int __init omap3xxx_dt_clk_init(int soc_type) +{ + if (soc_type == OMAP3_SOC_AM35XX || soc_type == OMAP3_SOC_OMAP3630 || + soc_type == OMAP3_SOC_OMAP3430_ES1 || + soc_type == OMAP3_SOC_OMAP3430_ES2_PLUS) + ti_dt_clocks_register(omap3xxx_clks); + + if (soc_type == OMAP3_SOC_AM35XX) + ti_dt_clocks_register(am35xx_clks); + + if (soc_type == OMAP3_SOC_OMAP3630 || soc_type == OMAP3_SOC_AM35XX || + soc_type == OMAP3_SOC_OMAP3430_ES2_PLUS) + ti_dt_clocks_register(omap36xx_am35xx_omap3430es2plus_clks); + + if (soc_type == OMAP3_SOC_OMAP3430_ES1) + ti_dt_clocks_register(omap3430es1_clks); + + if (soc_type == OMAP3_SOC_OMAP3430_ES2_PLUS || + soc_type == OMAP3_SOC_OMAP3630) + ti_dt_clocks_register(omap36xx_omap3430es2plus_clks); + + if (soc_type == OMAP3_SOC_OMAP3430_ES1 || + soc_type == OMAP3_SOC_OMAP3430_ES2_PLUS || + soc_type == OMAP3_SOC_OMAP3630) + ti_dt_clocks_register(omap34xx_omap36xx_clks); + + if (soc_type == OMAP3_SOC_OMAP3630) + ti_dt_clocks_register(omap36xx_clks); + + omap2_clk_disable_autoidle_all(); + + omap2_clk_enable_init_clocks(enable_init_clks, + ARRAY_SIZE(enable_init_clks)); + + pr_info("Clocking rate (Crystal/Core/MPU): %ld.%01ld/%ld/%ld MHz\n", + (clk_get_rate(clk_get_sys(NULL, "osc_sys_ck")) / 1000000), + (clk_get_rate(clk_get_sys(NULL, "osc_sys_ck")) / 100000) % 10, + (clk_get_rate(clk_get_sys(NULL, "core_ck")) / 1000000), + (clk_get_rate(clk_get_sys(NULL, "arm_fck")) / 1000000)); + + if (soc_type != OMAP3_SOC_TI81XX && soc_type != OMAP3_SOC_OMAP3430_ES1) + omap3_clk_lock_dpll5(); + + return 0; +} + +int __init omap3430_dt_clk_init(void) +{ + return omap3xxx_dt_clk_init(OMAP3_SOC_OMAP3430_ES2_PLUS); +} + +int __init omap3630_dt_clk_init(void) +{ + return omap3xxx_dt_clk_init(OMAP3_SOC_OMAP3630); +} + +int __init am35xx_dt_clk_init(void) +{ + return omap3xxx_dt_clk_init(OMAP3_SOC_AM35XX); +} + +int __init ti81xx_dt_clk_init(void) +{ + return omap3xxx_dt_clk_init(OMAP3_SOC_TI81XX); +} diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h index 17c034ea03ad..3d2ba57446cd 100644 --- a/include/linux/clk/ti.h +++ b/include/linux/clk/ti.h @@ -254,6 +254,7 @@ int omap3_dpll4_set_rate(struct clk_hw *clk, unsigned long rate, int omap2_dflt_clk_enable(struct clk_hw *hw); void omap2_dflt_clk_disable(struct clk_hw *hw); int omap2_dflt_clk_is_enabled(struct clk_hw *hw); +void omap3_clk_lock_dpll5(void); void __iomem *ti_clk_get_reg_addr(struct device_node *node, int index); void ti_dt_clocks_register(struct ti_dt_clk *oclks); @@ -264,6 +265,10 @@ int ti_clk_retry_init(struct device_node *node, struct clk_hw *hw, int of_ti_clk_autoidle_setup(struct device_node *node); int ti_clk_add_component(struct device_node *node, struct clk_hw *hw, int type); +int omap3430_dt_clk_init(void); +int omap3630_dt_clk_init(void); +int am35xx_dt_clk_init(void); +int ti81xx_dt_clk_init(void); int omap4xxx_dt_clk_init(void); int omap5xxx_dt_clk_init(void); int dra7xx_dt_clk_init(void); -- cgit v1.2.3-59-g8ed1b From ffab239956613be7b81d00999128fd05fd096762 Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Fri, 20 Sep 2013 17:02:40 +0300 Subject: CLK: TI: add am43xx clock init file clk-43xx.c now contains the clock init functionality for am43xx, including DT clock registration and adding of static clkdev entries. Signed-off-by: Tero Kristo Tested-by: Nishanth Menon Acked-by: Tony Lindgren Signed-off-by: Mike Turquette --- drivers/clk/ti/Makefile | 1 + drivers/clk/ti/clk-43xx.c | 118 ++++++++++++++++++++++++++++++++++++++++++++++ include/linux/clk/ti.h | 1 + 3 files changed, 120 insertions(+) create mode 100644 drivers/clk/ti/clk-43xx.c diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile index 99ead078b109..4319d4031aa3 100644 --- a/drivers/clk/ti/Makefile +++ b/drivers/clk/ti/Makefile @@ -7,4 +7,5 @@ obj-$(CONFIG_ARCH_OMAP3) += $(clk-common) interface.o clk-3xxx.o obj-$(CONFIG_ARCH_OMAP4) += $(clk-common) clk-44xx.o obj-$(CONFIG_SOC_OMAP5) += $(clk-common) clk-54xx.o obj-$(CONFIG_SOC_DRA7XX) += $(clk-common) clk-7xx.o +obj-$(CONFIG_SOC_AM43XX) += $(clk-common) clk-43xx.o endif diff --git a/drivers/clk/ti/clk-43xx.c b/drivers/clk/ti/clk-43xx.c new file mode 100644 index 000000000000..67c8de572c50 --- /dev/null +++ b/drivers/clk/ti/clk-43xx.c @@ -0,0 +1,118 @@ +/* + * AM43XX Clock init + * + * Copyright (C) 2013 Texas Instruments, Inc + * Tero Kristo (t-kristo@ti.com) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include + +static struct ti_dt_clk am43xx_clks[] = { + DT_CLK(NULL, "clk_32768_ck", "clk_32768_ck"), + DT_CLK(NULL, "clk_rc32k_ck", "clk_rc32k_ck"), + DT_CLK(NULL, "virt_19200000_ck", "virt_19200000_ck"), + DT_CLK(NULL, "virt_24000000_ck", "virt_24000000_ck"), + DT_CLK(NULL, "virt_25000000_ck", "virt_25000000_ck"), + DT_CLK(NULL, "virt_26000000_ck", "virt_26000000_ck"), + DT_CLK(NULL, "sys_clkin_ck", "sys_clkin_ck"), + DT_CLK(NULL, "tclkin_ck", "tclkin_ck"), + DT_CLK(NULL, "dpll_core_ck", "dpll_core_ck"), + DT_CLK(NULL, "dpll_core_x2_ck", "dpll_core_x2_ck"), + DT_CLK(NULL, "dpll_core_m4_ck", "dpll_core_m4_ck"), + DT_CLK(NULL, "dpll_core_m5_ck", "dpll_core_m5_ck"), + DT_CLK(NULL, "dpll_core_m6_ck", "dpll_core_m6_ck"), + DT_CLK(NULL, "dpll_mpu_ck", "dpll_mpu_ck"), + DT_CLK(NULL, "dpll_mpu_m2_ck", "dpll_mpu_m2_ck"), + DT_CLK(NULL, "dpll_ddr_ck", "dpll_ddr_ck"), + DT_CLK(NULL, "dpll_ddr_m2_ck", "dpll_ddr_m2_ck"), + DT_CLK(NULL, "dpll_disp_ck", "dpll_disp_ck"), + DT_CLK(NULL, "dpll_disp_m2_ck", "dpll_disp_m2_ck"), + DT_CLK(NULL, "dpll_per_ck", "dpll_per_ck"), + DT_CLK(NULL, "dpll_per_m2_ck", "dpll_per_m2_ck"), + DT_CLK(NULL, "dpll_per_m2_div4_wkupdm_ck", "dpll_per_m2_div4_wkupdm_ck"), + DT_CLK(NULL, "dpll_per_m2_div4_ck", "dpll_per_m2_div4_ck"), + DT_CLK(NULL, "adc_tsc_fck", "adc_tsc_fck"), + DT_CLK(NULL, "clkdiv32k_ck", "clkdiv32k_ck"), + DT_CLK(NULL, "clkdiv32k_ick", "clkdiv32k_ick"), + DT_CLK(NULL, "dcan0_fck", "dcan0_fck"), + DT_CLK(NULL, "dcan1_fck", "dcan1_fck"), + DT_CLK(NULL, "pruss_ocp_gclk", "pruss_ocp_gclk"), + DT_CLK(NULL, "mcasp0_fck", "mcasp0_fck"), + DT_CLK(NULL, "mcasp1_fck", "mcasp1_fck"), + DT_CLK(NULL, "smartreflex0_fck", "smartreflex0_fck"), + DT_CLK(NULL, "smartreflex1_fck", "smartreflex1_fck"), + DT_CLK(NULL, "sha0_fck", "sha0_fck"), + DT_CLK(NULL, "aes0_fck", "aes0_fck"), + DT_CLK(NULL, "timer1_fck", "timer1_fck"), + DT_CLK(NULL, "timer2_fck", "timer2_fck"), + DT_CLK(NULL, "timer3_fck", "timer3_fck"), + DT_CLK(NULL, "timer4_fck", "timer4_fck"), + DT_CLK(NULL, "timer5_fck", "timer5_fck"), + DT_CLK(NULL, "timer6_fck", "timer6_fck"), + DT_CLK(NULL, "timer7_fck", "timer7_fck"), + DT_CLK(NULL, "wdt1_fck", "wdt1_fck"), + DT_CLK(NULL, "l3_gclk", "l3_gclk"), + DT_CLK(NULL, "dpll_core_m4_div2_ck", "dpll_core_m4_div2_ck"), + DT_CLK(NULL, "l4hs_gclk", "l4hs_gclk"), + DT_CLK(NULL, "l3s_gclk", "l3s_gclk"), + DT_CLK(NULL, "l4ls_gclk", "l4ls_gclk"), + DT_CLK(NULL, "clk_24mhz", "clk_24mhz"), + DT_CLK(NULL, "cpsw_125mhz_gclk", "cpsw_125mhz_gclk"), + DT_CLK(NULL, "cpsw_cpts_rft_clk", "cpsw_cpts_rft_clk"), + DT_CLK(NULL, "gpio0_dbclk_mux_ck", "gpio0_dbclk_mux_ck"), + DT_CLK(NULL, "gpio0_dbclk", "gpio0_dbclk"), + DT_CLK(NULL, "gpio1_dbclk", "gpio1_dbclk"), + DT_CLK(NULL, "gpio2_dbclk", "gpio2_dbclk"), + DT_CLK(NULL, "gpio3_dbclk", "gpio3_dbclk"), + DT_CLK(NULL, "gpio4_dbclk", "gpio4_dbclk"), + DT_CLK(NULL, "gpio5_dbclk", "gpio5_dbclk"), + DT_CLK(NULL, "mmc_clk", "mmc_clk"), + DT_CLK(NULL, "gfx_fclk_clksel_ck", "gfx_fclk_clksel_ck"), + DT_CLK(NULL, "gfx_fck_div_ck", "gfx_fck_div_ck"), + DT_CLK(NULL, "timer_32k_ck", "clkdiv32k_ick"), + DT_CLK(NULL, "timer_sys_ck", "sys_clkin_ck"), + DT_CLK(NULL, "sysclk_div", "sysclk_div"), + DT_CLK(NULL, "disp_clk", "disp_clk"), + DT_CLK(NULL, "clk_32k_mosc_ck", "clk_32k_mosc_ck"), + DT_CLK(NULL, "clk_32k_tpm_ck", "clk_32k_tpm_ck"), + DT_CLK(NULL, "dpll_extdev_ck", "dpll_extdev_ck"), + DT_CLK(NULL, "dpll_extdev_m2_ck", "dpll_extdev_m2_ck"), + DT_CLK(NULL, "mux_synctimer32k_ck", "mux_synctimer32k_ck"), + DT_CLK(NULL, "synctimer_32kclk", "synctimer_32kclk"), + DT_CLK(NULL, "timer8_fck", "timer8_fck"), + DT_CLK(NULL, "timer9_fck", "timer9_fck"), + DT_CLK(NULL, "timer10_fck", "timer10_fck"), + DT_CLK(NULL, "timer11_fck", "timer11_fck"), + DT_CLK(NULL, "cpsw_50m_clkdiv", "cpsw_50m_clkdiv"), + DT_CLK(NULL, "cpsw_5m_clkdiv", "cpsw_5m_clkdiv"), + DT_CLK(NULL, "dpll_ddr_x2_ck", "dpll_ddr_x2_ck"), + DT_CLK(NULL, "dpll_ddr_m4_ck", "dpll_ddr_m4_ck"), + DT_CLK(NULL, "dpll_per_clkdcoldo", "dpll_per_clkdcoldo"), + DT_CLK(NULL, "dll_aging_clk_div", "dll_aging_clk_div"), + DT_CLK(NULL, "div_core_25m_ck", "div_core_25m_ck"), + DT_CLK(NULL, "func_12m_clk", "func_12m_clk"), + DT_CLK(NULL, "vtp_clk_div", "vtp_clk_div"), + DT_CLK(NULL, "usbphy_32khz_clkmux", "usbphy_32khz_clkmux"), + { .node_name = NULL }, +}; + +int __init am43xx_dt_clk_init(void) +{ + ti_dt_clocks_register(am43xx_clks); + + omap2_clk_disable_autoidle_all(); + + return 0; +} diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h index 3d2ba57446cd..092b64168d7f 100644 --- a/include/linux/clk/ti.h +++ b/include/linux/clk/ti.h @@ -273,6 +273,7 @@ int omap4xxx_dt_clk_init(void); int omap5xxx_dt_clk_init(void); int dra7xx_dt_clk_init(void); int am33xx_dt_clk_init(void); +int am43xx_dt_clk_init(void); #ifdef CONFIG_OF void of_ti_clk_allow_autoidle_all(void); -- cgit v1.2.3-59-g8ed1b From 2488ff6cfcedc26b635eddf5a2997352da0098f8 Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Thu, 18 Jul 2013 12:42:02 +0300 Subject: ARM: dts: omap4 clock data This patch creates a unique node for each clock in the OMAP4 power, reset and clock manager (PRCM). OMAP443x and OMAP446x have slightly different clock tree which is taken into account in the data. Signed-off-by: Tero Kristo Acked-by: Tony Lindgren Signed-off-by: Mike Turquette --- arch/arm/boot/dts/omap4.dtsi | 54 ++ arch/arm/boot/dts/omap443x-clocks.dtsi | 18 + arch/arm/boot/dts/omap443x.dtsi | 2 + arch/arm/boot/dts/omap4460.dtsi | 2 + arch/arm/boot/dts/omap446x-clocks.dtsi | 27 + arch/arm/boot/dts/omap44xx-clocks.dtsi | 1651 ++++++++++++++++++++++++++++++++ 6 files changed, 1754 insertions(+) create mode 100644 arch/arm/boot/dts/omap443x-clocks.dtsi create mode 100644 arch/arm/boot/dts/omap446x-clocks.dtsi create mode 100644 arch/arm/boot/dts/omap44xx-clocks.dtsi diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi index a1e05853afcd..d3f8a6e8ca20 100644 --- a/arch/arm/boot/dts/omap4.dtsi +++ b/arch/arm/boot/dts/omap4.dtsi @@ -107,6 +107,58 @@ interrupts = , ; + cm1: cm1@4a004000 { + compatible = "ti,omap4-cm1"; + reg = <0x4a004000 0x2000>; + + cm1_clocks: clocks { + #address-cells = <1>; + #size-cells = <0>; + }; + + cm1_clockdomains: clockdomains { + }; + }; + + prm: prm@4a306000 { + compatible = "ti,omap4-prm"; + reg = <0x4a306000 0x3000>; + + prm_clocks: clocks { + #address-cells = <1>; + #size-cells = <0>; + }; + + prm_clockdomains: clockdomains { + }; + }; + + cm2: cm2@4a008000 { + compatible = "ti,omap4-cm2"; + reg = <0x4a008000 0x3000>; + + cm2_clocks: clocks { + #address-cells = <1>; + #size-cells = <0>; + }; + + cm2_clockdomains: clockdomains { + }; + }; + + scrm: scrm@4a30a000 { + compatible = "ti,omap4-scrm"; + reg = <0x4a30a000 0x2000>; + + scrm_clocks: clocks { + #address-cells = <1>; + #size-cells = <0>; + }; + + scrm_clockdomains: clockdomains { + }; + }; + counter32k: counter@4a304000 { compatible = "ti,omap-counter32k"; reg = <0x4a304000 0x20>; @@ -707,3 +759,5 @@ }; }; }; + +/include/ "omap44xx-clocks.dtsi" diff --git a/arch/arm/boot/dts/omap443x-clocks.dtsi b/arch/arm/boot/dts/omap443x-clocks.dtsi new file mode 100644 index 000000000000..2bd2166f88d3 --- /dev/null +++ b/arch/arm/boot/dts/omap443x-clocks.dtsi @@ -0,0 +1,18 @@ +/* + * Device Tree Source for OMAP4 clock data + * + * Copyright (C) 2013 Texas Instruments, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +&prm_clocks { + bandgap_fclk: bandgap_fclk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&sys_32k_ck>; + ti,bit-shift = <8>; + reg = <0x1888>; + }; +}; diff --git a/arch/arm/boot/dts/omap443x.dtsi b/arch/arm/boot/dts/omap443x.dtsi index bcf455efe18d..f67e191c1e74 100644 --- a/arch/arm/boot/dts/omap443x.dtsi +++ b/arch/arm/boot/dts/omap443x.dtsi @@ -31,3 +31,5 @@ compatible = "ti,omap4430-bandgap"; }; }; + +/include/ "omap443x-clocks.dtsi" diff --git a/arch/arm/boot/dts/omap4460.dtsi b/arch/arm/boot/dts/omap4460.dtsi index c2f0f39b5a24..1758601b96b4 100644 --- a/arch/arm/boot/dts/omap4460.dtsi +++ b/arch/arm/boot/dts/omap4460.dtsi @@ -39,3 +39,5 @@ gpios = <&gpio3 22 0>; /* tshut */ }; }; + +/include/ "omap446x-clocks.dtsi" diff --git a/arch/arm/boot/dts/omap446x-clocks.dtsi b/arch/arm/boot/dts/omap446x-clocks.dtsi new file mode 100644 index 000000000000..be033e9803e9 --- /dev/null +++ b/arch/arm/boot/dts/omap446x-clocks.dtsi @@ -0,0 +1,27 @@ +/* + * Device Tree Source for OMAP4 clock data + * + * Copyright (C) 2013 Texas Instruments, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +&prm_clocks { + div_ts_ck: div_ts_ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&l4_wkup_clk_mux_ck>; + ti,bit-shift = <24>; + reg = <0x1888>; + ti,dividers = <8>, <16>, <32>; + }; + + bandgap_ts_fclk: bandgap_ts_fclk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&div_ts_ck>; + ti,bit-shift = <8>; + reg = <0x1888>; + }; +}; diff --git a/arch/arm/boot/dts/omap44xx-clocks.dtsi b/arch/arm/boot/dts/omap44xx-clocks.dtsi new file mode 100644 index 000000000000..c821ff5e9b8d --- /dev/null +++ b/arch/arm/boot/dts/omap44xx-clocks.dtsi @@ -0,0 +1,1651 @@ +/* + * Device Tree Source for OMAP4 clock data + * + * Copyright (C) 2013 Texas Instruments, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +&cm1_clocks { + extalt_clkin_ck: extalt_clkin_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <59000000>; + }; + + pad_clks_src_ck: pad_clks_src_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <12000000>; + }; + + pad_clks_ck: pad_clks_ck { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&pad_clks_src_ck>; + ti,bit-shift = <8>; + reg = <0x0108>; + }; + + pad_slimbus_core_clks_ck: pad_slimbus_core_clks_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <12000000>; + }; + + secure_32k_clk_src_ck: secure_32k_clk_src_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + }; + + slimbus_src_clk: slimbus_src_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <12000000>; + }; + + slimbus_clk: slimbus_clk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&slimbus_src_clk>; + ti,bit-shift = <10>; + reg = <0x0108>; + }; + + sys_32k_ck: sys_32k_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + }; + + virt_12000000_ck: virt_12000000_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <12000000>; + }; + + virt_13000000_ck: virt_13000000_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <13000000>; + }; + + virt_16800000_ck: virt_16800000_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <16800000>; + }; + + virt_19200000_ck: virt_19200000_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <19200000>; + }; + + virt_26000000_ck: virt_26000000_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <26000000>; + }; + + virt_27000000_ck: virt_27000000_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <27000000>; + }; + + virt_38400000_ck: virt_38400000_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <38400000>; + }; + + tie_low_clock_ck: tie_low_clock_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0>; + }; + + utmi_phy_clkout_ck: utmi_phy_clkout_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <60000000>; + }; + + xclk60mhsp1_ck: xclk60mhsp1_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <60000000>; + }; + + xclk60mhsp2_ck: xclk60mhsp2_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <60000000>; + }; + + xclk60motg_ck: xclk60motg_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <60000000>; + }; + + dpll_abe_ck: dpll_abe_ck { + #clock-cells = <0>; + compatible = "ti,omap4-dpll-m4xen-clock"; + clocks = <&abe_dpll_refclk_mux_ck>, <&abe_dpll_bypass_clk_mux_ck>; + reg = <0x01e0>, <0x01e4>, <0x01ec>, <0x01e8>; + }; + + dpll_abe_x2_ck: dpll_abe_x2_ck { + #clock-cells = <0>; + compatible = "ti,omap4-dpll-x2-clock"; + clocks = <&dpll_abe_ck>; + reg = <0x01f0>; + }; + + dpll_abe_m2x2_ck: dpll_abe_m2x2_ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll_abe_x2_ck>; + ti,max-div = <31>; + ti,autoidle-shift = <8>; + reg = <0x01f0>; + ti,index-starts-at-one; + ti,invert-autoidle-bit; + }; + + abe_24m_fclk: abe_24m_fclk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll_abe_m2x2_ck>; + clock-mult = <1>; + clock-div = <8>; + }; + + abe_clk: abe_clk { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll_abe_m2x2_ck>; + ti,max-div = <4>; + reg = <0x0108>; + ti,index-power-of-two; + }; + + aess_fclk: aess_fclk { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&abe_clk>; + ti,bit-shift = <24>; + ti,max-div = <2>; + reg = <0x0528>; + }; + + dpll_abe_m3x2_ck: dpll_abe_m3x2_ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll_abe_x2_ck>; + ti,max-div = <31>; + ti,autoidle-shift = <8>; + reg = <0x01f4>; + ti,index-starts-at-one; + ti,invert-autoidle-bit; + }; + + core_hsd_byp_clk_mux_ck: core_hsd_byp_clk_mux_ck { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&sys_clkin_ck>, <&dpll_abe_m3x2_ck>; + ti,bit-shift = <23>; + reg = <0x012c>; + }; + + dpll_core_ck: dpll_core_ck { + #clock-cells = <0>; + compatible = "ti,omap4-dpll-core-clock"; + clocks = <&sys_clkin_ck>, <&core_hsd_byp_clk_mux_ck>; + reg = <0x0120>, <0x0124>, <0x012c>, <0x0128>; + }; + + dpll_core_x2_ck: dpll_core_x2_ck { + #clock-cells = <0>; + compatible = "ti,omap4-dpll-x2-clock"; + clocks = <&dpll_core_ck>; + }; + + dpll_core_m6x2_ck: dpll_core_m6x2_ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll_core_x2_ck>; + ti,max-div = <31>; + ti,autoidle-shift = <8>; + reg = <0x0140>; + ti,index-starts-at-one; + ti,invert-autoidle-bit; + }; + + dpll_core_m2_ck: dpll_core_m2_ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll_core_ck>; + ti,max-div = <31>; + ti,autoidle-shift = <8>; + reg = <0x0130>; + ti,index-starts-at-one; + ti,invert-autoidle-bit; + }; + + ddrphy_ck: ddrphy_ck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll_core_m2_ck>; + clock-mult = <1>; + clock-div = <2>; + }; + + dpll_core_m5x2_ck: dpll_core_m5x2_ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll_core_x2_ck>; + ti,max-div = <31>; + ti,autoidle-shift = <8>; + reg = <0x013c>; + ti,index-starts-at-one; + ti,invert-autoidle-bit; + }; + + div_core_ck: div_core_ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll_core_m5x2_ck>; + reg = <0x0100>; + ti,max-div = <2>; + }; + + div_iva_hs_clk: div_iva_hs_clk { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll_core_m5x2_ck>; + ti,max-div = <4>; + reg = <0x01dc>; + ti,index-power-of-two; + }; + + div_mpu_hs_clk: div_mpu_hs_clk { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll_core_m5x2_ck>; + ti,max-div = <4>; + reg = <0x019c>; + ti,index-power-of-two; + }; + + dpll_core_m4x2_ck: dpll_core_m4x2_ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll_core_x2_ck>; + ti,max-div = <31>; + ti,autoidle-shift = <8>; + reg = <0x0138>; + ti,index-starts-at-one; + ti,invert-autoidle-bit; + }; + + dll_clk_div_ck: dll_clk_div_ck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll_core_m4x2_ck>; + clock-mult = <1>; + clock-div = <2>; + }; + + dpll_abe_m2_ck: dpll_abe_m2_ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll_abe_ck>; + ti,max-div = <31>; + reg = <0x01f0>; + ti,index-starts-at-one; + }; + + dpll_core_m3x2_gate_ck: dpll_core_m3x2_gate_ck { + #clock-cells = <0>; + compatible = "ti,composite-no-wait-gate-clock"; + clocks = <&dpll_core_x2_ck>; + ti,bit-shift = <8>; + reg = <0x0134>; + }; + + dpll_core_m3x2_div_ck: dpll_core_m3x2_div_ck { + #clock-cells = <0>; + compatible = "ti,composite-divider-clock"; + clocks = <&dpll_core_x2_ck>; + ti,max-div = <31>; + reg = <0x0134>; + ti,index-starts-at-one; + }; + + dpll_core_m3x2_ck: dpll_core_m3x2_ck { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&dpll_core_m3x2_gate_ck>, <&dpll_core_m3x2_div_ck>; + }; + + dpll_core_m7x2_ck: dpll_core_m7x2_ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll_core_x2_ck>; + ti,max-div = <31>; + ti,autoidle-shift = <8>; + reg = <0x0144>; + ti,index-starts-at-one; + ti,invert-autoidle-bit; + }; + + iva_hsd_byp_clk_mux_ck: iva_hsd_byp_clk_mux_ck { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&sys_clkin_ck>, <&div_iva_hs_clk>; + ti,bit-shift = <23>; + reg = <0x01ac>; + }; + + dpll_iva_ck: dpll_iva_ck { + #clock-cells = <0>; + compatible = "ti,omap4-dpll-clock"; + clocks = <&sys_clkin_ck>, <&iva_hsd_byp_clk_mux_ck>; + reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>; + }; + + dpll_iva_x2_ck: dpll_iva_x2_ck { + #clock-cells = <0>; + compatible = "ti,omap4-dpll-x2-clock"; + clocks = <&dpll_iva_ck>; + }; + + dpll_iva_m4x2_ck: dpll_iva_m4x2_ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll_iva_x2_ck>; + ti,max-div = <31>; + ti,autoidle-shift = <8>; + reg = <0x01b8>; + ti,index-starts-at-one; + ti,invert-autoidle-bit; + }; + + dpll_iva_m5x2_ck: dpll_iva_m5x2_ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll_iva_x2_ck>; + ti,max-div = <31>; + ti,autoidle-shift = <8>; + reg = <0x01bc>; + ti,index-starts-at-one; + ti,invert-autoidle-bit; + }; + + dpll_mpu_ck: dpll_mpu_ck { + #clock-cells = <0>; + compatible = "ti,omap4-dpll-clock"; + clocks = <&sys_clkin_ck>, <&div_mpu_hs_clk>; + reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>; + }; + + dpll_mpu_m2_ck: dpll_mpu_m2_ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll_mpu_ck>; + ti,max-div = <31>; + ti,autoidle-shift = <8>; + reg = <0x0170>; + ti,index-starts-at-one; + ti,invert-autoidle-bit; + }; + + per_hs_clk_div_ck: per_hs_clk_div_ck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll_abe_m3x2_ck>; + clock-mult = <1>; + clock-div = <2>; + }; + + usb_hs_clk_div_ck: usb_hs_clk_div_ck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll_abe_m3x2_ck>; + clock-mult = <1>; + clock-div = <3>; + }; + + l3_div_ck: l3_div_ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&div_core_ck>; + ti,bit-shift = <4>; + ti,max-div = <2>; + reg = <0x0100>; + }; + + l4_div_ck: l4_div_ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&l3_div_ck>; + ti,bit-shift = <8>; + ti,max-div = <2>; + reg = <0x0100>; + }; + + lp_clk_div_ck: lp_clk_div_ck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll_abe_m2x2_ck>; + clock-mult = <1>; + clock-div = <16>; + }; + + mpu_periphclk: mpu_periphclk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll_mpu_ck>; + clock-mult = <1>; + clock-div = <2>; + }; + + ocp_abe_iclk: ocp_abe_iclk { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&aess_fclk>; + ti,bit-shift = <24>; + reg = <0x0528>; + ti,dividers = <2>, <1>; + }; + + per_abe_24m_fclk: per_abe_24m_fclk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll_abe_m2_ck>; + clock-mult = <1>; + clock-div = <4>; + }; + + dmic_sync_mux_ck: dmic_sync_mux_ck { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&abe_24m_fclk>, <&syc_clk_div_ck>, <&func_24m_clk>; + ti,bit-shift = <25>; + reg = <0x0538>; + }; + + func_dmic_abe_gfclk: func_dmic_abe_gfclk { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&dmic_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>; + ti,bit-shift = <24>; + reg = <0x0538>; + }; + + mcasp_sync_mux_ck: mcasp_sync_mux_ck { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&abe_24m_fclk>, <&syc_clk_div_ck>, <&func_24m_clk>; + ti,bit-shift = <25>; + reg = <0x0540>; + }; + + func_mcasp_abe_gfclk: func_mcasp_abe_gfclk { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&mcasp_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>; + ti,bit-shift = <24>; + reg = <0x0540>; + }; + + mcbsp1_sync_mux_ck: mcbsp1_sync_mux_ck { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&abe_24m_fclk>, <&syc_clk_div_ck>, <&func_24m_clk>; + ti,bit-shift = <25>; + reg = <0x0548>; + }; + + func_mcbsp1_gfclk: func_mcbsp1_gfclk { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&mcbsp1_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>; + ti,bit-shift = <24>; + reg = <0x0548>; + }; + + mcbsp2_sync_mux_ck: mcbsp2_sync_mux_ck { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&abe_24m_fclk>, <&syc_clk_div_ck>, <&func_24m_clk>; + ti,bit-shift = <25>; + reg = <0x0550>; + }; + + func_mcbsp2_gfclk: func_mcbsp2_gfclk { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&mcbsp2_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>; + ti,bit-shift = <24>; + reg = <0x0550>; + }; + + mcbsp3_sync_mux_ck: mcbsp3_sync_mux_ck { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&abe_24m_fclk>, <&syc_clk_div_ck>, <&func_24m_clk>; + ti,bit-shift = <25>; + reg = <0x0558>; + }; + + func_mcbsp3_gfclk: func_mcbsp3_gfclk { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&mcbsp3_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>; + ti,bit-shift = <24>; + reg = <0x0558>; + }; + + slimbus1_fclk_1: slimbus1_fclk_1 { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&func_24m_clk>; + ti,bit-shift = <9>; + reg = <0x0560>; + }; + + slimbus1_fclk_0: slimbus1_fclk_0 { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&abe_24m_fclk>; + ti,bit-shift = <8>; + reg = <0x0560>; + }; + + slimbus1_fclk_2: slimbus1_fclk_2 { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&pad_clks_ck>; + ti,bit-shift = <10>; + reg = <0x0560>; + }; + + slimbus1_slimbus_clk: slimbus1_slimbus_clk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&slimbus_clk>; + ti,bit-shift = <11>; + reg = <0x0560>; + }; + + timer5_sync_mux: timer5_sync_mux { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&syc_clk_div_ck>, <&sys_32k_ck>; + ti,bit-shift = <24>; + reg = <0x0568>; + }; + + timer6_sync_mux: timer6_sync_mux { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&syc_clk_div_ck>, <&sys_32k_ck>; + ti,bit-shift = <24>; + reg = <0x0570>; + }; + + timer7_sync_mux: timer7_sync_mux { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&syc_clk_div_ck>, <&sys_32k_ck>; + ti,bit-shift = <24>; + reg = <0x0578>; + }; + + timer8_sync_mux: timer8_sync_mux { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&syc_clk_div_ck>, <&sys_32k_ck>; + ti,bit-shift = <24>; + reg = <0x0580>; + }; + + dummy_ck: dummy_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0>; + }; +}; +&prm_clocks { + sys_clkin_ck: sys_clkin_ck { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&virt_12000000_ck>, <&virt_13000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>; + reg = <0x0110>; + ti,index-starts-at-one; + }; + + abe_dpll_bypass_clk_mux_ck: abe_dpll_bypass_clk_mux_ck { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&sys_clkin_ck>, <&sys_32k_ck>; + ti,bit-shift = <24>; + reg = <0x0108>; + }; + + abe_dpll_refclk_mux_ck: abe_dpll_refclk_mux_ck { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&sys_clkin_ck>, <&sys_32k_ck>; + reg = <0x010c>; + }; + + dbgclk_mux_ck: dbgclk_mux_ck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&sys_clkin_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + l4_wkup_clk_mux_ck: l4_wkup_clk_mux_ck { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&sys_clkin_ck>, <&lp_clk_div_ck>; + reg = <0x0108>; + }; + + syc_clk_div_ck: syc_clk_div_ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&sys_clkin_ck>; + reg = <0x0100>; + ti,max-div = <2>; + }; + + gpio1_dbclk: gpio1_dbclk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&sys_32k_ck>; + ti,bit-shift = <8>; + reg = <0x1838>; + }; + + dmt1_clk_mux: dmt1_clk_mux { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&sys_clkin_ck>, <&sys_32k_ck>; + ti,bit-shift = <24>; + reg = <0x1840>; + }; + + usim_ck: usim_ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll_per_m4x2_ck>; + ti,bit-shift = <24>; + reg = <0x1858>; + ti,dividers = <14>, <18>; + }; + + usim_fclk: usim_fclk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&usim_ck>; + ti,bit-shift = <8>; + reg = <0x1858>; + }; + + pmd_stm_clock_mux_ck: pmd_stm_clock_mux_ck { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&sys_clkin_ck>, <&dpll_core_m6x2_ck>, <&tie_low_clock_ck>; + ti,bit-shift = <20>; + reg = <0x1a20>; + }; + + pmd_trace_clk_mux_ck: pmd_trace_clk_mux_ck { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&sys_clkin_ck>, <&dpll_core_m6x2_ck>, <&tie_low_clock_ck>; + ti,bit-shift = <22>; + reg = <0x1a20>; + }; + + stm_clk_div_ck: stm_clk_div_ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&pmd_stm_clock_mux_ck>; + ti,bit-shift = <27>; + ti,max-div = <64>; + reg = <0x1a20>; + ti,index-power-of-two; + }; + + trace_clk_div_div_ck: trace_clk_div_div_ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&pmd_trace_clk_mux_ck>; + ti,bit-shift = <24>; + reg = <0x1a20>; + ti,dividers = <0>, <1>, <2>, <0>, <4>; + }; + + trace_clk_div_ck: trace_clk_div_ck { + #clock-cells = <0>; + compatible = "ti,clkdm-gate-clock"; + clocks = <&trace_clk_div_div_ck>; + }; +}; + +&prm_clockdomains { + emu_sys_clkdm: emu_sys_clkdm { + compatible = "ti,clockdomain"; + clocks = <&trace_clk_div_ck>; + }; +}; + +&cm2_clocks { + per_hsd_byp_clk_mux_ck: per_hsd_byp_clk_mux_ck { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&sys_clkin_ck>, <&per_hs_clk_div_ck>; + ti,bit-shift = <23>; + reg = <0x014c>; + }; + + dpll_per_ck: dpll_per_ck { + #clock-cells = <0>; + compatible = "ti,omap4-dpll-clock"; + clocks = <&sys_clkin_ck>, <&per_hsd_byp_clk_mux_ck>; + reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>; + }; + + dpll_per_m2_ck: dpll_per_m2_ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll_per_ck>; + ti,max-div = <31>; + reg = <0x0150>; + ti,index-starts-at-one; + }; + + dpll_per_x2_ck: dpll_per_x2_ck { + #clock-cells = <0>; + compatible = "ti,omap4-dpll-x2-clock"; + clocks = <&dpll_per_ck>; + reg = <0x0150>; + }; + + dpll_per_m2x2_ck: dpll_per_m2x2_ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll_per_x2_ck>; + ti,max-div = <31>; + ti,autoidle-shift = <8>; + reg = <0x0150>; + ti,index-starts-at-one; + ti,invert-autoidle-bit; + }; + + dpll_per_m3x2_gate_ck: dpll_per_m3x2_gate_ck { + #clock-cells = <0>; + compatible = "ti,composite-no-wait-gate-clock"; + clocks = <&dpll_per_x2_ck>; + ti,bit-shift = <8>; + reg = <0x0154>; + }; + + dpll_per_m3x2_div_ck: dpll_per_m3x2_div_ck { + #clock-cells = <0>; + compatible = "ti,composite-divider-clock"; + clocks = <&dpll_per_x2_ck>; + ti,max-div = <31>; + reg = <0x0154>; + ti,index-starts-at-one; + }; + + dpll_per_m3x2_ck: dpll_per_m3x2_ck { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&dpll_per_m3x2_gate_ck>, <&dpll_per_m3x2_div_ck>; + }; + + dpll_per_m4x2_ck: dpll_per_m4x2_ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll_per_x2_ck>; + ti,max-div = <31>; + ti,autoidle-shift = <8>; + reg = <0x0158>; + ti,index-starts-at-one; + ti,invert-autoidle-bit; + }; + + dpll_per_m5x2_ck: dpll_per_m5x2_ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll_per_x2_ck>; + ti,max-div = <31>; + ti,autoidle-shift = <8>; + reg = <0x015c>; + ti,index-starts-at-one; + ti,invert-autoidle-bit; + }; + + dpll_per_m6x2_ck: dpll_per_m6x2_ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll_per_x2_ck>; + ti,max-div = <31>; + ti,autoidle-shift = <8>; + reg = <0x0160>; + ti,index-starts-at-one; + ti,invert-autoidle-bit; + }; + + dpll_per_m7x2_ck: dpll_per_m7x2_ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll_per_x2_ck>; + ti,max-div = <31>; + ti,autoidle-shift = <8>; + reg = <0x0164>; + ti,index-starts-at-one; + ti,invert-autoidle-bit; + }; + + dpll_usb_ck: dpll_usb_ck { + #clock-cells = <0>; + compatible = "ti,omap4-dpll-j-type-clock"; + clocks = <&sys_clkin_ck>, <&usb_hs_clk_div_ck>; + reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>; + }; + + dpll_usb_clkdcoldo_ck: dpll_usb_clkdcoldo_ck { + #clock-cells = <0>; + compatible = "ti,fixed-factor-clock"; + clocks = <&dpll_usb_ck>; + ti,clock-div = <1>; + ti,autoidle-shift = <8>; + reg = <0x01b4>; + ti,clock-mult = <1>; + ti,invert-autoidle-bit; + }; + + dpll_usb_m2_ck: dpll_usb_m2_ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll_usb_ck>; + ti,max-div = <127>; + ti,autoidle-shift = <8>; + reg = <0x0190>; + ti,index-starts-at-one; + ti,invert-autoidle-bit; + }; + + ducati_clk_mux_ck: ducati_clk_mux_ck { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&div_core_ck>, <&dpll_per_m6x2_ck>; + reg = <0x0100>; + }; + + func_12m_fclk: func_12m_fclk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll_per_m2x2_ck>; + clock-mult = <1>; + clock-div = <16>; + }; + + func_24m_clk: func_24m_clk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll_per_m2_ck>; + clock-mult = <1>; + clock-div = <4>; + }; + + func_24mc_fclk: func_24mc_fclk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll_per_m2x2_ck>; + clock-mult = <1>; + clock-div = <8>; + }; + + func_48m_fclk: func_48m_fclk { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll_per_m2x2_ck>; + reg = <0x0108>; + ti,dividers = <4>, <8>; + }; + + func_48mc_fclk: func_48mc_fclk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll_per_m2x2_ck>; + clock-mult = <1>; + clock-div = <4>; + }; + + func_64m_fclk: func_64m_fclk { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll_per_m4x2_ck>; + reg = <0x0108>; + ti,dividers = <2>, <4>; + }; + + func_96m_fclk: func_96m_fclk { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll_per_m2x2_ck>; + reg = <0x0108>; + ti,dividers = <2>, <4>; + }; + + init_60m_fclk: init_60m_fclk { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll_usb_m2_ck>; + reg = <0x0104>; + ti,dividers = <1>, <8>; + }; + + per_abe_nc_fclk: per_abe_nc_fclk { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll_abe_m2_ck>; + reg = <0x0108>; + ti,max-div = <2>; + }; + + aes1_fck: aes1_fck { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&l3_div_ck>; + ti,bit-shift = <1>; + reg = <0x15a0>; + }; + + aes2_fck: aes2_fck { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&l3_div_ck>; + ti,bit-shift = <1>; + reg = <0x15a8>; + }; + + dss_sys_clk: dss_sys_clk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&syc_clk_div_ck>; + ti,bit-shift = <10>; + reg = <0x1120>; + }; + + dss_tv_clk: dss_tv_clk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&extalt_clkin_ck>; + ti,bit-shift = <11>; + reg = <0x1120>; + }; + + dss_dss_clk: dss_dss_clk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&dpll_per_m5x2_ck>; + ti,bit-shift = <8>; + reg = <0x1120>; + ti,set-rate-parent; + }; + + dss_48mhz_clk: dss_48mhz_clk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&func_48mc_fclk>; + ti,bit-shift = <9>; + reg = <0x1120>; + }; + + dss_fck: dss_fck { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&l3_div_ck>; + ti,bit-shift = <1>; + reg = <0x1120>; + }; + + fdif_fck: fdif_fck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll_per_m4x2_ck>; + ti,bit-shift = <24>; + ti,max-div = <4>; + reg = <0x1028>; + ti,index-power-of-two; + }; + + gpio2_dbclk: gpio2_dbclk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&sys_32k_ck>; + ti,bit-shift = <8>; + reg = <0x1460>; + }; + + gpio3_dbclk: gpio3_dbclk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&sys_32k_ck>; + ti,bit-shift = <8>; + reg = <0x1468>; + }; + + gpio4_dbclk: gpio4_dbclk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&sys_32k_ck>; + ti,bit-shift = <8>; + reg = <0x1470>; + }; + + gpio5_dbclk: gpio5_dbclk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&sys_32k_ck>; + ti,bit-shift = <8>; + reg = <0x1478>; + }; + + gpio6_dbclk: gpio6_dbclk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&sys_32k_ck>; + ti,bit-shift = <8>; + reg = <0x1480>; + }; + + sgx_clk_mux: sgx_clk_mux { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&dpll_core_m7x2_ck>, <&dpll_per_m7x2_ck>; + ti,bit-shift = <24>; + reg = <0x1220>; + }; + + hsi_fck: hsi_fck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll_per_m2x2_ck>; + ti,bit-shift = <24>; + ti,max-div = <4>; + reg = <0x1338>; + ti,index-power-of-two; + }; + + iss_ctrlclk: iss_ctrlclk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&func_96m_fclk>; + ti,bit-shift = <8>; + reg = <0x1020>; + }; + + mcbsp4_sync_mux_ck: mcbsp4_sync_mux_ck { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&func_96m_fclk>, <&per_abe_nc_fclk>; + ti,bit-shift = <25>; + reg = <0x14e0>; + }; + + per_mcbsp4_gfclk: per_mcbsp4_gfclk { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&mcbsp4_sync_mux_ck>, <&pad_clks_ck>; + ti,bit-shift = <24>; + reg = <0x14e0>; + }; + + hsmmc1_fclk: hsmmc1_fclk { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&func_64m_fclk>, <&func_96m_fclk>; + ti,bit-shift = <24>; + reg = <0x1328>; + }; + + hsmmc2_fclk: hsmmc2_fclk { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&func_64m_fclk>, <&func_96m_fclk>; + ti,bit-shift = <24>; + reg = <0x1330>; + }; + + ocp2scp_usb_phy_phy_48m: ocp2scp_usb_phy_phy_48m { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&func_48m_fclk>; + ti,bit-shift = <8>; + reg = <0x13e0>; + }; + + sha2md5_fck: sha2md5_fck { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&l3_div_ck>; + ti,bit-shift = <1>; + reg = <0x15c8>; + }; + + slimbus2_fclk_1: slimbus2_fclk_1 { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&per_abe_24m_fclk>; + ti,bit-shift = <9>; + reg = <0x1538>; + }; + + slimbus2_fclk_0: slimbus2_fclk_0 { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&func_24mc_fclk>; + ti,bit-shift = <8>; + reg = <0x1538>; + }; + + slimbus2_slimbus_clk: slimbus2_slimbus_clk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&pad_slimbus_core_clks_ck>; + ti,bit-shift = <10>; + reg = <0x1538>; + }; + + smartreflex_core_fck: smartreflex_core_fck { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&l4_wkup_clk_mux_ck>; + ti,bit-shift = <1>; + reg = <0x0638>; + }; + + smartreflex_iva_fck: smartreflex_iva_fck { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&l4_wkup_clk_mux_ck>; + ti,bit-shift = <1>; + reg = <0x0630>; + }; + + smartreflex_mpu_fck: smartreflex_mpu_fck { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&l4_wkup_clk_mux_ck>; + ti,bit-shift = <1>; + reg = <0x0628>; + }; + + cm2_dm10_mux: cm2_dm10_mux { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&sys_clkin_ck>, <&sys_32k_ck>; + ti,bit-shift = <24>; + reg = <0x1428>; + }; + + cm2_dm11_mux: cm2_dm11_mux { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&sys_clkin_ck>, <&sys_32k_ck>; + ti,bit-shift = <24>; + reg = <0x1430>; + }; + + cm2_dm2_mux: cm2_dm2_mux { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&sys_clkin_ck>, <&sys_32k_ck>; + ti,bit-shift = <24>; + reg = <0x1438>; + }; + + cm2_dm3_mux: cm2_dm3_mux { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&sys_clkin_ck>, <&sys_32k_ck>; + ti,bit-shift = <24>; + reg = <0x1440>; + }; + + cm2_dm4_mux: cm2_dm4_mux { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&sys_clkin_ck>, <&sys_32k_ck>; + ti,bit-shift = <24>; + reg = <0x1448>; + }; + + cm2_dm9_mux: cm2_dm9_mux { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&sys_clkin_ck>, <&sys_32k_ck>; + ti,bit-shift = <24>; + reg = <0x1450>; + }; + + usb_host_fs_fck: usb_host_fs_fck { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&func_48mc_fclk>; + ti,bit-shift = <1>; + reg = <0x13d0>; + }; + + utmi_p1_gfclk: utmi_p1_gfclk { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&init_60m_fclk>, <&xclk60mhsp1_ck>; + ti,bit-shift = <24>; + reg = <0x1358>; + }; + + usb_host_hs_utmi_p1_clk: usb_host_hs_utmi_p1_clk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&utmi_p1_gfclk>; + ti,bit-shift = <8>; + reg = <0x1358>; + }; + + utmi_p2_gfclk: utmi_p2_gfclk { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&init_60m_fclk>, <&xclk60mhsp2_ck>; + ti,bit-shift = <25>; + reg = <0x1358>; + }; + + usb_host_hs_utmi_p2_clk: usb_host_hs_utmi_p2_clk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&utmi_p2_gfclk>; + ti,bit-shift = <9>; + reg = <0x1358>; + }; + + usb_host_hs_utmi_p3_clk: usb_host_hs_utmi_p3_clk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&init_60m_fclk>; + ti,bit-shift = <10>; + reg = <0x1358>; + }; + + usb_host_hs_hsic480m_p1_clk: usb_host_hs_hsic480m_p1_clk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&dpll_usb_m2_ck>; + ti,bit-shift = <13>; + reg = <0x1358>; + }; + + usb_host_hs_hsic60m_p1_clk: usb_host_hs_hsic60m_p1_clk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&init_60m_fclk>; + ti,bit-shift = <11>; + reg = <0x1358>; + }; + + usb_host_hs_hsic60m_p2_clk: usb_host_hs_hsic60m_p2_clk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&init_60m_fclk>; + ti,bit-shift = <12>; + reg = <0x1358>; + }; + + usb_host_hs_hsic480m_p2_clk: usb_host_hs_hsic480m_p2_clk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&dpll_usb_m2_ck>; + ti,bit-shift = <14>; + reg = <0x1358>; + }; + + usb_host_hs_func48mclk: usb_host_hs_func48mclk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&func_48mc_fclk>; + ti,bit-shift = <15>; + reg = <0x1358>; + }; + + usb_host_hs_fck: usb_host_hs_fck { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&init_60m_fclk>; + ti,bit-shift = <1>; + reg = <0x1358>; + }; + + otg_60m_gfclk: otg_60m_gfclk { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&utmi_phy_clkout_ck>, <&xclk60motg_ck>; + ti,bit-shift = <24>; + reg = <0x1360>; + }; + + usb_otg_hs_xclk: usb_otg_hs_xclk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&otg_60m_gfclk>; + ti,bit-shift = <8>; + reg = <0x1360>; + }; + + usb_otg_hs_ick: usb_otg_hs_ick { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&l3_div_ck>; + ti,bit-shift = <0>; + reg = <0x1360>; + }; + + usb_phy_cm_clk32k: usb_phy_cm_clk32k { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&sys_32k_ck>; + ti,bit-shift = <8>; + reg = <0x0640>; + }; + + usb_tll_hs_usb_ch2_clk: usb_tll_hs_usb_ch2_clk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&init_60m_fclk>; + ti,bit-shift = <10>; + reg = <0x1368>; + }; + + usb_tll_hs_usb_ch0_clk: usb_tll_hs_usb_ch0_clk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&init_60m_fclk>; + ti,bit-shift = <8>; + reg = <0x1368>; + }; + + usb_tll_hs_usb_ch1_clk: usb_tll_hs_usb_ch1_clk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&init_60m_fclk>; + ti,bit-shift = <9>; + reg = <0x1368>; + }; + + usb_tll_hs_ick: usb_tll_hs_ick { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&l4_div_ck>; + ti,bit-shift = <0>; + reg = <0x1368>; + }; +}; + +&cm2_clockdomains { + l3_init_clkdm: l3_init_clkdm { + compatible = "ti,clockdomain"; + clocks = <&dpll_usb_ck>, <&usb_host_fs_fck>; + }; +}; + +&scrm_clocks { + auxclk0_src_gate_ck: auxclk0_src_gate_ck { + #clock-cells = <0>; + compatible = "ti,composite-no-wait-gate-clock"; + clocks = <&dpll_core_m3x2_ck>; + ti,bit-shift = <8>; + reg = <0x0310>; + }; + + auxclk0_src_mux_ck: auxclk0_src_mux_ck { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; + ti,bit-shift = <1>; + reg = <0x0310>; + }; + + auxclk0_src_ck: auxclk0_src_ck { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&auxclk0_src_gate_ck>, <&auxclk0_src_mux_ck>; + }; + + auxclk0_ck: auxclk0_ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&auxclk0_src_ck>; + ti,bit-shift = <16>; + ti,max-div = <16>; + reg = <0x0310>; + }; + + auxclk1_src_gate_ck: auxclk1_src_gate_ck { + #clock-cells = <0>; + compatible = "ti,composite-no-wait-gate-clock"; + clocks = <&dpll_core_m3x2_ck>; + ti,bit-shift = <8>; + reg = <0x0314>; + }; + + auxclk1_src_mux_ck: auxclk1_src_mux_ck { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; + ti,bit-shift = <1>; + reg = <0x0314>; + }; + + auxclk1_src_ck: auxclk1_src_ck { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&auxclk1_src_gate_ck>, <&auxclk1_src_mux_ck>; + }; + + auxclk1_ck: auxclk1_ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&auxclk1_src_ck>; + ti,bit-shift = <16>; + ti,max-div = <16>; + reg = <0x0314>; + }; + + auxclk2_src_gate_ck: auxclk2_src_gate_ck { + #clock-cells = <0>; + compatible = "ti,composite-no-wait-gate-clock"; + clocks = <&dpll_core_m3x2_ck>; + ti,bit-shift = <8>; + reg = <0x0318>; + }; + + auxclk2_src_mux_ck: auxclk2_src_mux_ck { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; + ti,bit-shift = <1>; + reg = <0x0318>; + }; + + auxclk2_src_ck: auxclk2_src_ck { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&auxclk2_src_gate_ck>, <&auxclk2_src_mux_ck>; + }; + + auxclk2_ck: auxclk2_ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&auxclk2_src_ck>; + ti,bit-shift = <16>; + ti,max-div = <16>; + reg = <0x0318>; + }; + + auxclk3_src_gate_ck: auxclk3_src_gate_ck { + #clock-cells = <0>; + compatible = "ti,composite-no-wait-gate-clock"; + clocks = <&dpll_core_m3x2_ck>; + ti,bit-shift = <8>; + reg = <0x031c>; + }; + + auxclk3_src_mux_ck: auxclk3_src_mux_ck { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; + ti,bit-shift = <1>; + reg = <0x031c>; + }; + + auxclk3_src_ck: auxclk3_src_ck { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&auxclk3_src_gate_ck>, <&auxclk3_src_mux_ck>; + }; + + auxclk3_ck: auxclk3_ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&auxclk3_src_ck>; + ti,bit-shift = <16>; + ti,max-div = <16>; + reg = <0x031c>; + }; + + auxclk4_src_gate_ck: auxclk4_src_gate_ck { + #clock-cells = <0>; + compatible = "ti,composite-no-wait-gate-clock"; + clocks = <&dpll_core_m3x2_ck>; + ti,bit-shift = <8>; + reg = <0x0320>; + }; + + auxclk4_src_mux_ck: auxclk4_src_mux_ck { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; + ti,bit-shift = <1>; + reg = <0x0320>; + }; + + auxclk4_src_ck: auxclk4_src_ck { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&auxclk4_src_gate_ck>, <&auxclk4_src_mux_ck>; + }; + + auxclk4_ck: auxclk4_ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&auxclk4_src_ck>; + ti,bit-shift = <16>; + ti,max-div = <16>; + reg = <0x0320>; + }; + + auxclk5_src_gate_ck: auxclk5_src_gate_ck { + #clock-cells = <0>; + compatible = "ti,composite-no-wait-gate-clock"; + clocks = <&dpll_core_m3x2_ck>; + ti,bit-shift = <8>; + reg = <0x0324>; + }; + + auxclk5_src_mux_ck: auxclk5_src_mux_ck { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; + ti,bit-shift = <1>; + reg = <0x0324>; + }; + + auxclk5_src_ck: auxclk5_src_ck { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&auxclk5_src_gate_ck>, <&auxclk5_src_mux_ck>; + }; + + auxclk5_ck: auxclk5_ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&auxclk5_src_ck>; + ti,bit-shift = <16>; + ti,max-div = <16>; + reg = <0x0324>; + }; + + auxclkreq0_ck: auxclkreq0_ck { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>; + ti,bit-shift = <2>; + reg = <0x0210>; + }; + + auxclkreq1_ck: auxclkreq1_ck { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>; + ti,bit-shift = <2>; + reg = <0x0214>; + }; + + auxclkreq2_ck: auxclkreq2_ck { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>; + ti,bit-shift = <2>; + reg = <0x0218>; + }; + + auxclkreq3_ck: auxclkreq3_ck { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>; + ti,bit-shift = <2>; + reg = <0x021c>; + }; + + auxclkreq4_ck: auxclkreq4_ck { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>; + ti,bit-shift = <2>; + reg = <0x0220>; + }; + + auxclkreq5_ck: auxclkreq5_ck { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>; + ti,bit-shift = <2>; + reg = <0x0224>; + }; +}; -- cgit v1.2.3-59-g8ed1b From 85dc74e9bd9cb5bac39e63bd3fe1f1d083e3973d Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Thu, 18 Jul 2013 17:09:29 +0300 Subject: ARM: dts: omap5 clock data This patch creates a unique node for each clock in the OMAP5 power, reset and clock manager (PRCM). Signed-off-by: Tero Kristo Acked-by: Tony Lindgren Signed-off-by: Mike Turquette --- arch/arm/boot/dts/omap5.dtsi | 54 ++ arch/arm/boot/dts/omap54xx-clocks.dtsi | 1399 ++++++++++++++++++++++++++++++++ 2 files changed, 1453 insertions(+) create mode 100644 arch/arm/boot/dts/omap54xx-clocks.dtsi diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi index fc3fad563861..2f12a47aa83c 100644 --- a/arch/arm/boot/dts/omap5.dtsi +++ b/arch/arm/boot/dts/omap5.dtsi @@ -107,6 +107,58 @@ interrupts = , ; + prm: prm@4ae06000 { + compatible = "ti,omap5-prm"; + reg = <0x4ae06000 0x3000>; + + prm_clocks: clocks { + #address-cells = <1>; + #size-cells = <0>; + }; + + prm_clockdomains: clockdomains { + }; + }; + + cm_core_aon: cm_core_aon@4a004000 { + compatible = "ti,omap5-cm-core-aon"; + reg = <0x4a004000 0x2000>; + + cm_core_aon_clocks: clocks { + #address-cells = <1>; + #size-cells = <0>; + }; + + cm_core_aon_clockdomains: clockdomains { + }; + }; + + scrm: scrm@4ae0a000 { + compatible = "ti,omap5-scrm"; + reg = <0x4ae0a000 0x2000>; + + scrm_clocks: clocks { + #address-cells = <1>; + #size-cells = <0>; + }; + + scrm_clockdomains: clockdomains { + }; + }; + + cm_core: cm_core@4a008000 { + compatible = "ti,omap5-cm-core"; + reg = <0x4a008000 0x3000>; + + cm_core_clocks: clocks { + #address-cells = <1>; + #size-cells = <0>; + }; + + cm_core_clockdomains: clockdomains { + }; + }; + counter32k: counter@4ae04000 { compatible = "ti,omap-counter32k"; reg = <0x4ae04000 0x40>; @@ -739,3 +791,5 @@ }; }; }; + +/include/ "omap54xx-clocks.dtsi" diff --git a/arch/arm/boot/dts/omap54xx-clocks.dtsi b/arch/arm/boot/dts/omap54xx-clocks.dtsi new file mode 100644 index 000000000000..d487fdab3921 --- /dev/null +++ b/arch/arm/boot/dts/omap54xx-clocks.dtsi @@ -0,0 +1,1399 @@ +/* + * Device Tree Source for OMAP5 clock data + * + * Copyright (C) 2013 Texas Instruments, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +&cm_core_aon_clocks { + pad_clks_src_ck: pad_clks_src_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <12000000>; + }; + + pad_clks_ck: pad_clks_ck { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&pad_clks_src_ck>; + ti,bit-shift = <8>; + reg = <0x0108>; + }; + + secure_32k_clk_src_ck: secure_32k_clk_src_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + }; + + slimbus_src_clk: slimbus_src_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <12000000>; + }; + + slimbus_clk: slimbus_clk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&slimbus_src_clk>; + ti,bit-shift = <10>; + reg = <0x0108>; + }; + + sys_32k_ck: sys_32k_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + }; + + virt_12000000_ck: virt_12000000_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <12000000>; + }; + + virt_13000000_ck: virt_13000000_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <13000000>; + }; + + virt_16800000_ck: virt_16800000_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <16800000>; + }; + + virt_19200000_ck: virt_19200000_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <19200000>; + }; + + virt_26000000_ck: virt_26000000_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <26000000>; + }; + + virt_27000000_ck: virt_27000000_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <27000000>; + }; + + virt_38400000_ck: virt_38400000_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <38400000>; + }; + + xclk60mhsp1_ck: xclk60mhsp1_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <60000000>; + }; + + xclk60mhsp2_ck: xclk60mhsp2_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <60000000>; + }; + + dpll_abe_ck: dpll_abe_ck { + #clock-cells = <0>; + compatible = "ti,omap4-dpll-m4xen-clock"; + clocks = <&abe_dpll_clk_mux>, <&abe_dpll_bypass_clk_mux>; + reg = <0x01e0>, <0x01e4>, <0x01ec>, <0x01e8>; + }; + + dpll_abe_x2_ck: dpll_abe_x2_ck { + #clock-cells = <0>; + compatible = "ti,omap4-dpll-x2-clock"; + clocks = <&dpll_abe_ck>; + }; + + dpll_abe_m2x2_ck: dpll_abe_m2x2_ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll_abe_x2_ck>; + ti,max-div = <31>; + ti,autoidle-shift = <8>; + reg = <0x01f0>; + ti,index-starts-at-one; + ti,invert-autoidle-bit; + }; + + abe_24m_fclk: abe_24m_fclk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll_abe_m2x2_ck>; + clock-mult = <1>; + clock-div = <8>; + }; + + abe_clk: abe_clk { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll_abe_m2x2_ck>; + ti,max-div = <4>; + reg = <0x0108>; + ti,index-power-of-two; + }; + + abe_iclk: abe_iclk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&abe_clk>; + clock-mult = <1>; + clock-div = <2>; + }; + + abe_lp_clk_div: abe_lp_clk_div { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll_abe_m2x2_ck>; + clock-mult = <1>; + clock-div = <16>; + }; + + dpll_abe_m3x2_ck: dpll_abe_m3x2_ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll_abe_x2_ck>; + ti,max-div = <31>; + ti,autoidle-shift = <8>; + reg = <0x01f4>; + ti,index-starts-at-one; + ti,invert-autoidle-bit; + }; + + dpll_core_ck: dpll_core_ck { + #clock-cells = <0>; + compatible = "ti,omap4-dpll-core-clock"; + clocks = <&sys_clkin>, <&dpll_abe_m3x2_ck>; + reg = <0x0120>, <0x0124>, <0x012c>, <0x0128>; + }; + + dpll_core_x2_ck: dpll_core_x2_ck { + #clock-cells = <0>; + compatible = "ti,omap4-dpll-x2-clock"; + clocks = <&dpll_core_ck>; + }; + + dpll_core_h21x2_ck: dpll_core_h21x2_ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll_core_x2_ck>; + ti,max-div = <63>; + ti,autoidle-shift = <8>; + reg = <0x0150>; + ti,index-starts-at-one; + ti,invert-autoidle-bit; + }; + + c2c_fclk: c2c_fclk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll_core_h21x2_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + c2c_iclk: c2c_iclk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&c2c_fclk>; + clock-mult = <1>; + clock-div = <2>; + }; + + dpll_core_h11x2_ck: dpll_core_h11x2_ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll_core_x2_ck>; + ti,max-div = <63>; + ti,autoidle-shift = <8>; + reg = <0x0138>; + ti,index-starts-at-one; + ti,invert-autoidle-bit; + }; + + dpll_core_h12x2_ck: dpll_core_h12x2_ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll_core_x2_ck>; + ti,max-div = <63>; + ti,autoidle-shift = <8>; + reg = <0x013c>; + ti,index-starts-at-one; + ti,invert-autoidle-bit; + }; + + dpll_core_h13x2_ck: dpll_core_h13x2_ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll_core_x2_ck>; + ti,max-div = <63>; + ti,autoidle-shift = <8>; + reg = <0x0140>; + ti,index-starts-at-one; + ti,invert-autoidle-bit; + }; + + dpll_core_h14x2_ck: dpll_core_h14x2_ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll_core_x2_ck>; + ti,max-div = <63>; + ti,autoidle-shift = <8>; + reg = <0x0144>; + ti,index-starts-at-one; + ti,invert-autoidle-bit; + }; + + dpll_core_h22x2_ck: dpll_core_h22x2_ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll_core_x2_ck>; + ti,max-div = <63>; + ti,autoidle-shift = <8>; + reg = <0x0154>; + ti,index-starts-at-one; + ti,invert-autoidle-bit; + }; + + dpll_core_h23x2_ck: dpll_core_h23x2_ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll_core_x2_ck>; + ti,max-div = <63>; + ti,autoidle-shift = <8>; + reg = <0x0158>; + ti,index-starts-at-one; + ti,invert-autoidle-bit; + }; + + dpll_core_h24x2_ck: dpll_core_h24x2_ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll_core_x2_ck>; + ti,max-div = <63>; + ti,autoidle-shift = <8>; + reg = <0x015c>; + ti,index-starts-at-one; + ti,invert-autoidle-bit; + }; + + dpll_core_m2_ck: dpll_core_m2_ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll_core_ck>; + ti,max-div = <31>; + ti,autoidle-shift = <8>; + reg = <0x0130>; + ti,index-starts-at-one; + ti,invert-autoidle-bit; + }; + + dpll_core_m3x2_ck: dpll_core_m3x2_ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll_core_x2_ck>; + ti,max-div = <31>; + ti,autoidle-shift = <8>; + reg = <0x0134>; + ti,index-starts-at-one; + ti,invert-autoidle-bit; + }; + + iva_dpll_hs_clk_div: iva_dpll_hs_clk_div { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll_core_h12x2_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + dpll_iva_ck: dpll_iva_ck { + #clock-cells = <0>; + compatible = "ti,omap4-dpll-clock"; + clocks = <&sys_clkin>, <&iva_dpll_hs_clk_div>; + reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>; + }; + + dpll_iva_x2_ck: dpll_iva_x2_ck { + #clock-cells = <0>; + compatible = "ti,omap4-dpll-x2-clock"; + clocks = <&dpll_iva_ck>; + }; + + dpll_iva_h11x2_ck: dpll_iva_h11x2_ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll_iva_x2_ck>; + ti,max-div = <63>; + ti,autoidle-shift = <8>; + reg = <0x01b8>; + ti,index-starts-at-one; + ti,invert-autoidle-bit; + }; + + dpll_iva_h12x2_ck: dpll_iva_h12x2_ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll_iva_x2_ck>; + ti,max-div = <63>; + ti,autoidle-shift = <8>; + reg = <0x01bc>; + ti,index-starts-at-one; + ti,invert-autoidle-bit; + }; + + mpu_dpll_hs_clk_div: mpu_dpll_hs_clk_div { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll_core_h12x2_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + dpll_mpu_ck: dpll_mpu_ck { + #clock-cells = <0>; + compatible = "ti,omap4-dpll-clock"; + clocks = <&sys_clkin>, <&mpu_dpll_hs_clk_div>; + reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>; + }; + + dpll_mpu_m2_ck: dpll_mpu_m2_ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll_mpu_ck>; + ti,max-div = <31>; + ti,autoidle-shift = <8>; + reg = <0x0170>; + ti,index-starts-at-one; + ti,invert-autoidle-bit; + }; + + per_dpll_hs_clk_div: per_dpll_hs_clk_div { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll_abe_m3x2_ck>; + clock-mult = <1>; + clock-div = <2>; + }; + + usb_dpll_hs_clk_div: usb_dpll_hs_clk_div { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll_abe_m3x2_ck>; + clock-mult = <1>; + clock-div = <3>; + }; + + l3_iclk_div: l3_iclk_div { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll_core_h12x2_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + gpu_l3_iclk: gpu_l3_iclk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&l3_iclk_div>; + clock-mult = <1>; + clock-div = <1>; + }; + + l4_root_clk_div: l4_root_clk_div { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&l3_iclk_div>; + clock-mult = <1>; + clock-div = <1>; + }; + + slimbus1_slimbus_clk: slimbus1_slimbus_clk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&slimbus_clk>; + ti,bit-shift = <11>; + reg = <0x0560>; + }; + + aess_fclk: aess_fclk { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&abe_clk>; + ti,bit-shift = <24>; + ti,max-div = <2>; + reg = <0x0528>; + }; + + dmic_sync_mux_ck: dmic_sync_mux_ck { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>; + ti,bit-shift = <26>; + reg = <0x0538>; + }; + + dmic_gfclk: dmic_gfclk { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&dmic_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>; + ti,bit-shift = <24>; + reg = <0x0538>; + }; + + mcasp_sync_mux_ck: mcasp_sync_mux_ck { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>; + ti,bit-shift = <26>; + reg = <0x0540>; + }; + + mcasp_gfclk: mcasp_gfclk { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&mcasp_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>; + ti,bit-shift = <24>; + reg = <0x0540>; + }; + + mcbsp1_sync_mux_ck: mcbsp1_sync_mux_ck { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>; + ti,bit-shift = <26>; + reg = <0x0548>; + }; + + mcbsp1_gfclk: mcbsp1_gfclk { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&mcbsp1_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>; + ti,bit-shift = <24>; + reg = <0x0548>; + }; + + mcbsp2_sync_mux_ck: mcbsp2_sync_mux_ck { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>; + ti,bit-shift = <26>; + reg = <0x0550>; + }; + + mcbsp2_gfclk: mcbsp2_gfclk { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&mcbsp2_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>; + ti,bit-shift = <24>; + reg = <0x0550>; + }; + + mcbsp3_sync_mux_ck: mcbsp3_sync_mux_ck { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>; + ti,bit-shift = <26>; + reg = <0x0558>; + }; + + mcbsp3_gfclk: mcbsp3_gfclk { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&mcbsp3_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>; + ti,bit-shift = <24>; + reg = <0x0558>; + }; + + timer5_gfclk_mux: timer5_gfclk_mux { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>; + ti,bit-shift = <24>; + reg = <0x0568>; + }; + + timer6_gfclk_mux: timer6_gfclk_mux { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>; + ti,bit-shift = <24>; + reg = <0x0570>; + }; + + timer7_gfclk_mux: timer7_gfclk_mux { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>; + ti,bit-shift = <24>; + reg = <0x0578>; + }; + + timer8_gfclk_mux: timer8_gfclk_mux { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>; + ti,bit-shift = <24>; + reg = <0x0580>; + }; + + dummy_ck: dummy_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0>; + }; +}; +&prm_clocks { + sys_clkin: sys_clkin { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&virt_12000000_ck>, <&virt_13000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>; + reg = <0x0110>; + ti,index-starts-at-one; + }; + + abe_dpll_bypass_clk_mux: abe_dpll_bypass_clk_mux { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&sys_clkin>, <&sys_32k_ck>; + reg = <0x0108>; + }; + + abe_dpll_clk_mux: abe_dpll_clk_mux { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&sys_clkin>, <&sys_32k_ck>; + reg = <0x010c>; + }; + + custefuse_sys_gfclk_div: custefuse_sys_gfclk_div { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&sys_clkin>; + clock-mult = <1>; + clock-div = <2>; + }; + + dss_syc_gfclk_div: dss_syc_gfclk_div { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&sys_clkin>; + clock-mult = <1>; + clock-div = <1>; + }; + + wkupaon_iclk_mux: wkupaon_iclk_mux { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&sys_clkin>, <&abe_lp_clk_div>; + reg = <0x0108>; + }; + + l3instr_ts_gclk_div: l3instr_ts_gclk_div { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&wkupaon_iclk_mux>; + clock-mult = <1>; + clock-div = <1>; + }; + + gpio1_dbclk: gpio1_dbclk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&sys_32k_ck>; + ti,bit-shift = <8>; + reg = <0x1938>; + }; + + timer1_gfclk_mux: timer1_gfclk_mux { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&sys_clkin>, <&sys_32k_ck>; + ti,bit-shift = <24>; + reg = <0x1940>; + }; +}; +&cm_core_clocks { + dpll_per_ck: dpll_per_ck { + #clock-cells = <0>; + compatible = "ti,omap4-dpll-clock"; + clocks = <&sys_clkin>, <&per_dpll_hs_clk_div>; + reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>; + }; + + dpll_per_x2_ck: dpll_per_x2_ck { + #clock-cells = <0>; + compatible = "ti,omap4-dpll-x2-clock"; + clocks = <&dpll_per_ck>; + }; + + dpll_per_h11x2_ck: dpll_per_h11x2_ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll_per_x2_ck>; + ti,max-div = <63>; + ti,autoidle-shift = <8>; + reg = <0x0158>; + ti,index-starts-at-one; + ti,invert-autoidle-bit; + }; + + dpll_per_h12x2_ck: dpll_per_h12x2_ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll_per_x2_ck>; + ti,max-div = <63>; + ti,autoidle-shift = <8>; + reg = <0x015c>; + ti,index-starts-at-one; + ti,invert-autoidle-bit; + }; + + dpll_per_h14x2_ck: dpll_per_h14x2_ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll_per_x2_ck>; + ti,max-div = <63>; + ti,autoidle-shift = <8>; + reg = <0x0164>; + ti,index-starts-at-one; + ti,invert-autoidle-bit; + }; + + dpll_per_m2_ck: dpll_per_m2_ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll_per_ck>; + ti,max-div = <31>; + ti,autoidle-shift = <8>; + reg = <0x0150>; + ti,index-starts-at-one; + ti,invert-autoidle-bit; + }; + + dpll_per_m2x2_ck: dpll_per_m2x2_ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll_per_x2_ck>; + ti,max-div = <31>; + ti,autoidle-shift = <8>; + reg = <0x0150>; + ti,index-starts-at-one; + ti,invert-autoidle-bit; + }; + + dpll_per_m3x2_ck: dpll_per_m3x2_ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll_per_x2_ck>; + ti,max-div = <31>; + ti,autoidle-shift = <8>; + reg = <0x0154>; + ti,index-starts-at-one; + ti,invert-autoidle-bit; + }; + + dpll_unipro1_ck: dpll_unipro1_ck { + #clock-cells = <0>; + compatible = "ti,omap4-dpll-clock"; + clocks = <&sys_clkin>, <&sys_clkin>; + reg = <0x0200>, <0x0204>, <0x020c>, <0x0208>; + }; + + dpll_unipro1_clkdcoldo: dpll_unipro1_clkdcoldo { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll_unipro1_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + dpll_unipro1_m2_ck: dpll_unipro1_m2_ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll_unipro1_ck>; + ti,max-div = <127>; + ti,autoidle-shift = <8>; + reg = <0x0210>; + ti,index-starts-at-one; + ti,invert-autoidle-bit; + }; + + dpll_unipro2_ck: dpll_unipro2_ck { + #clock-cells = <0>; + compatible = "ti,omap4-dpll-clock"; + clocks = <&sys_clkin>, <&sys_clkin>; + reg = <0x01c0>, <0x01c4>, <0x01cc>, <0x01c8>; + }; + + dpll_unipro2_clkdcoldo: dpll_unipro2_clkdcoldo { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll_unipro2_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + dpll_unipro2_m2_ck: dpll_unipro2_m2_ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll_unipro2_ck>; + ti,max-div = <127>; + ti,autoidle-shift = <8>; + reg = <0x01d0>; + ti,index-starts-at-one; + ti,invert-autoidle-bit; + }; + + dpll_usb_ck: dpll_usb_ck { + #clock-cells = <0>; + compatible = "ti,omap4-dpll-j-type-clock"; + clocks = <&sys_clkin>, <&usb_dpll_hs_clk_div>; + reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>; + }; + + dpll_usb_clkdcoldo: dpll_usb_clkdcoldo { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll_usb_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + dpll_usb_m2_ck: dpll_usb_m2_ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll_usb_ck>; + ti,max-div = <127>; + ti,autoidle-shift = <8>; + reg = <0x0190>; + ti,index-starts-at-one; + ti,invert-autoidle-bit; + }; + + func_128m_clk: func_128m_clk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll_per_h11x2_ck>; + clock-mult = <1>; + clock-div = <2>; + }; + + func_12m_fclk: func_12m_fclk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll_per_m2x2_ck>; + clock-mult = <1>; + clock-div = <16>; + }; + + func_24m_clk: func_24m_clk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll_per_m2_ck>; + clock-mult = <1>; + clock-div = <4>; + }; + + func_48m_fclk: func_48m_fclk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll_per_m2x2_ck>; + clock-mult = <1>; + clock-div = <4>; + }; + + func_96m_fclk: func_96m_fclk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll_per_m2x2_ck>; + clock-mult = <1>; + clock-div = <2>; + }; + + l3init_60m_fclk: l3init_60m_fclk { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll_usb_m2_ck>; + reg = <0x0104>; + ti,dividers = <1>, <8>; + }; + + dss_32khz_clk: dss_32khz_clk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&sys_32k_ck>; + ti,bit-shift = <11>; + reg = <0x1420>; + }; + + dss_48mhz_clk: dss_48mhz_clk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&func_48m_fclk>; + ti,bit-shift = <9>; + reg = <0x1420>; + }; + + dss_dss_clk: dss_dss_clk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&dpll_per_h12x2_ck>; + ti,bit-shift = <8>; + reg = <0x1420>; + }; + + dss_sys_clk: dss_sys_clk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&dss_syc_gfclk_div>; + ti,bit-shift = <10>; + reg = <0x1420>; + }; + + gpio2_dbclk: gpio2_dbclk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&sys_32k_ck>; + ti,bit-shift = <8>; + reg = <0x1060>; + }; + + gpio3_dbclk: gpio3_dbclk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&sys_32k_ck>; + ti,bit-shift = <8>; + reg = <0x1068>; + }; + + gpio4_dbclk: gpio4_dbclk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&sys_32k_ck>; + ti,bit-shift = <8>; + reg = <0x1070>; + }; + + gpio5_dbclk: gpio5_dbclk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&sys_32k_ck>; + ti,bit-shift = <8>; + reg = <0x1078>; + }; + + gpio6_dbclk: gpio6_dbclk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&sys_32k_ck>; + ti,bit-shift = <8>; + reg = <0x1080>; + }; + + gpio7_dbclk: gpio7_dbclk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&sys_32k_ck>; + ti,bit-shift = <8>; + reg = <0x1110>; + }; + + gpio8_dbclk: gpio8_dbclk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&sys_32k_ck>; + ti,bit-shift = <8>; + reg = <0x1118>; + }; + + iss_ctrlclk: iss_ctrlclk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&func_96m_fclk>; + ti,bit-shift = <8>; + reg = <0x1320>; + }; + + lli_txphy_clk: lli_txphy_clk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&dpll_unipro1_clkdcoldo>; + ti,bit-shift = <8>; + reg = <0x0f20>; + }; + + lli_txphy_ls_clk: lli_txphy_ls_clk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&dpll_unipro1_m2_ck>; + ti,bit-shift = <9>; + reg = <0x0f20>; + }; + + mmc1_32khz_clk: mmc1_32khz_clk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&sys_32k_ck>; + ti,bit-shift = <8>; + reg = <0x1628>; + }; + + sata_ref_clk: sata_ref_clk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&sys_clkin>; + ti,bit-shift = <8>; + reg = <0x1688>; + }; + + usb_host_hs_hsic480m_p1_clk: usb_host_hs_hsic480m_p1_clk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&dpll_usb_m2_ck>; + ti,bit-shift = <13>; + reg = <0x1658>; + }; + + usb_host_hs_hsic480m_p2_clk: usb_host_hs_hsic480m_p2_clk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&dpll_usb_m2_ck>; + ti,bit-shift = <14>; + reg = <0x1658>; + }; + + usb_host_hs_hsic480m_p3_clk: usb_host_hs_hsic480m_p3_clk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&dpll_usb_m2_ck>; + ti,bit-shift = <7>; + reg = <0x1658>; + }; + + usb_host_hs_hsic60m_p1_clk: usb_host_hs_hsic60m_p1_clk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&l3init_60m_fclk>; + ti,bit-shift = <11>; + reg = <0x1658>; + }; + + usb_host_hs_hsic60m_p2_clk: usb_host_hs_hsic60m_p2_clk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&l3init_60m_fclk>; + ti,bit-shift = <12>; + reg = <0x1658>; + }; + + usb_host_hs_hsic60m_p3_clk: usb_host_hs_hsic60m_p3_clk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&l3init_60m_fclk>; + ti,bit-shift = <6>; + reg = <0x1658>; + }; + + utmi_p1_gfclk: utmi_p1_gfclk { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&l3init_60m_fclk>, <&xclk60mhsp1_ck>; + ti,bit-shift = <24>; + reg = <0x1658>; + }; + + usb_host_hs_utmi_p1_clk: usb_host_hs_utmi_p1_clk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&utmi_p1_gfclk>; + ti,bit-shift = <8>; + reg = <0x1658>; + }; + + utmi_p2_gfclk: utmi_p2_gfclk { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&l3init_60m_fclk>, <&xclk60mhsp2_ck>; + ti,bit-shift = <25>; + reg = <0x1658>; + }; + + usb_host_hs_utmi_p2_clk: usb_host_hs_utmi_p2_clk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&utmi_p2_gfclk>; + ti,bit-shift = <9>; + reg = <0x1658>; + }; + + usb_host_hs_utmi_p3_clk: usb_host_hs_utmi_p3_clk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&l3init_60m_fclk>; + ti,bit-shift = <10>; + reg = <0x1658>; + }; + + usb_otg_ss_refclk960m: usb_otg_ss_refclk960m { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&dpll_usb_clkdcoldo>; + ti,bit-shift = <8>; + reg = <0x16f0>; + }; + + usb_phy_cm_clk32k: usb_phy_cm_clk32k { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&sys_32k_ck>; + ti,bit-shift = <8>; + reg = <0x0640>; + }; + + usb_tll_hs_usb_ch0_clk: usb_tll_hs_usb_ch0_clk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&l3init_60m_fclk>; + ti,bit-shift = <8>; + reg = <0x1668>; + }; + + usb_tll_hs_usb_ch1_clk: usb_tll_hs_usb_ch1_clk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&l3init_60m_fclk>; + ti,bit-shift = <9>; + reg = <0x1668>; + }; + + usb_tll_hs_usb_ch2_clk: usb_tll_hs_usb_ch2_clk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&l3init_60m_fclk>; + ti,bit-shift = <10>; + reg = <0x1668>; + }; + + fdif_fclk: fdif_fclk { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll_per_h11x2_ck>; + ti,bit-shift = <24>; + ti,max-div = <2>; + reg = <0x1328>; + }; + + gpu_core_gclk_mux: gpu_core_gclk_mux { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>; + ti,bit-shift = <24>; + reg = <0x1520>; + }; + + gpu_hyd_gclk_mux: gpu_hyd_gclk_mux { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>; + ti,bit-shift = <25>; + reg = <0x1520>; + }; + + hsi_fclk: hsi_fclk { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll_per_m2x2_ck>; + ti,bit-shift = <24>; + ti,max-div = <2>; + reg = <0x1638>; + }; + + mmc1_fclk_mux: mmc1_fclk_mux { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>; + ti,bit-shift = <24>; + reg = <0x1628>; + }; + + mmc1_fclk: mmc1_fclk { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&mmc1_fclk_mux>; + ti,bit-shift = <25>; + ti,max-div = <2>; + reg = <0x1628>; + }; + + mmc2_fclk_mux: mmc2_fclk_mux { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>; + ti,bit-shift = <24>; + reg = <0x1630>; + }; + + mmc2_fclk: mmc2_fclk { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&mmc2_fclk_mux>; + ti,bit-shift = <25>; + ti,max-div = <2>; + reg = <0x1630>; + }; + + timer10_gfclk_mux: timer10_gfclk_mux { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&sys_clkin>, <&sys_32k_ck>; + ti,bit-shift = <24>; + reg = <0x1028>; + }; + + timer11_gfclk_mux: timer11_gfclk_mux { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&sys_clkin>, <&sys_32k_ck>; + ti,bit-shift = <24>; + reg = <0x1030>; + }; + + timer2_gfclk_mux: timer2_gfclk_mux { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&sys_clkin>, <&sys_32k_ck>; + ti,bit-shift = <24>; + reg = <0x1038>; + }; + + timer3_gfclk_mux: timer3_gfclk_mux { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&sys_clkin>, <&sys_32k_ck>; + ti,bit-shift = <24>; + reg = <0x1040>; + }; + + timer4_gfclk_mux: timer4_gfclk_mux { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&sys_clkin>, <&sys_32k_ck>; + ti,bit-shift = <24>; + reg = <0x1048>; + }; + + timer9_gfclk_mux: timer9_gfclk_mux { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&sys_clkin>, <&sys_32k_ck>; + ti,bit-shift = <24>; + reg = <0x1050>; + }; +}; + +&cm_core_clockdomains { + l3init_clkdm: l3init_clkdm { + compatible = "ti,clockdomain"; + clocks = <&dpll_usb_ck>; + }; +}; + +&scrm_clocks { + auxclk0_src_gate_ck: auxclk0_src_gate_ck { + #clock-cells = <0>; + compatible = "ti,composite-no-wait-gate-clock"; + clocks = <&dpll_core_m3x2_ck>; + ti,bit-shift = <8>; + reg = <0x0310>; + }; + + auxclk0_src_mux_ck: auxclk0_src_mux_ck { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; + ti,bit-shift = <1>; + reg = <0x0310>; + }; + + auxclk0_src_ck: auxclk0_src_ck { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&auxclk0_src_gate_ck>, <&auxclk0_src_mux_ck>; + }; + + auxclk0_ck: auxclk0_ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&auxclk0_src_ck>; + ti,bit-shift = <16>; + ti,max-div = <16>; + reg = <0x0310>; + }; + + auxclk1_src_gate_ck: auxclk1_src_gate_ck { + #clock-cells = <0>; + compatible = "ti,composite-no-wait-gate-clock"; + clocks = <&dpll_core_m3x2_ck>; + ti,bit-shift = <8>; + reg = <0x0314>; + }; + + auxclk1_src_mux_ck: auxclk1_src_mux_ck { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; + ti,bit-shift = <1>; + reg = <0x0314>; + }; + + auxclk1_src_ck: auxclk1_src_ck { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&auxclk1_src_gate_ck>, <&auxclk1_src_mux_ck>; + }; + + auxclk1_ck: auxclk1_ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&auxclk1_src_ck>; + ti,bit-shift = <16>; + ti,max-div = <16>; + reg = <0x0314>; + }; + + auxclk2_src_gate_ck: auxclk2_src_gate_ck { + #clock-cells = <0>; + compatible = "ti,composite-no-wait-gate-clock"; + clocks = <&dpll_core_m3x2_ck>; + ti,bit-shift = <8>; + reg = <0x0318>; + }; + + auxclk2_src_mux_ck: auxclk2_src_mux_ck { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; + ti,bit-shift = <1>; + reg = <0x0318>; + }; + + auxclk2_src_ck: auxclk2_src_ck { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&auxclk2_src_gate_ck>, <&auxclk2_src_mux_ck>; + }; + + auxclk2_ck: auxclk2_ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&auxclk2_src_ck>; + ti,bit-shift = <16>; + ti,max-div = <16>; + reg = <0x0318>; + }; + + auxclk3_src_gate_ck: auxclk3_src_gate_ck { + #clock-cells = <0>; + compatible = "ti,composite-no-wait-gate-clock"; + clocks = <&dpll_core_m3x2_ck>; + ti,bit-shift = <8>; + reg = <0x031c>; + }; + + auxclk3_src_mux_ck: auxclk3_src_mux_ck { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; + ti,bit-shift = <1>; + reg = <0x031c>; + }; + + auxclk3_src_ck: auxclk3_src_ck { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&auxclk3_src_gate_ck>, <&auxclk3_src_mux_ck>; + }; + + auxclk3_ck: auxclk3_ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&auxclk3_src_ck>; + ti,bit-shift = <16>; + ti,max-div = <16>; + reg = <0x031c>; + }; + + auxclk4_src_gate_ck: auxclk4_src_gate_ck { + #clock-cells = <0>; + compatible = "ti,composite-no-wait-gate-clock"; + clocks = <&dpll_core_m3x2_ck>; + ti,bit-shift = <8>; + reg = <0x0320>; + }; + + auxclk4_src_mux_ck: auxclk4_src_mux_ck { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; + ti,bit-shift = <1>; + reg = <0x0320>; + }; + + auxclk4_src_ck: auxclk4_src_ck { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&auxclk4_src_gate_ck>, <&auxclk4_src_mux_ck>; + }; + + auxclk4_ck: auxclk4_ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&auxclk4_src_ck>; + ti,bit-shift = <16>; + ti,max-div = <16>; + reg = <0x0320>; + }; + + auxclkreq0_ck: auxclkreq0_ck { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>; + ti,bit-shift = <2>; + reg = <0x0210>; + }; + + auxclkreq1_ck: auxclkreq1_ck { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>; + ti,bit-shift = <2>; + reg = <0x0214>; + }; + + auxclkreq2_ck: auxclkreq2_ck { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>; + ti,bit-shift = <2>; + reg = <0x0218>; + }; + + auxclkreq3_ck: auxclkreq3_ck { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>; + ti,bit-shift = <2>; + reg = <0x021c>; + }; +}; -- cgit v1.2.3-59-g8ed1b From ee6c750761dc125cb4390b11551f221006c26224 Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Thu, 18 Jul 2013 17:18:33 +0300 Subject: ARM: dts: dra7 clock data This patch creates a unique node for each clock in the DRA7 power, reset and clock manager (PRCM). TODO: apll_pcie clock node is still a dummy in this version, and proper support for the APLL should be added. Signed-off-by: Tero Kristo Acked-by: Tony Lindgren Signed-off-by: Mike Turquette --- arch/arm/boot/dts/dra7.dtsi | 41 + arch/arm/boot/dts/dra7xx-clocks.dtsi | 1985 ++++++++++++++++++++++++++++++++++ 2 files changed, 2026 insertions(+) create mode 100644 arch/arm/boot/dts/dra7xx-clocks.dtsi diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index d0df4c4e8b0a..1fd75aa4639d 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -104,6 +104,45 @@ interrupts = , ; + prm: prm@4ae06000 { + compatible = "ti,dra7-prm"; + reg = <0x4ae06000 0x3000>; + + prm_clocks: clocks { + #address-cells = <1>; + #size-cells = <0>; + }; + + prm_clockdomains: clockdomains { + }; + }; + + cm_core_aon: cm_core_aon@4a005000 { + compatible = "ti,dra7-cm-core-aon"; + reg = <0x4a005000 0x2000>; + + cm_core_aon_clocks: clocks { + #address-cells = <1>; + #size-cells = <0>; + }; + + cm_core_aon_clockdomains: clockdomains { + }; + }; + + cm_core: cm_core@4a008000 { + compatible = "ti,dra7-cm-core"; + reg = <0x4a008000 0x3000>; + + cm_core_clocks: clocks { + #address-cells = <1>; + #size-cells = <0>; + }; + + cm_core_clockdomains: clockdomains { + }; + }; + counter32k: counter@4ae04000 { compatible = "ti,omap-counter32k"; reg = <0x4ae04000 0x40>; @@ -584,3 +623,5 @@ }; }; }; + +/include/ "dra7xx-clocks.dtsi" diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi new file mode 100644 index 000000000000..32df8470b4a8 --- /dev/null +++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi @@ -0,0 +1,1985 @@ +/* + * Device Tree Source for DRA7xx clock data + * + * Copyright (C) 2013 Texas Instruments, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +&cm_core_aon_clocks { + atl_clkin0_ck: atl_clkin0_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0>; + }; + + atl_clkin1_ck: atl_clkin1_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0>; + }; + + atl_clkin2_ck: atl_clkin2_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0>; + }; + + atlclkin3_ck: atlclkin3_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0>; + }; + + hdmi_clkin_ck: hdmi_clkin_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0>; + }; + + mlb_clkin_ck: mlb_clkin_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0>; + }; + + mlbp_clkin_ck: mlbp_clkin_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0>; + }; + + pciesref_acs_clk_ck: pciesref_acs_clk_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <100000000>; + }; + + ref_clkin0_ck: ref_clkin0_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0>; + }; + + ref_clkin1_ck: ref_clkin1_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0>; + }; + + ref_clkin2_ck: ref_clkin2_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0>; + }; + + ref_clkin3_ck: ref_clkin3_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0>; + }; + + rmii_clk_ck: rmii_clk_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0>; + }; + + sdvenc_clkin_ck: sdvenc_clkin_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0>; + }; + + secure_32k_clk_src_ck: secure_32k_clk_src_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + }; + + sys_32k_ck: sys_32k_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + }; + + virt_12000000_ck: virt_12000000_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <12000000>; + }; + + virt_13000000_ck: virt_13000000_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <13000000>; + }; + + virt_16800000_ck: virt_16800000_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <16800000>; + }; + + virt_19200000_ck: virt_19200000_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <19200000>; + }; + + virt_20000000_ck: virt_20000000_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <20000000>; + }; + + virt_26000000_ck: virt_26000000_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <26000000>; + }; + + virt_27000000_ck: virt_27000000_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <27000000>; + }; + + virt_38400000_ck: virt_38400000_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <38400000>; + }; + + sys_clkin2: sys_clkin2 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <22579200>; + }; + + usb_otg_clkin_ck: usb_otg_clkin_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0>; + }; + + video1_clkin_ck: video1_clkin_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0>; + }; + + video1_m2_clkin_ck: video1_m2_clkin_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0>; + }; + + video2_clkin_ck: video2_clkin_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0>; + }; + + video2_m2_clkin_ck: video2_m2_clkin_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0>; + }; + + dpll_abe_ck: dpll_abe_ck { + #clock-cells = <0>; + compatible = "ti,omap4-dpll-m4xen-clock"; + clocks = <&abe_dpll_clk_mux>, <&abe_dpll_bypass_clk_mux>; + reg = <0x01e0>, <0x01e4>, <0x01ec>, <0x01e8>; + }; + + dpll_abe_x2_ck: dpll_abe_x2_ck { + #clock-cells = <0>; + compatible = "ti,omap4-dpll-x2-clock"; + clocks = <&dpll_abe_ck>; + }; + + dpll_abe_m2x2_ck: dpll_abe_m2x2_ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll_abe_x2_ck>; + ti,max-div = <31>; + ti,autoidle-shift = <8>; + reg = <0x01f0>; + ti,index-starts-at-one; + ti,invert-autoidle-bit; + }; + + abe_clk: abe_clk { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll_abe_m2x2_ck>; + ti,max-div = <4>; + reg = <0x0108>; + ti,index-power-of-two; + }; + + dpll_abe_m2_ck: dpll_abe_m2_ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll_abe_ck>; + ti,max-div = <31>; + ti,autoidle-shift = <8>; + reg = <0x01f0>; + ti,index-starts-at-one; + ti,invert-autoidle-bit; + }; + + dpll_abe_m3x2_ck: dpll_abe_m3x2_ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll_abe_x2_ck>; + ti,max-div = <31>; + ti,autoidle-shift = <8>; + reg = <0x01f4>; + ti,index-starts-at-one; + ti,invert-autoidle-bit; + }; + + dpll_core_ck: dpll_core_ck { + #clock-cells = <0>; + compatible = "ti,omap4-dpll-core-clock"; + clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>; + reg = <0x0120>, <0x0124>, <0x012c>, <0x0128>; + }; + + dpll_core_x2_ck: dpll_core_x2_ck { + #clock-cells = <0>; + compatible = "ti,omap4-dpll-x2-clock"; + clocks = <&dpll_core_ck>; + }; + + dpll_core_h12x2_ck: dpll_core_h12x2_ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll_core_x2_ck>; + ti,max-div = <63>; + ti,autoidle-shift = <8>; + reg = <0x013c>; + ti,index-starts-at-one; + ti,invert-autoidle-bit; + }; + + mpu_dpll_hs_clk_div: mpu_dpll_hs_clk_div { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll_core_h12x2_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + dpll_mpu_ck: dpll_mpu_ck { + #clock-cells = <0>; + compatible = "ti,omap4-dpll-clock"; + clocks = <&sys_clkin1>, <&mpu_dpll_hs_clk_div>; + reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>; + }; + + dpll_mpu_m2_ck: dpll_mpu_m2_ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll_mpu_ck>; + ti,max-div = <31>; + ti,autoidle-shift = <8>; + reg = <0x0170>; + ti,index-starts-at-one; + ti,invert-autoidle-bit; + }; + + mpu_dclk_div: mpu_dclk_div { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll_mpu_m2_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + dsp_dpll_hs_clk_div: dsp_dpll_hs_clk_div { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll_core_h12x2_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + dpll_dsp_ck: dpll_dsp_ck { + #clock-cells = <0>; + compatible = "ti,omap4-dpll-clock"; + clocks = <&sys_clkin1>, <&dsp_dpll_hs_clk_div>; + reg = <0x0234>, <0x0238>, <0x0240>, <0x023c>; + }; + + dpll_dsp_m2_ck: dpll_dsp_m2_ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll_dsp_ck>; + ti,max-div = <31>; + ti,autoidle-shift = <8>; + reg = <0x0244>; + ti,index-starts-at-one; + ti,invert-autoidle-bit; + }; + + iva_dpll_hs_clk_div: iva_dpll_hs_clk_div { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll_core_h12x2_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + dpll_iva_ck: dpll_iva_ck { + #clock-cells = <0>; + compatible = "ti,omap4-dpll-clock"; + clocks = <&sys_clkin1>, <&iva_dpll_hs_clk_div>; + reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>; + }; + + dpll_iva_m2_ck: dpll_iva_m2_ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll_iva_ck>; + ti,max-div = <31>; + ti,autoidle-shift = <8>; + reg = <0x01b0>; + ti,index-starts-at-one; + ti,invert-autoidle-bit; + }; + + iva_dclk: iva_dclk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll_iva_m2_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + dpll_gpu_ck: dpll_gpu_ck { + #clock-cells = <0>; + compatible = "ti,omap4-dpll-clock"; + clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>; + reg = <0x02d8>, <0x02dc>, <0x02e4>, <0x02e0>; + }; + + dpll_gpu_m2_ck: dpll_gpu_m2_ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll_gpu_ck>; + ti,max-div = <31>; + ti,autoidle-shift = <8>; + reg = <0x02e8>; + ti,index-starts-at-one; + ti,invert-autoidle-bit; + }; + + dpll_core_m2_ck: dpll_core_m2_ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll_core_ck>; + ti,max-div = <31>; + ti,autoidle-shift = <8>; + reg = <0x0130>; + ti,index-starts-at-one; + ti,invert-autoidle-bit; + }; + + core_dpll_out_dclk_div: core_dpll_out_dclk_div { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll_core_m2_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + dpll_ddr_ck: dpll_ddr_ck { + #clock-cells = <0>; + compatible = "ti,omap4-dpll-clock"; + clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>; + reg = <0x0210>, <0x0214>, <0x021c>, <0x0218>; + }; + + dpll_ddr_m2_ck: dpll_ddr_m2_ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll_ddr_ck>; + ti,max-div = <31>; + ti,autoidle-shift = <8>; + reg = <0x0220>; + ti,index-starts-at-one; + ti,invert-autoidle-bit; + }; + + dpll_gmac_ck: dpll_gmac_ck { + #clock-cells = <0>; + compatible = "ti,omap4-dpll-clock"; + clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>; + reg = <0x02a8>, <0x02ac>, <0x02b4>, <0x02b0>; + }; + + dpll_gmac_m2_ck: dpll_gmac_m2_ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll_gmac_ck>; + ti,max-div = <31>; + ti,autoidle-shift = <8>; + reg = <0x02b8>; + ti,index-starts-at-one; + ti,invert-autoidle-bit; + }; + + video2_dclk_div: video2_dclk_div { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&video2_m2_clkin_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + video1_dclk_div: video1_dclk_div { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&video1_m2_clkin_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + hdmi_dclk_div: hdmi_dclk_div { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&hdmi_clkin_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + per_dpll_hs_clk_div: per_dpll_hs_clk_div { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll_abe_m3x2_ck>; + clock-mult = <1>; + clock-div = <2>; + }; + + usb_dpll_hs_clk_div: usb_dpll_hs_clk_div { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll_abe_m3x2_ck>; + clock-mult = <1>; + clock-div = <3>; + }; + + eve_dpll_hs_clk_div: eve_dpll_hs_clk_div { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll_core_h12x2_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + dpll_eve_ck: dpll_eve_ck { + #clock-cells = <0>; + compatible = "ti,omap4-dpll-clock"; + clocks = <&sys_clkin1>, <&eve_dpll_hs_clk_div>; + reg = <0x0284>, <0x0288>, <0x0290>, <0x028c>; + }; + + dpll_eve_m2_ck: dpll_eve_m2_ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll_eve_ck>; + ti,max-div = <31>; + ti,autoidle-shift = <8>; + reg = <0x0294>; + ti,index-starts-at-one; + ti,invert-autoidle-bit; + }; + + eve_dclk_div: eve_dclk_div { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll_eve_m2_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + dpll_core_h13x2_ck: dpll_core_h13x2_ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll_core_x2_ck>; + ti,max-div = <63>; + ti,autoidle-shift = <8>; + reg = <0x0140>; + ti,index-starts-at-one; + ti,invert-autoidle-bit; + }; + + dpll_core_h14x2_ck: dpll_core_h14x2_ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll_core_x2_ck>; + ti,max-div = <63>; + ti,autoidle-shift = <8>; + reg = <0x0144>; + ti,index-starts-at-one; + ti,invert-autoidle-bit; + }; + + dpll_core_h22x2_ck: dpll_core_h22x2_ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll_core_x2_ck>; + ti,max-div = <63>; + ti,autoidle-shift = <8>; + reg = <0x0154>; + ti,index-starts-at-one; + ti,invert-autoidle-bit; + }; + + dpll_core_h23x2_ck: dpll_core_h23x2_ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll_core_x2_ck>; + ti,max-div = <63>; + ti,autoidle-shift = <8>; + reg = <0x0158>; + ti,index-starts-at-one; + ti,invert-autoidle-bit; + }; + + dpll_core_h24x2_ck: dpll_core_h24x2_ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll_core_x2_ck>; + ti,max-div = <63>; + ti,autoidle-shift = <8>; + reg = <0x015c>; + ti,index-starts-at-one; + ti,invert-autoidle-bit; + }; + + dpll_ddr_x2_ck: dpll_ddr_x2_ck { + #clock-cells = <0>; + compatible = "ti,omap4-dpll-x2-clock"; + clocks = <&dpll_ddr_ck>; + }; + + dpll_ddr_h11x2_ck: dpll_ddr_h11x2_ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll_ddr_x2_ck>; + ti,max-div = <63>; + ti,autoidle-shift = <8>; + reg = <0x0228>; + ti,index-starts-at-one; + ti,invert-autoidle-bit; + }; + + dpll_dsp_x2_ck: dpll_dsp_x2_ck { + #clock-cells = <0>; + compatible = "ti,omap4-dpll-x2-clock"; + clocks = <&dpll_dsp_ck>; + }; + + dpll_dsp_m3x2_ck: dpll_dsp_m3x2_ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll_dsp_x2_ck>; + ti,max-div = <31>; + ti,autoidle-shift = <8>; + reg = <0x0248>; + ti,index-starts-at-one; + ti,invert-autoidle-bit; + }; + + dpll_gmac_x2_ck: dpll_gmac_x2_ck { + #clock-cells = <0>; + compatible = "ti,omap4-dpll-x2-clock"; + clocks = <&dpll_gmac_ck>; + }; + + dpll_gmac_h11x2_ck: dpll_gmac_h11x2_ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll_gmac_x2_ck>; + ti,max-div = <63>; + ti,autoidle-shift = <8>; + reg = <0x02c0>; + ti,index-starts-at-one; + ti,invert-autoidle-bit; + }; + + dpll_gmac_h12x2_ck: dpll_gmac_h12x2_ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll_gmac_x2_ck>; + ti,max-div = <63>; + ti,autoidle-shift = <8>; + reg = <0x02c4>; + ti,index-starts-at-one; + ti,invert-autoidle-bit; + }; + + dpll_gmac_h13x2_ck: dpll_gmac_h13x2_ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll_gmac_x2_ck>; + ti,max-div = <63>; + ti,autoidle-shift = <8>; + reg = <0x02c8>; + ti,index-starts-at-one; + ti,invert-autoidle-bit; + }; + + dpll_gmac_m3x2_ck: dpll_gmac_m3x2_ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll_gmac_x2_ck>; + ti,max-div = <31>; + ti,autoidle-shift = <8>; + reg = <0x02bc>; + ti,index-starts-at-one; + ti,invert-autoidle-bit; + }; + + gmii_m_clk_div: gmii_m_clk_div { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll_gmac_h11x2_ck>; + clock-mult = <1>; + clock-div = <2>; + }; + + hdmi_clk2_div: hdmi_clk2_div { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&hdmi_clkin_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + hdmi_div_clk: hdmi_div_clk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&hdmi_clkin_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + l3_iclk_div: l3_iclk_div { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll_core_h12x2_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + l4_root_clk_div: l4_root_clk_div { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&l3_iclk_div>; + clock-mult = <1>; + clock-div = <1>; + }; + + video1_clk2_div: video1_clk2_div { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&video1_clkin_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + video1_div_clk: video1_div_clk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&video1_clkin_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + video2_clk2_div: video2_clk2_div { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&video2_clkin_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + video2_div_clk: video2_div_clk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&video2_clkin_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + ipu1_gfclk_mux: ipu1_gfclk_mux { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&dpll_abe_m2x2_ck>, <&dpll_core_h22x2_ck>; + ti,bit-shift = <24>; + reg = <0x0520>; + }; + + mcasp1_ahclkr_mux: mcasp1_ahclkr_mux { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>; + ti,bit-shift = <28>; + reg = <0x0550>; + }; + + mcasp1_ahclkx_mux: mcasp1_ahclkx_mux { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>; + ti,bit-shift = <24>; + reg = <0x0550>; + }; + + mcasp1_aux_gfclk_mux: mcasp1_aux_gfclk_mux { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>; + ti,bit-shift = <22>; + reg = <0x0550>; + }; + + timer5_gfclk_mux: timer5_gfclk_mux { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>; + ti,bit-shift = <24>; + reg = <0x0558>; + }; + + timer6_gfclk_mux: timer6_gfclk_mux { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>; + ti,bit-shift = <24>; + reg = <0x0560>; + }; + + timer7_gfclk_mux: timer7_gfclk_mux { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>; + ti,bit-shift = <24>; + reg = <0x0568>; + }; + + timer8_gfclk_mux: timer8_gfclk_mux { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>; + ti,bit-shift = <24>; + reg = <0x0570>; + }; + + uart6_gfclk_mux: uart6_gfclk_mux { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>; + ti,bit-shift = <24>; + reg = <0x0580>; + }; + + dummy_ck: dummy_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0>; + }; +}; +&prm_clocks { + sys_clkin1: sys_clkin1 { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&virt_12000000_ck>, <&virt_20000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>; + reg = <0x0110>; + ti,index-starts-at-one; + }; + + abe_dpll_sys_clk_mux: abe_dpll_sys_clk_mux { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&sys_clkin1>, <&sys_clkin2>; + reg = <0x0118>; + }; + + abe_dpll_bypass_clk_mux: abe_dpll_bypass_clk_mux { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&abe_dpll_sys_clk_mux>, <&sys_32k_ck>; + reg = <0x0114>; + }; + + abe_dpll_clk_mux: abe_dpll_clk_mux { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&abe_dpll_sys_clk_mux>, <&sys_32k_ck>; + reg = <0x010c>; + }; + + abe_24m_fclk: abe_24m_fclk { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll_abe_m2x2_ck>; + reg = <0x011c>; + ti,dividers = <8>, <16>; + }; + + aess_fclk: aess_fclk { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&abe_clk>; + reg = <0x0178>; + ti,max-div = <2>; + }; + + abe_giclk_div: abe_giclk_div { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&aess_fclk>; + reg = <0x0174>; + ti,max-div = <2>; + }; + + abe_lp_clk_div: abe_lp_clk_div { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll_abe_m2x2_ck>; + reg = <0x01d8>; + ti,dividers = <16>, <32>; + }; + + abe_sys_clk_div: abe_sys_clk_div { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&sys_clkin1>; + reg = <0x0120>; + ti,max-div = <2>; + }; + + adc_gfclk_mux: adc_gfclk_mux { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&sys_clkin1>, <&sys_clkin2>, <&sys_32k_ck>; + reg = <0x01dc>; + }; + + sys_clk1_dclk_div: sys_clk1_dclk_div { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&sys_clkin1>; + ti,max-div = <64>; + reg = <0x01c8>; + ti,index-power-of-two; + }; + + sys_clk2_dclk_div: sys_clk2_dclk_div { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&sys_clkin2>; + ti,max-div = <64>; + reg = <0x01cc>; + ti,index-power-of-two; + }; + + per_abe_x1_dclk_div: per_abe_x1_dclk_div { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll_abe_m2_ck>; + ti,max-div = <64>; + reg = <0x01bc>; + ti,index-power-of-two; + }; + + dsp_gclk_div: dsp_gclk_div { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll_dsp_m2_ck>; + ti,max-div = <64>; + reg = <0x018c>; + ti,index-power-of-two; + }; + + gpu_dclk: gpu_dclk { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll_gpu_m2_ck>; + ti,max-div = <64>; + reg = <0x01a0>; + ti,index-power-of-two; + }; + + emif_phy_dclk_div: emif_phy_dclk_div { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll_ddr_m2_ck>; + ti,max-div = <64>; + reg = <0x0190>; + ti,index-power-of-two; + }; + + gmac_250m_dclk_div: gmac_250m_dclk_div { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll_gmac_m2_ck>; + ti,max-div = <64>; + reg = <0x019c>; + ti,index-power-of-two; + }; + + l3init_480m_dclk_div: l3init_480m_dclk_div { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll_usb_m2_ck>; + ti,max-div = <64>; + reg = <0x01ac>; + ti,index-power-of-two; + }; + + usb_otg_dclk_div: usb_otg_dclk_div { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&usb_otg_clkin_ck>; + ti,max-div = <64>; + reg = <0x0184>; + ti,index-power-of-two; + }; + + sata_dclk_div: sata_dclk_div { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&sys_clkin1>; + ti,max-div = <64>; + reg = <0x01c0>; + ti,index-power-of-two; + }; + + pcie2_dclk_div: pcie2_dclk_div { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll_pcie_ref_m2_ck>; + ti,max-div = <64>; + reg = <0x01b8>; + ti,index-power-of-two; + }; + + pcie_dclk_div: pcie_dclk_div { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&apll_pcie_m2_ck>; + ti,max-div = <64>; + reg = <0x01b4>; + ti,index-power-of-two; + }; + + emu_dclk_div: emu_dclk_div { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&sys_clkin1>; + ti,max-div = <64>; + reg = <0x0194>; + ti,index-power-of-two; + }; + + secure_32k_dclk_div: secure_32k_dclk_div { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&secure_32k_clk_src_ck>; + ti,max-div = <64>; + reg = <0x01c4>; + ti,index-power-of-two; + }; + + clkoutmux0_clk_mux: clkoutmux0_clk_mux { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>; + reg = <0x0158>; + }; + + clkoutmux1_clk_mux: clkoutmux1_clk_mux { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>; + reg = <0x015c>; + }; + + clkoutmux2_clk_mux: clkoutmux2_clk_mux { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>; + reg = <0x0160>; + }; + + custefuse_sys_gfclk_div: custefuse_sys_gfclk_div { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&sys_clkin1>; + clock-mult = <1>; + clock-div = <2>; + }; + + eve_clk: eve_clk { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&dpll_eve_m2_ck>, <&dpll_dsp_m3x2_ck>; + reg = <0x0180>; + }; + + hdmi_dpll_clk_mux: hdmi_dpll_clk_mux { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&sys_clkin1>, <&sys_clkin2>; + reg = <0x01a4>; + }; + + mlb_clk: mlb_clk { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&mlb_clkin_ck>; + ti,max-div = <64>; + reg = <0x0134>; + ti,index-power-of-two; + }; + + mlbp_clk: mlbp_clk { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&mlbp_clkin_ck>; + ti,max-div = <64>; + reg = <0x0130>; + ti,index-power-of-two; + }; + + per_abe_x1_gfclk2_div: per_abe_x1_gfclk2_div { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll_abe_m2_ck>; + ti,max-div = <64>; + reg = <0x0138>; + ti,index-power-of-two; + }; + + timer_sys_clk_div: timer_sys_clk_div { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&sys_clkin1>; + reg = <0x0144>; + ti,max-div = <2>; + }; + + video1_dpll_clk_mux: video1_dpll_clk_mux { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&sys_clkin1>, <&sys_clkin2>; + reg = <0x01d0>; + }; + + video2_dpll_clk_mux: video2_dpll_clk_mux { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&sys_clkin1>, <&sys_clkin2>; + reg = <0x01d4>; + }; + + wkupaon_iclk_mux: wkupaon_iclk_mux { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&sys_clkin1>, <&abe_lp_clk_div>; + reg = <0x0108>; + }; + + gpio1_dbclk: gpio1_dbclk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&sys_32k_ck>; + ti,bit-shift = <8>; + reg = <0x1838>; + }; + + dcan1_sys_clk_mux: dcan1_sys_clk_mux { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&sys_clkin1>, <&sys_clkin2>; + ti,bit-shift = <24>; + reg = <0x1888>; + }; + + timer1_gfclk_mux: timer1_gfclk_mux { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>; + ti,bit-shift = <24>; + reg = <0x1840>; + }; + + uart10_gfclk_mux: uart10_gfclk_mux { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>; + ti,bit-shift = <24>; + reg = <0x1880>; + }; +}; +&cm_core_clocks { + dpll_pcie_ref_ck: dpll_pcie_ref_ck { + #clock-cells = <0>; + compatible = "ti,omap4-dpll-clock"; + clocks = <&sys_clkin1>, <&sys_clkin1>; + reg = <0x0200>, <0x0204>, <0x020c>, <0x0208>; + }; + + dpll_pcie_ref_m2ldo_ck: dpll_pcie_ref_m2ldo_ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll_pcie_ref_ck>; + ti,max-div = <31>; + ti,autoidle-shift = <8>; + reg = <0x0210>; + ti,index-starts-at-one; + ti,invert-autoidle-bit; + }; + + apll_pcie_ck: apll_pcie_ck { + #clock-cells = <0>; + compatible = "ti,omap4-dpll-clock"; + clocks = <&dpll_pcie_ref_ck>, <&dpll_pcie_ref_ck>; + reg = <0x0200>, <0x0204>, <0x020c>, <0x0208>; + }; + + apll_pcie_clkvcoldo: apll_pcie_clkvcoldo { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&apll_pcie_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + apll_pcie_clkvcoldo_div: apll_pcie_clkvcoldo_div { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&apll_pcie_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + apll_pcie_m2_ck: apll_pcie_m2_ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&apll_pcie_ck>; + ti,max-div = <127>; + ti,autoidle-shift = <8>; + reg = <0x0224>; + ti,index-starts-at-one; + ti,invert-autoidle-bit; + }; + + dpll_per_ck: dpll_per_ck { + #clock-cells = <0>; + compatible = "ti,omap4-dpll-clock"; + clocks = <&sys_clkin1>, <&per_dpll_hs_clk_div>; + reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>; + }; + + dpll_per_m2_ck: dpll_per_m2_ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll_per_ck>; + ti,max-div = <31>; + ti,autoidle-shift = <8>; + reg = <0x0150>; + ti,index-starts-at-one; + ti,invert-autoidle-bit; + }; + + func_96m_aon_dclk_div: func_96m_aon_dclk_div { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll_per_m2_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + dpll_usb_ck: dpll_usb_ck { + #clock-cells = <0>; + compatible = "ti,omap4-dpll-j-type-clock"; + clocks = <&sys_clkin1>, <&usb_dpll_hs_clk_div>; + reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>; + }; + + dpll_usb_m2_ck: dpll_usb_m2_ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll_usb_ck>; + ti,max-div = <127>; + ti,autoidle-shift = <8>; + reg = <0x0190>; + ti,index-starts-at-one; + ti,invert-autoidle-bit; + }; + + dpll_pcie_ref_m2_ck: dpll_pcie_ref_m2_ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll_pcie_ref_ck>; + ti,max-div = <127>; + ti,autoidle-shift = <8>; + reg = <0x0210>; + ti,index-starts-at-one; + ti,invert-autoidle-bit; + }; + + dpll_per_x2_ck: dpll_per_x2_ck { + #clock-cells = <0>; + compatible = "ti,omap4-dpll-x2-clock"; + clocks = <&dpll_per_ck>; + }; + + dpll_per_h11x2_ck: dpll_per_h11x2_ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll_per_x2_ck>; + ti,max-div = <63>; + ti,autoidle-shift = <8>; + reg = <0x0158>; + ti,index-starts-at-one; + ti,invert-autoidle-bit; + }; + + dpll_per_h12x2_ck: dpll_per_h12x2_ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll_per_x2_ck>; + ti,max-div = <63>; + ti,autoidle-shift = <8>; + reg = <0x015c>; + ti,index-starts-at-one; + ti,invert-autoidle-bit; + }; + + dpll_per_h13x2_ck: dpll_per_h13x2_ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll_per_x2_ck>; + ti,max-div = <63>; + ti,autoidle-shift = <8>; + reg = <0x0160>; + ti,index-starts-at-one; + ti,invert-autoidle-bit; + }; + + dpll_per_h14x2_ck: dpll_per_h14x2_ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll_per_x2_ck>; + ti,max-div = <63>; + ti,autoidle-shift = <8>; + reg = <0x0164>; + ti,index-starts-at-one; + ti,invert-autoidle-bit; + }; + + dpll_per_m2x2_ck: dpll_per_m2x2_ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll_per_x2_ck>; + ti,max-div = <31>; + ti,autoidle-shift = <8>; + reg = <0x0150>; + ti,index-starts-at-one; + ti,invert-autoidle-bit; + }; + + dpll_usb_clkdcoldo: dpll_usb_clkdcoldo { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll_usb_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + func_128m_clk: func_128m_clk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll_per_h11x2_ck>; + clock-mult = <1>; + clock-div = <2>; + }; + + func_12m_fclk: func_12m_fclk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll_per_m2x2_ck>; + clock-mult = <1>; + clock-div = <16>; + }; + + func_24m_clk: func_24m_clk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll_per_m2_ck>; + clock-mult = <1>; + clock-div = <4>; + }; + + func_48m_fclk: func_48m_fclk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll_per_m2x2_ck>; + clock-mult = <1>; + clock-div = <4>; + }; + + func_96m_fclk: func_96m_fclk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll_per_m2x2_ck>; + clock-mult = <1>; + clock-div = <2>; + }; + + l3init_60m_fclk: l3init_60m_fclk { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll_usb_m2_ck>; + reg = <0x0104>; + ti,dividers = <1>, <8>; + }; + + dss_32khz_clk: dss_32khz_clk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&sys_32k_ck>; + ti,bit-shift = <11>; + reg = <0x1120>; + }; + + dss_48mhz_clk: dss_48mhz_clk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&func_48m_fclk>; + ti,bit-shift = <9>; + reg = <0x1120>; + }; + + dss_dss_clk: dss_dss_clk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&dpll_per_h12x2_ck>; + ti,bit-shift = <8>; + reg = <0x1120>; + }; + + dss_hdmi_clk: dss_hdmi_clk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&hdmi_dpll_clk_mux>; + ti,bit-shift = <10>; + reg = <0x1120>; + }; + + dss_video1_clk: dss_video1_clk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&video1_dpll_clk_mux>; + ti,bit-shift = <12>; + reg = <0x1120>; + }; + + dss_video2_clk: dss_video2_clk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&video2_dpll_clk_mux>; + ti,bit-shift = <13>; + reg = <0x1120>; + }; + + gpio2_dbclk: gpio2_dbclk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&sys_32k_ck>; + ti,bit-shift = <8>; + reg = <0x1760>; + }; + + gpio3_dbclk: gpio3_dbclk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&sys_32k_ck>; + ti,bit-shift = <8>; + reg = <0x1768>; + }; + + gpio4_dbclk: gpio4_dbclk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&sys_32k_ck>; + ti,bit-shift = <8>; + reg = <0x1770>; + }; + + gpio5_dbclk: gpio5_dbclk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&sys_32k_ck>; + ti,bit-shift = <8>; + reg = <0x1778>; + }; + + gpio6_dbclk: gpio6_dbclk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&sys_32k_ck>; + ti,bit-shift = <8>; + reg = <0x1780>; + }; + + gpio7_dbclk: gpio7_dbclk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&sys_32k_ck>; + ti,bit-shift = <8>; + reg = <0x1810>; + }; + + gpio8_dbclk: gpio8_dbclk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&sys_32k_ck>; + ti,bit-shift = <8>; + reg = <0x1818>; + }; + + mmc1_clk32k: mmc1_clk32k { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&sys_32k_ck>; + ti,bit-shift = <8>; + reg = <0x1328>; + }; + + mmc2_clk32k: mmc2_clk32k { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&sys_32k_ck>; + ti,bit-shift = <8>; + reg = <0x1330>; + }; + + mmc3_clk32k: mmc3_clk32k { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&sys_32k_ck>; + ti,bit-shift = <8>; + reg = <0x1820>; + }; + + mmc4_clk32k: mmc4_clk32k { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&sys_32k_ck>; + ti,bit-shift = <8>; + reg = <0x1828>; + }; + + sata_ref_clk: sata_ref_clk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&sys_clkin1>; + ti,bit-shift = <8>; + reg = <0x1388>; + }; + + usb_otg_ss1_refclk960m: usb_otg_ss1_refclk960m { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&dpll_usb_clkdcoldo>; + ti,bit-shift = <8>; + reg = <0x13f0>; + }; + + usb_otg_ss2_refclk960m: usb_otg_ss2_refclk960m { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&dpll_usb_clkdcoldo>; + ti,bit-shift = <8>; + reg = <0x1340>; + }; + + usb_phy1_always_on_clk32k: usb_phy1_always_on_clk32k { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&sys_32k_ck>; + ti,bit-shift = <8>; + reg = <0x0640>; + }; + + usb_phy2_always_on_clk32k: usb_phy2_always_on_clk32k { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&sys_32k_ck>; + ti,bit-shift = <8>; + reg = <0x0688>; + }; + + usb_phy3_always_on_clk32k: usb_phy3_always_on_clk32k { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&sys_32k_ck>; + ti,bit-shift = <8>; + reg = <0x0698>; + }; + + atl_dpll_clk_mux: atl_dpll_clk_mux { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&sys_32k_ck>, <&video1_clkin_ck>, <&video2_clkin_ck>, <&hdmi_clkin_ck>; + ti,bit-shift = <24>; + reg = <0x0c00>; + }; + + atl_gfclk_mux: atl_gfclk_mux { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&l3_iclk_div>, <&dpll_abe_m2_ck>, <&atl_dpll_clk_mux>; + ti,bit-shift = <26>; + reg = <0x0c00>; + }; + + gmac_gmii_ref_clk_div: gmac_gmii_ref_clk_div { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll_gmac_m2_ck>; + ti,bit-shift = <24>; + reg = <0x13d0>; + ti,dividers = <2>; + }; + + gmac_rft_clk_mux: gmac_rft_clk_mux { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&video1_clkin_ck>, <&video2_clkin_ck>, <&dpll_abe_m2_ck>, <&hdmi_clkin_ck>, <&l3_iclk_div>; + ti,bit-shift = <25>; + reg = <0x13d0>; + }; + + gpu_core_gclk_mux: gpu_core_gclk_mux { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>, <&dpll_gpu_m2_ck>; + ti,bit-shift = <24>; + reg = <0x1220>; + }; + + gpu_hyd_gclk_mux: gpu_hyd_gclk_mux { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>, <&dpll_gpu_m2_ck>; + ti,bit-shift = <26>; + reg = <0x1220>; + }; + + l3instr_ts_gclk_div: l3instr_ts_gclk_div { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&wkupaon_iclk_mux>; + ti,bit-shift = <24>; + reg = <0x0e50>; + ti,dividers = <8>, <16>, <32>; + }; + + mcasp2_ahclkr_mux: mcasp2_ahclkr_mux { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>; + ti,bit-shift = <28>; + reg = <0x1860>; + }; + + mcasp2_ahclkx_mux: mcasp2_ahclkx_mux { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>; + ti,bit-shift = <28>; + reg = <0x1860>; + }; + + mcasp2_aux_gfclk_mux: mcasp2_aux_gfclk_mux { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>; + ti,bit-shift = <22>; + reg = <0x1860>; + }; + + mcasp3_ahclkx_mux: mcasp3_ahclkx_mux { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>; + ti,bit-shift = <24>; + reg = <0x1868>; + }; + + mcasp3_aux_gfclk_mux: mcasp3_aux_gfclk_mux { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>; + ti,bit-shift = <22>; + reg = <0x1868>; + }; + + mcasp4_ahclkx_mux: mcasp4_ahclkx_mux { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>; + ti,bit-shift = <24>; + reg = <0x1898>; + }; + + mcasp4_aux_gfclk_mux: mcasp4_aux_gfclk_mux { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>; + ti,bit-shift = <22>; + reg = <0x1898>; + }; + + mcasp5_ahclkx_mux: mcasp5_ahclkx_mux { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>; + ti,bit-shift = <24>; + reg = <0x1878>; + }; + + mcasp5_aux_gfclk_mux: mcasp5_aux_gfclk_mux { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>; + ti,bit-shift = <22>; + reg = <0x1878>; + }; + + mcasp6_ahclkx_mux: mcasp6_ahclkx_mux { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>; + ti,bit-shift = <24>; + reg = <0x1904>; + }; + + mcasp6_aux_gfclk_mux: mcasp6_aux_gfclk_mux { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>; + ti,bit-shift = <22>; + reg = <0x1904>; + }; + + mcasp7_ahclkx_mux: mcasp7_ahclkx_mux { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>; + ti,bit-shift = <24>; + reg = <0x1908>; + }; + + mcasp7_aux_gfclk_mux: mcasp7_aux_gfclk_mux { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>; + ti,bit-shift = <22>; + reg = <0x1908>; + }; + + mcasp8_ahclk_mux: mcasp8_ahclk_mux { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>; + ti,bit-shift = <22>; + reg = <0x1890>; + }; + + mcasp8_aux_gfclk_mux: mcasp8_aux_gfclk_mux { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>; + ti,bit-shift = <24>; + reg = <0x1890>; + }; + + mmc1_fclk_mux: mmc1_fclk_mux { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>; + ti,bit-shift = <24>; + reg = <0x1328>; + }; + + mmc1_fclk_div: mmc1_fclk_div { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&mmc1_fclk_mux>; + ti,bit-shift = <25>; + ti,max-div = <4>; + reg = <0x1328>; + ti,index-power-of-two; + }; + + mmc2_fclk_mux: mmc2_fclk_mux { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>; + ti,bit-shift = <24>; + reg = <0x1330>; + }; + + mmc2_fclk_div: mmc2_fclk_div { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&mmc2_fclk_mux>; + ti,bit-shift = <25>; + ti,max-div = <4>; + reg = <0x1330>; + ti,index-power-of-two; + }; + + mmc3_gfclk_mux: mmc3_gfclk_mux { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>; + ti,bit-shift = <24>; + reg = <0x1820>; + }; + + mmc3_gfclk_div: mmc3_gfclk_div { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&mmc3_gfclk_mux>; + ti,bit-shift = <25>; + ti,max-div = <4>; + reg = <0x1820>; + ti,index-power-of-two; + }; + + mmc4_gfclk_mux: mmc4_gfclk_mux { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>; + ti,bit-shift = <24>; + reg = <0x1828>; + }; + + mmc4_gfclk_div: mmc4_gfclk_div { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&mmc4_gfclk_mux>; + ti,bit-shift = <25>; + ti,max-div = <4>; + reg = <0x1828>; + ti,index-power-of-two; + }; + + qspi_gfclk_mux: qspi_gfclk_mux { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&func_128m_clk>, <&dpll_per_h13x2_ck>; + ti,bit-shift = <24>; + reg = <0x1838>; + }; + + qspi_gfclk_div: qspi_gfclk_div { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&qspi_gfclk_mux>; + ti,bit-shift = <25>; + ti,max-div = <4>; + reg = <0x1838>; + ti,index-power-of-two; + }; + + timer10_gfclk_mux: timer10_gfclk_mux { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>; + ti,bit-shift = <24>; + reg = <0x1728>; + }; + + timer11_gfclk_mux: timer11_gfclk_mux { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>; + ti,bit-shift = <24>; + reg = <0x1730>; + }; + + timer13_gfclk_mux: timer13_gfclk_mux { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>; + ti,bit-shift = <24>; + reg = <0x17c8>; + }; + + timer14_gfclk_mux: timer14_gfclk_mux { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>; + ti,bit-shift = <24>; + reg = <0x17d0>; + }; + + timer15_gfclk_mux: timer15_gfclk_mux { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>; + ti,bit-shift = <24>; + reg = <0x17d8>; + }; + + timer16_gfclk_mux: timer16_gfclk_mux { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>; + ti,bit-shift = <24>; + reg = <0x1830>; + }; + + timer2_gfclk_mux: timer2_gfclk_mux { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>; + ti,bit-shift = <24>; + reg = <0x1738>; + }; + + timer3_gfclk_mux: timer3_gfclk_mux { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>; + ti,bit-shift = <24>; + reg = <0x1740>; + }; + + timer4_gfclk_mux: timer4_gfclk_mux { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>; + ti,bit-shift = <24>; + reg = <0x1748>; + }; + + timer9_gfclk_mux: timer9_gfclk_mux { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>; + ti,bit-shift = <24>; + reg = <0x1750>; + }; + + uart1_gfclk_mux: uart1_gfclk_mux { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>; + ti,bit-shift = <24>; + reg = <0x1840>; + }; + + uart2_gfclk_mux: uart2_gfclk_mux { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>; + ti,bit-shift = <24>; + reg = <0x1848>; + }; + + uart3_gfclk_mux: uart3_gfclk_mux { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>; + ti,bit-shift = <24>; + reg = <0x1850>; + }; + + uart4_gfclk_mux: uart4_gfclk_mux { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>; + ti,bit-shift = <24>; + reg = <0x1858>; + }; + + uart5_gfclk_mux: uart5_gfclk_mux { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>; + ti,bit-shift = <24>; + reg = <0x1870>; + }; + + uart7_gfclk_mux: uart7_gfclk_mux { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>; + ti,bit-shift = <24>; + reg = <0x18d0>; + }; + + uart8_gfclk_mux: uart8_gfclk_mux { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>; + ti,bit-shift = <24>; + reg = <0x18e0>; + }; + + uart9_gfclk_mux: uart9_gfclk_mux { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>; + ti,bit-shift = <24>; + reg = <0x18e8>; + }; + + vip1_gclk_mux: vip1_gclk_mux { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>; + ti,bit-shift = <24>; + reg = <0x1020>; + }; + + vip2_gclk_mux: vip2_gclk_mux { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>; + ti,bit-shift = <24>; + reg = <0x1028>; + }; + + vip3_gclk_mux: vip3_gclk_mux { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>; + ti,bit-shift = <24>; + reg = <0x1030>; + }; +}; + +&cm_core_clockdomains { + coreaon_clkdm: coreaon_clkdm { + compatible = "ti,clockdomain"; + clocks = <&dpll_usb_ck>; + }; +}; -- cgit v1.2.3-59-g8ed1b From 7d138d3aafea6e7252ae5ea1e80423335b6c70dc Mon Sep 17 00:00:00 2001 From: J Keerthy Date: Tue, 23 Jul 2013 12:05:38 +0530 Subject: ARM: dts: clk: Add apll related clocks The patch adds a mux node to choose the parent of apll_pcie_ck node. Signed-off-by: J Keerthy Signed-off-by: Tero Kristo Tested-by: Nishanth Menon Acked-by: Tony Lindgren Signed-off-by: Mike Turquette --- arch/arm/boot/dts/dra7xx-clocks.dtsi | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi index 32df8470b4a8..d4e7410dc0cd 100644 --- a/arch/arm/boot/dts/dra7xx-clocks.dtsi +++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi @@ -1150,11 +1150,19 @@ ti,invert-autoidle-bit; }; + apll_pcie_in_clk_mux: apll_pcie_in_clk_mux@4ae06118 { + compatible = "ti,mux-clock"; + clocks = <&dpll_pcie_ref_ck>, <&pciesref_acs_clk_ck>; + #clock-cells = <0>; + reg = <0x021c 0x4>; + ti,bit-shift = <7>; + }; + apll_pcie_ck: apll_pcie_ck { #clock-cells = <0>; - compatible = "ti,omap4-dpll-clock"; - clocks = <&dpll_pcie_ref_ck>, <&dpll_pcie_ref_ck>; - reg = <0x0200>, <0x0204>, <0x020c>, <0x0208>; + compatible = "ti,dra7-apll-clock"; + clocks = <&apll_pcie_in_clk_mux>, <&dpll_pcie_ref_ck>; + reg = <0x021c>, <0x0220>; }; apll_pcie_clkvcoldo: apll_pcie_clkvcoldo { -- cgit v1.2.3-59-g8ed1b From c3be7acdeb5ce5bc857ee47664b0be36241e2402 Mon Sep 17 00:00:00 2001 From: J Keerthy Date: Tue, 23 Jul 2013 12:05:39 +0530 Subject: ARM: dts: DRA7: Change apll_pcie_m2_ck to fixed factor clock This patch changes apll_pcie_m2_ck to fixed factor clock as there are no configurable divider associated to m2. Signed-off-by: J Keerthy Signed-off-by: Tero Kristo Tested-by: Nishanth Menon Acked-by: Tony Lindgren Signed-off-by: Mike Turquette --- arch/arm/boot/dts/dra7xx-clocks.dtsi | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi index d4e7410dc0cd..d616359baed1 100644 --- a/arch/arm/boot/dts/dra7xx-clocks.dtsi +++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi @@ -1183,13 +1183,10 @@ apll_pcie_m2_ck: apll_pcie_m2_ck { #clock-cells = <0>; - compatible = "ti,divider-clock"; + compatible = "fixed-factor-clock"; clocks = <&apll_pcie_ck>; - ti,max-div = <127>; - ti,autoidle-shift = <8>; - reg = <0x0224>; - ti,index-starts-at-one; - ti,invert-autoidle-bit; + clock-mult = <1>; + clock-div = <1>; }; dpll_per_ck: dpll_per_ck { -- cgit v1.2.3-59-g8ed1b From a0289f917402a08b049b818ffba638cb16994315 Mon Sep 17 00:00:00 2001 From: J Keerthy Date: Tue, 23 Jul 2013 12:05:40 +0530 Subject: ARM: dts: DRA7: Add PCIe related clock nodes This patch adds optfclk_pciephy_clk and optfclk_pciephy_div_clk which are used by PCIe phy. It also adds a mux clock to choose the source of optfclk_pciephy_div_clk clock. Signed-off-by: J Keerthy Signed-off-by: Tero Kristo Tested-by: Nishanth Menon Acked-by: Tony Lindgren Signed-off-by: Mike Turquette --- arch/arm/boot/dts/dra7xx-clocks.dtsi | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi index d616359baed1..e96da9a898ad 100644 --- a/arch/arm/boot/dts/dra7xx-clocks.dtsi +++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi @@ -1165,6 +1165,31 @@ reg = <0x021c>, <0x0220>; }; + optfclk_pciephy_div: optfclk_pciephy_div@4a00821c { + compatible = "ti,divider-clock"; + clocks = <&apll_pcie_ck>; + #clock-cells = <0>; + reg = <0x021c>; + ti,bit-shift = <8>; + ti,max-div = <2>; + }; + + optfclk_pciephy_clk: optfclk_pciephy_clk@4a0093b0 { + compatible = "ti,gate-clock"; + clocks = <&apll_pcie_ck>; + #clock-cells = <0>; + reg = <0x13b0>; + ti,bit-shift = <9>; + }; + + optfclk_pciephy_div_clk: optfclk_pciephy_div_clk@4a0093b0 { + compatible = "ti,gate-clock"; + clocks = <&optfclk_pciephy_div>; + #clock-cells = <0>; + reg = <0x13b0>; + ti,bit-shift = <10>; + }; + apll_pcie_clkvcoldo: apll_pcie_clkvcoldo { #clock-cells = <0>; compatible = "fixed-factor-clock"; -- cgit v1.2.3-59-g8ed1b From ea291c9851d8f3a8d79a2b7a530df27548c7652c Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Thu, 18 Jul 2013 18:15:35 +0300 Subject: ARM: dts: am33xx clock data This patch creates a unique node for each clock in the AM33xx power, reset and clock manager (PRCM). Signed-off-by: Tero Kristo Acked-by: Tony Lindgren Signed-off-by: Mike Turquette --- arch/arm/boot/dts/am33xx-clocks.dtsi | 664 +++++++++++++++++++++++++++++++++++ arch/arm/boot/dts/am33xx.dtsi | 28 ++ 2 files changed, 692 insertions(+) create mode 100644 arch/arm/boot/dts/am33xx-clocks.dtsi diff --git a/arch/arm/boot/dts/am33xx-clocks.dtsi b/arch/arm/boot/dts/am33xx-clocks.dtsi new file mode 100644 index 000000000000..9ccfe508dea2 --- /dev/null +++ b/arch/arm/boot/dts/am33xx-clocks.dtsi @@ -0,0 +1,664 @@ +/* + * Device Tree Source for AM33xx clock data + * + * Copyright (C) 2013 Texas Instruments, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +&scrm_clocks { + sys_clkin_ck: sys_clkin_ck { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>; + ti,bit-shift = <22>; + reg = <0x0040>; + }; + + adc_tsc_fck: adc_tsc_fck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&sys_clkin_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + dcan0_fck: dcan0_fck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&sys_clkin_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + dcan1_fck: dcan1_fck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&sys_clkin_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + mcasp0_fck: mcasp0_fck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&sys_clkin_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + mcasp1_fck: mcasp1_fck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&sys_clkin_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + smartreflex0_fck: smartreflex0_fck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&sys_clkin_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + smartreflex1_fck: smartreflex1_fck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&sys_clkin_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + sha0_fck: sha0_fck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&sys_clkin_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + aes0_fck: aes0_fck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&sys_clkin_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + rng_fck: rng_fck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&sys_clkin_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + ehrpwm0_gate_tbclk: ehrpwm0_gate_tbclk { + #clock-cells = <0>; + compatible = "ti,composite-no-wait-gate-clock"; + clocks = <&dpll_per_m2_ck>; + ti,bit-shift = <0>; + reg = <0x0664>; + }; + + ehrpwm0_tbclk: ehrpwm0_tbclk { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&ehrpwm0_gate_tbclk>; + }; + + ehrpwm1_gate_tbclk: ehrpwm1_gate_tbclk { + #clock-cells = <0>; + compatible = "ti,composite-no-wait-gate-clock"; + clocks = <&dpll_per_m2_ck>; + ti,bit-shift = <1>; + reg = <0x0664>; + }; + + ehrpwm1_tbclk: ehrpwm1_tbclk { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&ehrpwm1_gate_tbclk>; + }; + + ehrpwm2_gate_tbclk: ehrpwm2_gate_tbclk { + #clock-cells = <0>; + compatible = "ti,composite-no-wait-gate-clock"; + clocks = <&dpll_per_m2_ck>; + ti,bit-shift = <2>; + reg = <0x0664>; + }; + + ehrpwm2_tbclk: ehrpwm2_tbclk { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&ehrpwm2_gate_tbclk>; + }; +}; +&prcm_clocks { + clk_32768_ck: clk_32768_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + }; + + clk_rc32k_ck: clk_rc32k_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32000>; + }; + + virt_19200000_ck: virt_19200000_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <19200000>; + }; + + virt_24000000_ck: virt_24000000_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + }; + + virt_25000000_ck: virt_25000000_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <25000000>; + }; + + virt_26000000_ck: virt_26000000_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <26000000>; + }; + + tclkin_ck: tclkin_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <12000000>; + }; + + dpll_core_ck: dpll_core_ck { + #clock-cells = <0>; + compatible = "ti,am3-dpll-core-clock"; + clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; + reg = <0x0490>, <0x045c>, <0x0468>; + }; + + dpll_core_x2_ck: dpll_core_x2_ck { + #clock-cells = <0>; + compatible = "ti,am3-dpll-x2-clock"; + clocks = <&dpll_core_ck>; + }; + + dpll_core_m4_ck: dpll_core_m4_ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll_core_x2_ck>; + ti,max-div = <31>; + reg = <0x0480>; + ti,index-starts-at-one; + }; + + dpll_core_m5_ck: dpll_core_m5_ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll_core_x2_ck>; + ti,max-div = <31>; + reg = <0x0484>; + ti,index-starts-at-one; + }; + + dpll_core_m6_ck: dpll_core_m6_ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll_core_x2_ck>; + ti,max-div = <31>; + reg = <0x04d8>; + ti,index-starts-at-one; + }; + + dpll_mpu_ck: dpll_mpu_ck { + #clock-cells = <0>; + compatible = "ti,am3-dpll-clock"; + clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; + reg = <0x0488>, <0x0420>, <0x042c>; + }; + + dpll_mpu_m2_ck: dpll_mpu_m2_ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll_mpu_ck>; + ti,max-div = <31>; + reg = <0x04a8>; + ti,index-starts-at-one; + }; + + dpll_ddr_ck: dpll_ddr_ck { + #clock-cells = <0>; + compatible = "ti,am3-dpll-no-gate-clock"; + clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; + reg = <0x0494>, <0x0434>, <0x0440>; + }; + + dpll_ddr_m2_ck: dpll_ddr_m2_ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll_ddr_ck>; + ti,max-div = <31>; + reg = <0x04a0>; + ti,index-starts-at-one; + }; + + dpll_ddr_m2_div2_ck: dpll_ddr_m2_div2_ck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll_ddr_m2_ck>; + clock-mult = <1>; + clock-div = <2>; + }; + + dpll_disp_ck: dpll_disp_ck { + #clock-cells = <0>; + compatible = "ti,am3-dpll-no-gate-clock"; + clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; + reg = <0x0498>, <0x0448>, <0x0454>; + }; + + dpll_disp_m2_ck: dpll_disp_m2_ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll_disp_ck>; + ti,max-div = <31>; + reg = <0x04a4>; + ti,index-starts-at-one; + ti,set-rate-parent; + }; + + dpll_per_ck: dpll_per_ck { + #clock-cells = <0>; + compatible = "ti,am3-dpll-no-gate-j-type-clock"; + clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; + reg = <0x048c>, <0x0470>, <0x049c>; + }; + + dpll_per_m2_ck: dpll_per_m2_ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll_per_ck>; + ti,max-div = <31>; + reg = <0x04ac>; + ti,index-starts-at-one; + }; + + dpll_per_m2_div4_wkupdm_ck: dpll_per_m2_div4_wkupdm_ck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll_per_m2_ck>; + clock-mult = <1>; + clock-div = <4>; + }; + + dpll_per_m2_div4_ck: dpll_per_m2_div4_ck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll_per_m2_ck>; + clock-mult = <1>; + clock-div = <4>; + }; + + cefuse_fck: cefuse_fck { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&sys_clkin_ck>; + ti,bit-shift = <1>; + reg = <0x0a20>; + }; + + clk_24mhz: clk_24mhz { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll_per_m2_ck>; + clock-mult = <1>; + clock-div = <8>; + }; + + clkdiv32k_ck: clkdiv32k_ck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&clk_24mhz>; + clock-mult = <1>; + clock-div = <732>; + }; + + clkdiv32k_ick: clkdiv32k_ick { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&clkdiv32k_ck>; + ti,bit-shift = <1>; + reg = <0x014c>; + }; + + l3_gclk: l3_gclk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll_core_m4_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + pruss_ocp_gclk: pruss_ocp_gclk { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&l3_gclk>, <&dpll_disp_m2_ck>; + reg = <0x0530>; + }; + + mmu_fck: mmu_fck { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&dpll_core_m4_ck>; + ti,bit-shift = <1>; + reg = <0x0914>; + }; + + timer1_fck: timer1_fck { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&sys_clkin_ck>, <&clkdiv32k_ick>, <&tclkin_ck>, <&clk_rc32k_ck>, <&clk_32768_ck>; + reg = <0x0528>; + }; + + timer2_fck: timer2_fck { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; + reg = <0x0508>; + }; + + timer3_fck: timer3_fck { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; + reg = <0x050c>; + }; + + timer4_fck: timer4_fck { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; + reg = <0x0510>; + }; + + timer5_fck: timer5_fck { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; + reg = <0x0518>; + }; + + timer6_fck: timer6_fck { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; + reg = <0x051c>; + }; + + timer7_fck: timer7_fck { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; + reg = <0x0504>; + }; + + usbotg_fck: usbotg_fck { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&dpll_per_ck>; + ti,bit-shift = <8>; + reg = <0x047c>; + }; + + dpll_core_m4_div2_ck: dpll_core_m4_div2_ck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll_core_m4_ck>; + clock-mult = <1>; + clock-div = <2>; + }; + + ieee5000_fck: ieee5000_fck { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&dpll_core_m4_div2_ck>; + ti,bit-shift = <1>; + reg = <0x00e4>; + }; + + wdt1_fck: wdt1_fck { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&clk_rc32k_ck>, <&clkdiv32k_ick>; + reg = <0x0538>; + }; + + l4_rtc_gclk: l4_rtc_gclk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll_core_m4_ck>; + clock-mult = <1>; + clock-div = <2>; + }; + + l4hs_gclk: l4hs_gclk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll_core_m4_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + l3s_gclk: l3s_gclk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll_core_m4_div2_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + l4fw_gclk: l4fw_gclk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll_core_m4_div2_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + l4ls_gclk: l4ls_gclk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll_core_m4_div2_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + sysclk_div_ck: sysclk_div_ck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll_core_m4_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + cpsw_125mhz_gclk: cpsw_125mhz_gclk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll_core_m5_ck>; + clock-mult = <1>; + clock-div = <2>; + }; + + cpsw_cpts_rft_clk: cpsw_cpts_rft_clk { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&dpll_core_m5_ck>, <&dpll_core_m4_ck>; + reg = <0x0520>; + }; + + gpio0_dbclk_mux_ck: gpio0_dbclk_mux_ck { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&clk_rc32k_ck>, <&clk_32768_ck>, <&clkdiv32k_ick>; + reg = <0x053c>; + }; + + gpio0_dbclk: gpio0_dbclk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&gpio0_dbclk_mux_ck>; + ti,bit-shift = <18>; + reg = <0x0408>; + }; + + gpio1_dbclk: gpio1_dbclk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&clkdiv32k_ick>; + ti,bit-shift = <18>; + reg = <0x00ac>; + }; + + gpio2_dbclk: gpio2_dbclk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&clkdiv32k_ick>; + ti,bit-shift = <18>; + reg = <0x00b0>; + }; + + gpio3_dbclk: gpio3_dbclk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&clkdiv32k_ick>; + ti,bit-shift = <18>; + reg = <0x00b4>; + }; + + lcd_gclk: lcd_gclk { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&dpll_disp_m2_ck>, <&dpll_core_m5_ck>, <&dpll_per_m2_ck>; + reg = <0x0534>; + ti,set-rate-parent; + }; + + mmc_clk: mmc_clk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll_per_m2_ck>; + clock-mult = <1>; + clock-div = <2>; + }; + + gfx_fclk_clksel_ck: gfx_fclk_clksel_ck { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&dpll_core_m4_ck>, <&dpll_per_m2_ck>; + ti,bit-shift = <1>; + reg = <0x052c>; + }; + + gfx_fck_div_ck: gfx_fck_div_ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&gfx_fclk_clksel_ck>; + reg = <0x052c>; + ti,max-div = <2>; + }; + + sysclkout_pre_ck: sysclkout_pre_ck { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&clk_32768_ck>, <&l3_gclk>, <&dpll_ddr_m2_ck>, <&dpll_per_m2_ck>, <&lcd_gclk>; + reg = <0x0700>; + }; + + clkout2_div_ck: clkout2_div_ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&sysclkout_pre_ck>; + ti,bit-shift = <3>; + ti,max-div = <8>; + reg = <0x0700>; + }; + + dbg_sysclk_ck: dbg_sysclk_ck { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&sys_clkin_ck>; + ti,bit-shift = <19>; + reg = <0x0414>; + }; + + dbg_clka_ck: dbg_clka_ck { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&dpll_core_m4_ck>; + ti,bit-shift = <30>; + reg = <0x0414>; + }; + + stm_pmd_clock_mux_ck: stm_pmd_clock_mux_ck { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&dbg_sysclk_ck>, <&dbg_clka_ck>; + ti,bit-shift = <22>; + reg = <0x0414>; + }; + + trace_pmd_clk_mux_ck: trace_pmd_clk_mux_ck { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&dbg_sysclk_ck>, <&dbg_clka_ck>; + ti,bit-shift = <20>; + reg = <0x0414>; + }; + + stm_clk_div_ck: stm_clk_div_ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&stm_pmd_clock_mux_ck>; + ti,bit-shift = <27>; + ti,max-div = <64>; + reg = <0x0414>; + ti,index-power-of-two; + }; + + trace_clk_div_ck: trace_clk_div_ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&trace_pmd_clk_mux_ck>; + ti,bit-shift = <24>; + ti,max-div = <64>; + reg = <0x0414>; + ti,index-power-of-two; + }; + + clkout2_ck: clkout2_ck { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&clkout2_div_ck>; + ti,bit-shift = <7>; + reg = <0x0700>; + }; +}; + +&prcm_clockdomains { + clk_24mhz_clkdm: clk_24mhz_clkdm { + compatible = "ti,clockdomain"; + clocks = <&clkdiv32k_ick>; + }; +}; diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi index f6d8ffe98d0b..6d95d3df33c7 100644 --- a/arch/arm/boot/dts/am33xx.dtsi +++ b/arch/arm/boot/dts/am33xx.dtsi @@ -102,6 +102,32 @@ ranges; ti,hwmods = "l3_main"; + prcm: prcm@44e00000 { + compatible = "ti,am3-prcm"; + reg = <0x44e00000 0x4000>; + + prcm_clocks: clocks { + #address-cells = <1>; + #size-cells = <0>; + }; + + prcm_clockdomains: clockdomains { + }; + }; + + scrm: scrm@44e10000 { + compatible = "ti,am3-scrm"; + reg = <0x44e10000 0x2000>; + + scrm_clocks: clocks { + #address-cells = <1>; + #size-cells = <0>; + }; + + scrm_clockdomains: clockdomains { + }; + }; + intc: interrupt-controller@48200000 { compatible = "ti,omap2-intc"; interrupt-controller; @@ -794,3 +820,5 @@ }; }; }; + +/include/ "am33xx-clocks.dtsi" -- cgit v1.2.3-59-g8ed1b From 657fc11cca50148544314e650a82cffc94d74db7 Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Mon, 22 Jul 2013 12:29:29 +0300 Subject: ARM: dts: omap3 clock data This patch creates a unique node for each clock in the OMAP3 power, reset and clock manager (PRCM). Signed-off-by: Tero Kristo Acked-by: Tony Lindgren Signed-off-by: Mike Turquette --- arch/arm/boot/dts/am35xx-clocks.dtsi | 128 ++ arch/arm/boot/dts/omap3.dtsi | 41 + arch/arm/boot/dts/omap3430es1-clocks.dtsi | 208 +++ arch/arm/boot/dts/omap34xx-omap36xx-clocks.dtsi | 268 ++++ arch/arm/boot/dts/omap34xx.dtsi | 4 + .../omap36xx-am35xx-omap3430es2plus-clocks.dtsi | 242 +++ arch/arm/boot/dts/omap36xx-clocks.dtsi | 90 ++ .../boot/dts/omap36xx-omap3430es2plus-clocks.dtsi | 198 +++ arch/arm/boot/dts/omap36xx.dtsi | 5 + arch/arm/boot/dts/omap3xxx-clocks.dtsi | 1660 ++++++++++++++++++++ 10 files changed, 2844 insertions(+) create mode 100644 arch/arm/boot/dts/am35xx-clocks.dtsi create mode 100644 arch/arm/boot/dts/omap3430es1-clocks.dtsi create mode 100644 arch/arm/boot/dts/omap34xx-omap36xx-clocks.dtsi create mode 100644 arch/arm/boot/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi create mode 100644 arch/arm/boot/dts/omap36xx-clocks.dtsi create mode 100644 arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi create mode 100644 arch/arm/boot/dts/omap3xxx-clocks.dtsi diff --git a/arch/arm/boot/dts/am35xx-clocks.dtsi b/arch/arm/boot/dts/am35xx-clocks.dtsi new file mode 100644 index 000000000000..df489d310b50 --- /dev/null +++ b/arch/arm/boot/dts/am35xx-clocks.dtsi @@ -0,0 +1,128 @@ +/* + * Device Tree Source for OMAP3 clock data + * + * Copyright (C) 2013 Texas Instruments, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +&scrm_clocks { + emac_ick: emac_ick { + #clock-cells = <0>; + compatible = "ti,am35xx-gate-clock"; + clocks = <&ipss_ick>; + reg = <0x059c>; + ti,bit-shift = <1>; + }; + + emac_fck: emac_fck { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&rmii_ck>; + reg = <0x059c>; + ti,bit-shift = <9>; + }; + + vpfe_ick: vpfe_ick { + #clock-cells = <0>; + compatible = "ti,am35xx-gate-clock"; + clocks = <&ipss_ick>; + reg = <0x059c>; + ti,bit-shift = <2>; + }; + + vpfe_fck: vpfe_fck { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&pclk_ck>; + reg = <0x059c>; + ti,bit-shift = <10>; + }; + + hsotgusb_ick_am35xx: hsotgusb_ick_am35xx { + #clock-cells = <0>; + compatible = "ti,am35xx-gate-clock"; + clocks = <&ipss_ick>; + reg = <0x059c>; + ti,bit-shift = <0>; + }; + + hsotgusb_fck_am35xx: hsotgusb_fck_am35xx { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&sys_ck>; + reg = <0x059c>; + ti,bit-shift = <8>; + }; + + hecc_ck: hecc_ck { + #clock-cells = <0>; + compatible = "ti,am35xx-gate-clock"; + clocks = <&sys_ck>; + reg = <0x059c>; + ti,bit-shift = <3>; + }; +}; +&cm_clocks { + ipss_ick: ipss_ick { + #clock-cells = <0>; + compatible = "ti,am35xx-interface-clock"; + clocks = <&core_l3_ick>; + reg = <0x0a10>; + ti,bit-shift = <4>; + }; + + rmii_ck: rmii_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <50000000>; + }; + + pclk_ck: pclk_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <27000000>; + }; + + uart4_ick_am35xx: uart4_ick_am35xx { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&core_l4_ick>; + reg = <0x0a10>; + ti,bit-shift = <23>; + }; + + uart4_fck_am35xx: uart4_fck_am35xx { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clocks = <&core_48m_fck>; + reg = <0x0a00>; + ti,bit-shift = <23>; + }; +}; + +&cm_clockdomains { + core_l3_clkdm: core_l3_clkdm { + compatible = "ti,clockdomain"; + clocks = <&sdrc_ick>, <&ipss_ick>, <&emac_ick>, <&vpfe_ick>, + <&hsotgusb_ick_am35xx>, <&hsotgusb_fck_am35xx>, + <&hecc_ck>; + }; + + core_l4_clkdm: core_l4_clkdm { + compatible = "ti,clockdomain"; + clocks = <&cpefuse_fck>, <&ts_fck>, <&usbtll_fck>, + <&usbtll_ick>, <&mmchs3_ick>, <&mmchs3_fck>, + <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>, + <&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>, + <&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>, + <&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>, + <&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>, + <&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>, + <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>, + <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>, + <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>, + <&uart4_ick_am35xx>, <&uart4_fck_am35xx>; + }; +}; diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi index daabf99d402a..07c7341d6c86 100644 --- a/arch/arm/boot/dts/omap3.dtsi +++ b/arch/arm/boot/dts/omap3.dtsi @@ -89,6 +89,45 @@ interrupts = <0>; }; + prm: prm@48306000 { + compatible = "ti,omap3-prm"; + reg = <0x48306000 0x4000>; + + prm_clocks: clocks { + #address-cells = <1>; + #size-cells = <0>; + }; + + prm_clockdomains: clockdomains { + }; + }; + + cm: cm@48004000 { + compatible = "ti,omap3-cm"; + reg = <0x48004000 0x4000>; + + cm_clocks: clocks { + #address-cells = <1>; + #size-cells = <0>; + }; + + cm_clockdomains: clockdomains { + }; + }; + + scrm: scrm@48002000 { + compatible = "ti,omap3-scrm"; + reg = <0x48002000 0x2000>; + + scrm_clocks: clocks { + #address-cells = <1>; + #size-cells = <0>; + }; + + scrm_clockdomains: clockdomains { + }; + }; + counter32k: counter@48320000 { compatible = "ti,omap-counter32k"; reg = <0x48320000 0x20>; @@ -632,3 +671,5 @@ }; }; }; + +/include/ "omap3xxx-clocks.dtsi" diff --git a/arch/arm/boot/dts/omap3430es1-clocks.dtsi b/arch/arm/boot/dts/omap3430es1-clocks.dtsi new file mode 100644 index 000000000000..02f6c7fabbec --- /dev/null +++ b/arch/arm/boot/dts/omap3430es1-clocks.dtsi @@ -0,0 +1,208 @@ +/* + * Device Tree Source for OMAP3430 ES1 clock data + * + * Copyright (C) 2013 Texas Instruments, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +&cm_clocks { + gfx_l3_ck: gfx_l3_ck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clocks = <&l3_ick>; + reg = <0x0b10>; + ti,bit-shift = <0>; + }; + + gfx_l3_fck: gfx_l3_fck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&l3_ick>; + ti,max-div = <7>; + reg = <0x0b40>; + ti,index-starts-at-one; + }; + + gfx_l3_ick: gfx_l3_ick { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&gfx_l3_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + gfx_cg1_ck: gfx_cg1_ck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clocks = <&gfx_l3_fck>; + reg = <0x0b00>; + ti,bit-shift = <1>; + }; + + gfx_cg2_ck: gfx_cg2_ck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clocks = <&gfx_l3_fck>; + reg = <0x0b00>; + ti,bit-shift = <2>; + }; + + d2d_26m_fck: d2d_26m_fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clocks = <&sys_ck>; + reg = <0x0a00>; + ti,bit-shift = <3>; + }; + + fshostusb_fck: fshostusb_fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clocks = <&core_48m_fck>; + reg = <0x0a00>; + ti,bit-shift = <5>; + }; + + ssi_ssr_gate_fck_3430es1: ssi_ssr_gate_fck_3430es1 { + #clock-cells = <0>; + compatible = "ti,composite-no-wait-gate-clock"; + clocks = <&corex2_fck>; + ti,bit-shift = <0>; + reg = <0x0a00>; + }; + + ssi_ssr_div_fck_3430es1: ssi_ssr_div_fck_3430es1 { + #clock-cells = <0>; + compatible = "ti,composite-divider-clock"; + clocks = <&corex2_fck>; + ti,bit-shift = <8>; + reg = <0x0a40>; + ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>; + }; + + ssi_ssr_fck_3430es1: ssi_ssr_fck_3430es1 { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&ssi_ssr_gate_fck_3430es1>, <&ssi_ssr_div_fck_3430es1>; + }; + + ssi_sst_fck_3430es1: ssi_sst_fck_3430es1 { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&ssi_ssr_fck_3430es1>; + clock-mult = <1>; + clock-div = <2>; + }; + + hsotgusb_ick_3430es1: hsotgusb_ick_3430es1 { + #clock-cells = <0>; + compatible = "ti,omap3-no-wait-interface-clock"; + clocks = <&core_l3_ick>; + reg = <0x0a10>; + ti,bit-shift = <4>; + }; + + fac_ick: fac_ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&core_l4_ick>; + reg = <0x0a10>; + ti,bit-shift = <8>; + }; + + ssi_l4_ick: ssi_l4_ick { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&l4_ick>; + clock-mult = <1>; + clock-div = <1>; + }; + + ssi_ick_3430es1: ssi_ick_3430es1 { + #clock-cells = <0>; + compatible = "ti,omap3-no-wait-interface-clock"; + clocks = <&ssi_l4_ick>; + reg = <0x0a10>; + ti,bit-shift = <0>; + }; + + usb_l4_gate_ick: usb_l4_gate_ick { + #clock-cells = <0>; + compatible = "ti,composite-interface-clock"; + clocks = <&l4_ick>; + ti,bit-shift = <5>; + reg = <0x0a10>; + }; + + usb_l4_div_ick: usb_l4_div_ick { + #clock-cells = <0>; + compatible = "ti,composite-divider-clock"; + clocks = <&l4_ick>; + ti,bit-shift = <4>; + ti,max-div = <1>; + reg = <0x0a40>; + ti,index-starts-at-one; + }; + + usb_l4_ick: usb_l4_ick { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&usb_l4_gate_ick>, <&usb_l4_div_ick>; + }; + + dss1_alwon_fck_3430es1: dss1_alwon_fck_3430es1 { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&dpll4_m4x2_ck>; + ti,bit-shift = <0>; + reg = <0x0e00>; + ti,set-rate-parent; + }; + + dss_ick_3430es1: dss_ick_3430es1 { + #clock-cells = <0>; + compatible = "ti,omap3-no-wait-interface-clock"; + clocks = <&l4_ick>; + reg = <0x0e10>; + ti,bit-shift = <0>; + }; +}; + +&cm_clockdomains { + core_l3_clkdm: core_l3_clkdm { + compatible = "ti,clockdomain"; + clocks = <&sdrc_ick>, <&hsotgusb_ick_3430es1>; + }; + + gfx_3430es1_clkdm: gfx_3430es1_clkdm { + compatible = "ti,clockdomain"; + clocks = <&gfx_l3_ck>, <&gfx_cg1_ck>, <&gfx_cg2_ck>; + }; + + dss_clkdm: dss_clkdm { + compatible = "ti,clockdomain"; + clocks = <&dss_tv_fck>, <&dss_96m_fck>, <&dss2_alwon_fck>, + <&dss1_alwon_fck_3430es1>, <&dss_ick_3430es1>; + }; + + d2d_clkdm: d2d_clkdm { + compatible = "ti,clockdomain"; + clocks = <&d2d_26m_fck>; + }; + + core_l4_clkdm: core_l4_clkdm { + compatible = "ti,clockdomain"; + clocks = <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>, + <&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>, + <&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>, + <&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>, + <&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>, + <&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>, + <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>, + <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>, + <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>, + <&fshostusb_fck>, <&fac_ick>, <&ssi_ick_3430es1>; + }; +}; diff --git a/arch/arm/boot/dts/omap34xx-omap36xx-clocks.dtsi b/arch/arm/boot/dts/omap34xx-omap36xx-clocks.dtsi new file mode 100644 index 000000000000..b02017b7630e --- /dev/null +++ b/arch/arm/boot/dts/omap34xx-omap36xx-clocks.dtsi @@ -0,0 +1,268 @@ +/* + * Device Tree Source for OMAP34XX/OMAP36XX clock data + * + * Copyright (C) 2013 Texas Instruments, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +&cm_clocks { + security_l4_ick2: security_l4_ick2 { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&l4_ick>; + clock-mult = <1>; + clock-div = <1>; + }; + + aes1_ick: aes1_ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&security_l4_ick2>; + ti,bit-shift = <3>; + reg = <0x0a14>; + }; + + rng_ick: rng_ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&security_l4_ick2>; + reg = <0x0a14>; + ti,bit-shift = <2>; + }; + + sha11_ick: sha11_ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&security_l4_ick2>; + reg = <0x0a14>; + ti,bit-shift = <1>; + }; + + des1_ick: des1_ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&security_l4_ick2>; + reg = <0x0a14>; + ti,bit-shift = <0>; + }; + + cam_mclk: cam_mclk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&dpll4_m5x2_ck>; + ti,bit-shift = <0>; + reg = <0x0f00>; + ti,set-rate-parent; + }; + + cam_ick: cam_ick { + #clock-cells = <0>; + compatible = "ti,omap3-no-wait-interface-clock"; + clocks = <&l4_ick>; + reg = <0x0f10>; + ti,bit-shift = <0>; + }; + + csi2_96m_fck: csi2_96m_fck { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&core_96m_fck>; + reg = <0x0f00>; + ti,bit-shift = <1>; + }; + + security_l3_ick: security_l3_ick { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&l3_ick>; + clock-mult = <1>; + clock-div = <1>; + }; + + pka_ick: pka_ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&security_l3_ick>; + reg = <0x0a14>; + ti,bit-shift = <4>; + }; + + icr_ick: icr_ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&core_l4_ick>; + reg = <0x0a10>; + ti,bit-shift = <29>; + }; + + des2_ick: des2_ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&core_l4_ick>; + reg = <0x0a10>; + ti,bit-shift = <26>; + }; + + mspro_ick: mspro_ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&core_l4_ick>; + reg = <0x0a10>; + ti,bit-shift = <23>; + }; + + mailboxes_ick: mailboxes_ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&core_l4_ick>; + reg = <0x0a10>; + ti,bit-shift = <7>; + }; + + ssi_l4_ick: ssi_l4_ick { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&l4_ick>; + clock-mult = <1>; + clock-div = <1>; + }; + + sr1_fck: sr1_fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clocks = <&sys_ck>; + reg = <0x0c00>; + ti,bit-shift = <6>; + }; + + sr2_fck: sr2_fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clocks = <&sys_ck>; + reg = <0x0c00>; + ti,bit-shift = <7>; + }; + + sr_l4_ick: sr_l4_ick { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&l4_ick>; + clock-mult = <1>; + clock-div = <1>; + }; + + dpll2_fck: dpll2_fck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&core_ck>; + ti,bit-shift = <19>; + ti,max-div = <7>; + reg = <0x0040>; + ti,index-starts-at-one; + }; + + dpll2_ck: dpll2_ck { + #clock-cells = <0>; + compatible = "ti,omap3-dpll-clock"; + clocks = <&sys_ck>, <&dpll2_fck>; + reg = <0x0004>, <0x0024>, <0x0040>, <0x0034>; + ti,low-power-stop; + ti,lock; + ti,low-power-bypass; + }; + + dpll2_m2_ck: dpll2_m2_ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll2_ck>; + ti,max-div = <31>; + reg = <0x0044>; + ti,index-starts-at-one; + }; + + iva2_ck: iva2_ck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clocks = <&dpll2_m2_ck>; + reg = <0x0000>; + ti,bit-shift = <0>; + }; + + modem_fck: modem_fck { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&sys_ck>; + reg = <0x0a00>; + ti,bit-shift = <31>; + }; + + sad2d_ick: sad2d_ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&l3_ick>; + reg = <0x0a10>; + ti,bit-shift = <3>; + }; + + mad2d_ick: mad2d_ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&l3_ick>; + reg = <0x0a18>; + ti,bit-shift = <3>; + }; + + mspro_fck: mspro_fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clocks = <&core_96m_fck>; + reg = <0x0a00>; + ti,bit-shift = <23>; + }; +}; + +&cm_clockdomains { + cam_clkdm: cam_clkdm { + compatible = "ti,clockdomain"; + clocks = <&cam_ick>, <&csi2_96m_fck>; + }; + + iva2_clkdm: iva2_clkdm { + compatible = "ti,clockdomain"; + clocks = <&iva2_ck>; + }; + + dpll2_clkdm: dpll2_clkdm { + compatible = "ti,clockdomain"; + clocks = <&dpll2_ck>; + }; + + wkup_clkdm: wkup_clkdm { + compatible = "ti,clockdomain"; + clocks = <&gpio1_dbck>, <&wdt2_fck>, <&wdt2_ick>, <&wdt1_ick>, + <&gpio1_ick>, <&omap_32ksync_ick>, <&gpt12_ick>, + <&gpt1_ick>, <&sr1_fck>, <&sr2_fck>; + }; + + d2d_clkdm: d2d_clkdm { + compatible = "ti,clockdomain"; + clocks = <&modem_fck>, <&sad2d_ick>, <&mad2d_ick>; + }; + + core_l4_clkdm: core_l4_clkdm { + compatible = "ti,clockdomain"; + clocks = <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>, + <&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>, + <&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>, + <&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>, + <&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>, + <&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>, + <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>, + <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>, + <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>, <&icr_ick>, + <&des2_ick>, <&mspro_ick>, <&mailboxes_ick>, + <&mspro_fck>; + }; +}; diff --git a/arch/arm/boot/dts/omap34xx.dtsi b/arch/arm/boot/dts/omap34xx.dtsi index 5355d6173748..d531abfc6e94 100644 --- a/arch/arm/boot/dts/omap34xx.dtsi +++ b/arch/arm/boot/dts/omap34xx.dtsi @@ -26,3 +26,7 @@ }; }; }; + +/include/ "omap34xx-omap36xx-clocks.dtsi" +/include/ "omap36xx-omap3430es2plus-clocks.dtsi" +/include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi" \ No newline at end of file diff --git a/arch/arm/boot/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi b/arch/arm/boot/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi new file mode 100644 index 000000000000..af9ae5346bf2 --- /dev/null +++ b/arch/arm/boot/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi @@ -0,0 +1,242 @@ +/* + * Device Tree Source for OMAP36xx/AM35xx/OMAP34xx clock data + * + * Copyright (C) 2013 Texas Instruments, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +&prm_clocks { + corex2_d3_fck: corex2_d3_fck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&corex2_fck>; + clock-mult = <1>; + clock-div = <3>; + }; + + corex2_d5_fck: corex2_d5_fck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&corex2_fck>; + clock-mult = <1>; + clock-div = <5>; + }; +}; +&cm_clocks { + dpll5_ck: dpll5_ck { + #clock-cells = <0>; + compatible = "ti,omap3-dpll-clock"; + clocks = <&sys_ck>, <&sys_ck>; + reg = <0x0d04>, <0x0d24>, <0x0d4c>, <0x0d34>; + ti,low-power-stop; + ti,lock; + }; + + dpll5_m2_ck: dpll5_m2_ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll5_ck>; + ti,max-div = <31>; + reg = <0x0d50>; + ti,index-starts-at-one; + }; + + sgx_gate_fck: sgx_gate_fck { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clocks = <&core_ck>; + ti,bit-shift = <1>; + reg = <0x0b00>; + }; + + core_d3_ck: core_d3_ck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&core_ck>; + clock-mult = <1>; + clock-div = <3>; + }; + + core_d4_ck: core_d4_ck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&core_ck>; + clock-mult = <1>; + clock-div = <4>; + }; + + core_d6_ck: core_d6_ck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&core_ck>; + clock-mult = <1>; + clock-div = <6>; + }; + + omap_192m_alwon_fck: omap_192m_alwon_fck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll4_m2x2_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + core_d2_ck: core_d2_ck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&core_ck>; + clock-mult = <1>; + clock-div = <2>; + }; + + sgx_mux_fck: sgx_mux_fck { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clocks = <&core_d3_ck>, <&core_d4_ck>, <&core_d6_ck>, <&cm_96m_fck>, <&omap_192m_alwon_fck>, <&core_d2_ck>, <&corex2_d3_fck>, <&corex2_d5_fck>; + reg = <0x0b40>; + }; + + sgx_fck: sgx_fck { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&sgx_gate_fck>, <&sgx_mux_fck>; + }; + + sgx_ick: sgx_ick { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clocks = <&l3_ick>; + reg = <0x0b10>; + ti,bit-shift = <0>; + }; + + cpefuse_fck: cpefuse_fck { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&sys_ck>; + reg = <0x0a08>; + ti,bit-shift = <0>; + }; + + ts_fck: ts_fck { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&omap_32k_fck>; + reg = <0x0a08>; + ti,bit-shift = <1>; + }; + + usbtll_fck: usbtll_fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clocks = <&dpll5_m2_ck>; + reg = <0x0a08>; + ti,bit-shift = <2>; + }; + + usbtll_ick: usbtll_ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&core_l4_ick>; + reg = <0x0a18>; + ti,bit-shift = <2>; + }; + + mmchs3_ick: mmchs3_ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&core_l4_ick>; + reg = <0x0a10>; + ti,bit-shift = <30>; + }; + + mmchs3_fck: mmchs3_fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clocks = <&core_96m_fck>; + reg = <0x0a00>; + ti,bit-shift = <30>; + }; + + dss1_alwon_fck_3430es2: dss1_alwon_fck_3430es2 { + #clock-cells = <0>; + compatible = "ti,dss-gate-clock"; + clocks = <&dpll4_m4x2_ck>; + ti,bit-shift = <0>; + reg = <0x0e00>; + ti,set-rate-parent; + }; + + dss_ick_3430es2: dss_ick_3430es2 { + #clock-cells = <0>; + compatible = "ti,omap3-dss-interface-clock"; + clocks = <&l4_ick>; + reg = <0x0e10>; + ti,bit-shift = <0>; + }; + + usbhost_120m_fck: usbhost_120m_fck { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&dpll5_m2_ck>; + reg = <0x1400>; + ti,bit-shift = <1>; + }; + + usbhost_48m_fck: usbhost_48m_fck { + #clock-cells = <0>; + compatible = "ti,dss-gate-clock"; + clocks = <&omap_48m_fck>; + reg = <0x1400>; + ti,bit-shift = <0>; + }; + + usbhost_ick: usbhost_ick { + #clock-cells = <0>; + compatible = "ti,omap3-dss-interface-clock"; + clocks = <&l4_ick>; + reg = <0x1410>; + ti,bit-shift = <0>; + }; +}; + +&cm_clockdomains { + dpll5_clkdm: dpll5_clkdm { + compatible = "ti,clockdomain"; + clocks = <&dpll5_ck>; + }; + + sgx_clkdm: sgx_clkdm { + compatible = "ti,clockdomain"; + clocks = <&sgx_ick>; + }; + + dss_clkdm: dss_clkdm { + compatible = "ti,clockdomain"; + clocks = <&dss_tv_fck>, <&dss_96m_fck>, <&dss2_alwon_fck>, + <&dss1_alwon_fck_3430es2>, <&dss_ick_3430es2>; + }; + + core_l4_clkdm: core_l4_clkdm { + compatible = "ti,clockdomain"; + clocks = <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>, + <&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>, + <&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>, + <&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>, + <&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>, + <&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>, + <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>, + <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>, + <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>, + <&cpefuse_fck>, <&ts_fck>, <&usbtll_fck>, + <&usbtll_ick>, <&mmchs3_ick>, <&mmchs3_fck>; + }; + + usbhost_clkdm: usbhost_clkdm { + compatible = "ti,clockdomain"; + clocks = <&usbhost_120m_fck>, <&usbhost_48m_fck>, + <&usbhost_ick>; + }; +}; diff --git a/arch/arm/boot/dts/omap36xx-clocks.dtsi b/arch/arm/boot/dts/omap36xx-clocks.dtsi new file mode 100644 index 000000000000..2fcf253b677c --- /dev/null +++ b/arch/arm/boot/dts/omap36xx-clocks.dtsi @@ -0,0 +1,90 @@ +/* + * Device Tree Source for OMAP36xx clock data + * + * Copyright (C) 2013 Texas Instruments, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +&cm_clocks { + dpll4_ck: dpll4_ck { + #clock-cells = <0>; + compatible = "ti,omap3-dpll-per-j-type-clock"; + clocks = <&sys_ck>, <&sys_ck>; + reg = <0x0d00>, <0x0d20>, <0x0d44>, <0x0d30>; + }; + + dpll4_m5x2_ck: dpll4_m5x2_ck { + #clock-cells = <0>; + compatible = "ti,hsdiv-gate-clock"; + clocks = <&dpll4_m5x2_mul_ck>; + ti,bit-shift = <0x1e>; + reg = <0x0d00>; + ti,set-rate-parent; + ti,set-bit-to-disable; + }; + + dpll4_m2x2_ck: dpll4_m2x2_ck { + #clock-cells = <0>; + compatible = "ti,hsdiv-gate-clock"; + clocks = <&dpll4_m2x2_mul_ck>; + ti,bit-shift = <0x1b>; + reg = <0x0d00>; + ti,set-bit-to-disable; + }; + + dpll3_m3x2_ck: dpll3_m3x2_ck { + #clock-cells = <0>; + compatible = "ti,hsdiv-gate-clock"; + clocks = <&dpll3_m3x2_mul_ck>; + ti,bit-shift = <0xc>; + reg = <0x0d00>; + ti,set-bit-to-disable; + }; + + dpll4_m3x2_ck: dpll4_m3x2_ck { + #clock-cells = <0>; + compatible = "ti,hsdiv-gate-clock"; + clocks = <&dpll4_m3x2_mul_ck>; + ti,bit-shift = <0x1c>; + reg = <0x0d00>; + ti,set-bit-to-disable; + }; + + dpll4_m6x2_ck: dpll4_m6x2_ck { + #clock-cells = <0>; + compatible = "ti,hsdiv-gate-clock"; + clocks = <&dpll4_m6x2_mul_ck>; + ti,bit-shift = <0x1f>; + reg = <0x0d00>; + ti,set-bit-to-disable; + }; + + uart4_fck: uart4_fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clocks = <&per_48m_fck>; + reg = <0x1000>; + ti,bit-shift = <18>; + }; +}; + +&cm_clockdomains { + dpll4_clkdm: dpll4_clkdm { + compatible = "ti,clockdomain"; + clocks = <&dpll4_ck>; + }; + + per_clkdm: per_clkdm { + compatible = "ti,clockdomain"; + clocks = <&uart3_fck>, <&gpio6_dbck>, <&gpio5_dbck>, + <&gpio4_dbck>, <&gpio3_dbck>, <&gpio2_dbck>, + <&wdt3_fck>, <&gpio6_ick>, <&gpio5_ick>, <&gpio4_ick>, + <&gpio3_ick>, <&gpio2_ick>, <&wdt3_ick>, <&uart3_ick>, + <&uart4_ick>, <&gpt9_ick>, <&gpt8_ick>, <&gpt7_ick>, + <&gpt6_ick>, <&gpt5_ick>, <&gpt4_ick>, <&gpt3_ick>, + <&gpt2_ick>, <&mcbsp2_ick>, <&mcbsp3_ick>, + <&mcbsp4_ick>, <&uart4_fck>; + }; +}; diff --git a/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi b/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi new file mode 100644 index 000000000000..8ed475dd63c9 --- /dev/null +++ b/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi @@ -0,0 +1,198 @@ +/* + * Device Tree Source for OMAP34xx/OMAP36xx clock data + * + * Copyright (C) 2013 Texas Instruments, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +&cm_clocks { + ssi_ssr_gate_fck_3430es2: ssi_ssr_gate_fck_3430es2 { + #clock-cells = <0>; + compatible = "ti,composite-no-wait-gate-clock"; + clocks = <&corex2_fck>; + ti,bit-shift = <0>; + reg = <0x0a00>; + }; + + ssi_ssr_div_fck_3430es2: ssi_ssr_div_fck_3430es2 { + #clock-cells = <0>; + compatible = "ti,composite-divider-clock"; + clocks = <&corex2_fck>; + ti,bit-shift = <8>; + reg = <0x0a40>; + ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>; + }; + + ssi_ssr_fck_3430es2: ssi_ssr_fck_3430es2 { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&ssi_ssr_gate_fck_3430es2>, <&ssi_ssr_div_fck_3430es2>; + }; + + ssi_sst_fck_3430es2: ssi_sst_fck_3430es2 { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&ssi_ssr_fck_3430es2>; + clock-mult = <1>; + clock-div = <2>; + }; + + hsotgusb_ick_3430es2: hsotgusb_ick_3430es2 { + #clock-cells = <0>; + compatible = "ti,omap3-hsotgusb-interface-clock"; + clocks = <&core_l3_ick>; + reg = <0x0a10>; + ti,bit-shift = <4>; + }; + + ssi_l4_ick: ssi_l4_ick { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&l4_ick>; + clock-mult = <1>; + clock-div = <1>; + }; + + ssi_ick_3430es2: ssi_ick_3430es2 { + #clock-cells = <0>; + compatible = "ti,omap3-ssi-interface-clock"; + clocks = <&ssi_l4_ick>; + reg = <0x0a10>; + ti,bit-shift = <0>; + }; + + usim_gate_fck: usim_gate_fck { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clocks = <&omap_96m_fck>; + ti,bit-shift = <9>; + reg = <0x0c00>; + }; + + sys_d2_ck: sys_d2_ck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&sys_ck>; + clock-mult = <1>; + clock-div = <2>; + }; + + omap_96m_d2_fck: omap_96m_d2_fck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&omap_96m_fck>; + clock-mult = <1>; + clock-div = <2>; + }; + + omap_96m_d4_fck: omap_96m_d4_fck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&omap_96m_fck>; + clock-mult = <1>; + clock-div = <4>; + }; + + omap_96m_d8_fck: omap_96m_d8_fck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&omap_96m_fck>; + clock-mult = <1>; + clock-div = <8>; + }; + + omap_96m_d10_fck: omap_96m_d10_fck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&omap_96m_fck>; + clock-mult = <1>; + clock-div = <10>; + }; + + dpll5_m2_d4_ck: dpll5_m2_d4_ck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll5_m2_ck>; + clock-mult = <1>; + clock-div = <4>; + }; + + dpll5_m2_d8_ck: dpll5_m2_d8_ck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll5_m2_ck>; + clock-mult = <1>; + clock-div = <8>; + }; + + dpll5_m2_d16_ck: dpll5_m2_d16_ck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll5_m2_ck>; + clock-mult = <1>; + clock-div = <16>; + }; + + dpll5_m2_d20_ck: dpll5_m2_d20_ck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll5_m2_ck>; + clock-mult = <1>; + clock-div = <20>; + }; + + usim_mux_fck: usim_mux_fck { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clocks = <&sys_ck>, <&sys_d2_ck>, <&omap_96m_d2_fck>, <&omap_96m_d4_fck>, <&omap_96m_d8_fck>, <&omap_96m_d10_fck>, <&dpll5_m2_d4_ck>, <&dpll5_m2_d8_ck>, <&dpll5_m2_d16_ck>, <&dpll5_m2_d20_ck>; + ti,bit-shift = <3>; + reg = <0x0c40>; + ti,index-starts-at-one; + }; + + usim_fck: usim_fck { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&usim_gate_fck>, <&usim_mux_fck>; + }; + + usim_ick: usim_ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&wkup_l4_ick>; + reg = <0x0c10>; + ti,bit-shift = <9>; + }; +}; + +&cm_clockdomains { + core_l3_clkdm: core_l3_clkdm { + compatible = "ti,clockdomain"; + clocks = <&sdrc_ick>, <&hsotgusb_ick_3430es2>; + }; + + wkup_clkdm: wkup_clkdm { + compatible = "ti,clockdomain"; + clocks = <&gpio1_dbck>, <&wdt2_fck>, <&wdt2_ick>, <&wdt1_ick>, + <&gpio1_ick>, <&omap_32ksync_ick>, <&gpt12_ick>, + <&gpt1_ick>, <&usim_ick>; + }; + + core_l4_clkdm: core_l4_clkdm { + compatible = "ti,clockdomain"; + clocks = <&cpefuse_fck>, <&ts_fck>, <&usbtll_fck>, + <&usbtll_ick>, <&mmchs3_ick>, <&mmchs3_fck>, + <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>, + <&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>, + <&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>, + <&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>, + <&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>, + <&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>, + <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>, + <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>, + <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>, + <&ssi_ick_3430es2>; + }; +}; diff --git a/arch/arm/boot/dts/omap36xx.dtsi b/arch/arm/boot/dts/omap36xx.dtsi index 380c22eb468e..55ebaaa358b1 100644 --- a/arch/arm/boot/dts/omap36xx.dtsi +++ b/arch/arm/boot/dts/omap36xx.dtsi @@ -40,3 +40,8 @@ }; }; }; + +/include/ "omap36xx-clocks.dtsi" +/include/ "omap34xx-omap36xx-clocks.dtsi" +/include/ "omap36xx-omap3430es2plus-clocks.dtsi" +/include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi" \ No newline at end of file diff --git a/arch/arm/boot/dts/omap3xxx-clocks.dtsi b/arch/arm/boot/dts/omap3xxx-clocks.dtsi new file mode 100644 index 000000000000..cb04d4b37e7f --- /dev/null +++ b/arch/arm/boot/dts/omap3xxx-clocks.dtsi @@ -0,0 +1,1660 @@ +/* + * Device Tree Source for OMAP3 clock data + * + * Copyright (C) 2013 Texas Instruments, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +&prm_clocks { + virt_16_8m_ck: virt_16_8m_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <16800000>; + }; + + osc_sys_ck: osc_sys_ck { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&virt_12m_ck>, <&virt_13m_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_38_4m_ck>, <&virt_16_8m_ck>; + reg = <0x0d40>; + }; + + sys_ck: sys_ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&osc_sys_ck>; + ti,bit-shift = <6>; + ti,max-div = <3>; + reg = <0x1270>; + ti,index-starts-at-one; + }; + + sys_clkout1: sys_clkout1 { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&osc_sys_ck>; + reg = <0x0d70>; + ti,bit-shift = <7>; + }; + + dpll3_x2_ck: dpll3_x2_ck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll3_ck>; + clock-mult = <2>; + clock-div = <1>; + }; + + dpll3_m2x2_ck: dpll3_m2x2_ck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll3_m2_ck>; + clock-mult = <2>; + clock-div = <1>; + }; + + dpll4_x2_ck: dpll4_x2_ck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll4_ck>; + clock-mult = <2>; + clock-div = <1>; + }; + + corex2_fck: corex2_fck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll3_m2x2_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + wkup_l4_ick: wkup_l4_ick { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&sys_ck>; + clock-mult = <1>; + clock-div = <1>; + }; +}; +&scrm_clocks { + mcbsp5_mux_fck: mcbsp5_mux_fck { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clocks = <&core_96m_fck>, <&mcbsp_clks>; + ti,bit-shift = <4>; + reg = <0x02d8>; + }; + + mcbsp5_fck: mcbsp5_fck { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&mcbsp5_gate_fck>, <&mcbsp5_mux_fck>; + }; + + mcbsp1_mux_fck: mcbsp1_mux_fck { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clocks = <&core_96m_fck>, <&mcbsp_clks>; + ti,bit-shift = <2>; + reg = <0x0274>; + }; + + mcbsp1_fck: mcbsp1_fck { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&mcbsp1_gate_fck>, <&mcbsp1_mux_fck>; + }; + + mcbsp2_mux_fck: mcbsp2_mux_fck { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clocks = <&per_96m_fck>, <&mcbsp_clks>; + ti,bit-shift = <6>; + reg = <0x0274>; + }; + + mcbsp2_fck: mcbsp2_fck { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&mcbsp2_gate_fck>, <&mcbsp2_mux_fck>; + }; + + mcbsp3_mux_fck: mcbsp3_mux_fck { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clocks = <&per_96m_fck>, <&mcbsp_clks>; + reg = <0x02d8>; + }; + + mcbsp3_fck: mcbsp3_fck { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&mcbsp3_gate_fck>, <&mcbsp3_mux_fck>; + }; + + mcbsp4_mux_fck: mcbsp4_mux_fck { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clocks = <&per_96m_fck>, <&mcbsp_clks>; + ti,bit-shift = <2>; + reg = <0x02d8>; + }; + + mcbsp4_fck: mcbsp4_fck { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&mcbsp4_gate_fck>, <&mcbsp4_mux_fck>; + }; +}; +&cm_clocks { + dummy_apb_pclk: dummy_apb_pclk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0x0>; + }; + + omap_32k_fck: omap_32k_fck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + }; + + virt_12m_ck: virt_12m_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <12000000>; + }; + + virt_13m_ck: virt_13m_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <13000000>; + }; + + virt_19200000_ck: virt_19200000_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <19200000>; + }; + + virt_26000000_ck: virt_26000000_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <26000000>; + }; + + virt_38_4m_ck: virt_38_4m_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <38400000>; + }; + + dpll4_ck: dpll4_ck { + #clock-cells = <0>; + compatible = "ti,omap3-dpll-per-clock"; + clocks = <&sys_ck>, <&sys_ck>; + reg = <0x0d00>, <0x0d20>, <0x0d44>, <0x0d30>; + }; + + dpll4_m2_ck: dpll4_m2_ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll4_ck>; + ti,max-div = <63>; + reg = <0x0d48>; + ti,index-starts-at-one; + }; + + dpll4_m2x2_mul_ck: dpll4_m2x2_mul_ck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll4_m2_ck>; + clock-mult = <2>; + clock-div = <1>; + }; + + dpll4_m2x2_ck: dpll4_m2x2_ck { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&dpll4_m2x2_mul_ck>; + ti,bit-shift = <0x1b>; + reg = <0x0d00>; + ti,set-bit-to-disable; + }; + + omap_96m_alwon_fck: omap_96m_alwon_fck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll4_m2x2_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + dpll3_ck: dpll3_ck { + #clock-cells = <0>; + compatible = "ti,omap3-dpll-core-clock"; + clocks = <&sys_ck>, <&sys_ck>; + reg = <0x0d00>, <0x0d20>, <0x0d40>, <0x0d30>; + }; + + dpll3_m3_ck: dpll3_m3_ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll3_ck>; + ti,bit-shift = <16>; + ti,max-div = <31>; + reg = <0x1140>; + ti,index-starts-at-one; + }; + + dpll3_m3x2_mul_ck: dpll3_m3x2_mul_ck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll3_m3_ck>; + clock-mult = <2>; + clock-div = <1>; + }; + + dpll3_m3x2_ck: dpll3_m3x2_ck { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&dpll3_m3x2_mul_ck>; + ti,bit-shift = <0xc>; + reg = <0x0d00>; + ti,set-bit-to-disable; + }; + + emu_core_alwon_ck: emu_core_alwon_ck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll3_m3x2_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + sys_altclk: sys_altclk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0x0>; + }; + + mcbsp_clks: mcbsp_clks { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0x0>; + }; + + dpll3_m2_ck: dpll3_m2_ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll3_ck>; + ti,bit-shift = <27>; + ti,max-div = <31>; + reg = <0x0d40>; + ti,index-starts-at-one; + }; + + core_ck: core_ck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll3_m2_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + dpll1_fck: dpll1_fck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&core_ck>; + ti,bit-shift = <19>; + ti,max-div = <7>; + reg = <0x0940>; + ti,index-starts-at-one; + }; + + dpll1_ck: dpll1_ck { + #clock-cells = <0>; + compatible = "ti,omap3-dpll-clock"; + clocks = <&sys_ck>, <&dpll1_fck>; + reg = <0x0904>, <0x0924>, <0x0940>, <0x0934>; + }; + + dpll1_x2_ck: dpll1_x2_ck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll1_ck>; + clock-mult = <2>; + clock-div = <1>; + }; + + dpll1_x2m2_ck: dpll1_x2m2_ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll1_x2_ck>; + ti,max-div = <31>; + reg = <0x0944>; + ti,index-starts-at-one; + }; + + cm_96m_fck: cm_96m_fck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&omap_96m_alwon_fck>; + clock-mult = <1>; + clock-div = <1>; + }; + + omap_96m_fck: omap_96m_fck { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&cm_96m_fck>, <&sys_ck>; + ti,bit-shift = <6>; + reg = <0x0d40>; + }; + + dpll4_m3_ck: dpll4_m3_ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll4_ck>; + ti,bit-shift = <8>; + ti,max-div = <32>; + reg = <0x0e40>; + ti,index-starts-at-one; + }; + + dpll4_m3x2_mul_ck: dpll4_m3x2_mul_ck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll4_m3_ck>; + clock-mult = <2>; + clock-div = <1>; + }; + + dpll4_m3x2_ck: dpll4_m3x2_ck { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&dpll4_m3x2_mul_ck>; + ti,bit-shift = <0x1c>; + reg = <0x0d00>; + ti,set-bit-to-disable; + }; + + omap_54m_fck: omap_54m_fck { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&dpll4_m3x2_ck>, <&sys_altclk>; + ti,bit-shift = <5>; + reg = <0x0d40>; + }; + + cm_96m_d2_fck: cm_96m_d2_fck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&cm_96m_fck>; + clock-mult = <1>; + clock-div = <2>; + }; + + omap_48m_fck: omap_48m_fck { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&cm_96m_d2_fck>, <&sys_altclk>; + ti,bit-shift = <3>; + reg = <0x0d40>; + }; + + omap_12m_fck: omap_12m_fck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&omap_48m_fck>; + clock-mult = <1>; + clock-div = <4>; + }; + + dpll4_m4_ck: dpll4_m4_ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll4_ck>; + ti,max-div = <32>; + reg = <0x0e40>; + ti,index-starts-at-one; + }; + + dpll4_m4x2_mul_ck: dpll4_m4x2_mul_ck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll4_m4_ck>; + clock-mult = <2>; + clock-div = <1>; + }; + + dpll4_m4x2_ck: dpll4_m4x2_ck { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&dpll4_m4x2_mul_ck>; + ti,bit-shift = <0x1d>; + reg = <0x0d00>; + ti,set-bit-to-disable; + }; + + dpll4_m5_ck: dpll4_m5_ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll4_ck>; + ti,max-div = <63>; + reg = <0x0f40>; + ti,index-starts-at-one; + }; + + dpll4_m5x2_mul_ck: dpll4_m5x2_mul_ck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll4_m5_ck>; + clock-mult = <2>; + clock-div = <1>; + }; + + dpll4_m5x2_ck: dpll4_m5x2_ck { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&dpll4_m5x2_mul_ck>; + ti,bit-shift = <0x1e>; + reg = <0x0d00>; + ti,set-bit-to-disable; + }; + + dpll4_m6_ck: dpll4_m6_ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll4_ck>; + ti,bit-shift = <24>; + ti,max-div = <63>; + reg = <0x1140>; + ti,index-starts-at-one; + }; + + dpll4_m6x2_mul_ck: dpll4_m6x2_mul_ck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll4_m6_ck>; + clock-mult = <2>; + clock-div = <1>; + }; + + dpll4_m6x2_ck: dpll4_m6x2_ck { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&dpll4_m6x2_mul_ck>; + ti,bit-shift = <0x1f>; + reg = <0x0d00>; + ti,set-bit-to-disable; + }; + + emu_per_alwon_ck: emu_per_alwon_ck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll4_m6x2_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + clkout2_src_gate_ck: clkout2_src_gate_ck { + #clock-cells = <0>; + compatible = "ti,composite-no-wait-gate-clock"; + clocks = <&core_ck>; + ti,bit-shift = <7>; + reg = <0x0d70>; + }; + + clkout2_src_mux_ck: clkout2_src_mux_ck { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clocks = <&core_ck>, <&sys_ck>, <&cm_96m_fck>, <&omap_54m_fck>; + reg = <0x0d70>; + }; + + clkout2_src_ck: clkout2_src_ck { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&clkout2_src_gate_ck>, <&clkout2_src_mux_ck>; + }; + + sys_clkout2: sys_clkout2 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&clkout2_src_ck>; + ti,bit-shift = <3>; + ti,max-div = <64>; + reg = <0x0d70>; + ti,index-power-of-two; + }; + + mpu_ck: mpu_ck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll1_x2m2_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + arm_fck: arm_fck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&mpu_ck>; + reg = <0x0924>; + ti,max-div = <2>; + }; + + emu_mpu_alwon_ck: emu_mpu_alwon_ck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&mpu_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + l3_ick: l3_ick { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&core_ck>; + ti,max-div = <3>; + reg = <0x0a40>; + ti,index-starts-at-one; + }; + + l4_ick: l4_ick { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&l3_ick>; + ti,bit-shift = <2>; + ti,max-div = <3>; + reg = <0x0a40>; + ti,index-starts-at-one; + }; + + rm_ick: rm_ick { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&l4_ick>; + ti,bit-shift = <1>; + ti,max-div = <3>; + reg = <0x0c40>; + ti,index-starts-at-one; + }; + + gpt10_gate_fck: gpt10_gate_fck { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clocks = <&sys_ck>; + ti,bit-shift = <11>; + reg = <0x0a00>; + }; + + gpt10_mux_fck: gpt10_mux_fck { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clocks = <&omap_32k_fck>, <&sys_ck>; + ti,bit-shift = <6>; + reg = <0x0a40>; + }; + + gpt10_fck: gpt10_fck { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&gpt10_gate_fck>, <&gpt10_mux_fck>; + }; + + gpt11_gate_fck: gpt11_gate_fck { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clocks = <&sys_ck>; + ti,bit-shift = <12>; + reg = <0x0a00>; + }; + + gpt11_mux_fck: gpt11_mux_fck { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clocks = <&omap_32k_fck>, <&sys_ck>; + ti,bit-shift = <7>; + reg = <0x0a40>; + }; + + gpt11_fck: gpt11_fck { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&gpt11_gate_fck>, <&gpt11_mux_fck>; + }; + + core_96m_fck: core_96m_fck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&omap_96m_fck>; + clock-mult = <1>; + clock-div = <1>; + }; + + mmchs2_fck: mmchs2_fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clocks = <&core_96m_fck>; + reg = <0x0a00>; + ti,bit-shift = <25>; + }; + + mmchs1_fck: mmchs1_fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clocks = <&core_96m_fck>; + reg = <0x0a00>; + ti,bit-shift = <24>; + }; + + i2c3_fck: i2c3_fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clocks = <&core_96m_fck>; + reg = <0x0a00>; + ti,bit-shift = <17>; + }; + + i2c2_fck: i2c2_fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clocks = <&core_96m_fck>; + reg = <0x0a00>; + ti,bit-shift = <16>; + }; + + i2c1_fck: i2c1_fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clocks = <&core_96m_fck>; + reg = <0x0a00>; + ti,bit-shift = <15>; + }; + + mcbsp5_gate_fck: mcbsp5_gate_fck { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clocks = <&mcbsp_clks>; + ti,bit-shift = <10>; + reg = <0x0a00>; + }; + + mcbsp1_gate_fck: mcbsp1_gate_fck { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clocks = <&mcbsp_clks>; + ti,bit-shift = <9>; + reg = <0x0a00>; + }; + + core_48m_fck: core_48m_fck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&omap_48m_fck>; + clock-mult = <1>; + clock-div = <1>; + }; + + mcspi4_fck: mcspi4_fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clocks = <&core_48m_fck>; + reg = <0x0a00>; + ti,bit-shift = <21>; + }; + + mcspi3_fck: mcspi3_fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clocks = <&core_48m_fck>; + reg = <0x0a00>; + ti,bit-shift = <20>; + }; + + mcspi2_fck: mcspi2_fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clocks = <&core_48m_fck>; + reg = <0x0a00>; + ti,bit-shift = <19>; + }; + + mcspi1_fck: mcspi1_fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clocks = <&core_48m_fck>; + reg = <0x0a00>; + ti,bit-shift = <18>; + }; + + uart2_fck: uart2_fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clocks = <&core_48m_fck>; + reg = <0x0a00>; + ti,bit-shift = <14>; + }; + + uart1_fck: uart1_fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clocks = <&core_48m_fck>; + reg = <0x0a00>; + ti,bit-shift = <13>; + }; + + core_12m_fck: core_12m_fck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&omap_12m_fck>; + clock-mult = <1>; + clock-div = <1>; + }; + + hdq_fck: hdq_fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clocks = <&core_12m_fck>; + reg = <0x0a00>; + ti,bit-shift = <22>; + }; + + core_l3_ick: core_l3_ick { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&l3_ick>; + clock-mult = <1>; + clock-div = <1>; + }; + + sdrc_ick: sdrc_ick { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clocks = <&core_l3_ick>; + reg = <0x0a10>; + ti,bit-shift = <1>; + }; + + gpmc_fck: gpmc_fck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&core_l3_ick>; + clock-mult = <1>; + clock-div = <1>; + }; + + core_l4_ick: core_l4_ick { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&l4_ick>; + clock-mult = <1>; + clock-div = <1>; + }; + + mmchs2_ick: mmchs2_ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&core_l4_ick>; + reg = <0x0a10>; + ti,bit-shift = <25>; + }; + + mmchs1_ick: mmchs1_ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&core_l4_ick>; + reg = <0x0a10>; + ti,bit-shift = <24>; + }; + + hdq_ick: hdq_ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&core_l4_ick>; + reg = <0x0a10>; + ti,bit-shift = <22>; + }; + + mcspi4_ick: mcspi4_ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&core_l4_ick>; + reg = <0x0a10>; + ti,bit-shift = <21>; + }; + + mcspi3_ick: mcspi3_ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&core_l4_ick>; + reg = <0x0a10>; + ti,bit-shift = <20>; + }; + + mcspi2_ick: mcspi2_ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&core_l4_ick>; + reg = <0x0a10>; + ti,bit-shift = <19>; + }; + + mcspi1_ick: mcspi1_ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&core_l4_ick>; + reg = <0x0a10>; + ti,bit-shift = <18>; + }; + + i2c3_ick: i2c3_ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&core_l4_ick>; + reg = <0x0a10>; + ti,bit-shift = <17>; + }; + + i2c2_ick: i2c2_ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&core_l4_ick>; + reg = <0x0a10>; + ti,bit-shift = <16>; + }; + + i2c1_ick: i2c1_ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&core_l4_ick>; + reg = <0x0a10>; + ti,bit-shift = <15>; + }; + + uart2_ick: uart2_ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&core_l4_ick>; + reg = <0x0a10>; + ti,bit-shift = <14>; + }; + + uart1_ick: uart1_ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&core_l4_ick>; + reg = <0x0a10>; + ti,bit-shift = <13>; + }; + + gpt11_ick: gpt11_ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&core_l4_ick>; + reg = <0x0a10>; + ti,bit-shift = <12>; + }; + + gpt10_ick: gpt10_ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&core_l4_ick>; + reg = <0x0a10>; + ti,bit-shift = <11>; + }; + + mcbsp5_ick: mcbsp5_ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&core_l4_ick>; + reg = <0x0a10>; + ti,bit-shift = <10>; + }; + + mcbsp1_ick: mcbsp1_ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&core_l4_ick>; + reg = <0x0a10>; + ti,bit-shift = <9>; + }; + + omapctrl_ick: omapctrl_ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&core_l4_ick>; + reg = <0x0a10>; + ti,bit-shift = <6>; + }; + + dss_tv_fck: dss_tv_fck { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&omap_54m_fck>; + reg = <0x0e00>; + ti,bit-shift = <2>; + }; + + dss_96m_fck: dss_96m_fck { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&omap_96m_fck>; + reg = <0x0e00>; + ti,bit-shift = <2>; + }; + + dss2_alwon_fck: dss2_alwon_fck { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&sys_ck>; + reg = <0x0e00>; + ti,bit-shift = <1>; + }; + + dummy_ck: dummy_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0>; + }; + + gpt1_gate_fck: gpt1_gate_fck { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clocks = <&sys_ck>; + ti,bit-shift = <0>; + reg = <0x0c00>; + }; + + gpt1_mux_fck: gpt1_mux_fck { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clocks = <&omap_32k_fck>, <&sys_ck>; + reg = <0x0c40>; + }; + + gpt1_fck: gpt1_fck { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&gpt1_gate_fck>, <&gpt1_mux_fck>; + }; + + aes2_ick: aes2_ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&core_l4_ick>; + ti,bit-shift = <28>; + reg = <0x0a10>; + }; + + wkup_32k_fck: wkup_32k_fck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&omap_32k_fck>; + clock-mult = <1>; + clock-div = <1>; + }; + + gpio1_dbck: gpio1_dbck { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&wkup_32k_fck>; + reg = <0x0c00>; + ti,bit-shift = <3>; + }; + + sha12_ick: sha12_ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&core_l4_ick>; + reg = <0x0a10>; + ti,bit-shift = <27>; + }; + + wdt2_fck: wdt2_fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clocks = <&wkup_32k_fck>; + reg = <0x0c00>; + ti,bit-shift = <5>; + }; + + wdt2_ick: wdt2_ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&wkup_l4_ick>; + reg = <0x0c10>; + ti,bit-shift = <5>; + }; + + wdt1_ick: wdt1_ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&wkup_l4_ick>; + reg = <0x0c10>; + ti,bit-shift = <4>; + }; + + gpio1_ick: gpio1_ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&wkup_l4_ick>; + reg = <0x0c10>; + ti,bit-shift = <3>; + }; + + omap_32ksync_ick: omap_32ksync_ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&wkup_l4_ick>; + reg = <0x0c10>; + ti,bit-shift = <2>; + }; + + gpt12_ick: gpt12_ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&wkup_l4_ick>; + reg = <0x0c10>; + ti,bit-shift = <1>; + }; + + gpt1_ick: gpt1_ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&wkup_l4_ick>; + reg = <0x0c10>; + ti,bit-shift = <0>; + }; + + per_96m_fck: per_96m_fck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&omap_96m_alwon_fck>; + clock-mult = <1>; + clock-div = <1>; + }; + + per_48m_fck: per_48m_fck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&omap_48m_fck>; + clock-mult = <1>; + clock-div = <1>; + }; + + uart3_fck: uart3_fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clocks = <&per_48m_fck>; + reg = <0x1000>; + ti,bit-shift = <11>; + }; + + gpt2_gate_fck: gpt2_gate_fck { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clocks = <&sys_ck>; + ti,bit-shift = <3>; + reg = <0x1000>; + }; + + gpt2_mux_fck: gpt2_mux_fck { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clocks = <&omap_32k_fck>, <&sys_ck>; + reg = <0x1040>; + }; + + gpt2_fck: gpt2_fck { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&gpt2_gate_fck>, <&gpt2_mux_fck>; + }; + + gpt3_gate_fck: gpt3_gate_fck { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clocks = <&sys_ck>; + ti,bit-shift = <4>; + reg = <0x1000>; + }; + + gpt3_mux_fck: gpt3_mux_fck { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clocks = <&omap_32k_fck>, <&sys_ck>; + ti,bit-shift = <1>; + reg = <0x1040>; + }; + + gpt3_fck: gpt3_fck { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&gpt3_gate_fck>, <&gpt3_mux_fck>; + }; + + gpt4_gate_fck: gpt4_gate_fck { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clocks = <&sys_ck>; + ti,bit-shift = <5>; + reg = <0x1000>; + }; + + gpt4_mux_fck: gpt4_mux_fck { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clocks = <&omap_32k_fck>, <&sys_ck>; + ti,bit-shift = <2>; + reg = <0x1040>; + }; + + gpt4_fck: gpt4_fck { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&gpt4_gate_fck>, <&gpt4_mux_fck>; + }; + + gpt5_gate_fck: gpt5_gate_fck { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clocks = <&sys_ck>; + ti,bit-shift = <6>; + reg = <0x1000>; + }; + + gpt5_mux_fck: gpt5_mux_fck { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clocks = <&omap_32k_fck>, <&sys_ck>; + ti,bit-shift = <3>; + reg = <0x1040>; + }; + + gpt5_fck: gpt5_fck { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&gpt5_gate_fck>, <&gpt5_mux_fck>; + }; + + gpt6_gate_fck: gpt6_gate_fck { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clocks = <&sys_ck>; + ti,bit-shift = <7>; + reg = <0x1000>; + }; + + gpt6_mux_fck: gpt6_mux_fck { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clocks = <&omap_32k_fck>, <&sys_ck>; + ti,bit-shift = <4>; + reg = <0x1040>; + }; + + gpt6_fck: gpt6_fck { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&gpt6_gate_fck>, <&gpt6_mux_fck>; + }; + + gpt7_gate_fck: gpt7_gate_fck { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clocks = <&sys_ck>; + ti,bit-shift = <8>; + reg = <0x1000>; + }; + + gpt7_mux_fck: gpt7_mux_fck { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clocks = <&omap_32k_fck>, <&sys_ck>; + ti,bit-shift = <5>; + reg = <0x1040>; + }; + + gpt7_fck: gpt7_fck { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&gpt7_gate_fck>, <&gpt7_mux_fck>; + }; + + gpt8_gate_fck: gpt8_gate_fck { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clocks = <&sys_ck>; + ti,bit-shift = <9>; + reg = <0x1000>; + }; + + gpt8_mux_fck: gpt8_mux_fck { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clocks = <&omap_32k_fck>, <&sys_ck>; + ti,bit-shift = <6>; + reg = <0x1040>; + }; + + gpt8_fck: gpt8_fck { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&gpt8_gate_fck>, <&gpt8_mux_fck>; + }; + + gpt9_gate_fck: gpt9_gate_fck { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clocks = <&sys_ck>; + ti,bit-shift = <10>; + reg = <0x1000>; + }; + + gpt9_mux_fck: gpt9_mux_fck { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clocks = <&omap_32k_fck>, <&sys_ck>; + ti,bit-shift = <7>; + reg = <0x1040>; + }; + + gpt9_fck: gpt9_fck { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&gpt9_gate_fck>, <&gpt9_mux_fck>; + }; + + per_32k_alwon_fck: per_32k_alwon_fck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&omap_32k_fck>; + clock-mult = <1>; + clock-div = <1>; + }; + + gpio6_dbck: gpio6_dbck { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&per_32k_alwon_fck>; + reg = <0x1000>; + ti,bit-shift = <17>; + }; + + gpio5_dbck: gpio5_dbck { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&per_32k_alwon_fck>; + reg = <0x1000>; + ti,bit-shift = <16>; + }; + + gpio4_dbck: gpio4_dbck { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&per_32k_alwon_fck>; + reg = <0x1000>; + ti,bit-shift = <15>; + }; + + gpio3_dbck: gpio3_dbck { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&per_32k_alwon_fck>; + reg = <0x1000>; + ti,bit-shift = <14>; + }; + + gpio2_dbck: gpio2_dbck { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&per_32k_alwon_fck>; + reg = <0x1000>; + ti,bit-shift = <13>; + }; + + wdt3_fck: wdt3_fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clocks = <&per_32k_alwon_fck>; + reg = <0x1000>; + ti,bit-shift = <12>; + }; + + per_l4_ick: per_l4_ick { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&l4_ick>; + clock-mult = <1>; + clock-div = <1>; + }; + + gpio6_ick: gpio6_ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&per_l4_ick>; + reg = <0x1010>; + ti,bit-shift = <17>; + }; + + gpio5_ick: gpio5_ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&per_l4_ick>; + reg = <0x1010>; + ti,bit-shift = <16>; + }; + + gpio4_ick: gpio4_ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&per_l4_ick>; + reg = <0x1010>; + ti,bit-shift = <15>; + }; + + gpio3_ick: gpio3_ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&per_l4_ick>; + reg = <0x1010>; + ti,bit-shift = <14>; + }; + + gpio2_ick: gpio2_ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&per_l4_ick>; + reg = <0x1010>; + ti,bit-shift = <13>; + }; + + wdt3_ick: wdt3_ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&per_l4_ick>; + reg = <0x1010>; + ti,bit-shift = <12>; + }; + + uart3_ick: uart3_ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&per_l4_ick>; + reg = <0x1010>; + ti,bit-shift = <11>; + }; + + uart4_ick: uart4_ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&per_l4_ick>; + reg = <0x1010>; + ti,bit-shift = <18>; + }; + + gpt9_ick: gpt9_ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&per_l4_ick>; + reg = <0x1010>; + ti,bit-shift = <10>; + }; + + gpt8_ick: gpt8_ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&per_l4_ick>; + reg = <0x1010>; + ti,bit-shift = <9>; + }; + + gpt7_ick: gpt7_ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&per_l4_ick>; + reg = <0x1010>; + ti,bit-shift = <8>; + }; + + gpt6_ick: gpt6_ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&per_l4_ick>; + reg = <0x1010>; + ti,bit-shift = <7>; + }; + + gpt5_ick: gpt5_ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&per_l4_ick>; + reg = <0x1010>; + ti,bit-shift = <6>; + }; + + gpt4_ick: gpt4_ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&per_l4_ick>; + reg = <0x1010>; + ti,bit-shift = <5>; + }; + + gpt3_ick: gpt3_ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&per_l4_ick>; + reg = <0x1010>; + ti,bit-shift = <4>; + }; + + gpt2_ick: gpt2_ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&per_l4_ick>; + reg = <0x1010>; + ti,bit-shift = <3>; + }; + + mcbsp2_ick: mcbsp2_ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&per_l4_ick>; + reg = <0x1010>; + ti,bit-shift = <0>; + }; + + mcbsp3_ick: mcbsp3_ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&per_l4_ick>; + reg = <0x1010>; + ti,bit-shift = <1>; + }; + + mcbsp4_ick: mcbsp4_ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&per_l4_ick>; + reg = <0x1010>; + ti,bit-shift = <2>; + }; + + mcbsp2_gate_fck: mcbsp2_gate_fck { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clocks = <&mcbsp_clks>; + ti,bit-shift = <0>; + reg = <0x1000>; + }; + + mcbsp3_gate_fck: mcbsp3_gate_fck { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clocks = <&mcbsp_clks>; + ti,bit-shift = <1>; + reg = <0x1000>; + }; + + mcbsp4_gate_fck: mcbsp4_gate_fck { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clocks = <&mcbsp_clks>; + ti,bit-shift = <2>; + reg = <0x1000>; + }; + + emu_src_mux_ck: emu_src_mux_ck { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&sys_ck>, <&emu_core_alwon_ck>, <&emu_per_alwon_ck>, <&emu_mpu_alwon_ck>; + reg = <0x1140>; + }; + + emu_src_ck: emu_src_ck { + #clock-cells = <0>; + compatible = "ti,clkdm-gate-clock"; + clocks = <&emu_src_mux_ck>; + }; + + pclk_fck: pclk_fck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&emu_src_ck>; + ti,bit-shift = <8>; + ti,max-div = <7>; + reg = <0x1140>; + ti,index-starts-at-one; + }; + + pclkx2_fck: pclkx2_fck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&emu_src_ck>; + ti,bit-shift = <6>; + ti,max-div = <3>; + reg = <0x1140>; + ti,index-starts-at-one; + }; + + atclk_fck: atclk_fck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&emu_src_ck>; + ti,bit-shift = <4>; + ti,max-div = <3>; + reg = <0x1140>; + ti,index-starts-at-one; + }; + + traceclk_src_fck: traceclk_src_fck { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&sys_ck>, <&emu_core_alwon_ck>, <&emu_per_alwon_ck>, <&emu_mpu_alwon_ck>; + ti,bit-shift = <2>; + reg = <0x1140>; + }; + + traceclk_fck: traceclk_fck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&traceclk_src_fck>; + ti,bit-shift = <11>; + ti,max-div = <7>; + reg = <0x1140>; + ti,index-starts-at-one; + }; + + secure_32k_fck: secure_32k_fck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + }; + + gpt12_fck: gpt12_fck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&secure_32k_fck>; + clock-mult = <1>; + clock-div = <1>; + }; + + wdt1_fck: wdt1_fck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&secure_32k_fck>; + clock-mult = <1>; + clock-div = <1>; + }; +}; + +&cm_clockdomains { + core_l3_clkdm: core_l3_clkdm { + compatible = "ti,clockdomain"; + clocks = <&sdrc_ick>; + }; + + dpll3_clkdm: dpll3_clkdm { + compatible = "ti,clockdomain"; + clocks = <&dpll3_ck>; + }; + + dpll1_clkdm: dpll1_clkdm { + compatible = "ti,clockdomain"; + clocks = <&dpll1_ck>; + }; + + per_clkdm: per_clkdm { + compatible = "ti,clockdomain"; + clocks = <&uart3_fck>, <&gpio6_dbck>, <&gpio5_dbck>, + <&gpio4_dbck>, <&gpio3_dbck>, <&gpio2_dbck>, + <&wdt3_fck>, <&gpio6_ick>, <&gpio5_ick>, <&gpio4_ick>, + <&gpio3_ick>, <&gpio2_ick>, <&wdt3_ick>, <&uart3_ick>, + <&uart4_ick>, <&gpt9_ick>, <&gpt8_ick>, <&gpt7_ick>, + <&gpt6_ick>, <&gpt5_ick>, <&gpt4_ick>, <&gpt3_ick>, + <&gpt2_ick>, <&mcbsp2_ick>, <&mcbsp3_ick>, + <&mcbsp4_ick>; + }; + + emu_clkdm: emu_clkdm { + compatible = "ti,clockdomain"; + clocks = <&emu_src_ck>; + }; + + dpll4_clkdm: dpll4_clkdm { + compatible = "ti,clockdomain"; + clocks = <&dpll4_ck>; + }; + + wkup_clkdm: wkup_clkdm { + compatible = "ti,clockdomain"; + clocks = <&gpio1_dbck>, <&wdt2_fck>, <&wdt2_ick>, <&wdt1_ick>, + <&gpio1_ick>, <&omap_32ksync_ick>, <&gpt12_ick>, + <&gpt1_ick>; + }; + + dss_clkdm: dss_clkdm { + compatible = "ti,clockdomain"; + clocks = <&dss_tv_fck>, <&dss_96m_fck>, <&dss2_alwon_fck>; + }; + + core_l4_clkdm: core_l4_clkdm { + compatible = "ti,clockdomain"; + clocks = <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>, + <&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>, + <&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>, + <&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>, + <&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>, + <&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>, + <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>, + <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>, + <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>; + }; +}; -- cgit v1.2.3-59-g8ed1b From fdff8a1f136c730259b1e55c07b1c090ef07af47 Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Thu, 25 Jul 2013 11:28:54 +0300 Subject: ARM: dts: AM35xx: use DT clock data AM35xx now uses the clock data from device tree. Most of the data is shared with OMAP3xxx, but as there is some delta, a new base .dtsi file is also created for the SoC. Signed-off-by: Tero Kristo Acked-by: Tony Lindgren Signed-off-by: Mike Turquette --- arch/arm/boot/dts/am3517.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/boot/dts/am3517.dtsi b/arch/arm/boot/dts/am3517.dtsi index 2fbe02faa8b1..788391f91684 100644 --- a/arch/arm/boot/dts/am3517.dtsi +++ b/arch/arm/boot/dts/am3517.dtsi @@ -61,3 +61,6 @@ }; }; }; + +/include/ "am35xx-clocks.dtsi" +/include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi" -- cgit v1.2.3-59-g8ed1b From 6a67920811c23320aa25d94e5891d229eab506d9 Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Fri, 2 Aug 2013 19:12:04 +0300 Subject: ARM: dts: am43xx clock data This patch creates a unique node for each clock in the AM43xx power, reset and clock manager (PRCM). Signed-off-by: Tero Kristo Acked-by: Tony Lindgren Signed-off-by: Mike Turquette --- arch/arm/boot/dts/am4372.dtsi | 28 ++ arch/arm/boot/dts/am43xx-clocks.dtsi | 656 +++++++++++++++++++++++++++++++++++ 2 files changed, 684 insertions(+) create mode 100644 arch/arm/boot/dts/am43xx-clocks.dtsi diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi index 974d103ab3b1..c6bd4d986c29 100644 --- a/arch/arm/boot/dts/am4372.dtsi +++ b/arch/arm/boot/dts/am4372.dtsi @@ -67,6 +67,32 @@ ranges; ti,hwmods = "l3_main"; + prcm: prcm@44df0000 { + compatible = "ti,am4-prcm"; + reg = <0x44df0000 0x11000>; + + prcm_clocks: clocks { + #address-cells = <1>; + #size-cells = <0>; + }; + + prcm_clockdomains: clockdomains { + }; + }; + + scrm: scrm@44e10000 { + compatible = "ti,am4-scrm"; + reg = <0x44e10000 0x2000>; + + scrm_clocks: clocks { + #address-cells = <1>; + #size-cells = <0>; + }; + + scrm_clockdomains: clockdomains { + }; + }; + edma: edma@49000000 { compatible = "ti,edma3"; ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2"; @@ -665,3 +691,5 @@ }; }; }; + +/include/ "am43xx-clocks.dtsi" diff --git a/arch/arm/boot/dts/am43xx-clocks.dtsi b/arch/arm/boot/dts/am43xx-clocks.dtsi new file mode 100644 index 000000000000..142009cc9332 --- /dev/null +++ b/arch/arm/boot/dts/am43xx-clocks.dtsi @@ -0,0 +1,656 @@ +/* + * Device Tree Source for AM43xx clock data + * + * Copyright (C) 2013 Texas Instruments, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +&scrm_clocks { + sys_clkin_ck: sys_clkin_ck { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>; + ti,bit-shift = <22>; + reg = <0x0040>; + }; + + adc_tsc_fck: adc_tsc_fck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&sys_clkin_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + dcan0_fck: dcan0_fck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&sys_clkin_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + dcan1_fck: dcan1_fck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&sys_clkin_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + mcasp0_fck: mcasp0_fck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&sys_clkin_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + mcasp1_fck: mcasp1_fck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&sys_clkin_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + smartreflex0_fck: smartreflex0_fck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&sys_clkin_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + smartreflex1_fck: smartreflex1_fck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&sys_clkin_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + sha0_fck: sha0_fck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&sys_clkin_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + aes0_fck: aes0_fck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&sys_clkin_ck>; + clock-mult = <1>; + clock-div = <1>; + }; +}; +&prcm_clocks { + clk_32768_ck: clk_32768_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + }; + + clk_rc32k_ck: clk_rc32k_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + }; + + virt_19200000_ck: virt_19200000_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <19200000>; + }; + + virt_24000000_ck: virt_24000000_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + }; + + virt_25000000_ck: virt_25000000_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <25000000>; + }; + + virt_26000000_ck: virt_26000000_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <26000000>; + }; + + tclkin_ck: tclkin_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <26000000>; + }; + + dpll_core_ck: dpll_core_ck { + #clock-cells = <0>; + compatible = "ti,am3-dpll-core-clock"; + clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; + reg = <0x2d20>, <0x2d24>, <0x2d2c>; + }; + + dpll_core_x2_ck: dpll_core_x2_ck { + #clock-cells = <0>; + compatible = "ti,am3-dpll-x2-clock"; + clocks = <&dpll_core_ck>; + }; + + dpll_core_m4_ck: dpll_core_m4_ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll_core_x2_ck>; + ti,max-div = <31>; + ti,autoidle-shift = <8>; + reg = <0x2d38>; + ti,index-starts-at-one; + ti,invert-autoidle-bit; + }; + + dpll_core_m5_ck: dpll_core_m5_ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll_core_x2_ck>; + ti,max-div = <31>; + ti,autoidle-shift = <8>; + reg = <0x2d3c>; + ti,index-starts-at-one; + ti,invert-autoidle-bit; + }; + + dpll_core_m6_ck: dpll_core_m6_ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll_core_x2_ck>; + ti,max-div = <31>; + ti,autoidle-shift = <8>; + reg = <0x2d40>; + ti,index-starts-at-one; + ti,invert-autoidle-bit; + }; + + dpll_mpu_ck: dpll_mpu_ck { + #clock-cells = <0>; + compatible = "ti,am3-dpll-clock"; + clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; + reg = <0x2d60>, <0x2d64>, <0x2d6c>; + }; + + dpll_mpu_m2_ck: dpll_mpu_m2_ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll_mpu_ck>; + ti,max-div = <31>; + ti,autoidle-shift = <8>; + reg = <0x2d70>; + ti,index-starts-at-one; + ti,invert-autoidle-bit; + }; + + dpll_ddr_ck: dpll_ddr_ck { + #clock-cells = <0>; + compatible = "ti,am3-dpll-clock"; + clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; + reg = <0x2da0>, <0x2da4>, <0x2dac>; + }; + + dpll_ddr_m2_ck: dpll_ddr_m2_ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll_ddr_ck>; + ti,max-div = <31>; + ti,autoidle-shift = <8>; + reg = <0x2db0>; + ti,index-starts-at-one; + ti,invert-autoidle-bit; + }; + + dpll_disp_ck: dpll_disp_ck { + #clock-cells = <0>; + compatible = "ti,am3-dpll-clock"; + clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; + reg = <0x2e20>, <0x2e24>, <0x2e2c>; + }; + + dpll_disp_m2_ck: dpll_disp_m2_ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll_disp_ck>; + ti,max-div = <31>; + ti,autoidle-shift = <8>; + reg = <0x2e30>; + ti,index-starts-at-one; + ti,invert-autoidle-bit; + }; + + dpll_per_ck: dpll_per_ck { + #clock-cells = <0>; + compatible = "ti,am3-dpll-j-type-clock"; + clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; + reg = <0x2de0>, <0x2de4>, <0x2dec>; + }; + + dpll_per_m2_ck: dpll_per_m2_ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll_per_ck>; + ti,max-div = <127>; + ti,autoidle-shift = <8>; + reg = <0x2df0>; + ti,index-starts-at-one; + ti,invert-autoidle-bit; + }; + + dpll_per_m2_div4_wkupdm_ck: dpll_per_m2_div4_wkupdm_ck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll_per_m2_ck>; + clock-mult = <1>; + clock-div = <4>; + }; + + dpll_per_m2_div4_ck: dpll_per_m2_div4_ck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll_per_m2_ck>; + clock-mult = <1>; + clock-div = <4>; + }; + + clk_24mhz: clk_24mhz { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll_per_m2_ck>; + clock-mult = <1>; + clock-div = <8>; + }; + + clkdiv32k_ck: clkdiv32k_ck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&clk_24mhz>; + clock-mult = <1>; + clock-div = <732>; + }; + + clkdiv32k_ick: clkdiv32k_ick { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&clkdiv32k_ck>; + ti,bit-shift = <8>; + reg = <0x2a38>; + }; + + sysclk_div: sysclk_div { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll_core_m4_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + pruss_ocp_gclk: pruss_ocp_gclk { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&sysclk_div>, <&dpll_disp_m2_ck>; + reg = <0x4248>; + }; + + clk_32k_tpm_ck: clk_32k_tpm_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + }; + + timer1_fck: timer1_fck { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&sys_clkin_ck>, <&clkdiv32k_ick>, <&tclkin_ck>, <&clk_rc32k_ck>, <&clk_32768_ck>, <&clk_32k_tpm_ck>; + reg = <0x4200>; + }; + + timer2_fck: timer2_fck { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; + reg = <0x4204>; + }; + + timer3_fck: timer3_fck { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; + reg = <0x4208>; + }; + + timer4_fck: timer4_fck { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; + reg = <0x420c>; + }; + + timer5_fck: timer5_fck { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; + reg = <0x4210>; + }; + + timer6_fck: timer6_fck { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; + reg = <0x4214>; + }; + + timer7_fck: timer7_fck { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; + reg = <0x4218>; + }; + + wdt1_fck: wdt1_fck { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&clk_rc32k_ck>, <&clkdiv32k_ick>; + reg = <0x422c>; + }; + + l3_gclk: l3_gclk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll_core_m4_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + dpll_core_m4_div2_ck: dpll_core_m4_div2_ck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&sysclk_div>; + clock-mult = <1>; + clock-div = <2>; + }; + + l4hs_gclk: l4hs_gclk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll_core_m4_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + l3s_gclk: l3s_gclk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll_core_m4_div2_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + l4ls_gclk: l4ls_gclk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll_core_m4_div2_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + cpsw_125mhz_gclk: cpsw_125mhz_gclk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll_core_m5_ck>; + clock-mult = <1>; + clock-div = <2>; + }; + + cpsw_cpts_rft_clk: cpsw_cpts_rft_clk { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&sysclk_div>, <&dpll_core_m5_ck>, <&dpll_disp_m2_ck>; + reg = <0x4238>; + }; + + clk_32k_mosc_ck: clk_32k_mosc_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + }; + + gpio0_dbclk_mux_ck: gpio0_dbclk_mux_ck { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&clk_rc32k_ck>, <&clk_32768_ck>, <&clkdiv32k_ick>, <&clk_32k_mosc_ck>, <&clk_32k_tpm_ck>; + reg = <0x4240>; + }; + + gpio0_dbclk: gpio0_dbclk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&gpio0_dbclk_mux_ck>; + ti,bit-shift = <8>; + reg = <0x2b68>; + }; + + gpio1_dbclk: gpio1_dbclk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&clkdiv32k_ick>; + ti,bit-shift = <8>; + reg = <0x8c78>; + }; + + gpio2_dbclk: gpio2_dbclk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&clkdiv32k_ick>; + ti,bit-shift = <8>; + reg = <0x8c80>; + }; + + gpio3_dbclk: gpio3_dbclk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&clkdiv32k_ick>; + ti,bit-shift = <8>; + reg = <0x8c88>; + }; + + gpio4_dbclk: gpio4_dbclk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&clkdiv32k_ick>; + ti,bit-shift = <8>; + reg = <0x8c90>; + }; + + gpio5_dbclk: gpio5_dbclk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&clkdiv32k_ick>; + ti,bit-shift = <8>; + reg = <0x8c98>; + }; + + mmc_clk: mmc_clk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll_per_m2_ck>; + clock-mult = <1>; + clock-div = <2>; + }; + + gfx_fclk_clksel_ck: gfx_fclk_clksel_ck { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&sysclk_div>, <&dpll_per_m2_ck>; + ti,bit-shift = <1>; + reg = <0x423c>; + }; + + gfx_fck_div_ck: gfx_fck_div_ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&gfx_fclk_clksel_ck>; + reg = <0x423c>; + ti,max-div = <2>; + }; + + disp_clk: disp_clk { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&dpll_disp_m2_ck>, <&dpll_core_m5_ck>, <&dpll_per_m2_ck>; + reg = <0x4244>; + }; + + dpll_extdev_ck: dpll_extdev_ck { + #clock-cells = <0>; + compatible = "ti,am3-dpll-clock"; + clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; + reg = <0x2e60>, <0x2e64>, <0x2e6c>; + }; + + dpll_extdev_m2_ck: dpll_extdev_m2_ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll_extdev_ck>; + ti,max-div = <127>; + ti,autoidle-shift = <8>; + reg = <0x2e70>; + ti,index-starts-at-one; + ti,invert-autoidle-bit; + }; + + mux_synctimer32k_ck: mux_synctimer32k_ck { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&clk_32768_ck>, <&clk_32k_tpm_ck>, <&clkdiv32k_ick>; + reg = <0x4230>; + }; + + synctimer_32kclk: synctimer_32kclk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&mux_synctimer32k_ck>; + ti,bit-shift = <8>; + reg = <0x2a30>; + }; + + timer8_fck: timer8_fck { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>; + reg = <0x421c>; + }; + + timer9_fck: timer9_fck { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>; + reg = <0x4220>; + }; + + timer10_fck: timer10_fck { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>; + reg = <0x4224>; + }; + + timer11_fck: timer11_fck { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>; + reg = <0x4228>; + }; + + cpsw_50m_clkdiv: cpsw_50m_clkdiv { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll_core_m5_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + cpsw_5m_clkdiv: cpsw_5m_clkdiv { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&cpsw_50m_clkdiv>; + clock-mult = <1>; + clock-div = <10>; + }; + + dpll_ddr_x2_ck: dpll_ddr_x2_ck { + #clock-cells = <0>; + compatible = "ti,am3-dpll-x2-clock"; + clocks = <&dpll_ddr_ck>; + }; + + dpll_ddr_m4_ck: dpll_ddr_m4_ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll_ddr_x2_ck>; + ti,max-div = <31>; + ti,autoidle-shift = <8>; + reg = <0x2db8>; + ti,index-starts-at-one; + ti,invert-autoidle-bit; + }; + + dpll_per_clkdcoldo: dpll_per_clkdcoldo { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll_per_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + dll_aging_clk_div: dll_aging_clk_div { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&sys_clkin_ck>; + reg = <0x4250>; + ti,dividers = <8>, <16>, <32>; + }; + + div_core_25m_ck: div_core_25m_ck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&sysclk_div>; + clock-mult = <1>; + clock-div = <8>; + }; + + func_12m_clk: func_12m_clk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll_per_m2_ck>; + clock-mult = <1>; + clock-div = <16>; + }; + + vtp_clk_div: vtp_clk_div { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&sys_clkin_ck>; + clock-mult = <1>; + clock-div = <2>; + }; + + usbphy_32khz_clkmux: usbphy_32khz_clkmux { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&clk_32768_ck>, <&clk_32k_tpm_ck>; + reg = <0x4260>; + }; +}; -- cgit v1.2.3-59-g8ed1b From 3ada6b10aaf2ff5c7dc6e8add6fdf1b7333d1b34 Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Tue, 22 Oct 2013 11:47:08 +0300 Subject: ARM: OMAP2+: clock: add support for indexed memmaps Using indexed memmaps is required for isolating the actual memory access from the clock code. Now, the driver providing the support for the clock IP block provides the low level routines for reading/writing clock registers also. Signed-off-by: Tero Kristo Acked-by: Tony Lindgren Signed-off-by: Mike Turquette --- arch/arm/mach-omap2/clock.c | 26 +++++++++++++++++++++++++- arch/arm/mach-omap2/clock.h | 5 +++++ 2 files changed, 30 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c index 238be3f1ddce..be53bb21301c 100644 --- a/arch/arm/mach-omap2/clock.c +++ b/arch/arm/mach-omap2/clock.c @@ -26,7 +26,6 @@ #include #include - #include #include "soc.h" @@ -56,6 +55,31 @@ u16 cpu_mask; static bool clkdm_control = true; static LIST_HEAD(clk_hw_omap_clocks); +void __iomem *clk_memmaps[CLK_MAX_MEMMAPS]; + +void omap2_clk_writel(u32 val, struct clk_hw_omap *clk, void __iomem *reg) +{ + if (clk->flags & MEMMAP_ADDRESSING) { + struct clk_omap_reg *r = (struct clk_omap_reg *)® + writel_relaxed(val, clk_memmaps[r->index] + r->offset); + } else { + writel_relaxed(val, reg); + } +} + +u32 omap2_clk_readl(struct clk_hw_omap *clk, void __iomem *reg) +{ + u32 val; + + if (clk->flags & MEMMAP_ADDRESSING) { + struct clk_omap_reg *r = (struct clk_omap_reg *)® + val = readl_relaxed(clk_memmaps[r->index] + r->offset); + } else { + val = readl_relaxed(reg); + } + + return val; +} /* * Used for clocks that have the same value as the parent clock, diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h index cbe5ff770ec4..bda767a9dea8 100644 --- a/arch/arm/mach-omap2/clock.h +++ b/arch/arm/mach-omap2/clock.h @@ -254,6 +254,9 @@ void omap2_clk_print_new_rates(const char *hfclkin_ck_name, const char *core_ck_name, const char *mpu_ck_name); +u32 omap2_clk_readl(struct clk_hw_omap *clk, void __iomem *reg); +void omap2_clk_writel(u32 val, struct clk_hw_omap *clk, void __iomem *reg); + extern u16 cpu_mask; extern const struct clkops clkops_omap2_dflt_wait; @@ -288,6 +291,8 @@ extern const struct clksel_rate div_1_3_rates[]; extern const struct clksel_rate div_1_4_rates[]; extern const struct clksel_rate div31_1to31_rates[]; +extern void __iomem *clk_memmaps[]; + extern int am33xx_clk_init(void); extern int omap2_clkops_enable_clkdm(struct clk_hw *hw); -- cgit v1.2.3-59-g8ed1b From 519ab8b202f37fb76cc6f32ef34da79716680d03 Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Tue, 22 Oct 2013 11:49:58 +0300 Subject: ARM: OMAP2+: clock: use driver API instead of direct memory read/write Clock nodes shall use the services provided by underlying drivers to access the hardware registers instead of direct memory read/write. Thus, change all the code to use the new omap2_clk_readl / omap2_clk_writel APIs for this. Signed-off-by: Tero Kristo Acked-by: Tony Lindgren Signed-off-by: Mike Turquette --- arch/arm/mach-omap2/clkt_clksel.c | 10 +++++----- arch/arm/mach-omap2/clkt_dpll.c | 6 +++--- arch/arm/mach-omap2/clkt_iclk.c | 20 ++++++++++++-------- arch/arm/mach-omap2/clock.c | 25 +++++++++++++------------ arch/arm/mach-omap2/clock36xx.c | 7 ++++--- arch/arm/mach-omap2/dpll3xxx.c | 37 ++++++++++++++++++++----------------- arch/arm/mach-omap2/dpll44xx.c | 12 ++++++------ 7 files changed, 63 insertions(+), 54 deletions(-) diff --git a/arch/arm/mach-omap2/clkt_clksel.c b/arch/arm/mach-omap2/clkt_clksel.c index 0ec9f6fdf046..7ee26108ac0d 100644 --- a/arch/arm/mach-omap2/clkt_clksel.c +++ b/arch/arm/mach-omap2/clkt_clksel.c @@ -97,12 +97,12 @@ static void _write_clksel_reg(struct clk_hw_omap *clk, u32 field_val) { u32 v; - v = __raw_readl(clk->clksel_reg); + v = omap2_clk_readl(clk, clk->clksel_reg); v &= ~clk->clksel_mask; v |= field_val << __ffs(clk->clksel_mask); - __raw_writel(v, clk->clksel_reg); + omap2_clk_writel(v, clk, clk->clksel_reg); - v = __raw_readl(clk->clksel_reg); /* OCP barrier */ + v = omap2_clk_readl(clk, clk->clksel_reg); /* OCP barrier */ } /** @@ -204,7 +204,7 @@ static u32 _read_divisor(struct clk_hw_omap *clk) if (!clk->clksel || !clk->clksel_mask) return 0; - v = __raw_readl(clk->clksel_reg); + v = omap2_clk_readl(clk, clk->clksel_reg); v &= clk->clksel_mask; v >>= __ffs(clk->clksel_mask); @@ -320,7 +320,7 @@ u8 omap2_clksel_find_parent_index(struct clk_hw *hw) WARN((!clk->clksel || !clk->clksel_mask), "clock: %s: attempt to call on a non-clksel clock", clk_name); - r = __raw_readl(clk->clksel_reg) & clk->clksel_mask; + r = omap2_clk_readl(clk, clk->clksel_reg) & clk->clksel_mask; r >>= __ffs(clk->clksel_mask); for (clks = clk->clksel; clks->parent && !found; clks++) { diff --git a/arch/arm/mach-omap2/clkt_dpll.c b/arch/arm/mach-omap2/clkt_dpll.c index 924c230f8948..47f9562ca7aa 100644 --- a/arch/arm/mach-omap2/clkt_dpll.c +++ b/arch/arm/mach-omap2/clkt_dpll.c @@ -196,7 +196,7 @@ u8 omap2_init_dpll_parent(struct clk_hw *hw) if (!dd) return -EINVAL; - v = __raw_readl(dd->control_reg); + v = omap2_clk_readl(clk, dd->control_reg); v &= dd->enable_mask; v >>= __ffs(dd->enable_mask); @@ -243,7 +243,7 @@ unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk) return 0; /* Return bypass rate if DPLL is bypassed */ - v = __raw_readl(dd->control_reg); + v = omap2_clk_readl(clk, dd->control_reg); v &= dd->enable_mask; v >>= __ffs(dd->enable_mask); @@ -262,7 +262,7 @@ unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk) return __clk_get_rate(dd->clk_bypass); } - v = __raw_readl(dd->mult_div1_reg); + v = omap2_clk_readl(clk, dd->mult_div1_reg); dpll_mult = v & dd->mult_mask; dpll_mult >>= __ffs(dd->mult_mask); dpll_div = v & dd->div1_mask; diff --git a/arch/arm/mach-omap2/clkt_iclk.c b/arch/arm/mach-omap2/clkt_iclk.c index f10eb03ce3e2..333f0a666171 100644 --- a/arch/arm/mach-omap2/clkt_iclk.c +++ b/arch/arm/mach-omap2/clkt_iclk.c @@ -25,25 +25,29 @@ /* XXX */ void omap2_clkt_iclk_allow_idle(struct clk_hw_omap *clk) { - u32 v, r; + u32 v; + void __iomem *r; - r = ((__force u32)clk->enable_reg ^ (CM_AUTOIDLE ^ CM_ICLKEN)); + r = (__force void __iomem *) + ((__force u32)clk->enable_reg ^ (CM_AUTOIDLE ^ CM_ICLKEN)); - v = __raw_readl((__force void __iomem *)r); + v = omap2_clk_readl(clk, r); v |= (1 << clk->enable_bit); - __raw_writel(v, (__force void __iomem *)r); + omap2_clk_writel(v, clk, r); } /* XXX */ void omap2_clkt_iclk_deny_idle(struct clk_hw_omap *clk) { - u32 v, r; + u32 v; + void __iomem *r; - r = ((__force u32)clk->enable_reg ^ (CM_AUTOIDLE ^ CM_ICLKEN)); + r = (__force void __iomem *) + ((__force u32)clk->enable_reg ^ (CM_AUTOIDLE ^ CM_ICLKEN)); - v = __raw_readl((__force void __iomem *)r); + v = omap2_clk_readl(clk, r); v &= ~(1 << clk->enable_bit); - __raw_writel(v, (__force void __iomem *)r); + omap2_clk_writel(v, clk, r); } /* Public data */ diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c index be53bb21301c..591581a66532 100644 --- a/arch/arm/mach-omap2/clock.c +++ b/arch/arm/mach-omap2/clock.c @@ -111,6 +111,7 @@ unsigned long omap_fixed_divisor_recalc(struct clk_hw *hw, /** * _wait_idlest_generic - wait for a module to leave the idle state + * @clk: module clock to wait for (needed for register offsets) * @reg: virtual address of module IDLEST register * @mask: value to mask against to determine if the module is active * @idlest: idle state indicator (0 or 1) for the clock @@ -122,14 +123,14 @@ unsigned long omap_fixed_divisor_recalc(struct clk_hw *hw, * elapsed. XXX Deprecated - should be moved into drivers for the * individual IP block that the IDLEST register exists in. */ -static int _wait_idlest_generic(void __iomem *reg, u32 mask, u8 idlest, - const char *name) +static int _wait_idlest_generic(struct clk_hw_omap *clk, void __iomem *reg, + u32 mask, u8 idlest, const char *name) { int i = 0, ena = 0; ena = (idlest) ? 0 : mask; - omap_test_timeout(((__raw_readl(reg) & mask) == ena), + omap_test_timeout(((omap2_clk_readl(clk, reg) & mask) == ena), MAX_MODULE_ENABLE_WAIT, i); if (i < MAX_MODULE_ENABLE_WAIT) @@ -162,7 +163,7 @@ static void _omap2_module_wait_ready(struct clk_hw_omap *clk) /* Not all modules have multiple clocks that their IDLEST depends on */ if (clk->ops->find_companion) { clk->ops->find_companion(clk, &companion_reg, &other_bit); - if (!(__raw_readl(companion_reg) & (1 << other_bit))) + if (!(omap2_clk_readl(clk, companion_reg) & (1 << other_bit))) return; } @@ -170,8 +171,8 @@ static void _omap2_module_wait_ready(struct clk_hw_omap *clk) r = cm_split_idlest_reg(idlest_reg, &prcm_mod, &idlest_reg_id); if (r) { /* IDLEST register not in the CM module */ - _wait_idlest_generic(idlest_reg, (1 << idlest_bit), idlest_val, - __clk_get_name(clk->hw.clk)); + _wait_idlest_generic(clk, idlest_reg, (1 << idlest_bit), + idlest_val, __clk_get_name(clk->hw.clk)); } else { cm_wait_module_ready(prcm_mod, idlest_reg_id, idlest_bit); }; @@ -333,13 +334,13 @@ int omap2_dflt_clk_enable(struct clk_hw *hw) } /* FIXME should not have INVERT_ENABLE bit here */ - v = __raw_readl(clk->enable_reg); + v = omap2_clk_readl(clk, clk->enable_reg); if (clk->flags & INVERT_ENABLE) v &= ~(1 << clk->enable_bit); else v |= (1 << clk->enable_bit); - __raw_writel(v, clk->enable_reg); - v = __raw_readl(clk->enable_reg); /* OCP barrier */ + omap2_clk_writel(v, clk, clk->enable_reg); + v = omap2_clk_readl(clk, clk->enable_reg); /* OCP barrier */ if (clk->ops && clk->ops->find_idlest) _omap2_module_wait_ready(clk); @@ -377,12 +378,12 @@ void omap2_dflt_clk_disable(struct clk_hw *hw) return; } - v = __raw_readl(clk->enable_reg); + v = omap2_clk_readl(clk, clk->enable_reg); if (clk->flags & INVERT_ENABLE) v |= (1 << clk->enable_bit); else v &= ~(1 << clk->enable_bit); - __raw_writel(v, clk->enable_reg); + omap2_clk_writel(v, clk, clk->enable_reg); /* No OCP barrier needed here since it is a disable operation */ if (clkdm_control && clk->clkdm) @@ -478,7 +479,7 @@ int omap2_dflt_clk_is_enabled(struct clk_hw *hw) struct clk_hw_omap *clk = to_clk_hw_omap(hw); u32 v; - v = __raw_readl(clk->enable_reg); + v = omap2_clk_readl(clk, clk->enable_reg); if (clk->flags & INVERT_ENABLE) v ^= BIT(clk->enable_bit); diff --git a/arch/arm/mach-omap2/clock36xx.c b/arch/arm/mach-omap2/clock36xx.c index bbd6a3f717e6..91ccb962e09e 100644 --- a/arch/arm/mach-omap2/clock36xx.c +++ b/arch/arm/mach-omap2/clock36xx.c @@ -43,6 +43,7 @@ int omap36xx_pwrdn_clk_enable_with_hsdiv_restore(struct clk_hw *clk) struct clk_divider *parent; struct clk_hw *parent_hw; u32 dummy_v, orig_v; + struct clk_hw_omap *omap_clk = to_clk_hw_omap(clk); int ret; /* Clear PWRDN bit of HSDIVIDER */ @@ -53,15 +54,15 @@ int omap36xx_pwrdn_clk_enable_with_hsdiv_restore(struct clk_hw *clk) /* Restore the dividers */ if (!ret) { - orig_v = __raw_readl(parent->reg); + orig_v = omap2_clk_readl(omap_clk, parent->reg); dummy_v = orig_v; /* Write any other value different from the Read value */ dummy_v ^= (1 << parent->shift); - __raw_writel(dummy_v, parent->reg); + omap2_clk_writel(dummy_v, omap_clk, parent->reg); /* Write the original divider */ - __raw_writel(orig_v, parent->reg); + omap2_clk_writel(orig_v, omap_clk, parent->reg); } return ret; diff --git a/arch/arm/mach-omap2/dpll3xxx.c b/arch/arm/mach-omap2/dpll3xxx.c index 3a0296cfcace..3185ced807c9 100644 --- a/arch/arm/mach-omap2/dpll3xxx.c +++ b/arch/arm/mach-omap2/dpll3xxx.c @@ -50,10 +50,10 @@ static void _omap3_dpll_write_clken(struct clk_hw_omap *clk, u8 clken_bits) dd = clk->dpll_data; - v = __raw_readl(dd->control_reg); + v = omap2_clk_readl(clk, dd->control_reg); v &= ~dd->enable_mask; v |= clken_bits << __ffs(dd->enable_mask); - __raw_writel(v, dd->control_reg); + omap2_clk_writel(v, clk, dd->control_reg); } /* _omap3_wait_dpll_status: wait for a DPLL to enter a specific state */ @@ -69,8 +69,8 @@ static int _omap3_wait_dpll_status(struct clk_hw_omap *clk, u8 state) state <<= __ffs(dd->idlest_mask); - while (((__raw_readl(dd->idlest_reg) & dd->idlest_mask) != state) && - i < MAX_DPLL_WAIT_TRIES) { + while (((omap2_clk_readl(clk, dd->idlest_reg) & dd->idlest_mask) + != state) && i < MAX_DPLL_WAIT_TRIES) { i++; udelay(1); } @@ -147,7 +147,7 @@ static int _omap3_noncore_dpll_lock(struct clk_hw_omap *clk) state <<= __ffs(dd->idlest_mask); /* Check if already locked */ - if ((__raw_readl(dd->idlest_reg) & dd->idlest_mask) == state) + if ((omap2_clk_readl(clk, dd->idlest_reg) & dd->idlest_mask) == state) goto done; ai = omap3_dpll_autoidle_read(clk); @@ -311,14 +311,14 @@ static int omap3_noncore_dpll_program(struct clk_hw_omap *clk, u16 freqsel) * only since freqsel field is no longer present on other devices. */ if (cpu_is_omap343x()) { - v = __raw_readl(dd->control_reg); + v = omap2_clk_readl(clk, dd->control_reg); v &= ~dd->freqsel_mask; v |= freqsel << __ffs(dd->freqsel_mask); - __raw_writel(v, dd->control_reg); + omap2_clk_writel(v, clk, dd->control_reg); } /* Set DPLL multiplier, divider */ - v = __raw_readl(dd->mult_div1_reg); + v = omap2_clk_readl(clk, dd->mult_div1_reg); v &= ~(dd->mult_mask | dd->div1_mask); v |= dd->last_rounded_m << __ffs(dd->mult_mask); v |= (dd->last_rounded_n - 1) << __ffs(dd->div1_mask); @@ -336,11 +336,11 @@ static int omap3_noncore_dpll_program(struct clk_hw_omap *clk, u16 freqsel) v |= sd_div << __ffs(dd->sddiv_mask); } - __raw_writel(v, dd->mult_div1_reg); + omap2_clk_writel(v, clk, dd->mult_div1_reg); /* Set 4X multiplier and low-power mode */ if (dd->m4xen_mask || dd->lpmode_mask) { - v = __raw_readl(dd->control_reg); + v = omap2_clk_readl(clk, dd->control_reg); if (dd->m4xen_mask) { if (dd->last_rounded_m4xen) @@ -356,7 +356,7 @@ static int omap3_noncore_dpll_program(struct clk_hw_omap *clk, u16 freqsel) v &= ~dd->lpmode_mask; } - __raw_writel(v, dd->control_reg); + omap2_clk_writel(v, clk, dd->control_reg); } /* We let the clock framework set the other output dividers later */ @@ -554,7 +554,7 @@ u32 omap3_dpll_autoidle_read(struct clk_hw_omap *clk) if (!dd->autoidle_reg) return -EINVAL; - v = __raw_readl(dd->autoidle_reg); + v = omap2_clk_readl(clk, dd->autoidle_reg); v &= dd->autoidle_mask; v >>= __ffs(dd->autoidle_mask); @@ -588,10 +588,10 @@ void omap3_dpll_allow_idle(struct clk_hw_omap *clk) * by writing 0x5 instead of 0x1. Add some mechanism to * optionally enter this mode. */ - v = __raw_readl(dd->autoidle_reg); + v = omap2_clk_readl(clk, dd->autoidle_reg); v &= ~dd->autoidle_mask; v |= DPLL_AUTOIDLE_LOW_POWER_STOP << __ffs(dd->autoidle_mask); - __raw_writel(v, dd->autoidle_reg); + omap2_clk_writel(v, clk, dd->autoidle_reg); } @@ -614,10 +614,10 @@ void omap3_dpll_deny_idle(struct clk_hw_omap *clk) if (!dd->autoidle_reg) return; - v = __raw_readl(dd->autoidle_reg); + v = omap2_clk_readl(clk, dd->autoidle_reg); v &= ~dd->autoidle_mask; v |= DPLL_AUTOIDLE_DISABLE << __ffs(dd->autoidle_mask); - __raw_writel(v, dd->autoidle_reg); + omap2_clk_writel(v, clk, dd->autoidle_reg); } @@ -639,6 +639,9 @@ unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw, struct clk_hw_omap *pclk = NULL; struct clk *parent; + if (!parent_rate) + return 0; + /* Walk up the parents of clk, looking for a DPLL */ do { do { @@ -660,7 +663,7 @@ unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw, WARN_ON(!dd->enable_mask); - v = __raw_readl(dd->control_reg) & dd->enable_mask; + v = omap2_clk_readl(pclk, dd->control_reg) & dd->enable_mask; v >>= __ffs(dd->enable_mask); if ((v != OMAP3XXX_EN_DPLL_LOCKED) || (dd->flags & DPLL_J_TYPE)) rate = parent_rate; diff --git a/arch/arm/mach-omap2/dpll44xx.c b/arch/arm/mach-omap2/dpll44xx.c index d28b0f726715..52f9438b92f2 100644 --- a/arch/arm/mach-omap2/dpll44xx.c +++ b/arch/arm/mach-omap2/dpll44xx.c @@ -42,7 +42,7 @@ int omap4_dpllmx_gatectrl_read(struct clk_hw_omap *clk) OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK : OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK; - v = __raw_readl(clk->clksel_reg); + v = omap2_clk_readl(clk, clk->clksel_reg); v &= mask; v >>= __ffs(mask); @@ -61,10 +61,10 @@ void omap4_dpllmx_allow_gatectrl(struct clk_hw_omap *clk) OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK : OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK; - v = __raw_readl(clk->clksel_reg); + v = omap2_clk_readl(clk, clk->clksel_reg); /* Clear the bit to allow gatectrl */ v &= ~mask; - __raw_writel(v, clk->clksel_reg); + omap2_clk_writel(v, clk, clk->clksel_reg); } void omap4_dpllmx_deny_gatectrl(struct clk_hw_omap *clk) @@ -79,10 +79,10 @@ void omap4_dpllmx_deny_gatectrl(struct clk_hw_omap *clk) OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK : OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK; - v = __raw_readl(clk->clksel_reg); + v = omap2_clk_readl(clk, clk->clksel_reg); /* Set the bit to deny gatectrl */ v |= mask; - __raw_writel(v, clk->clksel_reg); + omap2_clk_writel(v, clk, clk->clksel_reg); } const struct clk_hw_omap_ops clkhwops_omap4_dpllmx = { @@ -140,7 +140,7 @@ unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw, rate = omap2_get_dpll_rate(clk); /* regm4xen adds a multiplier of 4 to DPLL calculations */ - v = __raw_readl(dd->control_reg); + v = omap2_clk_readl(clk, dd->control_reg); if (v & OMAP4430_DPLL_REGM4XEN_MASK) rate *= OMAP4430_REGM4XEN_MULT; -- cgit v1.2.3-59-g8ed1b From 924f9498acb004d8cb704a008f1060fad604ccca Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Fri, 12 Jul 2013 12:26:41 +0300 Subject: ARM: OMAP: hwmod: fix an incorrect clk type cast with _get_clkdm If the main clock for a hwmod is of basic clock type, it is illegal to type cast this to clk_hw_omap and will result in bogus data. Fixed by checking the clock flags before attempting the type cast. Signed-off-by: Tero Kristo Tested-by: Nishanth Menon Acked-by: Tony Lindgren Signed-off-by: Mike Turquette --- arch/arm/mach-omap2/omap_hwmod.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c index 8a1b5e0bad40..cc24c95b77e5 100644 --- a/arch/arm/mach-omap2/omap_hwmod.c +++ b/arch/arm/mach-omap2/omap_hwmod.c @@ -686,6 +686,8 @@ static struct clockdomain *_get_clkdm(struct omap_hwmod *oh) if (oh->clkdm) { return oh->clkdm; } else if (oh->_clk) { + if (__clk_get_flags(oh->_clk) & CLK_IS_BASIC) + return NULL; clk = to_clk_hw_omap(__clk_get_hw(oh->_clk)); return clk->clkdm; } -- cgit v1.2.3-59-g8ed1b From 0385c58207771efed179670549573fb779c15dc9 Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Wed, 17 Jul 2013 18:03:25 +0300 Subject: ARM: OMAP3: hwmod: initialize clkdm from clkdm_name DT clocks are mostly missing clkdm info now, and this causes an issue with counter32k which makes its slave idlemode wrong and prevents core idle. Fixed by initializing the hwmod clkdm pointers for omap3 also which makes sure the clkdm flag matching logic works properly. This patch also changes the return value for _init_clkdm to 0 for incorrect clkdm_name, as this a warning, not a fatal error. Signed-off-by: Tero Kristo Tested-by: Nishanth Menon Acked-by: Tony Lindgren Signed-off-by: Mike Turquette --- arch/arm/mach-omap2/omap_hwmod.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c index cc24c95b77e5..433fe2f9278c 100644 --- a/arch/arm/mach-omap2/omap_hwmod.c +++ b/arch/arm/mach-omap2/omap_hwmod.c @@ -1578,7 +1578,7 @@ static int _init_clkdm(struct omap_hwmod *oh) if (!oh->clkdm) { pr_warning("omap_hwmod: %s: could not associate to clkdm %s\n", oh->name, oh->clkdm_name); - return -EINVAL; + return 0; } pr_debug("omap_hwmod: %s: associated to clkdm %s\n", @@ -4237,6 +4237,7 @@ void __init omap_hwmod_init(void) soc_ops.assert_hardreset = _omap2_assert_hardreset; soc_ops.deassert_hardreset = _omap2_deassert_hardreset; soc_ops.is_hardreset_asserted = _omap2_is_hardreset_asserted; + soc_ops.init_clkdm = _init_clkdm; } else if (cpu_is_omap44xx() || soc_is_omap54xx() || soc_is_dra7xx()) { soc_ops.enable_module = _omap4_enable_module; soc_ops.disable_module = _omap4_disable_module; -- cgit v1.2.3-59-g8ed1b From 943a63a41f8542eed31c902d840e9ca2753a592f Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Fri, 25 Oct 2013 15:28:11 +0300 Subject: ARM: OMAP2+: PRM: add support for initializing PRCM clock modules from DT This patch provides top level functionality for the DT clock initialization. Clock tree is initialized hierarchically starting from IP modules (CM/PRM/PRCM) going down towards individual clock nodes, and finally initializing clockdomains once all the clocks are ready. Signed-off-by: Tero Kristo Acked-by: Tony Lindgren Signed-off-by: Mike Turquette --- arch/arm/mach-omap2/prm.h | 1 + arch/arm/mach-omap2/prm_common.c | 66 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 67 insertions(+) diff --git a/arch/arm/mach-omap2/prm.h b/arch/arm/mach-omap2/prm.h index ac25ae6667cf..623db40fdbbd 100644 --- a/arch/arm/mach-omap2/prm.h +++ b/arch/arm/mach-omap2/prm.h @@ -18,6 +18,7 @@ # ifndef __ASSEMBLER__ extern void __iomem *prm_base; extern void omap2_set_globals_prm(void __iomem *prm); +int of_prcm_init(void); # endif diff --git a/arch/arm/mach-omap2/prm_common.c b/arch/arm/mach-omap2/prm_common.c index a2e1174ad1b6..b4c4ab9c8044 100644 --- a/arch/arm/mach-omap2/prm_common.c +++ b/arch/arm/mach-omap2/prm_common.c @@ -23,6 +23,10 @@ #include #include #include +#include +#include +#include +#include #include "soc.h" #include "prm2xxx_3xxx.h" @@ -30,6 +34,7 @@ #include "prm3xxx.h" #include "prm44xx.h" #include "common.h" +#include "clock.h" /* * OMAP_PRCM_MAX_NR_PENDING_REG: maximum number of PRM_IRQ*_MPU regs @@ -464,3 +469,64 @@ int prm_unregister(struct prm_ll_data *pld) return 0; } + +static struct of_device_id omap_prcm_dt_match_table[] = { + { .compatible = "ti,am3-prcm" }, + { .compatible = "ti,am3-scrm" }, + { .compatible = "ti,am4-prcm" }, + { .compatible = "ti,am4-scrm" }, + { .compatible = "ti,omap3-prm" }, + { .compatible = "ti,omap3-cm" }, + { .compatible = "ti,omap3-scrm" }, + { .compatible = "ti,omap4-cm1" }, + { .compatible = "ti,omap4-prm" }, + { .compatible = "ti,omap4-cm2" }, + { .compatible = "ti,omap4-scrm" }, + { .compatible = "ti,omap5-prm" }, + { .compatible = "ti,omap5-cm-core-aon" }, + { .compatible = "ti,omap5-scrm" }, + { .compatible = "ti,omap5-cm-core" }, + { .compatible = "ti,dra7-prm" }, + { .compatible = "ti,dra7-cm-core-aon" }, + { .compatible = "ti,dra7-cm-core" }, + { } +}; + +static struct clk_hw_omap memmap_dummy_ck = { + .flags = MEMMAP_ADDRESSING, +}; + +static u32 prm_clk_readl(void __iomem *reg) +{ + return omap2_clk_readl(&memmap_dummy_ck, reg); +} + +static void prm_clk_writel(u32 val, void __iomem *reg) +{ + omap2_clk_writel(val, &memmap_dummy_ck, reg); +} + +static struct ti_clk_ll_ops omap_clk_ll_ops = { + .clk_readl = prm_clk_readl, + .clk_writel = prm_clk_writel, +}; + +int __init of_prcm_init(void) +{ + struct device_node *np; + void __iomem *mem; + int memmap_index = 0; + + ti_clk_ll_ops = &omap_clk_ll_ops; + + for_each_matching_node(np, omap_prcm_dt_match_table) { + mem = of_iomap(np, 0); + clk_memmaps[memmap_index] = mem; + ti_dt_clk_init_provider(np, memmap_index); + memmap_index++; + } + + ti_dt_clockdomains_setup(); + + return 0; +} -- cgit v1.2.3-59-g8ed1b From cfa9667d4ac9da8b3ba2269f934ecd69ae504d39 Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Tue, 22 Oct 2013 11:53:02 +0300 Subject: ARM: OMAP2+: io: use new clock init API clk_init is now separated to a common function which gets called for all SoC:s, which initializes the DT clocks and calls the SoC specific clock init. Signed-off-by: Tero Kristo Acked-by: Tony Lindgren Signed-off-by: Mike Turquette --- arch/arm/mach-omap2/common.h | 2 +- arch/arm/mach-omap2/io.c | 32 +++++++++++++++++++++++--------- arch/arm/mach-omap2/timer.c | 6 ++---- 3 files changed, 26 insertions(+), 14 deletions(-) diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h index e30ef6797c63..5ccf36d3e2d3 100644 --- a/arch/arm/mach-omap2/common.h +++ b/arch/arm/mach-omap2/common.h @@ -305,7 +305,7 @@ struct omap_hwmod; extern int omap_dss_reset(struct omap_hwmod *); /* SoC specific clock initializer */ -extern int (*omap_clk_init)(void); +int omap_clk_init(void); #endif /* __ASSEMBLER__ */ #endif /* __ARCH_ARM_MACH_OMAP2PLUS_COMMON_H */ diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c index 3d9b3fcb1266..8517a62a97f0 100644 --- a/arch/arm/mach-omap2/io.c +++ b/arch/arm/mach-omap2/io.c @@ -55,10 +55,10 @@ #include "prm44xx.h" /* - * omap_clk_init: points to a function that does the SoC-specific + * omap_clk_soc_init: points to a function that does the SoC-specific * clock initializations */ -int (*omap_clk_init)(void); +static int (*omap_clk_soc_init)(void); /* * The machine specific code may provide the extra mapping besides the @@ -419,7 +419,7 @@ void __init omap2420_init_early(void) omap242x_clockdomains_init(); omap2420_hwmod_init(); omap_hwmod_init_postsetup(); - omap_clk_init = omap2420_clk_init; + omap_clk_soc_init = omap2420_clk_init; } void __init omap2420_init_late(void) @@ -448,7 +448,7 @@ void __init omap2430_init_early(void) omap243x_clockdomains_init(); omap2430_hwmod_init(); omap_hwmod_init_postsetup(); - omap_clk_init = omap2430_clk_init; + omap_clk_soc_init = omap2430_clk_init; } void __init omap2430_init_late(void) @@ -482,7 +482,7 @@ void __init omap3_init_early(void) omap3xxx_clockdomains_init(); omap3xxx_hwmod_init(); omap_hwmod_init_postsetup(); - omap_clk_init = omap3xxx_clk_init; + omap_clk_soc_init = omap3xxx_clk_init; } void __init omap3430_init_early(void) @@ -520,7 +520,7 @@ void __init ti81xx_init_early(void) omap3xxx_clockdomains_init(); omap3xxx_hwmod_init(); omap_hwmod_init_postsetup(); - omap_clk_init = omap3xxx_clk_init; + omap_clk_soc_init = omap3xxx_clk_init; } void __init omap3_init_late(void) @@ -581,7 +581,7 @@ void __init am33xx_init_early(void) am33xx_clockdomains_init(); am33xx_hwmod_init(); omap_hwmod_init_postsetup(); - omap_clk_init = am33xx_clk_init; + omap_clk_soc_init = am33xx_clk_init; } void __init am33xx_init_late(void) @@ -635,7 +635,7 @@ void __init omap4430_init_early(void) omap44xx_clockdomains_init(); omap44xx_hwmod_init(); omap_hwmod_init_postsetup(); - omap_clk_init = omap4xxx_clk_init; + omap_clk_soc_init = omap4xxx_clk_init; } void __init omap4430_init_late(void) @@ -666,7 +666,7 @@ void __init omap5_init_early(void) omap54xx_clockdomains_init(); omap54xx_hwmod_init(); omap_hwmod_init_postsetup(); - omap_clk_init = omap5xxx_dt_clk_init; + omap_clk_soc_init = omap5xxx_dt_clk_init; } void __init omap5_init_late(void) @@ -711,3 +711,17 @@ void __init omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0, _omap2_init_reprogram_sdrc(); } } + +int __init omap_clk_init(void) +{ + int ret = 0; + + if (!omap_clk_soc_init) + return 0; + + ret = of_prcm_init(); + if (!ret) + ret = omap_clk_soc_init(); + + return ret; +} diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c index 3ca81e0ada5e..60e5fc93b114 100644 --- a/arch/arm/mach-omap2/timer.c +++ b/arch/arm/mach-omap2/timer.c @@ -570,8 +570,7 @@ static inline void __init realtime_counter_init(void) clksrc_nr, clksrc_src, clksrc_prop) \ void __init omap##name##_gptimer_timer_init(void) \ { \ - if (omap_clk_init) \ - omap_clk_init(); \ + omap_clk_init(); \ omap_dmtimer_init(); \ omap2_gp_clockevent_init((clkev_nr), clkev_src, clkev_prop); \ omap2_gptimer_clocksource_init((clksrc_nr), clksrc_src, \ @@ -582,8 +581,7 @@ void __init omap##name##_gptimer_timer_init(void) \ clksrc_nr, clksrc_src, clksrc_prop) \ void __init omap##name##_sync32k_timer_init(void) \ { \ - if (omap_clk_init) \ - omap_clk_init(); \ + omap_clk_init(); \ omap_dmtimer_init(); \ omap2_gp_clockevent_init((clkev_nr), clkev_src, clkev_prop); \ /* Enable the use of clocksource="gp_timer" kernel parameter */ \ -- cgit v1.2.3-59-g8ed1b From c8c88d8512d34140c9fcf855dbf0a187491691ae Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Thu, 18 Jul 2013 16:04:00 +0300 Subject: ARM: OMAP4: remove old clock data and link in new clock init code OMAP4 clocks have now been moved to DT, thus remove the old data file and use the new init code under drivers/clk/omap/clk-44xx.c. Signed-off-by: Tero Kristo Tested-by: Nishanth Menon Acked-by: Tony Lindgren Signed-off-by: Mike Turquette --- arch/arm/mach-omap2/Makefile | 2 +- arch/arm/mach-omap2/cclock44xx_data.c | 1735 --------------------------------- arch/arm/mach-omap2/io.c | 2 +- 3 files changed, 2 insertions(+), 1737 deletions(-) delete mode 100644 arch/arm/mach-omap2/cclock44xx_data.c diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index 3d9c121305f4..665455a852f4 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -187,7 +187,7 @@ obj-$(CONFIG_ARCH_OMAP3) += clock34xx.o clkt34xx_dpll3m2.o obj-$(CONFIG_ARCH_OMAP3) += clock3517.o clock36xx.o obj-$(CONFIG_ARCH_OMAP3) += dpll3xxx.o cclock3xxx_data.o obj-$(CONFIG_ARCH_OMAP3) += clkt_iclk.o -obj-$(CONFIG_ARCH_OMAP4) += $(clock-common) cclock44xx_data.o +obj-$(CONFIG_ARCH_OMAP4) += $(clock-common) obj-$(CONFIG_ARCH_OMAP4) += dpll3xxx.o dpll44xx.o obj-$(CONFIG_SOC_AM33XX) += $(clock-common) dpll3xxx.o obj-$(CONFIG_SOC_AM33XX) += cclock33xx_data.o diff --git a/arch/arm/mach-omap2/cclock44xx_data.c b/arch/arm/mach-omap2/cclock44xx_data.c deleted file mode 100644 index ec0dc0b1755e..000000000000 --- a/arch/arm/mach-omap2/cclock44xx_data.c +++ /dev/null @@ -1,1735 +0,0 @@ -/* - * OMAP4 Clock data - * - * Copyright (C) 2009-2012 Texas Instruments, Inc. - * Copyright (C) 2009-2010 Nokia Corporation - * - * Paul Walmsley (paul@pwsan.com) - * Rajendra Nayak (rnayak@ti.com) - * Benoit Cousson (b-cousson@ti.com) - * Mike Turquette (mturquette@ti.com) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * XXX Some of the ES1 clocks have been removed/changed; once support - * is added for discriminating clocks by ES level, these should be added back - * in. - * - * XXX All of the remaining MODULEMODE clock nodes should be removed - * once the drivers are updated to use pm_runtime or to use the appropriate - * upstream clock node for rate/parent selection. - */ - -#include -#include -#include -#include -#include - -#include "soc.h" -#include "iomap.h" -#include "clock.h" -#include "clock44xx.h" -#include "cm1_44xx.h" -#include "cm2_44xx.h" -#include "cm-regbits-44xx.h" -#include "prm44xx.h" -#include "prm-regbits-44xx.h" -#include "control.h" -#include "scrm44xx.h" - -/* OMAP4 modulemode control */ -#define OMAP4430_MODULEMODE_HWCTRL_SHIFT 0 -#define OMAP4430_MODULEMODE_SWCTRL_SHIFT 1 - -/* - * OMAP4 ABE DPLL default frequency. In OMAP4460 TRM version V, section - * "3.6.3.2.3 CM1_ABE Clock Generator" states that the "DPLL_ABE_X2_CLK - * must be set to 196.608 MHz" and hence, the DPLL locked frequency is - * half of this value. - */ -#define OMAP4_DPLL_ABE_DEFFREQ 98304000 - -/* - * OMAP4 USB DPLL default frequency. In OMAP4430 TRM version V, section - * "3.6.3.9.5 DPLL_USB Preferred Settings" shows that the preferred - * locked frequency for the USB DPLL is 960MHz. - */ -#define OMAP4_DPLL_USB_DEFFREQ 960000000 - -/* Root clocks */ - -DEFINE_CLK_FIXED_RATE(extalt_clkin_ck, CLK_IS_ROOT, 59000000, 0x0); - -DEFINE_CLK_FIXED_RATE(pad_clks_src_ck, CLK_IS_ROOT, 12000000, 0x0); - -DEFINE_CLK_GATE(pad_clks_ck, "pad_clks_src_ck", &pad_clks_src_ck, 0x0, - OMAP4430_CM_CLKSEL_ABE, OMAP4430_PAD_CLKS_GATE_SHIFT, - 0x0, NULL); - -DEFINE_CLK_FIXED_RATE(pad_slimbus_core_clks_ck, CLK_IS_ROOT, 12000000, 0x0); - -DEFINE_CLK_FIXED_RATE(secure_32k_clk_src_ck, CLK_IS_ROOT, 32768, 0x0); - -DEFINE_CLK_FIXED_RATE(slimbus_src_clk, CLK_IS_ROOT, 12000000, 0x0); - -DEFINE_CLK_GATE(slimbus_clk, "slimbus_src_clk", &slimbus_src_clk, 0x0, - OMAP4430_CM_CLKSEL_ABE, OMAP4430_SLIMBUS_CLK_GATE_SHIFT, - 0x0, NULL); - -DEFINE_CLK_FIXED_RATE(sys_32k_ck, CLK_IS_ROOT, 32768, 0x0); - -DEFINE_CLK_FIXED_RATE(virt_12000000_ck, CLK_IS_ROOT, 12000000, 0x0); - -DEFINE_CLK_FIXED_RATE(virt_13000000_ck, CLK_IS_ROOT, 13000000, 0x0); - -DEFINE_CLK_FIXED_RATE(virt_16800000_ck, CLK_IS_ROOT, 16800000, 0x0); - -DEFINE_CLK_FIXED_RATE(virt_19200000_ck, CLK_IS_ROOT, 19200000, 0x0); - -DEFINE_CLK_FIXED_RATE(virt_26000000_ck, CLK_IS_ROOT, 26000000, 0x0); - -DEFINE_CLK_FIXED_RATE(virt_27000000_ck, CLK_IS_ROOT, 27000000, 0x0); - -DEFINE_CLK_FIXED_RATE(virt_38400000_ck, CLK_IS_ROOT, 38400000, 0x0); - -static const char *sys_clkin_ck_parents[] = { - "virt_12000000_ck", "virt_13000000_ck", "virt_16800000_ck", - "virt_19200000_ck", "virt_26000000_ck", "virt_27000000_ck", - "virt_38400000_ck", -}; - -DEFINE_CLK_MUX(sys_clkin_ck, sys_clkin_ck_parents, NULL, 0x0, - OMAP4430_CM_SYS_CLKSEL, OMAP4430_SYS_CLKSEL_SHIFT, - OMAP4430_SYS_CLKSEL_WIDTH, CLK_MUX_INDEX_ONE, NULL); - -DEFINE_CLK_FIXED_RATE(tie_low_clock_ck, CLK_IS_ROOT, 0, 0x0); - -DEFINE_CLK_FIXED_RATE(utmi_phy_clkout_ck, CLK_IS_ROOT, 60000000, 0x0); - -DEFINE_CLK_FIXED_RATE(xclk60mhsp1_ck, CLK_IS_ROOT, 60000000, 0x0); - -DEFINE_CLK_FIXED_RATE(xclk60mhsp2_ck, CLK_IS_ROOT, 60000000, 0x0); - -DEFINE_CLK_FIXED_RATE(xclk60motg_ck, CLK_IS_ROOT, 60000000, 0x0); - -/* Module clocks and DPLL outputs */ - -static const char *abe_dpll_bypass_clk_mux_ck_parents[] = { - "sys_clkin_ck", "sys_32k_ck", -}; - -DEFINE_CLK_MUX(abe_dpll_bypass_clk_mux_ck, abe_dpll_bypass_clk_mux_ck_parents, - NULL, 0x0, OMAP4430_CM_L4_WKUP_CLKSEL, OMAP4430_CLKSEL_SHIFT, - OMAP4430_CLKSEL_WIDTH, 0x0, NULL); - -DEFINE_CLK_MUX(abe_dpll_refclk_mux_ck, abe_dpll_bypass_clk_mux_ck_parents, NULL, - 0x0, OMAP4430_CM_ABE_PLL_REF_CLKSEL, OMAP4430_CLKSEL_0_0_SHIFT, - OMAP4430_CLKSEL_0_0_WIDTH, 0x0, NULL); - -/* DPLL_ABE */ -static struct dpll_data dpll_abe_dd = { - .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_ABE, - .clk_bypass = &abe_dpll_bypass_clk_mux_ck, - .clk_ref = &abe_dpll_refclk_mux_ck, - .control_reg = OMAP4430_CM_CLKMODE_DPLL_ABE, - .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), - .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_ABE, - .idlest_reg = OMAP4430_CM_IDLEST_DPLL_ABE, - .mult_mask = OMAP4430_DPLL_MULT_MASK, - .div1_mask = OMAP4430_DPLL_DIV_MASK, - .enable_mask = OMAP4430_DPLL_EN_MASK, - .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK, - .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK, - .m4xen_mask = OMAP4430_DPLL_REGM4XEN_MASK, - .lpmode_mask = OMAP4430_DPLL_LPMODE_EN_MASK, - .max_multiplier = 2047, - .max_divider = 128, - .min_divider = 1, -}; - - -static const char *dpll_abe_ck_parents[] = { - "abe_dpll_refclk_mux_ck", -}; - -static struct clk dpll_abe_ck; - -static const struct clk_ops dpll_abe_ck_ops = { - .enable = &omap3_noncore_dpll_enable, - .disable = &omap3_noncore_dpll_disable, - .recalc_rate = &omap4_dpll_regm4xen_recalc, - .round_rate = &omap4_dpll_regm4xen_round_rate, - .set_rate = &omap3_noncore_dpll_set_rate, - .get_parent = &omap2_init_dpll_parent, -}; - -static struct clk_hw_omap dpll_abe_ck_hw = { - .hw = { - .clk = &dpll_abe_ck, - }, - .dpll_data = &dpll_abe_dd, - .ops = &clkhwops_omap3_dpll, -}; - -DEFINE_STRUCT_CLK(dpll_abe_ck, dpll_abe_ck_parents, dpll_abe_ck_ops); - -static const char *dpll_abe_x2_ck_parents[] = { - "dpll_abe_ck", -}; - -static struct clk dpll_abe_x2_ck; - -static const struct clk_ops dpll_abe_x2_ck_ops = { - .recalc_rate = &omap3_clkoutx2_recalc, -}; - -static struct clk_hw_omap dpll_abe_x2_ck_hw = { - .hw = { - .clk = &dpll_abe_x2_ck, - }, - .flags = CLOCK_CLKOUTX2, - .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_ABE, - .ops = &clkhwops_omap4_dpllmx, -}; - -DEFINE_STRUCT_CLK(dpll_abe_x2_ck, dpll_abe_x2_ck_parents, dpll_abe_x2_ck_ops); - -static const struct clk_ops omap_hsdivider_ops = { - .set_rate = &omap2_clksel_set_rate, - .recalc_rate = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, -}; - -DEFINE_CLK_OMAP_HSDIVIDER(dpll_abe_m2x2_ck, "dpll_abe_x2_ck", &dpll_abe_x2_ck, - 0x0, OMAP4430_CM_DIV_M2_DPLL_ABE, - OMAP4430_DPLL_CLKOUT_DIV_MASK); - -DEFINE_CLK_FIXED_FACTOR(abe_24m_fclk, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck, - 0x0, 1, 8); - -DEFINE_CLK_DIVIDER(abe_clk, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck, 0x0, - OMAP4430_CM_CLKSEL_ABE, OMAP4430_CLKSEL_OPP_SHIFT, - OMAP4430_CLKSEL_OPP_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL); - -DEFINE_CLK_DIVIDER(aess_fclk, "abe_clk", &abe_clk, 0x0, - OMAP4430_CM1_ABE_AESS_CLKCTRL, - OMAP4430_CLKSEL_AESS_FCLK_SHIFT, - OMAP4430_CLKSEL_AESS_FCLK_WIDTH, - 0x0, NULL); - -DEFINE_CLK_OMAP_HSDIVIDER(dpll_abe_m3x2_ck, "dpll_abe_x2_ck", &dpll_abe_x2_ck, - 0x0, OMAP4430_CM_DIV_M3_DPLL_ABE, - OMAP4430_DPLL_CLKOUTHIF_DIV_MASK); - -static const char *core_hsd_byp_clk_mux_ck_parents[] = { - "sys_clkin_ck", "dpll_abe_m3x2_ck", -}; - -DEFINE_CLK_MUX(core_hsd_byp_clk_mux_ck, core_hsd_byp_clk_mux_ck_parents, NULL, - 0x0, OMAP4430_CM_CLKSEL_DPLL_CORE, - OMAP4430_DPLL_BYP_CLKSEL_SHIFT, OMAP4430_DPLL_BYP_CLKSEL_WIDTH, - 0x0, NULL); - -/* DPLL_CORE */ -static struct dpll_data dpll_core_dd = { - .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_CORE, - .clk_bypass = &core_hsd_byp_clk_mux_ck, - .clk_ref = &sys_clkin_ck, - .control_reg = OMAP4430_CM_CLKMODE_DPLL_CORE, - .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), - .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_CORE, - .idlest_reg = OMAP4430_CM_IDLEST_DPLL_CORE, - .mult_mask = OMAP4430_DPLL_MULT_MASK, - .div1_mask = OMAP4430_DPLL_DIV_MASK, - .enable_mask = OMAP4430_DPLL_EN_MASK, - .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK, - .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK, - .max_multiplier = 2047, - .max_divider = 128, - .min_divider = 1, -}; - - -static const char *dpll_core_ck_parents[] = { - "sys_clkin_ck", "core_hsd_byp_clk_mux_ck" -}; - -static struct clk dpll_core_ck; - -static const struct clk_ops dpll_core_ck_ops = { - .recalc_rate = &omap3_dpll_recalc, - .get_parent = &omap2_init_dpll_parent, -}; - -static struct clk_hw_omap dpll_core_ck_hw = { - .hw = { - .clk = &dpll_core_ck, - }, - .dpll_data = &dpll_core_dd, - .ops = &clkhwops_omap3_dpll, -}; - -DEFINE_STRUCT_CLK(dpll_core_ck, dpll_core_ck_parents, dpll_core_ck_ops); - -static const char *dpll_core_x2_ck_parents[] = { - "dpll_core_ck", -}; - -static struct clk dpll_core_x2_ck; - -static struct clk_hw_omap dpll_core_x2_ck_hw = { - .hw = { - .clk = &dpll_core_x2_ck, - }, -}; - -DEFINE_STRUCT_CLK(dpll_core_x2_ck, dpll_core_x2_ck_parents, dpll_abe_x2_ck_ops); - -DEFINE_CLK_OMAP_HSDIVIDER(dpll_core_m6x2_ck, "dpll_core_x2_ck", - &dpll_core_x2_ck, 0x0, OMAP4430_CM_DIV_M6_DPLL_CORE, - OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK); - -DEFINE_CLK_OMAP_HSDIVIDER(dpll_core_m2_ck, "dpll_core_ck", &dpll_core_ck, 0x0, - OMAP4430_CM_DIV_M2_DPLL_CORE, - OMAP4430_DPLL_CLKOUT_DIV_MASK); - -DEFINE_CLK_FIXED_FACTOR(ddrphy_ck, "dpll_core_m2_ck", &dpll_core_m2_ck, 0x0, 1, - 2); - -DEFINE_CLK_OMAP_HSDIVIDER(dpll_core_m5x2_ck, "dpll_core_x2_ck", - &dpll_core_x2_ck, 0x0, OMAP4430_CM_DIV_M5_DPLL_CORE, - OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK); - -DEFINE_CLK_DIVIDER(div_core_ck, "dpll_core_m5x2_ck", &dpll_core_m5x2_ck, 0x0, - OMAP4430_CM_CLKSEL_CORE, OMAP4430_CLKSEL_CORE_SHIFT, - OMAP4430_CLKSEL_CORE_WIDTH, 0x0, NULL); - -DEFINE_CLK_DIVIDER(div_iva_hs_clk, "dpll_core_m5x2_ck", &dpll_core_m5x2_ck, - 0x0, OMAP4430_CM_BYPCLK_DPLL_IVA, OMAP4430_CLKSEL_0_1_SHIFT, - OMAP4430_CLKSEL_0_1_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL); - -DEFINE_CLK_DIVIDER(div_mpu_hs_clk, "dpll_core_m5x2_ck", &dpll_core_m5x2_ck, - 0x0, OMAP4430_CM_BYPCLK_DPLL_MPU, OMAP4430_CLKSEL_0_1_SHIFT, - OMAP4430_CLKSEL_0_1_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL); - -DEFINE_CLK_OMAP_HSDIVIDER(dpll_core_m4x2_ck, "dpll_core_x2_ck", - &dpll_core_x2_ck, 0x0, OMAP4430_CM_DIV_M4_DPLL_CORE, - OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK); - -DEFINE_CLK_FIXED_FACTOR(dll_clk_div_ck, "dpll_core_m4x2_ck", &dpll_core_m4x2_ck, - 0x0, 1, 2); - -DEFINE_CLK_DIVIDER(dpll_abe_m2_ck, "dpll_abe_ck", &dpll_abe_ck, 0x0, - OMAP4430_CM_DIV_M2_DPLL_ABE, OMAP4430_DPLL_CLKOUT_DIV_SHIFT, - OMAP4430_DPLL_CLKOUT_DIV_WIDTH, CLK_DIVIDER_ONE_BASED, NULL); - -static const struct clk_ops dpll_hsd_ops = { - .enable = &omap2_dflt_clk_enable, - .disable = &omap2_dflt_clk_disable, - .is_enabled = &omap2_dflt_clk_is_enabled, - .recalc_rate = &omap2_clksel_recalc, - .get_parent = &omap2_clksel_find_parent_index, - .set_parent = &omap2_clksel_set_parent, - .init = &omap2_init_clk_clkdm, -}; - -static const struct clk_ops func_dmic_abe_gfclk_ops = { - .recalc_rate = &omap2_clksel_recalc, - .get_parent = &omap2_clksel_find_parent_index, - .set_parent = &omap2_clksel_set_parent, -}; - -static const char *dpll_core_m3x2_ck_parents[] = { - "dpll_core_x2_ck", -}; - -static const struct clksel dpll_core_m3x2_div[] = { - { .parent = &dpll_core_x2_ck, .rates = div31_1to31_rates }, - { .parent = NULL }, -}; - -/* XXX Missing round_rate, set_rate in ops */ -DEFINE_CLK_OMAP_MUX_GATE(dpll_core_m3x2_ck, NULL, dpll_core_m3x2_div, - OMAP4430_CM_DIV_M3_DPLL_CORE, - OMAP4430_DPLL_CLKOUTHIF_DIV_MASK, - OMAP4430_CM_DIV_M3_DPLL_CORE, - OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT, NULL, - dpll_core_m3x2_ck_parents, dpll_hsd_ops); - -DEFINE_CLK_OMAP_HSDIVIDER(dpll_core_m7x2_ck, "dpll_core_x2_ck", - &dpll_core_x2_ck, 0x0, OMAP4430_CM_DIV_M7_DPLL_CORE, - OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK); - -static const char *iva_hsd_byp_clk_mux_ck_parents[] = { - "sys_clkin_ck", "div_iva_hs_clk", -}; - -DEFINE_CLK_MUX(iva_hsd_byp_clk_mux_ck, iva_hsd_byp_clk_mux_ck_parents, NULL, - 0x0, OMAP4430_CM_CLKSEL_DPLL_IVA, OMAP4430_DPLL_BYP_CLKSEL_SHIFT, - OMAP4430_DPLL_BYP_CLKSEL_WIDTH, 0x0, NULL); - -/* DPLL_IVA */ -static struct dpll_data dpll_iva_dd = { - .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_IVA, - .clk_bypass = &iva_hsd_byp_clk_mux_ck, - .clk_ref = &sys_clkin_ck, - .control_reg = OMAP4430_CM_CLKMODE_DPLL_IVA, - .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), - .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_IVA, - .idlest_reg = OMAP4430_CM_IDLEST_DPLL_IVA, - .mult_mask = OMAP4430_DPLL_MULT_MASK, - .div1_mask = OMAP4430_DPLL_DIV_MASK, - .enable_mask = OMAP4430_DPLL_EN_MASK, - .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK, - .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK, - .max_multiplier = 2047, - .max_divider = 128, - .min_divider = 1, -}; - -static const char *dpll_iva_ck_parents[] = { - "sys_clkin_ck", "iva_hsd_byp_clk_mux_ck" -}; - -static struct clk dpll_iva_ck; - -static const struct clk_ops dpll_ck_ops = { - .enable = &omap3_noncore_dpll_enable, - .disable = &omap3_noncore_dpll_disable, - .recalc_rate = &omap3_dpll_recalc, - .round_rate = &omap2_dpll_round_rate, - .set_rate = &omap3_noncore_dpll_set_rate, - .get_parent = &omap2_init_dpll_parent, -}; - -static struct clk_hw_omap dpll_iva_ck_hw = { - .hw = { - .clk = &dpll_iva_ck, - }, - .dpll_data = &dpll_iva_dd, - .ops = &clkhwops_omap3_dpll, -}; - -DEFINE_STRUCT_CLK(dpll_iva_ck, dpll_iva_ck_parents, dpll_ck_ops); - -static const char *dpll_iva_x2_ck_parents[] = { - "dpll_iva_ck", -}; - -static struct clk dpll_iva_x2_ck; - -static struct clk_hw_omap dpll_iva_x2_ck_hw = { - .hw = { - .clk = &dpll_iva_x2_ck, - }, -}; - -DEFINE_STRUCT_CLK(dpll_iva_x2_ck, dpll_iva_x2_ck_parents, dpll_abe_x2_ck_ops); - -DEFINE_CLK_OMAP_HSDIVIDER(dpll_iva_m4x2_ck, "dpll_iva_x2_ck", &dpll_iva_x2_ck, - 0x0, OMAP4430_CM_DIV_M4_DPLL_IVA, - OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK); - -DEFINE_CLK_OMAP_HSDIVIDER(dpll_iva_m5x2_ck, "dpll_iva_x2_ck", &dpll_iva_x2_ck, - 0x0, OMAP4430_CM_DIV_M5_DPLL_IVA, - OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK); - -/* DPLL_MPU */ -static struct dpll_data dpll_mpu_dd = { - .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_MPU, - .clk_bypass = &div_mpu_hs_clk, - .clk_ref = &sys_clkin_ck, - .control_reg = OMAP4430_CM_CLKMODE_DPLL_MPU, - .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), - .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_MPU, - .idlest_reg = OMAP4430_CM_IDLEST_DPLL_MPU, - .mult_mask = OMAP4430_DPLL_MULT_MASK, - .div1_mask = OMAP4430_DPLL_DIV_MASK, - .enable_mask = OMAP4430_DPLL_EN_MASK, - .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK, - .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK, - .max_multiplier = 2047, - .max_divider = 128, - .min_divider = 1, -}; - -static const char *dpll_mpu_ck_parents[] = { - "sys_clkin_ck", "div_mpu_hs_clk" -}; - -static struct clk dpll_mpu_ck; - -static struct clk_hw_omap dpll_mpu_ck_hw = { - .hw = { - .clk = &dpll_mpu_ck, - }, - .dpll_data = &dpll_mpu_dd, - .ops = &clkhwops_omap3_dpll, -}; - -DEFINE_STRUCT_CLK(dpll_mpu_ck, dpll_mpu_ck_parents, dpll_ck_ops); - -DEFINE_CLK_FIXED_FACTOR(mpu_periphclk, "dpll_mpu_ck", &dpll_mpu_ck, 0x0, 1, 2); - -DEFINE_CLK_OMAP_HSDIVIDER(dpll_mpu_m2_ck, "dpll_mpu_ck", &dpll_mpu_ck, 0x0, - OMAP4430_CM_DIV_M2_DPLL_MPU, - OMAP4430_DPLL_CLKOUT_DIV_MASK); - -DEFINE_CLK_FIXED_FACTOR(per_hs_clk_div_ck, "dpll_abe_m3x2_ck", - &dpll_abe_m3x2_ck, 0x0, 1, 2); - -static const char *per_hsd_byp_clk_mux_ck_parents[] = { - "sys_clkin_ck", "per_hs_clk_div_ck", -}; - -DEFINE_CLK_MUX(per_hsd_byp_clk_mux_ck, per_hsd_byp_clk_mux_ck_parents, NULL, - 0x0, OMAP4430_CM_CLKSEL_DPLL_PER, OMAP4430_DPLL_BYP_CLKSEL_SHIFT, - OMAP4430_DPLL_BYP_CLKSEL_WIDTH, 0x0, NULL); - -/* DPLL_PER */ -static struct dpll_data dpll_per_dd = { - .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_PER, - .clk_bypass = &per_hsd_byp_clk_mux_ck, - .clk_ref = &sys_clkin_ck, - .control_reg = OMAP4430_CM_CLKMODE_DPLL_PER, - .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), - .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_PER, - .idlest_reg = OMAP4430_CM_IDLEST_DPLL_PER, - .mult_mask = OMAP4430_DPLL_MULT_MASK, - .div1_mask = OMAP4430_DPLL_DIV_MASK, - .enable_mask = OMAP4430_DPLL_EN_MASK, - .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK, - .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK, - .max_multiplier = 2047, - .max_divider = 128, - .min_divider = 1, -}; - -static const char *dpll_per_ck_parents[] = { - "sys_clkin_ck", "per_hsd_byp_clk_mux_ck" -}; - -static struct clk dpll_per_ck; - -static struct clk_hw_omap dpll_per_ck_hw = { - .hw = { - .clk = &dpll_per_ck, - }, - .dpll_data = &dpll_per_dd, - .ops = &clkhwops_omap3_dpll, -}; - -DEFINE_STRUCT_CLK(dpll_per_ck, dpll_per_ck_parents, dpll_ck_ops); - -DEFINE_CLK_DIVIDER(dpll_per_m2_ck, "dpll_per_ck", &dpll_per_ck, 0x0, - OMAP4430_CM_DIV_M2_DPLL_PER, OMAP4430_DPLL_CLKOUT_DIV_SHIFT, - OMAP4430_DPLL_CLKOUT_DIV_WIDTH, CLK_DIVIDER_ONE_BASED, NULL); - -static const char *dpll_per_x2_ck_parents[] = { - "dpll_per_ck", -}; - -static struct clk dpll_per_x2_ck; - -static struct clk_hw_omap dpll_per_x2_ck_hw = { - .hw = { - .clk = &dpll_per_x2_ck, - }, - .flags = CLOCK_CLKOUTX2, - .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_PER, - .ops = &clkhwops_omap4_dpllmx, -}; - -DEFINE_STRUCT_CLK(dpll_per_x2_ck, dpll_per_x2_ck_parents, dpll_abe_x2_ck_ops); - -DEFINE_CLK_OMAP_HSDIVIDER(dpll_per_m2x2_ck, "dpll_per_x2_ck", &dpll_per_x2_ck, - 0x0, OMAP4430_CM_DIV_M2_DPLL_PER, - OMAP4430_DPLL_CLKOUT_DIV_MASK); - -static const char *dpll_per_m3x2_ck_parents[] = { - "dpll_per_x2_ck", -}; - -static const struct clksel dpll_per_m3x2_div[] = { - { .parent = &dpll_per_x2_ck, .rates = div31_1to31_rates }, - { .parent = NULL }, -}; - -/* XXX Missing round_rate, set_rate in ops */ -DEFINE_CLK_OMAP_MUX_GATE(dpll_per_m3x2_ck, NULL, dpll_per_m3x2_div, - OMAP4430_CM_DIV_M3_DPLL_PER, - OMAP4430_DPLL_CLKOUTHIF_DIV_MASK, - OMAP4430_CM_DIV_M3_DPLL_PER, - OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT, NULL, - dpll_per_m3x2_ck_parents, dpll_hsd_ops); - -DEFINE_CLK_OMAP_HSDIVIDER(dpll_per_m4x2_ck, "dpll_per_x2_ck", &dpll_per_x2_ck, - 0x0, OMAP4430_CM_DIV_M4_DPLL_PER, - OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK); - -DEFINE_CLK_OMAP_HSDIVIDER(dpll_per_m5x2_ck, "dpll_per_x2_ck", &dpll_per_x2_ck, - 0x0, OMAP4430_CM_DIV_M5_DPLL_PER, - OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK); - -DEFINE_CLK_OMAP_HSDIVIDER(dpll_per_m6x2_ck, "dpll_per_x2_ck", &dpll_per_x2_ck, - 0x0, OMAP4430_CM_DIV_M6_DPLL_PER, - OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK); - -DEFINE_CLK_OMAP_HSDIVIDER(dpll_per_m7x2_ck, "dpll_per_x2_ck", &dpll_per_x2_ck, - 0x0, OMAP4430_CM_DIV_M7_DPLL_PER, - OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK); - -DEFINE_CLK_FIXED_FACTOR(usb_hs_clk_div_ck, "dpll_abe_m3x2_ck", - &dpll_abe_m3x2_ck, 0x0, 1, 3); - -/* DPLL_USB */ -static struct dpll_data dpll_usb_dd = { - .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_USB, - .clk_bypass = &usb_hs_clk_div_ck, - .flags = DPLL_J_TYPE, - .clk_ref = &sys_clkin_ck, - .control_reg = OMAP4430_CM_CLKMODE_DPLL_USB, - .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), - .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_USB, - .idlest_reg = OMAP4430_CM_IDLEST_DPLL_USB, - .mult_mask = OMAP4430_DPLL_MULT_USB_MASK, - .div1_mask = OMAP4430_DPLL_DIV_0_7_MASK, - .enable_mask = OMAP4430_DPLL_EN_MASK, - .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK, - .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK, - .sddiv_mask = OMAP4430_DPLL_SD_DIV_MASK, - .max_multiplier = 4095, - .max_divider = 256, - .min_divider = 1, -}; - -static const char *dpll_usb_ck_parents[] = { - "sys_clkin_ck", "usb_hs_clk_div_ck" -}; - -static struct clk dpll_usb_ck; - -static const struct clk_ops dpll_usb_ck_ops = { - .enable = &omap3_noncore_dpll_enable, - .disable = &omap3_noncore_dpll_disable, - .recalc_rate = &omap3_dpll_recalc, - .round_rate = &omap2_dpll_round_rate, - .set_rate = &omap3_noncore_dpll_set_rate, - .get_parent = &omap2_init_dpll_parent, - .init = &omap2_init_clk_clkdm, -}; - -static struct clk_hw_omap dpll_usb_ck_hw = { - .hw = { - .clk = &dpll_usb_ck, - }, - .dpll_data = &dpll_usb_dd, - .clkdm_name = "l3_init_clkdm", - .ops = &clkhwops_omap3_dpll, -}; - -DEFINE_STRUCT_CLK(dpll_usb_ck, dpll_usb_ck_parents, dpll_usb_ck_ops); - -static const char *dpll_usb_clkdcoldo_ck_parents[] = { - "dpll_usb_ck", -}; - -static struct clk dpll_usb_clkdcoldo_ck; - -static const struct clk_ops dpll_usb_clkdcoldo_ck_ops = { -}; - -static struct clk_hw_omap dpll_usb_clkdcoldo_ck_hw = { - .hw = { - .clk = &dpll_usb_clkdcoldo_ck, - }, - .clksel_reg = OMAP4430_CM_CLKDCOLDO_DPLL_USB, - .ops = &clkhwops_omap4_dpllmx, -}; - -DEFINE_STRUCT_CLK(dpll_usb_clkdcoldo_ck, dpll_usb_clkdcoldo_ck_parents, - dpll_usb_clkdcoldo_ck_ops); - -DEFINE_CLK_OMAP_HSDIVIDER(dpll_usb_m2_ck, "dpll_usb_ck", &dpll_usb_ck, 0x0, - OMAP4430_CM_DIV_M2_DPLL_USB, - OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK); - -static const char *ducati_clk_mux_ck_parents[] = { - "div_core_ck", "dpll_per_m6x2_ck", -}; - -DEFINE_CLK_MUX(ducati_clk_mux_ck, ducati_clk_mux_ck_parents, NULL, 0x0, - OMAP4430_CM_CLKSEL_DUCATI_ISS_ROOT, OMAP4430_CLKSEL_0_0_SHIFT, - OMAP4430_CLKSEL_0_0_WIDTH, 0x0, NULL); - -DEFINE_CLK_FIXED_FACTOR(func_12m_fclk, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck, - 0x0, 1, 16); - -DEFINE_CLK_FIXED_FACTOR(func_24m_clk, "dpll_per_m2_ck", &dpll_per_m2_ck, 0x0, - 1, 4); - -DEFINE_CLK_FIXED_FACTOR(func_24mc_fclk, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck, - 0x0, 1, 8); - -static const struct clk_div_table func_48m_fclk_rates[] = { - { .div = 4, .val = 0 }, - { .div = 8, .val = 1 }, - { .div = 0 }, -}; -DEFINE_CLK_DIVIDER_TABLE(func_48m_fclk, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck, - 0x0, OMAP4430_CM_SCALE_FCLK, OMAP4430_SCALE_FCLK_SHIFT, - OMAP4430_SCALE_FCLK_WIDTH, 0x0, func_48m_fclk_rates, - NULL); - -DEFINE_CLK_FIXED_FACTOR(func_48mc_fclk, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck, - 0x0, 1, 4); - -static const struct clk_div_table func_64m_fclk_rates[] = { - { .div = 2, .val = 0 }, - { .div = 4, .val = 1 }, - { .div = 0 }, -}; -DEFINE_CLK_DIVIDER_TABLE(func_64m_fclk, "dpll_per_m4x2_ck", &dpll_per_m4x2_ck, - 0x0, OMAP4430_CM_SCALE_FCLK, OMAP4430_SCALE_FCLK_SHIFT, - OMAP4430_SCALE_FCLK_WIDTH, 0x0, func_64m_fclk_rates, - NULL); - -static const struct clk_div_table func_96m_fclk_rates[] = { - { .div = 2, .val = 0 }, - { .div = 4, .val = 1 }, - { .div = 0 }, -}; -DEFINE_CLK_DIVIDER_TABLE(func_96m_fclk, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck, - 0x0, OMAP4430_CM_SCALE_FCLK, OMAP4430_SCALE_FCLK_SHIFT, - OMAP4430_SCALE_FCLK_WIDTH, 0x0, func_96m_fclk_rates, - NULL); - -static const struct clk_div_table init_60m_fclk_rates[] = { - { .div = 1, .val = 0 }, - { .div = 8, .val = 1 }, - { .div = 0 }, -}; -DEFINE_CLK_DIVIDER_TABLE(init_60m_fclk, "dpll_usb_m2_ck", &dpll_usb_m2_ck, - 0x0, OMAP4430_CM_CLKSEL_USB_60MHZ, - OMAP4430_CLKSEL_0_0_SHIFT, OMAP4430_CLKSEL_0_0_WIDTH, - 0x0, init_60m_fclk_rates, NULL); - -DEFINE_CLK_DIVIDER(l3_div_ck, "div_core_ck", &div_core_ck, 0x0, - OMAP4430_CM_CLKSEL_CORE, OMAP4430_CLKSEL_L3_SHIFT, - OMAP4430_CLKSEL_L3_WIDTH, 0x0, NULL); - -DEFINE_CLK_DIVIDER(l4_div_ck, "l3_div_ck", &l3_div_ck, 0x0, - OMAP4430_CM_CLKSEL_CORE, OMAP4430_CLKSEL_L4_SHIFT, - OMAP4430_CLKSEL_L4_WIDTH, 0x0, NULL); - -DEFINE_CLK_FIXED_FACTOR(lp_clk_div_ck, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck, - 0x0, 1, 16); - -static const char *l4_wkup_clk_mux_ck_parents[] = { - "sys_clkin_ck", "lp_clk_div_ck", -}; - -DEFINE_CLK_MUX(l4_wkup_clk_mux_ck, l4_wkup_clk_mux_ck_parents, NULL, 0x0, - OMAP4430_CM_L4_WKUP_CLKSEL, OMAP4430_CLKSEL_0_0_SHIFT, - OMAP4430_CLKSEL_0_0_WIDTH, 0x0, NULL); - -static const struct clk_div_table ocp_abe_iclk_rates[] = { - { .div = 2, .val = 0 }, - { .div = 1, .val = 1 }, - { .div = 0 }, -}; -DEFINE_CLK_DIVIDER_TABLE(ocp_abe_iclk, "aess_fclk", &aess_fclk, 0x0, - OMAP4430_CM1_ABE_AESS_CLKCTRL, - OMAP4430_CLKSEL_AESS_FCLK_SHIFT, - OMAP4430_CLKSEL_AESS_FCLK_WIDTH, - 0x0, ocp_abe_iclk_rates, NULL); - -DEFINE_CLK_FIXED_FACTOR(per_abe_24m_fclk, "dpll_abe_m2_ck", &dpll_abe_m2_ck, - 0x0, 1, 4); - -DEFINE_CLK_DIVIDER(per_abe_nc_fclk, "dpll_abe_m2_ck", &dpll_abe_m2_ck, 0x0, - OMAP4430_CM_SCALE_FCLK, OMAP4430_SCALE_FCLK_SHIFT, - OMAP4430_SCALE_FCLK_WIDTH, 0x0, NULL); - -DEFINE_CLK_DIVIDER(syc_clk_div_ck, "sys_clkin_ck", &sys_clkin_ck, 0x0, - OMAP4430_CM_ABE_DSS_SYS_CLKSEL, OMAP4430_CLKSEL_0_0_SHIFT, - OMAP4430_CLKSEL_0_0_WIDTH, 0x0, NULL); - -static const char *dbgclk_mux_ck_parents[] = { - "sys_clkin_ck" -}; - -static struct clk dbgclk_mux_ck; -DEFINE_STRUCT_CLK_HW_OMAP(dbgclk_mux_ck, NULL); -DEFINE_STRUCT_CLK(dbgclk_mux_ck, dbgclk_mux_ck_parents, - dpll_usb_clkdcoldo_ck_ops); - -/* Leaf clocks controlled by modules */ - -DEFINE_CLK_GATE(aes1_fck, "l3_div_ck", &l3_div_ck, 0x0, - OMAP4430_CM_L4SEC_AES1_CLKCTRL, - OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); - -DEFINE_CLK_GATE(aes2_fck, "l3_div_ck", &l3_div_ck, 0x0, - OMAP4430_CM_L4SEC_AES2_CLKCTRL, - OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); - -DEFINE_CLK_GATE(bandgap_fclk, "sys_32k_ck", &sys_32k_ck, 0x0, - OMAP4430_CM_WKUP_BANDGAP_CLKCTRL, - OMAP4430_OPTFCLKEN_BGAP_32K_SHIFT, 0x0, NULL); - -static const struct clk_div_table div_ts_ck_rates[] = { - { .div = 8, .val = 0 }, - { .div = 16, .val = 1 }, - { .div = 32, .val = 2 }, - { .div = 0 }, -}; -DEFINE_CLK_DIVIDER_TABLE(div_ts_ck, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck, - 0x0, OMAP4430_CM_WKUP_BANDGAP_CLKCTRL, - OMAP4430_CLKSEL_24_25_SHIFT, - OMAP4430_CLKSEL_24_25_WIDTH, 0x0, div_ts_ck_rates, - NULL); - -DEFINE_CLK_GATE(bandgap_ts_fclk, "div_ts_ck", &div_ts_ck, 0x0, - OMAP4430_CM_WKUP_BANDGAP_CLKCTRL, - OMAP4460_OPTFCLKEN_TS_FCLK_SHIFT, - 0x0, NULL); - -static const char *dmic_sync_mux_ck_parents[] = { - "abe_24m_fclk", "syc_clk_div_ck", "func_24m_clk", -}; - -DEFINE_CLK_MUX(dmic_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, - 0x0, OMAP4430_CM1_ABE_DMIC_CLKCTRL, - OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT, - OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL); - -static const struct clksel func_dmic_abe_gfclk_sel[] = { - { .parent = &dmic_sync_mux_ck, .rates = div_1_0_rates }, - { .parent = &pad_clks_ck, .rates = div_1_1_rates }, - { .parent = &slimbus_clk, .rates = div_1_2_rates }, - { .parent = NULL }, -}; - -static const char *func_dmic_abe_gfclk_parents[] = { - "dmic_sync_mux_ck", "pad_clks_ck", "slimbus_clk", -}; - -DEFINE_CLK_OMAP_MUX(func_dmic_abe_gfclk, "abe_clkdm", func_dmic_abe_gfclk_sel, - OMAP4430_CM1_ABE_DMIC_CLKCTRL, OMAP4430_CLKSEL_SOURCE_MASK, - func_dmic_abe_gfclk_parents, func_dmic_abe_gfclk_ops); - -DEFINE_CLK_GATE(dss_sys_clk, "syc_clk_div_ck", &syc_clk_div_ck, 0x0, - OMAP4430_CM_DSS_DSS_CLKCTRL, - OMAP4430_OPTFCLKEN_SYS_CLK_SHIFT, 0x0, NULL); - -DEFINE_CLK_GATE(dss_tv_clk, "extalt_clkin_ck", &extalt_clkin_ck, 0x0, - OMAP4430_CM_DSS_DSS_CLKCTRL, - OMAP4430_OPTFCLKEN_TV_CLK_SHIFT, 0x0, NULL); - -DEFINE_CLK_GATE(dss_dss_clk, "dpll_per_m5x2_ck", &dpll_per_m5x2_ck, - CLK_SET_RATE_PARENT, - OMAP4430_CM_DSS_DSS_CLKCTRL, OMAP4430_OPTFCLKEN_DSSCLK_SHIFT, - 0x0, NULL); - -DEFINE_CLK_GATE(dss_48mhz_clk, "func_48mc_fclk", &func_48mc_fclk, 0x0, - OMAP4430_CM_DSS_DSS_CLKCTRL, OMAP4430_OPTFCLKEN_48MHZ_CLK_SHIFT, - 0x0, NULL); - -DEFINE_CLK_GATE(dss_fck, "l3_div_ck", &l3_div_ck, 0x0, - OMAP4430_CM_DSS_DSS_CLKCTRL, OMAP4430_MODULEMODE_SWCTRL_SHIFT, - 0x0, NULL); - -DEFINE_CLK_DIVIDER(fdif_fck, "dpll_per_m4x2_ck", &dpll_per_m4x2_ck, 0x0, - OMAP4430_CM_CAM_FDIF_CLKCTRL, OMAP4430_CLKSEL_FCLK_SHIFT, - OMAP4430_CLKSEL_FCLK_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL); - -DEFINE_CLK_GATE(gpio1_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0, - OMAP4430_CM_WKUP_GPIO1_CLKCTRL, - OMAP4430_OPTFCLKEN_DBCLK_SHIFT, 0x0, NULL); - -DEFINE_CLK_GATE(gpio2_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0, - OMAP4430_CM_L4PER_GPIO2_CLKCTRL, OMAP4430_OPTFCLKEN_DBCLK_SHIFT, - 0x0, NULL); - -DEFINE_CLK_GATE(gpio3_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0, - OMAP4430_CM_L4PER_GPIO3_CLKCTRL, - OMAP4430_OPTFCLKEN_DBCLK_SHIFT, 0x0, NULL); - -DEFINE_CLK_GATE(gpio4_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0, - OMAP4430_CM_L4PER_GPIO4_CLKCTRL, OMAP4430_OPTFCLKEN_DBCLK_SHIFT, - 0x0, NULL); - -DEFINE_CLK_GATE(gpio5_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0, - OMAP4430_CM_L4PER_GPIO5_CLKCTRL, OMAP4430_OPTFCLKEN_DBCLK_SHIFT, - 0x0, NULL); - -DEFINE_CLK_GATE(gpio6_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0, - OMAP4430_CM_L4PER_GPIO6_CLKCTRL, OMAP4430_OPTFCLKEN_DBCLK_SHIFT, - 0x0, NULL); - -static const struct clksel sgx_clk_mux_sel[] = { - { .parent = &dpll_core_m7x2_ck, .rates = div_1_0_rates }, - { .parent = &dpll_per_m7x2_ck, .rates = div_1_1_rates }, - { .parent = NULL }, -}; - -static const char *sgx_clk_mux_parents[] = { - "dpll_core_m7x2_ck", "dpll_per_m7x2_ck", -}; - -DEFINE_CLK_OMAP_MUX(sgx_clk_mux, "l3_gfx_clkdm", sgx_clk_mux_sel, - OMAP4430_CM_GFX_GFX_CLKCTRL, OMAP4430_CLKSEL_SGX_FCLK_MASK, - sgx_clk_mux_parents, func_dmic_abe_gfclk_ops); - -DEFINE_CLK_DIVIDER(hsi_fck, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck, 0x0, - OMAP4430_CM_L3INIT_HSI_CLKCTRL, OMAP4430_CLKSEL_24_25_SHIFT, - OMAP4430_CLKSEL_24_25_WIDTH, CLK_DIVIDER_POWER_OF_TWO, - NULL); - -DEFINE_CLK_GATE(iss_ctrlclk, "func_96m_fclk", &func_96m_fclk, 0x0, - OMAP4430_CM_CAM_ISS_CLKCTRL, OMAP4430_OPTFCLKEN_CTRLCLK_SHIFT, - 0x0, NULL); - -DEFINE_CLK_MUX(mcasp_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, 0x0, - OMAP4430_CM1_ABE_MCASP_CLKCTRL, - OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT, - OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL); - -static const struct clksel func_mcasp_abe_gfclk_sel[] = { - { .parent = &mcasp_sync_mux_ck, .rates = div_1_0_rates }, - { .parent = &pad_clks_ck, .rates = div_1_1_rates }, - { .parent = &slimbus_clk, .rates = div_1_2_rates }, - { .parent = NULL }, -}; - -static const char *func_mcasp_abe_gfclk_parents[] = { - "mcasp_sync_mux_ck", "pad_clks_ck", "slimbus_clk", -}; - -DEFINE_CLK_OMAP_MUX(func_mcasp_abe_gfclk, "abe_clkdm", func_mcasp_abe_gfclk_sel, - OMAP4430_CM1_ABE_MCASP_CLKCTRL, OMAP4430_CLKSEL_SOURCE_MASK, - func_mcasp_abe_gfclk_parents, func_dmic_abe_gfclk_ops); - -DEFINE_CLK_MUX(mcbsp1_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, 0x0, - OMAP4430_CM1_ABE_MCBSP1_CLKCTRL, - OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT, - OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL); - -static const struct clksel func_mcbsp1_gfclk_sel[] = { - { .parent = &mcbsp1_sync_mux_ck, .rates = div_1_0_rates }, - { .parent = &pad_clks_ck, .rates = div_1_1_rates }, - { .parent = &slimbus_clk, .rates = div_1_2_rates }, - { .parent = NULL }, -}; - -static const char *func_mcbsp1_gfclk_parents[] = { - "mcbsp1_sync_mux_ck", "pad_clks_ck", "slimbus_clk", -}; - -DEFINE_CLK_OMAP_MUX(func_mcbsp1_gfclk, "abe_clkdm", func_mcbsp1_gfclk_sel, - OMAP4430_CM1_ABE_MCBSP1_CLKCTRL, - OMAP4430_CLKSEL_SOURCE_MASK, func_mcbsp1_gfclk_parents, - func_dmic_abe_gfclk_ops); - -DEFINE_CLK_MUX(mcbsp2_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, 0x0, - OMAP4430_CM1_ABE_MCBSP2_CLKCTRL, - OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT, - OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL); - -static const struct clksel func_mcbsp2_gfclk_sel[] = { - { .parent = &mcbsp2_sync_mux_ck, .rates = div_1_0_rates }, - { .parent = &pad_clks_ck, .rates = div_1_1_rates }, - { .parent = &slimbus_clk, .rates = div_1_2_rates }, - { .parent = NULL }, -}; - -static const char *func_mcbsp2_gfclk_parents[] = { - "mcbsp2_sync_mux_ck", "pad_clks_ck", "slimbus_clk", -}; - -DEFINE_CLK_OMAP_MUX(func_mcbsp2_gfclk, "abe_clkdm", func_mcbsp2_gfclk_sel, - OMAP4430_CM1_ABE_MCBSP2_CLKCTRL, - OMAP4430_CLKSEL_SOURCE_MASK, func_mcbsp2_gfclk_parents, - func_dmic_abe_gfclk_ops); - -DEFINE_CLK_MUX(mcbsp3_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, 0x0, - OMAP4430_CM1_ABE_MCBSP3_CLKCTRL, - OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT, - OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL); - -static const struct clksel func_mcbsp3_gfclk_sel[] = { - { .parent = &mcbsp3_sync_mux_ck, .rates = div_1_0_rates }, - { .parent = &pad_clks_ck, .rates = div_1_1_rates }, - { .parent = &slimbus_clk, .rates = div_1_2_rates }, - { .parent = NULL }, -}; - -static const char *func_mcbsp3_gfclk_parents[] = { - "mcbsp3_sync_mux_ck", "pad_clks_ck", "slimbus_clk", -}; - -DEFINE_CLK_OMAP_MUX(func_mcbsp3_gfclk, "abe_clkdm", func_mcbsp3_gfclk_sel, - OMAP4430_CM1_ABE_MCBSP3_CLKCTRL, - OMAP4430_CLKSEL_SOURCE_MASK, func_mcbsp3_gfclk_parents, - func_dmic_abe_gfclk_ops); - -static const char *mcbsp4_sync_mux_ck_parents[] = { - "func_96m_fclk", "per_abe_nc_fclk", -}; - -DEFINE_CLK_MUX(mcbsp4_sync_mux_ck, mcbsp4_sync_mux_ck_parents, NULL, 0x0, - OMAP4430_CM_L4PER_MCBSP4_CLKCTRL, - OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT, - OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL); - -static const struct clksel per_mcbsp4_gfclk_sel[] = { - { .parent = &mcbsp4_sync_mux_ck, .rates = div_1_0_rates }, - { .parent = &pad_clks_ck, .rates = div_1_1_rates }, - { .parent = NULL }, -}; - -static const char *per_mcbsp4_gfclk_parents[] = { - "mcbsp4_sync_mux_ck", "pad_clks_ck", -}; - -DEFINE_CLK_OMAP_MUX(per_mcbsp4_gfclk, "l4_per_clkdm", per_mcbsp4_gfclk_sel, - OMAP4430_CM_L4PER_MCBSP4_CLKCTRL, - OMAP4430_CLKSEL_SOURCE_24_24_MASK, per_mcbsp4_gfclk_parents, - func_dmic_abe_gfclk_ops); - -static const struct clksel hsmmc1_fclk_sel[] = { - { .parent = &func_64m_fclk, .rates = div_1_0_rates }, - { .parent = &func_96m_fclk, .rates = div_1_1_rates }, - { .parent = NULL }, -}; - -static const char *hsmmc1_fclk_parents[] = { - "func_64m_fclk", "func_96m_fclk", -}; - -DEFINE_CLK_OMAP_MUX(hsmmc1_fclk, "l3_init_clkdm", hsmmc1_fclk_sel, - OMAP4430_CM_L3INIT_MMC1_CLKCTRL, OMAP4430_CLKSEL_MASK, - hsmmc1_fclk_parents, func_dmic_abe_gfclk_ops); - -DEFINE_CLK_OMAP_MUX(hsmmc2_fclk, "l3_init_clkdm", hsmmc1_fclk_sel, - OMAP4430_CM_L3INIT_MMC2_CLKCTRL, OMAP4430_CLKSEL_MASK, - hsmmc1_fclk_parents, func_dmic_abe_gfclk_ops); - -DEFINE_CLK_GATE(ocp2scp_usb_phy_phy_48m, "func_48m_fclk", &func_48m_fclk, 0x0, - OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, - OMAP4430_OPTFCLKEN_PHY_48M_SHIFT, 0x0, NULL); - -DEFINE_CLK_GATE(sha2md5_fck, "l3_div_ck", &l3_div_ck, 0x0, - OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL, - OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); - -DEFINE_CLK_GATE(slimbus1_fclk_1, "func_24m_clk", &func_24m_clk, 0x0, - OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL, - OMAP4430_OPTFCLKEN_FCLK1_SHIFT, 0x0, NULL); - -DEFINE_CLK_GATE(slimbus1_fclk_0, "abe_24m_fclk", &abe_24m_fclk, 0x0, - OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL, - OMAP4430_OPTFCLKEN_FCLK0_SHIFT, 0x0, NULL); - -DEFINE_CLK_GATE(slimbus1_fclk_2, "pad_clks_ck", &pad_clks_ck, 0x0, - OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL, - OMAP4430_OPTFCLKEN_FCLK2_SHIFT, 0x0, NULL); - -DEFINE_CLK_GATE(slimbus1_slimbus_clk, "slimbus_clk", &slimbus_clk, 0x0, - OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL, - OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_SHIFT, 0x0, NULL); - -DEFINE_CLK_GATE(slimbus2_fclk_1, "per_abe_24m_fclk", &per_abe_24m_fclk, 0x0, - OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL, - OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_SHIFT, 0x0, NULL); - -DEFINE_CLK_GATE(slimbus2_fclk_0, "func_24mc_fclk", &func_24mc_fclk, 0x0, - OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL, - OMAP4430_OPTFCLKEN_PER24MC_GFCLK_SHIFT, 0x0, NULL); - -DEFINE_CLK_GATE(slimbus2_slimbus_clk, "pad_slimbus_core_clks_ck", - &pad_slimbus_core_clks_ck, 0x0, - OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL, - OMAP4430_OPTFCLKEN_SLIMBUS_CLK_SHIFT, 0x0, NULL); - -DEFINE_CLK_GATE(smartreflex_core_fck, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck, - 0x0, OMAP4430_CM_ALWON_SR_CORE_CLKCTRL, - OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); - -DEFINE_CLK_GATE(smartreflex_iva_fck, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck, - 0x0, OMAP4430_CM_ALWON_SR_IVA_CLKCTRL, - OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); - -DEFINE_CLK_GATE(smartreflex_mpu_fck, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck, - 0x0, OMAP4430_CM_ALWON_SR_MPU_CLKCTRL, - OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); - -static const struct clksel dmt1_clk_mux_sel[] = { - { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, - { .parent = &sys_32k_ck, .rates = div_1_1_rates }, - { .parent = NULL }, -}; - -DEFINE_CLK_OMAP_MUX(dmt1_clk_mux, "l4_wkup_clkdm", dmt1_clk_mux_sel, - OMAP4430_CM_WKUP_TIMER1_CLKCTRL, OMAP4430_CLKSEL_MASK, - abe_dpll_bypass_clk_mux_ck_parents, - func_dmic_abe_gfclk_ops); - -DEFINE_CLK_OMAP_MUX(cm2_dm10_mux, "l4_per_clkdm", dmt1_clk_mux_sel, - OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL, OMAP4430_CLKSEL_MASK, - abe_dpll_bypass_clk_mux_ck_parents, - func_dmic_abe_gfclk_ops); - -DEFINE_CLK_OMAP_MUX(cm2_dm11_mux, "l4_per_clkdm", dmt1_clk_mux_sel, - OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL, OMAP4430_CLKSEL_MASK, - abe_dpll_bypass_clk_mux_ck_parents, - func_dmic_abe_gfclk_ops); - -DEFINE_CLK_OMAP_MUX(cm2_dm2_mux, "l4_per_clkdm", dmt1_clk_mux_sel, - OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL, OMAP4430_CLKSEL_MASK, - abe_dpll_bypass_clk_mux_ck_parents, - func_dmic_abe_gfclk_ops); - -DEFINE_CLK_OMAP_MUX(cm2_dm3_mux, "l4_per_clkdm", dmt1_clk_mux_sel, - OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL, OMAP4430_CLKSEL_MASK, - abe_dpll_bypass_clk_mux_ck_parents, - func_dmic_abe_gfclk_ops); - -DEFINE_CLK_OMAP_MUX(cm2_dm4_mux, "l4_per_clkdm", dmt1_clk_mux_sel, - OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL, OMAP4430_CLKSEL_MASK, - abe_dpll_bypass_clk_mux_ck_parents, - func_dmic_abe_gfclk_ops); - -static const struct clksel timer5_sync_mux_sel[] = { - { .parent = &syc_clk_div_ck, .rates = div_1_0_rates }, - { .parent = &sys_32k_ck, .rates = div_1_1_rates }, - { .parent = NULL }, -}; - -static const char *timer5_sync_mux_parents[] = { - "syc_clk_div_ck", "sys_32k_ck", -}; - -DEFINE_CLK_OMAP_MUX(timer5_sync_mux, "abe_clkdm", timer5_sync_mux_sel, - OMAP4430_CM1_ABE_TIMER5_CLKCTRL, OMAP4430_CLKSEL_MASK, - timer5_sync_mux_parents, func_dmic_abe_gfclk_ops); - -DEFINE_CLK_OMAP_MUX(timer6_sync_mux, "abe_clkdm", timer5_sync_mux_sel, - OMAP4430_CM1_ABE_TIMER6_CLKCTRL, OMAP4430_CLKSEL_MASK, - timer5_sync_mux_parents, func_dmic_abe_gfclk_ops); - -DEFINE_CLK_OMAP_MUX(timer7_sync_mux, "abe_clkdm", timer5_sync_mux_sel, - OMAP4430_CM1_ABE_TIMER7_CLKCTRL, OMAP4430_CLKSEL_MASK, - timer5_sync_mux_parents, func_dmic_abe_gfclk_ops); - -DEFINE_CLK_OMAP_MUX(timer8_sync_mux, "abe_clkdm", timer5_sync_mux_sel, - OMAP4430_CM1_ABE_TIMER8_CLKCTRL, OMAP4430_CLKSEL_MASK, - timer5_sync_mux_parents, func_dmic_abe_gfclk_ops); - -DEFINE_CLK_OMAP_MUX(cm2_dm9_mux, "l4_per_clkdm", dmt1_clk_mux_sel, - OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL, OMAP4430_CLKSEL_MASK, - abe_dpll_bypass_clk_mux_ck_parents, - func_dmic_abe_gfclk_ops); - -static struct clk usb_host_fs_fck; - -static const char *usb_host_fs_fck_parent_names[] = { - "func_48mc_fclk", -}; - -static const struct clk_ops usb_host_fs_fck_ops = { - .enable = &omap2_dflt_clk_enable, - .disable = &omap2_dflt_clk_disable, - .is_enabled = &omap2_dflt_clk_is_enabled, -}; - -static struct clk_hw_omap usb_host_fs_fck_hw = { - .hw = { - .clk = &usb_host_fs_fck, - }, - .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_FS_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL_SHIFT, - .clkdm_name = "l3_init_clkdm", -}; - -DEFINE_STRUCT_CLK(usb_host_fs_fck, usb_host_fs_fck_parent_names, - usb_host_fs_fck_ops); - -static const char *utmi_p1_gfclk_parents[] = { - "init_60m_fclk", "xclk60mhsp1_ck", -}; - -DEFINE_CLK_MUX(utmi_p1_gfclk, utmi_p1_gfclk_parents, NULL, 0x0, - OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, - OMAP4430_CLKSEL_UTMI_P1_SHIFT, OMAP4430_CLKSEL_UTMI_P1_WIDTH, - 0x0, NULL); - -DEFINE_CLK_GATE(usb_host_hs_utmi_p1_clk, "utmi_p1_gfclk", &utmi_p1_gfclk, 0x0, - OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, - OMAP4430_OPTFCLKEN_UTMI_P1_CLK_SHIFT, 0x0, NULL); - -static const char *utmi_p2_gfclk_parents[] = { - "init_60m_fclk", "xclk60mhsp2_ck", -}; - -DEFINE_CLK_MUX(utmi_p2_gfclk, utmi_p2_gfclk_parents, NULL, 0x0, - OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, - OMAP4430_CLKSEL_UTMI_P2_SHIFT, OMAP4430_CLKSEL_UTMI_P2_WIDTH, - 0x0, NULL); - -DEFINE_CLK_GATE(usb_host_hs_utmi_p2_clk, "utmi_p2_gfclk", &utmi_p2_gfclk, 0x0, - OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, - OMAP4430_OPTFCLKEN_UTMI_P2_CLK_SHIFT, 0x0, NULL); - -DEFINE_CLK_GATE(usb_host_hs_utmi_p3_clk, "init_60m_fclk", &init_60m_fclk, 0x0, - OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, - OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT, 0x0, NULL); - -DEFINE_CLK_GATE(usb_host_hs_hsic480m_p1_clk, "dpll_usb_m2_ck", - &dpll_usb_m2_ck, 0x0, - OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, - OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT, 0x0, NULL); - -DEFINE_CLK_GATE(usb_host_hs_hsic60m_p1_clk, "init_60m_fclk", - &init_60m_fclk, 0x0, - OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, - OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT, 0x0, NULL); - -DEFINE_CLK_GATE(usb_host_hs_hsic60m_p2_clk, "init_60m_fclk", - &init_60m_fclk, 0x0, - OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, - OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT, 0x0, NULL); - -DEFINE_CLK_GATE(usb_host_hs_hsic480m_p2_clk, "dpll_usb_m2_ck", - &dpll_usb_m2_ck, 0x0, - OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, - OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT, 0x0, NULL); - -DEFINE_CLK_GATE(usb_host_hs_func48mclk, "func_48mc_fclk", &func_48mc_fclk, 0x0, - OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, - OMAP4430_OPTFCLKEN_FUNC48MCLK_SHIFT, 0x0, NULL); - -DEFINE_CLK_GATE(usb_host_hs_fck, "init_60m_fclk", &init_60m_fclk, 0x0, - OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, - OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); - -static const char *otg_60m_gfclk_parents[] = { - "utmi_phy_clkout_ck", "xclk60motg_ck", -}; - -DEFINE_CLK_MUX(otg_60m_gfclk, otg_60m_gfclk_parents, NULL, 0x0, - OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL, OMAP4430_CLKSEL_60M_SHIFT, - OMAP4430_CLKSEL_60M_WIDTH, 0x0, NULL); - -DEFINE_CLK_GATE(usb_otg_hs_xclk, "otg_60m_gfclk", &otg_60m_gfclk, 0x0, - OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL, - OMAP4430_OPTFCLKEN_XCLK_SHIFT, 0x0, NULL); - -DEFINE_CLK_GATE(usb_otg_hs_ick, "l3_div_ck", &l3_div_ck, 0x0, - OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL, - OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL); - -DEFINE_CLK_GATE(usb_phy_cm_clk32k, "sys_32k_ck", &sys_32k_ck, 0x0, - OMAP4430_CM_ALWON_USBPHY_CLKCTRL, - OMAP4430_OPTFCLKEN_CLK32K_SHIFT, 0x0, NULL); - -DEFINE_CLK_GATE(usb_tll_hs_usb_ch2_clk, "init_60m_fclk", &init_60m_fclk, 0x0, - OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL, - OMAP4430_OPTFCLKEN_USB_CH2_CLK_SHIFT, 0x0, NULL); - -DEFINE_CLK_GATE(usb_tll_hs_usb_ch0_clk, "init_60m_fclk", &init_60m_fclk, 0x0, - OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL, - OMAP4430_OPTFCLKEN_USB_CH0_CLK_SHIFT, 0x0, NULL); - -DEFINE_CLK_GATE(usb_tll_hs_usb_ch1_clk, "init_60m_fclk", &init_60m_fclk, 0x0, - OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL, - OMAP4430_OPTFCLKEN_USB_CH1_CLK_SHIFT, 0x0, NULL); - -DEFINE_CLK_GATE(usb_tll_hs_ick, "l4_div_ck", &l4_div_ck, 0x0, - OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL, - OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL); - -static const struct clk_div_table usim_ck_rates[] = { - { .div = 14, .val = 0 }, - { .div = 18, .val = 1 }, - { .div = 0 }, -}; -DEFINE_CLK_DIVIDER_TABLE(usim_ck, "dpll_per_m4x2_ck", &dpll_per_m4x2_ck, 0x0, - OMAP4430_CM_WKUP_USIM_CLKCTRL, - OMAP4430_CLKSEL_DIV_SHIFT, OMAP4430_CLKSEL_DIV_WIDTH, - 0x0, usim_ck_rates, NULL); - -DEFINE_CLK_GATE(usim_fclk, "usim_ck", &usim_ck, 0x0, - OMAP4430_CM_WKUP_USIM_CLKCTRL, OMAP4430_OPTFCLKEN_FCLK_SHIFT, - 0x0, NULL); - -/* Remaining optional clocks */ -static const char *pmd_stm_clock_mux_ck_parents[] = { - "sys_clkin_ck", "dpll_core_m6x2_ck", "tie_low_clock_ck", -}; - -DEFINE_CLK_MUX(pmd_stm_clock_mux_ck, pmd_stm_clock_mux_ck_parents, NULL, 0x0, - OMAP4430_CM_EMU_DEBUGSS_CLKCTRL, OMAP4430_PMD_STM_MUX_CTRL_SHIFT, - OMAP4430_PMD_STM_MUX_CTRL_WIDTH, 0x0, NULL); - -DEFINE_CLK_MUX(pmd_trace_clk_mux_ck, pmd_stm_clock_mux_ck_parents, NULL, 0x0, - OMAP4430_CM_EMU_DEBUGSS_CLKCTRL, - OMAP4430_PMD_TRACE_MUX_CTRL_SHIFT, - OMAP4430_PMD_TRACE_MUX_CTRL_WIDTH, 0x0, NULL); - -DEFINE_CLK_DIVIDER(stm_clk_div_ck, "pmd_stm_clock_mux_ck", - &pmd_stm_clock_mux_ck, 0x0, OMAP4430_CM_EMU_DEBUGSS_CLKCTRL, - OMAP4430_CLKSEL_PMD_STM_CLK_SHIFT, - OMAP4430_CLKSEL_PMD_STM_CLK_WIDTH, CLK_DIVIDER_POWER_OF_TWO, - NULL); - -static const char *trace_clk_div_ck_parents[] = { - "pmd_trace_clk_mux_ck", -}; - -static const struct clksel trace_clk_div_div[] = { - { .parent = &pmd_trace_clk_mux_ck, .rates = div3_1to4_rates }, - { .parent = NULL }, -}; - -static struct clk trace_clk_div_ck; - -static const struct clk_ops trace_clk_div_ck_ops = { - .recalc_rate = &omap2_clksel_recalc, - .set_rate = &omap2_clksel_set_rate, - .round_rate = &omap2_clksel_round_rate, - .init = &omap2_init_clk_clkdm, - .enable = &omap2_clkops_enable_clkdm, - .disable = &omap2_clkops_disable_clkdm, -}; - -static struct clk_hw_omap trace_clk_div_ck_hw = { - .hw = { - .clk = &trace_clk_div_ck, - }, - .clkdm_name = "emu_sys_clkdm", - .clksel = trace_clk_div_div, - .clksel_reg = OMAP4430_CM_EMU_DEBUGSS_CLKCTRL, - .clksel_mask = OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK, -}; - -DEFINE_STRUCT_CLK(trace_clk_div_ck, trace_clk_div_ck_parents, - trace_clk_div_ck_ops); - -/* SCRM aux clk nodes */ - -static const struct clksel auxclk_src_sel[] = { - { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, - { .parent = &dpll_core_m3x2_ck, .rates = div_1_1_rates }, - { .parent = &dpll_per_m3x2_ck, .rates = div_1_2_rates }, - { .parent = NULL }, -}; - -static const char *auxclk_src_ck_parents[] = { - "sys_clkin_ck", "dpll_core_m3x2_ck", "dpll_per_m3x2_ck", -}; - -static const struct clk_ops auxclk_src_ck_ops = { - .enable = &omap2_dflt_clk_enable, - .disable = &omap2_dflt_clk_disable, - .is_enabled = &omap2_dflt_clk_is_enabled, - .recalc_rate = &omap2_clksel_recalc, - .get_parent = &omap2_clksel_find_parent_index, -}; - -DEFINE_CLK_OMAP_MUX_GATE(auxclk0_src_ck, NULL, auxclk_src_sel, - OMAP4_SCRM_AUXCLK0, OMAP4_SRCSELECT_MASK, - OMAP4_SCRM_AUXCLK0, OMAP4_ENABLE_SHIFT, NULL, - auxclk_src_ck_parents, auxclk_src_ck_ops); - -DEFINE_CLK_DIVIDER(auxclk0_ck, "auxclk0_src_ck", &auxclk0_src_ck, 0x0, - OMAP4_SCRM_AUXCLK0, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH, - 0x0, NULL); - -DEFINE_CLK_OMAP_MUX_GATE(auxclk1_src_ck, NULL, auxclk_src_sel, - OMAP4_SCRM_AUXCLK1, OMAP4_SRCSELECT_MASK, - OMAP4_SCRM_AUXCLK1, OMAP4_ENABLE_SHIFT, NULL, - auxclk_src_ck_parents, auxclk_src_ck_ops); - -DEFINE_CLK_DIVIDER(auxclk1_ck, "auxclk1_src_ck", &auxclk1_src_ck, 0x0, - OMAP4_SCRM_AUXCLK1, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH, - 0x0, NULL); - -DEFINE_CLK_OMAP_MUX_GATE(auxclk2_src_ck, NULL, auxclk_src_sel, - OMAP4_SCRM_AUXCLK2, OMAP4_SRCSELECT_MASK, - OMAP4_SCRM_AUXCLK2, OMAP4_ENABLE_SHIFT, NULL, - auxclk_src_ck_parents, auxclk_src_ck_ops); - -DEFINE_CLK_DIVIDER(auxclk2_ck, "auxclk2_src_ck", &auxclk2_src_ck, 0x0, - OMAP4_SCRM_AUXCLK2, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH, - 0x0, NULL); - -DEFINE_CLK_OMAP_MUX_GATE(auxclk3_src_ck, NULL, auxclk_src_sel, - OMAP4_SCRM_AUXCLK3, OMAP4_SRCSELECT_MASK, - OMAP4_SCRM_AUXCLK3, OMAP4_ENABLE_SHIFT, NULL, - auxclk_src_ck_parents, auxclk_src_ck_ops); - -DEFINE_CLK_DIVIDER(auxclk3_ck, "auxclk3_src_ck", &auxclk3_src_ck, 0x0, - OMAP4_SCRM_AUXCLK3, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH, - 0x0, NULL); - -DEFINE_CLK_OMAP_MUX_GATE(auxclk4_src_ck, NULL, auxclk_src_sel, - OMAP4_SCRM_AUXCLK4, OMAP4_SRCSELECT_MASK, - OMAP4_SCRM_AUXCLK4, OMAP4_ENABLE_SHIFT, NULL, - auxclk_src_ck_parents, auxclk_src_ck_ops); - -DEFINE_CLK_DIVIDER(auxclk4_ck, "auxclk4_src_ck", &auxclk4_src_ck, 0x0, - OMAP4_SCRM_AUXCLK4, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH, - 0x0, NULL); - -DEFINE_CLK_OMAP_MUX_GATE(auxclk5_src_ck, NULL, auxclk_src_sel, - OMAP4_SCRM_AUXCLK5, OMAP4_SRCSELECT_MASK, - OMAP4_SCRM_AUXCLK5, OMAP4_ENABLE_SHIFT, NULL, - auxclk_src_ck_parents, auxclk_src_ck_ops); - -DEFINE_CLK_DIVIDER(auxclk5_ck, "auxclk5_src_ck", &auxclk5_src_ck, 0x0, - OMAP4_SCRM_AUXCLK5, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH, - 0x0, NULL); - -static const char *auxclkreq_ck_parents[] = { - "auxclk0_ck", "auxclk1_ck", "auxclk2_ck", "auxclk3_ck", "auxclk4_ck", - "auxclk5_ck", -}; - -DEFINE_CLK_MUX(auxclkreq0_ck, auxclkreq_ck_parents, NULL, 0x0, - OMAP4_SCRM_AUXCLKREQ0, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH, - 0x0, NULL); - -DEFINE_CLK_MUX(auxclkreq1_ck, auxclkreq_ck_parents, NULL, 0x0, - OMAP4_SCRM_AUXCLKREQ1, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH, - 0x0, NULL); - -DEFINE_CLK_MUX(auxclkreq2_ck, auxclkreq_ck_parents, NULL, 0x0, - OMAP4_SCRM_AUXCLKREQ2, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH, - 0x0, NULL); - -DEFINE_CLK_MUX(auxclkreq3_ck, auxclkreq_ck_parents, NULL, 0x0, - OMAP4_SCRM_AUXCLKREQ3, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH, - 0x0, NULL); - -DEFINE_CLK_MUX(auxclkreq4_ck, auxclkreq_ck_parents, NULL, 0x0, - OMAP4_SCRM_AUXCLKREQ4, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH, - 0x0, NULL); - -DEFINE_CLK_MUX(auxclkreq5_ck, auxclkreq_ck_parents, NULL, 0x0, - OMAP4_SCRM_AUXCLKREQ5, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH, - 0x0, NULL); - -/* - * clocks specific to omap4460 - */ -static struct omap_clk omap446x_clks[] = { - CLK(NULL, "div_ts_ck", &div_ts_ck), - CLK(NULL, "bandgap_ts_fclk", &bandgap_ts_fclk), -}; - -/* - * clocks specific to omap4430 - */ -static struct omap_clk omap443x_clks[] = { - CLK(NULL, "bandgap_fclk", &bandgap_fclk), -}; - -/* - * clocks common to omap44xx - */ -static struct omap_clk omap44xx_clks[] = { - CLK(NULL, "extalt_clkin_ck", &extalt_clkin_ck), - CLK(NULL, "pad_clks_src_ck", &pad_clks_src_ck), - CLK(NULL, "pad_clks_ck", &pad_clks_ck), - CLK(NULL, "pad_slimbus_core_clks_ck", &pad_slimbus_core_clks_ck), - CLK(NULL, "secure_32k_clk_src_ck", &secure_32k_clk_src_ck), - CLK(NULL, "slimbus_src_clk", &slimbus_src_clk), - CLK(NULL, "slimbus_clk", &slimbus_clk), - CLK(NULL, "sys_32k_ck", &sys_32k_ck), - CLK(NULL, "virt_12000000_ck", &virt_12000000_ck), - CLK(NULL, "virt_13000000_ck", &virt_13000000_ck), - CLK(NULL, "virt_16800000_ck", &virt_16800000_ck), - CLK(NULL, "virt_19200000_ck", &virt_19200000_ck), - CLK(NULL, "virt_26000000_ck", &virt_26000000_ck), - CLK(NULL, "virt_27000000_ck", &virt_27000000_ck), - CLK(NULL, "virt_38400000_ck", &virt_38400000_ck), - CLK(NULL, "sys_clkin_ck", &sys_clkin_ck), - CLK(NULL, "tie_low_clock_ck", &tie_low_clock_ck), - CLK(NULL, "utmi_phy_clkout_ck", &utmi_phy_clkout_ck), - CLK(NULL, "xclk60mhsp1_ck", &xclk60mhsp1_ck), - CLK(NULL, "xclk60mhsp2_ck", &xclk60mhsp2_ck), - CLK(NULL, "xclk60motg_ck", &xclk60motg_ck), - CLK(NULL, "abe_dpll_bypass_clk_mux_ck", &abe_dpll_bypass_clk_mux_ck), - CLK(NULL, "abe_dpll_refclk_mux_ck", &abe_dpll_refclk_mux_ck), - CLK(NULL, "dpll_abe_ck", &dpll_abe_ck), - CLK(NULL, "dpll_abe_x2_ck", &dpll_abe_x2_ck), - CLK(NULL, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck), - CLK(NULL, "abe_24m_fclk", &abe_24m_fclk), - CLK(NULL, "abe_clk", &abe_clk), - CLK(NULL, "aess_fclk", &aess_fclk), - CLK(NULL, "dpll_abe_m3x2_ck", &dpll_abe_m3x2_ck), - CLK(NULL, "core_hsd_byp_clk_mux_ck", &core_hsd_byp_clk_mux_ck), - CLK(NULL, "dpll_core_ck", &dpll_core_ck), - CLK(NULL, "dpll_core_x2_ck", &dpll_core_x2_ck), - CLK(NULL, "dpll_core_m6x2_ck", &dpll_core_m6x2_ck), - CLK(NULL, "dbgclk_mux_ck", &dbgclk_mux_ck), - CLK(NULL, "dpll_core_m2_ck", &dpll_core_m2_ck), - CLK(NULL, "ddrphy_ck", &ddrphy_ck), - CLK(NULL, "dpll_core_m5x2_ck", &dpll_core_m5x2_ck), - CLK(NULL, "div_core_ck", &div_core_ck), - CLK(NULL, "div_iva_hs_clk", &div_iva_hs_clk), - CLK(NULL, "div_mpu_hs_clk", &div_mpu_hs_clk), - CLK(NULL, "dpll_core_m4x2_ck", &dpll_core_m4x2_ck), - CLK(NULL, "dll_clk_div_ck", &dll_clk_div_ck), - CLK(NULL, "dpll_abe_m2_ck", &dpll_abe_m2_ck), - CLK(NULL, "dpll_core_m3x2_ck", &dpll_core_m3x2_ck), - CLK(NULL, "dpll_core_m7x2_ck", &dpll_core_m7x2_ck), - CLK(NULL, "iva_hsd_byp_clk_mux_ck", &iva_hsd_byp_clk_mux_ck), - CLK(NULL, "dpll_iva_ck", &dpll_iva_ck), - CLK(NULL, "dpll_iva_x2_ck", &dpll_iva_x2_ck), - CLK(NULL, "dpll_iva_m4x2_ck", &dpll_iva_m4x2_ck), - CLK(NULL, "dpll_iva_m5x2_ck", &dpll_iva_m5x2_ck), - CLK(NULL, "dpll_mpu_ck", &dpll_mpu_ck), - CLK(NULL, "dpll_mpu_m2_ck", &dpll_mpu_m2_ck), - CLK(NULL, "per_hs_clk_div_ck", &per_hs_clk_div_ck), - CLK(NULL, "per_hsd_byp_clk_mux_ck", &per_hsd_byp_clk_mux_ck), - CLK(NULL, "dpll_per_ck", &dpll_per_ck), - CLK(NULL, "dpll_per_m2_ck", &dpll_per_m2_ck), - CLK(NULL, "dpll_per_x2_ck", &dpll_per_x2_ck), - CLK(NULL, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck), - CLK(NULL, "dpll_per_m3x2_ck", &dpll_per_m3x2_ck), - CLK(NULL, "dpll_per_m4x2_ck", &dpll_per_m4x2_ck), - CLK(NULL, "dpll_per_m5x2_ck", &dpll_per_m5x2_ck), - CLK(NULL, "dpll_per_m6x2_ck", &dpll_per_m6x2_ck), - CLK(NULL, "dpll_per_m7x2_ck", &dpll_per_m7x2_ck), - CLK(NULL, "usb_hs_clk_div_ck", &usb_hs_clk_div_ck), - CLK(NULL, "dpll_usb_ck", &dpll_usb_ck), - CLK(NULL, "dpll_usb_clkdcoldo_ck", &dpll_usb_clkdcoldo_ck), - CLK(NULL, "dpll_usb_m2_ck", &dpll_usb_m2_ck), - CLK(NULL, "ducati_clk_mux_ck", &ducati_clk_mux_ck), - CLK(NULL, "func_12m_fclk", &func_12m_fclk), - CLK(NULL, "func_24m_clk", &func_24m_clk), - CLK(NULL, "func_24mc_fclk", &func_24mc_fclk), - CLK(NULL, "func_48m_fclk", &func_48m_fclk), - CLK(NULL, "func_48mc_fclk", &func_48mc_fclk), - CLK(NULL, "func_64m_fclk", &func_64m_fclk), - CLK(NULL, "func_96m_fclk", &func_96m_fclk), - CLK(NULL, "init_60m_fclk", &init_60m_fclk), - CLK(NULL, "l3_div_ck", &l3_div_ck), - CLK(NULL, "l4_div_ck", &l4_div_ck), - CLK(NULL, "lp_clk_div_ck", &lp_clk_div_ck), - CLK(NULL, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck), - CLK("smp_twd", NULL, &mpu_periphclk), - CLK(NULL, "ocp_abe_iclk", &ocp_abe_iclk), - CLK(NULL, "per_abe_24m_fclk", &per_abe_24m_fclk), - CLK(NULL, "per_abe_nc_fclk", &per_abe_nc_fclk), - CLK(NULL, "syc_clk_div_ck", &syc_clk_div_ck), - CLK(NULL, "aes1_fck", &aes1_fck), - CLK(NULL, "aes2_fck", &aes2_fck), - CLK(NULL, "dmic_sync_mux_ck", &dmic_sync_mux_ck), - CLK(NULL, "func_dmic_abe_gfclk", &func_dmic_abe_gfclk), - CLK(NULL, "dss_sys_clk", &dss_sys_clk), - CLK(NULL, "dss_tv_clk", &dss_tv_clk), - CLK(NULL, "dss_dss_clk", &dss_dss_clk), - CLK(NULL, "dss_48mhz_clk", &dss_48mhz_clk), - CLK(NULL, "dss_fck", &dss_fck), - CLK("omapdss_dss", "ick", &dss_fck), - CLK(NULL, "fdif_fck", &fdif_fck), - CLK(NULL, "gpio1_dbclk", &gpio1_dbclk), - CLK(NULL, "gpio2_dbclk", &gpio2_dbclk), - CLK(NULL, "gpio3_dbclk", &gpio3_dbclk), - CLK(NULL, "gpio4_dbclk", &gpio4_dbclk), - CLK(NULL, "gpio5_dbclk", &gpio5_dbclk), - CLK(NULL, "gpio6_dbclk", &gpio6_dbclk), - CLK(NULL, "sgx_clk_mux", &sgx_clk_mux), - CLK(NULL, "hsi_fck", &hsi_fck), - CLK(NULL, "iss_ctrlclk", &iss_ctrlclk), - CLK(NULL, "mcasp_sync_mux_ck", &mcasp_sync_mux_ck), - CLK(NULL, "func_mcasp_abe_gfclk", &func_mcasp_abe_gfclk), - CLK(NULL, "mcbsp1_sync_mux_ck", &mcbsp1_sync_mux_ck), - CLK(NULL, "func_mcbsp1_gfclk", &func_mcbsp1_gfclk), - CLK(NULL, "mcbsp2_sync_mux_ck", &mcbsp2_sync_mux_ck), - CLK(NULL, "func_mcbsp2_gfclk", &func_mcbsp2_gfclk), - CLK(NULL, "mcbsp3_sync_mux_ck", &mcbsp3_sync_mux_ck), - CLK(NULL, "func_mcbsp3_gfclk", &func_mcbsp3_gfclk), - CLK(NULL, "mcbsp4_sync_mux_ck", &mcbsp4_sync_mux_ck), - CLK(NULL, "per_mcbsp4_gfclk", &per_mcbsp4_gfclk), - CLK(NULL, "hsmmc1_fclk", &hsmmc1_fclk), - CLK(NULL, "hsmmc2_fclk", &hsmmc2_fclk), - CLK(NULL, "ocp2scp_usb_phy_phy_48m", &ocp2scp_usb_phy_phy_48m), - CLK(NULL, "sha2md5_fck", &sha2md5_fck), - CLK(NULL, "slimbus1_fclk_1", &slimbus1_fclk_1), - CLK(NULL, "slimbus1_fclk_0", &slimbus1_fclk_0), - CLK(NULL, "slimbus1_fclk_2", &slimbus1_fclk_2), - CLK(NULL, "slimbus1_slimbus_clk", &slimbus1_slimbus_clk), - CLK(NULL, "slimbus2_fclk_1", &slimbus2_fclk_1), - CLK(NULL, "slimbus2_fclk_0", &slimbus2_fclk_0), - CLK(NULL, "slimbus2_slimbus_clk", &slimbus2_slimbus_clk), - CLK(NULL, "smartreflex_core_fck", &smartreflex_core_fck), - CLK(NULL, "smartreflex_iva_fck", &smartreflex_iva_fck), - CLK(NULL, "smartreflex_mpu_fck", &smartreflex_mpu_fck), - CLK(NULL, "dmt1_clk_mux", &dmt1_clk_mux), - CLK(NULL, "cm2_dm10_mux", &cm2_dm10_mux), - CLK(NULL, "cm2_dm11_mux", &cm2_dm11_mux), - CLK(NULL, "cm2_dm2_mux", &cm2_dm2_mux), - CLK(NULL, "cm2_dm3_mux", &cm2_dm3_mux), - CLK(NULL, "cm2_dm4_mux", &cm2_dm4_mux), - CLK(NULL, "timer5_sync_mux", &timer5_sync_mux), - CLK(NULL, "timer6_sync_mux", &timer6_sync_mux), - CLK(NULL, "timer7_sync_mux", &timer7_sync_mux), - CLK(NULL, "timer8_sync_mux", &timer8_sync_mux), - CLK(NULL, "cm2_dm9_mux", &cm2_dm9_mux), - CLK(NULL, "usb_host_fs_fck", &usb_host_fs_fck), - CLK("usbhs_omap", "fs_fck", &usb_host_fs_fck), - CLK(NULL, "utmi_p1_gfclk", &utmi_p1_gfclk), - CLK(NULL, "usb_host_hs_utmi_p1_clk", &usb_host_hs_utmi_p1_clk), - CLK(NULL, "utmi_p2_gfclk", &utmi_p2_gfclk), - CLK(NULL, "usb_host_hs_utmi_p2_clk", &usb_host_hs_utmi_p2_clk), - CLK(NULL, "usb_host_hs_utmi_p3_clk", &usb_host_hs_utmi_p3_clk), - CLK(NULL, "usb_host_hs_hsic480m_p1_clk", &usb_host_hs_hsic480m_p1_clk), - CLK(NULL, "usb_host_hs_hsic60m_p1_clk", &usb_host_hs_hsic60m_p1_clk), - CLK(NULL, "usb_host_hs_hsic60m_p2_clk", &usb_host_hs_hsic60m_p2_clk), - CLK(NULL, "usb_host_hs_hsic480m_p2_clk", &usb_host_hs_hsic480m_p2_clk), - CLK(NULL, "usb_host_hs_func48mclk", &usb_host_hs_func48mclk), - CLK(NULL, "usb_host_hs_fck", &usb_host_hs_fck), - CLK("usbhs_omap", "hs_fck", &usb_host_hs_fck), - CLK(NULL, "otg_60m_gfclk", &otg_60m_gfclk), - CLK(NULL, "usb_otg_hs_xclk", &usb_otg_hs_xclk), - CLK(NULL, "usb_otg_hs_ick", &usb_otg_hs_ick), - CLK("musb-omap2430", "ick", &usb_otg_hs_ick), - CLK(NULL, "usb_phy_cm_clk32k", &usb_phy_cm_clk32k), - CLK(NULL, "usb_tll_hs_usb_ch2_clk", &usb_tll_hs_usb_ch2_clk), - CLK(NULL, "usb_tll_hs_usb_ch0_clk", &usb_tll_hs_usb_ch0_clk), - CLK(NULL, "usb_tll_hs_usb_ch1_clk", &usb_tll_hs_usb_ch1_clk), - CLK(NULL, "usb_tll_hs_ick", &usb_tll_hs_ick), - CLK("usbhs_omap", "usbtll_ick", &usb_tll_hs_ick), - CLK("usbhs_tll", "usbtll_ick", &usb_tll_hs_ick), - CLK(NULL, "usim_ck", &usim_ck), - CLK(NULL, "usim_fclk", &usim_fclk), - CLK(NULL, "pmd_stm_clock_mux_ck", &pmd_stm_clock_mux_ck), - CLK(NULL, "pmd_trace_clk_mux_ck", &pmd_trace_clk_mux_ck), - CLK(NULL, "stm_clk_div_ck", &stm_clk_div_ck), - CLK(NULL, "trace_clk_div_ck", &trace_clk_div_ck), - CLK(NULL, "auxclk0_src_ck", &auxclk0_src_ck), - CLK(NULL, "auxclk0_ck", &auxclk0_ck), - CLK(NULL, "auxclkreq0_ck", &auxclkreq0_ck), - CLK(NULL, "auxclk1_src_ck", &auxclk1_src_ck), - CLK(NULL, "auxclk1_ck", &auxclk1_ck), - CLK(NULL, "auxclkreq1_ck", &auxclkreq1_ck), - CLK(NULL, "auxclk2_src_ck", &auxclk2_src_ck), - CLK(NULL, "auxclk2_ck", &auxclk2_ck), - CLK(NULL, "auxclkreq2_ck", &auxclkreq2_ck), - CLK(NULL, "auxclk3_src_ck", &auxclk3_src_ck), - CLK(NULL, "auxclk3_ck", &auxclk3_ck), - CLK(NULL, "auxclkreq3_ck", &auxclkreq3_ck), - CLK(NULL, "auxclk4_src_ck", &auxclk4_src_ck), - CLK(NULL, "auxclk4_ck", &auxclk4_ck), - CLK(NULL, "auxclkreq4_ck", &auxclkreq4_ck), - CLK(NULL, "auxclk5_src_ck", &auxclk5_src_ck), - CLK(NULL, "auxclk5_ck", &auxclk5_ck), - CLK(NULL, "auxclkreq5_ck", &auxclkreq5_ck), - CLK("50000000.gpmc", "fck", &dummy_ck), - CLK("omap_i2c.1", "ick", &dummy_ck), - CLK("omap_i2c.2", "ick", &dummy_ck), - CLK("omap_i2c.3", "ick", &dummy_ck), - CLK("omap_i2c.4", "ick", &dummy_ck), - CLK(NULL, "mailboxes_ick", &dummy_ck), - CLK("omap_hsmmc.0", "ick", &dummy_ck), - CLK("omap_hsmmc.1", "ick", &dummy_ck), - CLK("omap_hsmmc.2", "ick", &dummy_ck), - CLK("omap_hsmmc.3", "ick", &dummy_ck), - CLK("omap_hsmmc.4", "ick", &dummy_ck), - CLK("omap-mcbsp.1", "ick", &dummy_ck), - CLK("omap-mcbsp.2", "ick", &dummy_ck), - CLK("omap-mcbsp.3", "ick", &dummy_ck), - CLK("omap-mcbsp.4", "ick", &dummy_ck), - CLK("omap2_mcspi.1", "ick", &dummy_ck), - CLK("omap2_mcspi.2", "ick", &dummy_ck), - CLK("omap2_mcspi.3", "ick", &dummy_ck), - CLK("omap2_mcspi.4", "ick", &dummy_ck), - CLK(NULL, "uart1_ick", &dummy_ck), - CLK(NULL, "uart2_ick", &dummy_ck), - CLK(NULL, "uart3_ick", &dummy_ck), - CLK(NULL, "uart4_ick", &dummy_ck), - CLK("usbhs_omap", "usbhost_ick", &dummy_ck), - CLK("usbhs_omap", "usbtll_fck", &dummy_ck), - CLK("usbhs_tll", "usbtll_fck", &dummy_ck), - CLK("omap_wdt", "ick", &dummy_ck), - CLK(NULL, "timer_32k_ck", &sys_32k_ck), - /* TODO: Remove "omap_timer.X" aliases once DT migration is complete */ - CLK("omap_timer.1", "timer_sys_ck", &sys_clkin_ck), - CLK("omap_timer.2", "timer_sys_ck", &sys_clkin_ck), - CLK("omap_timer.3", "timer_sys_ck", &sys_clkin_ck), - CLK("omap_timer.4", "timer_sys_ck", &sys_clkin_ck), - CLK("omap_timer.9", "timer_sys_ck", &sys_clkin_ck), - CLK("omap_timer.10", "timer_sys_ck", &sys_clkin_ck), - CLK("omap_timer.11", "timer_sys_ck", &sys_clkin_ck), - CLK("omap_timer.5", "timer_sys_ck", &syc_clk_div_ck), - CLK("omap_timer.6", "timer_sys_ck", &syc_clk_div_ck), - CLK("omap_timer.7", "timer_sys_ck", &syc_clk_div_ck), - CLK("omap_timer.8", "timer_sys_ck", &syc_clk_div_ck), - CLK("4a318000.timer", "timer_sys_ck", &sys_clkin_ck), - CLK("48032000.timer", "timer_sys_ck", &sys_clkin_ck), - CLK("48034000.timer", "timer_sys_ck", &sys_clkin_ck), - CLK("48036000.timer", "timer_sys_ck", &sys_clkin_ck), - CLK("4803e000.timer", "timer_sys_ck", &sys_clkin_ck), - CLK("48086000.timer", "timer_sys_ck", &sys_clkin_ck), - CLK("48088000.timer", "timer_sys_ck", &sys_clkin_ck), - CLK("40138000.timer", "timer_sys_ck", &syc_clk_div_ck), - CLK("4013a000.timer", "timer_sys_ck", &syc_clk_div_ck), - CLK("4013c000.timer", "timer_sys_ck", &syc_clk_div_ck), - CLK("4013e000.timer", "timer_sys_ck", &syc_clk_div_ck), - CLK(NULL, "cpufreq_ck", &dpll_mpu_ck), -}; - -int __init omap4xxx_clk_init(void) -{ - int rc; - - if (cpu_is_omap443x()) { - cpu_mask = RATE_IN_4430; - omap_clocks_register(omap443x_clks, ARRAY_SIZE(omap443x_clks)); - } else if (cpu_is_omap446x() || cpu_is_omap447x()) { - cpu_mask = RATE_IN_4460 | RATE_IN_4430; - omap_clocks_register(omap446x_clks, ARRAY_SIZE(omap446x_clks)); - if (cpu_is_omap447x()) - pr_warn("WARNING: OMAP4470 clock data incomplete!\n"); - } else { - return 0; - } - - omap_clocks_register(omap44xx_clks, ARRAY_SIZE(omap44xx_clks)); - - omap2_clk_disable_autoidle_all(); - - /* - * A set rate of ABE DPLL inturn triggers a set rate of USB DPLL - * when its in bypass. So always lock USB before ABE DPLL. - */ - /* - * Lock USB DPLL on OMAP4 devices so that the L3INIT power - * domain can transition to retention state when not in use. - */ - rc = clk_set_rate(&dpll_usb_ck, OMAP4_DPLL_USB_DEFFREQ); - if (rc) - pr_err("%s: failed to configure USB DPLL!\n", __func__); - - /* - * On OMAP4460 the ABE DPLL fails to turn on if in idle low-power - * state when turning the ABE clock domain. Workaround this by - * locking the ABE DPLL on boot. - * Lock the ABE DPLL in any case to avoid issues with audio. - */ - rc = clk_set_parent(&abe_dpll_refclk_mux_ck, &sys_32k_ck); - if (!rc) - rc = clk_set_rate(&dpll_abe_ck, OMAP4_DPLL_ABE_DEFFREQ); - if (rc) - pr_err("%s: failed to configure ABE DPLL!\n", __func__); - - return 0; -} diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c index 8517a62a97f0..c95b836f81aa 100644 --- a/arch/arm/mach-omap2/io.c +++ b/arch/arm/mach-omap2/io.c @@ -635,7 +635,7 @@ void __init omap4430_init_early(void) omap44xx_clockdomains_init(); omap44xx_hwmod_init(); omap_hwmod_init_postsetup(); - omap_clk_soc_init = omap4xxx_clk_init; + omap_clk_soc_init = omap4xxx_dt_clk_init; } void __init omap4430_init_late(void) -- cgit v1.2.3-59-g8ed1b From f1cf498ea88caa47f02ca384b2eede8c70f38c9c Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Thu, 29 Aug 2013 11:35:43 +0300 Subject: ARM: OMAP: DRA7: Enable clock init Initializes clock data from device tree. Signed-off-by: Tero Kristo Acked-by: Tony Lindgren Signed-off-by: Mike Turquette --- arch/arm/mach-omap2/io.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c index c95b836f81aa..44fc8cd20920 100644 --- a/arch/arm/mach-omap2/io.c +++ b/arch/arm/mach-omap2/io.c @@ -692,6 +692,7 @@ void __init dra7xx_init_early(void) dra7xx_clockdomains_init(); dra7xx_hwmod_init(); omap_hwmod_init_postsetup(); + omap_clk_soc_init = dra7xx_dt_clk_init; } void __init dra7xx_init_late(void) -- cgit v1.2.3-59-g8ed1b From d22031e2ac0777b35557bdd9f7959cc230de2625 Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Thu, 21 Nov 2013 16:49:59 +0200 Subject: ARM: AM43xx: Enable clock init Initializes clock data from device tree. Signed-off-by: Tero Kristo Acked-by: Tony Lindgren Signed-off-by: Mike Turquette --- arch/arm/mach-omap2/io.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c index 44fc8cd20920..bbd2959c63d6 100644 --- a/arch/arm/mach-omap2/io.c +++ b/arch/arm/mach-omap2/io.c @@ -606,6 +606,7 @@ void __init am43xx_init_early(void) am43xx_clockdomains_init(); am43xx_hwmod_init(); omap_hwmod_init_postsetup(); + omap_clk_soc_init = am43xx_dt_clk_init; } void __init am43xx_init_late(void) -- cgit v1.2.3-59-g8ed1b From 149c09d3a61dcb90b9cc55beafc70f06e80389f1 Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Fri, 19 Jul 2013 11:37:17 +0300 Subject: ARM: AM33xx: remove old clock data and link in new clock init code AM33xx clocks have now been moved to DT, thus remove the old data file and use the new init code under OMAP clock driver. Signed-off-by: Tero Kristo Tested-by: Nishanth Menon Acked-by: Tony Lindgren Signed-off-by: Mike Turquette --- arch/arm/mach-omap2/Makefile | 1 - arch/arm/mach-omap2/cclock33xx_data.c | 1064 --------------------------------- arch/arm/mach-omap2/io.c | 2 +- 3 files changed, 1 insertion(+), 1066 deletions(-) delete mode 100644 arch/arm/mach-omap2/cclock33xx_data.c diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index 665455a852f4..8ebe9f3dd7d4 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -190,7 +190,6 @@ obj-$(CONFIG_ARCH_OMAP3) += clkt_iclk.o obj-$(CONFIG_ARCH_OMAP4) += $(clock-common) obj-$(CONFIG_ARCH_OMAP4) += dpll3xxx.o dpll44xx.o obj-$(CONFIG_SOC_AM33XX) += $(clock-common) dpll3xxx.o -obj-$(CONFIG_SOC_AM33XX) += cclock33xx_data.o obj-$(CONFIG_SOC_OMAP5) += $(clock-common) obj-$(CONFIG_SOC_OMAP5) += dpll3xxx.o dpll44xx.o obj-$(CONFIG_SOC_DRA7XX) += $(clock-common) diff --git a/arch/arm/mach-omap2/cclock33xx_data.c b/arch/arm/mach-omap2/cclock33xx_data.c deleted file mode 100644 index 865d30ee812f..000000000000 --- a/arch/arm/mach-omap2/cclock33xx_data.c +++ /dev/null @@ -1,1064 +0,0 @@ -/* - * AM33XX Clock data - * - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ - * Vaibhav Hiremath - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation version 2. - * - * This program is distributed "as is" WITHOUT ANY WARRANTY of any - * kind, whether express or implied; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include - -#include "am33xx.h" -#include "soc.h" -#include "iomap.h" -#include "clock.h" -#include "control.h" -#include "cm.h" -#include "cm33xx.h" -#include "cm-regbits-33xx.h" -#include "prm.h" - -/* Modulemode control */ -#define AM33XX_MODULEMODE_HWCTRL_SHIFT 0 -#define AM33XX_MODULEMODE_SWCTRL_SHIFT 1 - -/*LIST_HEAD(clocks);*/ - -/* Root clocks */ - -/* RTC 32k */ -DEFINE_CLK_FIXED_RATE(clk_32768_ck, CLK_IS_ROOT, 32768, 0x0); - -/* On-Chip 32KHz RC OSC */ -DEFINE_CLK_FIXED_RATE(clk_rc32k_ck, CLK_IS_ROOT, 32000, 0x0); - -/* Crystal input clks */ -DEFINE_CLK_FIXED_RATE(virt_19200000_ck, CLK_IS_ROOT, 19200000, 0x0); - -DEFINE_CLK_FIXED_RATE(virt_24000000_ck, CLK_IS_ROOT, 24000000, 0x0); - -DEFINE_CLK_FIXED_RATE(virt_25000000_ck, CLK_IS_ROOT, 25000000, 0x0); - -DEFINE_CLK_FIXED_RATE(virt_26000000_ck, CLK_IS_ROOT, 26000000, 0x0); - -/* Oscillator clock */ -/* 19.2, 24, 25 or 26 MHz */ -static const char *sys_clkin_ck_parents[] = { - "virt_19200000_ck", "virt_24000000_ck", "virt_25000000_ck", - "virt_26000000_ck", -}; - -/* - * sys_clk in: input to the dpll and also used as funtional clock for, - * adc_tsc, smartreflex0-1, timer1-7, mcasp0-1, dcan0-1, cefuse - * - */ -DEFINE_CLK_MUX(sys_clkin_ck, sys_clkin_ck_parents, NULL, 0x0, - AM33XX_CTRL_REGADDR(AM33XX_CONTROL_STATUS), - AM33XX_CONTROL_STATUS_SYSBOOT1_SHIFT, - AM33XX_CONTROL_STATUS_SYSBOOT1_WIDTH, - 0, NULL); - -/* External clock - 12 MHz */ -DEFINE_CLK_FIXED_RATE(tclkin_ck, CLK_IS_ROOT, 12000000, 0x0); - -/* Module clocks and DPLL outputs */ - -/* DPLL_CORE */ -static struct dpll_data dpll_core_dd = { - .mult_div1_reg = AM33XX_CM_CLKSEL_DPLL_CORE, - .clk_bypass = &sys_clkin_ck, - .clk_ref = &sys_clkin_ck, - .control_reg = AM33XX_CM_CLKMODE_DPLL_CORE, - .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), - .idlest_reg = AM33XX_CM_IDLEST_DPLL_CORE, - .mult_mask = AM33XX_DPLL_MULT_MASK, - .div1_mask = AM33XX_DPLL_DIV_MASK, - .enable_mask = AM33XX_DPLL_EN_MASK, - .idlest_mask = AM33XX_ST_DPLL_CLK_MASK, - .max_multiplier = 2047, - .max_divider = 128, - .min_divider = 1, -}; - -/* CLKDCOLDO output */ -static const char *dpll_core_ck_parents[] = { - "sys_clkin_ck", -}; - -static struct clk dpll_core_ck; - -static const struct clk_ops dpll_core_ck_ops = { - .recalc_rate = &omap3_dpll_recalc, - .get_parent = &omap2_init_dpll_parent, -}; - -static struct clk_hw_omap dpll_core_ck_hw = { - .hw = { - .clk = &dpll_core_ck, - }, - .dpll_data = &dpll_core_dd, - .ops = &clkhwops_omap3_dpll, -}; - -DEFINE_STRUCT_CLK(dpll_core_ck, dpll_core_ck_parents, dpll_core_ck_ops); - -static const char *dpll_core_x2_ck_parents[] = { - "dpll_core_ck", -}; - -static struct clk dpll_core_x2_ck; - -static const struct clk_ops dpll_x2_ck_ops = { - .recalc_rate = &omap3_clkoutx2_recalc, -}; - -static struct clk_hw_omap dpll_core_x2_ck_hw = { - .hw = { - .clk = &dpll_core_x2_ck, - }, - .flags = CLOCK_CLKOUTX2, -}; - -DEFINE_STRUCT_CLK(dpll_core_x2_ck, dpll_core_x2_ck_parents, dpll_x2_ck_ops); - -DEFINE_CLK_DIVIDER(dpll_core_m4_ck, "dpll_core_x2_ck", &dpll_core_x2_ck, - 0x0, AM33XX_CM_DIV_M4_DPLL_CORE, - AM33XX_HSDIVIDER_CLKOUT1_DIV_SHIFT, - AM33XX_HSDIVIDER_CLKOUT1_DIV_WIDTH, CLK_DIVIDER_ONE_BASED, - NULL); - -DEFINE_CLK_DIVIDER(dpll_core_m5_ck, "dpll_core_x2_ck", &dpll_core_x2_ck, - 0x0, AM33XX_CM_DIV_M5_DPLL_CORE, - AM33XX_HSDIVIDER_CLKOUT2_DIV_SHIFT, - AM33XX_HSDIVIDER_CLKOUT2_DIV_WIDTH, - CLK_DIVIDER_ONE_BASED, NULL); - -DEFINE_CLK_DIVIDER(dpll_core_m6_ck, "dpll_core_x2_ck", &dpll_core_x2_ck, - 0x0, AM33XX_CM_DIV_M6_DPLL_CORE, - AM33XX_HSDIVIDER_CLKOUT3_DIV_SHIFT, - AM33XX_HSDIVIDER_CLKOUT3_DIV_WIDTH, - CLK_DIVIDER_ONE_BASED, NULL); - - -/* DPLL_MPU */ -static struct dpll_data dpll_mpu_dd = { - .mult_div1_reg = AM33XX_CM_CLKSEL_DPLL_MPU, - .clk_bypass = &sys_clkin_ck, - .clk_ref = &sys_clkin_ck, - .control_reg = AM33XX_CM_CLKMODE_DPLL_MPU, - .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), - .idlest_reg = AM33XX_CM_IDLEST_DPLL_MPU, - .mult_mask = AM33XX_DPLL_MULT_MASK, - .div1_mask = AM33XX_DPLL_DIV_MASK, - .enable_mask = AM33XX_DPLL_EN_MASK, - .idlest_mask = AM33XX_ST_DPLL_CLK_MASK, - .max_multiplier = 2047, - .max_divider = 128, - .min_divider = 1, -}; - -/* CLKOUT: fdpll/M2 */ -static struct clk dpll_mpu_ck; - -static const struct clk_ops dpll_mpu_ck_ops = { - .enable = &omap3_noncore_dpll_enable, - .disable = &omap3_noncore_dpll_disable, - .recalc_rate = &omap3_dpll_recalc, - .round_rate = &omap2_dpll_round_rate, - .set_rate = &omap3_noncore_dpll_set_rate, - .get_parent = &omap2_init_dpll_parent, -}; - -static struct clk_hw_omap dpll_mpu_ck_hw = { - .hw = { - .clk = &dpll_mpu_ck, - }, - .dpll_data = &dpll_mpu_dd, - .ops = &clkhwops_omap3_dpll, -}; - -DEFINE_STRUCT_CLK(dpll_mpu_ck, dpll_core_ck_parents, dpll_mpu_ck_ops); - -/* - * TODO: Add clksel here (sys_clkin, CORE_CLKOUTM6, PER_CLKOUTM2 - * and ALT_CLK1/2) - */ -DEFINE_CLK_DIVIDER(dpll_mpu_m2_ck, "dpll_mpu_ck", &dpll_mpu_ck, - 0x0, AM33XX_CM_DIV_M2_DPLL_MPU, AM33XX_DPLL_CLKOUT_DIV_SHIFT, - AM33XX_DPLL_CLKOUT_DIV_WIDTH, CLK_DIVIDER_ONE_BASED, NULL); - -/* DPLL_DDR */ -static struct dpll_data dpll_ddr_dd = { - .mult_div1_reg = AM33XX_CM_CLKSEL_DPLL_DDR, - .clk_bypass = &sys_clkin_ck, - .clk_ref = &sys_clkin_ck, - .control_reg = AM33XX_CM_CLKMODE_DPLL_DDR, - .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), - .idlest_reg = AM33XX_CM_IDLEST_DPLL_DDR, - .mult_mask = AM33XX_DPLL_MULT_MASK, - .div1_mask = AM33XX_DPLL_DIV_MASK, - .enable_mask = AM33XX_DPLL_EN_MASK, - .idlest_mask = AM33XX_ST_DPLL_CLK_MASK, - .max_multiplier = 2047, - .max_divider = 128, - .min_divider = 1, -}; - -/* CLKOUT: fdpll/M2 */ -static struct clk dpll_ddr_ck; - -static const struct clk_ops dpll_ddr_ck_ops = { - .recalc_rate = &omap3_dpll_recalc, - .get_parent = &omap2_init_dpll_parent, - .round_rate = &omap2_dpll_round_rate, - .set_rate = &omap3_noncore_dpll_set_rate, -}; - -static struct clk_hw_omap dpll_ddr_ck_hw = { - .hw = { - .clk = &dpll_ddr_ck, - }, - .dpll_data = &dpll_ddr_dd, - .ops = &clkhwops_omap3_dpll, -}; - -DEFINE_STRUCT_CLK(dpll_ddr_ck, dpll_core_ck_parents, dpll_ddr_ck_ops); - -/* - * TODO: Add clksel here (sys_clkin, CORE_CLKOUTM6, PER_CLKOUTM2 - * and ALT_CLK1/2) - */ -DEFINE_CLK_DIVIDER(dpll_ddr_m2_ck, "dpll_ddr_ck", &dpll_ddr_ck, - 0x0, AM33XX_CM_DIV_M2_DPLL_DDR, - AM33XX_DPLL_CLKOUT_DIV_SHIFT, AM33XX_DPLL_CLKOUT_DIV_WIDTH, - CLK_DIVIDER_ONE_BASED, NULL); - -/* emif_fck functional clock */ -DEFINE_CLK_FIXED_FACTOR(dpll_ddr_m2_div2_ck, "dpll_ddr_m2_ck", &dpll_ddr_m2_ck, - 0x0, 1, 2); - -/* DPLL_DISP */ -static struct dpll_data dpll_disp_dd = { - .mult_div1_reg = AM33XX_CM_CLKSEL_DPLL_DISP, - .clk_bypass = &sys_clkin_ck, - .clk_ref = &sys_clkin_ck, - .control_reg = AM33XX_CM_CLKMODE_DPLL_DISP, - .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), - .idlest_reg = AM33XX_CM_IDLEST_DPLL_DISP, - .mult_mask = AM33XX_DPLL_MULT_MASK, - .div1_mask = AM33XX_DPLL_DIV_MASK, - .enable_mask = AM33XX_DPLL_EN_MASK, - .idlest_mask = AM33XX_ST_DPLL_CLK_MASK, - .max_multiplier = 2047, - .max_divider = 128, - .min_divider = 1, -}; - -/* CLKOUT: fdpll/M2 */ -static struct clk dpll_disp_ck; - -static struct clk_hw_omap dpll_disp_ck_hw = { - .hw = { - .clk = &dpll_disp_ck, - }, - .dpll_data = &dpll_disp_dd, - .ops = &clkhwops_omap3_dpll, -}; - -DEFINE_STRUCT_CLK(dpll_disp_ck, dpll_core_ck_parents, dpll_ddr_ck_ops); - -/* - * TODO: Add clksel here (sys_clkin, CORE_CLKOUTM6, PER_CLKOUTM2 - * and ALT_CLK1/2) - */ -DEFINE_CLK_DIVIDER(dpll_disp_m2_ck, "dpll_disp_ck", &dpll_disp_ck, - CLK_SET_RATE_PARENT, AM33XX_CM_DIV_M2_DPLL_DISP, - AM33XX_DPLL_CLKOUT_DIV_SHIFT, AM33XX_DPLL_CLKOUT_DIV_WIDTH, - CLK_DIVIDER_ONE_BASED, NULL); - -/* DPLL_PER */ -static struct dpll_data dpll_per_dd = { - .mult_div1_reg = AM33XX_CM_CLKSEL_DPLL_PERIPH, - .clk_bypass = &sys_clkin_ck, - .clk_ref = &sys_clkin_ck, - .control_reg = AM33XX_CM_CLKMODE_DPLL_PER, - .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), - .idlest_reg = AM33XX_CM_IDLEST_DPLL_PER, - .mult_mask = AM33XX_DPLL_MULT_PERIPH_MASK, - .div1_mask = AM33XX_DPLL_PER_DIV_MASK, - .enable_mask = AM33XX_DPLL_EN_MASK, - .idlest_mask = AM33XX_ST_DPLL_CLK_MASK, - .max_multiplier = 2047, - .max_divider = 128, - .min_divider = 1, - .flags = DPLL_J_TYPE, -}; - -/* CLKDCOLDO */ -static struct clk dpll_per_ck; - -static struct clk_hw_omap dpll_per_ck_hw = { - .hw = { - .clk = &dpll_per_ck, - }, - .dpll_data = &dpll_per_dd, - .ops = &clkhwops_omap3_dpll, -}; - -DEFINE_STRUCT_CLK(dpll_per_ck, dpll_core_ck_parents, dpll_ddr_ck_ops); - -/* CLKOUT: fdpll/M2 */ -DEFINE_CLK_DIVIDER(dpll_per_m2_ck, "dpll_per_ck", &dpll_per_ck, 0x0, - AM33XX_CM_DIV_M2_DPLL_PER, AM33XX_DPLL_CLKOUT_DIV_SHIFT, - AM33XX_DPLL_CLKOUT_DIV_WIDTH, CLK_DIVIDER_ONE_BASED, - NULL); - -DEFINE_CLK_FIXED_FACTOR(dpll_per_m2_div4_wkupdm_ck, "dpll_per_m2_ck", - &dpll_per_m2_ck, 0x0, 1, 4); - -DEFINE_CLK_FIXED_FACTOR(dpll_per_m2_div4_ck, "dpll_per_m2_ck", - &dpll_per_m2_ck, 0x0, 1, 4); - -DEFINE_CLK_FIXED_FACTOR(dpll_core_m4_div2_ck, "dpll_core_m4_ck", - &dpll_core_m4_ck, 0x0, 1, 2); - -DEFINE_CLK_FIXED_FACTOR(l4_rtc_gclk, "dpll_core_m4_ck", &dpll_core_m4_ck, 0x0, - 1, 2); - -DEFINE_CLK_FIXED_FACTOR(clk_24mhz, "dpll_per_m2_ck", &dpll_per_m2_ck, 0x0, 1, - 8); - -/* - * Below clock nodes describes clockdomains derived out - * of core clock. - */ -static const struct clk_ops clk_ops_null = { -}; - -static const char *l3_gclk_parents[] = { - "dpll_core_m4_ck" -}; - -static struct clk l3_gclk; -DEFINE_STRUCT_CLK_HW_OMAP(l3_gclk, NULL); -DEFINE_STRUCT_CLK(l3_gclk, l3_gclk_parents, clk_ops_null); - -static struct clk l4hs_gclk; -DEFINE_STRUCT_CLK_HW_OMAP(l4hs_gclk, NULL); -DEFINE_STRUCT_CLK(l4hs_gclk, l3_gclk_parents, clk_ops_null); - -static const char *l3s_gclk_parents[] = { - "dpll_core_m4_div2_ck" -}; - -static struct clk l3s_gclk; -DEFINE_STRUCT_CLK_HW_OMAP(l3s_gclk, NULL); -DEFINE_STRUCT_CLK(l3s_gclk, l3s_gclk_parents, clk_ops_null); - -static struct clk l4fw_gclk; -DEFINE_STRUCT_CLK_HW_OMAP(l4fw_gclk, NULL); -DEFINE_STRUCT_CLK(l4fw_gclk, l3s_gclk_parents, clk_ops_null); - -static struct clk l4ls_gclk; -DEFINE_STRUCT_CLK_HW_OMAP(l4ls_gclk, NULL); -DEFINE_STRUCT_CLK(l4ls_gclk, l3s_gclk_parents, clk_ops_null); - -static struct clk sysclk_div_ck; -DEFINE_STRUCT_CLK_HW_OMAP(sysclk_div_ck, NULL); -DEFINE_STRUCT_CLK(sysclk_div_ck, l3_gclk_parents, clk_ops_null); - -/* - * In order to match the clock domain with hwmod clockdomain entry, - * separate clock nodes is required for the modules which are - * directly getting their funtioncal clock from sys_clkin. - */ -static struct clk adc_tsc_fck; -DEFINE_STRUCT_CLK_HW_OMAP(adc_tsc_fck, NULL); -DEFINE_STRUCT_CLK(adc_tsc_fck, dpll_core_ck_parents, clk_ops_null); - -static struct clk dcan0_fck; -DEFINE_STRUCT_CLK_HW_OMAP(dcan0_fck, NULL); -DEFINE_STRUCT_CLK(dcan0_fck, dpll_core_ck_parents, clk_ops_null); - -static struct clk dcan1_fck; -DEFINE_STRUCT_CLK_HW_OMAP(dcan1_fck, NULL); -DEFINE_STRUCT_CLK(dcan1_fck, dpll_core_ck_parents, clk_ops_null); - -static struct clk mcasp0_fck; -DEFINE_STRUCT_CLK_HW_OMAP(mcasp0_fck, NULL); -DEFINE_STRUCT_CLK(mcasp0_fck, dpll_core_ck_parents, clk_ops_null); - -static struct clk mcasp1_fck; -DEFINE_STRUCT_CLK_HW_OMAP(mcasp1_fck, NULL); -DEFINE_STRUCT_CLK(mcasp1_fck, dpll_core_ck_parents, clk_ops_null); - -static struct clk smartreflex0_fck; -DEFINE_STRUCT_CLK_HW_OMAP(smartreflex0_fck, NULL); -DEFINE_STRUCT_CLK(smartreflex0_fck, dpll_core_ck_parents, clk_ops_null); - -static struct clk smartreflex1_fck; -DEFINE_STRUCT_CLK_HW_OMAP(smartreflex1_fck, NULL); -DEFINE_STRUCT_CLK(smartreflex1_fck, dpll_core_ck_parents, clk_ops_null); - -static struct clk sha0_fck; -DEFINE_STRUCT_CLK_HW_OMAP(sha0_fck, NULL); -DEFINE_STRUCT_CLK(sha0_fck, dpll_core_ck_parents, clk_ops_null); - -static struct clk aes0_fck; -DEFINE_STRUCT_CLK_HW_OMAP(aes0_fck, NULL); -DEFINE_STRUCT_CLK(aes0_fck, dpll_core_ck_parents, clk_ops_null); - -static struct clk rng_fck; -DEFINE_STRUCT_CLK_HW_OMAP(rng_fck, NULL); -DEFINE_STRUCT_CLK(rng_fck, dpll_core_ck_parents, clk_ops_null); - -/* - * Modules clock nodes - * - * The following clock leaf nodes are added for the moment because: - * - * - hwmod data is not present for these modules, either hwmod - * control is not required or its not populated. - * - Driver code is not yet migrated to use hwmod/runtime pm - * - Modules outside kernel access (to disable them by default) - * - * - mmu (gfx domain) - * - cefuse - * - usbotg_fck (its additional clock and not really a modulemode) - * - ieee5000 - */ - -DEFINE_CLK_GATE(mmu_fck, "dpll_core_m4_ck", &dpll_core_m4_ck, 0x0, - AM33XX_CM_GFX_MMUDATA_CLKCTRL, AM33XX_MODULEMODE_SWCTRL_SHIFT, - 0x0, NULL); - -DEFINE_CLK_GATE(cefuse_fck, "sys_clkin_ck", &sys_clkin_ck, 0x0, - AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL, AM33XX_MODULEMODE_SWCTRL_SHIFT, - 0x0, NULL); - -/* - * clkdiv32 is generated from fixed division of 732.4219 - */ -DEFINE_CLK_FIXED_FACTOR(clkdiv32k_ck, "clk_24mhz", &clk_24mhz, 0x0, 1, 732); - -static struct clk clkdiv32k_ick; - -static const char *clkdiv32k_ick_parent_names[] = { - "clkdiv32k_ck", -}; - -static const struct clk_ops clkdiv32k_ick_ops = { - .enable = &omap2_dflt_clk_enable, - .disable = &omap2_dflt_clk_disable, - .is_enabled = &omap2_dflt_clk_is_enabled, - .init = &omap2_init_clk_clkdm, -}; - -static struct clk_hw_omap clkdiv32k_ick_hw = { - .hw = { - .clk = &clkdiv32k_ick, - }, - .enable_reg = AM33XX_CM_PER_CLKDIV32K_CLKCTRL, - .enable_bit = AM33XX_MODULEMODE_SWCTRL_SHIFT, - .clkdm_name = "clk_24mhz_clkdm", -}; - -DEFINE_STRUCT_CLK(clkdiv32k_ick, clkdiv32k_ick_parent_names, clkdiv32k_ick_ops); - -/* "usbotg_fck" is an additional clock and not really a modulemode */ -DEFINE_CLK_GATE(usbotg_fck, "dpll_per_ck", &dpll_per_ck, 0x0, - AM33XX_CM_CLKDCOLDO_DPLL_PER, AM33XX_ST_DPLL_CLKDCOLDO_SHIFT, - 0x0, NULL); - -DEFINE_CLK_GATE(ieee5000_fck, "dpll_core_m4_div2_ck", &dpll_core_m4_div2_ck, - 0x0, AM33XX_CM_PER_IEEE5000_CLKCTRL, - AM33XX_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); - -/* Timers */ -static const struct clksel timer1_clkmux_sel[] = { - { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, - { .parent = &clkdiv32k_ick, .rates = div_1_1_rates }, - { .parent = &tclkin_ck, .rates = div_1_2_rates }, - { .parent = &clk_rc32k_ck, .rates = div_1_3_rates }, - { .parent = &clk_32768_ck, .rates = div_1_4_rates }, - { .parent = NULL }, -}; - -static const char *timer1_ck_parents[] = { - "sys_clkin_ck", "clkdiv32k_ick", "tclkin_ck", "clk_rc32k_ck", - "clk_32768_ck", -}; - -static struct clk timer1_fck; - -static const struct clk_ops timer1_fck_ops = { - .recalc_rate = &omap2_clksel_recalc, - .get_parent = &omap2_clksel_find_parent_index, - .set_parent = &omap2_clksel_set_parent, - .init = &omap2_init_clk_clkdm, -}; - -static struct clk_hw_omap timer1_fck_hw = { - .hw = { - .clk = &timer1_fck, - }, - .clkdm_name = "l4ls_clkdm", - .clksel = timer1_clkmux_sel, - .clksel_reg = AM33XX_CLKSEL_TIMER1MS_CLK, - .clksel_mask = AM33XX_CLKSEL_0_2_MASK, -}; - -DEFINE_STRUCT_CLK(timer1_fck, timer1_ck_parents, timer1_fck_ops); - -static const struct clksel timer2_to_7_clk_sel[] = { - { .parent = &tclkin_ck, .rates = div_1_0_rates }, - { .parent = &sys_clkin_ck, .rates = div_1_1_rates }, - { .parent = &clkdiv32k_ick, .rates = div_1_2_rates }, - { .parent = NULL }, -}; - -static const char *timer2_to_7_ck_parents[] = { - "tclkin_ck", "sys_clkin_ck", "clkdiv32k_ick", -}; - -static struct clk timer2_fck; - -static struct clk_hw_omap timer2_fck_hw = { - .hw = { - .clk = &timer2_fck, - }, - .clkdm_name = "l4ls_clkdm", - .clksel = timer2_to_7_clk_sel, - .clksel_reg = AM33XX_CLKSEL_TIMER2_CLK, - .clksel_mask = AM33XX_CLKSEL_0_1_MASK, -}; - -DEFINE_STRUCT_CLK(timer2_fck, timer2_to_7_ck_parents, timer1_fck_ops); - -static struct clk timer3_fck; - -static struct clk_hw_omap timer3_fck_hw = { - .hw = { - .clk = &timer3_fck, - }, - .clkdm_name = "l4ls_clkdm", - .clksel = timer2_to_7_clk_sel, - .clksel_reg = AM33XX_CLKSEL_TIMER3_CLK, - .clksel_mask = AM33XX_CLKSEL_0_1_MASK, -}; - -DEFINE_STRUCT_CLK(timer3_fck, timer2_to_7_ck_parents, timer1_fck_ops); - -static struct clk timer4_fck; - -static struct clk_hw_omap timer4_fck_hw = { - .hw = { - .clk = &timer4_fck, - }, - .clkdm_name = "l4ls_clkdm", - .clksel = timer2_to_7_clk_sel, - .clksel_reg = AM33XX_CLKSEL_TIMER4_CLK, - .clksel_mask = AM33XX_CLKSEL_0_1_MASK, -}; - -DEFINE_STRUCT_CLK(timer4_fck, timer2_to_7_ck_parents, timer1_fck_ops); - -static struct clk timer5_fck; - -static struct clk_hw_omap timer5_fck_hw = { - .hw = { - .clk = &timer5_fck, - }, - .clkdm_name = "l4ls_clkdm", - .clksel = timer2_to_7_clk_sel, - .clksel_reg = AM33XX_CLKSEL_TIMER5_CLK, - .clksel_mask = AM33XX_CLKSEL_0_1_MASK, -}; - -DEFINE_STRUCT_CLK(timer5_fck, timer2_to_7_ck_parents, timer1_fck_ops); - -static struct clk timer6_fck; - -static struct clk_hw_omap timer6_fck_hw = { - .hw = { - .clk = &timer6_fck, - }, - .clkdm_name = "l4ls_clkdm", - .clksel = timer2_to_7_clk_sel, - .clksel_reg = AM33XX_CLKSEL_TIMER6_CLK, - .clksel_mask = AM33XX_CLKSEL_0_1_MASK, -}; - -DEFINE_STRUCT_CLK(timer6_fck, timer2_to_7_ck_parents, timer1_fck_ops); - -static struct clk timer7_fck; - -static struct clk_hw_omap timer7_fck_hw = { - .hw = { - .clk = &timer7_fck, - }, - .clkdm_name = "l4ls_clkdm", - .clksel = timer2_to_7_clk_sel, - .clksel_reg = AM33XX_CLKSEL_TIMER7_CLK, - .clksel_mask = AM33XX_CLKSEL_0_1_MASK, -}; - -DEFINE_STRUCT_CLK(timer7_fck, timer2_to_7_ck_parents, timer1_fck_ops); - -DEFINE_CLK_FIXED_FACTOR(cpsw_125mhz_gclk, - "dpll_core_m5_ck", - &dpll_core_m5_ck, - 0x0, - 1, 2); - -static const struct clk_ops cpsw_fck_ops = { - .recalc_rate = &omap2_clksel_recalc, - .get_parent = &omap2_clksel_find_parent_index, - .set_parent = &omap2_clksel_set_parent, -}; - -static const struct clksel cpsw_cpts_rft_clkmux_sel[] = { - { .parent = &dpll_core_m5_ck, .rates = div_1_0_rates }, - { .parent = &dpll_core_m4_ck, .rates = div_1_1_rates }, - { .parent = NULL }, -}; - -static const char *cpsw_cpts_rft_ck_parents[] = { - "dpll_core_m5_ck", "dpll_core_m4_ck", -}; - -static struct clk cpsw_cpts_rft_clk; - -static struct clk_hw_omap cpsw_cpts_rft_clk_hw = { - .hw = { - .clk = &cpsw_cpts_rft_clk, - }, - .clkdm_name = "cpsw_125mhz_clkdm", - .clksel = cpsw_cpts_rft_clkmux_sel, - .clksel_reg = AM33XX_CM_CPTS_RFT_CLKSEL, - .clksel_mask = AM33XX_CLKSEL_0_0_MASK, -}; - -DEFINE_STRUCT_CLK(cpsw_cpts_rft_clk, cpsw_cpts_rft_ck_parents, cpsw_fck_ops); - - -/* gpio */ -static const char *gpio0_ck_parents[] = { - "clk_rc32k_ck", "clk_32768_ck", "clkdiv32k_ick", -}; - -static const struct clksel gpio0_dbclk_mux_sel[] = { - { .parent = &clk_rc32k_ck, .rates = div_1_0_rates }, - { .parent = &clk_32768_ck, .rates = div_1_1_rates }, - { .parent = &clkdiv32k_ick, .rates = div_1_2_rates }, - { .parent = NULL }, -}; - -static const struct clk_ops gpio_fck_ops = { - .recalc_rate = &omap2_clksel_recalc, - .get_parent = &omap2_clksel_find_parent_index, - .set_parent = &omap2_clksel_set_parent, - .init = &omap2_init_clk_clkdm, -}; - -static struct clk gpio0_dbclk_mux_ck; - -static struct clk_hw_omap gpio0_dbclk_mux_ck_hw = { - .hw = { - .clk = &gpio0_dbclk_mux_ck, - }, - .clkdm_name = "l4_wkup_clkdm", - .clksel = gpio0_dbclk_mux_sel, - .clksel_reg = AM33XX_CLKSEL_GPIO0_DBCLK, - .clksel_mask = AM33XX_CLKSEL_0_1_MASK, -}; - -DEFINE_STRUCT_CLK(gpio0_dbclk_mux_ck, gpio0_ck_parents, gpio_fck_ops); - -DEFINE_CLK_GATE(gpio0_dbclk, "gpio0_dbclk_mux_ck", &gpio0_dbclk_mux_ck, 0x0, - AM33XX_CM_WKUP_GPIO0_CLKCTRL, - AM33XX_OPTFCLKEN_GPIO0_GDBCLK_SHIFT, 0x0, NULL); - -DEFINE_CLK_GATE(gpio1_dbclk, "clkdiv32k_ick", &clkdiv32k_ick, 0x0, - AM33XX_CM_PER_GPIO1_CLKCTRL, - AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_SHIFT, 0x0, NULL); - -DEFINE_CLK_GATE(gpio2_dbclk, "clkdiv32k_ick", &clkdiv32k_ick, 0x0, - AM33XX_CM_PER_GPIO2_CLKCTRL, - AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_SHIFT, 0x0, NULL); - -DEFINE_CLK_GATE(gpio3_dbclk, "clkdiv32k_ick", &clkdiv32k_ick, 0x0, - AM33XX_CM_PER_GPIO3_CLKCTRL, - AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_SHIFT, 0x0, NULL); - - -static const char *pruss_ck_parents[] = { - "l3_gclk", "dpll_disp_m2_ck", -}; - -static const struct clksel pruss_ocp_clk_mux_sel[] = { - { .parent = &l3_gclk, .rates = div_1_0_rates }, - { .parent = &dpll_disp_m2_ck, .rates = div_1_1_rates }, - { .parent = NULL }, -}; - -static struct clk pruss_ocp_gclk; - -static struct clk_hw_omap pruss_ocp_gclk_hw = { - .hw = { - .clk = &pruss_ocp_gclk, - }, - .clkdm_name = "pruss_ocp_clkdm", - .clksel = pruss_ocp_clk_mux_sel, - .clksel_reg = AM33XX_CLKSEL_PRUSS_OCP_CLK, - .clksel_mask = AM33XX_CLKSEL_0_0_MASK, -}; - -DEFINE_STRUCT_CLK(pruss_ocp_gclk, pruss_ck_parents, gpio_fck_ops); - -static const char *lcd_ck_parents[] = { - "dpll_disp_m2_ck", "dpll_core_m5_ck", "dpll_per_m2_ck", -}; - -static const struct clksel lcd_clk_mux_sel[] = { - { .parent = &dpll_disp_m2_ck, .rates = div_1_0_rates }, - { .parent = &dpll_core_m5_ck, .rates = div_1_1_rates }, - { .parent = &dpll_per_m2_ck, .rates = div_1_2_rates }, - { .parent = NULL }, -}; - -static struct clk lcd_gclk; - -static struct clk_hw_omap lcd_gclk_hw = { - .hw = { - .clk = &lcd_gclk, - }, - .clkdm_name = "lcdc_clkdm", - .clksel = lcd_clk_mux_sel, - .clksel_reg = AM33XX_CLKSEL_LCDC_PIXEL_CLK, - .clksel_mask = AM33XX_CLKSEL_0_1_MASK, -}; - -DEFINE_STRUCT_CLK_FLAGS(lcd_gclk, lcd_ck_parents, - gpio_fck_ops, CLK_SET_RATE_PARENT); - -DEFINE_CLK_FIXED_FACTOR(mmc_clk, "dpll_per_m2_ck", &dpll_per_m2_ck, 0x0, 1, 2); - -static const char *gfx_ck_parents[] = { - "dpll_core_m4_ck", "dpll_per_m2_ck", -}; - -static const struct clksel gfx_clksel_sel[] = { - { .parent = &dpll_core_m4_ck, .rates = div_1_0_rates }, - { .parent = &dpll_per_m2_ck, .rates = div_1_1_rates }, - { .parent = NULL }, -}; - -static struct clk gfx_fclk_clksel_ck; - -static struct clk_hw_omap gfx_fclk_clksel_ck_hw = { - .hw = { - .clk = &gfx_fclk_clksel_ck, - }, - .clksel = gfx_clksel_sel, - .clksel_reg = AM33XX_CLKSEL_GFX_FCLK, - .clksel_mask = AM33XX_CLKSEL_GFX_FCLK_MASK, -}; - -DEFINE_STRUCT_CLK(gfx_fclk_clksel_ck, gfx_ck_parents, gpio_fck_ops); - -static const struct clk_div_table div_1_0_2_1_rates[] = { - { .div = 1, .val = 0, }, - { .div = 2, .val = 1, }, - { .div = 0 }, -}; - -DEFINE_CLK_DIVIDER_TABLE(gfx_fck_div_ck, "gfx_fclk_clksel_ck", - &gfx_fclk_clksel_ck, 0x0, AM33XX_CLKSEL_GFX_FCLK, - AM33XX_CLKSEL_0_0_SHIFT, AM33XX_CLKSEL_0_0_WIDTH, - 0x0, div_1_0_2_1_rates, NULL); - -static const char *sysclkout_ck_parents[] = { - "clk_32768_ck", "l3_gclk", "dpll_ddr_m2_ck", "dpll_per_m2_ck", - "lcd_gclk", -}; - -static const struct clksel sysclkout_pre_sel[] = { - { .parent = &clk_32768_ck, .rates = div_1_0_rates }, - { .parent = &l3_gclk, .rates = div_1_1_rates }, - { .parent = &dpll_ddr_m2_ck, .rates = div_1_2_rates }, - { .parent = &dpll_per_m2_ck, .rates = div_1_3_rates }, - { .parent = &lcd_gclk, .rates = div_1_4_rates }, - { .parent = NULL }, -}; - -static struct clk sysclkout_pre_ck; - -static struct clk_hw_omap sysclkout_pre_ck_hw = { - .hw = { - .clk = &sysclkout_pre_ck, - }, - .clksel = sysclkout_pre_sel, - .clksel_reg = AM33XX_CM_CLKOUT_CTRL, - .clksel_mask = AM33XX_CLKOUT2SOURCE_MASK, -}; - -DEFINE_STRUCT_CLK(sysclkout_pre_ck, sysclkout_ck_parents, gpio_fck_ops); - -/* Divide by 8 clock rates with default clock is 1/1*/ -static const struct clk_div_table div8_rates[] = { - { .div = 1, .val = 0, }, - { .div = 2, .val = 1, }, - { .div = 3, .val = 2, }, - { .div = 4, .val = 3, }, - { .div = 5, .val = 4, }, - { .div = 6, .val = 5, }, - { .div = 7, .val = 6, }, - { .div = 8, .val = 7, }, - { .div = 0 }, -}; - -DEFINE_CLK_DIVIDER_TABLE(clkout2_div_ck, "sysclkout_pre_ck", &sysclkout_pre_ck, - 0x0, AM33XX_CM_CLKOUT_CTRL, AM33XX_CLKOUT2DIV_SHIFT, - AM33XX_CLKOUT2DIV_WIDTH, 0x0, div8_rates, NULL); - -DEFINE_CLK_GATE(clkout2_ck, "clkout2_div_ck", &clkout2_div_ck, 0x0, - AM33XX_CM_CLKOUT_CTRL, AM33XX_CLKOUT2EN_SHIFT, 0x0, NULL); - -static const char *wdt_ck_parents[] = { - "clk_rc32k_ck", "clkdiv32k_ick", -}; - -static const struct clksel wdt_clkmux_sel[] = { - { .parent = &clk_rc32k_ck, .rates = div_1_0_rates }, - { .parent = &clkdiv32k_ick, .rates = div_1_1_rates }, - { .parent = NULL }, -}; - -static struct clk wdt1_fck; - -static struct clk_hw_omap wdt1_fck_hw = { - .hw = { - .clk = &wdt1_fck, - }, - .clkdm_name = "l4_wkup_clkdm", - .clksel = wdt_clkmux_sel, - .clksel_reg = AM33XX_CLKSEL_WDT1_CLK, - .clksel_mask = AM33XX_CLKSEL_0_1_MASK, -}; - -DEFINE_STRUCT_CLK(wdt1_fck, wdt_ck_parents, gpio_fck_ops); - -static const char *pwmss_clk_parents[] = { - "dpll_per_m2_ck", -}; - -static const struct clk_ops ehrpwm_tbclk_ops = { - .enable = &omap2_dflt_clk_enable, - .disable = &omap2_dflt_clk_disable, -}; - -DEFINE_CLK_OMAP_MUX_GATE(ehrpwm0_tbclk, "l4ls_clkdm", - NULL, NULL, 0, - AM33XX_CTRL_REGADDR(AM33XX_PWMSS_TBCLK_CLKCTRL), - AM33XX_PWMSS0_TBCLKEN_SHIFT, - NULL, pwmss_clk_parents, ehrpwm_tbclk_ops); - -DEFINE_CLK_OMAP_MUX_GATE(ehrpwm1_tbclk, "l4ls_clkdm", - NULL, NULL, 0, - AM33XX_CTRL_REGADDR(AM33XX_PWMSS_TBCLK_CLKCTRL), - AM33XX_PWMSS1_TBCLKEN_SHIFT, - NULL, pwmss_clk_parents, ehrpwm_tbclk_ops); - -DEFINE_CLK_OMAP_MUX_GATE(ehrpwm2_tbclk, "l4ls_clkdm", - NULL, NULL, 0, - AM33XX_CTRL_REGADDR(AM33XX_PWMSS_TBCLK_CLKCTRL), - AM33XX_PWMSS2_TBCLKEN_SHIFT, - NULL, pwmss_clk_parents, ehrpwm_tbclk_ops); - -/* - * debugss optional clocks - */ -DEFINE_CLK_GATE(dbg_sysclk_ck, "sys_clkin_ck", &sys_clkin_ck, - 0x0, AM33XX_CM_WKUP_DEBUGSS_CLKCTRL, - AM33XX_OPTFCLKEN_DBGSYSCLK_SHIFT, 0x0, NULL); - -DEFINE_CLK_GATE(dbg_clka_ck, "dpll_core_m4_ck", &dpll_core_m4_ck, - 0x0, AM33XX_CM_WKUP_DEBUGSS_CLKCTRL, - AM33XX_OPTCLK_DEBUG_CLKA_SHIFT, 0x0, NULL); - -static const char *stm_pmd_clock_mux_ck_parents[] = { - "dbg_sysclk_ck", "dbg_clka_ck", -}; - -DEFINE_CLK_MUX(stm_pmd_clock_mux_ck, stm_pmd_clock_mux_ck_parents, NULL, 0x0, - AM33XX_CM_WKUP_DEBUGSS_CLKCTRL, AM33XX_STM_PMD_CLKSEL_SHIFT, - AM33XX_STM_PMD_CLKSEL_WIDTH, 0x0, NULL); - -DEFINE_CLK_MUX(trace_pmd_clk_mux_ck, stm_pmd_clock_mux_ck_parents, NULL, 0x0, - AM33XX_CM_WKUP_DEBUGSS_CLKCTRL, - AM33XX_TRC_PMD_CLKSEL_SHIFT, - AM33XX_TRC_PMD_CLKSEL_WIDTH, 0x0, NULL); - -DEFINE_CLK_DIVIDER(stm_clk_div_ck, "stm_pmd_clock_mux_ck", - &stm_pmd_clock_mux_ck, 0x0, AM33XX_CM_WKUP_DEBUGSS_CLKCTRL, - AM33XX_STM_PMD_CLKDIVSEL_SHIFT, - AM33XX_STM_PMD_CLKDIVSEL_WIDTH, CLK_DIVIDER_POWER_OF_TWO, - NULL); - -DEFINE_CLK_DIVIDER(trace_clk_div_ck, "trace_pmd_clk_mux_ck", - &trace_pmd_clk_mux_ck, 0x0, AM33XX_CM_WKUP_DEBUGSS_CLKCTRL, - AM33XX_TRC_PMD_CLKDIVSEL_SHIFT, - AM33XX_TRC_PMD_CLKDIVSEL_WIDTH, CLK_DIVIDER_POWER_OF_TWO, - NULL); - -/* - * clkdev - */ -static struct omap_clk am33xx_clks[] = { - CLK(NULL, "clk_32768_ck", &clk_32768_ck), - CLK(NULL, "clk_rc32k_ck", &clk_rc32k_ck), - CLK(NULL, "virt_19200000_ck", &virt_19200000_ck), - CLK(NULL, "virt_24000000_ck", &virt_24000000_ck), - CLK(NULL, "virt_25000000_ck", &virt_25000000_ck), - CLK(NULL, "virt_26000000_ck", &virt_26000000_ck), - CLK(NULL, "sys_clkin_ck", &sys_clkin_ck), - CLK(NULL, "tclkin_ck", &tclkin_ck), - CLK(NULL, "dpll_core_ck", &dpll_core_ck), - CLK(NULL, "dpll_core_x2_ck", &dpll_core_x2_ck), - CLK(NULL, "dpll_core_m4_ck", &dpll_core_m4_ck), - CLK(NULL, "dpll_core_m5_ck", &dpll_core_m5_ck), - CLK(NULL, "dpll_core_m6_ck", &dpll_core_m6_ck), - CLK(NULL, "dpll_mpu_ck", &dpll_mpu_ck), - CLK("cpu0", NULL, &dpll_mpu_ck), - CLK(NULL, "dpll_mpu_m2_ck", &dpll_mpu_m2_ck), - CLK(NULL, "dpll_ddr_ck", &dpll_ddr_ck), - CLK(NULL, "dpll_ddr_m2_ck", &dpll_ddr_m2_ck), - CLK(NULL, "dpll_ddr_m2_div2_ck", &dpll_ddr_m2_div2_ck), - CLK(NULL, "dpll_disp_ck", &dpll_disp_ck), - CLK(NULL, "dpll_disp_m2_ck", &dpll_disp_m2_ck), - CLK(NULL, "dpll_per_ck", &dpll_per_ck), - CLK(NULL, "dpll_per_m2_ck", &dpll_per_m2_ck), - CLK(NULL, "dpll_per_m2_div4_wkupdm_ck", &dpll_per_m2_div4_wkupdm_ck), - CLK(NULL, "dpll_per_m2_div4_ck", &dpll_per_m2_div4_ck), - CLK(NULL, "adc_tsc_fck", &adc_tsc_fck), - CLK(NULL, "cefuse_fck", &cefuse_fck), - CLK(NULL, "clkdiv32k_ck", &clkdiv32k_ck), - CLK(NULL, "clkdiv32k_ick", &clkdiv32k_ick), - CLK(NULL, "dcan0_fck", &dcan0_fck), - CLK("481cc000.d_can", NULL, &dcan0_fck), - CLK(NULL, "dcan1_fck", &dcan1_fck), - CLK("481d0000.d_can", NULL, &dcan1_fck), - CLK(NULL, "pruss_ocp_gclk", &pruss_ocp_gclk), - CLK(NULL, "mcasp0_fck", &mcasp0_fck), - CLK(NULL, "mcasp1_fck", &mcasp1_fck), - CLK(NULL, "mmu_fck", &mmu_fck), - CLK(NULL, "smartreflex0_fck", &smartreflex0_fck), - CLK(NULL, "smartreflex1_fck", &smartreflex1_fck), - CLK(NULL, "sha0_fck", &sha0_fck), - CLK(NULL, "aes0_fck", &aes0_fck), - CLK(NULL, "rng_fck", &rng_fck), - CLK(NULL, "timer1_fck", &timer1_fck), - CLK(NULL, "timer2_fck", &timer2_fck), - CLK(NULL, "timer3_fck", &timer3_fck), - CLK(NULL, "timer4_fck", &timer4_fck), - CLK(NULL, "timer5_fck", &timer5_fck), - CLK(NULL, "timer6_fck", &timer6_fck), - CLK(NULL, "timer7_fck", &timer7_fck), - CLK(NULL, "usbotg_fck", &usbotg_fck), - CLK(NULL, "ieee5000_fck", &ieee5000_fck), - CLK(NULL, "wdt1_fck", &wdt1_fck), - CLK(NULL, "l4_rtc_gclk", &l4_rtc_gclk), - CLK(NULL, "l3_gclk", &l3_gclk), - CLK(NULL, "dpll_core_m4_div2_ck", &dpll_core_m4_div2_ck), - CLK(NULL, "l4hs_gclk", &l4hs_gclk), - CLK(NULL, "l3s_gclk", &l3s_gclk), - CLK(NULL, "l4fw_gclk", &l4fw_gclk), - CLK(NULL, "l4ls_gclk", &l4ls_gclk), - CLK(NULL, "clk_24mhz", &clk_24mhz), - CLK(NULL, "sysclk_div_ck", &sysclk_div_ck), - CLK(NULL, "cpsw_125mhz_gclk", &cpsw_125mhz_gclk), - CLK(NULL, "cpsw_cpts_rft_clk", &cpsw_cpts_rft_clk), - CLK(NULL, "gpio0_dbclk_mux_ck", &gpio0_dbclk_mux_ck), - CLK(NULL, "gpio0_dbclk", &gpio0_dbclk), - CLK(NULL, "gpio1_dbclk", &gpio1_dbclk), - CLK(NULL, "gpio2_dbclk", &gpio2_dbclk), - CLK(NULL, "gpio3_dbclk", &gpio3_dbclk), - CLK(NULL, "lcd_gclk", &lcd_gclk), - CLK(NULL, "mmc_clk", &mmc_clk), - CLK(NULL, "gfx_fclk_clksel_ck", &gfx_fclk_clksel_ck), - CLK(NULL, "gfx_fck_div_ck", &gfx_fck_div_ck), - CLK(NULL, "sysclkout_pre_ck", &sysclkout_pre_ck), - CLK(NULL, "clkout2_div_ck", &clkout2_div_ck), - CLK(NULL, "timer_32k_ck", &clkdiv32k_ick), - CLK(NULL, "timer_sys_ck", &sys_clkin_ck), - CLK(NULL, "dbg_sysclk_ck", &dbg_sysclk_ck), - CLK(NULL, "dbg_clka_ck", &dbg_clka_ck), - CLK(NULL, "stm_pmd_clock_mux_ck", &stm_pmd_clock_mux_ck), - CLK(NULL, "trace_pmd_clk_mux_ck", &trace_pmd_clk_mux_ck), - CLK(NULL, "stm_clk_div_ck", &stm_clk_div_ck), - CLK(NULL, "trace_clk_div_ck", &trace_clk_div_ck), - CLK(NULL, "clkout2_ck", &clkout2_ck), - CLK("48300200.ehrpwm", "tbclk", &ehrpwm0_tbclk), - CLK("48302200.ehrpwm", "tbclk", &ehrpwm1_tbclk), - CLK("48304200.ehrpwm", "tbclk", &ehrpwm2_tbclk), -}; - - -static const char *enable_init_clks[] = { - "dpll_ddr_m2_ck", - "dpll_mpu_m2_ck", - "l3_gclk", - "l4hs_gclk", - "l4fw_gclk", - "l4ls_gclk", - "clkout2_ck", /* Required for external peripherals like, Audio codecs */ -}; - -int __init am33xx_clk_init(void) -{ - if (soc_is_am33xx()) - cpu_mask = RATE_IN_AM33XX; - - omap_clocks_register(am33xx_clks, ARRAY_SIZE(am33xx_clks)); - - omap2_clk_disable_autoidle_all(); - - omap2_clk_enable_init_clocks(enable_init_clks, - ARRAY_SIZE(enable_init_clks)); - - /* TRM ERRATA: Timer 3 & 6 default parent (TCLKIN) may not be always - * physically present, in such a case HWMOD enabling of - * clock would be failure with default parent. And timer - * probe thinks clock is already enabled, this leads to - * crash upon accessing timer 3 & 6 registers in probe. - * Fix by setting parent of both these timers to master - * oscillator clock. - */ - - clk_set_parent(&timer3_fck, &sys_clkin_ck); - clk_set_parent(&timer6_fck, &sys_clkin_ck); - /* - * The On-Chip 32K RC Osc clock is not an accurate clock-source as per - * the design/spec, so as a result, for example, timer which supposed - * to get expired @60Sec, but will expire somewhere ~@40Sec, which is - * not expected by any use-case, so change WDT1 clock source to PRCM - * 32KHz clock. - */ - clk_set_parent(&wdt1_fck, &clkdiv32k_ick); - - return 0; -} diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c index bbd2959c63d6..f28399f7ed4f 100644 --- a/arch/arm/mach-omap2/io.c +++ b/arch/arm/mach-omap2/io.c @@ -581,7 +581,7 @@ void __init am33xx_init_early(void) am33xx_clockdomains_init(); am33xx_hwmod_init(); omap_hwmod_init_postsetup(); - omap_clk_soc_init = am33xx_clk_init; + omap_clk_soc_init = am33xx_dt_clk_init; } void __init am33xx_init_late(void) -- cgit v1.2.3-59-g8ed1b From 3e049157911ad0126b6e21460251f84fb38aad63 Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Fri, 2 Aug 2013 14:32:30 +0300 Subject: ARM: OMAP3: use DT clock init if DT data is available OMAP3 platforms support both DT and non-DT boot at the moment, make the clock init work according to the used setup. Signed-off-by: Tero Kristo Tested-by: Nishanth Menon Acked-by: Tony Lindgren Signed-off-by: Mike Turquette --- arch/arm/mach-omap2/io.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c index f28399f7ed4f..b8097fe498ec 100644 --- a/arch/arm/mach-omap2/io.c +++ b/arch/arm/mach-omap2/io.c @@ -488,21 +488,29 @@ void __init omap3_init_early(void) void __init omap3430_init_early(void) { omap3_init_early(); + if (of_have_populated_dt()) + omap_clk_soc_init = omap3430_dt_clk_init; } void __init omap35xx_init_early(void) { omap3_init_early(); + if (of_have_populated_dt()) + omap_clk_soc_init = omap3430_dt_clk_init; } void __init omap3630_init_early(void) { omap3_init_early(); + if (of_have_populated_dt()) + omap_clk_soc_init = omap3630_dt_clk_init; } void __init am35xx_init_early(void) { omap3_init_early(); + if (of_have_populated_dt()) + omap_clk_soc_init = am35xx_dt_clk_init; } void __init ti81xx_init_early(void) @@ -520,7 +528,10 @@ void __init ti81xx_init_early(void) omap3xxx_clockdomains_init(); omap3xxx_hwmod_init(); omap_hwmod_init_postsetup(); - omap_clk_soc_init = omap3xxx_clk_init; + if (of_have_populated_dt()) + omap_clk_soc_init = ti81xx_dt_clk_init; + else + omap_clk_soc_init = omap3xxx_clk_init; } void __init omap3_init_late(void) -- cgit v1.2.3-59-g8ed1b From 051c8d0b667400b00dc0e53c3cf61ad6991bfefb Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Fri, 17 Jan 2014 12:09:40 -0800 Subject: clk: qcom: Fix modular build According to Documentation/kbuild/makefiles.txt these symbols should be clk-qcom-y. Otherwise the build will fail if CONFIG_COMMON_CLK_QCOM=m. Fix it. Reported-by: kbuild test robot Signed-off-by: Stephen Boyd Signed-off-by: Mike Turquette --- drivers/clk/qcom/Makefile | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index 190d38433202..f60db2ef1aee 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -1,11 +1,11 @@ obj-$(CONFIG_COMMON_CLK_QCOM) += clk-qcom.o -clk-qcom-$(CONFIG_COMMON_CLK_QCOM) += clk-regmap.o -clk-qcom-$(CONFIG_COMMON_CLK_QCOM) += clk-pll.o -clk-qcom-$(CONFIG_COMMON_CLK_QCOM) += clk-rcg.o -clk-qcom-$(CONFIG_COMMON_CLK_QCOM) += clk-rcg2.o -clk-qcom-$(CONFIG_COMMON_CLK_QCOM) += clk-branch.o -clk-qcom-$(CONFIG_COMMON_CLK_QCOM) += reset.o +clk-qcom-y += clk-regmap.o +clk-qcom-y += clk-pll.o +clk-qcom-y += clk-rcg.o +clk-qcom-y += clk-rcg2.o +clk-qcom-y += clk-branch.o +clk-qcom-y += reset.o obj-$(CONFIG_MSM_GCC_8660) += gcc-msm8660.o obj-$(CONFIG_MSM_GCC_8960) += gcc-msm8960.o -- cgit v1.2.3-59-g8ed1b From 8e31d19b93377e2e6ad67bc2e898186327cb0308 Mon Sep 17 00:00:00 2001 From: Sachin Kamat Date: Fri, 17 Jan 2014 17:05:52 +0530 Subject: clk: samsung: Remove unneeded semicolon Semicolon not needed after switch statement. Signed-off-by: Sachin Kamat Signed-off-by: Mike Turquette --- drivers/clk/samsung/clk-pll.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c index 529e11dc2c6b..81e6d2f49aa0 100644 --- a/drivers/clk/samsung/clk-pll.c +++ b/drivers/clk/samsung/clk-pll.c @@ -375,7 +375,7 @@ static int samsung_pll45xx_set_rate(struct clk_hw *hw, unsigned long drate, break; default: break; - }; + } /* Set new configuration. */ __raw_writel(con1, pll->con_reg + 0x4); -- cgit v1.2.3-59-g8ed1b From 9d43dc7f403dbe5da25c7eb488a5975b08d95496 Mon Sep 17 00:00:00 2001 From: Sebastian Hesselbarth Date: Sat, 25 Jan 2014 21:48:31 +0100 Subject: clk: si5351: remove variant from platform_data Commit 9807362bfe1748d9bb48eecb9261f1b1aaafea1c "clk: si5351: declare all device IDs for module loading" removed the common i2c_device_id and introduced new ones for each variant of the clock generator. Instead of exploiting that information in the driver, it still depends on platform_data passing the chips .variant. This removes the now redundant .variant from the platform_data and puts it in i2c_device_id's .driver_data instead. Signed-off-by: Sebastian Hesselbarth Signed-off-by: Mike Turquette --- drivers/clk/clk-si5351.c | 28 ++++++++++++---------------- drivers/clk/clk-si5351.h | 14 ++++++++++++++ include/linux/platform_data/si5351.h | 16 ---------------- 3 files changed, 26 insertions(+), 32 deletions(-) diff --git a/drivers/clk/clk-si5351.c b/drivers/clk/clk-si5351.c index c50e83744b0a..b95aa09b7aed 100644 --- a/drivers/clk/clk-si5351.c +++ b/drivers/clk/clk-si5351.c @@ -1111,11 +1111,11 @@ static const struct of_device_id si5351_dt_ids[] = { }; MODULE_DEVICE_TABLE(of, si5351_dt_ids); -static int si5351_dt_parse(struct i2c_client *client) +static int si5351_dt_parse(struct i2c_client *client, + enum si5351_variant variant) { struct device_node *child, *np = client->dev.of_node; struct si5351_platform_data *pdata; - const struct of_device_id *match; struct property *prop; const __be32 *p; int num = 0; @@ -1124,15 +1124,10 @@ static int si5351_dt_parse(struct i2c_client *client) if (np == NULL) return 0; - match = of_match_node(si5351_dt_ids, np); - if (match == NULL) - return -EINVAL; - pdata = devm_kzalloc(&client->dev, sizeof(*pdata), GFP_KERNEL); if (!pdata) return -ENOMEM; - pdata->variant = (enum si5351_variant)match->data; pdata->clk_xtal = of_clk_get(np, 0); if (!IS_ERR(pdata->clk_xtal)) clk_put(pdata->clk_xtal); @@ -1163,7 +1158,7 @@ static int si5351_dt_parse(struct i2c_client *client) pdata->pll_src[num] = SI5351_PLL_SRC_XTAL; break; case 1: - if (pdata->variant != SI5351_VARIANT_C) { + if (variant != SI5351_VARIANT_C) { dev_err(&client->dev, "invalid parent %d for pll %d\n", val, num); @@ -1187,7 +1182,7 @@ static int si5351_dt_parse(struct i2c_client *client) } if (num >= 8 || - (pdata->variant == SI5351_VARIANT_A3 && num >= 3)) { + (variant == SI5351_VARIANT_A3 && num >= 3)) { dev_err(&client->dev, "invalid clkout %d\n", num); return -EINVAL; } @@ -1226,7 +1221,7 @@ static int si5351_dt_parse(struct i2c_client *client) SI5351_CLKOUT_SRC_XTAL; break; case 3: - if (pdata->variant != SI5351_VARIANT_C) { + if (variant != SI5351_VARIANT_C) { dev_err(&client->dev, "invalid parent %d for clkout %d\n", val, num); @@ -1307,6 +1302,7 @@ static int si5351_dt_parse(struct i2c_client *client) static int si5351_i2c_probe(struct i2c_client *client, const struct i2c_device_id *id) { + enum si5351_variant variant = (enum si5351_variant)id->driver_data; struct si5351_platform_data *pdata; struct si5351_driver_data *drvdata; struct clk_init_data init; @@ -1315,7 +1311,7 @@ static int si5351_i2c_probe(struct i2c_client *client, u8 num_parents, num_clocks; int ret, n; - ret = si5351_dt_parse(client); + ret = si5351_dt_parse(client, variant); if (ret) return ret; @@ -1331,7 +1327,7 @@ static int si5351_i2c_probe(struct i2c_client *client, i2c_set_clientdata(client, drvdata); drvdata->client = client; - drvdata->variant = pdata->variant; + drvdata->variant = variant; drvdata->pxtal = pdata->clk_xtal; drvdata->pclkin = pdata->clk_clkin; @@ -1568,10 +1564,10 @@ static int si5351_i2c_probe(struct i2c_client *client, } static const struct i2c_device_id si5351_i2c_ids[] = { - { "si5351a", 0 }, - { "si5351a-msop", 0 }, - { "si5351b", 0 }, - { "si5351c", 0 }, + { "si5351a", SI5351_VARIANT_A }, + { "si5351a-msop", SI5351_VARIANT_A3 }, + { "si5351b", SI5351_VARIANT_B }, + { "si5351c", SI5351_VARIANT_C }, { } }; MODULE_DEVICE_TABLE(i2c, si5351_i2c_ids); diff --git a/drivers/clk/clk-si5351.h b/drivers/clk/clk-si5351.h index c0dbf2676872..4d0746b50c32 100644 --- a/drivers/clk/clk-si5351.h +++ b/drivers/clk/clk-si5351.h @@ -153,4 +153,18 @@ #define SI5351_XTAL_ENABLE (1<<6) #define SI5351_MULTISYNTH_ENABLE (1<<4) +/** + * enum si5351_variant - SiLabs Si5351 chip variant + * @SI5351_VARIANT_A: Si5351A (8 output clocks, XTAL input) + * @SI5351_VARIANT_A3: Si5351A MSOP10 (3 output clocks, XTAL input) + * @SI5351_VARIANT_B: Si5351B (8 output clocks, XTAL/VXCO input) + * @SI5351_VARIANT_C: Si5351C (8 output clocks, XTAL/CLKIN input) + */ +enum si5351_variant { + SI5351_VARIANT_A = 1, + SI5351_VARIANT_A3 = 2, + SI5351_VARIANT_B = 3, + SI5351_VARIANT_C = 4, +}; + #endif diff --git a/include/linux/platform_data/si5351.h b/include/linux/platform_data/si5351.h index 54334393ab92..a947ab8b441a 100644 --- a/include/linux/platform_data/si5351.h +++ b/include/linux/platform_data/si5351.h @@ -7,20 +7,6 @@ struct clk; -/** - * enum si5351_variant - SiLabs Si5351 chip variant - * @SI5351_VARIANT_A: Si5351A (8 output clocks, XTAL input) - * @SI5351_VARIANT_A3: Si5351A MSOP10 (3 output clocks, XTAL input) - * @SI5351_VARIANT_B: Si5351B (8 output clocks, XTAL/VXCO input) - * @SI5351_VARIANT_C: Si5351C (8 output clocks, XTAL/CLKIN input) - */ -enum si5351_variant { - SI5351_VARIANT_A = 1, - SI5351_VARIANT_A3 = 2, - SI5351_VARIANT_B = 3, - SI5351_VARIANT_C = 4, -}; - /** * enum si5351_pll_src - Si5351 pll clock source * @SI5351_PLL_SRC_DEFAULT: default, do not change eeprom config @@ -115,14 +101,12 @@ struct si5351_clkout_config { /** * struct si5351_platform_data - Platform data for the Si5351 clock driver - * @variant: Si5351 chip variant * @clk_xtal: xtal input clock * @clk_clkin: clkin input clock * @pll_src: array of pll source clock setting * @clkout: array of clkout configuration */ struct si5351_platform_data { - enum si5351_variant variant; struct clk *clk_xtal; struct clk *clk_clkin; enum si5351_pll_src pll_src[2]; -- cgit v1.2.3-59-g8ed1b From 88d5fe037dad80bbaf64a5c6eccd9605fcedf2e0 Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Fri, 17 Jan 2014 17:05:19 -0800 Subject: dt-bindings: qcom: Fix warning with duplicate dt define arch/arm/boot/dts/include/dt-bindings/clock/qcom,mmcc-msm8974.h:60:0: warning: "RBCPR_CLK_SRC" redefined Rename this to MMSS_RBCPR_CLK_SRC to avoid conflicts with the RBCPR clock in the gcc header. Reported-by: Bjorn Andersson Signed-off-by: Stephen Boyd Signed-off-by: Mike Turquette --- include/dt-bindings/clock/qcom,mmcc-msm8974.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/dt-bindings/clock/qcom,mmcc-msm8974.h b/include/dt-bindings/clock/qcom,mmcc-msm8974.h index 04d318d1187a..032ed87ef0f3 100644 --- a/include/dt-bindings/clock/qcom,mmcc-msm8974.h +++ b/include/dt-bindings/clock/qcom,mmcc-msm8974.h @@ -57,7 +57,7 @@ #define EXTPCLK_CLK_SRC 40 #define HDMI_CLK_SRC 41 #define VSYNC_CLK_SRC 42 -#define RBCPR_CLK_SRC 43 +#define MMSS_RBCPR_CLK_SRC 43 #define CAMSS_CCI_CCI_AHB_CLK 44 #define CAMSS_CCI_CCI_CLK 45 #define CAMSS_CSI0_AHB_CLK 46 -- cgit v1.2.3-59-g8ed1b From 0b7f04b868ec1230cf2dd698697dbc32a509ea4d Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Fri, 17 Jan 2014 19:47:17 -0800 Subject: clk: Export more clk-provider functions Allow drivers to be compiled as modules by exporting more clock provider functions. Reported-by: kbuild test robot Signed-off-by: Stephen Boyd Signed-off-by: Mike Turquette --- drivers/clk/clk.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c index 077106732550..5517944495d8 100644 --- a/drivers/clk/clk.c +++ b/drivers/clk/clk.c @@ -575,16 +575,19 @@ struct clk_hw *__clk_get_hw(struct clk *clk) { return !clk ? NULL : clk->hw; } +EXPORT_SYMBOL_GPL(__clk_get_hw); u8 __clk_get_num_parents(struct clk *clk) { return !clk ? 0 : clk->num_parents; } +EXPORT_SYMBOL_GPL(__clk_get_num_parents); struct clk *__clk_get_parent(struct clk *clk) { return !clk ? NULL : clk->parent; } +EXPORT_SYMBOL_GPL(__clk_get_parent); struct clk *clk_get_parent_by_index(struct clk *clk, u8 index) { @@ -598,6 +601,7 @@ struct clk *clk_get_parent_by_index(struct clk *clk, u8 index) else return clk->parents[index]; } +EXPORT_SYMBOL_GPL(clk_get_parent_by_index); unsigned int __clk_get_enable_count(struct clk *clk) { @@ -629,6 +633,7 @@ unsigned long __clk_get_rate(struct clk *clk) out: return ret; } +EXPORT_SYMBOL_GPL(__clk_get_rate); unsigned long __clk_get_accuracy(struct clk *clk) { @@ -685,6 +690,7 @@ bool __clk_is_enabled(struct clk *clk) out: return !!ret; } +EXPORT_SYMBOL_GPL(__clk_is_enabled); static struct clk *__clk_lookup_subtree(const char *name, struct clk *clk) { @@ -776,6 +782,7 @@ out: return best; } +EXPORT_SYMBOL_GPL(__clk_mux_determine_rate); /*** clk api ***/ -- cgit v1.2.3-59-g8ed1b From d1933689aa9ce2e07fe9e7e2ff77358f8bb11864 Mon Sep 17 00:00:00 2001 From: Emilio López Date: Fri, 24 Jan 2014 22:32:41 -0300 Subject: clk: sunxi: fix overflow when setting up divided factors MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Currently, we are allocating space for two pointers, when we actually may need to store three of them (two divisors plus the original clock). Fix this, and change sizeof(type) to sizeof(*var) to keep checkpatch.pl happy. Reported-by: Dan Carpenter Signed-off-by: Emilio López Signed-off-by: Mike Turquette --- drivers/clk/sunxi/clk-sunxi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c index 659e4ea31893..abb6c5ac8a10 100644 --- a/drivers/clk/sunxi/clk-sunxi.c +++ b/drivers/clk/sunxi/clk-sunxi.c @@ -875,7 +875,7 @@ static void __init sunxi_divs_clk_setup(struct device_node *node, if (!clk_data) return; - clks = kzalloc(SUNXI_DIVS_MAX_QTY * sizeof(struct clk *), GFP_KERNEL); + clks = kzalloc((SUNXI_DIVS_MAX_QTY+1) * sizeof(*clks), GFP_KERNEL); if (!clks) goto free_clkdata; -- cgit v1.2.3-59-g8ed1b From fd3fdaf09f26cd4f53fd4d7cdfe8e3dbb55a4dda Mon Sep 17 00:00:00 2001 From: Mike Turquette Date: Mon, 27 Jan 2014 13:04:49 -0800 Subject: clk: sort Makefile Signed-off-by: Mike Turquette --- drivers/clk/Makefile | 76 +++++++++++++++++++++++++--------------------------- 1 file changed, 37 insertions(+), 39 deletions(-) diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index 13c1e91a86bc..51a4c0dac1af 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -9,45 +9,43 @@ obj-$(CONFIG_COMMON_CLK) += clk-gate.o obj-$(CONFIG_COMMON_CLK) += clk-mux.o obj-$(CONFIG_COMMON_CLK) += clk-composite.o -# SoCs specific -obj-$(CONFIG_ARCH_BCM2835) += clk-bcm2835.o -obj-$(CONFIG_ARCH_EFM32) += clk-efm32gg.o -obj-$(CONFIG_ARCH_NOMADIK) += clk-nomadik.o -obj-$(CONFIG_ARCH_HIGHBANK) += clk-highbank.o -obj-$(CONFIG_ARCH_HI3xxx) += hisilicon/ -obj-$(CONFIG_ARCH_NSPIRE) += clk-nspire.o -obj-$(CONFIG_ARCH_MXS) += mxs/ -obj-$(CONFIG_ARCH_SOCFPGA) += socfpga/ -obj-$(CONFIG_PLAT_SPEAR) += spear/ -obj-$(CONFIG_ARCH_U300) += clk-u300.o -obj-$(CONFIG_COMMON_CLK_VERSATILE) += versatile/ -obj-$(CONFIG_COMMON_CLK_QCOM) += qcom/ -obj-$(CONFIG_PLAT_ORION) += mvebu/ +# hardware specific clock types +# please keep this section sorted lexicographically by file/directory path name +obj-$(CONFIG_COMMON_CLK_AXI_CLKGEN) += clk-axi-clkgen.o +obj-$(CONFIG_ARCH_BCM2835) += clk-bcm2835.o +obj-$(CONFIG_ARCH_EFM32) += clk-efm32gg.o +obj-$(CONFIG_ARCH_HIGHBANK) += clk-highbank.o +obj-$(CONFIG_MACH_LOONGSON1) += clk-ls1x.o +obj-$(CONFIG_COMMON_CLK_MAX77686) += clk-max77686.o +obj-$(CONFIG_ARCH_NOMADIK) += clk-nomadik.o +obj-$(CONFIG_ARCH_NSPIRE) += clk-nspire.o +obj-$(CONFIG_CLK_PPC_CORENET) += clk-ppc-corenet.o +obj-$(CONFIG_COMMON_CLK_S2MPS11) += clk-s2mps11.o +obj-$(CONFIG_COMMON_CLK_SI5351) += clk-si5351.o +obj-$(CONFIG_COMMON_CLK_SI570) += clk-si570.o +obj-$(CONFIG_CLK_TWL6040) += clk-twl6040.o +obj-$(CONFIG_ARCH_U300) += clk-u300.o +obj-$(CONFIG_ARCH_VT8500) += clk-vt8500.o +obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o +obj-$(CONFIG_COMMON_CLK_XGENE) += clk-xgene.o +obj-$(CONFIG_ARCH_HI3xxx) += hisilicon/ +obj-$(CONFIG_COMMON_CLK_KEYSTONE) += keystone/ ifeq ($(CONFIG_COMMON_CLK), y) -obj-$(CONFIG_ARCH_MMP) += mmp/ +obj-$(CONFIG_ARCH_MMP) += mmp/ endif -obj-$(CONFIG_MACH_LOONGSON1) += clk-ls1x.o -obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/ -obj-$(CONFIG_ARCH_SUNXI) += sunxi/ -obj-$(CONFIG_ARCH_U8500) += ux500/ -obj-$(CONFIG_ARCH_VT8500) += clk-vt8500.o -obj-$(CONFIG_ARCH_SIRF) += sirf/ -obj-$(CONFIG_ARCH_ZYNQ) += zynq/ -obj-$(CONFIG_ARCH_TEGRA) += tegra/ -obj-$(CONFIG_PLAT_SAMSUNG) += samsung/ -obj-$(CONFIG_COMMON_CLK_XGENE) += clk-xgene.o -obj-$(CONFIG_COMMON_CLK_KEYSTONE) += keystone/ +obj-$(CONFIG_PLAT_ORION) += mvebu/ +obj-$(CONFIG_ARCH_MXS) += mxs/ +obj-$(CONFIG_COMMON_CLK_QCOM) += qcom/ +obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/ +obj-$(CONFIG_PLAT_SAMSUNG) += samsung/ obj-$(CONFIG_ARCH_SHMOBILE_MULTI) += shmobile/ -obj-$(CONFIG_ARCH_OMAP2PLUS) += ti/ - -obj-$(CONFIG_X86) += x86/ - -# Chip specific -obj-$(CONFIG_COMMON_CLK_AXI_CLKGEN) += clk-axi-clkgen.o -obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o -obj-$(CONFIG_COMMON_CLK_MAX77686) += clk-max77686.o -obj-$(CONFIG_COMMON_CLK_SI5351) += clk-si5351.o -obj-$(CONFIG_COMMON_CLK_SI570) += clk-si570.o -obj-$(CONFIG_COMMON_CLK_S2MPS11) += clk-s2mps11.o -obj-$(CONFIG_CLK_TWL6040) += clk-twl6040.o -obj-$(CONFIG_CLK_PPC_CORENET) += clk-ppc-corenet.o +obj-$(CONFIG_ARCH_SIRF) += sirf/ +obj-$(CONFIG_ARCH_SOCFPGA) += socfpga/ +obj-$(CONFIG_PLAT_SPEAR) += spear/ +obj-$(CONFIG_ARCH_SUNXI) += sunxi/ +obj-$(CONFIG_ARCH_TEGRA) += tegra/ +obj-$(CONFIG_ARCH_OMAP2PLUS) += ti/ +obj-$(CONFIG_ARCH_U8500) += ux500/ +obj-$(CONFIG_COMMON_CLK_VERSATILE) += versatile/ +obj-$(CONFIG_X86) += x86/ +obj-$(CONFIG_ARCH_ZYNQ) += zynq/ -- cgit v1.2.3-59-g8ed1b