From 23565baecee4fb5ac6f1d43e9b0685cca9438204 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Fri, 9 Aug 2019 16:40:27 +0200 Subject: usb: ohci-nxp: enable compile-testing The driver hardcodes a hardware I/O address the way one should generally not do, and this prevents both compile-testing, and moving the platform to CONFIG_ARCH_MULTIPLATFORM. Change the code to be independent of the machine headers to allow those two. Removing the hardcoded address would be hard and is not necessary, so leave that in place for now. Link: https://lore.kernel.org/r/20190809144043.476786-2-arnd@arndb.de Signed-off-by: Arnd Bergmann Reviewed-by: Greg Kroah-Hartman Signed-off-by: Arnd Bergmann --- drivers/usb/host/Kconfig | 3 ++- drivers/usb/host/ohci-nxp.c | 25 ++++++++++++++++++------- 2 files changed, 20 insertions(+), 8 deletions(-) diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig index 40b5de597112..73d233d3bf4d 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig @@ -441,7 +441,8 @@ config USB_OHCI_HCD_S3C2410 config USB_OHCI_HCD_LPC32XX tristate "Support for LPC on-chip OHCI USB controller" - depends on USB_OHCI_HCD && ARCH_LPC32XX + depends on USB_OHCI_HCD + depends on ARCH_LPC32XX || COMPILE_TEST depends on USB_ISP1301 default y ---help--- diff --git a/drivers/usb/host/ohci-nxp.c b/drivers/usb/host/ohci-nxp.c index f5f532601092..c561881d0e79 100644 --- a/drivers/usb/host/ohci-nxp.c +++ b/drivers/usb/host/ohci-nxp.c @@ -29,10 +29,7 @@ #include "ohci.h" -#include - #define USB_CONFIG_BASE 0x31020000 -#define USB_OTG_STAT_CONTROL IO_ADDRESS(USB_CONFIG_BASE + 0x110) /* USB_OTG_STAT_CONTROL bit defines */ #define TRANSPARENT_I2C_EN (1 << 7) @@ -122,19 +119,33 @@ static inline void isp1301_vbus_off(void) static void ohci_nxp_start_hc(void) { - unsigned long tmp = __raw_readl(USB_OTG_STAT_CONTROL) | HOST_EN; + void __iomem *usb_otg_stat_control = ioremap(USB_CONFIG_BASE + 0x110, 4); + unsigned long tmp; + + if (WARN_ON(!usb_otg_stat_control)) + return; + + tmp = __raw_readl(usb_otg_stat_control) | HOST_EN; - __raw_writel(tmp, USB_OTG_STAT_CONTROL); + __raw_writel(tmp, usb_otg_stat_control); isp1301_vbus_on(); + + iounmap(usb_otg_stat_control); } static void ohci_nxp_stop_hc(void) { + void __iomem *usb_otg_stat_control = ioremap(USB_CONFIG_BASE + 0x110, 4); unsigned long tmp; + if (WARN_ON(!usb_otg_stat_control)) + return; + isp1301_vbus_off(); - tmp = __raw_readl(USB_OTG_STAT_CONTROL) & ~HOST_EN; - __raw_writel(tmp, USB_OTG_STAT_CONTROL); + tmp = __raw_readl(usb_otg_stat_control) & ~HOST_EN; + __raw_writel(tmp, usb_otg_stat_control); + + iounmap(usb_otg_stat_control); } static int ohci_hcd_nxp_probe(struct platform_device *pdev) -- cgit v1.3-14-g43fede From 50ad15282e7c75269ab754f9460dd36ae784e181 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Fri, 9 Aug 2019 16:40:28 +0200 Subject: usb: udc: lpc32xx: allow compile-testing The only thing that prevents building this driver on other platforms is the mach/hardware.h include, which is not actually used here at all, so remove the line and allow CONFIG_COMPILE_TEST. Link: https://lore.kernel.org/r/20190809144043.476786-3-arnd@arndb.de Acked-by: Greg Kroah-Hartman Acked-by: Sylvain Lemieux Signed-off-by: Arnd Bergmann --- drivers/usb/gadget/udc/Kconfig | 3 ++- drivers/usb/gadget/udc/lpc32xx_udc.c | 3 +-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/usb/gadget/udc/Kconfig b/drivers/usb/gadget/udc/Kconfig index ef0259a950ba..d354036ff6c8 100644 --- a/drivers/usb/gadget/udc/Kconfig +++ b/drivers/usb/gadget/udc/Kconfig @@ -45,7 +45,8 @@ config USB_AT91 config USB_LPC32XX tristate "LPC32XX USB Peripheral Controller" - depends on ARCH_LPC32XX && I2C + depends on ARCH_LPC32XX || COMPILE_TEST + depends on I2C select USB_ISP1301 help This option selects the USB device controller in the LPC32xx SoC. diff --git a/drivers/usb/gadget/udc/lpc32xx_udc.c b/drivers/usb/gadget/udc/lpc32xx_udc.c index 5f1b14f3e5a0..defe04d52e6d 100644 --- a/drivers/usb/gadget/udc/lpc32xx_udc.c +++ b/drivers/usb/gadget/udc/lpc32xx_udc.c @@ -24,6 +24,7 @@ #include #include #include +#include #include #include #include @@ -35,8 +36,6 @@ #include #endif -#include - /* * USB device configuration structure */ -- cgit v1.3-14-g43fede From 0a453d527ba4ce393d8d8bc0b3f21d5df3d640bf Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Fri, 9 Aug 2019 16:40:29 +0200 Subject: watchdog: pnx4008_wdt: allow compile-testing The only thing that prevents building this driver on other platforms is the mach/hardware.h include, which is not actually used here at all, so remove the line and allow CONFIG_COMPILE_TEST. Link: https://lore.kernel.org/r/20190809144043.476786-4-arnd@arndb.de Acked-by: Sylvain Lemieux Reviewed-by: Guenter Roeck Signed-off-by: Arnd Bergmann --- drivers/watchdog/Kconfig | 2 +- drivers/watchdog/pnx4008_wdt.c | 1 - 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index 8188963a405b..a45f9e3e442b 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -551,7 +551,7 @@ config OMAP_WATCHDOG config PNX4008_WATCHDOG tristate "LPC32XX Watchdog" - depends on ARCH_LPC32XX + depends on ARCH_LPC32XX || COMPILE_TEST select WATCHDOG_CORE help Say Y here if to include support for the watchdog timer diff --git a/drivers/watchdog/pnx4008_wdt.c b/drivers/watchdog/pnx4008_wdt.c index 7b446b696f2b..e0ea133c1690 100644 --- a/drivers/watchdog/pnx4008_wdt.c +++ b/drivers/watchdog/pnx4008_wdt.c @@ -30,7 +30,6 @@ #include #include #include -#include /* WatchDog Timer - Chapter 23 Page 207 */ -- cgit v1.3-14-g43fede From 5711e41b682ed4fc9b0803dc27722b1d8723a78a Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Fri, 9 Aug 2019 16:40:30 +0200 Subject: serial: lpc32xx_hs: allow compile-testing The only thing that prevents building this driver on other platforms is the mach/hardware.h include, which is not actually used here at all, so remove the line and allow CONFIG_COMPILE_TEST. Link: https://lore.kernel.org/r/20190809144043.476786-5-arnd@arndb.de Acked-by: Greg Kroah-Hartman Acked-by: Sylvain Lemieux Signed-off-by: Arnd Bergmann --- drivers/tty/serial/Kconfig | 3 ++- drivers/tty/serial/lpc32xx_hs.c | 2 -- 2 files changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig index 3083dbae35f7..518aac902e4b 100644 --- a/drivers/tty/serial/Kconfig +++ b/drivers/tty/serial/Kconfig @@ -739,7 +739,8 @@ config SERIAL_PNX8XXX_CONSOLE config SERIAL_HS_LPC32XX tristate "LPC32XX high speed serial port support" - depends on ARCH_LPC32XX && OF + depends on ARCH_LPC32XX || COMPILE_TEST + depends on OF select SERIAL_CORE help Support for the LPC32XX high speed serial ports (up to 900kbps). diff --git a/drivers/tty/serial/lpc32xx_hs.c b/drivers/tty/serial/lpc32xx_hs.c index f4e27d0ad947..7f14cd8fac47 100644 --- a/drivers/tty/serial/lpc32xx_hs.c +++ b/drivers/tty/serial/lpc32xx_hs.c @@ -25,8 +25,6 @@ #include #include #include -#include -#include /* * High Speed UART register offsets -- cgit v1.3-14-g43fede From d88ce24a0f3b30aba39e2a8966381fdfa9191106 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Fri, 9 Aug 2019 16:40:31 +0200 Subject: gpio: lpc32xx: allow building on non-lpc32xx targets The driver uses hardwire MMIO addresses instead of the data that is passed in device tree. Change it over to only hardcode the register offset values and allow compile-testing. Link: https://lore.kernel.org/r/20190809144043.476786-6-arnd@arndb.de Acked-by: Sylvain Lemieux Tested-by: Sylvain Lemieux Signed-off-by: Arnd Bergmann --- arch/arm/configs/lpc32xx_defconfig | 1 + drivers/gpio/Kconfig | 7 +++ drivers/gpio/Makefile | 2 +- drivers/gpio/gpio-lpc32xx.c | 118 +++++++++++++++++++++---------------- 4 files changed, 77 insertions(+), 51 deletions(-) diff --git a/arch/arm/configs/lpc32xx_defconfig b/arch/arm/configs/lpc32xx_defconfig index 0cdc6c7974b3..3772d5a8975a 100644 --- a/arch/arm/configs/lpc32xx_defconfig +++ b/arch/arm/configs/lpc32xx_defconfig @@ -93,6 +93,7 @@ CONFIG_SERIAL_HS_LPC32XX_CONSOLE=y # CONFIG_HW_RANDOM is not set CONFIG_I2C_CHARDEV=y CONFIG_I2C_PNX=y +CONFIG_GPIO_LPC32XX=y CONFIG_SPI=y CONFIG_SPI_PL022=y CONFIG_GPIO_SYSFS=y diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index bb13c266c329..8b40a578963c 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -311,6 +311,13 @@ config GPIO_LPC18XX Select this option to enable GPIO driver for NXP LPC18XX/43XX devices. +config GPIO_LPC32XX + tristate "NXP LPC32XX GPIO support" + depends on OF_GPIO && (ARCH_LPC32XX || COMPILE_TEST) + help + Select this option to enable GPIO driver for + NXP LPC32XX devices. + config GPIO_LYNXPOINT tristate "Intel Lynxpoint GPIO support" depends on ACPI && X86 diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index a4e91175c708..87d659ae95eb 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -74,7 +74,7 @@ obj-$(CONFIG_GPIO_LP3943) += gpio-lp3943.o obj-$(CONFIG_GPIO_LP873X) += gpio-lp873x.o obj-$(CONFIG_GPIO_LP87565) += gpio-lp87565.o obj-$(CONFIG_GPIO_LPC18XX) += gpio-lpc18xx.o -obj-$(CONFIG_ARCH_LPC32XX) += gpio-lpc32xx.o +obj-$(CONFIG_GPIO_LPC32XX) += gpio-lpc32xx.o obj-$(CONFIG_GPIO_LYNXPOINT) += gpio-lynxpoint.o obj-$(CONFIG_GPIO_MADERA) += gpio-madera.o obj-$(CONFIG_GPIO_MAX3191X) += gpio-max3191x.o diff --git a/drivers/gpio/gpio-lpc32xx.c b/drivers/gpio/gpio-lpc32xx.c index 24885b3db3d5..4e626c4235c2 100644 --- a/drivers/gpio/gpio-lpc32xx.c +++ b/drivers/gpio/gpio-lpc32xx.c @@ -16,36 +16,33 @@ #include #include -#include -#include - -#define LPC32XX_GPIO_P3_INP_STATE _GPREG(0x000) -#define LPC32XX_GPIO_P3_OUTP_SET _GPREG(0x004) -#define LPC32XX_GPIO_P3_OUTP_CLR _GPREG(0x008) -#define LPC32XX_GPIO_P3_OUTP_STATE _GPREG(0x00C) -#define LPC32XX_GPIO_P2_DIR_SET _GPREG(0x010) -#define LPC32XX_GPIO_P2_DIR_CLR _GPREG(0x014) -#define LPC32XX_GPIO_P2_DIR_STATE _GPREG(0x018) -#define LPC32XX_GPIO_P2_INP_STATE _GPREG(0x01C) -#define LPC32XX_GPIO_P2_OUTP_SET _GPREG(0x020) -#define LPC32XX_GPIO_P2_OUTP_CLR _GPREG(0x024) -#define LPC32XX_GPIO_P2_MUX_SET _GPREG(0x028) -#define LPC32XX_GPIO_P2_MUX_CLR _GPREG(0x02C) -#define LPC32XX_GPIO_P2_MUX_STATE _GPREG(0x030) -#define LPC32XX_GPIO_P0_INP_STATE _GPREG(0x040) -#define LPC32XX_GPIO_P0_OUTP_SET _GPREG(0x044) -#define LPC32XX_GPIO_P0_OUTP_CLR _GPREG(0x048) -#define LPC32XX_GPIO_P0_OUTP_STATE _GPREG(0x04C) -#define LPC32XX_GPIO_P0_DIR_SET _GPREG(0x050) -#define LPC32XX_GPIO_P0_DIR_CLR _GPREG(0x054) -#define LPC32XX_GPIO_P0_DIR_STATE _GPREG(0x058) -#define LPC32XX_GPIO_P1_INP_STATE _GPREG(0x060) -#define LPC32XX_GPIO_P1_OUTP_SET _GPREG(0x064) -#define LPC32XX_GPIO_P1_OUTP_CLR _GPREG(0x068) -#define LPC32XX_GPIO_P1_OUTP_STATE _GPREG(0x06C) -#define LPC32XX_GPIO_P1_DIR_SET _GPREG(0x070) -#define LPC32XX_GPIO_P1_DIR_CLR _GPREG(0x074) -#define LPC32XX_GPIO_P1_DIR_STATE _GPREG(0x078) +#define LPC32XX_GPIO_P3_INP_STATE (0x000) +#define LPC32XX_GPIO_P3_OUTP_SET (0x004) +#define LPC32XX_GPIO_P3_OUTP_CLR (0x008) +#define LPC32XX_GPIO_P3_OUTP_STATE (0x00C) +#define LPC32XX_GPIO_P2_DIR_SET (0x010) +#define LPC32XX_GPIO_P2_DIR_CLR (0x014) +#define LPC32XX_GPIO_P2_DIR_STATE (0x018) +#define LPC32XX_GPIO_P2_INP_STATE (0x01C) +#define LPC32XX_GPIO_P2_OUTP_SET (0x020) +#define LPC32XX_GPIO_P2_OUTP_CLR (0x024) +#define LPC32XX_GPIO_P2_MUX_SET (0x028) +#define LPC32XX_GPIO_P2_MUX_CLR (0x02C) +#define LPC32XX_GPIO_P2_MUX_STATE (0x030) +#define LPC32XX_GPIO_P0_INP_STATE (0x040) +#define LPC32XX_GPIO_P0_OUTP_SET (0x044) +#define LPC32XX_GPIO_P0_OUTP_CLR (0x048) +#define LPC32XX_GPIO_P0_OUTP_STATE (0x04C) +#define LPC32XX_GPIO_P0_DIR_SET (0x050) +#define LPC32XX_GPIO_P0_DIR_CLR (0x054) +#define LPC32XX_GPIO_P0_DIR_STATE (0x058) +#define LPC32XX_GPIO_P1_INP_STATE (0x060) +#define LPC32XX_GPIO_P1_OUTP_SET (0x064) +#define LPC32XX_GPIO_P1_OUTP_CLR (0x068) +#define LPC32XX_GPIO_P1_OUTP_STATE (0x06C) +#define LPC32XX_GPIO_P1_DIR_SET (0x070) +#define LPC32XX_GPIO_P1_DIR_CLR (0x074) +#define LPC32XX_GPIO_P1_DIR_STATE (0x078) #define GPIO012_PIN_TO_BIT(x) (1 << (x)) #define GPIO3_PIN_TO_BIT(x) (1 << ((x) + 25)) @@ -72,12 +69,12 @@ #define LPC32XX_GPO_P3_GRP (LPC32XX_GPI_P3_GRP + LPC32XX_GPI_P3_MAX) struct gpio_regs { - void __iomem *inp_state; - void __iomem *outp_state; - void __iomem *outp_set; - void __iomem *outp_clr; - void __iomem *dir_set; - void __iomem *dir_clr; + unsigned long inp_state; + unsigned long outp_state; + unsigned long outp_set; + unsigned long outp_clr; + unsigned long dir_set; + unsigned long dir_clr; }; /* @@ -165,16 +162,27 @@ static struct gpio_regs gpio_grp_regs_p3 = { struct lpc32xx_gpio_chip { struct gpio_chip chip; struct gpio_regs *gpio_grp; + void __iomem *reg_base; }; +static inline u32 gpreg_read(struct lpc32xx_gpio_chip *group, unsigned long offset) +{ + return __raw_readl(group->reg_base + offset); +} + +static inline void gpreg_write(struct lpc32xx_gpio_chip *group, u32 val, unsigned long offset) +{ + __raw_writel(val, group->reg_base + offset); +} + static void __set_gpio_dir_p012(struct lpc32xx_gpio_chip *group, unsigned pin, int input) { if (input) - __raw_writel(GPIO012_PIN_TO_BIT(pin), + gpreg_write(group, GPIO012_PIN_TO_BIT(pin), group->gpio_grp->dir_clr); else - __raw_writel(GPIO012_PIN_TO_BIT(pin), + gpreg_write(group, GPIO012_PIN_TO_BIT(pin), group->gpio_grp->dir_set); } @@ -184,19 +192,19 @@ static void __set_gpio_dir_p3(struct lpc32xx_gpio_chip *group, u32 u = GPIO3_PIN_TO_BIT(pin); if (input) - __raw_writel(u, group->gpio_grp->dir_clr); + gpreg_write(group, u, group->gpio_grp->dir_clr); else - __raw_writel(u, group->gpio_grp->dir_set); + gpreg_write(group, u, group->gpio_grp->dir_set); } static void __set_gpio_level_p012(struct lpc32xx_gpio_chip *group, unsigned pin, int high) { if (high) - __raw_writel(GPIO012_PIN_TO_BIT(pin), + gpreg_write(group, GPIO012_PIN_TO_BIT(pin), group->gpio_grp->outp_set); else - __raw_writel(GPIO012_PIN_TO_BIT(pin), + gpreg_write(group, GPIO012_PIN_TO_BIT(pin), group->gpio_grp->outp_clr); } @@ -206,31 +214,31 @@ static void __set_gpio_level_p3(struct lpc32xx_gpio_chip *group, u32 u = GPIO3_PIN_TO_BIT(pin); if (high) - __raw_writel(u, group->gpio_grp->outp_set); + gpreg_write(group, u, group->gpio_grp->outp_set); else - __raw_writel(u, group->gpio_grp->outp_clr); + gpreg_write(group, u, group->gpio_grp->outp_clr); } static void __set_gpo_level_p3(struct lpc32xx_gpio_chip *group, unsigned pin, int high) { if (high) - __raw_writel(GPO3_PIN_TO_BIT(pin), group->gpio_grp->outp_set); + gpreg_write(group, GPO3_PIN_TO_BIT(pin), group->gpio_grp->outp_set); else - __raw_writel(GPO3_PIN_TO_BIT(pin), group->gpio_grp->outp_clr); + gpreg_write(group, GPO3_PIN_TO_BIT(pin), group->gpio_grp->outp_clr); } static int __get_gpio_state_p012(struct lpc32xx_gpio_chip *group, unsigned pin) { - return GPIO012_PIN_IN_SEL(__raw_readl(group->gpio_grp->inp_state), + return GPIO012_PIN_IN_SEL(gpreg_read(group, group->gpio_grp->inp_state), pin); } static int __get_gpio_state_p3(struct lpc32xx_gpio_chip *group, unsigned pin) { - int state = __raw_readl(group->gpio_grp->inp_state); + int state = gpreg_read(group, group->gpio_grp->inp_state); /* * P3 GPIO pin input mapping is not contiguous, GPIOP3-0..4 is mapped @@ -242,13 +250,13 @@ static int __get_gpio_state_p3(struct lpc32xx_gpio_chip *group, static int __get_gpi_state_p3(struct lpc32xx_gpio_chip *group, unsigned pin) { - return GPI3_PIN_IN_SEL(__raw_readl(group->gpio_grp->inp_state), pin); + return GPI3_PIN_IN_SEL(gpreg_read(group, group->gpio_grp->inp_state), pin); } static int __get_gpo_state_p3(struct lpc32xx_gpio_chip *group, unsigned pin) { - return GPO3_PIN_IN_SEL(__raw_readl(group->gpio_grp->outp_state), pin); + return GPO3_PIN_IN_SEL(gpreg_read(group, group->gpio_grp->outp_state), pin); } /* @@ -497,12 +505,18 @@ static int lpc32xx_of_xlate(struct gpio_chip *gc, static int lpc32xx_gpio_probe(struct platform_device *pdev) { int i; + void __iomem *reg_base; + + reg_base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(reg_base)) + return PTR_ERR(reg_base); for (i = 0; i < ARRAY_SIZE(lpc32xx_gpiochip); i++) { if (pdev->dev.of_node) { lpc32xx_gpiochip[i].chip.of_xlate = lpc32xx_of_xlate; lpc32xx_gpiochip[i].chip.of_gpio_n_cells = 3; lpc32xx_gpiochip[i].chip.of_node = pdev->dev.of_node; + lpc32xx_gpiochip[i].reg_base = reg_base; } devm_gpiochip_add_data(&pdev->dev, &lpc32xx_gpiochip[i].chip, &lpc32xx_gpiochip[i]); @@ -527,3 +541,7 @@ static struct platform_driver lpc32xx_gpio_driver = { }; module_platform_driver(lpc32xx_gpio_driver); + +MODULE_AUTHOR("Kevin Wells "); +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("GPIO driver for LPC32xx SoC"); -- cgit v1.3-14-g43fede From 9dc03ffd996d4103cc2a11286d61e517bce27440 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Fri, 9 Aug 2019 16:40:32 +0200 Subject: net: lpc-enet: factor out iram access The lpc_eth driver uses a platform specific method to find the internal sram. This prevents building it on other machines. Rework to only use one function call and keep the other platform internals where they belong. Ideally this would look up the sram location from DT, but as this is a rarely used driver, I want to keep the modifications to a minimum. Link: https://lore.kernel.org/r/20190809144043.476786-7-arnd@arndb.de Signed-off-by: Arnd Bergmann --- arch/arm/mach-lpc32xx/common.c | 9 +++++++-- arch/arm/mach-lpc32xx/common.h | 1 - arch/arm/mach-lpc32xx/include/mach/board.h | 15 --------------- drivers/net/ethernet/nxp/lpc_eth.c | 17 ++++++++--------- include/linux/soc/nxp/lpc32xx-misc.h | 24 ++++++++++++++++++++++++ 5 files changed, 39 insertions(+), 27 deletions(-) delete mode 100644 arch/arm/mach-lpc32xx/include/mach/board.h create mode 100644 include/linux/soc/nxp/lpc32xx-misc.h diff --git a/arch/arm/mach-lpc32xx/common.c b/arch/arm/mach-lpc32xx/common.c index 5b71b4fab2cd..f648324d5fb4 100644 --- a/arch/arm/mach-lpc32xx/common.c +++ b/arch/arm/mach-lpc32xx/common.c @@ -8,6 +8,7 @@ */ #include +#include #include #include @@ -32,7 +33,7 @@ void lpc32xx_get_uid(u32 devid[4]) */ #define LPC32XX_IRAM_BANK_SIZE SZ_128K static u32 iram_size; -u32 lpc32xx_return_iram_size(void) +u32 lpc32xx_return_iram(void __iomem **mapbase, dma_addr_t *dmaaddr) { if (iram_size == 0) { u32 savedval1, savedval2; @@ -53,10 +54,14 @@ u32 lpc32xx_return_iram_size(void) } else iram_size = LPC32XX_IRAM_BANK_SIZE * 2; } + if (dmaaddr) + *dmaaddr = LPC32XX_IRAM_BASE; + if (mapbase) + *mapbase = io_p2v(LPC32XX_IRAM_BASE); return iram_size; } -EXPORT_SYMBOL_GPL(lpc32xx_return_iram_size); +EXPORT_SYMBOL_GPL(lpc32xx_return_iram); static struct map_desc lpc32xx_io_desc[] __initdata = { { diff --git a/arch/arm/mach-lpc32xx/common.h b/arch/arm/mach-lpc32xx/common.h index 8e597ce48a73..32f0ad217807 100644 --- a/arch/arm/mach-lpc32xx/common.h +++ b/arch/arm/mach-lpc32xx/common.h @@ -23,7 +23,6 @@ extern void __init lpc32xx_serial_init(void); */ extern void lpc32xx_get_uid(u32 devid[4]); -extern u32 lpc32xx_return_iram_size(void); /* * Pointers used for sizing and copying suspend function data */ diff --git a/arch/arm/mach-lpc32xx/include/mach/board.h b/arch/arm/mach-lpc32xx/include/mach/board.h deleted file mode 100644 index 476513d970a4..000000000000 --- a/arch/arm/mach-lpc32xx/include/mach/board.h +++ /dev/null @@ -1,15 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * arm/arch/mach-lpc32xx/include/mach/board.h - * - * Author: Kevin Wells - * - * Copyright (C) 2010 NXP Semiconductors - */ - -#ifndef __ASM_ARCH_BOARD_H -#define __ASM_ARCH_BOARD_H - -extern u32 lpc32xx_return_iram_size(void); - -#endif /* __ASM_ARCH_BOARD_H */ diff --git a/drivers/net/ethernet/nxp/lpc_eth.c b/drivers/net/ethernet/nxp/lpc_eth.c index f7e11f1b0426..bcdd0adcfb0c 100644 --- a/drivers/net/ethernet/nxp/lpc_eth.c +++ b/drivers/net/ethernet/nxp/lpc_eth.c @@ -18,8 +18,8 @@ #include #include #include +#include -#include #include #include @@ -1311,16 +1311,15 @@ static int lpc_eth_drv_probe(struct platform_device *pdev) /* Get size of DMA buffers/descriptors region */ pldat->dma_buff_size = (ENET_TX_DESC + ENET_RX_DESC) * (ENET_MAXF_SIZE + sizeof(struct txrx_desc_t) + sizeof(struct rx_status_t)); - pldat->dma_buff_base_v = 0; if (use_iram_for_net(dev)) { - dma_handle = LPC32XX_IRAM_BASE; - if (pldat->dma_buff_size <= lpc32xx_return_iram_size()) - pldat->dma_buff_base_v = - io_p2v(LPC32XX_IRAM_BASE); - else + if (pldat->dma_buff_size > + lpc32xx_return_iram(&pldat->dma_buff_base_v, &dma_handle)) { + pldat->dma_buff_base_v = NULL; + pldat->dma_buff_size = 0; netdev_err(ndev, "IRAM not big enough for net buffers, using SDRAM instead.\n"); + } } if (pldat->dma_buff_base_v == 0) { @@ -1409,7 +1408,7 @@ err_out_unregister_netdev: unregister_netdev(ndev); err_out_dma_unmap: if (!use_iram_for_net(dev) || - pldat->dma_buff_size > lpc32xx_return_iram_size()) + pldat->dma_buff_size > lpc32xx_return_iram(NULL, NULL)) dma_free_coherent(dev, pldat->dma_buff_size, pldat->dma_buff_base_v, pldat->dma_buff_base_p); @@ -1436,7 +1435,7 @@ static int lpc_eth_drv_remove(struct platform_device *pdev) unregister_netdev(ndev); if (!use_iram_for_net(&pldat->pdev->dev) || - pldat->dma_buff_size > lpc32xx_return_iram_size()) + pldat->dma_buff_size > lpc32xx_return_iram(NULL, NULL)) dma_free_coherent(&pldat->pdev->dev, pldat->dma_buff_size, pldat->dma_buff_base_v, pldat->dma_buff_base_p); diff --git a/include/linux/soc/nxp/lpc32xx-misc.h b/include/linux/soc/nxp/lpc32xx-misc.h new file mode 100644 index 000000000000..f232e1a1bcdc --- /dev/null +++ b/include/linux/soc/nxp/lpc32xx-misc.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Author: Kevin Wells + * + * Copyright (C) 2010 NXP Semiconductors + */ + +#ifndef __SOC_LPC32XX_MISC_H +#define __SOC_LPC32XX_MISC_H + +#include + +#ifdef CONFIG_ARCH_LPC32XX +extern u32 lpc32xx_return_iram(void __iomem **mapbase, dma_addr_t *dmaaddr); +#else +static inline u32 lpc32xx_return_iram(void __iomem **mapbase, dma_addr_t *dmaaddr) +{ + *mapbase = NULL; + *dmaaddr = 0; + return 0; +} +#endif + +#endif /* __SOC_LPC32XX_MISC_H */ -- cgit v1.3-14-g43fede From ecca1a6277aac10e40e4baba28adb893899b24b3 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Fri, 9 Aug 2019 16:40:33 +0200 Subject: net: lpc-enet: move phy setup into platform code Setting the phy mode requires touching a platform specific register, which prevents us from building the driver without its header files. Move it into a separate function in arch/arm/mach/lpc32xx to hide the core registers from the network driver. Link: https://lore.kernel.org/r/20190809144043.476786-8-arnd@arndb.de Acked-by: Sylvain Lemieux Signed-off-by: Arnd Bergmann --- arch/arm/mach-lpc32xx/common.c | 12 ++++++++++++ drivers/net/ethernet/nxp/lpc_eth.c | 12 +----------- include/linux/soc/nxp/lpc32xx-misc.h | 5 +++++ 3 files changed, 18 insertions(+), 11 deletions(-) diff --git a/arch/arm/mach-lpc32xx/common.c b/arch/arm/mach-lpc32xx/common.c index f648324d5fb4..a475339333c1 100644 --- a/arch/arm/mach-lpc32xx/common.c +++ b/arch/arm/mach-lpc32xx/common.c @@ -63,6 +63,18 @@ u32 lpc32xx_return_iram(void __iomem **mapbase, dma_addr_t *dmaaddr) } EXPORT_SYMBOL_GPL(lpc32xx_return_iram); +void lpc32xx_set_phy_interface_mode(phy_interface_t mode) +{ + u32 tmp = __raw_readl(LPC32XX_CLKPWR_MACCLK_CTRL); + tmp &= ~LPC32XX_CLKPWR_MACCTRL_PINS_MSK; + if (mode == PHY_INTERFACE_MODE_MII) + tmp |= LPC32XX_CLKPWR_MACCTRL_USE_MII_PINS; + else + tmp |= LPC32XX_CLKPWR_MACCTRL_USE_RMII_PINS; + __raw_writel(tmp, LPC32XX_CLKPWR_MACCLK_CTRL); +} +EXPORT_SYMBOL_GPL(lpc32xx_set_phy_interface_mode); + static struct map_desc lpc32xx_io_desc[] __initdata = { { .virtual = (unsigned long)IO_ADDRESS(LPC32XX_AHB0_START), diff --git a/drivers/net/ethernet/nxp/lpc_eth.c b/drivers/net/ethernet/nxp/lpc_eth.c index bcdd0adcfb0c..0893b77c385d 100644 --- a/drivers/net/ethernet/nxp/lpc_eth.c +++ b/drivers/net/ethernet/nxp/lpc_eth.c @@ -20,9 +20,6 @@ #include #include -#include -#include - #define MODNAME "lpc-eth" #define DRV_VERSION "1.00" @@ -1237,16 +1234,9 @@ static int lpc_eth_drv_probe(struct platform_device *pdev) dma_addr_t dma_handle; struct resource *res; int irq, ret; - u32 tmp; /* Setup network interface for RMII or MII mode */ - tmp = __raw_readl(LPC32XX_CLKPWR_MACCLK_CTRL); - tmp &= ~LPC32XX_CLKPWR_MACCTRL_PINS_MSK; - if (lpc_phy_interface_mode(dev) == PHY_INTERFACE_MODE_MII) - tmp |= LPC32XX_CLKPWR_MACCTRL_USE_MII_PINS; - else - tmp |= LPC32XX_CLKPWR_MACCTRL_USE_RMII_PINS; - __raw_writel(tmp, LPC32XX_CLKPWR_MACCLK_CTRL); + lpc32xx_set_phy_interface_mode(lpc_phy_interface_mode(dev)); /* Get platform resources */ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); diff --git a/include/linux/soc/nxp/lpc32xx-misc.h b/include/linux/soc/nxp/lpc32xx-misc.h index f232e1a1bcdc..af4f82f6cf3b 100644 --- a/include/linux/soc/nxp/lpc32xx-misc.h +++ b/include/linux/soc/nxp/lpc32xx-misc.h @@ -9,9 +9,11 @@ #define __SOC_LPC32XX_MISC_H #include +#include #ifdef CONFIG_ARCH_LPC32XX extern u32 lpc32xx_return_iram(void __iomem **mapbase, dma_addr_t *dmaaddr); +extern void lpc32xx_set_phy_interface_mode(phy_interface_t mode); #else static inline u32 lpc32xx_return_iram(void __iomem **mapbase, dma_addr_t *dmaaddr) { @@ -19,6 +21,9 @@ static inline u32 lpc32xx_return_iram(void __iomem **mapbase, dma_addr_t *dmaadd *dmaaddr = 0; return 0; } +static inline void lpc32xx_set_phy_interface_mode(phy_interface_t mode) +{ +} #endif #endif /* __SOC_LPC32XX_MISC_H */ -- cgit v1.3-14-g43fede From 772775c1dfe00c99a9fe449ed35f74f1067f0128 Mon Sep 17 00:00:00 2001 From: kbuild test robot Date: Fri, 9 Aug 2019 16:40:34 +0200 Subject: net: lpc-enet: fix badzero.cocci warnings drivers/net/ethernet/nxp/lpc_eth.c:1316:31-32: WARNING comparing pointer to 0 Compare pointer-typed values to NULL rather than 0 Semantic patch information: This makes an effort to choose between !x and x == NULL. !x is used if it has previously been used with the function used to initialize x. This relies on type information. More type information can be obtained using the option -all_includes and the option -I to specify an include path. Generated by: scripts/coccinelle/null/badzero.cocci Link: https://lore.kernel.org/r/20190809144043.476786-9-arnd@arndb.de Fixes: e42016eb3844 ("net: lpc-enet: allow compile testing") Signed-off-by: kbuild test robot Signed-off-by: Arnd Bergmann --- drivers/net/ethernet/nxp/lpc_eth.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/ethernet/nxp/lpc_eth.c b/drivers/net/ethernet/nxp/lpc_eth.c index 0893b77c385d..797bdbbcef76 100644 --- a/drivers/net/ethernet/nxp/lpc_eth.c +++ b/drivers/net/ethernet/nxp/lpc_eth.c @@ -1312,7 +1312,7 @@ static int lpc_eth_drv_probe(struct platform_device *pdev) } } - if (pldat->dma_buff_base_v == 0) { + if (pldat->dma_buff_base_v == NULL) { ret = dma_coerce_mask_and_coherent(dev, DMA_BIT_MASK(32)); if (ret) goto err_out_free_irq; -- cgit v1.3-14-g43fede From de6f97b2bace0e2eb6c3a86e124d1e652a587b56 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Fri, 9 Aug 2019 16:40:35 +0200 Subject: net: lpc-enet: fix printk format strings compile-testing this driver on other architectures showed multiple warnings: drivers/net/ethernet/nxp/lpc_eth.c: In function 'lpc_eth_drv_probe': drivers/net/ethernet/nxp/lpc_eth.c:1337:19: warning: format '%d' expects argument of type 'int', but argument 4 has type 'resource_size_t {aka long long unsigned int}' [-Wformat=] drivers/net/ethernet/nxp/lpc_eth.c:1342:19: warning: format '%x' expects argument of type 'unsigned int', but argument 4 has type 'dma_addr_t {aka long long unsigned int}' [-Wformat=] Use format strings that work on all architectures. Link: https://lore.kernel.org/r/20190809144043.476786-10-arnd@arndb.de Reported-by: kbuild test robot Signed-off-by: Arnd Bergmann --- drivers/net/ethernet/nxp/lpc_eth.c | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/drivers/net/ethernet/nxp/lpc_eth.c b/drivers/net/ethernet/nxp/lpc_eth.c index 797bdbbcef76..96d509c418bf 100644 --- a/drivers/net/ethernet/nxp/lpc_eth.c +++ b/drivers/net/ethernet/nxp/lpc_eth.c @@ -1333,13 +1333,14 @@ static int lpc_eth_drv_probe(struct platform_device *pdev) pldat->dma_buff_base_p = dma_handle; netdev_dbg(ndev, "IO address space :%pR\n", res); - netdev_dbg(ndev, "IO address size :%d\n", resource_size(res)); + netdev_dbg(ndev, "IO address size :%zd\n", + (size_t)resource_size(res)); netdev_dbg(ndev, "IO address (mapped) :0x%p\n", pldat->net_base); netdev_dbg(ndev, "IRQ number :%d\n", ndev->irq); - netdev_dbg(ndev, "DMA buffer size :%d\n", pldat->dma_buff_size); - netdev_dbg(ndev, "DMA buffer P address :0x%08x\n", - pldat->dma_buff_base_p); + netdev_dbg(ndev, "DMA buffer size :%zd\n", pldat->dma_buff_size); + netdev_dbg(ndev, "DMA buffer P address :%pad\n", + &pldat->dma_buff_base_p); netdev_dbg(ndev, "DMA buffer V address :0x%p\n", pldat->dma_buff_base_v); @@ -1386,8 +1387,8 @@ static int lpc_eth_drv_probe(struct platform_device *pdev) if (ret) goto err_out_unregister_netdev; - netdev_info(ndev, "LPC mac at 0x%08x irq %d\n", - res->start, ndev->irq); + netdev_info(ndev, "LPC mac at 0x%08lx irq %d\n", + (unsigned long)res->start, ndev->irq); device_init_wakeup(dev, 1); device_set_wakeup_enable(dev, 0); -- cgit v1.3-14-g43fede From 35974a7cc23c5deb5597c0a42183172498c4a0a8 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Fri, 9 Aug 2019 16:40:36 +0200 Subject: net: lpc-enet: allow compile testing The lpc-enet driver can now be built on all platforms, so allow compile testing as well. Add one missing header inclusion that is required in some configurations. Link: https://lore.kernel.org/r/20190809144043.476786-11-arnd@arndb.de Signed-off-by: Arnd Bergmann --- drivers/net/ethernet/nxp/Kconfig | 2 +- drivers/net/ethernet/nxp/lpc_eth.c | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/nxp/Kconfig b/drivers/net/ethernet/nxp/Kconfig index 261f107e2be0..418afb84c84b 100644 --- a/drivers/net/ethernet/nxp/Kconfig +++ b/drivers/net/ethernet/nxp/Kconfig @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-only config LPC_ENET tristate "NXP ethernet MAC on LPC devices" - depends on ARCH_LPC32XX + depends on ARCH_LPC32XX || COMPILE_TEST select PHYLIB help Say Y or M here if you want to use the NXP ethernet MAC included on diff --git a/drivers/net/ethernet/nxp/lpc_eth.c b/drivers/net/ethernet/nxp/lpc_eth.c index 96d509c418bf..141571e2ec11 100644 --- a/drivers/net/ethernet/nxp/lpc_eth.c +++ b/drivers/net/ethernet/nxp/lpc_eth.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include -- cgit v1.3-14-g43fede From ffba29c9ebd0977dbf77bf6064776716a51b8ae5 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Fri, 9 Aug 2019 16:40:37 +0200 Subject: serial: lpc32xx: allow compile testing The lpc32xx_loopback_set() function in hte lpc32xx_hs driver is the one thing that relies on platform header files. Move that into the core platform code so we only need a variable declaration for it, and enable COMPILE_TEST building. Link: https://lore.kernel.org/r/20190809144043.476786-12-arnd@arndb.de Signed-off-by: Arnd Bergmann Acked-by: Greg Kroah-Hartman Signed-off-by: Arnd Bergmann --- arch/arm/mach-lpc32xx/serial.c | 30 ++++++++++++++++++++++++++++++ drivers/tty/serial/lpc32xx_hs.c | 35 ++++------------------------------- include/linux/soc/nxp/lpc32xx-misc.h | 4 ++++ 3 files changed, 38 insertions(+), 31 deletions(-) diff --git a/arch/arm/mach-lpc32xx/serial.c b/arch/arm/mach-lpc32xx/serial.c index 3f9b30df9f0e..cfb35e5691cd 100644 --- a/arch/arm/mach-lpc32xx/serial.c +++ b/arch/arm/mach-lpc32xx/serial.c @@ -60,6 +60,36 @@ static struct uartinit uartinit_data[] __initdata = { }, }; +/* LPC3250 Errata HSUART.1: Hang workaround via loopback mode on inactivity */ +void lpc32xx_loopback_set(resource_size_t mapbase, int state) +{ + int bit; + u32 tmp; + + switch (mapbase) { + case LPC32XX_HS_UART1_BASE: + bit = 0; + break; + case LPC32XX_HS_UART2_BASE: + bit = 1; + break; + case LPC32XX_HS_UART7_BASE: + bit = 6; + break; + default: + WARN(1, "lpc32xx_hs: Warning: Unknown port at %08x\n", mapbase); + return; + } + + tmp = readl(LPC32XX_UARTCTL_CLOOP); + if (state) + tmp |= (1 << bit); + else + tmp &= ~(1 << bit); + writel(tmp, LPC32XX_UARTCTL_CLOOP); +} +EXPORT_SYMBOL_GPL(lpc32xx_loopback_set); + void __init lpc32xx_serial_init(void) { u32 tmp, clkmodes = 0; diff --git a/drivers/tty/serial/lpc32xx_hs.c b/drivers/tty/serial/lpc32xx_hs.c index 7f14cd8fac47..d3843f722182 100644 --- a/drivers/tty/serial/lpc32xx_hs.c +++ b/drivers/tty/serial/lpc32xx_hs.c @@ -25,6 +25,8 @@ #include #include #include +#include +#include /* * High Speed UART register offsets @@ -79,6 +81,8 @@ #define LPC32XX_HSU_TX_TL8B (0x2 << 0) #define LPC32XX_HSU_TX_TL16B (0x3 << 0) +#define LPC32XX_MAIN_OSC_FREQ 13000000 + #define MODNAME "lpc32xx_hsuart" struct lpc32xx_hsuart_port { @@ -149,8 +153,6 @@ static void lpc32xx_hsuart_console_write(struct console *co, const char *s, local_irq_restore(flags); } -static void lpc32xx_loopback_set(resource_size_t mapbase, int state); - static int __init lpc32xx_hsuart_console_setup(struct console *co, char *options) { @@ -437,35 +439,6 @@ static void serial_lpc32xx_break_ctl(struct uart_port *port, spin_unlock_irqrestore(&port->lock, flags); } -/* LPC3250 Errata HSUART.1: Hang workaround via loopback mode on inactivity */ -static void lpc32xx_loopback_set(resource_size_t mapbase, int state) -{ - int bit; - u32 tmp; - - switch (mapbase) { - case LPC32XX_HS_UART1_BASE: - bit = 0; - break; - case LPC32XX_HS_UART2_BASE: - bit = 1; - break; - case LPC32XX_HS_UART7_BASE: - bit = 6; - break; - default: - WARN(1, "lpc32xx_hs: Warning: Unknown port at %08x\n", mapbase); - return; - } - - tmp = readl(LPC32XX_UARTCTL_CLOOP); - if (state) - tmp |= (1 << bit); - else - tmp &= ~(1 << bit); - writel(tmp, LPC32XX_UARTCTL_CLOOP); -} - /* port->lock is not held. */ static int serial_lpc32xx_startup(struct uart_port *port) { diff --git a/include/linux/soc/nxp/lpc32xx-misc.h b/include/linux/soc/nxp/lpc32xx-misc.h index af4f82f6cf3b..699c6f1e3aab 100644 --- a/include/linux/soc/nxp/lpc32xx-misc.h +++ b/include/linux/soc/nxp/lpc32xx-misc.h @@ -14,6 +14,7 @@ #ifdef CONFIG_ARCH_LPC32XX extern u32 lpc32xx_return_iram(void __iomem **mapbase, dma_addr_t *dmaaddr); extern void lpc32xx_set_phy_interface_mode(phy_interface_t mode); +extern void lpc32xx_loopback_set(resource_size_t mapbase, int state); #else static inline u32 lpc32xx_return_iram(void __iomem **mapbase, dma_addr_t *dmaaddr) { @@ -24,6 +25,9 @@ static inline u32 lpc32xx_return_iram(void __iomem **mapbase, dma_addr_t *dmaadd static inline void lpc32xx_set_phy_interface_mode(phy_interface_t mode) { } +static inline void lpc32xx_loopback_set(resource_size_t mapbase, int state) +{ +} #endif #endif /* __SOC_LPC32XX_MISC_H */ -- cgit v1.3-14-g43fede From d3532910038bb1e95e9c5952e98dd1d18b636e8b Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Fri, 9 Aug 2019 16:40:38 +0200 Subject: ARM: lpc32xx: clean up header files All device drivers have stopped relying on mach/*.h headers, so move the remaining headers into arch/arm/mach-lpc32xx/lpc32xx.h to prepare for multiplatform builds. The mach/entry-macro.S file has been unused for a long time now and can simply get removed. Link: https://lore.kernel.org/r/20190809144043.476786-13-arnd@arndb.de Acked-by: Sylvain Lemieux Signed-off-by: Arnd Bergmann --- arch/arm/mach-lpc32xx/common.c | 3 +- arch/arm/mach-lpc32xx/include/mach/entry-macro.S | 28 - arch/arm/mach-lpc32xx/include/mach/hardware.h | 25 - arch/arm/mach-lpc32xx/include/mach/platform.h | 703 ---------------------- arch/arm/mach-lpc32xx/include/mach/uncompress.h | 4 +- arch/arm/mach-lpc32xx/lpc32xx.h | 717 +++++++++++++++++++++++ arch/arm/mach-lpc32xx/pm.c | 3 +- arch/arm/mach-lpc32xx/serial.c | 3 +- arch/arm/mach-lpc32xx/suspend.S | 3 +- 9 files changed, 722 insertions(+), 767 deletions(-) delete mode 100644 arch/arm/mach-lpc32xx/include/mach/entry-macro.S delete mode 100644 arch/arm/mach-lpc32xx/include/mach/hardware.h delete mode 100644 arch/arm/mach-lpc32xx/include/mach/platform.h create mode 100644 arch/arm/mach-lpc32xx/lpc32xx.h diff --git a/arch/arm/mach-lpc32xx/common.c b/arch/arm/mach-lpc32xx/common.c index a475339333c1..304ea61a0716 100644 --- a/arch/arm/mach-lpc32xx/common.c +++ b/arch/arm/mach-lpc32xx/common.c @@ -13,8 +13,7 @@ #include #include -#include -#include +#include "lpc32xx.h" #include "common.h" /* diff --git a/arch/arm/mach-lpc32xx/include/mach/entry-macro.S b/arch/arm/mach-lpc32xx/include/mach/entry-macro.S deleted file mode 100644 index eec0f5f7e722..000000000000 --- a/arch/arm/mach-lpc32xx/include/mach/entry-macro.S +++ /dev/null @@ -1,28 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * arch/arm/mach-lpc32xx/include/mach/entry-macro.S - * - * Author: Kevin Wells - * - * Copyright (C) 2010 NXP Semiconductors - */ - -#include -#include - -#define LPC32XX_INTC_MASKED_STATUS_OFS 0x8 - - .macro get_irqnr_preamble, base, tmp - ldr \base, =IO_ADDRESS(LPC32XX_MIC_BASE) - .endm - -/* - * Return IRQ number in irqnr. Also return processor Z flag status in CPSR - * as set if an interrupt is pending. - */ - .macro get_irqnr_and_base, irqnr, irqstat, base, tmp - ldr \irqstat, [\base, #LPC32XX_INTC_MASKED_STATUS_OFS] - clz \irqnr, \irqstat - rsb \irqnr, \irqnr, #31 - teq \irqstat, #0 - .endm diff --git a/arch/arm/mach-lpc32xx/include/mach/hardware.h b/arch/arm/mach-lpc32xx/include/mach/hardware.h deleted file mode 100644 index 4866f096ffce..000000000000 --- a/arch/arm/mach-lpc32xx/include/mach/hardware.h +++ /dev/null @@ -1,25 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * arch/arm/mach-lpc32xx/include/mach/hardware.h - * - * Copyright (c) 2005 MontaVista Software, Inc. - */ - -#ifndef __ASM_ARCH_HARDWARE_H -#define __ASM_ARCH_HARDWARE_H - -/* - * Start of virtual addresses for IO devices - */ -#define IO_BASE 0xF0000000 - -/* - * This macro relies on fact that for all HW i/o addresses bits 20-23 are 0 - */ -#define IO_ADDRESS(x) IOMEM(((((x) & 0xff000000) >> 4) | ((x) & 0xfffff)) |\ - IO_BASE) - -#define io_p2v(x) ((void __iomem *) (unsigned long) IO_ADDRESS(x)) -#define io_v2p(x) ((((x) & 0x0ff00000) << 4) | ((x) & 0x000fffff)) - -#endif diff --git a/arch/arm/mach-lpc32xx/include/mach/platform.h b/arch/arm/mach-lpc32xx/include/mach/platform.h deleted file mode 100644 index 1c53790444fc..000000000000 --- a/arch/arm/mach-lpc32xx/include/mach/platform.h +++ /dev/null @@ -1,703 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * arch/arm/mach-lpc32xx/include/mach/platform.h - * - * Author: Kevin Wells - * - * Copyright (C) 2010 NXP Semiconductors - */ - -#ifndef __ASM_ARCH_PLATFORM_H -#define __ASM_ARCH_PLATFORM_H - -#define _SBF(f, v) ((v) << (f)) -#define _BIT(n) _SBF(n, 1) - -/* - * AHB 0 physical base addresses - */ -#define LPC32XX_SLC_BASE 0x20020000 -#define LPC32XX_SSP0_BASE 0x20084000 -#define LPC32XX_SPI1_BASE 0x20088000 -#define LPC32XX_SSP1_BASE 0x2008C000 -#define LPC32XX_SPI2_BASE 0x20090000 -#define LPC32XX_I2S0_BASE 0x20094000 -#define LPC32XX_SD_BASE 0x20098000 -#define LPC32XX_I2S1_BASE 0x2009C000 -#define LPC32XX_MLC_BASE 0x200A8000 -#define LPC32XX_AHB0_START LPC32XX_SLC_BASE -#define LPC32XX_AHB0_SIZE 0x00089000 - -/* - * AHB 1 physical base addresses - */ -#define LPC32XX_DMA_BASE 0x31000000 -#define LPC32XX_USB_BASE 0x31020000 -#define LPC32XX_USBH_BASE 0x31020000 -#define LPC32XX_USB_OTG_BASE 0x31020000 -#define LPC32XX_OTG_I2C_BASE 0x31020300 -#define LPC32XX_LCD_BASE 0x31040000 -#define LPC32XX_ETHERNET_BASE 0x31060000 -#define LPC32XX_EMC_BASE 0x31080000 -#define LPC32XX_ETB_CFG_BASE 0x310C0000 -#define LPC32XX_ETB_DATA_BASE 0x310E0000 -#define LPC32XX_AHB1_START LPC32XX_DMA_BASE -#define LPC32XX_AHB1_SIZE 0x000E1000 - -/* - * FAB physical base addresses - */ -#define LPC32XX_CLK_PM_BASE 0x40004000 -#define LPC32XX_MIC_BASE 0x40008000 -#define LPC32XX_SIC1_BASE 0x4000C000 -#define LPC32XX_SIC2_BASE 0x40010000 -#define LPC32XX_HS_UART1_BASE 0x40014000 -#define LPC32XX_HS_UART2_BASE 0x40018000 -#define LPC32XX_HS_UART7_BASE 0x4001C000 -#define LPC32XX_RTC_BASE 0x40024000 -#define LPC32XX_RTC_RAM_BASE 0x40024080 -#define LPC32XX_GPIO_BASE 0x40028000 -#define LPC32XX_PWM3_BASE 0x4002C000 -#define LPC32XX_PWM4_BASE 0x40030000 -#define LPC32XX_MSTIM_BASE 0x40034000 -#define LPC32XX_HSTIM_BASE 0x40038000 -#define LPC32XX_WDTIM_BASE 0x4003C000 -#define LPC32XX_DEBUG_CTRL_BASE 0x40040000 -#define LPC32XX_TIMER0_BASE 0x40044000 -#define LPC32XX_ADC_BASE 0x40048000 -#define LPC32XX_TIMER1_BASE 0x4004C000 -#define LPC32XX_KSCAN_BASE 0x40050000 -#define LPC32XX_UART_CTRL_BASE 0x40054000 -#define LPC32XX_TIMER2_BASE 0x40058000 -#define LPC32XX_PWM1_BASE 0x4005C000 -#define LPC32XX_PWM2_BASE 0x4005C004 -#define LPC32XX_TIMER3_BASE 0x40060000 - -/* - * APB physical base addresses - */ -#define LPC32XX_UART3_BASE 0x40080000 -#define LPC32XX_UART4_BASE 0x40088000 -#define LPC32XX_UART5_BASE 0x40090000 -#define LPC32XX_UART6_BASE 0x40098000 -#define LPC32XX_I2C1_BASE 0x400A0000 -#define LPC32XX_I2C2_BASE 0x400A8000 - -/* - * FAB and APB base and sizing - */ -#define LPC32XX_FABAPB_START LPC32XX_CLK_PM_BASE -#define LPC32XX_FABAPB_SIZE 0x000A5000 - -/* - * Internal memory bases and sizes - */ -#define LPC32XX_IRAM_BASE 0x08000000 -#define LPC32XX_IROM_BASE 0x0C000000 - -/* - * External Static Memory Bank Address Space Bases - */ -#define LPC32XX_EMC_CS0_BASE 0xE0000000 -#define LPC32XX_EMC_CS1_BASE 0xE1000000 -#define LPC32XX_EMC_CS2_BASE 0xE2000000 -#define LPC32XX_EMC_CS3_BASE 0xE3000000 - -/* - * External SDRAM Memory Bank Address Space Bases - */ -#define LPC32XX_EMC_DYCS0_BASE 0x80000000 -#define LPC32XX_EMC_DYCS1_BASE 0xA0000000 - -/* - * Clock and crystal information - */ -#define LPC32XX_MAIN_OSC_FREQ 13000000 -#define LPC32XX_CLOCK_OSC_FREQ 32768 - -/* - * Clock and Power control register offsets - */ -#define _PMREG(x) io_p2v(LPC32XX_CLK_PM_BASE +\ - (x)) -#define LPC32XX_CLKPWR_DEBUG_CTRL _PMREG(0x000) -#define LPC32XX_CLKPWR_BOOTMAP _PMREG(0x014) -#define LPC32XX_CLKPWR_P01_ER _PMREG(0x018) -#define LPC32XX_CLKPWR_USBCLK_PDIV _PMREG(0x01C) -#define LPC32XX_CLKPWR_INT_ER _PMREG(0x020) -#define LPC32XX_CLKPWR_INT_RS _PMREG(0x024) -#define LPC32XX_CLKPWR_INT_SR _PMREG(0x028) -#define LPC32XX_CLKPWR_INT_AP _PMREG(0x02C) -#define LPC32XX_CLKPWR_PIN_ER _PMREG(0x030) -#define LPC32XX_CLKPWR_PIN_RS _PMREG(0x034) -#define LPC32XX_CLKPWR_PIN_SR _PMREG(0x038) -#define LPC32XX_CLKPWR_PIN_AP _PMREG(0x03C) -#define LPC32XX_CLKPWR_HCLK_DIV _PMREG(0x040) -#define LPC32XX_CLKPWR_PWR_CTRL _PMREG(0x044) -#define LPC32XX_CLKPWR_PLL397_CTRL _PMREG(0x048) -#define LPC32XX_CLKPWR_MAIN_OSC_CTRL _PMREG(0x04C) -#define LPC32XX_CLKPWR_SYSCLK_CTRL _PMREG(0x050) -#define LPC32XX_CLKPWR_LCDCLK_CTRL _PMREG(0x054) -#define LPC32XX_CLKPWR_HCLKPLL_CTRL _PMREG(0x058) -#define LPC32XX_CLKPWR_ADC_CLK_CTRL_1 _PMREG(0x060) -#define LPC32XX_CLKPWR_USB_CTRL _PMREG(0x064) -#define LPC32XX_CLKPWR_SDRAMCLK_CTRL _PMREG(0x068) -#define LPC32XX_CLKPWR_DDR_LAP_NOM _PMREG(0x06C) -#define LPC32XX_CLKPWR_DDR_LAP_COUNT _PMREG(0x070) -#define LPC32XX_CLKPWR_DDR_LAP_DELAY _PMREG(0x074) -#define LPC32XX_CLKPWR_SSP_CLK_CTRL _PMREG(0x078) -#define LPC32XX_CLKPWR_I2S_CLK_CTRL _PMREG(0x07C) -#define LPC32XX_CLKPWR_MS_CTRL _PMREG(0x080) -#define LPC32XX_CLKPWR_MACCLK_CTRL _PMREG(0x090) -#define LPC32XX_CLKPWR_TEST_CLK_SEL _PMREG(0x0A4) -#define LPC32XX_CLKPWR_SFW_INT _PMREG(0x0A8) -#define LPC32XX_CLKPWR_I2C_CLK_CTRL _PMREG(0x0AC) -#define LPC32XX_CLKPWR_KEY_CLK_CTRL _PMREG(0x0B0) -#define LPC32XX_CLKPWR_ADC_CLK_CTRL _PMREG(0x0B4) -#define LPC32XX_CLKPWR_PWM_CLK_CTRL _PMREG(0x0B8) -#define LPC32XX_CLKPWR_TIMER_CLK_CTRL _PMREG(0x0BC) -#define LPC32XX_CLKPWR_TIMERS_PWMS_CLK_CTRL_1 _PMREG(0x0C0) -#define LPC32XX_CLKPWR_SPI_CLK_CTRL _PMREG(0x0C4) -#define LPC32XX_CLKPWR_NAND_CLK_CTRL _PMREG(0x0C8) -#define LPC32XX_CLKPWR_UART3_CLK_CTRL _PMREG(0x0D0) -#define LPC32XX_CLKPWR_UART4_CLK_CTRL _PMREG(0x0D4) -#define LPC32XX_CLKPWR_UART5_CLK_CTRL _PMREG(0x0D8) -#define LPC32XX_CLKPWR_UART6_CLK_CTRL _PMREG(0x0DC) -#define LPC32XX_CLKPWR_IRDA_CLK_CTRL _PMREG(0x0E0) -#define LPC32XX_CLKPWR_UART_CLK_CTRL _PMREG(0x0E4) -#define LPC32XX_CLKPWR_DMA_CLK_CTRL _PMREG(0x0E8) -#define LPC32XX_CLKPWR_AUTOCLOCK _PMREG(0x0EC) -#define LPC32XX_CLKPWR_DEVID(x) _PMREG(0x130 + (x)) - -/* - * clkpwr_debug_ctrl register definitions -*/ -#define LPC32XX_CLKPWR_VFP_CLOCK_ENABLE_BIT _BIT(4) - -/* - * clkpwr_bootmap register definitions - */ -#define LPC32XX_CLKPWR_BOOTMAP_SEL_BIT _BIT(1) - -/* - * clkpwr_start_gpio register bit definitions - */ -#define LPC32XX_CLKPWR_GPIOSRC_P1IO23_BIT _BIT(31) -#define LPC32XX_CLKPWR_GPIOSRC_P1IO22_BIT _BIT(30) -#define LPC32XX_CLKPWR_GPIOSRC_P1IO21_BIT _BIT(29) -#define LPC32XX_CLKPWR_GPIOSRC_P1IO20_BIT _BIT(28) -#define LPC32XX_CLKPWR_GPIOSRC_P1IO19_BIT _BIT(27) -#define LPC32XX_CLKPWR_GPIOSRC_P1IO18_BIT _BIT(26) -#define LPC32XX_CLKPWR_GPIOSRC_P1IO17_BIT _BIT(25) -#define LPC32XX_CLKPWR_GPIOSRC_P1IO16_BIT _BIT(24) -#define LPC32XX_CLKPWR_GPIOSRC_P1IO15_BIT _BIT(23) -#define LPC32XX_CLKPWR_GPIOSRC_P1IO14_BIT _BIT(22) -#define LPC32XX_CLKPWR_GPIOSRC_P1IO13_BIT _BIT(21) -#define LPC32XX_CLKPWR_GPIOSRC_P1IO12_BIT _BIT(20) -#define LPC32XX_CLKPWR_GPIOSRC_P1IO11_BIT _BIT(19) -#define LPC32XX_CLKPWR_GPIOSRC_P1IO10_BIT _BIT(18) -#define LPC32XX_CLKPWR_GPIOSRC_P1IO9_BIT _BIT(17) -#define LPC32XX_CLKPWR_GPIOSRC_P1IO8_BIT _BIT(16) -#define LPC32XX_CLKPWR_GPIOSRC_P1IO7_BIT _BIT(15) -#define LPC32XX_CLKPWR_GPIOSRC_P1IO6_BIT _BIT(14) -#define LPC32XX_CLKPWR_GPIOSRC_P1IO5_BIT _BIT(13) -#define LPC32XX_CLKPWR_GPIOSRC_P1IO4_BIT _BIT(12) -#define LPC32XX_CLKPWR_GPIOSRC_P1IO3_BIT _BIT(11) -#define LPC32XX_CLKPWR_GPIOSRC_P1IO2_BIT _BIT(10) -#define LPC32XX_CLKPWR_GPIOSRC_P1IO1_BIT _BIT(9) -#define LPC32XX_CLKPWR_GPIOSRC_P1IO0_BIT _BIT(8) -#define LPC32XX_CLKPWR_GPIOSRC_P0IO7_BIT _BIT(7) -#define LPC32XX_CLKPWR_GPIOSRC_P0IO6_BIT _BIT(6) -#define LPC32XX_CLKPWR_GPIOSRC_P0IO5_BIT _BIT(5) -#define LPC32XX_CLKPWR_GPIOSRC_P0IO4_BIT _BIT(4) -#define LPC32XX_CLKPWR_GPIOSRC_P0IO3_BIT _BIT(3) -#define LPC32XX_CLKPWR_GPIOSRC_P0IO2_BIT _BIT(2) -#define LPC32XX_CLKPWR_GPIOSRC_P0IO1_BIT _BIT(1) -#define LPC32XX_CLKPWR_GPIOSRC_P0IO0_BIT _BIT(0) - -/* - * clkpwr_usbclk_pdiv register definitions - */ -#define LPC32XX_CLKPWR_USBPDIV_PLL_MASK 0xF - -/* - * clkpwr_start_int, clkpwr_start_raw_sts_int, clkpwr_start_sts_int, - * clkpwr_start_pol_int, register bit definitions - */ -#define LPC32XX_CLKPWR_INTSRC_ADC_BIT _BIT(31) -#define LPC32XX_CLKPWR_INTSRC_TS_P_BIT _BIT(30) -#define LPC32XX_CLKPWR_INTSRC_TS_AUX_BIT _BIT(29) -#define LPC32XX_CLKPWR_INTSRC_USBAHNEEDCLK_BIT _BIT(26) -#define LPC32XX_CLKPWR_INTSRC_MSTIMER_BIT _BIT(25) -#define LPC32XX_CLKPWR_INTSRC_RTC_BIT _BIT(24) -#define LPC32XX_CLKPWR_INTSRC_USBNEEDCLK_BIT _BIT(23) -#define LPC32XX_CLKPWR_INTSRC_USB_BIT _BIT(22) -#define LPC32XX_CLKPWR_INTSRC_I2C_BIT _BIT(21) -#define LPC32XX_CLKPWR_INTSRC_USBOTGTIMER_BIT _BIT(20) -#define LPC32XX_CLKPWR_INTSRC_USBATXINT_BIT _BIT(19) -#define LPC32XX_CLKPWR_INTSRC_KEY_BIT _BIT(16) -#define LPC32XX_CLKPWR_INTSRC_MAC_BIT _BIT(7) -#define LPC32XX_CLKPWR_INTSRC_P0P1_BIT _BIT(6) -#define LPC32XX_CLKPWR_INTSRC_GPIO_05_BIT _BIT(5) -#define LPC32XX_CLKPWR_INTSRC_GPIO_04_BIT _BIT(4) -#define LPC32XX_CLKPWR_INTSRC_GPIO_03_BIT _BIT(3) -#define LPC32XX_CLKPWR_INTSRC_GPIO_02_BIT _BIT(2) -#define LPC32XX_CLKPWR_INTSRC_GPIO_01_BIT _BIT(1) -#define LPC32XX_CLKPWR_INTSRC_GPIO_00_BIT _BIT(0) - -/* - * clkpwr_start_pin, clkpwr_start_raw_sts_pin, clkpwr_start_sts_pin, - * clkpwr_start_pol_pin register bit definitions - */ -#define LPC32XX_CLKPWR_EXTSRC_U7_RX_BIT _BIT(31) -#define LPC32XX_CLKPWR_EXTSRC_U7_HCTS_BIT _BIT(30) -#define LPC32XX_CLKPWR_EXTSRC_U6_IRRX_BIT _BIT(28) -#define LPC32XX_CLKPWR_EXTSRC_U5_RX_BIT _BIT(26) -#define LPC32XX_CLKPWR_EXTSRC_GPI_28_BIT _BIT(25) -#define LPC32XX_CLKPWR_EXTSRC_U3_RX_BIT _BIT(24) -#define LPC32XX_CLKPWR_EXTSRC_U2_HCTS_BIT _BIT(23) -#define LPC32XX_CLKPWR_EXTSRC_U2_RX_BIT _BIT(22) -#define LPC32XX_CLKPWR_EXTSRC_U1_RX_BIT _BIT(21) -#define LPC32XX_CLKPWR_EXTSRC_MSDIO_INT_BIT _BIT(18) -#define LPC32XX_CLKPWR_EXTSRC_MSDIO_SRT_BIT _BIT(17) -#define LPC32XX_CLKPWR_EXTSRC_GPI_06_BIT _BIT(16) -#define LPC32XX_CLKPWR_EXTSRC_GPI_05_BIT _BIT(15) -#define LPC32XX_CLKPWR_EXTSRC_GPI_04_BIT _BIT(14) -#define LPC32XX_CLKPWR_EXTSRC_GPI_03_BIT _BIT(13) -#define LPC32XX_CLKPWR_EXTSRC_GPI_02_BIT _BIT(12) -#define LPC32XX_CLKPWR_EXTSRC_GPI_01_BIT _BIT(11) -#define LPC32XX_CLKPWR_EXTSRC_GPI_00_BIT _BIT(10) -#define LPC32XX_CLKPWR_EXTSRC_SYSCLKEN_BIT _BIT(9) -#define LPC32XX_CLKPWR_EXTSRC_SPI1_DATIN_BIT _BIT(8) -#define LPC32XX_CLKPWR_EXTSRC_GPI_07_BIT _BIT(7) -#define LPC32XX_CLKPWR_EXTSRC_SPI2_DATIN_BIT _BIT(6) -#define LPC32XX_CLKPWR_EXTSRC_GPI_19_BIT _BIT(5) -#define LPC32XX_CLKPWR_EXTSRC_GPI_09_BIT _BIT(4) -#define LPC32XX_CLKPWR_EXTSRC_GPI_08_BIT _BIT(3) - -/* - * clkpwr_hclk_div register definitions - */ -#define LPC32XX_CLKPWR_HCLKDIV_DDRCLK_STOP (0x0 << 7) -#define LPC32XX_CLKPWR_HCLKDIV_DDRCLK_NORM (0x1 << 7) -#define LPC32XX_CLKPWR_HCLKDIV_DDRCLK_HALF (0x2 << 7) -#define LPC32XX_CLKPWR_HCLKDIV_PCLK_DIV(n) (((n) & 0x1F) << 2) -#define LPC32XX_CLKPWR_HCLKDIV_DIV_2POW(n) ((n) & 0x3) - -/* - * clkpwr_pwr_ctrl register definitions - */ -#define LPC32XX_CLKPWR_CTRL_FORCE_PCLK _BIT(10) -#define LPC32XX_CLKPWR_SDRAM_SELF_RFSH _BIT(9) -#define LPC32XX_CLKPWR_UPD_SDRAM_SELF_RFSH _BIT(8) -#define LPC32XX_CLKPWR_AUTO_SDRAM_SELF_RFSH _BIT(7) -#define LPC32XX_CLKPWR_HIGHCORE_STATE_BIT _BIT(5) -#define LPC32XX_CLKPWR_SYSCLKEN_STATE_BIT _BIT(4) -#define LPC32XX_CLKPWR_SYSCLKEN_GPIO_EN _BIT(3) -#define LPC32XX_CLKPWR_SELECT_RUN_MODE _BIT(2) -#define LPC32XX_CLKPWR_HIGHCORE_GPIO_EN _BIT(1) -#define LPC32XX_CLKPWR_STOP_MODE_CTRL _BIT(0) - -/* - * clkpwr_pll397_ctrl register definitions - */ -#define LPC32XX_CLKPWR_PLL397_MSLOCK_STS _BIT(10) -#define LPC32XX_CLKPWR_PLL397_BYPASS _BIT(9) -#define LPC32XX_CLKPWR_PLL397_BIAS_NORM 0x000 -#define LPC32XX_CLKPWR_PLL397_BIAS_N12_5 0x040 -#define LPC32XX_CLKPWR_PLL397_BIAS_N25 0x080 -#define LPC32XX_CLKPWR_PLL397_BIAS_N37_5 0x0C0 -#define LPC32XX_CLKPWR_PLL397_BIAS_P12_5 0x100 -#define LPC32XX_CLKPWR_PLL397_BIAS_P25 0x140 -#define LPC32XX_CLKPWR_PLL397_BIAS_P37_5 0x180 -#define LPC32XX_CLKPWR_PLL397_BIAS_P50 0x1C0 -#define LPC32XX_CLKPWR_PLL397_BIAS_MASK 0x1C0 -#define LPC32XX_CLKPWR_SYSCTRL_PLL397_DIS _BIT(1) -#define LPC32XX_CLKPWR_SYSCTRL_PLL397_STS _BIT(0) - -/* - * clkpwr_main_osc_ctrl register definitions - */ -#define LPC32XX_CLKPWR_MOSC_ADD_CAP(n) (((n) & 0x7F) << 2) -#define LPC32XX_CLKPWR_MOSC_CAP_MASK (0x7F << 2) -#define LPC32XX_CLKPWR_TEST_MODE _BIT(1) -#define LPC32XX_CLKPWR_MOSC_DISABLE _BIT(0) - -/* - * clkpwr_sysclk_ctrl register definitions - */ -#define LPC32XX_CLKPWR_SYSCTRL_BP_TRIG(n) (((n) & 0x3FF) << 2) -#define LPC32XX_CLKPWR_SYSCTRL_BP_MASK (0x3FF << 2) -#define LPC32XX_CLKPWR_SYSCTRL_USEPLL397 _BIT(1) -#define LPC32XX_CLKPWR_SYSCTRL_SYSCLKMUX _BIT(0) - -/* - * clkpwr_lcdclk_ctrl register definitions - */ -#define LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_TFT12 0x000 -#define LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_TFT16 0x040 -#define LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_TFT15 0x080 -#define LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_TFT24 0x0C0 -#define LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_STN4M 0x100 -#define LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_STN8C 0x140 -#define LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_DSTN4M 0x180 -#define LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_DSTN8C 0x1C0 -#define LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_MSK 0x01C0 -#define LPC32XX_CLKPWR_LCDCTRL_CLK_EN 0x020 -#define LPC32XX_CLKPWR_LCDCTRL_SET_PSCALE(n) ((n - 1) & 0x1F) -#define LPC32XX_CLKPWR_LCDCTRL_PSCALE_MSK 0x001F - -/* - * clkpwr_hclkpll_ctrl register definitions - */ -#define LPC32XX_CLKPWR_HCLKPLL_POWER_UP _BIT(16) -#define LPC32XX_CLKPWR_HCLKPLL_CCO_BYPASS _BIT(15) -#define LPC32XX_CLKPWR_HCLKPLL_POSTDIV_BYPASS _BIT(14) -#define LPC32XX_CLKPWR_HCLKPLL_FDBK_SEL_FCLK _BIT(13) -#define LPC32XX_CLKPWR_HCLKPLL_POSTDIV_2POW(n) (((n) & 0x3) << 11) -#define LPC32XX_CLKPWR_HCLKPLL_PREDIV_PLUS1(n) (((n) & 0x3) << 9) -#define LPC32XX_CLKPWR_HCLKPLL_PLLM(n) (((n) & 0xFF) << 1) -#define LPC32XX_CLKPWR_HCLKPLL_PLL_STS _BIT(0) - -/* - * clkpwr_adc_clk_ctrl_1 register definitions - */ -#define LPC32XX_CLKPWR_ADCCTRL1_RTDIV(n) (((n) & 0xFF) << 0) -#define LPC32XX_CLKPWR_ADCCTRL1_PCLK_SEL _BIT(8) - -/* - * clkpwr_usb_ctrl register definitions - */ -#define LPC32XX_CLKPWR_USBCTRL_HCLK_EN _BIT(24) -#define LPC32XX_CLKPWR_USBCTRL_USBI2C_EN _BIT(23) -#define LPC32XX_CLKPWR_USBCTRL_USBDVND_EN _BIT(22) -#define LPC32XX_CLKPWR_USBCTRL_USBHSTND_EN _BIT(21) -#define LPC32XX_CLKPWR_USBCTRL_PU_ADD (0x0 << 19) -#define LPC32XX_CLKPWR_USBCTRL_BUS_KEEPER (0x1 << 19) -#define LPC32XX_CLKPWR_USBCTRL_PD_ADD (0x3 << 19) -#define LPC32XX_CLKPWR_USBCTRL_CLK_EN2 _BIT(18) -#define LPC32XX_CLKPWR_USBCTRL_CLK_EN1 _BIT(17) -#define LPC32XX_CLKPWR_USBCTRL_PLL_PWRUP _BIT(16) -#define LPC32XX_CLKPWR_USBCTRL_CCO_BYPASS _BIT(15) -#define LPC32XX_CLKPWR_USBCTRL_POSTDIV_BYPASS _BIT(14) -#define LPC32XX_CLKPWR_USBCTRL_FDBK_SEL_FCLK _BIT(13) -#define LPC32XX_CLKPWR_USBCTRL_POSTDIV_2POW(n) (((n) & 0x3) << 11) -#define LPC32XX_CLKPWR_USBCTRL_PREDIV_PLUS1(n) (((n) & 0x3) << 9) -#define LPC32XX_CLKPWR_USBCTRL_FDBK_PLUS1(n) (((n) & 0xFF) << 1) -#define LPC32XX_CLKPWR_USBCTRL_PLL_STS _BIT(0) - -/* - * clkpwr_sdramclk_ctrl register definitions - */ -#define LPC32XX_CLKPWR_SDRCLK_FASTSLEW_CLK _BIT(22) -#define LPC32XX_CLKPWR_SDRCLK_FASTSLEW _BIT(21) -#define LPC32XX_CLKPWR_SDRCLK_FASTSLEW_DAT _BIT(20) -#define LPC32XX_CLKPWR_SDRCLK_SW_DDR_RESET _BIT(19) -#define LPC32XX_CLKPWR_SDRCLK_HCLK_DLY(n) (((n) & 0x1F) << 14) -#define LPC32XX_CLKPWR_SDRCLK_DLY_ADDR_STS _BIT(13) -#define LPC32XX_CLKPWR_SDRCLK_SENS_FACT(n) (((n) & 0x7) << 10) -#define LPC32XX_CLKPWR_SDRCLK_USE_CAL _BIT(9) -#define LPC32XX_CLKPWR_SDRCLK_DO_CAL _BIT(8) -#define LPC32XX_CLKPWR_SDRCLK_CAL_ON_RTC _BIT(7) -#define LPC32XX_CLKPWR_SDRCLK_DQS_DLY(n) (((n) & 0x1F) << 2) -#define LPC32XX_CLKPWR_SDRCLK_USE_DDR _BIT(1) -#define LPC32XX_CLKPWR_SDRCLK_CLK_DIS _BIT(0) - -/* - * clkpwr_ssp_blk_ctrl register definitions - */ -#define LPC32XX_CLKPWR_SSPCTRL_DMA_SSP1RX _BIT(5) -#define LPC32XX_CLKPWR_SSPCTRL_DMA_SSP1TX _BIT(4) -#define LPC32XX_CLKPWR_SSPCTRL_DMA_SSP0RX _BIT(3) -#define LPC32XX_CLKPWR_SSPCTRL_DMA_SSP0TX _BIT(2) -#define LPC32XX_CLKPWR_SSPCTRL_SSPCLK1_EN _BIT(1) -#define LPC32XX_CLKPWR_SSPCTRL_SSPCLK0_EN _BIT(0) - -/* - * clkpwr_i2s_clk_ctrl register definitions - */ -#define LPC32XX_CLKPWR_I2SCTRL_I2S1_RX_FOR_TX _BIT(6) -#define LPC32XX_CLKPWR_I2SCTRL_I2S1_TX_FOR_RX _BIT(5) -#define LPC32XX_CLKPWR_I2SCTRL_I2S1_USE_DMA _BIT(4) -#define LPC32XX_CLKPWR_I2SCTRL_I2S0_RX_FOR_TX _BIT(3) -#define LPC32XX_CLKPWR_I2SCTRL_I2S0_TX_FOR_RX _BIT(2) -#define LPC32XX_CLKPWR_I2SCTRL_I2SCLK1_EN _BIT(1) -#define LPC32XX_CLKPWR_I2SCTRL_I2SCLK0_EN _BIT(0) - -/* - * clkpwr_ms_ctrl register definitions - */ -#define LPC32XX_CLKPWR_MSCARD_MSDIO_PIN_DIS _BIT(10) -#define LPC32XX_CLKPWR_MSCARD_MSDIO_PU_EN _BIT(9) -#define LPC32XX_CLKPWR_MSCARD_MSDIO23_DIS _BIT(8) -#define LPC32XX_CLKPWR_MSCARD_MSDIO1_DIS _BIT(7) -#define LPC32XX_CLKPWR_MSCARD_MSDIO0_DIS _BIT(6) -#define LPC32XX_CLKPWR_MSCARD_SDCARD_EN _BIT(5) -#define LPC32XX_CLKPWR_MSCARD_SDCARD_DIV(n) ((n) & 0xF) - -/* - * clkpwr_macclk_ctrl register definitions - */ -#define LPC32XX_CLKPWR_MACCTRL_NO_ENET_PIS 0x00 -#define LPC32XX_CLKPWR_MACCTRL_USE_MII_PINS 0x08 -#define LPC32XX_CLKPWR_MACCTRL_USE_RMII_PINS 0x18 -#define LPC32XX_CLKPWR_MACCTRL_PINS_MSK 0x18 -#define LPC32XX_CLKPWR_MACCTRL_DMACLK_EN _BIT(2) -#define LPC32XX_CLKPWR_MACCTRL_MMIOCLK_EN _BIT(1) -#define LPC32XX_CLKPWR_MACCTRL_HRCCLK_EN _BIT(0) - -/* - * clkpwr_test_clk_sel register definitions - */ -#define LPC32XX_CLKPWR_TESTCLK1_SEL_PERCLK (0x0 << 5) -#define LPC32XX_CLKPWR_TESTCLK1_SEL_RTC (0x1 << 5) -#define LPC32XX_CLKPWR_TESTCLK1_SEL_MOSC (0x2 << 5) -#define LPC32XX_CLKPWR_TESTCLK1_SEL_MASK (0x3 << 5) -#define LPC32XX_CLKPWR_TESTCLK_TESTCLK1_EN _BIT(4) -#define LPC32XX_CLKPWR_TESTCLK2_SEL_HCLK (0x0 << 1) -#define LPC32XX_CLKPWR_TESTCLK2_SEL_PERCLK (0x1 << 1) -#define LPC32XX_CLKPWR_TESTCLK2_SEL_USBCLK (0x2 << 1) -#define LPC32XX_CLKPWR_TESTCLK2_SEL_MOSC (0x5 << 1) -#define LPC32XX_CLKPWR_TESTCLK2_SEL_PLL397 (0x7 << 1) -#define LPC32XX_CLKPWR_TESTCLK2_SEL_MASK (0x7 << 1) -#define LPC32XX_CLKPWR_TESTCLK_TESTCLK2_EN _BIT(0) - -/* - * clkpwr_sw_int register definitions - */ -#define LPC32XX_CLKPWR_SW_INT(n) (_BIT(0) | (((n) & 0x7F) << 1)) -#define LPC32XX_CLKPWR_SW_GET_ARG(n) (((n) & 0xFE) >> 1) - -/* - * clkpwr_i2c_clk_ctrl register definitions - */ -#define LPC32XX_CLKPWR_I2CCLK_USBI2CHI_DRIVE _BIT(4) -#define LPC32XX_CLKPWR_I2CCLK_I2C2HI_DRIVE _BIT(3) -#define LPC32XX_CLKPWR_I2CCLK_I2C1HI_DRIVE _BIT(2) -#define LPC32XX_CLKPWR_I2CCLK_I2C2CLK_EN _BIT(1) -#define LPC32XX_CLKPWR_I2CCLK_I2C1CLK_EN _BIT(0) - -/* - * clkpwr_key_clk_ctrl register definitions - */ -#define LPC32XX_CLKPWR_KEYCLKCTRL_CLK_EN 0x1 - -/* - * clkpwr_adc_clk_ctrl register definitions - */ -#define LPC32XX_CLKPWR_ADC32CLKCTRL_CLK_EN 0x1 - -/* - * clkpwr_pwm_clk_ctrl register definitions - */ -#define LPC32XX_CLKPWR_PWMCLK_PWM2_DIV(n) (((n) & 0xF) << 8) -#define LPC32XX_CLKPWR_PWMCLK_PWM1_DIV(n) (((n) & 0xF) << 4) -#define LPC32XX_CLKPWR_PWMCLK_PWM2SEL_PCLK 0x8 -#define LPC32XX_CLKPWR_PWMCLK_PWM2CLK_EN 0x4 -#define LPC32XX_CLKPWR_PWMCLK_PWM1SEL_PCLK 0x2 -#define LPC32XX_CLKPWR_PWMCLK_PWM1CLK_EN 0x1 - -/* - * clkpwr_timer_clk_ctrl register definitions - */ -#define LPC32XX_CLKPWR_PWMCLK_HSTIMER_EN 0x2 -#define LPC32XX_CLKPWR_PWMCLK_WDOG_EN 0x1 - -/* - * clkpwr_timers_pwms_clk_ctrl_1 register definitions - */ -#define LPC32XX_CLKPWR_TMRPWMCLK_MPWM_EN 0x40 -#define LPC32XX_CLKPWR_TMRPWMCLK_TIMER3_EN 0x20 -#define LPC32XX_CLKPWR_TMRPWMCLK_TIMER2_EN 0x10 -#define LPC32XX_CLKPWR_TMRPWMCLK_TIMER1_EN 0x08 -#define LPC32XX_CLKPWR_TMRPWMCLK_TIMER0_EN 0x04 -#define LPC32XX_CLKPWR_TMRPWMCLK_PWM4_EN 0x02 -#define LPC32XX_CLKPWR_TMRPWMCLK_PWM3_EN 0x01 - -/* - * clkpwr_spi_clk_ctrl register definitions - */ -#define LPC32XX_CLKPWR_SPICLK_SET_SPI2DATIO 0x80 -#define LPC32XX_CLKPWR_SPICLK_SET_SPI2CLK 0x40 -#define LPC32XX_CLKPWR_SPICLK_USE_SPI2 0x20 -#define LPC32XX_CLKPWR_SPICLK_SPI2CLK_EN 0x10 -#define LPC32XX_CLKPWR_SPICLK_SET_SPI1DATIO 0x08 -#define LPC32XX_CLKPWR_SPICLK_SET_SPI1CLK 0x04 -#define LPC32XX_CLKPWR_SPICLK_USE_SPI1 0x02 -#define LPC32XX_CLKPWR_SPICLK_SPI1CLK_EN 0x01 - -/* - * clkpwr_nand_clk_ctrl register definitions - */ -#define LPC32XX_CLKPWR_NANDCLK_INTSEL_MLC 0x20 -#define LPC32XX_CLKPWR_NANDCLK_DMA_RNB 0x10 -#define LPC32XX_CLKPWR_NANDCLK_DMA_INT 0x08 -#define LPC32XX_CLKPWR_NANDCLK_SEL_SLC 0x04 -#define LPC32XX_CLKPWR_NANDCLK_MLCCLK_EN 0x02 -#define LPC32XX_CLKPWR_NANDCLK_SLCCLK_EN 0x01 - -/* - * clkpwr_uart3_clk_ctrl, clkpwr_uart4_clk_ctrl, clkpwr_uart5_clk_ctrl - * and clkpwr_uart6_clk_ctrl register definitions - */ -#define LPC32XX_CLKPWR_UART_Y_DIV(y) ((y) & 0xFF) -#define LPC32XX_CLKPWR_UART_X_DIV(x) (((x) & 0xFF) << 8) -#define LPC32XX_CLKPWR_UART_USE_HCLK _BIT(16) - -/* - * clkpwr_irda_clk_ctrl register definitions - */ -#define LPC32XX_CLKPWR_IRDA_Y_DIV(y) ((y) & 0xFF) -#define LPC32XX_CLKPWR_IRDA_X_DIV(x) (((x) & 0xFF) << 8) - -/* - * clkpwr_uart_clk_ctrl register definitions - */ -#define LPC32XX_CLKPWR_UARTCLKCTRL_UART6_EN _BIT(3) -#define LPC32XX_CLKPWR_UARTCLKCTRL_UART5_EN _BIT(2) -#define LPC32XX_CLKPWR_UARTCLKCTRL_UART4_EN _BIT(1) -#define LPC32XX_CLKPWR_UARTCLKCTRL_UART3_EN _BIT(0) - -/* - * clkpwr_dmaclk_ctrl register definitions - */ -#define LPC32XX_CLKPWR_DMACLKCTRL_CLK_EN 0x1 - -/* - * clkpwr_autoclock register definitions - */ -#define LPC32XX_CLKPWR_AUTOCLK_USB_EN 0x40 -#define LPC32XX_CLKPWR_AUTOCLK_IRAM_EN 0x02 -#define LPC32XX_CLKPWR_AUTOCLK_IROM_EN 0x01 - -/* - * Interrupt controller register offsets - */ -#define LPC32XX_INTC_MASK(x) io_p2v((x) + 0x00) -#define LPC32XX_INTC_RAW_STAT(x) io_p2v((x) + 0x04) -#define LPC32XX_INTC_STAT(x) io_p2v((x) + 0x08) -#define LPC32XX_INTC_POLAR(x) io_p2v((x) + 0x0C) -#define LPC32XX_INTC_ACT_TYPE(x) io_p2v((x) + 0x10) -#define LPC32XX_INTC_TYPE(x) io_p2v((x) + 0x14) - -/* - * Timer/counter register offsets - */ -#define LPC32XX_TIMER_IR(x) io_p2v((x) + 0x00) -#define LPC32XX_TIMER_TCR(x) io_p2v((x) + 0x04) -#define LPC32XX_TIMER_TC(x) io_p2v((x) + 0x08) -#define LPC32XX_TIMER_PR(x) io_p2v((x) + 0x0C) -#define LPC32XX_TIMER_PC(x) io_p2v((x) + 0x10) -#define LPC32XX_TIMER_MCR(x) io_p2v((x) + 0x14) -#define LPC32XX_TIMER_MR0(x) io_p2v((x) + 0x18) -#define LPC32XX_TIMER_MR1(x) io_p2v((x) + 0x1C) -#define LPC32XX_TIMER_MR2(x) io_p2v((x) + 0x20) -#define LPC32XX_TIMER_MR3(x) io_p2v((x) + 0x24) -#define LPC32XX_TIMER_CCR(x) io_p2v((x) + 0x28) -#define LPC32XX_TIMER_CR0(x) io_p2v((x) + 0x2C) -#define LPC32XX_TIMER_CR1(x) io_p2v((x) + 0x30) -#define LPC32XX_TIMER_CR2(x) io_p2v((x) + 0x34) -#define LPC32XX_TIMER_CR3(x) io_p2v((x) + 0x38) -#define LPC32XX_TIMER_EMR(x) io_p2v((x) + 0x3C) -#define LPC32XX_TIMER_CTCR(x) io_p2v((x) + 0x70) - -/* - * ir register definitions - */ -#define LPC32XX_TIMER_CNTR_MTCH_BIT(n) (1 << ((n) & 0x3)) -#define LPC32XX_TIMER_CNTR_CAPT_BIT(n) (1 << (4 + ((n) & 0x3))) - -/* - * tcr register definitions - */ -#define LPC32XX_TIMER_CNTR_TCR_EN 0x1 -#define LPC32XX_TIMER_CNTR_TCR_RESET 0x2 - -/* - * mcr register definitions - */ -#define LPC32XX_TIMER_CNTR_MCR_MTCH(n) (0x1 << ((n) * 3)) -#define LPC32XX_TIMER_CNTR_MCR_RESET(n) (0x1 << (((n) * 3) + 1)) -#define LPC32XX_TIMER_CNTR_MCR_STOP(n) (0x1 << (((n) * 3) + 2)) - -/* - * Standard UART register offsets - */ -#define LPC32XX_UART_DLL_FIFO(x) io_p2v((x) + 0x00) -#define LPC32XX_UART_DLM_IER(x) io_p2v((x) + 0x04) -#define LPC32XX_UART_IIR_FCR(x) io_p2v((x) + 0x08) -#define LPC32XX_UART_LCR(x) io_p2v((x) + 0x0C) -#define LPC32XX_UART_MODEM_CTRL(x) io_p2v((x) + 0x10) -#define LPC32XX_UART_LSR(x) io_p2v((x) + 0x14) -#define LPC32XX_UART_MODEM_STATUS(x) io_p2v((x) + 0x18) -#define LPC32XX_UART_RXLEV(x) io_p2v((x) + 0x1C) - -/* - * UART control structure offsets - */ -#define _UCREG(x) io_p2v(\ - LPC32XX_UART_CTRL_BASE + (x)) -#define LPC32XX_UARTCTL_CTRL _UCREG(0x00) -#define LPC32XX_UARTCTL_CLKMODE _UCREG(0x04) -#define LPC32XX_UARTCTL_CLOOP _UCREG(0x08) - -/* - * ctrl register definitions - */ -#define LPC32XX_UART_U3_MD_CTRL_EN _BIT(11) -#define LPC32XX_UART_IRRX6_INV_EN _BIT(10) -#define LPC32XX_UART_HDPX_EN _BIT(9) -#define LPC32XX_UART_UART6_IRDAMOD_BYPASS _BIT(5) -#define LPC32XX_RT_IRTX6_INV_EN _BIT(4) -#define LPC32XX_RT_IRTX6_INV_MIR_EN _BIT(3) -#define LPC32XX_RT_RX_IRPULSE_3_16_115K _BIT(2) -#define LPC32XX_RT_TX_IRPULSE_3_16_115K _BIT(1) -#define LPC32XX_UART_U5_ROUTE_TO_USB _BIT(0) - -/* - * clkmode register definitions - */ -#define LPC32XX_UART_ENABLED_CLOCKS(n) (((n) >> 16) & 0x7F) -#define LPC32XX_UART_ENABLED_CLOCK(n, u) (((n) >> (16 + (u))) & 0x1) -#define LPC32XX_UART_ENABLED_CLKS_ANY _BIT(14) -#define LPC32XX_UART_CLKMODE_OFF 0x0 -#define LPC32XX_UART_CLKMODE_ON 0x1 -#define LPC32XX_UART_CLKMODE_AUTO 0x2 -#define LPC32XX_UART_CLKMODE_MASK(u) (0x3 << ((((u) - 3) * 2) + 4)) -#define LPC32XX_UART_CLKMODE_LOAD(m, u) ((m) << ((((u) - 3) * 2) + 4)) - -/* - * GPIO Module Register offsets - */ -#define _GPREG(x) io_p2v(LPC32XX_GPIO_BASE + (x)) -#define LPC32XX_GPIO_P_MUX_SET _GPREG(0x100) -#define LPC32XX_GPIO_P_MUX_CLR _GPREG(0x104) -#define LPC32XX_GPIO_P_MUX_STATE _GPREG(0x108) -#define LPC32XX_GPIO_P3_MUX_SET _GPREG(0x110) -#define LPC32XX_GPIO_P3_MUX_CLR _GPREG(0x114) -#define LPC32XX_GPIO_P3_MUX_STATE _GPREG(0x118) -#define LPC32XX_GPIO_P0_MUX_SET _GPREG(0x120) -#define LPC32XX_GPIO_P0_MUX_CLR _GPREG(0x124) -#define LPC32XX_GPIO_P0_MUX_STATE _GPREG(0x128) -#define LPC32XX_GPIO_P1_MUX_SET _GPREG(0x130) -#define LPC32XX_GPIO_P1_MUX_CLR _GPREG(0x134) -#define LPC32XX_GPIO_P1_MUX_STATE _GPREG(0x138) -#define LPC32XX_GPIO_P2_MUX_SET _GPREG(0x028) -#define LPC32XX_GPIO_P2_MUX_CLR _GPREG(0x02C) -#define LPC32XX_GPIO_P2_MUX_STATE _GPREG(0x030) - -/* - * USB Otg Registers - */ -#define _OTGREG(x) io_p2v(LPC32XX_USB_OTG_BASE + (x)) -#define LPC32XX_USB_OTG_CLK_CTRL _OTGREG(0xFF4) -#define LPC32XX_USB_OTG_CLK_STAT _OTGREG(0xFF8) - -/* USB OTG CLK CTRL bit defines */ -#define LPC32XX_USB_OTG_AHB_M_CLOCK_ON _BIT(4) -#define LPC32XX_USB_OTG_OTG_CLOCK_ON _BIT(3) -#define LPC32XX_USB_OTG_I2C_CLOCK_ON _BIT(2) -#define LPC32XX_USB_OTG_DEV_CLOCK_ON _BIT(1) -#define LPC32XX_USB_OTG_HOST_CLOCK_ON _BIT(0) - -#endif diff --git a/arch/arm/mach-lpc32xx/include/mach/uncompress.h b/arch/arm/mach-lpc32xx/include/mach/uncompress.h index a568812a0b91..74b7aa0da0e4 100644 --- a/arch/arm/mach-lpc32xx/include/mach/uncompress.h +++ b/arch/arm/mach-lpc32xx/include/mach/uncompress.h @@ -12,15 +12,13 @@ #include -#include -#include - /* * Uncompress output is hardcoded to standard UART 5 */ #define UART_FIFO_CTL_TX_RESET (1 << 2) #define UART_STATUS_TX_MT (1 << 6) +#define LPC32XX_UART5_BASE 0x40090000 #define _UARTREG(x) (void __iomem *)(LPC32XX_UART5_BASE + (x)) diff --git a/arch/arm/mach-lpc32xx/lpc32xx.h b/arch/arm/mach-lpc32xx/lpc32xx.h new file mode 100644 index 000000000000..5eeb884a1993 --- /dev/null +++ b/arch/arm/mach-lpc32xx/lpc32xx.h @@ -0,0 +1,717 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * arch/arm/mach-lpc32xx/include/mach/platform.h + * + * Author: Kevin Wells + * + * Copyright (C) 2010 NXP Semiconductors + */ + +#ifndef __ARM_LPC32XX_H +#define __ARM_LPC32XX_H + +#define _SBF(f, v) ((v) << (f)) +#define _BIT(n) _SBF(n, 1) + +/* + * AHB 0 physical base addresses + */ +#define LPC32XX_SLC_BASE 0x20020000 +#define LPC32XX_SSP0_BASE 0x20084000 +#define LPC32XX_SPI1_BASE 0x20088000 +#define LPC32XX_SSP1_BASE 0x2008C000 +#define LPC32XX_SPI2_BASE 0x20090000 +#define LPC32XX_I2S0_BASE 0x20094000 +#define LPC32XX_SD_BASE 0x20098000 +#define LPC32XX_I2S1_BASE 0x2009C000 +#define LPC32XX_MLC_BASE 0x200A8000 +#define LPC32XX_AHB0_START LPC32XX_SLC_BASE +#define LPC32XX_AHB0_SIZE 0x00089000 + +/* + * AHB 1 physical base addresses + */ +#define LPC32XX_DMA_BASE 0x31000000 +#define LPC32XX_USB_BASE 0x31020000 +#define LPC32XX_USBH_BASE 0x31020000 +#define LPC32XX_USB_OTG_BASE 0x31020000 +#define LPC32XX_OTG_I2C_BASE 0x31020300 +#define LPC32XX_LCD_BASE 0x31040000 +#define LPC32XX_ETHERNET_BASE 0x31060000 +#define LPC32XX_EMC_BASE 0x31080000 +#define LPC32XX_ETB_CFG_BASE 0x310C0000 +#define LPC32XX_ETB_DATA_BASE 0x310E0000 +#define LPC32XX_AHB1_START LPC32XX_DMA_BASE +#define LPC32XX_AHB1_SIZE 0x000E1000 + +/* + * FAB physical base addresses + */ +#define LPC32XX_CLK_PM_BASE 0x40004000 +#define LPC32XX_MIC_BASE 0x40008000 +#define LPC32XX_SIC1_BASE 0x4000C000 +#define LPC32XX_SIC2_BASE 0x40010000 +#define LPC32XX_HS_UART1_BASE 0x40014000 +#define LPC32XX_HS_UART2_BASE 0x40018000 +#define LPC32XX_HS_UART7_BASE 0x4001C000 +#define LPC32XX_RTC_BASE 0x40024000 +#define LPC32XX_RTC_RAM_BASE 0x40024080 +#define LPC32XX_GPIO_BASE 0x40028000 +#define LPC32XX_PWM3_BASE 0x4002C000 +#define LPC32XX_PWM4_BASE 0x40030000 +#define LPC32XX_MSTIM_BASE 0x40034000 +#define LPC32XX_HSTIM_BASE 0x40038000 +#define LPC32XX_WDTIM_BASE 0x4003C000 +#define LPC32XX_DEBUG_CTRL_BASE 0x40040000 +#define LPC32XX_TIMER0_BASE 0x40044000 +#define LPC32XX_ADC_BASE 0x40048000 +#define LPC32XX_TIMER1_BASE 0x4004C000 +#define LPC32XX_KSCAN_BASE 0x40050000 +#define LPC32XX_UART_CTRL_BASE 0x40054000 +#define LPC32XX_TIMER2_BASE 0x40058000 +#define LPC32XX_PWM1_BASE 0x4005C000 +#define LPC32XX_PWM2_BASE 0x4005C004 +#define LPC32XX_TIMER3_BASE 0x40060000 + +/* + * APB physical base addresses + */ +#define LPC32XX_UART3_BASE 0x40080000 +#define LPC32XX_UART4_BASE 0x40088000 +#define LPC32XX_UART5_BASE 0x40090000 +#define LPC32XX_UART6_BASE 0x40098000 +#define LPC32XX_I2C1_BASE 0x400A0000 +#define LPC32XX_I2C2_BASE 0x400A8000 + +/* + * FAB and APB base and sizing + */ +#define LPC32XX_FABAPB_START LPC32XX_CLK_PM_BASE +#define LPC32XX_FABAPB_SIZE 0x000A5000 + +/* + * Internal memory bases and sizes + */ +#define LPC32XX_IRAM_BASE 0x08000000 +#define LPC32XX_IROM_BASE 0x0C000000 + +/* + * External Static Memory Bank Address Space Bases + */ +#define LPC32XX_EMC_CS0_BASE 0xE0000000 +#define LPC32XX_EMC_CS1_BASE 0xE1000000 +#define LPC32XX_EMC_CS2_BASE 0xE2000000 +#define LPC32XX_EMC_CS3_BASE 0xE3000000 + +/* + * External SDRAM Memory Bank Address Space Bases + */ +#define LPC32XX_EMC_DYCS0_BASE 0x80000000 +#define LPC32XX_EMC_DYCS1_BASE 0xA0000000 + +/* + * Clock and crystal information + */ +#define LPC32XX_MAIN_OSC_FREQ 13000000 +#define LPC32XX_CLOCK_OSC_FREQ 32768 + +/* + * Clock and Power control register offsets + */ +#define _PMREG(x) io_p2v(LPC32XX_CLK_PM_BASE +\ + (x)) +#define LPC32XX_CLKPWR_DEBUG_CTRL _PMREG(0x000) +#define LPC32XX_CLKPWR_BOOTMAP _PMREG(0x014) +#define LPC32XX_CLKPWR_P01_ER _PMREG(0x018) +#define LPC32XX_CLKPWR_USBCLK_PDIV _PMREG(0x01C) +#define LPC32XX_CLKPWR_INT_ER _PMREG(0x020) +#define LPC32XX_CLKPWR_INT_RS _PMREG(0x024) +#define LPC32XX_CLKPWR_INT_SR _PMREG(0x028) +#define LPC32XX_CLKPWR_INT_AP _PMREG(0x02C) +#define LPC32XX_CLKPWR_PIN_ER _PMREG(0x030) +#define LPC32XX_CLKPWR_PIN_RS _PMREG(0x034) +#define LPC32XX_CLKPWR_PIN_SR _PMREG(0x038) +#define LPC32XX_CLKPWR_PIN_AP _PMREG(0x03C) +#define LPC32XX_CLKPWR_HCLK_DIV _PMREG(0x040) +#define LPC32XX_CLKPWR_PWR_CTRL _PMREG(0x044) +#define LPC32XX_CLKPWR_PLL397_CTRL _PMREG(0x048) +#define LPC32XX_CLKPWR_MAIN_OSC_CTRL _PMREG(0x04C) +#define LPC32XX_CLKPWR_SYSCLK_CTRL _PMREG(0x050) +#define LPC32XX_CLKPWR_LCDCLK_CTRL _PMREG(0x054) +#define LPC32XX_CLKPWR_HCLKPLL_CTRL _PMREG(0x058) +#define LPC32XX_CLKPWR_ADC_CLK_CTRL_1 _PMREG(0x060) +#define LPC32XX_CLKPWR_USB_CTRL _PMREG(0x064) +#define LPC32XX_CLKPWR_SDRAMCLK_CTRL _PMREG(0x068) +#define LPC32XX_CLKPWR_DDR_LAP_NOM _PMREG(0x06C) +#define LPC32XX_CLKPWR_DDR_LAP_COUNT _PMREG(0x070) +#define LPC32XX_CLKPWR_DDR_LAP_DELAY _PMREG(0x074) +#define LPC32XX_CLKPWR_SSP_CLK_CTRL _PMREG(0x078) +#define LPC32XX_CLKPWR_I2S_CLK_CTRL _PMREG(0x07C) +#define LPC32XX_CLKPWR_MS_CTRL _PMREG(0x080) +#define LPC32XX_CLKPWR_MACCLK_CTRL _PMREG(0x090) +#define LPC32XX_CLKPWR_TEST_CLK_SEL _PMREG(0x0A4) +#define LPC32XX_CLKPWR_SFW_INT _PMREG(0x0A8) +#define LPC32XX_CLKPWR_I2C_CLK_CTRL _PMREG(0x0AC) +#define LPC32XX_CLKPWR_KEY_CLK_CTRL _PMREG(0x0B0) +#define LPC32XX_CLKPWR_ADC_CLK_CTRL _PMREG(0x0B4) +#define LPC32XX_CLKPWR_PWM_CLK_CTRL _PMREG(0x0B8) +#define LPC32XX_CLKPWR_TIMER_CLK_CTRL _PMREG(0x0BC) +#define LPC32XX_CLKPWR_TIMERS_PWMS_CLK_CTRL_1 _PMREG(0x0C0) +#define LPC32XX_CLKPWR_SPI_CLK_CTRL _PMREG(0x0C4) +#define LPC32XX_CLKPWR_NAND_CLK_CTRL _PMREG(0x0C8) +#define LPC32XX_CLKPWR_UART3_CLK_CTRL _PMREG(0x0D0) +#define LPC32XX_CLKPWR_UART4_CLK_CTRL _PMREG(0x0D4) +#define LPC32XX_CLKPWR_UART5_CLK_CTRL _PMREG(0x0D8) +#define LPC32XX_CLKPWR_UART6_CLK_CTRL _PMREG(0x0DC) +#define LPC32XX_CLKPWR_IRDA_CLK_CTRL _PMREG(0x0E0) +#define LPC32XX_CLKPWR_UART_CLK_CTRL _PMREG(0x0E4) +#define LPC32XX_CLKPWR_DMA_CLK_CTRL _PMREG(0x0E8) +#define LPC32XX_CLKPWR_AUTOCLOCK _PMREG(0x0EC) +#define LPC32XX_CLKPWR_DEVID(x) _PMREG(0x130 + (x)) + +/* + * clkpwr_debug_ctrl register definitions +*/ +#define LPC32XX_CLKPWR_VFP_CLOCK_ENABLE_BIT _BIT(4) + +/* + * clkpwr_bootmap register definitions + */ +#define LPC32XX_CLKPWR_BOOTMAP_SEL_BIT _BIT(1) + +/* + * clkpwr_start_gpio register bit definitions + */ +#define LPC32XX_CLKPWR_GPIOSRC_P1IO23_BIT _BIT(31) +#define LPC32XX_CLKPWR_GPIOSRC_P1IO22_BIT _BIT(30) +#define LPC32XX_CLKPWR_GPIOSRC_P1IO21_BIT _BIT(29) +#define LPC32XX_CLKPWR_GPIOSRC_P1IO20_BIT _BIT(28) +#define LPC32XX_CLKPWR_GPIOSRC_P1IO19_BIT _BIT(27) +#define LPC32XX_CLKPWR_GPIOSRC_P1IO18_BIT _BIT(26) +#define LPC32XX_CLKPWR_GPIOSRC_P1IO17_BIT _BIT(25) +#define LPC32XX_CLKPWR_GPIOSRC_P1IO16_BIT _BIT(24) +#define LPC32XX_CLKPWR_GPIOSRC_P1IO15_BIT _BIT(23) +#define LPC32XX_CLKPWR_GPIOSRC_P1IO14_BIT _BIT(22) +#define LPC32XX_CLKPWR_GPIOSRC_P1IO13_BIT _BIT(21) +#define LPC32XX_CLKPWR_GPIOSRC_P1IO12_BIT _BIT(20) +#define LPC32XX_CLKPWR_GPIOSRC_P1IO11_BIT _BIT(19) +#define LPC32XX_CLKPWR_GPIOSRC_P1IO10_BIT _BIT(18) +#define LPC32XX_CLKPWR_GPIOSRC_P1IO9_BIT _BIT(17) +#define LPC32XX_CLKPWR_GPIOSRC_P1IO8_BIT _BIT(16) +#define LPC32XX_CLKPWR_GPIOSRC_P1IO7_BIT _BIT(15) +#define LPC32XX_CLKPWR_GPIOSRC_P1IO6_BIT _BIT(14) +#define LPC32XX_CLKPWR_GPIOSRC_P1IO5_BIT _BIT(13) +#define LPC32XX_CLKPWR_GPIOSRC_P1IO4_BIT _BIT(12) +#define LPC32XX_CLKPWR_GPIOSRC_P1IO3_BIT _BIT(11) +#define LPC32XX_CLKPWR_GPIOSRC_P1IO2_BIT _BIT(10) +#define LPC32XX_CLKPWR_GPIOSRC_P1IO1_BIT _BIT(9) +#define LPC32XX_CLKPWR_GPIOSRC_P1IO0_BIT _BIT(8) +#define LPC32XX_CLKPWR_GPIOSRC_P0IO7_BIT _BIT(7) +#define LPC32XX_CLKPWR_GPIOSRC_P0IO6_BIT _BIT(6) +#define LPC32XX_CLKPWR_GPIOSRC_P0IO5_BIT _BIT(5) +#define LPC32XX_CLKPWR_GPIOSRC_P0IO4_BIT _BIT(4) +#define LPC32XX_CLKPWR_GPIOSRC_P0IO3_BIT _BIT(3) +#define LPC32XX_CLKPWR_GPIOSRC_P0IO2_BIT _BIT(2) +#define LPC32XX_CLKPWR_GPIOSRC_P0IO1_BIT _BIT(1) +#define LPC32XX_CLKPWR_GPIOSRC_P0IO0_BIT _BIT(0) + +/* + * clkpwr_usbclk_pdiv register definitions + */ +#define LPC32XX_CLKPWR_USBPDIV_PLL_MASK 0xF + +/* + * clkpwr_start_int, clkpwr_start_raw_sts_int, clkpwr_start_sts_int, + * clkpwr_start_pol_int, register bit definitions + */ +#define LPC32XX_CLKPWR_INTSRC_ADC_BIT _BIT(31) +#define LPC32XX_CLKPWR_INTSRC_TS_P_BIT _BIT(30) +#define LPC32XX_CLKPWR_INTSRC_TS_AUX_BIT _BIT(29) +#define LPC32XX_CLKPWR_INTSRC_USBAHNEEDCLK_BIT _BIT(26) +#define LPC32XX_CLKPWR_INTSRC_MSTIMER_BIT _BIT(25) +#define LPC32XX_CLKPWR_INTSRC_RTC_BIT _BIT(24) +#define LPC32XX_CLKPWR_INTSRC_USBNEEDCLK_BIT _BIT(23) +#define LPC32XX_CLKPWR_INTSRC_USB_BIT _BIT(22) +#define LPC32XX_CLKPWR_INTSRC_I2C_BIT _BIT(21) +#define LPC32XX_CLKPWR_INTSRC_USBOTGTIMER_BIT _BIT(20) +#define LPC32XX_CLKPWR_INTSRC_USBATXINT_BIT _BIT(19) +#define LPC32XX_CLKPWR_INTSRC_KEY_BIT _BIT(16) +#define LPC32XX_CLKPWR_INTSRC_MAC_BIT _BIT(7) +#define LPC32XX_CLKPWR_INTSRC_P0P1_BIT _BIT(6) +#define LPC32XX_CLKPWR_INTSRC_GPIO_05_BIT _BIT(5) +#define LPC32XX_CLKPWR_INTSRC_GPIO_04_BIT _BIT(4) +#define LPC32XX_CLKPWR_INTSRC_GPIO_03_BIT _BIT(3) +#define LPC32XX_CLKPWR_INTSRC_GPIO_02_BIT _BIT(2) +#define LPC32XX_CLKPWR_INTSRC_GPIO_01_BIT _BIT(1) +#define LPC32XX_CLKPWR_INTSRC_GPIO_00_BIT _BIT(0) + +/* + * clkpwr_start_pin, clkpwr_start_raw_sts_pin, clkpwr_start_sts_pin, + * clkpwr_start_pol_pin register bit definitions + */ +#define LPC32XX_CLKPWR_EXTSRC_U7_RX_BIT _BIT(31) +#define LPC32XX_CLKPWR_EXTSRC_U7_HCTS_BIT _BIT(30) +#define LPC32XX_CLKPWR_EXTSRC_U6_IRRX_BIT _BIT(28) +#define LPC32XX_CLKPWR_EXTSRC_U5_RX_BIT _BIT(26) +#define LPC32XX_CLKPWR_EXTSRC_GPI_28_BIT _BIT(25) +#define LPC32XX_CLKPWR_EXTSRC_U3_RX_BIT _BIT(24) +#define LPC32XX_CLKPWR_EXTSRC_U2_HCTS_BIT _BIT(23) +#define LPC32XX_CLKPWR_EXTSRC_U2_RX_BIT _BIT(22) +#define LPC32XX_CLKPWR_EXTSRC_U1_RX_BIT _BIT(21) +#define LPC32XX_CLKPWR_EXTSRC_MSDIO_INT_BIT _BIT(18) +#define LPC32XX_CLKPWR_EXTSRC_MSDIO_SRT_BIT _BIT(17) +#define LPC32XX_CLKPWR_EXTSRC_GPI_06_BIT _BIT(16) +#define LPC32XX_CLKPWR_EXTSRC_GPI_05_BIT _BIT(15) +#define LPC32XX_CLKPWR_EXTSRC_GPI_04_BIT _BIT(14) +#define LPC32XX_CLKPWR_EXTSRC_GPI_03_BIT _BIT(13) +#define LPC32XX_CLKPWR_EXTSRC_GPI_02_BIT _BIT(12) +#define LPC32XX_CLKPWR_EXTSRC_GPI_01_BIT _BIT(11) +#define LPC32XX_CLKPWR_EXTSRC_GPI_00_BIT _BIT(10) +#define LPC32XX_CLKPWR_EXTSRC_SYSCLKEN_BIT _BIT(9) +#define LPC32XX_CLKPWR_EXTSRC_SPI1_DATIN_BIT _BIT(8) +#define LPC32XX_CLKPWR_EXTSRC_GPI_07_BIT _BIT(7) +#define LPC32XX_CLKPWR_EXTSRC_SPI2_DATIN_BIT _BIT(6) +#define LPC32XX_CLKPWR_EXTSRC_GPI_19_BIT _BIT(5) +#define LPC32XX_CLKPWR_EXTSRC_GPI_09_BIT _BIT(4) +#define LPC32XX_CLKPWR_EXTSRC_GPI_08_BIT _BIT(3) + +/* + * clkpwr_hclk_div register definitions + */ +#define LPC32XX_CLKPWR_HCLKDIV_DDRCLK_STOP (0x0 << 7) +#define LPC32XX_CLKPWR_HCLKDIV_DDRCLK_NORM (0x1 << 7) +#define LPC32XX_CLKPWR_HCLKDIV_DDRCLK_HALF (0x2 << 7) +#define LPC32XX_CLKPWR_HCLKDIV_PCLK_DIV(n) (((n) & 0x1F) << 2) +#define LPC32XX_CLKPWR_HCLKDIV_DIV_2POW(n) ((n) & 0x3) + +/* + * clkpwr_pwr_ctrl register definitions + */ +#define LPC32XX_CLKPWR_CTRL_FORCE_PCLK _BIT(10) +#define LPC32XX_CLKPWR_SDRAM_SELF_RFSH _BIT(9) +#define LPC32XX_CLKPWR_UPD_SDRAM_SELF_RFSH _BIT(8) +#define LPC32XX_CLKPWR_AUTO_SDRAM_SELF_RFSH _BIT(7) +#define LPC32XX_CLKPWR_HIGHCORE_STATE_BIT _BIT(5) +#define LPC32XX_CLKPWR_SYSCLKEN_STATE_BIT _BIT(4) +#define LPC32XX_CLKPWR_SYSCLKEN_GPIO_EN _BIT(3) +#define LPC32XX_CLKPWR_SELECT_RUN_MODE _BIT(2) +#define LPC32XX_CLKPWR_HIGHCORE_GPIO_EN _BIT(1) +#define LPC32XX_CLKPWR_STOP_MODE_CTRL _BIT(0) + +/* + * clkpwr_pll397_ctrl register definitions + */ +#define LPC32XX_CLKPWR_PLL397_MSLOCK_STS _BIT(10) +#define LPC32XX_CLKPWR_PLL397_BYPASS _BIT(9) +#define LPC32XX_CLKPWR_PLL397_BIAS_NORM 0x000 +#define LPC32XX_CLKPWR_PLL397_BIAS_N12_5 0x040 +#define LPC32XX_CLKPWR_PLL397_BIAS_N25 0x080 +#define LPC32XX_CLKPWR_PLL397_BIAS_N37_5 0x0C0 +#define LPC32XX_CLKPWR_PLL397_BIAS_P12_5 0x100 +#define LPC32XX_CLKPWR_PLL397_BIAS_P25 0x140 +#define LPC32XX_CLKPWR_PLL397_BIAS_P37_5 0x180 +#define LPC32XX_CLKPWR_PLL397_BIAS_P50 0x1C0 +#define LPC32XX_CLKPWR_PLL397_BIAS_MASK 0x1C0 +#define LPC32XX_CLKPWR_SYSCTRL_PLL397_DIS _BIT(1) +#define LPC32XX_CLKPWR_SYSCTRL_PLL397_STS _BIT(0) + +/* + * clkpwr_main_osc_ctrl register definitions + */ +#define LPC32XX_CLKPWR_MOSC_ADD_CAP(n) (((n) & 0x7F) << 2) +#define LPC32XX_CLKPWR_MOSC_CAP_MASK (0x7F << 2) +#define LPC32XX_CLKPWR_TEST_MODE _BIT(1) +#define LPC32XX_CLKPWR_MOSC_DISABLE _BIT(0) + +/* + * clkpwr_sysclk_ctrl register definitions + */ +#define LPC32XX_CLKPWR_SYSCTRL_BP_TRIG(n) (((n) & 0x3FF) << 2) +#define LPC32XX_CLKPWR_SYSCTRL_BP_MASK (0x3FF << 2) +#define LPC32XX_CLKPWR_SYSCTRL_USEPLL397 _BIT(1) +#define LPC32XX_CLKPWR_SYSCTRL_SYSCLKMUX _BIT(0) + +/* + * clkpwr_lcdclk_ctrl register definitions + */ +#define LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_TFT12 0x000 +#define LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_TFT16 0x040 +#define LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_TFT15 0x080 +#define LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_TFT24 0x0C0 +#define LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_STN4M 0x100 +#define LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_STN8C 0x140 +#define LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_DSTN4M 0x180 +#define LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_DSTN8C 0x1C0 +#define LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_MSK 0x01C0 +#define LPC32XX_CLKPWR_LCDCTRL_CLK_EN 0x020 +#define LPC32XX_CLKPWR_LCDCTRL_SET_PSCALE(n) ((n - 1) & 0x1F) +#define LPC32XX_CLKPWR_LCDCTRL_PSCALE_MSK 0x001F + +/* + * clkpwr_hclkpll_ctrl register definitions + */ +#define LPC32XX_CLKPWR_HCLKPLL_POWER_UP _BIT(16) +#define LPC32XX_CLKPWR_HCLKPLL_CCO_BYPASS _BIT(15) +#define LPC32XX_CLKPWR_HCLKPLL_POSTDIV_BYPASS _BIT(14) +#define LPC32XX_CLKPWR_HCLKPLL_FDBK_SEL_FCLK _BIT(13) +#define LPC32XX_CLKPWR_HCLKPLL_POSTDIV_2POW(n) (((n) & 0x3) << 11) +#define LPC32XX_CLKPWR_HCLKPLL_PREDIV_PLUS1(n) (((n) & 0x3) << 9) +#define LPC32XX_CLKPWR_HCLKPLL_PLLM(n) (((n) & 0xFF) << 1) +#define LPC32XX_CLKPWR_HCLKPLL_PLL_STS _BIT(0) + +/* + * clkpwr_adc_clk_ctrl_1 register definitions + */ +#define LPC32XX_CLKPWR_ADCCTRL1_RTDIV(n) (((n) & 0xFF) << 0) +#define LPC32XX_CLKPWR_ADCCTRL1_PCLK_SEL _BIT(8) + +/* + * clkpwr_usb_ctrl register definitions + */ +#define LPC32XX_CLKPWR_USBCTRL_HCLK_EN _BIT(24) +#define LPC32XX_CLKPWR_USBCTRL_USBI2C_EN _BIT(23) +#define LPC32XX_CLKPWR_USBCTRL_USBDVND_EN _BIT(22) +#define LPC32XX_CLKPWR_USBCTRL_USBHSTND_EN _BIT(21) +#define LPC32XX_CLKPWR_USBCTRL_PU_ADD (0x0 << 19) +#define LPC32XX_CLKPWR_USBCTRL_BUS_KEEPER (0x1 << 19) +#define LPC32XX_CLKPWR_USBCTRL_PD_ADD (0x3 << 19) +#define LPC32XX_CLKPWR_USBCTRL_CLK_EN2 _BIT(18) +#define LPC32XX_CLKPWR_USBCTRL_CLK_EN1 _BIT(17) +#define LPC32XX_CLKPWR_USBCTRL_PLL_PWRUP _BIT(16) +#define LPC32XX_CLKPWR_USBCTRL_CCO_BYPASS _BIT(15) +#define LPC32XX_CLKPWR_USBCTRL_POSTDIV_BYPASS _BIT(14) +#define LPC32XX_CLKPWR_USBCTRL_FDBK_SEL_FCLK _BIT(13) +#define LPC32XX_CLKPWR_USBCTRL_POSTDIV_2POW(n) (((n) & 0x3) << 11) +#define LPC32XX_CLKPWR_USBCTRL_PREDIV_PLUS1(n) (((n) & 0x3) << 9) +#define LPC32XX_CLKPWR_USBCTRL_FDBK_PLUS1(n) (((n) & 0xFF) << 1) +#define LPC32XX_CLKPWR_USBCTRL_PLL_STS _BIT(0) + +/* + * clkpwr_sdramclk_ctrl register definitions + */ +#define LPC32XX_CLKPWR_SDRCLK_FASTSLEW_CLK _BIT(22) +#define LPC32XX_CLKPWR_SDRCLK_FASTSLEW _BIT(21) +#define LPC32XX_CLKPWR_SDRCLK_FASTSLEW_DAT _BIT(20) +#define LPC32XX_CLKPWR_SDRCLK_SW_DDR_RESET _BIT(19) +#define LPC32XX_CLKPWR_SDRCLK_HCLK_DLY(n) (((n) & 0x1F) << 14) +#define LPC32XX_CLKPWR_SDRCLK_DLY_ADDR_STS _BIT(13) +#define LPC32XX_CLKPWR_SDRCLK_SENS_FACT(n) (((n) & 0x7) << 10) +#define LPC32XX_CLKPWR_SDRCLK_USE_CAL _BIT(9) +#define LPC32XX_CLKPWR_SDRCLK_DO_CAL _BIT(8) +#define LPC32XX_CLKPWR_SDRCLK_CAL_ON_RTC _BIT(7) +#define LPC32XX_CLKPWR_SDRCLK_DQS_DLY(n) (((n) & 0x1F) << 2) +#define LPC32XX_CLKPWR_SDRCLK_USE_DDR _BIT(1) +#define LPC32XX_CLKPWR_SDRCLK_CLK_DIS _BIT(0) + +/* + * clkpwr_ssp_blk_ctrl register definitions + */ +#define LPC32XX_CLKPWR_SSPCTRL_DMA_SSP1RX _BIT(5) +#define LPC32XX_CLKPWR_SSPCTRL_DMA_SSP1TX _BIT(4) +#define LPC32XX_CLKPWR_SSPCTRL_DMA_SSP0RX _BIT(3) +#define LPC32XX_CLKPWR_SSPCTRL_DMA_SSP0TX _BIT(2) +#define LPC32XX_CLKPWR_SSPCTRL_SSPCLK1_EN _BIT(1) +#define LPC32XX_CLKPWR_SSPCTRL_SSPCLK0_EN _BIT(0) + +/* + * clkpwr_i2s_clk_ctrl register definitions + */ +#define LPC32XX_CLKPWR_I2SCTRL_I2S1_RX_FOR_TX _BIT(6) +#define LPC32XX_CLKPWR_I2SCTRL_I2S1_TX_FOR_RX _BIT(5) +#define LPC32XX_CLKPWR_I2SCTRL_I2S1_USE_DMA _BIT(4) +#define LPC32XX_CLKPWR_I2SCTRL_I2S0_RX_FOR_TX _BIT(3) +#define LPC32XX_CLKPWR_I2SCTRL_I2S0_TX_FOR_RX _BIT(2) +#define LPC32XX_CLKPWR_I2SCTRL_I2SCLK1_EN _BIT(1) +#define LPC32XX_CLKPWR_I2SCTRL_I2SCLK0_EN _BIT(0) + +/* + * clkpwr_ms_ctrl register definitions + */ +#define LPC32XX_CLKPWR_MSCARD_MSDIO_PIN_DIS _BIT(10) +#define LPC32XX_CLKPWR_MSCARD_MSDIO_PU_EN _BIT(9) +#define LPC32XX_CLKPWR_MSCARD_MSDIO23_DIS _BIT(8) +#define LPC32XX_CLKPWR_MSCARD_MSDIO1_DIS _BIT(7) +#define LPC32XX_CLKPWR_MSCARD_MSDIO0_DIS _BIT(6) +#define LPC32XX_CLKPWR_MSCARD_SDCARD_EN _BIT(5) +#define LPC32XX_CLKPWR_MSCARD_SDCARD_DIV(n) ((n) & 0xF) + +/* + * clkpwr_macclk_ctrl register definitions + */ +#define LPC32XX_CLKPWR_MACCTRL_NO_ENET_PIS 0x00 +#define LPC32XX_CLKPWR_MACCTRL_USE_MII_PINS 0x08 +#define LPC32XX_CLKPWR_MACCTRL_USE_RMII_PINS 0x18 +#define LPC32XX_CLKPWR_MACCTRL_PINS_MSK 0x18 +#define LPC32XX_CLKPWR_MACCTRL_DMACLK_EN _BIT(2) +#define LPC32XX_CLKPWR_MACCTRL_MMIOCLK_EN _BIT(1) +#define LPC32XX_CLKPWR_MACCTRL_HRCCLK_EN _BIT(0) + +/* + * clkpwr_test_clk_sel register definitions + */ +#define LPC32XX_CLKPWR_TESTCLK1_SEL_PERCLK (0x0 << 5) +#define LPC32XX_CLKPWR_TESTCLK1_SEL_RTC (0x1 << 5) +#define LPC32XX_CLKPWR_TESTCLK1_SEL_MOSC (0x2 << 5) +#define LPC32XX_CLKPWR_TESTCLK1_SEL_MASK (0x3 << 5) +#define LPC32XX_CLKPWR_TESTCLK_TESTCLK1_EN _BIT(4) +#define LPC32XX_CLKPWR_TESTCLK2_SEL_HCLK (0x0 << 1) +#define LPC32XX_CLKPWR_TESTCLK2_SEL_PERCLK (0x1 << 1) +#define LPC32XX_CLKPWR_TESTCLK2_SEL_USBCLK (0x2 << 1) +#define LPC32XX_CLKPWR_TESTCLK2_SEL_MOSC (0x5 << 1) +#define LPC32XX_CLKPWR_TESTCLK2_SEL_PLL397 (0x7 << 1) +#define LPC32XX_CLKPWR_TESTCLK2_SEL_MASK (0x7 << 1) +#define LPC32XX_CLKPWR_TESTCLK_TESTCLK2_EN _BIT(0) + +/* + * clkpwr_sw_int register definitions + */ +#define LPC32XX_CLKPWR_SW_INT(n) (_BIT(0) | (((n) & 0x7F) << 1)) +#define LPC32XX_CLKPWR_SW_GET_ARG(n) (((n) & 0xFE) >> 1) + +/* + * clkpwr_i2c_clk_ctrl register definitions + */ +#define LPC32XX_CLKPWR_I2CCLK_USBI2CHI_DRIVE _BIT(4) +#define LPC32XX_CLKPWR_I2CCLK_I2C2HI_DRIVE _BIT(3) +#define LPC32XX_CLKPWR_I2CCLK_I2C1HI_DRIVE _BIT(2) +#define LPC32XX_CLKPWR_I2CCLK_I2C2CLK_EN _BIT(1) +#define LPC32XX_CLKPWR_I2CCLK_I2C1CLK_EN _BIT(0) + +/* + * clkpwr_key_clk_ctrl register definitions + */ +#define LPC32XX_CLKPWR_KEYCLKCTRL_CLK_EN 0x1 + +/* + * clkpwr_adc_clk_ctrl register definitions + */ +#define LPC32XX_CLKPWR_ADC32CLKCTRL_CLK_EN 0x1 + +/* + * clkpwr_pwm_clk_ctrl register definitions + */ +#define LPC32XX_CLKPWR_PWMCLK_PWM2_DIV(n) (((n) & 0xF) << 8) +#define LPC32XX_CLKPWR_PWMCLK_PWM1_DIV(n) (((n) & 0xF) << 4) +#define LPC32XX_CLKPWR_PWMCLK_PWM2SEL_PCLK 0x8 +#define LPC32XX_CLKPWR_PWMCLK_PWM2CLK_EN 0x4 +#define LPC32XX_CLKPWR_PWMCLK_PWM1SEL_PCLK 0x2 +#define LPC32XX_CLKPWR_PWMCLK_PWM1CLK_EN 0x1 + +/* + * clkpwr_timer_clk_ctrl register definitions + */ +#define LPC32XX_CLKPWR_PWMCLK_HSTIMER_EN 0x2 +#define LPC32XX_CLKPWR_PWMCLK_WDOG_EN 0x1 + +/* + * clkpwr_timers_pwms_clk_ctrl_1 register definitions + */ +#define LPC32XX_CLKPWR_TMRPWMCLK_MPWM_EN 0x40 +#define LPC32XX_CLKPWR_TMRPWMCLK_TIMER3_EN 0x20 +#define LPC32XX_CLKPWR_TMRPWMCLK_TIMER2_EN 0x10 +#define LPC32XX_CLKPWR_TMRPWMCLK_TIMER1_EN 0x08 +#define LPC32XX_CLKPWR_TMRPWMCLK_TIMER0_EN 0x04 +#define LPC32XX_CLKPWR_TMRPWMCLK_PWM4_EN 0x02 +#define LPC32XX_CLKPWR_TMRPWMCLK_PWM3_EN 0x01 + +/* + * clkpwr_spi_clk_ctrl register definitions + */ +#define LPC32XX_CLKPWR_SPICLK_SET_SPI2DATIO 0x80 +#define LPC32XX_CLKPWR_SPICLK_SET_SPI2CLK 0x40 +#define LPC32XX_CLKPWR_SPICLK_USE_SPI2 0x20 +#define LPC32XX_CLKPWR_SPICLK_SPI2CLK_EN 0x10 +#define LPC32XX_CLKPWR_SPICLK_SET_SPI1DATIO 0x08 +#define LPC32XX_CLKPWR_SPICLK_SET_SPI1CLK 0x04 +#define LPC32XX_CLKPWR_SPICLK_USE_SPI1 0x02 +#define LPC32XX_CLKPWR_SPICLK_SPI1CLK_EN 0x01 + +/* + * clkpwr_nand_clk_ctrl register definitions + */ +#define LPC32XX_CLKPWR_NANDCLK_INTSEL_MLC 0x20 +#define LPC32XX_CLKPWR_NANDCLK_DMA_RNB 0x10 +#define LPC32XX_CLKPWR_NANDCLK_DMA_INT 0x08 +#define LPC32XX_CLKPWR_NANDCLK_SEL_SLC 0x04 +#define LPC32XX_CLKPWR_NANDCLK_MLCCLK_EN 0x02 +#define LPC32XX_CLKPWR_NANDCLK_SLCCLK_EN 0x01 + +/* + * clkpwr_uart3_clk_ctrl, clkpwr_uart4_clk_ctrl, clkpwr_uart5_clk_ctrl + * and clkpwr_uart6_clk_ctrl register definitions + */ +#define LPC32XX_CLKPWR_UART_Y_DIV(y) ((y) & 0xFF) +#define LPC32XX_CLKPWR_UART_X_DIV(x) (((x) & 0xFF) << 8) +#define LPC32XX_CLKPWR_UART_USE_HCLK _BIT(16) + +/* + * clkpwr_irda_clk_ctrl register definitions + */ +#define LPC32XX_CLKPWR_IRDA_Y_DIV(y) ((y) & 0xFF) +#define LPC32XX_CLKPWR_IRDA_X_DIV(x) (((x) & 0xFF) << 8) + +/* + * clkpwr_uart_clk_ctrl register definitions + */ +#define LPC32XX_CLKPWR_UARTCLKCTRL_UART6_EN _BIT(3) +#define LPC32XX_CLKPWR_UARTCLKCTRL_UART5_EN _BIT(2) +#define LPC32XX_CLKPWR_UARTCLKCTRL_UART4_EN _BIT(1) +#define LPC32XX_CLKPWR_UARTCLKCTRL_UART3_EN _BIT(0) + +/* + * clkpwr_dmaclk_ctrl register definitions + */ +#define LPC32XX_CLKPWR_DMACLKCTRL_CLK_EN 0x1 + +/* + * clkpwr_autoclock register definitions + */ +#define LPC32XX_CLKPWR_AUTOCLK_USB_EN 0x40 +#define LPC32XX_CLKPWR_AUTOCLK_IRAM_EN 0x02 +#define LPC32XX_CLKPWR_AUTOCLK_IROM_EN 0x01 + +/* + * Interrupt controller register offsets + */ +#define LPC32XX_INTC_MASK(x) io_p2v((x) + 0x00) +#define LPC32XX_INTC_RAW_STAT(x) io_p2v((x) + 0x04) +#define LPC32XX_INTC_STAT(x) io_p2v((x) + 0x08) +#define LPC32XX_INTC_POLAR(x) io_p2v((x) + 0x0C) +#define LPC32XX_INTC_ACT_TYPE(x) io_p2v((x) + 0x10) +#define LPC32XX_INTC_TYPE(x) io_p2v((x) + 0x14) + +/* + * Timer/counter register offsets + */ +#define LPC32XX_TIMER_IR(x) io_p2v((x) + 0x00) +#define LPC32XX_TIMER_TCR(x) io_p2v((x) + 0x04) +#define LPC32XX_TIMER_TC(x) io_p2v((x) + 0x08) +#define LPC32XX_TIMER_PR(x) io_p2v((x) + 0x0C) +#define LPC32XX_TIMER_PC(x) io_p2v((x) + 0x10) +#define LPC32XX_TIMER_MCR(x) io_p2v((x) + 0x14) +#define LPC32XX_TIMER_MR0(x) io_p2v((x) + 0x18) +#define LPC32XX_TIMER_MR1(x) io_p2v((x) + 0x1C) +#define LPC32XX_TIMER_MR2(x) io_p2v((x) + 0x20) +#define LPC32XX_TIMER_MR3(x) io_p2v((x) + 0x24) +#define LPC32XX_TIMER_CCR(x) io_p2v((x) + 0x28) +#define LPC32XX_TIMER_CR0(x) io_p2v((x) + 0x2C) +#define LPC32XX_TIMER_CR1(x) io_p2v((x) + 0x30) +#define LPC32XX_TIMER_CR2(x) io_p2v((x) + 0x34) +#define LPC32XX_TIMER_CR3(x) io_p2v((x) + 0x38) +#define LPC32XX_TIMER_EMR(x) io_p2v((x) + 0x3C) +#define LPC32XX_TIMER_CTCR(x) io_p2v((x) + 0x70) + +/* + * ir register definitions + */ +#define LPC32XX_TIMER_CNTR_MTCH_BIT(n) (1 << ((n) & 0x3)) +#define LPC32XX_TIMER_CNTR_CAPT_BIT(n) (1 << (4 + ((n) & 0x3))) + +/* + * tcr register definitions + */ +#define LPC32XX_TIMER_CNTR_TCR_EN 0x1 +#define LPC32XX_TIMER_CNTR_TCR_RESET 0x2 + +/* + * mcr register definitions + */ +#define LPC32XX_TIMER_CNTR_MCR_MTCH(n) (0x1 << ((n) * 3)) +#define LPC32XX_TIMER_CNTR_MCR_RESET(n) (0x1 << (((n) * 3) + 1)) +#define LPC32XX_TIMER_CNTR_MCR_STOP(n) (0x1 << (((n) * 3) + 2)) + +/* + * Standard UART register offsets + */ +#define LPC32XX_UART_DLL_FIFO(x) io_p2v((x) + 0x00) +#define LPC32XX_UART_DLM_IER(x) io_p2v((x) + 0x04) +#define LPC32XX_UART_IIR_FCR(x) io_p2v((x) + 0x08) +#define LPC32XX_UART_LCR(x) io_p2v((x) + 0x0C) +#define LPC32XX_UART_MODEM_CTRL(x) io_p2v((x) + 0x10) +#define LPC32XX_UART_LSR(x) io_p2v((x) + 0x14) +#define LPC32XX_UART_MODEM_STATUS(x) io_p2v((x) + 0x18) +#define LPC32XX_UART_RXLEV(x) io_p2v((x) + 0x1C) + +/* + * UART control structure offsets + */ +#define _UCREG(x) io_p2v(\ + LPC32XX_UART_CTRL_BASE + (x)) +#define LPC32XX_UARTCTL_CTRL _UCREG(0x00) +#define LPC32XX_UARTCTL_CLKMODE _UCREG(0x04) +#define LPC32XX_UARTCTL_CLOOP _UCREG(0x08) + +/* + * ctrl register definitions + */ +#define LPC32XX_UART_U3_MD_CTRL_EN _BIT(11) +#define LPC32XX_UART_IRRX6_INV_EN _BIT(10) +#define LPC32XX_UART_HDPX_EN _BIT(9) +#define LPC32XX_UART_UART6_IRDAMOD_BYPASS _BIT(5) +#define LPC32XX_RT_IRTX6_INV_EN _BIT(4) +#define LPC32XX_RT_IRTX6_INV_MIR_EN _BIT(3) +#define LPC32XX_RT_RX_IRPULSE_3_16_115K _BIT(2) +#define LPC32XX_RT_TX_IRPULSE_3_16_115K _BIT(1) +#define LPC32XX_UART_U5_ROUTE_TO_USB _BIT(0) + +/* + * clkmode register definitions + */ +#define LPC32XX_UART_ENABLED_CLOCKS(n) (((n) >> 16) & 0x7F) +#define LPC32XX_UART_ENABLED_CLOCK(n, u) (((n) >> (16 + (u))) & 0x1) +#define LPC32XX_UART_ENABLED_CLKS_ANY _BIT(14) +#define LPC32XX_UART_CLKMODE_OFF 0x0 +#define LPC32XX_UART_CLKMODE_ON 0x1 +#define LPC32XX_UART_CLKMODE_AUTO 0x2 +#define LPC32XX_UART_CLKMODE_MASK(u) (0x3 << ((((u) - 3) * 2) + 4)) +#define LPC32XX_UART_CLKMODE_LOAD(m, u) ((m) << ((((u) - 3) * 2) + 4)) + +/* + * GPIO Module Register offsets + */ +#define _GPREG(x) io_p2v(LPC32XX_GPIO_BASE + (x)) +#define LPC32XX_GPIO_P_MUX_SET _GPREG(0x100) +#define LPC32XX_GPIO_P_MUX_CLR _GPREG(0x104) +#define LPC32XX_GPIO_P_MUX_STATE _GPREG(0x108) +#define LPC32XX_GPIO_P3_MUX_SET _GPREG(0x110) +#define LPC32XX_GPIO_P3_MUX_CLR _GPREG(0x114) +#define LPC32XX_GPIO_P3_MUX_STATE _GPREG(0x118) +#define LPC32XX_GPIO_P0_MUX_SET _GPREG(0x120) +#define LPC32XX_GPIO_P0_MUX_CLR _GPREG(0x124) +#define LPC32XX_GPIO_P0_MUX_STATE _GPREG(0x128) +#define LPC32XX_GPIO_P1_MUX_SET _GPREG(0x130) +#define LPC32XX_GPIO_P1_MUX_CLR _GPREG(0x134) +#define LPC32XX_GPIO_P1_MUX_STATE _GPREG(0x138) +#define LPC32XX_GPIO_P2_MUX_SET _GPREG(0x028) +#define LPC32XX_GPIO_P2_MUX_CLR _GPREG(0x02C) +#define LPC32XX_GPIO_P2_MUX_STATE _GPREG(0x030) + +/* + * USB Otg Registers + */ +#define _OTGREG(x) io_p2v(LPC32XX_USB_OTG_BASE + (x)) +#define LPC32XX_USB_OTG_CLK_CTRL _OTGREG(0xFF4) +#define LPC32XX_USB_OTG_CLK_STAT _OTGREG(0xFF8) + +/* USB OTG CLK CTRL bit defines */ +#define LPC32XX_USB_OTG_AHB_M_CLOCK_ON _BIT(4) +#define LPC32XX_USB_OTG_OTG_CLOCK_ON _BIT(3) +#define LPC32XX_USB_OTG_I2C_CLOCK_ON _BIT(2) +#define LPC32XX_USB_OTG_DEV_CLOCK_ON _BIT(1) +#define LPC32XX_USB_OTG_HOST_CLOCK_ON _BIT(0) + +/* + * Start of virtual addresses for IO devices + */ +#define IO_BASE 0xF0000000 + +/* + * This macro relies on fact that for all HW i/o addresses bits 20-23 are 0 + */ +#define IO_ADDRESS(x) IOMEM(((((x) & 0xff000000) >> 4) | ((x) & 0xfffff)) |\ + IO_BASE) + +#define io_p2v(x) ((void __iomem *) (unsigned long) IO_ADDRESS(x)) +#define io_v2p(x) ((((x) & 0x0ff00000) << 4) | ((x) & 0x000fffff)) + +#endif diff --git a/arch/arm/mach-lpc32xx/pm.c b/arch/arm/mach-lpc32xx/pm.c index 32bca351a73b..b27fa1b9f56c 100644 --- a/arch/arm/mach-lpc32xx/pm.c +++ b/arch/arm/mach-lpc32xx/pm.c @@ -70,8 +70,7 @@ #include -#include -#include +#include "lpc32xx.h" #include "common.h" #define TEMP_IRAM_AREA IO_ADDRESS(LPC32XX_IRAM_BASE) diff --git a/arch/arm/mach-lpc32xx/serial.c b/arch/arm/mach-lpc32xx/serial.c index cfb35e5691cd..3e765c4bf986 100644 --- a/arch/arm/mach-lpc32xx/serial.c +++ b/arch/arm/mach-lpc32xx/serial.c @@ -16,8 +16,7 @@ #include #include -#include -#include +#include "lpc32xx.h" #include "common.h" #define LPC32XX_SUART_FIFO_SIZE 64 diff --git a/arch/arm/mach-lpc32xx/suspend.S b/arch/arm/mach-lpc32xx/suspend.S index 374f9f07fe48..3f0a8282ef6f 100644 --- a/arch/arm/mach-lpc32xx/suspend.S +++ b/arch/arm/mach-lpc32xx/suspend.S @@ -11,8 +11,7 @@ */ #include #include -#include -#include +#include "lpc32xx.h" /* Using named register defines makes the code easier to follow */ #define WORK1_REG r0 -- cgit v1.3-14-g43fede From 75bf1bd7d2f993787d0faa7d6e6534f7e88a2975 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Fri, 9 Aug 2019 16:40:39 +0200 Subject: ARM: lpc32xx: allow multiplatform build All preparation work is done, so the platform can finally be moved into ARCH_MULTIPLATFORM. This requires a small change to the defconfig file to enable the platform. Link: https://lore.kernel.org/r/20190809144043.476786-14-arnd@arndb.de Signed-off-by: Arnd Bergmann --- arch/arm/Kconfig | 17 ++------- arch/arm/configs/lpc32xx_defconfig | 1 + arch/arm/mach-lpc32xx/Kconfig | 11 ++++++ arch/arm/mach-lpc32xx/include/mach/uncompress.h | 48 ------------------------- 4 files changed, 14 insertions(+), 63 deletions(-) create mode 100644 arch/arm/mach-lpc32xx/Kconfig delete mode 100644 arch/arm/mach-lpc32xx/include/mach/uncompress.h diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 33b00579beff..65808e17cb3b 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -478,21 +478,6 @@ config ARCH_W90X900 -config ARCH_LPC32XX - bool "NXP LPC32XX" - select ARM_AMBA - select CLKDEV_LOOKUP - select CLKSRC_LPC32XX - select COMMON_CLK - select CPU_ARM926T - select GENERIC_CLOCKEVENTS - select GENERIC_IRQ_MULTI_HANDLER - select GPIOLIB - select SPARSE_IRQ - select USE_OF - help - Support for the NXP LPC32XX family of processors - config ARCH_PXA bool "PXA2xx/PXA3xx-based" depends on MMU @@ -746,6 +731,8 @@ source "arch/arm/mach-keystone/Kconfig" source "arch/arm/mach-ks8695/Kconfig" +source "arch/arm/mach-lpc32xx/Kconfig" + source "arch/arm/mach-mediatek/Kconfig" source "arch/arm/mach-meson/Kconfig" diff --git a/arch/arm/configs/lpc32xx_defconfig b/arch/arm/configs/lpc32xx_defconfig index 3772d5a8975a..09deb57db942 100644 --- a/arch/arm/configs/lpc32xx_defconfig +++ b/arch/arm/configs/lpc32xx_defconfig @@ -12,6 +12,7 @@ CONFIG_CC_OPTIMIZE_FOR_SIZE=y CONFIG_SYSCTL_SYSCALL=y CONFIG_EMBEDDED=y CONFIG_SLAB=y +# CONFIG_ARCH_MULTI_V7 is not set CONFIG_ARCH_LPC32XX=y CONFIG_AEABI=y CONFIG_ZBOOT_ROM_TEXT=0x0 diff --git a/arch/arm/mach-lpc32xx/Kconfig b/arch/arm/mach-lpc32xx/Kconfig new file mode 100644 index 000000000000..ec87c65f4536 --- /dev/null +++ b/arch/arm/mach-lpc32xx/Kconfig @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: GPL-2.0-only + +config ARCH_LPC32XX + bool "NXP LPC32XX" + depends on ARCH_MULTI_V5 + select ARM_AMBA + select CLKSRC_LPC32XX + select CPU_ARM926T + select GPIOLIB + help + Support for the NXP LPC32XX family of processors diff --git a/arch/arm/mach-lpc32xx/include/mach/uncompress.h b/arch/arm/mach-lpc32xx/include/mach/uncompress.h deleted file mode 100644 index 74b7aa0da0e4..000000000000 --- a/arch/arm/mach-lpc32xx/include/mach/uncompress.h +++ /dev/null @@ -1,48 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * arch/arm/mach-lpc32xx/include/mach/uncompress.h - * - * Author: Kevin Wells - * - * Copyright (C) 2010 NXP Semiconductors - */ - -#ifndef __ASM_ARM_ARCH_UNCOMPRESS_H -#define __ASM_ARM_ARCH_UNCOMPRESS_H - -#include - -/* - * Uncompress output is hardcoded to standard UART 5 - */ - -#define UART_FIFO_CTL_TX_RESET (1 << 2) -#define UART_STATUS_TX_MT (1 << 6) -#define LPC32XX_UART5_BASE 0x40090000 - -#define _UARTREG(x) (void __iomem *)(LPC32XX_UART5_BASE + (x)) - -#define LPC32XX_UART_DLLFIFO_O 0x00 -#define LPC32XX_UART_IIRFCR_O 0x08 -#define LPC32XX_UART_LSR_O 0x14 - -static inline void putc(int ch) -{ - /* Wait for transmit FIFO to empty */ - while ((__raw_readl(_UARTREG(LPC32XX_UART_LSR_O)) & - UART_STATUS_TX_MT) == 0) - ; - - __raw_writel((u32) ch, _UARTREG(LPC32XX_UART_DLLFIFO_O)); -} - -static inline void flush(void) -{ - __raw_writel(__raw_readl(_UARTREG(LPC32XX_UART_IIRFCR_O)) | - UART_FIFO_CTL_TX_RESET, _UARTREG(LPC32XX_UART_IIRFCR_O)); -} - -/* NULL functions; we don't presently need them */ -#define arch_decomp_setup() - -#endif -- cgit v1.3-14-g43fede