From d6a14ce6cd8d2d01d97a1450b9f755f5ed20ee34 Mon Sep 17 00:00:00 2001 From: Lubomir Rintel Date: Fri, 20 Mar 2020 18:41:00 +0100 Subject: ARM: dts: pxa*: Make the serial ports compatible with xscale-uart Some drivers that claim to support mrvl,mmp-uart default to a reg-shift of two, some don't. Be explicit to be on a safe side. With that in place, a XScale serial port driver is perfectly capable of supporting the MMP serial port. Add a compatible string. Signed-off-by: Lubomir Rintel Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/20200320174107.29406-4-lkundrak@v3.sk Signed-off-by: Greg Kroah-Hartman --- arch/arm/boot/dts/pxa168.dtsi | 9 ++++++--- arch/arm/boot/dts/pxa910.dtsi | 9 ++++++--- 2 files changed, 12 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/pxa168.dtsi b/arch/arm/boot/dts/pxa168.dtsi index 41dc79c9f632..9a9e38245e88 100644 --- a/arch/arm/boot/dts/pxa168.dtsi +++ b/arch/arm/boot/dts/pxa168.dtsi @@ -56,8 +56,9 @@ }; uart1: serial@d4017000 { - compatible = "mrvl,mmp-uart"; + compatible = "mrvl,mmp-uart", "intel,xscale-uart"; reg = <0xd4017000 0x1000>; + reg-shift = <2>; interrupts = <27>; clocks = <&soc_clocks PXA168_CLK_UART0>; resets = <&soc_clocks PXA168_CLK_UART0>; @@ -65,8 +66,9 @@ }; uart2: serial@d4018000 { - compatible = "mrvl,mmp-uart"; + compatible = "mrvl,mmp-uart", "intel,xscale-uart"; reg = <0xd4018000 0x1000>; + reg-shift = <2>; interrupts = <28>; clocks = <&soc_clocks PXA168_CLK_UART1>; resets = <&soc_clocks PXA168_CLK_UART1>; @@ -74,8 +76,9 @@ }; uart3: serial@d4026000 { - compatible = "mrvl,mmp-uart"; + compatible = "mrvl,mmp-uart", "intel,xscale-uart"; reg = <0xd4026000 0x1000>; + reg-shift = <2>; interrupts = <29>; clocks = <&soc_clocks PXA168_CLK_UART2>; resets = <&soc_clocks PXA168_CLK_UART2>; diff --git a/arch/arm/boot/dts/pxa910.dtsi b/arch/arm/boot/dts/pxa910.dtsi index 209b1f0ea67b..587a5e7f0702 100644 --- a/arch/arm/boot/dts/pxa910.dtsi +++ b/arch/arm/boot/dts/pxa910.dtsi @@ -68,8 +68,9 @@ }; uart1: serial@d4017000 { - compatible = "mrvl,mmp-uart"; + compatible = "mrvl,mmp-uart", "intel,xscale-uart"; reg = <0xd4017000 0x1000>; + reg-shift = <2>; interrupts = <27>; clocks = <&soc_clocks PXA910_CLK_UART0>; resets = <&soc_clocks PXA910_CLK_UART0>; @@ -77,8 +78,9 @@ }; uart2: serial@d4018000 { - compatible = "mrvl,mmp-uart"; + compatible = "mrvl,mmp-uart", "intel,xscale-uart"; reg = <0xd4018000 0x1000>; + reg-shift = <2>; interrupts = <28>; clocks = <&soc_clocks PXA910_CLK_UART1>; resets = <&soc_clocks PXA910_CLK_UART1>; @@ -86,8 +88,9 @@ }; uart3: serial@d4036000 { - compatible = "mrvl,mmp-uart"; + compatible = "mrvl,mmp-uart", "intel,xscale-uart"; reg = <0xd4036000 0x1000>; + reg-shift = <2>; interrupts = <59>; clocks = <&soc_clocks PXA910_CLK_UART2>; resets = <&soc_clocks PXA910_CLK_UART2>; -- cgit v1.2.3-59-g8ed1b