From 820970a5aa3c98be26e1df64da4b93294d20d4e7 Mon Sep 17 00:00:00 2001 From: Vineet Gupta Date: Fri, 6 Mar 2015 14:08:20 +0530 Subject: ARCv2: [intc] HS38 core interrupt controller Cc: Jason Cooper Cc: Thomas Gleixner Signed-off-by: Vineet Gupta --- .../devicetree/bindings/arc/archs-intc.txt | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) create mode 100644 Documentation/devicetree/bindings/arc/archs-intc.txt (limited to 'Documentation/devicetree/bindings/arc') diff --git a/Documentation/devicetree/bindings/arc/archs-intc.txt b/Documentation/devicetree/bindings/arc/archs-intc.txt new file mode 100644 index 000000000000..69f326d6a5ad --- /dev/null +++ b/Documentation/devicetree/bindings/arc/archs-intc.txt @@ -0,0 +1,22 @@ +* ARC-HS incore Interrupt Controller (Provided by cores implementing ARCv2 ISA) + +Properties: + +- compatible: "snps,archs-intc" +- interrupt-controller: This is an interrupt controller. +- #interrupt-cells: Must be <1>. + + Single Cell "interrupts" property of a device specifies the IRQ number + between 16 to 256 + + intc accessed via the special ARC AUX register interface, hence "reg" property + is not specified. + +Example: + + intc: interrupt-controller { + compatible = "snps,archs-intc"; + interrupt-controller; + #interrupt-cells = <1>; + interrupts = <16 17 18 19 20 21 22 23 24 25>; + }; -- cgit v1.2.3-59-g8ed1b