From fab8ad0b2b5f2b6d25c6020a61bf3339e53fec61 Mon Sep 17 00:00:00 2001 From: Jon Hunter Date: Fri, 19 Oct 2012 09:59:00 -0500 Subject: ARM: dts: OMAP: Add timer nodes Add the 12 GP timers nodes present in OMAP2. Add the 12 GP timers nodes present in OMAP3. Add the 11 GP timers nodes present in OMAP4. Add the 7 GP timers nodes present in AM33xx. Add documentation for timer properties specific to OMAP. Thanks to Vaibhav Hiremath for creating the AM33xx timer nodes. I have modified Vaibhav's original nodes adding information on which timers support a PWM output. V5 changes: - Updated timer register sizes for OMAP2/3/4. - Modified AM335x timer register size to be 1KB instead of 4KB to align with HWMOD. Signed-off-by: Jon Hunter Acked-Reviewed-&-Tested-By: Vaibhav Hiremath Signed-off-by: Benoit Cousson --- .../devicetree/bindings/arm/omap/timer.txt | 31 ++++++++++++++++++++++ 1 file changed, 31 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/omap/timer.txt (limited to 'Documentation/devicetree/bindings/arm') diff --git a/Documentation/devicetree/bindings/arm/omap/timer.txt b/Documentation/devicetree/bindings/arm/omap/timer.txt new file mode 100644 index 000000000000..8732d4d41f8b --- /dev/null +++ b/Documentation/devicetree/bindings/arm/omap/timer.txt @@ -0,0 +1,31 @@ +OMAP Timer bindings + +Required properties: +- compatible: Must be "ti,omap2-timer" for OMAP2+ controllers. +- reg: Contains timer register address range (base address and + length). +- interrupts: Contains the interrupt information for the timer. The + format is being dependent on which interrupt controller + the OMAP device uses. +- ti,hwmods: Name of the hwmod associated to the timer, "timer", + where is the instance number of the timer from the + HW spec. + +Optional properties: +- ti,timer-alwon: Indicates the timer is in an alway-on power domain. +- ti,timer-dsp: Indicates the timer can interrupt the on-chip DSP in + addition to the ARM CPU. +- ti,timer-pwm: Indicates the timer can generate a PWM output. +- ti,timer-secure: Indicates the timer is reserved on a secure OMAP device + and therefore cannot be used by the kernel. + +Example: + +timer12: timer@48304000 { + compatible = "ti,omap2-timer"; + reg = <0x48304000 0x400>; + interrupts = <95>; + ti,hwmods = "timer12" + ti,timer-alwon; + ti,timer-secure; +}; -- cgit v1.2.3-59-g8ed1b From 510c0ffdd408ced2654f073d0397f0fec410a235 Mon Sep 17 00:00:00 2001 From: Jon Hunter Date: Thu, 25 Oct 2012 14:24:14 -0500 Subject: ARM: dts: OMAP: Add counter-32k nodes Adds the counter-32k timers nodes present in OMAP2/3/4 devices and device-tree binding documentation for OMAP counter-32k. Signed-off-by: Jon Hunter Signed-off-by: Benoit Cousson --- Documentation/devicetree/bindings/arm/omap/counter.txt | 15 +++++++++++++++ arch/arm/boot/dts/omap2420.dtsi | 6 ++++++ arch/arm/boot/dts/omap2430.dtsi | 6 ++++++ arch/arm/boot/dts/omap3.dtsi | 6 ++++++ arch/arm/boot/dts/omap4.dtsi | 6 ++++++ 5 files changed, 39 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/omap/counter.txt (limited to 'Documentation/devicetree/bindings/arm') diff --git a/Documentation/devicetree/bindings/arm/omap/counter.txt b/Documentation/devicetree/bindings/arm/omap/counter.txt new file mode 100644 index 000000000000..5bd8aa091315 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/omap/counter.txt @@ -0,0 +1,15 @@ +OMAP Counter-32K bindings + +Required properties: +- compatible: Must be "ti,omap-counter32k" for OMAP controllers +- reg: Contains timer register address range (base address and length) +- ti,hwmods: Name of the hwmod associated to the counter, which is typically + "counter_32k" + +Example: + +counter32k: counter@4a304000 { + compatible = "ti,omap-counter32k"; + reg = <0x4a304000 0x20>; + ti,hwmods = "counter_32k"; +}; diff --git a/arch/arm/boot/dts/omap2420.dtsi b/arch/arm/boot/dts/omap2420.dtsi index af5ee262d0cf..af6560908905 100644 --- a/arch/arm/boot/dts/omap2420.dtsi +++ b/arch/arm/boot/dts/omap2420.dtsi @@ -14,6 +14,12 @@ compatible = "ti,omap2420", "ti,omap2"; ocp { + counter32k: counter@48004000 { + compatible = "ti,omap-counter32k"; + reg = <0x48004000 0x20>; + ti,hwmods = "counter_32k"; + }; + omap2420_pmx: pinmux@48000030 { compatible = "ti,omap2420-padconf", "pinctrl-single"; reg = <0x48000030 0x0113>; diff --git a/arch/arm/boot/dts/omap2430.dtsi b/arch/arm/boot/dts/omap2430.dtsi index 688729840f14..c3924457c9b6 100644 --- a/arch/arm/boot/dts/omap2430.dtsi +++ b/arch/arm/boot/dts/omap2430.dtsi @@ -14,6 +14,12 @@ compatible = "ti,omap2430", "ti,omap2"; ocp { + counter32k: counter@49020000 { + compatible = "ti,omap-counter32k"; + reg = <0x49020000 0x20>; + ti,hwmods = "counter_32k"; + }; + omap2430_pmx: pinmux@49002030 { compatible = "ti,omap2430-padconf", "pinctrl-single"; reg = <0x49002030 0x0154>; diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi index af9b1822ff84..1acc26148ffc 100644 --- a/arch/arm/boot/dts/omap3.dtsi +++ b/arch/arm/boot/dts/omap3.dtsi @@ -61,6 +61,12 @@ ranges; ti,hwmods = "l3_main"; + counter32k: counter@48320000 { + compatible = "ti,omap-counter32k"; + reg = <0x48320000 0x20>; + ti,hwmods = "counter_32k"; + }; + intc: interrupt-controller@48200000 { compatible = "ti,omap2-intc"; interrupt-controller; diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi index d3a82e0c3804..23ee1498c98c 100644 --- a/arch/arm/boot/dts/omap4.dtsi +++ b/arch/arm/boot/dts/omap4.dtsi @@ -95,6 +95,12 @@ ranges; ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3"; + counter32k: counter@4a304000 { + compatible = "ti,omap-counter32k"; + reg = <0x4a304000 0x20>; + ti,hwmods = "counter_32k"; + }; + omap4_pmx_core: pinmux@4a100040 { compatible = "ti,omap4-padconf", "pinctrl-single"; reg = <0x4a100040 0x0196>; -- cgit v1.2.3-59-g8ed1b From 64100a03ad0b94a45ed2753632d9dd68379ad3ac Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Fri, 2 Nov 2012 01:20:43 +0100 Subject: ARM: integrator: hook the CP into the SoC bus This hooks the Integrator/CP into the SoC bus when booting from device tree, by mapping the CP controller registers first, then registering the SoC device, and then populating the device tree with the SoC device as parent. Cc: Lee Jones Acked-by: Arnd Bergmann Signed-off-by: Linus Walleij --- Documentation/devicetree/bindings/arm/arm-boards | 4 ++ arch/arm/boot/dts/integratorcp.dts | 5 +++ arch/arm/mach-integrator/Kconfig | 1 + arch/arm/mach-integrator/integrator_cp.c | 57 +++++++++++++++++++++++- 4 files changed, 65 insertions(+), 2 deletions(-) (limited to 'Documentation/devicetree/bindings/arm') diff --git a/Documentation/devicetree/bindings/arm/arm-boards b/Documentation/devicetree/bindings/arm/arm-boards index fc81a7d6b0f1..db5858e32d3f 100644 --- a/Documentation/devicetree/bindings/arm/arm-boards +++ b/Documentation/devicetree/bindings/arm/arm-boards @@ -9,6 +9,10 @@ Required properties (in root node): FPGA type interrupt controllers, see the versatile-fpga-irq binding doc. +In the root node the Integrator/CP must have a /cpcon node pointing +to the CP control registers, and the Integrator/AP must have a +/syscon node pointing to the Integrator/AP system controller. + ARM Versatile Application and Platform Baseboards ------------------------------------------------- diff --git a/arch/arm/boot/dts/integratorcp.dts b/arch/arm/boot/dts/integratorcp.dts index 2dd5e4e48481..8b119399025a 100644 --- a/arch/arm/boot/dts/integratorcp.dts +++ b/arch/arm/boot/dts/integratorcp.dts @@ -18,6 +18,11 @@ bootargs = "root=/dev/ram0 console=ttyAMA0,38400n8 earlyprintk"; }; + cpcon { + /* CP controller registers */ + reg = <0xcb000000 0x100>; + }; + timer0: timer@13000000 { compatible = "arm,sp804", "arm,primecell"; }; diff --git a/arch/arm/mach-integrator/Kconfig b/arch/arm/mach-integrator/Kconfig index 3961942c9e11..abeff25532ab 100644 --- a/arch/arm/mach-integrator/Kconfig +++ b/arch/arm/mach-integrator/Kconfig @@ -20,6 +20,7 @@ config ARCH_INTEGRATOR_CP select PLAT_VERSATILE_CLCD select SERIAL_AMBA_PL011 select SERIAL_AMBA_PL011_CONSOLE + select SOC_BUS help Include support for the ARM(R) Integrator CP platform. diff --git a/arch/arm/mach-integrator/integrator_cp.c b/arch/arm/mach-integrator/integrator_cp.c index 5b08e8e4cc83..9194a4f3339c 100644 --- a/arch/arm/mach-integrator/integrator_cp.c +++ b/arch/arm/mach-integrator/integrator_cp.c @@ -26,6 +26,7 @@ #include #include #include +#include #include #include @@ -336,10 +337,62 @@ static struct of_dev_auxdata intcp_auxdata_lookup[] __initdata = { { /* sentinel */ }, }; +/* Base address to the CP controller */ +static void __iomem *intcp_con_base; + static void __init intcp_init_of(void) { - of_platform_populate(NULL, of_default_bus_match_table, - intcp_auxdata_lookup, NULL); + struct device_node *root; + struct device_node *cpcon; + struct device *parent; + struct soc_device *soc_dev; + struct soc_device_attribute *soc_dev_attr; + u32 intcp_sc_id; + int err; + + /* Here we create an SoC device for the root node */ + root = of_find_node_by_path("/"); + if (!root) + return; + cpcon = of_find_node_by_path("/cpcon"); + if (!cpcon) + return; + + intcp_con_base = of_iomap(cpcon, 0); + if (!intcp_con_base) + return; + + intcp_sc_id = readl(intcp_con_base); + + soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL); + if (!soc_dev_attr) + return; + + err = of_property_read_string(root, "compatible", + &soc_dev_attr->soc_id); + if (err) + return; + err = of_property_read_string(root, "model", &soc_dev_attr->machine); + if (err) + return; + soc_dev_attr->family = "Integrator"; + soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%c", + 'A' + (intcp_sc_id & 0x0f)); + + soc_dev = soc_device_register(soc_dev_attr); + if (IS_ERR_OR_NULL(soc_dev)) { + kfree(soc_dev_attr->revision); + kfree(soc_dev_attr); + return; + } + + parent = soc_device_to_device(soc_dev); + + if (!IS_ERR_OR_NULL(parent)) + integrator_init_sysfs(parent, intcp_sc_id); + + of_platform_populate(root, of_default_bus_match_table, + intcp_auxdata_lookup, parent); } static const char * intcp_dt_board_compat[] = { -- cgit v1.2.3-59-g8ed1b