From 5918410d991c2c9d38bf9d813d08a434fb36521b Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Thu, 30 Apr 2020 22:10:48 +0100 Subject: dt-bindings: sata: Convert Calxeda SATA controller to json-schema Convert the Calxeda Highbank SATA controller binding to DT schema format using json-schema. Signed-off-by: Andre Przywara Cc: Jens Axboe Signed-off-by: Rob Herring --- .../devicetree/bindings/ata/sata_highbank.txt | 44 ---------- .../devicetree/bindings/ata/sata_highbank.yaml | 95 ++++++++++++++++++++++ 2 files changed, 95 insertions(+), 44 deletions(-) delete mode 100644 Documentation/devicetree/bindings/ata/sata_highbank.txt create mode 100644 Documentation/devicetree/bindings/ata/sata_highbank.yaml (limited to 'Documentation/devicetree/bindings/ata') diff --git a/Documentation/devicetree/bindings/ata/sata_highbank.txt b/Documentation/devicetree/bindings/ata/sata_highbank.txt deleted file mode 100644 index aa83407cb7a4..000000000000 --- a/Documentation/devicetree/bindings/ata/sata_highbank.txt +++ /dev/null @@ -1,44 +0,0 @@ -* Calxeda AHCI SATA Controller - -SATA nodes are defined to describe on-chip Serial ATA controllers. -The Calxeda SATA controller mostly conforms to the AHCI interface -with some special extensions to add functionality. -Each SATA controller should have its own node. - -Required properties: -- compatible : compatible list, contains "calxeda,hb-ahci" -- interrupts : -- reg : - -Optional properties: -- dma-coherent : Present if dma operations are coherent -- calxeda,port-phys : phandle-combophy and lane assignment, which maps each - SATA port to a combophy and a lane within that - combophy -- calxeda,sgpio-gpio: phandle-gpio bank, bit offset, and default on or off, - which indicates that the driver supports SGPIO - indicator lights using the indicated GPIOs -- calxeda,led-order : a u32 array that map port numbers to offsets within the - SGPIO bitstream. -- calxeda,tx-atten : a u32 array that contains TX attenuation override - codes, one per port. The upper 3 bytes are always - 0 and thus ignored. -- calxeda,pre-clocks : a u32 that indicates the number of additional clock - cycles to transmit before sending an SGPIO pattern -- calxeda,post-clocks: a u32 that indicates the number of additional clock - cycles to transmit after sending an SGPIO pattern - -Example: - sata@ffe08000 { - compatible = "calxeda,hb-ahci"; - reg = <0xffe08000 0x1000>; - interrupts = <115>; - dma-coherent; - calxeda,port-phys = <&combophy5 0 &combophy0 0 &combophy0 1 - &combophy0 2 &combophy0 3>; - calxeda,sgpio-gpio =<&gpioh 5 1 &gpioh 6 1 &gpioh 7 1>; - calxeda,led-order = <4 0 1 2 3>; - calxeda,tx-atten = <0xff 22 0xff 0xff 23>; - calxeda,pre-clocks = <10>; - calxeda,post-clocks = <0>; - }; diff --git a/Documentation/devicetree/bindings/ata/sata_highbank.yaml b/Documentation/devicetree/bindings/ata/sata_highbank.yaml new file mode 100644 index 000000000000..b195457006cc --- /dev/null +++ b/Documentation/devicetree/bindings/ata/sata_highbank.yaml @@ -0,0 +1,95 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/ata/sata_highbank.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Calxeda AHCI SATA Controller + +description: | + The Calxeda SATA controller mostly conforms to the AHCI interface + with some special extensions to add functionality, to map GPIOs for + activity LEDs and for mapping the ComboPHYs. + +maintainers: + - Andre Przywara + +properties: + compatible: + const: calxeda,hb-ahci + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + dma-coherent: true + + calxeda,pre-clocks: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Indicates the number of additional clock cycles to transmit before + sending an SGPIO pattern. + + calxeda,post-clocks: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Indicates the number of additional clock cycles to transmit after + sending an SGPIO pattern. + + calxeda,led-order: + description: Maps port numbers to offsets within the SGPIO bitstream. + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32-array + - minItems: 1 + maxItems: 8 + + calxeda,port-phys: + description: | + phandle-combophy and lane assignment, which maps each SATA port to a + combophy and a lane within that combophy + allOf: + - $ref: /schemas/types.yaml#/definitions/phandle-array + - minItems: 1 + maxItems: 8 + + calxeda,tx-atten: + description: | + Contains TX attenuation override codes, one per port. + The upper 24 bits of each entry are always 0 and thus ignored. + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32-array + - minItems: 1 + maxItems: 8 + + calxeda,sgpio-gpio: + description: | + phandle-gpio bank, bit offset, and default on or off, which indicates + that the driver supports SGPIO indicator lights using the indicated + GPIOs. + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + sata@ffe08000 { + compatible = "calxeda,hb-ahci"; + reg = <0xffe08000 0x1000>; + interrupts = <115>; + dma-coherent; + calxeda,port-phys = <&combophy5 0>, <&combophy0 0>, <&combophy0 1>, + <&combophy0 2>, <&combophy0 3>; + calxeda,sgpio-gpio =<&gpioh 5 1>, <&gpioh 6 1>, <&gpioh 7 1>; + calxeda,led-order = <4 0 1 2 3>; + calxeda,tx-atten = <0xff 22 0xff 0xff 23>; + calxeda,pre-clocks = <10>; + calxeda,post-clocks = <0>; + }; + +... -- cgit v1.2.3-59-g8ed1b