From a3bb8a70e7effbbb7205615591392ac4b1dbe8bf Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sun, 29 Aug 2021 18:47:51 +0300 Subject: dt-bindings: clock: qcom,videocc: add mmcx power domain On sm8250 videocc requires MMCX power domain to be powered up before clock controller's registers become available. For now sm8250 was using external regulator driven by the power domain to describe this relationship. Switch into specifying power-domain and required opp-state directly. Signed-off-by: Dmitry Baryshkov Reviewed-by: Bjorn Andersson Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/20210829154757.784699-3-dmitry.baryshkov@linaro.org Signed-off-by: Stephen Boyd --- Documentation/devicetree/bindings/clock/qcom,videocc.yaml | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'Documentation/devicetree/bindings/clock/qcom,videocc.yaml') diff --git a/Documentation/devicetree/bindings/clock/qcom,videocc.yaml b/Documentation/devicetree/bindings/clock/qcom,videocc.yaml index 0d224f114b5b..3cdbcebdc1a1 100644 --- a/Documentation/devicetree/bindings/clock/qcom,videocc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,videocc.yaml @@ -49,6 +49,16 @@ properties: reg: maxItems: 1 + power-domains: + description: + A phandle and PM domain specifier for the MMCX power domain. + maxItems: 1 + + required-opps: + description: + A phandle to an OPP node describing required MMCX performance point. + maxItems: 1 + required: - compatible - reg @@ -63,6 +73,7 @@ additionalProperties: false examples: - | #include + #include clock-controller@ab00000 { compatible = "qcom,sdm845-videocc"; reg = <0x0ab00000 0x10000>; @@ -71,5 +82,7 @@ examples: #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; + power-domains = <&rpmhpd SM8250_MMCX>; + required-opps = <&rpmhpd_opp_low_svs>; }; ... -- cgit v1.2.3-59-g8ed1b