From 0f23a179746c10de8f8fe6ecc4767a0d6c824fa9 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Mon, 16 Jul 2018 13:06:06 -0500 Subject: dt-bindings: mailbox: Add support for secure proxy threads Secure Proxy is another communication scheme in Texas Instrument's devices intended to provide an unique communication path from various processors in the System on Chip(SoC) to a central System Controller. Secure proxy is, in effect, an evolution of current generation Message Manager hardware block found in K2G devices. However the following changes have taken place: Secure Proxy instance exposes "threads" or "proxies" which is primary representation of "a" communication channel. Each thread is preconfigured by System controller configuration based on SoC usage requirements. Secure proxy by itself represents a single "queue" of communication but allows the proxies to be independently operated. Each Secure proxy thread can uniquely have their own error and threshold interrupts allowing for more fine control of IRQ handling. Provide an hardware description of the same for device tree representation. See AM65x Technical Reference Manual (SPRUID7, April 2018) for further details: http://www.ti.com/lit/pdf/spruid7 Reviewed-by: Rob Herring Signed-off-by: Nishanth Menon Signed-off-by: Jassi Brar --- .../bindings/mailbox/ti,secure-proxy.txt | 50 ++++++++++++++++++++++ 1 file changed, 50 insertions(+) create mode 100644 Documentation/devicetree/bindings/mailbox/ti,secure-proxy.txt (limited to 'Documentation/devicetree/bindings/mailbox') diff --git a/Documentation/devicetree/bindings/mailbox/ti,secure-proxy.txt b/Documentation/devicetree/bindings/mailbox/ti,secure-proxy.txt new file mode 100644 index 000000000000..6c9c7daf0f5c --- /dev/null +++ b/Documentation/devicetree/bindings/mailbox/ti,secure-proxy.txt @@ -0,0 +1,50 @@ +Texas Instruments' Secure Proxy +======================================== + +The Texas Instruments' secure proxy is a mailbox controller that has +configurable queues selectable at SoC(System on Chip) integration. The +Message manager is broken up into different address regions that are +called "threads" or "proxies" - each instance is unidirectional and is +instantiated at SoC integration level by system controller to indicate +receive or transmit path. + +Message Manager Device Node: +=========================== +Required properties: +-------------------- +- compatible: Shall be "ti,am654-secure-proxy" +- reg-names target_data - Map the proxy data region + rt - Map the realtime status region + scfg - Map the configuration region +- reg: Contains the register map per reg-names. +- #mbox-cells Shall be 1 and shall refer to the transfer path + called thread. +- interrupt-names: Contains interrupt names matching the rx transfer path + for a given SoC. Receive interrupts shall be of the + format: "rx_". +- interrupts: Contains the interrupt information corresponding to + interrupt-names property. + +Example(AM654): +------------ + + secure_proxy: mailbox@32c00000 { + compatible = "ti,am654-secure-proxy"; + #mbox-cells = <1>; + reg-names = "target_data", "rt", "scfg"; + reg = <0x0 0x32c00000 0x0 0x100000>, + <0x0 0x32400000 0x0 0x100000>, + <0x0 0x32800000 0x0 0x100000>; + interrupt-names = "rx_011"; + interrupts = ; + }; + + dmsc: dmsc { + [...] + mbox-names = "rx", "tx"; + # RX Thread ID is 11 + # TX Thread ID is 13 + mboxes= <&secure_proxy 11>, + <&secure_proxy 13>; + [...] + }; -- cgit v1.2.3-59-g8ed1b From 1c82407aa302774b24bf619e56973aa97cbf25bd Mon Sep 17 00:00:00 2001 From: Houlong Wei Date: Wed, 25 Jul 2018 09:26:39 +0800 Subject: dt-bindings: soc: Add documentation for the MediaTek GCE unit This adds documentation for the MediaTek Global Command Engine (GCE) unit found in MT8173 SoCs. Signed-off-by: Houlong Wei Signed-off-by: HS Liao Reviewed-by: Rob Herring Signed-off-by: Jassi Brar --- .../devicetree/bindings/mailbox/mtk-gce.txt | 57 ++++++++++++++++++++++ include/dt-bindings/gce/mt8173-gce.h | 44 +++++++++++++++++ 2 files changed, 101 insertions(+) create mode 100644 Documentation/devicetree/bindings/mailbox/mtk-gce.txt create mode 100644 include/dt-bindings/gce/mt8173-gce.h (limited to 'Documentation/devicetree/bindings/mailbox') diff --git a/Documentation/devicetree/bindings/mailbox/mtk-gce.txt b/Documentation/devicetree/bindings/mailbox/mtk-gce.txt new file mode 100644 index 000000000000..7d72b21c9e94 --- /dev/null +++ b/Documentation/devicetree/bindings/mailbox/mtk-gce.txt @@ -0,0 +1,57 @@ +MediaTek GCE +=============== + +The Global Command Engine (GCE) is used to help read/write registers with +critical time limitation, such as updating display configuration during the +vblank. The GCE can be used to implement the Command Queue (CMDQ) driver. + +CMDQ driver uses mailbox framework for communication. Please refer to +mailbox.txt for generic information about mailbox device-tree bindings. + +Required properties: +- compatible: Must be "mediatek,mt8173-gce" +- reg: Address range of the GCE unit +- interrupts: The interrupt signal from the GCE block +- clock: Clocks according to the common clock binding +- clock-names: Must be "gce" to stand for GCE clock +- #mbox-cells: Should be 3. + <&phandle channel priority atomic_exec> + phandle: Label name of a gce node. + channel: Channel of mailbox. Be equal to the thread id of GCE. + priority: Priority of GCE thread. + atomic_exec: GCE processing continuous packets of commands in atomic + way. + +Required properties for a client device: +- mboxes: Client use mailbox to communicate with GCE, it should have this + property and list of phandle, mailbox specifiers. +- mediatek,gce-subsys: u32, specify the sub-system id which is corresponding + to the register address. + +Some vaules of properties are defined in 'dt-bindings/gce/mt8173-gce.h'. Such as +sub-system ids, thread priority, event ids. + +Example: + + gce: gce@10212000 { + compatible = "mediatek,mt8173-gce"; + reg = <0 0x10212000 0 0x1000>; + interrupts = ; + clocks = <&infracfg CLK_INFRA_GCE>; + clock-names = "gce"; + thread-num = CMDQ_THR_MAX_COUNT; + #mbox-cells = <3>; + }; + +Example for a client device: + + mmsys: clock-controller@14000000 { + compatible = "mediatek,mt8173-mmsys"; + mboxes = <&gce 0 CMDQ_THR_PRIO_LOWEST 1>, + <&gce 1 CMDQ_THR_PRIO_LOWEST 1>; + mediatek,gce-subsys = ; + mutex-event-eof = ; + + ... + }; diff --git a/include/dt-bindings/gce/mt8173-gce.h b/include/dt-bindings/gce/mt8173-gce.h new file mode 100644 index 000000000000..ffcf94ba96c6 --- /dev/null +++ b/include/dt-bindings/gce/mt8173-gce.h @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2018 MediaTek Inc. + * Author: Houlong Wei + * + */ + +#ifndef _DT_BINDINGS_GCE_MT8173_H +#define _DT_BINDINGS_GCE_MT8173_H + +/* GCE HW thread priority */ +#define CMDQ_THR_PRIO_LOWEST 0 +#define CMDQ_THR_PRIO_HIGHEST 1 + +/* GCE SUBSYS */ +#define SUBSYS_1400XXXX 1 +#define SUBSYS_1401XXXX 2 +#define SUBSYS_1402XXXX 3 + +/* GCE HW EVENT */ +#define CMDQ_EVENT_DISP_OVL0_SOF 11 +#define CMDQ_EVENT_DISP_OVL1_SOF 12 +#define CMDQ_EVENT_DISP_RDMA0_SOF 13 +#define CMDQ_EVENT_DISP_RDMA1_SOF 14 +#define CMDQ_EVENT_DISP_RDMA2_SOF 15 +#define CMDQ_EVENT_DISP_WDMA0_SOF 16 +#define CMDQ_EVENT_DISP_WDMA1_SOF 17 +#define CMDQ_EVENT_DISP_OVL0_EOF 39 +#define CMDQ_EVENT_DISP_OVL1_EOF 40 +#define CMDQ_EVENT_DISP_RDMA0_EOF 41 +#define CMDQ_EVENT_DISP_RDMA1_EOF 42 +#define CMDQ_EVENT_DISP_RDMA2_EOF 43 +#define CMDQ_EVENT_DISP_WDMA0_EOF 44 +#define CMDQ_EVENT_DISP_WDMA1_EOF 45 +#define CMDQ_EVENT_MUTEX0_STREAM_EOF 53 +#define CMDQ_EVENT_MUTEX1_STREAM_EOF 54 +#define CMDQ_EVENT_MUTEX2_STREAM_EOF 55 +#define CMDQ_EVENT_MUTEX3_STREAM_EOF 56 +#define CMDQ_EVENT_MUTEX4_STREAM_EOF 57 +#define CMDQ_EVENT_DISP_RDMA0_UNDERRUN 63 +#define CMDQ_EVENT_DISP_RDMA1_UNDERRUN 64 +#define CMDQ_EVENT_DISP_RDMA2_UNDERRUN 65 + +#endif -- cgit v1.2.3-59-g8ed1b From 480285bd11e63d9e225397516db39430f3e1b9c4 Mon Sep 17 00:00:00 2001 From: Dong Aisheng Date: Fri, 3 Aug 2018 07:29:16 +0200 Subject: dt-bindings: arm: fsl: add mu binding doc The Messaging Unit module enables two processors within the SoC to communicate and coordinate by passing messages (e.g. data, status and control) through the MU interface. Cc: Shawn Guo Cc: Sascha Hauer Cc: Fabio Estevam Cc: Mark Rutland Cc: devicetree@vger.kernel.org Reviewed-by: Rob Herring Signed-off-by: Dong Aisheng Signed-off-by: Jassi Brar --- .../devicetree/bindings/mailbox/fsl,mu.txt | 34 ++++++++++++++++++++++ 1 file changed, 34 insertions(+) create mode 100644 Documentation/devicetree/bindings/mailbox/fsl,mu.txt (limited to 'Documentation/devicetree/bindings/mailbox') diff --git a/Documentation/devicetree/bindings/mailbox/fsl,mu.txt b/Documentation/devicetree/bindings/mailbox/fsl,mu.txt new file mode 100644 index 000000000000..90e4905dfc69 --- /dev/null +++ b/Documentation/devicetree/bindings/mailbox/fsl,mu.txt @@ -0,0 +1,34 @@ +NXP i.MX Messaging Unit (MU) +-------------------------------------------------------------------- + +The Messaging Unit module enables two processors within the SoC to +communicate and coordinate by passing messages (e.g. data, status +and control) through the MU interface. The MU also provides the ability +for one processor to signal the other processor using interrupts. + +Because the MU manages the messaging between processors, the MU uses +different clocks (from each side of the different peripheral buses). +Therefore, the MU must synchronize the accesses from one side to the +other. The MU accomplishes synchronization using two sets of matching +registers (Processor A-facing, Processor B-facing). + +Messaging Unit Device Node: +============================= + +Required properties: +------------------- +- compatible : should be "fsl,-mu", the supported chips include + imx8qxp, imx8qm. +- reg : Should contain the registers location and length +- interrupts : Interrupt number. The interrupt specifier format depends + on the interrupt controller parent. +- #mbox-cells: Must be 0. Number of cells in a mailbox + +Examples: +-------- +lsio_mu0: mailbox@5d1b0000 { + compatible = "fsl,imx8qxp-mu"; + reg = <0x0 0x5d1b0000 0x0 0x10000>; + interrupts = ; + #mbox-cells = <0>; +}; -- cgit v1.2.3-59-g8ed1b From d6ef139c83cc562b29a5cdac270f0a562c1c8eda Mon Sep 17 00:00:00 2001 From: Oleksij Rempel Date: Fri, 3 Aug 2018 07:29:17 +0200 Subject: dt-bindings: mailbox: imx-mu: add generic MU channel support Each MU has four pairs of rx/tx data register with four rx/tx interrupts which can also be used as a separate channel. Reviewed-by: Rob Herring Signed-off-by: Oleksij Rempel Signed-off-by: Jassi Brar --- .../devicetree/bindings/mailbox/fsl,mu.txt | 26 +++++++++++++++++++--- 1 file changed, 23 insertions(+), 3 deletions(-) (limited to 'Documentation/devicetree/bindings/mailbox') diff --git a/Documentation/devicetree/bindings/mailbox/fsl,mu.txt b/Documentation/devicetree/bindings/mailbox/fsl,mu.txt index 90e4905dfc69..f3cf77eb5ab4 100644 --- a/Documentation/devicetree/bindings/mailbox/fsl,mu.txt +++ b/Documentation/devicetree/bindings/mailbox/fsl,mu.txt @@ -18,11 +18,31 @@ Messaging Unit Device Node: Required properties: ------------------- - compatible : should be "fsl,-mu", the supported chips include - imx8qxp, imx8qm. + imx6sx, imx7s, imx8qxp, imx8qm. + The "fsl,imx6sx-mu" compatible is seen as generic and should + be included together with SoC specific compatible. - reg : Should contain the registers location and length - interrupts : Interrupt number. The interrupt specifier format depends on the interrupt controller parent. -- #mbox-cells: Must be 0. Number of cells in a mailbox +- #mbox-cells: Must be 2. + <&phandle type channel> + phandle : Label name of controller + type : Channel type + channel : Channel number + + This MU support 4 type of unidirectional channels, each type + has 4 channels. A total of 16 channels. Following types are + supported: + 0 - TX channel with 32bit transmit register and IRQ transmit + acknowledgment support. + 1 - RX channel with 32bit receive register and IRQ support + 2 - TX doorbell channel. Without own register and no ACK support. + 3 - RX doorbell channel. + +Optional properties: +------------------- +- clocks : phandle to the input clock. +- fsl,mu-side-b : Should be set for side B MU. Examples: -------- @@ -30,5 +50,5 @@ lsio_mu0: mailbox@5d1b0000 { compatible = "fsl,imx8qxp-mu"; reg = <0x0 0x5d1b0000 0x0 0x10000>; interrupts = ; - #mbox-cells = <0>; + #mbox-cells = <2>; }; -- cgit v1.2.3-59-g8ed1b