From 96ef07f79ae8644ab9c277e3f2f4fb04a54be43d Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Wed, 1 May 2019 17:14:05 -0700 Subject: dt-bindings: phy: Add binding for Qualcomm PCIe2 PHY The Qualcomm PCIe2 PHY is a Synopsys based PCIe PHY found in a number of Qualcomm platforms, add a binding to describe this. Signed-off-by: Bjorn Andersson Reviewed-by: Rob Herring Signed-off-by: Kishon Vijay Abraham I --- .../devicetree/bindings/phy/qcom-pcie2-phy.txt | 42 ++++++++++++++++++++++ 1 file changed, 42 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/qcom-pcie2-phy.txt (limited to 'Documentation/devicetree/bindings/phy') diff --git a/Documentation/devicetree/bindings/phy/qcom-pcie2-phy.txt b/Documentation/devicetree/bindings/phy/qcom-pcie2-phy.txt new file mode 100644 index 000000000000..30064253f290 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/qcom-pcie2-phy.txt @@ -0,0 +1,42 @@ +Qualcomm PCIe2 PHY controller +============================= + +The Qualcomm PCIe2 PHY is a Synopsys based phy found in a number of Qualcomm +platforms. + +Required properties: + - compatible: compatible list, should be: + "qcom,qcs404-pcie2-phy", "qcom,pcie2-phy" + + - reg: offset and length of the PHY register set. + - #phy-cells: must be 0. + + - clocks: a clock-specifier pair for the "pipe" clock + + - vdda-vp-supply: phandle to low voltage regulator + - vdda-vph-supply: phandle to high voltage regulator + + - resets: reset-specifier pairs for the "phy" and "pipe" resets + - reset-names: list of resets, should contain: + "phy" and "pipe" + + - clock-output-names: name of the outgoing clock signal from the PHY PLL + - #clock-cells: must be 0 + +Example: + phy@7786000 { + compatible = "qcom,qcs404-pcie2-phy", "qcom,pcie2-phy"; + reg = <0x07786000 0xb8>; + + clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; + resets = <&gcc GCC_PCIEPHY_0_PHY_BCR>, + <&gcc GCC_PCIE_0_PIPE_ARES>; + reset-names = "phy", "pipe"; + + vdda-vp-supply = <&vreg_l3_1p05>; + vdda-vph-supply = <&vreg_l5_1p8>; + + clock-output-names = "pcie_0_pipe_clk"; + #clock-cells = <0>; + #phy-cells = <0>; + }; -- cgit v1.2.3-59-g8ed1b From 51cc0da52e16ef487e3b9f73ad0ba8243684e73d Mon Sep 17 00:00:00 2001 From: Lubomir Rintel Date: Thu, 20 Jun 2019 13:46:36 +0200 Subject: dt-bindings: phy-pxa-usb: add bindings This is the PHY chip for USB OTG on PXA platforms. Signed-off-by: Lubomir Rintel Acked-by: Pavel Machek Signed-off-by: Kishon Vijay Abraham I --- Documentation/devicetree/bindings/phy/phy-pxa-usb.txt | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/phy-pxa-usb.txt (limited to 'Documentation/devicetree/bindings/phy') diff --git a/Documentation/devicetree/bindings/phy/phy-pxa-usb.txt b/Documentation/devicetree/bindings/phy/phy-pxa-usb.txt new file mode 100644 index 000000000000..93fc09c12954 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/phy-pxa-usb.txt @@ -0,0 +1,18 @@ +Marvell PXA USB PHY +------------------- + +Required properties: +- compatible: one of: "marvell,mmp2-usb-phy", "marvell,pxa910-usb-phy", + "marvell,pxa168-usb-phy", +- #phy-cells: must be 0 + +Example: + usb-phy: usbphy@d4207000 { + compatible = "marvell,mmp2-usb-phy"; + reg = <0xd4207000 0x40>; + #phy-cells = <0>; + status = "okay"; + }; + +This document explains the device tree binding. For general +information about PHY subsystem refer to Documentation/phy.txt -- cgit v1.2.3-59-g8ed1b From 00fcc69d6e52643fc5ecd04ff7e2d560ed3e2ec0 Mon Sep 17 00:00:00 2001 From: Guido Günther Date: Thu, 20 Jun 2019 21:42:36 +0200 Subject: dt-bindings: phy: Add documentation for mixel dphy MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add support for the MIXEL DPHY IP as found on NXP's i.MX8MQ SoCs. Signed-off-by: Guido Günther Reviewed-by: Sam Ravnborg Reviewed-by: Rob Herring Reviewed-by: Fabio Estevam Signed-off-by: Kishon Vijay Abraham I --- .../devicetree/bindings/phy/mixel,mipi-dsi-phy.txt | 29 ++++++++++++++++++++++ 1 file changed, 29 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/mixel,mipi-dsi-phy.txt (limited to 'Documentation/devicetree/bindings/phy') diff --git a/Documentation/devicetree/bindings/phy/mixel,mipi-dsi-phy.txt b/Documentation/devicetree/bindings/phy/mixel,mipi-dsi-phy.txt new file mode 100644 index 000000000000..9b23407233c0 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/mixel,mipi-dsi-phy.txt @@ -0,0 +1,29 @@ +Mixel DSI PHY for i.MX8 + +The Mixel MIPI-DSI PHY IP block is e.g. found on i.MX8 platforms (along the +MIPI-DSI IP from Northwest Logic). It represents the physical layer for the +electrical signals for DSI. + +Required properties: +- compatible: Must be: + - "fsl,imx8mq-mipi-dphy" +- clocks: Must contain an entry for each entry in clock-names. +- clock-names: Must contain the following entries: + - "phy_ref": phandle and specifier referring to the DPHY ref clock +- reg: the register range of the PHY controller +- #phy-cells: number of cells in PHY, as defined in + Documentation/devicetree/bindings/phy/phy-bindings.txt + this must be <0> + +Optional properties: +- power-domains: phandle to power domain + +Example: + dphy: dphy@30a0030 { + compatible = "fsl,imx8mq-mipi-dphy"; + clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>; + clock-names = "phy_ref"; + reg = <0x30a00300 0x100>; + power-domains = <&pd_mipi0>; + #phy-cells = <0>; + }; -- cgit v1.2.3-59-g8ed1b