From 517bcde22c214612b86f4795e2c9d7df9b08cd54 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 21 Oct 2019 18:13:50 +0200 Subject: dt-bindings: sram: Merge Allwinner SRAM bindings into generic The Allwinner SRAM bindings list only compatible so integrate them into generic SRAM bindings schema. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Rob Herring --- Documentation/devicetree/bindings/sram/sram.yaml | 25 ++++++++++++++++++++++++ 1 file changed, 25 insertions(+) (limited to 'Documentation/devicetree/bindings/sram/sram.yaml') diff --git a/Documentation/devicetree/bindings/sram/sram.yaml b/Documentation/devicetree/bindings/sram/sram.yaml index 950043835ebb..59a4e0790f2b 100644 --- a/Documentation/devicetree/bindings/sram/sram.yaml +++ b/Documentation/devicetree/bindings/sram/sram.yaml @@ -65,6 +65,7 @@ patternProperties: Should contain a vendor specific string in the form ,[-] enum: + - allwinner,sun9i-a80-smp-sram - amlogic,meson8-smp-sram - amlogic,meson8b-smp-sram - renesas,smp-sram @@ -215,3 +216,27 @@ examples: reg = <0x10080000 0x50>; }; }; + + - | + // Allwinner's A80 SoC uses part of the secure sram for hotplugging of the + // primary core (cpu0). Once the core gets powered up it checks if a magic + // value is set at a specific location. If it is then the BROM will jump + // to the software entry address, instead of executing a standard boot. + // + // Also there are no "secure-only" properties. The implementation should + // check if this SRAM is usable first. + sram@20000 { + // 256 KiB secure SRAM at 0x20000 + compatible = "mmio-sram"; + reg = <0x00020000 0x40000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x00020000 0x40000>; + + smp-sram@1000 { + // This is checked by BROM to determine if + // cpu0 should jump to SMP entry vector + compatible = "allwinner,sun9i-a80-smp-sram"; + reg = <0x1000 0x8>; + }; + }; -- cgit v1.2.3-59-g8ed1b