From b9f9e9b8e42cae6de92617a6c45740e4e6eb6f7f Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Sun, 4 Nov 2018 19:26:42 +0100 Subject: dt-bindings: clock: sun8i-de2: Add H6 DE3 clock description This commit adds necessary description and dt includes for H6 DE3 clock. It is very similar to others, but memory region has some additional registers not found in DE2. Reviewed-by: Rob Herring Signed-off-by: Jernej Skrabec Signed-off-by: Maxime Ripard --- Documentation/devicetree/bindings/clock/sun8i-de2.txt | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/clock/sun8i-de2.txt b/Documentation/devicetree/bindings/clock/sun8i-de2.txt index e94582e8b8a9..41a52c2acffd 100644 --- a/Documentation/devicetree/bindings/clock/sun8i-de2.txt +++ b/Documentation/devicetree/bindings/clock/sun8i-de2.txt @@ -1,5 +1,5 @@ -Allwinner Display Engine 2.0 Clock Control Binding --------------------------------------------------- +Allwinner Display Engine 2.0/3.0 Clock Control Binding +------------------------------------------------------ Required properties : - compatible: must contain one of the following compatibles: @@ -8,6 +8,7 @@ Required properties : - "allwinner,sun8i-v3s-de2-clk" - "allwinner,sun50i-a64-de2-clk" - "allwinner,sun50i-h5-de2-clk" + - "allwinner,sun50i-h6-de3-clk" - reg: Must contain the registers base address and length - clocks: phandle to the clocks feeding the display engine subsystem. -- cgit v1.2.3-59-g8ed1b From eaeee28db2893dc56a29751f19210dc8ce8247c3 Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Sat, 3 Nov 2018 00:00:02 -0700 Subject: clk: qcom: smd: Add support for QCS404 rpm clocks Add rpm smd clocks, PMIC and bus clocks which are required on QCS404 for clients to vote on. Signed-off-by: Taniya Das Signed-off-by: Anu Ramanathan [bjorn: Dropped cxo, voter clocks and static initialization] Signed-off-by: Bjorn Andersson Signed-off-by: Stephen Boyd --- .../devicetree/bindings/clock/qcom,rpmcc.txt | 1 + drivers/clk/qcom/clk-smd-rpm.c | 45 ++++++++++++++++++++++ include/dt-bindings/clock/qcom,rpmcc.h | 4 ++ 3 files changed, 50 insertions(+) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt b/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt index 4491d1c104aa..87b4949e9bc8 100644 --- a/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt +++ b/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt @@ -16,6 +16,7 @@ Required properties : "qcom,rpmcc-msm8974", "qcom,rpmcc" "qcom,rpmcc-apq8064", "qcom,rpmcc" "qcom,rpmcc-msm8996", "qcom,rpmcc" + "qcom,rpmcc-qcs404", "qcom,rpmcc" - #clock-cells : shall contain 1 diff --git a/drivers/clk/qcom/clk-smd-rpm.c b/drivers/clk/qcom/clk-smd-rpm.c index 850c02a52248..d3aadaeb2903 100644 --- a/drivers/clk/qcom/clk-smd-rpm.c +++ b/drivers/clk/qcom/clk-smd-rpm.c @@ -611,10 +611,55 @@ static const struct rpm_smd_clk_desc rpm_clk_msm8996 = { .num_clks = ARRAY_SIZE(msm8996_clks), }; +/* QCS404 */ +DEFINE_CLK_SMD_RPM_QDSS(qcs404, qdss_clk, qdss_a_clk, QCOM_SMD_RPM_MISC_CLK, 1); + +DEFINE_CLK_SMD_RPM(qcs404, pnoc_clk, pnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 0); +DEFINE_CLK_SMD_RPM(qcs404, snoc_clk, snoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 1); + +DEFINE_CLK_SMD_RPM(qcs404, bimc_clk, bimc_a_clk, QCOM_SMD_RPM_MEM_CLK, 0); +DEFINE_CLK_SMD_RPM(qcs404, bimc_gpu_clk, bimc_gpu_a_clk, QCOM_SMD_RPM_MEM_CLK, 2); + +DEFINE_CLK_SMD_RPM(qcs404, qpic_clk, qpic_a_clk, QCOM_SMD_RPM_QPIC_CLK, 0); +DEFINE_CLK_SMD_RPM(qcs404, ce1_clk, ce1_a_clk, QCOM_SMD_RPM_CE_CLK, 0); + +DEFINE_CLK_SMD_RPM_XO_BUFFER(qcs404, rf_clk1, rf_clk1_a, 4); +DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(qcs404, rf_clk1_pin, rf_clk1_a_pin, 4); + +DEFINE_CLK_SMD_RPM_XO_BUFFER(qcs404, ln_bb_clk, ln_bb_a_clk, 8); +DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(qcs404, ln_bb_clk_pin, ln_bb_clk_a_pin, 8); + +static struct clk_smd_rpm *qcs404_clks[] = { + [RPM_SMD_QDSS_CLK] = &qcs404_qdss_clk, + [RPM_SMD_QDSS_A_CLK] = &qcs404_qdss_a_clk, + [RPM_SMD_PNOC_CLK] = &qcs404_pnoc_clk, + [RPM_SMD_PNOC_A_CLK] = &qcs404_pnoc_a_clk, + [RPM_SMD_SNOC_CLK] = &qcs404_snoc_clk, + [RPM_SMD_SNOC_A_CLK] = &qcs404_snoc_a_clk, + [RPM_SMD_BIMC_CLK] = &qcs404_bimc_clk, + [RPM_SMD_BIMC_A_CLK] = &qcs404_bimc_a_clk, + [RPM_SMD_BIMC_GPU_CLK] = &qcs404_bimc_gpu_clk, + [RPM_SMD_BIMC_GPU_A_CLK] = &qcs404_bimc_gpu_a_clk, + [RPM_SMD_QPIC_CLK] = &qcs404_qpic_clk, + [RPM_SMD_QPIC_CLK_A] = &qcs404_qpic_a_clk, + [RPM_SMD_CE1_CLK] = &qcs404_ce1_clk, + [RPM_SMD_CE1_A_CLK] = &qcs404_ce1_a_clk, + [RPM_SMD_RF_CLK1] = &qcs404_rf_clk1, + [RPM_SMD_RF_CLK1_A] = &qcs404_rf_clk1_a, + [RPM_SMD_LN_BB_CLK] = &qcs404_ln_bb_clk, + [RPM_SMD_LN_BB_A_CLK] = &qcs404_ln_bb_a_clk, +}; + +static const struct rpm_smd_clk_desc rpm_clk_qcs404 = { + .clks = qcs404_clks, + .num_clks = ARRAY_SIZE(qcs404_clks), +}; + static const struct of_device_id rpm_smd_clk_match_table[] = { { .compatible = "qcom,rpmcc-msm8916", .data = &rpm_clk_msm8916 }, { .compatible = "qcom,rpmcc-msm8974", .data = &rpm_clk_msm8974 }, { .compatible = "qcom,rpmcc-msm8996", .data = &rpm_clk_msm8996 }, + { .compatible = "qcom,rpmcc-qcs404", .data = &rpm_clk_qcs404 }, { } }; MODULE_DEVICE_TABLE(of, rpm_smd_clk_match_table); diff --git a/include/dt-bindings/clock/qcom,rpmcc.h b/include/dt-bindings/clock/qcom,rpmcc.h index c585b82b9c05..3658b0c14966 100644 --- a/include/dt-bindings/clock/qcom,rpmcc.h +++ b/include/dt-bindings/clock/qcom,rpmcc.h @@ -123,5 +123,9 @@ #define RPM_SMD_DIV_A_CLK3 73 #define RPM_SMD_LN_BB_CLK 74 #define RPM_SMD_LN_BB_A_CLK 75 +#define RPM_SMD_BIMC_GPU_CLK 76 +#define RPM_SMD_BIMC_GPU_A_CLK 77 +#define RPM_SMD_QPIC_CLK 78 +#define RPM_SMD_QPIC_CLK_A 79 #endif -- cgit v1.2.3-59-g8ed1b From d357b3134c9a7b1b78f5bfb2cd92423b91407cda Mon Sep 17 00:00:00 2001 From: "A.s. Dong" Date: Thu, 1 Nov 2018 15:20:02 +0000 Subject: dt-bindings: fsl: scu: update power domain binding Update the power domain binding with #power-domain-cells 1 format. The first cell can be a global SCU power domain and the 2nd cell the device ID. With this approach, we may remove all the sub power domain nodes from device tree which can relief the device tree a lot. Cc: Shawn Guo Cc: Sascha Hauer Reviewed-by: Rob Herring Reviewed-by: Ulf Hansson Signed-off-by: Dong Aisheng Signed-off-by: Shawn Guo --- .../devicetree/bindings/arm/freescale/fsl,scu.txt | 37 +++++----------------- 1 file changed, 8 insertions(+), 29 deletions(-) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt b/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt index 46d0af1f0872..c20f38e56544 100644 --- a/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt +++ b/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt @@ -58,19 +58,11 @@ This binding for the SCU power domain providers uses the generic power domain binding[2]. Required properties: -- compatible: Should be "fsl,scu-pd". -- #address-cells: Should be 1. -- #size-cells: Should be 0. - -Required properties for power domain sub nodes: -- #power-domain-cells: Must be 0. - -Optional Properties: -- reg: Resource ID of this power domain. - No exist means uncontrollable by user. +- compatible: Should be "fsl,imx8qxp-scu-pd". +- #power-domain-cells: Must be 1. Contains the Resource ID used by + SCU commands. See detailed Resource ID list from: - include/dt-bindings/power/imx-rsrc.h -- power-domains: phandle pointing to the parent power domain. + include/dt-bindings/firmware/imx/rsrc.h Clock bindings based on SCU Message Protocol ------------------------------------------------------------ @@ -152,22 +144,9 @@ firmware { ... }; - imx8qx-pm { - compatible = "fsl,scu-pd"; - #address-cells = <1>; - #size-cells = <0>; - - pd_dma: dma-power-domain { - #power-domain-cells = <0>; - - pd_dma_lpuart0: dma-lpuart0@57 { - reg = ; - #power-domain-cells = <0>; - power-domains = <&pd_dma>; - }; - ... - }; - ... + pd: imx8qx-pd { + compatible = "fsl,imx8qxp-scu-pd"; + #power-domain-cells = <1>; }; }; }; @@ -179,5 +158,5 @@ serial@5a060000 { clocks = <&clk IMX8QXP_UART0_CLK>, <&clk IMX8QXP_UART0_IPG_CLK>; clock-names = "per", "ipg"; - power-domains = <&pd_dma_lpuart0>; + power-domains = <&pd IMX_SC_R_UART_0>; }; -- cgit v1.2.3-59-g8ed1b From 6c763077163d13901ed2d41a67c741a940b695ac Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Sun, 28 Oct 2018 13:08:57 +0100 Subject: dt-bindings: clock: meson8b: use the registers from the HHI syscon The clock controller on Meson8/Meson8m2 and Meson8b is part of a register region called "HHI". This register area contains more functionality than just a clock controller: - the clock controller - some reset controller bits - temperature sensor calibration coefficient (only on Meson8b and Meson8m2 - one one out of five TSC bits is stored in the HHI registers) - HDMI controller The HHI register area may be accessed concurrently. Allow this by using a "system controller" as parent node. Signed-off-by: Martin Blumenstingl Acked-by: Neil Armstrong Signed-off-by: Neil Armstrong Link: https://lkml.kernel.org/r/20181028120859.5735-2-martin.blumenstingl@googlemail.com --- .../devicetree/bindings/clock/amlogic,meson8b-clkc.txt | 13 +++++-------- 1 file changed, 5 insertions(+), 8 deletions(-) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt b/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt index b455c5aa9139..4d94091c1d2d 100644 --- a/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt +++ b/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt @@ -9,15 +9,13 @@ Required Properties: - "amlogic,meson8-clkc" for Meson8 (S802) SoCs - "amlogic,meson8b-clkc" for Meson8 (S805) SoCs - "amlogic,meson8m2-clkc" for Meson8m2 (S812) SoCs -- reg: it must be composed by two tuples: - 0) physical base address of the xtal register and length of memory - mapped region. - 1) physical base address of the clock controller and length of memory - mapped region. - - #clock-cells: should be 1. - #reset-cells: should be 1. +Parent node should have the following properties : +- compatible: "amlogic,meson-hhi-sysctrl", "simple-mfd", "syscon" +- reg: base address and size of the HHI system control register space. + Each clock is assigned an identifier and client nodes can use this identifier to specify the clock which they consume. All available clocks are defined as preprocessor macros in the dt-bindings/clock/meson8b-clkc.h header and can be @@ -30,9 +28,8 @@ device tree sources). Example: Clock controller node: - clkc: clock-controller@c1104000 { + clkc: clock-controller { compatible = "amlogic,meson8b-clkc"; - reg = <0xc1108000 0x4>, <0xc1104000 0x460>; #clock-cells = <1>; #reset-cells = <1>; }; -- cgit v1.2.3-59-g8ed1b From e431c92188a9b76c16707302a9fe848a70982c13 Mon Sep 17 00:00:00 2001 From: Amit Nischal Date: Sun, 25 Nov 2018 10:06:07 +0530 Subject: dt-bindings: clock: Introduce QCOM Graphics clock bindings Add device tree bindings for graphics clock controller for Qualcomm Technology Inc's SDM845 SoCs. Signed-off-by: Amit Nischal Reviewed-by: Rob Herring [sboyd@kernel.org: Add input clocks property] Signed-off-by: Stephen Boyd --- .../devicetree/bindings/clock/qcom,gpucc.txt | 22 ++++++++++++++++++++ include/dt-bindings/clock/qcom,gpucc-sdm845.h | 24 ++++++++++++++++++++++ 2 files changed, 46 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,gpucc.txt create mode 100644 include/dt-bindings/clock/qcom,gpucc-sdm845.h (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/clock/qcom,gpucc.txt b/Documentation/devicetree/bindings/clock/qcom,gpucc.txt new file mode 100644 index 000000000000..9d0358cc08b4 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,gpucc.txt @@ -0,0 +1,22 @@ +Qualcomm Graphics Clock & Reset Controller Binding +-------------------------------------------------- + +Required properties : +- compatible : shall contain "qcom,sdm845-gpucc" +- reg : shall contain base register location and length +- #clock-cells : from common clock binding, shall contain 1 +- #reset-cells : from common reset binding, shall contain 1 +- #power-domain-cells : from generic power domain binding, shall contain 1 +- clocks : shall contain the XO clock +- clock-names : shall be "xo" + +Example: + gpucc: clock-controller@5090000 { + compatible = "qcom,sdm845-gpucc"; + reg = <0x5090000 0x9000>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + clocks = <&xo_board>; + clock-names = "xo"; + }; diff --git a/include/dt-bindings/clock/qcom,gpucc-sdm845.h b/include/dt-bindings/clock/qcom,gpucc-sdm845.h new file mode 100644 index 000000000000..9690d901b50a --- /dev/null +++ b/include/dt-bindings/clock/qcom,gpucc-sdm845.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_SDM_GPU_CC_SDM845_H +#define _DT_BINDINGS_CLK_SDM_GPU_CC_SDM845_H + +/* GPU_CC clock registers */ +#define GPU_CC_CX_GMU_CLK 0 +#define GPU_CC_CXO_CLK 1 +#define GPU_CC_GMU_CLK_SRC 2 +#define GPU_CC_PLL1 3 + +/* GPU_CC Resets */ +#define GPUCC_GPU_CC_CX_BCR 0 +#define GPUCC_GPU_CC_GMU_BCR 1 +#define GPUCC_GPU_CC_XO_BCR 2 + +/* GPU_CC GDSCRs */ +#define GPU_CX_GDSC 0 +#define GPU_GX_GDSC 1 + +#endif -- cgit v1.2.3-59-g8ed1b From 922b8fae085d6561ef4a2d1527a14bfde82fd1e8 Mon Sep 17 00:00:00 2001 From: Douglas Anderson Date: Wed, 28 Nov 2018 10:57:42 -0800 Subject: dt-bindings: clock: qcom: Fix the xo parent in gpucc example In the bindings that landed for the gpucc we require that the XO clock (one possible parent of the gpucc) be listed. The code doesn't use this yet--this is just to allow us to move toward the day when it does use it. What the code does do today is to hardcode the parent name to "bi_tcxo". That's all well and good. ...but the example in the bindings shows this clock mapping to the clock "xo_board". On the current sdm845.dtsi file the "xo_board" clock is a fixed clock with an output name of "xo_board". The clock with the name "bi_tcxo" is actually provided by the RPMh Clock Controller. Presumably that's the one that was wanted. Let's update the example to make this clearer. Fixes: e431c92188a9 ("dt-bindings: clock: Introduce QCOM Graphics clock bindings") Signed-off-by: Douglas Anderson Signed-off-by: Stephen Boyd --- Documentation/devicetree/bindings/clock/qcom,gpucc.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/clock/qcom,gpucc.txt b/Documentation/devicetree/bindings/clock/qcom,gpucc.txt index 9d0358cc08b4..4e5215ef1acd 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gpucc.txt +++ b/Documentation/devicetree/bindings/clock/qcom,gpucc.txt @@ -17,6 +17,6 @@ Example: #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; - clocks = <&xo_board>; + clocks = <&rpmhcc RPMH_CXO_CLK>; clock-names = "xo"; }; -- cgit v1.2.3-59-g8ed1b From 0cd41af05f130adcce6050acade97ec0fb5069b9 Mon Sep 17 00:00:00 2001 From: Ryder Lee Date: Mon, 5 Nov 2018 16:43:56 +0800 Subject: dt-bindings: arm: mediatek: document clk bindings for MT7629 This patch adds the binding documentation for apmixedsys, infracfg, pciesys, pericfg, topckgen, ethsys, sgmiisys and ssusbsys for MT7629. Signed-off-by: Ryder Lee Reviewed-by: Rob Herring Signed-off-by: Stephen Boyd --- Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt | 1 + Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt | 1 + Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt | 1 + Documentation/devicetree/bindings/arm/mediatek/mediatek,pciesys.txt | 1 + Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.txt | 1 + Documentation/devicetree/bindings/arm/mediatek/mediatek,sgmiisys.txt | 1 + Documentation/devicetree/bindings/arm/mediatek/mediatek,ssusbsys.txt | 1 + Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt | 1 + 8 files changed, 8 insertions(+) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt index 4e4a3c0ab9ab..de4075413d91 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt @@ -11,6 +11,7 @@ Required Properties: - "mediatek,mt6797-apmixedsys" - "mediatek,mt7622-apmixedsys" - "mediatek,mt7623-apmixedsys", "mediatek,mt2701-apmixedsys" + - "mediatek,mt7629-apmixedsys" - "mediatek,mt8135-apmixedsys" - "mediatek,mt8173-apmixedsys" - #clock-cells: Must be 1 diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt index f17cfe64255d..6b7e8067e7aa 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt @@ -9,6 +9,7 @@ Required Properties: - "mediatek,mt2701-ethsys", "syscon" - "mediatek,mt7622-ethsys", "syscon" - "mediatek,mt7623-ethsys", "mediatek,mt2701-ethsys", "syscon" + - "mediatek,mt7629-ethsys", "syscon" - #clock-cells: Must be 1 - #reset-cells: Must be 1 diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt index 89f4272a1441..417bd83d1378 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt @@ -12,6 +12,7 @@ Required Properties: - "mediatek,mt6797-infracfg", "syscon" - "mediatek,mt7622-infracfg", "syscon" - "mediatek,mt7623-infracfg", "mediatek,mt2701-infracfg", "syscon" + - "mediatek,mt7629-infracfg", "syscon" - "mediatek,mt8135-infracfg", "syscon" - "mediatek,mt8173-infracfg", "syscon" - #clock-cells: Must be 1 diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,pciesys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pciesys.txt index 7fe5dc6097a6..d179a61536f4 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,pciesys.txt +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pciesys.txt @@ -7,6 +7,7 @@ Required Properties: - compatible: Should be: - "mediatek,mt7622-pciesys", "syscon" + - "mediatek,mt7629-pciesys", "syscon" - #clock-cells: Must be 1 - #reset-cells: Must be 1 diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.txt index 6755514deb80..4c7e478117a0 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.txt +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.txt @@ -11,6 +11,7 @@ Required Properties: - "mediatek,mt2712-pericfg", "syscon" - "mediatek,mt7622-pericfg", "syscon" - "mediatek,mt7623-pericfg", "mediatek,mt2701-pericfg", "syscon" + - "mediatek,mt7629-pericfg", "syscon" - "mediatek,mt8135-pericfg", "syscon" - "mediatek,mt8173-pericfg", "syscon" - #clock-cells: Must be 1 diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,sgmiisys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,sgmiisys.txt index d113b8e741f3..30cb645c0e54 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,sgmiisys.txt +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,sgmiisys.txt @@ -7,6 +7,7 @@ Required Properties: - compatible: Should be: - "mediatek,mt7622-sgmiisys", "syscon" + - "mediatek,mt7629-sgmiisys", "syscon" - #clock-cells: Must be 1 The SGMIISYS controller uses the common clk binding from diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ssusbsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ssusbsys.txt index b8184da2508c..7cb02c930613 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ssusbsys.txt +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ssusbsys.txt @@ -7,6 +7,7 @@ Required Properties: - compatible: Should be: - "mediatek,mt7622-ssusbsys", "syscon" + - "mediatek,mt7629-ssusbsys", "syscon" - #clock-cells: Must be 1 - #reset-cells: Must be 1 diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt index d849465b8c99..d160c2b4b6fe 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt @@ -11,6 +11,7 @@ Required Properties: - "mediatek,mt6797-topckgen" - "mediatek,mt7622-topckgen" - "mediatek,mt7623-topckgen", "mediatek,mt2701-topckgen" + - "mediatek,mt7629-topckgen" - "mediatek,mt8135-topckgen" - "mediatek,mt8173-topckgen" - #clock-cells: Must be 1 -- cgit v1.2.3-59-g8ed1b From c51ba54f6349e677d136dac4d45d628bf1f9524d Mon Sep 17 00:00:00 2001 From: Douglas Anderson Date: Tue, 27 Nov 2018 11:24:43 -0800 Subject: dt-bindings: clock: Require #reset-cells in sdm845-videocc The #reset-cells was listed as optional in the bindings for qcom,sdm845-videocc. There's no reason for it to be optional. As per Stephen [1]: > We should update the binding to make it a required property. It > doesn't make any sense why that property would be optional given > that the hardware either has support for resets or it doesn't. sdm845 support is still in its infancy so we shouldn't be affecting any real device trees by modifying the bindings here. [1] https://lkml.kernel.org/r/154330186815.88331.12720647562079303842@swboyd.mtv.corp.google.com Fixes: 84b66b211603 ("dt-bindings: clock: Introduce QCOM Video clock bindings") Suggested-by: Stephen Boyd Signed-off-by: Douglas Anderson Signed-off-by: Stephen Boyd --- Documentation/devicetree/bindings/clock/qcom,videocc.txt | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/clock/qcom,videocc.txt b/Documentation/devicetree/bindings/clock/qcom,videocc.txt index e7c035afa778..8a8622c65c5a 100644 --- a/Documentation/devicetree/bindings/clock/qcom,videocc.txt +++ b/Documentation/devicetree/bindings/clock/qcom,videocc.txt @@ -6,8 +6,6 @@ Required properties : - reg : shall contain base register location and length - #clock-cells : from common clock binding, shall contain 1. - #power-domain-cells : from generic power domain binding, shall contain 1. - -Optional properties : - #reset-cells : from common reset binding, shall contain 1. Example: @@ -16,4 +14,5 @@ Example: reg = <0xab00000 0x10000>; #clock-cells = <1>; #power-domain-cells = <1>; + #reset-cells = <1>; }; -- cgit v1.2.3-59-g8ed1b From 7898e4fef8352ef8a0d2bbd13c10fcc77c38e80e Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Fri, 30 Nov 2018 23:51:27 +0530 Subject: dt-bindings: clock: Update GCC bindings for protected-clocks Add protected-clocks list which could used to specify the clocks to be bypassed on certain devices. Reviewed-by: Rob Herring Signed-off-by: Taniya Das Signed-off-by: Stephen Boyd --- Documentation/devicetree/bindings/clock/qcom,gcc.txt | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc.txt b/Documentation/devicetree/bindings/clock/qcom,gcc.txt index 52d9345c9927..5e37de95bfe8 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc.txt +++ b/Documentation/devicetree/bindings/clock/qcom,gcc.txt @@ -35,6 +35,8 @@ be part of GCC and hence the TSENS properties can also be part of the GCC/clock-controller node. For more details on the TSENS properties please refer Documentation/devicetree/bindings/thermal/qcom-tsens.txt +- protected-clocks : Protected clock specifier list as per common clock + binding. Example: clock-controller@900000 { @@ -55,3 +57,15 @@ Example of GCC with TSENS properties: #reset-cells = <1>; #thermal-sensor-cells = <1>; }; + +Example of GCC with protected-clocks properties: + clock-controller@100000 { + compatible = "qcom,gcc-sdm845"; + reg = <0x100000 0x1f0000>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + protected-clocks = , + , + ; + }; -- cgit v1.2.3-59-g8ed1b From 8ff1a156cb0b40a267fe7a2c69c06a6d566a7524 Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Fri, 30 Nov 2018 23:51:28 +0530 Subject: dt-bindings: clock: Introduce QCOM LPASS clock bindings Add device tree bindings for Low Power Audio subsystem clock controller for Qualcomm Technology Inc's SDM845 SoCs. Reviewed-by: Rob Herring Signed-off-by: Taniya Das Signed-off-by: Stephen Boyd --- .../devicetree/bindings/clock/qcom,gcc.txt | 4 +++- .../devicetree/bindings/clock/qcom,lpasscc.txt | 26 ++++++++++++++++++++++ include/dt-bindings/clock/qcom,gcc-sdm845.h | 2 ++ include/dt-bindings/clock/qcom,lpass-sdm845.h | 15 +++++++++++++ 4 files changed, 46 insertions(+), 1 deletion(-) create mode 100644 Documentation/devicetree/bindings/clock/qcom,lpasscc.txt create mode 100644 include/dt-bindings/clock/qcom,lpass-sdm845.h (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc.txt b/Documentation/devicetree/bindings/clock/qcom,gcc.txt index 5e37de95bfe8..8661c3cd3ccf 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc.txt +++ b/Documentation/devicetree/bindings/clock/qcom,gcc.txt @@ -67,5 +67,7 @@ Example of GCC with protected-clocks properties: #power-domain-cells = <1>; protected-clocks = , , - ; + , + , + ; }; diff --git a/Documentation/devicetree/bindings/clock/qcom,lpasscc.txt b/Documentation/devicetree/bindings/clock/qcom,lpasscc.txt new file mode 100644 index 000000000000..b9e9787045b9 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,lpasscc.txt @@ -0,0 +1,26 @@ +Qualcomm LPASS Clock Controller Binding +----------------------------------------------- + +Required properties : +- compatible : shall contain "qcom,sdm845-lpasscc" +- #clock-cells : from common clock binding, shall contain 1. +- reg : shall contain base register address and size, + in the order + Index-0 maps to LPASS_CC register region + Index-1 maps to LPASS_QDSP6SS register region + +Optional properties : +- reg-names : register names of LPASS domain + "cc", "qdsp6ss". + +Example: + +The below node has to be defined in the cases where the LPASS peripheral loader +would bring the subsystem out of reset. + + lpasscc: clock-controller@17014000 { + compatible = "qcom,sdm845-lpasscc"; + reg = <0x17014000 0x1f004>, <0x17300000 0x200>; + reg-names = "cc", "qdsp6ss"; + #clock-cells = <1>; + }; diff --git a/include/dt-bindings/clock/qcom,gcc-sdm845.h b/include/dt-bindings/clock/qcom,gcc-sdm845.h index b8eae5a76503..968fa65b9c42 100644 --- a/include/dt-bindings/clock/qcom,gcc-sdm845.h +++ b/include/dt-bindings/clock/qcom,gcc-sdm845.h @@ -197,6 +197,8 @@ #define GCC_QSPI_CORE_CLK_SRC 187 #define GCC_QSPI_CORE_CLK 188 #define GCC_QSPI_CNOC_PERIPH_AHB_CLK 189 +#define GCC_LPASS_Q6_AXI_CLK 190 +#define GCC_LPASS_SWAY_CLK 191 /* GCC Resets */ #define GCC_MMSS_BCR 0 diff --git a/include/dt-bindings/clock/qcom,lpass-sdm845.h b/include/dt-bindings/clock/qcom,lpass-sdm845.h new file mode 100644 index 000000000000..659050846f61 --- /dev/null +++ b/include/dt-bindings/clock/qcom,lpass-sdm845.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_SDM_LPASS_SDM845_H +#define _DT_BINDINGS_CLK_SDM_LPASS_SDM845_H + +#define LPASS_Q6SS_AHBM_AON_CLK 0 +#define LPASS_Q6SS_AHBS_AON_CLK 1 +#define LPASS_QDSP6SS_XO_CLK 2 +#define LPASS_QDSP6SS_SLEEP_CLK 3 +#define LPASS_QDSP6SS_CORE_CLK 4 + +#endif -- cgit v1.2.3-59-g8ed1b From 1cf3817bf1f52e57b3f5eb0413ee0d7f0c2e9829 Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Sat, 1 Dec 2018 10:52:10 +0000 Subject: dt-bindings: Add binding for i.MX8MQ CCM This adds the binding for the i.MX8MQ Clock Controller Module. Signed-off-by: Lucas Stach Signed-off-by: Abel Vesa Reviewed-by: Rob Herring Signed-off-by: Stephen Boyd --- .../devicetree/bindings/clock/imx8mq-clock.txt | 20 ++ include/dt-bindings/clock/imx8mq-clock.h | 395 +++++++++++++++++++++ 2 files changed, 415 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/imx8mq-clock.txt create mode 100644 include/dt-bindings/clock/imx8mq-clock.h (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/clock/imx8mq-clock.txt b/Documentation/devicetree/bindings/clock/imx8mq-clock.txt new file mode 100644 index 000000000000..52de8263e012 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/imx8mq-clock.txt @@ -0,0 +1,20 @@ +* Clock bindings for NXP i.MX8M Quad + +Required properties: +- compatible: Should be "fsl,imx8mq-ccm" +- reg: Address and length of the register set +- #clock-cells: Should be <1> +- clocks: list of clock specifiers, must contain an entry for each required + entry in clock-names +- clock-names: should include the following entries: + - "ckil" + - "osc_25m" + - "osc_27m" + - "clk_ext1" + - "clk_ext2" + - "clk_ext3" + - "clk_ext4" + +The clock consumer should specify the desired clock by having the clock +ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx8mq-clock.h +for the full list of i.MX8M Quad clock IDs. diff --git a/include/dt-bindings/clock/imx8mq-clock.h b/include/dt-bindings/clock/imx8mq-clock.h new file mode 100644 index 000000000000..b53be41929be --- /dev/null +++ b/include/dt-bindings/clock/imx8mq-clock.h @@ -0,0 +1,395 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + */ + +#ifndef __DT_BINDINGS_CLOCK_IMX8MQ_H +#define __DT_BINDINGS_CLOCK_IMX8MQ_H + +#define IMX8MQ_CLK_DUMMY 0 +#define IMX8MQ_CLK_32K 1 +#define IMX8MQ_CLK_25M 2 +#define IMX8MQ_CLK_27M 3 +#define IMX8MQ_CLK_EXT1 4 +#define IMX8MQ_CLK_EXT2 5 +#define IMX8MQ_CLK_EXT3 6 +#define IMX8MQ_CLK_EXT4 7 + +/* ANAMIX PLL clocks */ +/* FRAC PLLs */ +/* ARM PLL */ +#define IMX8MQ_ARM_PLL_REF_SEL 8 +#define IMX8MQ_ARM_PLL_REF_DIV 9 +#define IMX8MQ_ARM_PLL 10 +#define IMX8MQ_ARM_PLL_BYPASS 11 +#define IMX8MQ_ARM_PLL_OUT 12 + +/* GPU PLL */ +#define IMX8MQ_GPU_PLL_REF_SEL 13 +#define IMX8MQ_GPU_PLL_REF_DIV 14 +#define IMX8MQ_GPU_PLL 15 +#define IMX8MQ_GPU_PLL_BYPASS 16 +#define IMX8MQ_GPU_PLL_OUT 17 + +/* VPU PLL */ +#define IMX8MQ_VPU_PLL_REF_SEL 18 +#define IMX8MQ_VPU_PLL_REF_DIV 19 +#define IMX8MQ_VPU_PLL 20 +#define IMX8MQ_VPU_PLL_BYPASS 21 +#define IMX8MQ_VPU_PLL_OUT 22 + +/* AUDIO PLL1 */ +#define IMX8MQ_AUDIO_PLL1_REF_SEL 23 +#define IMX8MQ_AUDIO_PLL1_REF_DIV 24 +#define IMX8MQ_AUDIO_PLL1 25 +#define IMX8MQ_AUDIO_PLL1_BYPASS 26 +#define IMX8MQ_AUDIO_PLL1_OUT 27 + +/* AUDIO PLL2 */ +#define IMX8MQ_AUDIO_PLL2_REF_SEL 28 +#define IMX8MQ_AUDIO_PLL2_REF_DIV 29 +#define IMX8MQ_AUDIO_PLL2 30 +#define IMX8MQ_AUDIO_PLL2_BYPASS 31 +#define IMX8MQ_AUDIO_PLL2_OUT 32 + +/* VIDEO PLL1 */ +#define IMX8MQ_VIDEO_PLL1_REF_SEL 33 +#define IMX8MQ_VIDEO_PLL1_REF_DIV 34 +#define IMX8MQ_VIDEO_PLL1 35 +#define IMX8MQ_VIDEO_PLL1_BYPASS 36 +#define IMX8MQ_VIDEO_PLL1_OUT 37 + +/* SYS1 PLL */ +#define IMX8MQ_SYS1_PLL1_REF_SEL 38 +#define IMX8MQ_SYS1_PLL1_REF_DIV 39 +#define IMX8MQ_SYS1_PLL1 40 +#define IMX8MQ_SYS1_PLL1_OUT 41 +#define IMX8MQ_SYS1_PLL1_OUT_DIV 42 +#define IMX8MQ_SYS1_PLL2 43 +#define IMX8MQ_SYS1_PLL2_DIV 44 +#define IMX8MQ_SYS1_PLL2_OUT 45 + +/* SYS2 PLL */ +#define IMX8MQ_SYS2_PLL1_REF_SEL 46 +#define IMX8MQ_SYS2_PLL1_REF_DIV 47 +#define IMX8MQ_SYS2_PLL1 48 +#define IMX8MQ_SYS2_PLL1_OUT 49 +#define IMX8MQ_SYS2_PLL1_OUT_DIV 50 +#define IMX8MQ_SYS2_PLL2 51 +#define IMX8MQ_SYS2_PLL2_DIV 52 +#define IMX8MQ_SYS2_PLL2_OUT 53 + +/* SYS3 PLL */ +#define IMX8MQ_SYS3_PLL1_REF_SEL 54 +#define IMX8MQ_SYS3_PLL1_REF_DIV 55 +#define IMX8MQ_SYS3_PLL1 56 +#define IMX8MQ_SYS3_PLL1_OUT 57 +#define IMX8MQ_SYS3_PLL1_OUT_DIV 58 +#define IMX8MQ_SYS3_PLL2 59 +#define IMX8MQ_SYS3_PLL2_DIV 60 +#define IMX8MQ_SYS3_PLL2_OUT 61 + +/* DRAM PLL */ +#define IMX8MQ_DRAM_PLL1_REF_SEL 62 +#define IMX8MQ_DRAM_PLL1_REF_DIV 63 +#define IMX8MQ_DRAM_PLL1 64 +#define IMX8MQ_DRAM_PLL1_OUT 65 +#define IMX8MQ_DRAM_PLL1_OUT_DIV 66 +#define IMX8MQ_DRAM_PLL2 67 +#define IMX8MQ_DRAM_PLL2_DIV 68 +#define IMX8MQ_DRAM_PLL2_OUT 69 + +/* SYS PLL DIV */ +#define IMX8MQ_SYS1_PLL_40M 70 +#define IMX8MQ_SYS1_PLL_80M 71 +#define IMX8MQ_SYS1_PLL_100M 72 +#define IMX8MQ_SYS1_PLL_133M 73 +#define IMX8MQ_SYS1_PLL_160M 74 +#define IMX8MQ_SYS1_PLL_200M 75 +#define IMX8MQ_SYS1_PLL_266M 76 +#define IMX8MQ_SYS1_PLL_400M 77 +#define IMX8MQ_SYS1_PLL_800M 78 + +#define IMX8MQ_SYS2_PLL_50M 79 +#define IMX8MQ_SYS2_PLL_100M 80 +#define IMX8MQ_SYS2_PLL_125M 81 +#define IMX8MQ_SYS2_PLL_166M 82 +#define IMX8MQ_SYS2_PLL_200M 83 +#define IMX8MQ_SYS2_PLL_250M 84 +#define IMX8MQ_SYS2_PLL_333M 85 +#define IMX8MQ_SYS2_PLL_500M 86 +#define IMX8MQ_SYS2_PLL_1000M 87 + +/* CCM ROOT clocks */ +/* A53 */ +#define IMX8MQ_CLK_A53_SRC 88 +#define IMX8MQ_CLK_A53_CG 89 +#define IMX8MQ_CLK_A53_DIV 90 +/* M4 */ +#define IMX8MQ_CLK_M4_SRC 91 +#define IMX8MQ_CLK_M4_CG 92 +#define IMX8MQ_CLK_M4_DIV 93 +/* VPU */ +#define IMX8MQ_CLK_VPU_SRC 94 +#define IMX8MQ_CLK_VPU_CG 95 +#define IMX8MQ_CLK_VPU_DIV 96 +/* GPU CORE */ +#define IMX8MQ_CLK_GPU_CORE_SRC 97 +#define IMX8MQ_CLK_GPU_CORE_CG 98 +#define IMX8MQ_CLK_GPU_CORE_DIV 99 +/* GPU SHADER */ +#define IMX8MQ_CLK_GPU_SHADER_SRC 100 +#define IMX8MQ_CLK_GPU_SHADER_CG 101 +#define IMX8MQ_CLK_GPU_SHADER_DIV 102 + +/* BUS TYPE */ +/* MAIN AXI */ +#define IMX8MQ_CLK_MAIN_AXI 103 +/* ENET AXI */ +#define IMX8MQ_CLK_ENET_AXI 104 +/* NAND_USDHC_BUS */ +#define IMX8MQ_CLK_NAND_USDHC_BUS 105 +/* VPU BUS */ +#define IMX8MQ_CLK_VPU_BUS 106 +/* DISP_AXI */ +#define IMX8MQ_CLK_DISP_AXI 107 +/* DISP APB */ +#define IMX8MQ_CLK_DISP_APB 108 +/* DISP RTRM */ +#define IMX8MQ_CLK_DISP_RTRM 109 +/* USB_BUS */ +#define IMX8MQ_CLK_USB_BUS 110 +/* GPU_AXI */ +#define IMX8MQ_CLK_GPU_AXI 111 +/* GPU_AHB */ +#define IMX8MQ_CLK_GPU_AHB 112 +/* NOC */ +#define IMX8MQ_CLK_NOC 113 +/* NOC_APB */ +#define IMX8MQ_CLK_NOC_APB 115 + +/* AHB */ +#define IMX8MQ_CLK_AHB 116 +/* AUDIO AHB */ +#define IMX8MQ_CLK_AUDIO_AHB 117 + +/* DRAM_ALT */ +#define IMX8MQ_CLK_DRAM_ALT 118 +/* DRAM APB */ +#define IMX8MQ_CLK_DRAM_APB 119 +/* VPU_G1 */ +#define IMX8MQ_CLK_VPU_G1 120 +/* VPU_G2 */ +#define IMX8MQ_CLK_VPU_G2 121 +/* DISP_DTRC */ +#define IMX8MQ_CLK_DISP_DTRC 122 +/* DISP_DC8000 */ +#define IMX8MQ_CLK_DISP_DC8000 123 +/* PCIE_CTRL */ +#define IMX8MQ_CLK_PCIE1_CTRL 124 +/* PCIE_PHY */ +#define IMX8MQ_CLK_PCIE1_PHY 125 +/* PCIE_AUX */ +#define IMX8MQ_CLK_PCIE1_AUX 126 +/* DC_PIXEL */ +#define IMX8MQ_CLK_DC_PIXEL 127 +/* LCDIF_PIXEL */ +#define IMX8MQ_CLK_LCDIF_PIXEL 128 +/* SAI1~6 */ +#define IMX8MQ_CLK_SAI1 129 + +#define IMX8MQ_CLK_SAI2 130 + +#define IMX8MQ_CLK_SAI3 131 + +#define IMX8MQ_CLK_SAI4 132 + +#define IMX8MQ_CLK_SAI5 133 + +#define IMX8MQ_CLK_SAI6 134 +/* SPDIF1 */ +#define IMX8MQ_CLK_SPDIF1 135 +/* SPDIF2 */ +#define IMX8MQ_CLK_SPDIF2 136 +/* ENET_REF */ +#define IMX8MQ_CLK_ENET_REF 137 +/* ENET_TIMER */ +#define IMX8MQ_CLK_ENET_TIMER 138 +/* ENET_PHY */ +#define IMX8MQ_CLK_ENET_PHY_REF 139 +/* NAND */ +#define IMX8MQ_CLK_NAND 140 +/* QSPI */ +#define IMX8MQ_CLK_QSPI 141 +/* USDHC1 */ +#define IMX8MQ_CLK_USDHC1 142 +/* USDHC2 */ +#define IMX8MQ_CLK_USDHC2 143 +/* I2C1 */ +#define IMX8MQ_CLK_I2C1 144 +/* I2C2 */ +#define IMX8MQ_CLK_I2C2 145 +/* I2C3 */ +#define IMX8MQ_CLK_I2C3 146 +/* I2C4 */ +#define IMX8MQ_CLK_I2C4 147 +/* UART1 */ +#define IMX8MQ_CLK_UART1 148 +/* UART2 */ +#define IMX8MQ_CLK_UART2 149 +/* UART3 */ +#define IMX8MQ_CLK_UART3 150 +/* UART4 */ +#define IMX8MQ_CLK_UART4 151 +/* USB_CORE_REF */ +#define IMX8MQ_CLK_USB_CORE_REF 152 +/* USB_PHY_REF */ +#define IMX8MQ_CLK_USB_PHY_REF 163 +/* ECSPI1 */ +#define IMX8MQ_CLK_ECSPI1 164 +/* ECSPI2 */ +#define IMX8MQ_CLK_ECSPI2 165 +/* PWM1 */ +#define IMX8MQ_CLK_PWM1 166 +/* PWM2 */ +#define IMX8MQ_CLK_PWM2 167 +/* PWM3 */ +#define IMX8MQ_CLK_PWM3 168 +/* PWM4 */ +#define IMX8MQ_CLK_PWM4 169 +/* GPT1 */ +#define IMX8MQ_CLK_GPT1 170 +/* WDOG */ +#define IMX8MQ_CLK_WDOG 171 +/* WRCLK */ +#define IMX8MQ_CLK_WRCLK 172 +/* DSI_CORE */ +#define IMX8MQ_CLK_DSI_CORE 173 +/* DSI_PHY */ +#define IMX8MQ_CLK_DSI_PHY_REF 174 +/* DSI_DBI */ +#define IMX8MQ_CLK_DSI_DBI 175 +/*DSI_ESC */ +#define IMX8MQ_CLK_DSI_ESC 176 +/* CSI1_CORE */ +#define IMX8MQ_CLK_CSI1_CORE 177 +/* CSI1_PHY */ +#define IMX8MQ_CLK_CSI1_PHY_REF 178 +/* CSI_ESC */ +#define IMX8MQ_CLK_CSI1_ESC 179 +/* CSI2_CORE */ +#define IMX8MQ_CLK_CSI2_CORE 170 +/* CSI2_PHY */ +#define IMX8MQ_CLK_CSI2_PHY_REF 181 +/* CSI2_ESC */ +#define IMX8MQ_CLK_CSI2_ESC 182 +/* PCIE2_CTRL */ +#define IMX8MQ_CLK_PCIE2_CTRL 183 +/* PCIE2_PHY */ +#define IMX8MQ_CLK_PCIE2_PHY 184 +/* PCIE2_AUX */ +#define IMX8MQ_CLK_PCIE2_AUX 185 +/* ECSPI3 */ +#define IMX8MQ_CLK_ECSPI3 186 + +/* CCGR clocks */ +#define IMX8MQ_CLK_A53_ROOT 187 +#define IMX8MQ_CLK_DRAM_ROOT 188 +#define IMX8MQ_CLK_ECSPI1_ROOT 189 +#define IMX8MQ_CLK_ECSPI2_ROOT 180 +#define IMX8MQ_CLK_ECSPI3_ROOT 181 +#define IMX8MQ_CLK_ENET1_ROOT 182 +#define IMX8MQ_CLK_GPT1_ROOT 193 +#define IMX8MQ_CLK_I2C1_ROOT 194 +#define IMX8MQ_CLK_I2C2_ROOT 195 +#define IMX8MQ_CLK_I2C3_ROOT 196 +#define IMX8MQ_CLK_I2C4_ROOT 197 +#define IMX8MQ_CLK_M4_ROOT 198 +#define IMX8MQ_CLK_PCIE1_ROOT 199 +#define IMX8MQ_CLK_PCIE2_ROOT 200 +#define IMX8MQ_CLK_PWM1_ROOT 201 +#define IMX8MQ_CLK_PWM2_ROOT 202 +#define IMX8MQ_CLK_PWM3_ROOT 203 +#define IMX8MQ_CLK_PWM4_ROOT 204 +#define IMX8MQ_CLK_QSPI_ROOT 205 +#define IMX8MQ_CLK_SAI1_ROOT 206 +#define IMX8MQ_CLK_SAI2_ROOT 207 +#define IMX8MQ_CLK_SAI3_ROOT 208 +#define IMX8MQ_CLK_SAI4_ROOT 209 +#define IMX8MQ_CLK_SAI5_ROOT 210 +#define IMX8MQ_CLK_SAI6_ROOT 212 +#define IMX8MQ_CLK_UART1_ROOT 213 +#define IMX8MQ_CLK_UART2_ROOT 214 +#define IMX8MQ_CLK_UART3_ROOT 215 +#define IMX8MQ_CLK_UART4_ROOT 216 +#define IMX8MQ_CLK_USB1_CTRL_ROOT 217 +#define IMX8MQ_CLK_USB2_CTRL_ROOT 218 +#define IMX8MQ_CLK_USB1_PHY_ROOT 219 +#define IMX8MQ_CLK_USB2_PHY_ROOT 220 +#define IMX8MQ_CLK_USDHC1_ROOT 221 +#define IMX8MQ_CLK_USDHC2_ROOT 222 +#define IMX8MQ_CLK_WDOG1_ROOT 223 +#define IMX8MQ_CLK_WDOG2_ROOT 224 +#define IMX8MQ_CLK_WDOG3_ROOT 225 +#define IMX8MQ_CLK_GPU_ROOT 226 +#define IMX8MQ_CLK_HEVC_ROOT 227 +#define IMX8MQ_CLK_AVC_ROOT 228 +#define IMX8MQ_CLK_VP9_ROOT 229 +#define IMX8MQ_CLK_HEVC_INTER_ROOT 230 +#define IMX8MQ_CLK_DISP_ROOT 231 +#define IMX8MQ_CLK_HDMI_ROOT 232 +#define IMX8MQ_CLK_HDMI_PHY_ROOT 233 +#define IMX8MQ_CLK_VPU_DEC_ROOT 234 +#define IMX8MQ_CLK_CSI1_ROOT 235 +#define IMX8MQ_CLK_CSI2_ROOT 236 +#define IMX8MQ_CLK_RAWNAND_ROOT 237 +#define IMX8MQ_CLK_SDMA1_ROOT 238 +#define IMX8MQ_CLK_SDMA2_ROOT 239 +#define IMX8MQ_CLK_VPU_G1_ROOT 240 +#define IMX8MQ_CLK_VPU_G2_ROOT 241 + +/* SCCG PLL GATE */ +#define IMX8MQ_SYS1_PLL_OUT 232 +#define IMX8MQ_SYS2_PLL_OUT 243 +#define IMX8MQ_SYS3_PLL_OUT 244 +#define IMX8MQ_DRAM_PLL_OUT 245 + +#define IMX8MQ_GPT_3M_CLK 246 + +#define IMX8MQ_CLK_IPG_ROOT 247 +#define IMX8MQ_CLK_IPG_AUDIO_ROOT 248 +#define IMX8MQ_CLK_SAI1_IPG 249 +#define IMX8MQ_CLK_SAI2_IPG 250 +#define IMX8MQ_CLK_SAI3_IPG 251 +#define IMX8MQ_CLK_SAI4_IPG 252 +#define IMX8MQ_CLK_SAI5_IPG 253 +#define IMX8MQ_CLK_SAI6_IPG 254 + +/* DSI AHB/IPG clocks */ +/* rxesc clock */ +#define IMX8MQ_CLK_DSI_AHB 255 +/* txesc clock */ +#define IMX8MQ_CLK_DSI_IPG_DIV 256 + +#define IMX8MQ_CLK_TMU_ROOT 265 + +/* Display root clocks */ +#define IMX8MQ_CLK_DISP_AXI_ROOT 266 +#define IMX8MQ_CLK_DISP_APB_ROOT 267 +#define IMX8MQ_CLK_DISP_RTRM_ROOT 268 + +#define IMX8MQ_CLK_OCOTP_ROOT 269 + +#define IMX8MQ_CLK_DRAM_ALT_ROOT 270 +#define IMX8MQ_CLK_DRAM_CORE 271 + +#define IMX8MQ_CLK_MU_ROOT 272 +#define IMX8MQ_VIDEO2_PLL_OUT 273 + +#define IMX8MQ_CLK_CLKO2 274 + +#define IMX8MQ_CLK_NAND_USDHC_BUS_RAWNAND_CLK 275 + +#define IMX8MQ_CLK_END 276 +#endif /* __DT_BINDINGS_CLOCK_IMX8MQ_H */ -- cgit v1.2.3-59-g8ed1b From eb299e4d5708c1d95779997b3268aac1a1854bbf Mon Sep 17 00:00:00 2001 From: "A.s. Dong" Date: Wed, 14 Nov 2018 13:01:56 +0000 Subject: dt-bindings: clock: add imx7ulp clock binding doc i.MX7ULP Clock functions are under joint control of the System Clock Generation (SCG) modules, Peripheral Clock Control (PCC) modules, and Core Mode Controller (CMC)1 blocks Note IMX7ULP has two clock domains: M4 and A7. This binding doc is only for A7 clock domain. Cc: Rob Herring Cc: Mark Rutland Cc: Stephen Boyd Cc: Michael Turquette Cc: Shawn Guo Cc: Anson Huang Cc: Bai Ping Signed-off-by: Dong Aisheng Signed-off-by: Stephen Boyd --- .../devicetree/bindings/clock/imx7ulp-clock.txt | 104 ++++++++++++++++++++ include/dt-bindings/clock/imx7ulp-clock.h | 109 +++++++++++++++++++++ 2 files changed, 213 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/imx7ulp-clock.txt create mode 100644 include/dt-bindings/clock/imx7ulp-clock.h (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/clock/imx7ulp-clock.txt b/Documentation/devicetree/bindings/clock/imx7ulp-clock.txt new file mode 100644 index 000000000000..a4f8cd478f92 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/imx7ulp-clock.txt @@ -0,0 +1,104 @@ +* Clock bindings for Freescale i.MX7ULP + +i.MX7ULP Clock functions are under joint control of the System +Clock Generation (SCG) modules, Peripheral Clock Control (PCC) +modules, and Core Mode Controller (CMC)1 blocks + +The clocking scheme provides clear separation between M4 domain +and A7 domain. Except for a few clock sources shared between two +domains, such as the System Oscillator clock, the Slow IRC (SIRC), +and and the Fast IRC clock (FIRCLK), clock sources and clock +management are separated and contained within each domain. + +M4 clock management consists of SCG0, PCC0, PCC1, and CMC0 modules. +A7 clock management consists of SCG1, PCC2, PCC3, and CMC1 modules. + +Note: this binding doc is only for A7 clock domain. + +System Clock Generation (SCG) modules: +--------------------------------------------------------------------- +The System Clock Generation (SCG) is responsible for clock generation +and distribution across this device. Functions performed by the SCG +include: clock reference selection, generation of clock used to derive +processor, system, peripheral bus and external memory interface clocks, +source selection for peripheral clocks and control of power saving +clock gating mode. + +Required properties: + +- compatible: Should be "fsl,imx7ulp-scg1". +- reg : Should contain registers location and length. +- #clock-cells: Should be <1>. +- clocks: Should contain the fixed input clocks. +- clock-names: Should contain the following clock names: + "rosc", "sosc", "sirc", "firc", "upll", "mpll". + +Peripheral Clock Control (PCC) modules: +--------------------------------------------------------------------- +The Peripheral Clock Control (PCC) is responsible for clock selection, +optional division and clock gating mode for peripherals in their +respected power domain + +Required properties: +- compatible: Should be one of: + "fsl,imx7ulp-pcc2", + "fsl,imx7ulp-pcc3". +- reg : Should contain registers location and length. +- #clock-cells: Should be <1>. +- clocks: Should contain the fixed input clocks. +- clock-names: Should contain the following clock names: + "nic1_bus_clk", "nic1_clk", "ddr_clk", "apll_pfd2", + "apll_pfd1", "apll_pfd0", "upll", "sosc_bus_clk", + "mpll", "firc_bus_clk", "rosc", "spll_bus_clk"; + +The clock consumer should specify the desired clock by having the clock +ID in its "clocks" phandle cell. +See include/dt-bindings/clock/imx7ulp-clock.h +for the full list of i.MX7ULP clock IDs of each module. + +Examples: + +#include + +scg1: scg1@403e0000 { + compatible = "fsl,imx7ulp-scg1; + reg = <0x403e0000 0x10000>; + clocks = <&rosc>, <&sosc>, <&sirc>, + <&firc>, <&upll>, <&mpll>; + clock-names = "rosc", "sosc", "sirc", + "firc", "upll", "mpll"; + #clock-cells = <1>; +}; + +pcc2: pcc2@403f0000 { + compatible = "fsl,imx7ulp-pcc2"; + reg = <0x403f0000 0x10000>; + #clock-cells = <1>; + clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>, + <&scg1 IMX7ULP_CLK_NIC1_DIV>, + <&scg1 IMX7ULP_CLK_DDR_DIV>, + <&scg1 IMX7ULP_CLK_APLL_PFD2>, + <&scg1 IMX7ULP_CLK_APLL_PFD1>, + <&scg1 IMX7ULP_CLK_APLL_PFD0>, + <&scg1 IMX7ULP_CLK_UPLL>, + <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>, + <&scg1 IMX7ULP_CLK_MIPI_PLL>, + <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>, + <&scg1 IMX7ULP_CLK_ROSC>, + <&scg1 IMX7ULP_CLK_SPLL_BUS_CLK>; + clock-names = "nic1_bus_clk", "nic1_clk", "ddr_clk", + "apll_pfd2", "apll_pfd1", "apll_pfd0", + "upll", "sosc_bus_clk", "mpll", + "firc_bus_clk", "rosc", "spll_bus_clk"; +}; + +usdhc1: usdhc@40380000 { + compatible = "fsl,imx7ulp-usdhc"; + reg = <0x40380000 0x10000>; + interrupts = ; + clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>, + <&scg1 IMX7ULP_CLK_NIC1_DIV>, + <&pcc2 IMX7ULP_CLK_USDHC1>; + clock-names ="ipg", "ahb", "per"; + bus-width = <4>; +}; diff --git a/include/dt-bindings/clock/imx7ulp-clock.h b/include/dt-bindings/clock/imx7ulp-clock.h new file mode 100644 index 000000000000..008c5ee144c2 --- /dev/null +++ b/include/dt-bindings/clock/imx7ulp-clock.h @@ -0,0 +1,109 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017~2018 NXP + * + */ + +#ifndef __DT_BINDINGS_CLOCK_IMX7ULP_H +#define __DT_BINDINGS_CLOCK_IMX7ULP_H + +/* SCG1 */ + +#define IMX7ULP_CLK_DUMMY 0 +#define IMX7ULP_CLK_ROSC 1 +#define IMX7ULP_CLK_SOSC 2 +#define IMX7ULP_CLK_FIRC 3 +#define IMX7ULP_CLK_SPLL_PRE_SEL 4 +#define IMX7ULP_CLK_SPLL_PRE_DIV 5 +#define IMX7ULP_CLK_SPLL 6 +#define IMX7ULP_CLK_SPLL_POST_DIV1 7 +#define IMX7ULP_CLK_SPLL_POST_DIV2 8 +#define IMX7ULP_CLK_SPLL_PFD0 9 +#define IMX7ULP_CLK_SPLL_PFD1 10 +#define IMX7ULP_CLK_SPLL_PFD2 11 +#define IMX7ULP_CLK_SPLL_PFD3 12 +#define IMX7ULP_CLK_SPLL_PFD_SEL 13 +#define IMX7ULP_CLK_SPLL_SEL 14 +#define IMX7ULP_CLK_APLL_PRE_SEL 15 +#define IMX7ULP_CLK_APLL_PRE_DIV 16 +#define IMX7ULP_CLK_APLL 17 +#define IMX7ULP_CLK_APLL_POST_DIV1 18 +#define IMX7ULP_CLK_APLL_POST_DIV2 19 +#define IMX7ULP_CLK_APLL_PFD0 20 +#define IMX7ULP_CLK_APLL_PFD1 21 +#define IMX7ULP_CLK_APLL_PFD2 22 +#define IMX7ULP_CLK_APLL_PFD3 23 +#define IMX7ULP_CLK_APLL_PFD_SEL 24 +#define IMX7ULP_CLK_APLL_SEL 25 +#define IMX7ULP_CLK_UPLL 26 +#define IMX7ULP_CLK_SYS_SEL 27 +#define IMX7ULP_CLK_CORE_DIV 28 +#define IMX7ULP_CLK_BUS_DIV 29 +#define IMX7ULP_CLK_PLAT_DIV 30 +#define IMX7ULP_CLK_DDR_SEL 31 +#define IMX7ULP_CLK_DDR_DIV 32 +#define IMX7ULP_CLK_NIC_SEL 33 +#define IMX7ULP_CLK_NIC0_DIV 34 +#define IMX7ULP_CLK_GPU_DIV 35 +#define IMX7ULP_CLK_NIC1_DIV 36 +#define IMX7ULP_CLK_NIC1_BUS_DIV 37 +#define IMX7ULP_CLK_NIC1_EXT_DIV 38 +#define IMX7ULP_CLK_MIPI_PLL 39 +#define IMX7ULP_CLK_SIRC 40 +#define IMX7ULP_CLK_SOSC_BUS_CLK 41 +#define IMX7ULP_CLK_FIRC_BUS_CLK 42 +#define IMX7ULP_CLK_SPLL_BUS_CLK 43 + +#define IMX7ULP_CLK_SCG1_END 44 + +/* PCC2 */ +#define IMX7ULP_CLK_DMA1 0 +#define IMX7ULP_CLK_RGPIO2P1 1 +#define IMX7ULP_CLK_FLEXBUS 2 +#define IMX7ULP_CLK_SEMA42_1 3 +#define IMX7ULP_CLK_DMA_MUX1 4 +#define IMX7ULP_CLK_SNVS 5 +#define IMX7ULP_CLK_CAAM 6 +#define IMX7ULP_CLK_LPTPM4 7 +#define IMX7ULP_CLK_LPTPM5 8 +#define IMX7ULP_CLK_LPIT1 9 +#define IMX7ULP_CLK_LPSPI2 10 +#define IMX7ULP_CLK_LPSPI3 11 +#define IMX7ULP_CLK_LPI2C4 12 +#define IMX7ULP_CLK_LPI2C5 13 +#define IMX7ULP_CLK_LPUART4 14 +#define IMX7ULP_CLK_LPUART5 15 +#define IMX7ULP_CLK_FLEXIO1 16 +#define IMX7ULP_CLK_USB0 17 +#define IMX7ULP_CLK_USB1 18 +#define IMX7ULP_CLK_USB_PHY 19 +#define IMX7ULP_CLK_USB_PL301 20 +#define IMX7ULP_CLK_USDHC0 21 +#define IMX7ULP_CLK_USDHC1 22 +#define IMX7ULP_CLK_WDG1 23 +#define IMX7ULP_CLK_WDG2 24 + +#define IMX7ULP_CLK_PCC2_END 25 + +/* PCC3 */ +#define IMX7ULP_CLK_LPTPM6 0 +#define IMX7ULP_CLK_LPTPM7 1 +#define IMX7ULP_CLK_LPI2C6 2 +#define IMX7ULP_CLK_LPI2C7 3 +#define IMX7ULP_CLK_LPUART6 4 +#define IMX7ULP_CLK_LPUART7 5 +#define IMX7ULP_CLK_VIU 6 +#define IMX7ULP_CLK_DSI 7 +#define IMX7ULP_CLK_LCDIF 8 +#define IMX7ULP_CLK_MMDC 9 +#define IMX7ULP_CLK_PCTLC 10 +#define IMX7ULP_CLK_PCTLD 11 +#define IMX7ULP_CLK_PCTLE 12 +#define IMX7ULP_CLK_PCTLF 13 +#define IMX7ULP_CLK_GPU3D 14 +#define IMX7ULP_CLK_GPU2D 15 + +#define IMX7ULP_CLK_PCC3_END 16 + +#endif /* __DT_BINDINGS_CLOCK_IMX7ULP_H */ -- cgit v1.2.3-59-g8ed1b From 3d737ddbe74c421ab5da563908484a06748e0211 Mon Sep 17 00:00:00 2001 From: Mesih Kilinc Date: Sun, 2 Dec 2018 23:23:46 +0300 Subject: dt-bindings: clock: Add Allwinner suniv F1C100s CCU Add compatiple string for Allwinner suniv F1C100s CCU. Add clock and reset definitions. Signed-off-by: Mesih Kilinc Acked-by: Maxime Ripard Acked-by: Stephen Boyd Signed-off-by: Maxime Ripard --- .../devicetree/bindings/clock/sunxi-ccu.txt | 1 + include/dt-bindings/clock/suniv-ccu-f1c100s.h | 70 ++++++++++++++++++++++ include/dt-bindings/reset/suniv-ccu-f1c100s.h | 38 ++++++++++++ 3 files changed, 109 insertions(+) create mode 100644 include/dt-bindings/clock/suniv-ccu-f1c100s.h create mode 100644 include/dt-bindings/reset/suniv-ccu-f1c100s.h (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt index 47d2e902ced4..e3bd88ae456b 100644 --- a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt +++ b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt @@ -22,6 +22,7 @@ Required properties : - "allwinner,sun50i-h5-ccu" - "allwinner,sun50i-h6-ccu" - "allwinner,sun50i-h6-r-ccu" + - "allwinner,suniv-f1c100s-ccu" - "nextthing,gr8-ccu" - reg: Must contain the registers base address and length diff --git a/include/dt-bindings/clock/suniv-ccu-f1c100s.h b/include/dt-bindings/clock/suniv-ccu-f1c100s.h new file mode 100644 index 000000000000..f5ac155c9c70 --- /dev/null +++ b/include/dt-bindings/clock/suniv-ccu-f1c100s.h @@ -0,0 +1,70 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) + * + * Copyright (c) 2018 Icenowy Zheng + * + */ + +#ifndef _DT_BINDINGS_CLK_SUNIV_F1C100S_H_ +#define _DT_BINDINGS_CLK_SUNIV_F1C100S_H_ + +#define CLK_CPU 11 + +#define CLK_BUS_DMA 14 +#define CLK_BUS_MMC0 15 +#define CLK_BUS_MMC1 16 +#define CLK_BUS_DRAM 17 +#define CLK_BUS_SPI0 18 +#define CLK_BUS_SPI1 19 +#define CLK_BUS_OTG 20 +#define CLK_BUS_VE 21 +#define CLK_BUS_LCD 22 +#define CLK_BUS_DEINTERLACE 23 +#define CLK_BUS_CSI 24 +#define CLK_BUS_TVD 25 +#define CLK_BUS_TVE 26 +#define CLK_BUS_DE_BE 27 +#define CLK_BUS_DE_FE 28 +#define CLK_BUS_CODEC 29 +#define CLK_BUS_SPDIF 30 +#define CLK_BUS_IR 31 +#define CLK_BUS_RSB 32 +#define CLK_BUS_I2S0 33 +#define CLK_BUS_I2C0 34 +#define CLK_BUS_I2C1 35 +#define CLK_BUS_I2C2 36 +#define CLK_BUS_PIO 37 +#define CLK_BUS_UART0 38 +#define CLK_BUS_UART1 39 +#define CLK_BUS_UART2 40 + +#define CLK_MMC0 41 +#define CLK_MMC0_SAMPLE 42 +#define CLK_MMC0_OUTPUT 43 +#define CLK_MMC1 44 +#define CLK_MMC1_SAMPLE 45 +#define CLK_MMC1_OUTPUT 46 +#define CLK_I2S 47 +#define CLK_SPDIF 48 + +#define CLK_USB_PHY0 49 + +#define CLK_DRAM_VE 50 +#define CLK_DRAM_CSI 51 +#define CLK_DRAM_DEINTERLACE 52 +#define CLK_DRAM_TVD 53 +#define CLK_DRAM_DE_FE 54 +#define CLK_DRAM_DE_BE 55 + +#define CLK_DE_BE 56 +#define CLK_DE_FE 57 +#define CLK_TCON 58 +#define CLK_DEINTERLACE 59 +#define CLK_TVE2_CLK 60 +#define CLK_TVE1_CLK 61 +#define CLK_TVD 62 +#define CLK_CSI 63 +#define CLK_VE 64 +#define CLK_CODEC 65 +#define CLK_AVS 66 + +#endif diff --git a/include/dt-bindings/reset/suniv-ccu-f1c100s.h b/include/dt-bindings/reset/suniv-ccu-f1c100s.h new file mode 100644 index 000000000000..6a4b4385fe5a --- /dev/null +++ b/include/dt-bindings/reset/suniv-ccu-f1c100s.h @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) + * + * Copyright (C) 2018 Icenowy Zheng + * + */ + +#ifndef _DT_BINDINGS_RST_SUNIV_F1C100S_H_ +#define _DT_BINDINGS_RST_SUNIV_F1C100S_H_ + +#define RST_USB_PHY0 0 +#define RST_BUS_DMA 1 +#define RST_BUS_MMC0 2 +#define RST_BUS_MMC1 3 +#define RST_BUS_DRAM 4 +#define RST_BUS_SPI0 5 +#define RST_BUS_SPI1 6 +#define RST_BUS_OTG 7 +#define RST_BUS_VE 8 +#define RST_BUS_LCD 9 +#define RST_BUS_DEINTERLACE 10 +#define RST_BUS_CSI 11 +#define RST_BUS_TVD 12 +#define RST_BUS_TVE 13 +#define RST_BUS_DE_BE 14 +#define RST_BUS_DE_FE 15 +#define RST_BUS_CODEC 16 +#define RST_BUS_SPDIF 17 +#define RST_BUS_IR 18 +#define RST_BUS_RSB 19 +#define RST_BUS_I2S0 20 +#define RST_BUS_I2C0 21 +#define RST_BUS_I2C1 22 +#define RST_BUS_I2C2 23 +#define RST_BUS_UART0 24 +#define RST_BUS_UART1 25 +#define RST_BUS_UART2 26 + +#endif /* _DT_BINDINGS_RST_SUNIV_F1C100S_H_ */ -- cgit v1.2.3-59-g8ed1b From a29be9185d195bf5abd5ff5482a26800d58bac19 Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Thu, 15 Nov 2018 15:30:27 +0100 Subject: clk: imx6q: optionally get CCM inputs via standard clock handles When specifying external clock inputs to the CCM the current code requires the clocks to be in a "clocks" child node of the DT root. This is not really conformant with DT best practices. To avoid the need to deviate from those best practices, allow the clock inputs to be specified via standard clock handles. This is in line with how drivers of the later CCM driver revisions on newer i.MX SoCs handle this. As we can't retroactively change the DT binding, allow this as an option with a fallback to the old way of how this has been handled. Signed-off-by: Lucas Stach Acked-by: Rob Herring Reviewed-by: Dong Aisheng Signed-off-by: Stephen Boyd --- .../devicetree/bindings/clock/imx6q-clock.txt | 3 +++ drivers/clk/imx/clk-imx6q.c | 22 +++++++++++++++++----- 2 files changed, 20 insertions(+), 5 deletions(-) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/clock/imx6q-clock.txt b/Documentation/devicetree/bindings/clock/imx6q-clock.txt index e1308346e00d..13d36d4c6991 100644 --- a/Documentation/devicetree/bindings/clock/imx6q-clock.txt +++ b/Documentation/devicetree/bindings/clock/imx6q-clock.txt @@ -13,6 +13,9 @@ Optional properties: management IC (PMIC) triggered via PMIC_STBY_REQ signal. Boards that are designed to initiate poweroff on PMIC_ON_REQ signal should be using "syscon-poweroff" driver instead. +- clocks: list of clock specifiers, must contain an entry for each entry + in clock-names +- clock-names: valid names are "osc", "ckil", "ckih1", "anaclk1" and "anaclk2" The clock consumer should specify the desired clock by having the clock ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx6qdl-clock.h diff --git a/drivers/clk/imx/clk-imx6q.c b/drivers/clk/imx/clk-imx6q.c index 59f6a3e087db..bd53c403bcc1 100644 --- a/drivers/clk/imx/clk-imx6q.c +++ b/drivers/clk/imx/clk-imx6q.c @@ -414,12 +414,24 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) int ret; clk[IMX6QDL_CLK_DUMMY] = imx_clk_fixed("dummy", 0); - clk[IMX6QDL_CLK_CKIL] = imx_obtain_fixed_clock("ckil", 0); - clk[IMX6QDL_CLK_CKIH] = imx_obtain_fixed_clock("ckih1", 0); - clk[IMX6QDL_CLK_OSC] = imx_obtain_fixed_clock("osc", 0); + clk[IMX6QDL_CLK_CKIL] = of_clk_get_by_name(ccm_node, "ckil"); + if (IS_ERR(clk[IMX6QDL_CLK_CKIL])) + clk[IMX6QDL_CLK_CKIL] = imx_obtain_fixed_clock("ckil", 0); + clk[IMX6QDL_CLK_CKIH] = of_clk_get_by_name(ccm_node, "ckih1"); + if (IS_ERR(clk[IMX6QDL_CLK_CKIH])) + clk[IMX6QDL_CLK_CKIH] = imx_obtain_fixed_clock("ckih1", 0); + clk[IMX6QDL_CLK_OSC] = of_clk_get_by_name(ccm_node, "osc"); + if (IS_ERR(clk[IMX6QDL_CLK_OSC])) + clk[IMX6QDL_CLK_OSC] = imx_obtain_fixed_clock("osc", 0); + /* Clock source from external clock via CLK1/2 PADs */ - clk[IMX6QDL_CLK_ANACLK1] = imx_obtain_fixed_clock("anaclk1", 0); - clk[IMX6QDL_CLK_ANACLK2] = imx_obtain_fixed_clock("anaclk2", 0); + clk[IMX6QDL_CLK_ANACLK1] = of_clk_get_by_name(ccm_node, "anaclk1"); + if (IS_ERR(clk[IMX6QDL_CLK_ANACLK1])) + clk[IMX6QDL_CLK_ANACLK1] = imx_obtain_fixed_clock("anaclk1", 0); + + clk[IMX6QDL_CLK_ANACLK2] = of_clk_get_by_name(ccm_node, "anaclk2"); + if (IS_ERR(clk[IMX6QDL_CLK_ANACLK2])) + clk[IMX6QDL_CLK_ANACLK2] = imx_obtain_fixed_clock("anaclk2", 0); np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-anatop"); anatop_base = base = of_iomap(np, 0); -- cgit v1.2.3-59-g8ed1b From 0f5ab411f5878274b41839bad8bdcc7af1fcaa27 Mon Sep 17 00:00:00 2001 From: Aisheng Dong Date: Thu, 13 Dec 2018 01:08:06 +0000 Subject: dt-bindings: clock: add imx8qxp lpcg clock binding The Low-Power Clock Gate (LPCG) modules contain a local programming model to control the clock gates for the peripherals. An LPCG module is used to locally gate the clocks for the associated peripheral. Note: This level of clock gating is provided after the clocks are generated by the SCU resources and clock controls. Thus even if the clock is enabled by these control bits, it might still not be running based on the base resource. Cc: Stephen Boyd Cc: Shawn Guo Cc: Sascha Hauer Cc: devicetree@vger.kernel.org Reviewed-by: Rob Herring Signed-off-by: Dong Aisheng Signed-off-by: Stephen Boyd --- .../devicetree/bindings/clock/imx8qxp-lpcg.txt | 51 +++++++ include/dt-bindings/clock/imx8qxp-clock.h | 153 +++++++++++++++++++++ 2 files changed, 204 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/imx8qxp-lpcg.txt (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/clock/imx8qxp-lpcg.txt b/Documentation/devicetree/bindings/clock/imx8qxp-lpcg.txt new file mode 100644 index 000000000000..965cfa42e025 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/imx8qxp-lpcg.txt @@ -0,0 +1,51 @@ +* NXP i.MX8QXP LPCG (Low-Power Clock Gating) Clock bindings + +The Low-Power Clock Gate (LPCG) modules contain a local programming +model to control the clock gates for the peripherals. An LPCG module +is used to locally gate the clocks for the associated peripheral. + +Note: +This level of clock gating is provided after the clocks are generated +by the SCU resources and clock controls. Thus even if the clock is +enabled by these control bits, it might still not be running based +on the base resource. + +Required properties: +- compatible: Should be one of: + "fsl,imx8qxp-lpcg-adma", + "fsl,imx8qxp-lpcg-conn", + "fsl,imx8qxp-lpcg-dc", + "fsl,imx8qxp-lpcg-dsp", + "fsl,imx8qxp-lpcg-gpu", + "fsl,imx8qxp-lpcg-hsio", + "fsl,imx8qxp-lpcg-img", + "fsl,imx8qxp-lpcg-lsio", + "fsl,imx8qxp-lpcg-vpu" +- reg: Address and length of the register set +- #clock-cells: Should be <1> + +The clock consumer should specify the desired clock by having the clock +ID in its "clocks" phandle cell. +See the full list of clock IDs from: +include/dt-bindings/clock/imx8qxp-clock.h + +Examples: + +#include + +conn_lpcg: clock-controller@5b200000 { + compatible = "fsl,imx8qxp-lpcg-conn"; + reg = <0x5b200000 0xb0000>; + #clock-cells = <1>; +}; + +usdhc1: mmc@5b010000 { + compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc"; + interrupt-parent = <&gic>; + interrupts = ; + reg = <0x5b010000 0x10000>; + clocks = <&conn_lpcg IMX8QXP_CONN_LPCG_SDHC0_IPG_CLK>, + <&conn_lpcg IMX8QXP_CONN_LPCG_SDHC0_PER_CLK>, + <&conn_lpcg IMX8QXP_CONN_LPCG_SDHC0_HCLK>; + clock-names = "ipg", "per", "ahb"; +}; diff --git a/include/dt-bindings/clock/imx8qxp-clock.h b/include/dt-bindings/clock/imx8qxp-clock.h index d72a39c2d721..6fec3687f3c7 100644 --- a/include/dt-bindings/clock/imx8qxp-clock.h +++ b/include/dt-bindings/clock/imx8qxp-clock.h @@ -133,4 +133,157 @@ #define IMX8QXP_SCU_CLK_END 190 +/* LPCG clocks */ + +/* LSIO SS LPCG */ +#define IMX8QXP_LSIO_LPCG_PWM0_IPG_CLK 0 +#define IMX8QXP_LSIO_LPCG_PWM0_IPG_S_CLK 1 +#define IMX8QXP_LSIO_LPCG_PWM0_IPG_HF_CLK 2 +#define IMX8QXP_LSIO_LPCG_PWM0_IPG_SLV_CLK 3 +#define IMX8QXP_LSIO_LPCG_PWM0_IPG_MSTR_CLK 4 +#define IMX8QXP_LSIO_LPCG_PWM1_IPG_CLK 5 +#define IMX8QXP_LSIO_LPCG_PWM1_IPG_S_CLK 6 +#define IMX8QXP_LSIO_LPCG_PWM1_IPG_HF_CLK 7 +#define IMX8QXP_LSIO_LPCG_PWM1_IPG_SLV_CLK 8 +#define IMX8QXP_LSIO_LPCG_PWM1_IPG_MSTR_CLK 9 +#define IMX8QXP_LSIO_LPCG_PWM2_IPG_CLK 10 +#define IMX8QXP_LSIO_LPCG_PWM2_IPG_S_CLK 11 +#define IMX8QXP_LSIO_LPCG_PWM2_IPG_HF_CLK 12 +#define IMX8QXP_LSIO_LPCG_PWM2_IPG_SLV_CLK 13 +#define IMX8QXP_LSIO_LPCG_PWM2_IPG_MSTR_CLK 14 +#define IMX8QXP_LSIO_LPCG_PWM3_IPG_CLK 15 +#define IMX8QXP_LSIO_LPCG_PWM3_IPG_S_CLK 16 +#define IMX8QXP_LSIO_LPCG_PWM3_IPG_HF_CLK 17 +#define IMX8QXP_LSIO_LPCG_PWM3_IPG_SLV_CLK 18 +#define IMX8QXP_LSIO_LPCG_PWM3_IPG_MSTR_CLK 19 +#define IMX8QXP_LSIO_LPCG_PWM4_IPG_CLK 20 +#define IMX8QXP_LSIO_LPCG_PWM4_IPG_S_CLK 21 +#define IMX8QXP_LSIO_LPCG_PWM4_IPG_HF_CLK 22 +#define IMX8QXP_LSIO_LPCG_PWM4_IPG_SLV_CLK 23 +#define IMX8QXP_LSIO_LPCG_PWM4_IPG_MSTR_CLK 24 +#define IMX8QXP_LSIO_LPCG_PWM5_IPG_CLK 25 +#define IMX8QXP_LSIO_LPCG_PWM5_IPG_S_CLK 26 +#define IMX8QXP_LSIO_LPCG_PWM5_IPG_HF_CLK 27 +#define IMX8QXP_LSIO_LPCG_PWM5_IPG_SLV_CLK 28 +#define IMX8QXP_LSIO_LPCG_PWM5_IPG_MSTR_CLK 29 +#define IMX8QXP_LSIO_LPCG_PWM6_IPG_CLK 30 +#define IMX8QXP_LSIO_LPCG_PWM6_IPG_S_CLK 31 +#define IMX8QXP_LSIO_LPCG_PWM6_IPG_HF_CLK 32 +#define IMX8QXP_LSIO_LPCG_PWM6_IPG_SLV_CLK 33 +#define IMX8QXP_LSIO_LPCG_PWM6_IPG_MSTR_CLK 34 +#define IMX8QXP_LSIO_LPCG_PWM7_IPG_CLK 35 +#define IMX8QXP_LSIO_LPCG_PWM7_IPG_S_CLK 36 +#define IMX8QXP_LSIO_LPCG_PWM7_IPG_HF_CLK 37 +#define IMX8QXP_LSIO_LPCG_PWM7_IPG_SLV_CLK 38 +#define IMX8QXP_LSIO_LPCG_PWM7_IPG_MSTR_CLK 39 +#define IMX8QXP_LSIO_LPCG_GPT0_IPG_CLK 40 +#define IMX8QXP_LSIO_LPCG_GPT0_IPG_S_CLK 41 +#define IMX8QXP_LSIO_LPCG_GPT0_IPG_HF_CLK 42 +#define IMX8QXP_LSIO_LPCG_GPT0_IPG_SLV_CLK 43 +#define IMX8QXP_LSIO_LPCG_GPT0_IPG_MSTR_CLK 44 +#define IMX8QXP_LSIO_LPCG_GPT1_IPG_CLK 45 +#define IMX8QXP_LSIO_LPCG_GPT1_IPG_S_CLK 46 +#define IMX8QXP_LSIO_LPCG_GPT1_IPG_HF_CLK 47 +#define IMX8QXP_LSIO_LPCG_GPT1_IPG_SLV_CLK 48 +#define IMX8QXP_LSIO_LPCG_GPT1_IPG_MSTR_CLK 49 +#define IMX8QXP_LSIO_LPCG_GPT2_IPG_CLK 50 +#define IMX8QXP_LSIO_LPCG_GPT2_IPG_S_CLK 51 +#define IMX8QXP_LSIO_LPCG_GPT2_IPG_HF_CLK 52 +#define IMX8QXP_LSIO_LPCG_GPT2_IPG_SLV_CLK 53 +#define IMX8QXP_LSIO_LPCG_GPT2_IPG_MSTR_CLK 54 +#define IMX8QXP_LSIO_LPCG_GPT3_IPG_CLK 55 +#define IMX8QXP_LSIO_LPCG_GPT3_IPG_S_CLK 56 +#define IMX8QXP_LSIO_LPCG_GPT3_IPG_HF_CLK 57 +#define IMX8QXP_LSIO_LPCG_GPT3_IPG_SLV_CLK 58 +#define IMX8QXP_LSIO_LPCG_GPT3_IPG_MSTR_CLK 59 +#define IMX8QXP_LSIO_LPCG_GPT4_IPG_CLK 60 +#define IMX8QXP_LSIO_LPCG_GPT4_IPG_S_CLK 61 +#define IMX8QXP_LSIO_LPCG_GPT4_IPG_HF_CLK 62 +#define IMX8QXP_LSIO_LPCG_GPT4_IPG_SLV_CLK 63 +#define IMX8QXP_LSIO_LPCG_GPT4_IPG_MSTR_CLK 64 +#define IMX8QXP_LSIO_LPCG_FSPI0_HCLK 65 +#define IMX8QXP_LSIO_LPCG_FSPI0_IPG_CLK 66 +#define IMX8QXP_LSIO_LPCG_FSPI0_IPG_S_CLK 67 +#define IMX8QXP_LSIO_LPCG_FSPI0_IPG_SFCK 68 +#define IMX8QXP_LSIO_LPCG_FSPI1_HCLK 69 +#define IMX8QXP_LSIO_LPCG_FSPI1_IPG_CLK 70 +#define IMX8QXP_LSIO_LPCG_FSPI1_IPG_S_CLK 71 +#define IMX8QXP_LSIO_LPCG_FSPI1_IPG_SFCK 72 + +#define IMX8QXP_LSIO_LPCG_CLK_END 73 + +/* Connectivity SS LPCG */ +#define IMX8QXP_CONN_LPCG_SDHC0_IPG_CLK 0 +#define IMX8QXP_CONN_LPCG_SDHC0_PER_CLK 1 +#define IMX8QXP_CONN_LPCG_SDHC0_HCLK 2 +#define IMX8QXP_CONN_LPCG_SDHC1_IPG_CLK 3 +#define IMX8QXP_CONN_LPCG_SDHC1_PER_CLK 4 +#define IMX8QXP_CONN_LPCG_SDHC1_HCLK 5 +#define IMX8QXP_CONN_LPCG_SDHC2_IPG_CLK 6 +#define IMX8QXP_CONN_LPCG_SDHC2_PER_CLK 7 +#define IMX8QXP_CONN_LPCG_SDHC2_HCLK 8 +#define IMX8QXP_CONN_LPCG_GPMI_APB_CLK 9 +#define IMX8QXP_CONN_LPCG_GPMI_BCH_APB_CLK 10 +#define IMX8QXP_CONN_LPCG_GPMI_BCH_IO_CLK 11 +#define IMX8QXP_CONN_LPCG_GPMI_BCH_CLK 12 +#define IMX8QXP_CONN_LPCG_APBHDMA_CLK 13 +#define IMX8QXP_CONN_LPCG_ENET0_ROOT_CLK 14 +#define IMX8QXP_CONN_LPCG_ENET0_TX_CLK 15 +#define IMX8QXP_CONN_LPCG_ENET0_AHB_CLK 16 +#define IMX8QXP_CONN_LPCG_ENET0_IPG_S_CLK 17 +#define IMX8QXP_CONN_LPCG_ENET0_IPG_CLK 18 + +#define IMX8QXP_CONN_LPCG_ENET1_ROOT_CLK 19 +#define IMX8QXP_CONN_LPCG_ENET1_TX_CLK 20 +#define IMX8QXP_CONN_LPCG_ENET1_AHB_CLK 21 +#define IMX8QXP_CONN_LPCG_ENET1_IPG_S_CLK 22 +#define IMX8QXP_CONN_LPCG_ENET1_IPG_CLK 23 + +#define IMX8QXP_CONN_LPCG_CLK_END 24 + +/* ADMA SS LPCG */ +#define IMX8QXP_ADMA_LPCG_UART0_IPG_CLK 0 +#define IMX8QXP_ADMA_LPCG_UART0_BAUD_CLK 1 +#define IMX8QXP_ADMA_LPCG_UART1_IPG_CLK 2 +#define IMX8QXP_ADMA_LPCG_UART1_BAUD_CLK 3 +#define IMX8QXP_ADMA_LPCG_UART2_IPG_CLK 4 +#define IMX8QXP_ADMA_LPCG_UART2_BAUD_CLK 5 +#define IMX8QXP_ADMA_LPCG_UART3_IPG_CLK 6 +#define IMX8QXP_ADMA_LPCG_UART3_BAUD_CLK 7 +#define IMX8QXP_ADMA_LPCG_SPI0_IPG_CLK 8 +#define IMX8QXP_ADMA_LPCG_SPI1_IPG_CLK 9 +#define IMX8QXP_ADMA_LPCG_SPI2_IPG_CLK 10 +#define IMX8QXP_ADMA_LPCG_SPI3_IPG_CLK 11 +#define IMX8QXP_ADMA_LPCG_SPI0_CLK 12 +#define IMX8QXP_ADMA_LPCG_SPI1_CLK 13 +#define IMX8QXP_ADMA_LPCG_SPI2_CLK 14 +#define IMX8QXP_ADMA_LPCG_SPI3_CLK 15 +#define IMX8QXP_ADMA_LPCG_CAN0_IPG_CLK 16 +#define IMX8QXP_ADMA_LPCG_CAN0_IPG_PE_CLK 17 +#define IMX8QXP_ADMA_LPCG_CAN0_IPG_CHI_CLK 18 +#define IMX8QXP_ADMA_LPCG_CAN1_IPG_CLK 19 +#define IMX8QXP_ADMA_LPCG_CAN1_IPG_PE_CLK 20 +#define IMX8QXP_ADMA_LPCG_CAN1_IPG_CHI_CLK 21 +#define IMX8QXP_ADMA_LPCG_CAN2_IPG_CLK 22 +#define IMX8QXP_ADMA_LPCG_CAN2_IPG_PE_CLK 23 +#define IMX8QXP_ADMA_LPCG_CAN2_IPG_CHI_CLK 24 +#define IMX8QXP_ADMA_LPCG_I2C0_CLK 25 +#define IMX8QXP_ADMA_LPCG_I2C1_CLK 26 +#define IMX8QXP_ADMA_LPCG_I2C2_CLK 27 +#define IMX8QXP_ADMA_LPCG_I2C3_CLK 28 +#define IMX8QXP_ADMA_LPCG_I2C0_IPG_CLK 29 +#define IMX8QXP_ADMA_LPCG_I2C1_IPG_CLK 30 +#define IMX8QXP_ADMA_LPCG_I2C2_IPG_CLK 31 +#define IMX8QXP_ADMA_LPCG_I2C3_IPG_CLK 32 +#define IMX8QXP_ADMA_LPCG_FTM0_CLK 33 +#define IMX8QXP_ADMA_LPCG_FTM1_CLK 34 +#define IMX8QXP_ADMA_LPCG_FTM0_IPG_CLK 35 +#define IMX8QXP_ADMA_LPCG_FTM1_IPG_CLK 36 +#define IMX8QXP_ADMA_LPCG_PWM_HI_CLK 37 +#define IMX8QXP_ADMA_LPCG_PWM_IPG_CLK 38 +#define IMX8QXP_ADMA_LPCG_LCD_PIX_CLK 39 +#define IMX8QXP_ADMA_LPCG_LCD_APB_CLK 40 + +#define IMX8QXP_ADMA_LPCG_CLK_END 41 + #endif /* __DT_BINDINGS_CLOCK_IMX8QXP_H */ -- cgit v1.2.3-59-g8ed1b