From 7b0c9ca7f18e8d2e2cf3c342d91f037d436777bf Mon Sep 17 00:00:00 2001 From: Rafał Miłecki Date: Fri, 5 Nov 2021 11:14:12 +0100 Subject: dt-bindings: arm: bcm: document Netgear RAXE500 binding MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit One more BCM4908 based device. Signed-off-by: Rafał Miłecki Acked-by: Rob Herring Signed-off-by: Florian Fainelli --- Documentation/devicetree/bindings/arm/bcm/brcm,bcm4908.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4908.yaml b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4908.yaml index 2cd4e4a32278..9b745531ff04 100644 --- a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4908.yaml +++ b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4908.yaml @@ -29,6 +29,7 @@ properties: items: - enum: - asus,gt-ac5300 + - netgear,raxe500 - const: brcm,bcm4908 - description: BCM49408 based boards -- cgit v1.2.3-59-g8ed1b From 7358101393123aae68878fc05835f5add649ea6b Mon Sep 17 00:00:00 2001 From: Hsin-Yi Wang Date: Wed, 10 Nov 2021 14:31:16 +0800 Subject: dt-bindings: arm64: dts: mediatek: Add mt8183-kukui-jacuzzi-cozmo Cozmo is known as Acer Chromebook 314 (CB314-2H/CB314-2HT) Chromebook. Signed-off-by: Hsin-Yi Wang Link: https://lore.kernel.org/r/20211110063118.3412564-5-hsinyi@chromium.org Signed-off-by: Matthias Brugger --- Documentation/devicetree/bindings/arm/mediatek.yaml | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/arm/mediatek.yaml b/Documentation/devicetree/bindings/arm/mediatek.yaml index 0fa55497b96f..7cf0c76cd310 100644 --- a/Documentation/devicetree/bindings/arm/mediatek.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek.yaml @@ -134,6 +134,10 @@ properties: - google,krane-sku176 - const: google,krane - const: mediatek,mt8183 + - description: Google Cozmo (Acer Chromebook 314) + items: + - const: google,cozmo + - const: mediatek,mt8183 - description: Google Damu (ASUS Chromebook Flip CM3) items: - const: google,damu -- cgit v1.2.3-59-g8ed1b From bf08726b34c18dc917d9155ee52ee9cba94fb9e1 Mon Sep 17 00:00:00 2001 From: Hsin-Yi Wang Date: Wed, 10 Nov 2021 14:31:17 +0800 Subject: dt-bindings: arm64: dts: mediatek: Add more SKUs for mt8183 fennel board Add sku2 and sku7 which uses different audio codec than other fennel boards. Signed-off-by: Hsin-Yi Wang Link: https://lore.kernel.org/r/20211110063118.3412564-6-hsinyi@chromium.org Signed-off-by: Matthias Brugger --- Documentation/devicetree/bindings/arm/mediatek.yaml | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/arm/mediatek.yaml b/Documentation/devicetree/bindings/arm/mediatek.yaml index 7cf0c76cd310..99e7f8e294cd 100644 --- a/Documentation/devicetree/bindings/arm/mediatek.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek.yaml @@ -147,7 +147,9 @@ properties: - enum: - google,fennel-sku0 - google,fennel-sku1 + - google,fennel-sku2 - google,fennel-sku6 + - google,fennel-sku7 - const: google,fennel - const: mediatek,mt8183 - description: Google Juniper (Acer Chromebook Spin 311) / Kenzo (Acer Chromebook 311) -- cgit v1.2.3-59-g8ed1b From 861a08874fdbf625fea5ac265ff6aabbf6b68c56 Mon Sep 17 00:00:00 2001 From: Hsin-Yi Wang Date: Wed, 10 Nov 2021 14:31:18 +0800 Subject: dt-bindings: arm64: dts: mediatek: Add sku22 for mt8183 kakadu board Add sku22 which uses different audio codec than previous kakadu board. Signed-off-by: Hsin-Yi Wang Link: https://lore.kernel.org/r/20211110063118.3412564-7-hsinyi@chromium.org Signed-off-by: Matthias Brugger --- Documentation/devicetree/bindings/arm/mediatek.yaml | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/arm/mediatek.yaml b/Documentation/devicetree/bindings/arm/mediatek.yaml index 99e7f8e294cd..723810cffce2 100644 --- a/Documentation/devicetree/bindings/arm/mediatek.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek.yaml @@ -165,6 +165,12 @@ properties: - const: google,kakadu-rev2 - const: google,kakadu - const: mediatek,mt8183 + - description: Google Kakadu (ASUS Chromebook Detachable CM3) + items: + - const: google,kakadu-rev3-sku22 + - const: google,kakadu-rev2-sku22 + - const: google,kakadu + - const: mediatek,mt8183 - description: Google Kappa (HP Chromebook 11a) items: - const: google,kappa -- cgit v1.2.3-59-g8ed1b From e051025efac3929ca7e3e2f2c8860d3447366ebc Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Mon, 15 Nov 2021 17:06:00 +0100 Subject: dt-bindings: mmc: renesas,sdhi: Add optional SDnH clock This only applies to R-Car Gen2 and later generations, so we need to distinguish. Signed-off-by: Wolfram Sang Acked-by: Ulf Hansson Link: https://lore.kernel.org/r/20211115160600.4455-1-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven --- .../devicetree/bindings/mmc/renesas,sdhi.yaml | 38 +++++++++++++++++----- 1 file changed, 29 insertions(+), 9 deletions(-) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml b/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml index 9f1e7092cf44..f5107a641790 100644 --- a/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml +++ b/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml @@ -129,15 +129,35 @@ allOf: - clock-names - resets else: - properties: - clocks: - minItems: 1 - maxItems: 2 - clock-names: - minItems: 1 - items: - - const: core - - const: cd + if: + properties: + compatible: + contains: + enum: + - renesas,rcar-gen2-sdhi + - renesas,rcar-gen3-sdhi + then: + properties: + clocks: + minItems: 1 + maxItems: 3 + clock-names: + minItems: 1 + uniqueItems: true + items: + - const: core + - enum: [ clkh, cd ] + - const: cd + else: + properties: + clocks: + minItems: 1 + maxItems: 2 + clock-names: + minItems: 1 + items: + - const: core + - const: cd - if: properties: -- cgit v1.2.3-59-g8ed1b From 663eede58f83783ff246573937615f0792788876 Mon Sep 17 00:00:00 2001 From: Yoshihiro Shimoda Date: Tue, 16 Nov 2021 16:41:15 +0900 Subject: dt-bindings: arm: renesas: Document R-Car S4-8 SoC DT bindings Add device tree bindings documentation for Renesas R-Car S4-8 (r8a779f0). Signed-off-by: Yoshihiro Shimoda Link: https://lore.kernel.org/r/20211116074130.107554-2-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven --- Documentation/devicetree/bindings/arm/renesas.yaml | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/arm/renesas.yaml b/Documentation/devicetree/bindings/arm/renesas.yaml index 517206507801..36197f53b310 100644 --- a/Documentation/devicetree/bindings/arm/renesas.yaml +++ b/Documentation/devicetree/bindings/arm/renesas.yaml @@ -315,6 +315,10 @@ properties: - const: renesas,falcon-cpu - const: renesas,r8a779a0 + - description: R-Car S4-8 (R8A779F0) + items: + - const: renesas,r8a779f0 + - description: R-Car H3e (R8A779M0) items: - enum: -- cgit v1.2.3-59-g8ed1b From 06bd71cd2ebd98bb177fc7c35c10fed855781b82 Mon Sep 17 00:00:00 2001 From: Yoshihiro Shimoda Date: Tue, 16 Nov 2021 16:41:17 +0900 Subject: dt-bindings: reset: renesas,rst: Document r8a779f0 reset module Document bindings for the R-Car S4-8 (R8A779F0) reset module. Signed-off-by: Yoshihiro Shimoda Link: https://lore.kernel.org/r/20211116074130.107554-4-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven --- Documentation/devicetree/bindings/reset/renesas,rst.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/reset/renesas,rst.yaml b/Documentation/devicetree/bindings/reset/renesas,rst.yaml index 620cd0538bbe..bbe313bf1796 100644 --- a/Documentation/devicetree/bindings/reset/renesas,rst.yaml +++ b/Documentation/devicetree/bindings/reset/renesas,rst.yaml @@ -48,6 +48,7 @@ properties: - renesas,r8a77990-rst # R-Car E3 - renesas,r8a77995-rst # R-Car D3 - renesas,r8a779a0-rst # R-Car V3U + - renesas,r8a779f0-rst # R-Car S4-8 reg: maxItems: 1 -- cgit v1.2.3-59-g8ed1b From c014e935596b2637e00dcd32077ac5019d9a7e64 Mon Sep 17 00:00:00 2001 From: Yoshihiro Shimoda Date: Tue, 16 Nov 2021 16:41:18 +0900 Subject: dt-bindings: power: renesas,rcar-sysc: Document r8a779f0 SYSC bindings Document bindings for the R-Car S4-8 (aka R8A779F0) SYSC block. Signed-off-by: Yoshihiro Shimoda Link: https://lore.kernel.org/r/20211116074130.107554-5-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven --- Documentation/devicetree/bindings/power/renesas,rcar-sysc.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/power/renesas,rcar-sysc.yaml b/Documentation/devicetree/bindings/power/renesas,rcar-sysc.yaml index 99e8042ac111..62a49ca319ec 100644 --- a/Documentation/devicetree/bindings/power/renesas,rcar-sysc.yaml +++ b/Documentation/devicetree/bindings/power/renesas,rcar-sysc.yaml @@ -41,6 +41,7 @@ properties: - renesas,r8a77990-sysc # R-Car E3 - renesas,r8a77995-sysc # R-Car D3 - renesas,r8a779a0-sysc # R-Car V3U + - renesas,r8a779f0-sysc # R-Car S4-8 reg: maxItems: 1 -- cgit v1.2.3-59-g8ed1b From 34734edd06f84290a3fc6f2a4ae61969e9d25801 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Tue, 16 Nov 2021 15:32:55 +0100 Subject: dt-bindings: crypto: Add optional dma properties Some platforms, like the v3s, have DMA channels assigned to the crypto engine, which were in the DTSI but were never documented. Let's make sure they are. Signed-off-by: Maxime Ripard Acked-by: Corentin Labbe Acked-by: Jernej Skrabec Link: https://lore.kernel.org/r/20211116143255.385480-1-maxime@cerno.tech --- .../devicetree/bindings/crypto/allwinner,sun4i-a10-crypto.yaml | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/crypto/allwinner,sun4i-a10-crypto.yaml b/Documentation/devicetree/bindings/crypto/allwinner,sun4i-a10-crypto.yaml index 0429fb774f10..dedc99e34ebc 100644 --- a/Documentation/devicetree/bindings/crypto/allwinner,sun4i-a10-crypto.yaml +++ b/Documentation/devicetree/bindings/crypto/allwinner,sun4i-a10-crypto.yaml @@ -44,6 +44,16 @@ properties: - const: ahb - const: mod + dmas: + items: + - description: RX DMA Channel + - description: TX DMA Channel + + dma-names: + items: + - const: rx + - const: tx + resets: maxItems: 1 -- cgit v1.2.3-59-g8ed1b From 245578ba9f03e07132bcaf60cbdfeb0e89457104 Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Wed, 17 Nov 2021 21:18:37 -0600 Subject: dt-bindings: arm: sunxi: Expand MBUS binding The MBUS provides more than address translation and bandwidth control. It also provides a PMU to measure bandwidth usage by certain masters, and it provides notification via IRQ when they are active or idle. The MBUS is also tightly integrated with the DRAM controller to provide a Memory Dynamic Frequency Scaling (MDFS) feature. In view of this, the MBUS binding needs to represent the hardware resources needed for MDFS, which include the clocks and MMIO range of the adjacent DRAM controller. Add the additional resources for the H3 and A64 compatibles, and a new example showing how they are used. Reviewed-by: Chanwoo Choi Signed-off-by: Samuel Holland Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20211118031841.42315-3-samuel@sholland.org --- .../arm/sunxi/allwinner,sun4i-a10-mbus.yaml | 89 +++++++++++++++++++++- 1 file changed, 86 insertions(+), 3 deletions(-) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/arm/sunxi/allwinner,sun4i-a10-mbus.yaml b/Documentation/devicetree/bindings/arm/sunxi/allwinner,sun4i-a10-mbus.yaml index 29c9961ee2d8..2b3829e0e240 100644 --- a/Documentation/devicetree/bindings/arm/sunxi/allwinner,sun4i-a10-mbus.yaml +++ b/Documentation/devicetree/bindings/arm/sunxi/allwinner,sun4i-a10-mbus.yaml @@ -34,10 +34,35 @@ properties: - allwinner,sun50i-a64-mbus reg: - maxItems: 1 + minItems: 1 + items: + - description: MBUS interconnect/bandwidth limit/PMU registers + - description: DRAM controller/PHY registers + + reg-names: + minItems: 1 + items: + - const: mbus + - const: dram clocks: + minItems: 1 + items: + - description: MBUS interconnect module clock + - description: DRAM controller/PHY module clock + - description: Register bus clock, shared by MBUS and DRAM + + clock-names: + minItems: 1 + items: + - const: mbus + - const: dram + - const: bus + + interrupts: maxItems: 1 + description: + MBUS PMU activity interrupt. dma-ranges: description: @@ -54,13 +79,54 @@ required: - clocks - dma-ranges +if: + properties: + compatible: + contains: + enum: + - allwinner,sun8i-h3-mbus + - allwinner,sun50i-a64-mbus + +then: + properties: + reg: + minItems: 2 + + reg-names: + minItems: 2 + + clocks: + minItems: 3 + + clock-names: + minItems: 3 + + required: + - reg-names + - clock-names + +else: + properties: + reg: + maxItems: 1 + + reg-names: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + maxItems: 1 + additionalProperties: false examples: - | - #include + #include + #include - mbus: dram-controller@1c01000 { + dram-controller@1c01000 { compatible = "allwinner,sun5i-a13-mbus"; reg = <0x01c01000 0x1000>; clocks = <&ccu CLK_MBUS>; @@ -70,4 +136,21 @@ examples: #interconnect-cells = <1>; }; + - | + dram-controller@1c62000 { + compatible = "allwinner,sun50i-a64-mbus"; + reg = <0x01c62000 0x1000>, + <0x01c63000 0x1000>; + reg-names = "mbus", "dram"; + clocks = <&ccu CLK_MBUS>, + <&ccu CLK_DRAM>, + <&ccu CLK_BUS_DRAM>; + clock-names = "mbus", "dram", "bus"; + interrupts = ; + #address-cells = <1>; + #size-cells = <1>; + dma-ranges = <0x00000000 0x40000000 0xc0000000>; + #interconnect-cells = <1>; + }; + ... -- cgit v1.2.3-59-g8ed1b From 9f193dedd6efeb4e193d706856f26fcf11ae0ff2 Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Wed, 17 Nov 2021 21:18:38 -0600 Subject: dt-bindings: arm: sunxi: Add H5 MBUS compatible The H5 SoC has a MBUS very similar to the H3 SoC, but it has a smaller MDFS divider range (1-4 instead of 1-16). Add a separate compatible for this variant. Acked-by: Rob Herring Signed-off-by: Samuel Holland Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20211118031841.42315-4-samuel@sholland.org --- .../devicetree/bindings/arm/sunxi/allwinner,sun4i-a10-mbus.yaml | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/arm/sunxi/allwinner,sun4i-a10-mbus.yaml b/Documentation/devicetree/bindings/arm/sunxi/allwinner,sun4i-a10-mbus.yaml index 2b3829e0e240..8eee312c2e6f 100644 --- a/Documentation/devicetree/bindings/arm/sunxi/allwinner,sun4i-a10-mbus.yaml +++ b/Documentation/devicetree/bindings/arm/sunxi/allwinner,sun4i-a10-mbus.yaml @@ -32,6 +32,7 @@ properties: - allwinner,sun8i-h3-mbus - allwinner,sun8i-r40-mbus - allwinner,sun50i-a64-mbus + - allwinner,sun50i-h5-mbus reg: minItems: 1 @@ -86,6 +87,7 @@ if: enum: - allwinner,sun8i-h3-mbus - allwinner,sun50i-a64-mbus + - allwinner,sun50i-h5-mbus then: properties: -- cgit v1.2.3-59-g8ed1b From 217c7d1840b5377543eff84fe28409d0bd4d3433 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Mon, 22 Nov 2021 10:39:04 +0000 Subject: dt-bindings: mmc: renesas,sdhi: Rename RZ/G2L clocks Rename the below RZ/G2L clocks to match with the clock names used in R-Car Gen2 and later generations. imclk->core clk_hs->clkh imclk2->cd This changes will avoid using fallback for RZ/G2L high speed clock, if "clkh" is not used in device tree and also the code changes in driver related to this clocks. Signed-off-by: Biju Das Reviewed-by: Wolfram Sang Acked-by: Ulf Hansson Link: https://lore.kernel.org/r/20211122103905.14439-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml b/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml index f5107a641790..9ce6e06c19db 100644 --- a/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml +++ b/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml @@ -113,17 +113,17 @@ allOf: clocks: items: - description: IMCLK, SDHI channel main clock1. + - description: CLK_HS, SDHI channel High speed clock which operates + 4 times that of SDHI channel main clock1. - description: IMCLK2, SDHI channel main clock2. When this clock is turned off, external SD card detection cannot be detected. - - description: CLK_HS, SDHI channel High speed clock which operates - 4 times that of SDHI channel main clock1. - description: ACLK, SDHI channel bus clock. clock-names: items: - - const: imclk - - const: imclk2 - - const: clk_hs + - const: core + - const: clkh + - const: cd - const: aclk required: - clock-names -- cgit v1.2.3-59-g8ed1b From 7a21328bb3ade238e35c4de81da3ad8d76437b72 Mon Sep 17 00:00:00 2001 From: Rajendra Nayak Date: Mon, 29 Nov 2021 17:01:34 +0530 Subject: dt-bindings: arm: qcom: Document qcom,sc7280-crd board Document the qcom,sc7280-crd board based off sc7280 SoC, The board is also known as hoglin in the Chrome OS builds, so document the google,hoglin compatible as well. Signed-off-by: Rajendra Nayak Reviewed-by: Matthias Kaehlcke Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1638185497-26477-2-git-send-email-quic_rjendra@quicinc.com --- Documentation/devicetree/bindings/arm/qcom.yaml | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index c8808e0f9e64..41e1d781e43f 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -201,8 +201,10 @@ properties: - items: - enum: + - qcom,sc7280-crd - qcom,sc7280-idp - qcom,sc7280-idp2 + - google,hoglin - google,piglin - google,senor - const: qcom,sc7280 -- cgit v1.2.3-59-g8ed1b From ad1569476e7644ac5754ac9a710ce771a7b4976f Mon Sep 17 00:00:00 2001 From: Janne Grunau Date: Tue, 23 Nov 2021 23:49:22 +0100 Subject: dt-bindings: arm: apple: Add iMac (24-inch 2021) to Apple bindings This introduces compatible strings for both 2021 Apple iMac M1 devices: * apple,j456 - iMac (24-inch, 4x USB-C, M1, 2021) * apple,j457 - iMac (24-inch, 2x USB-C, M1, 2021) Reviewed-by: Mark Kettenis Signed-off-by: Janne Grunau Tested-by: Hector Martin Acked-by: Rob Herring Signed-off-by: Hector Martin --- Documentation/devicetree/bindings/arm/apple.yaml | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/arm/apple.yaml b/Documentation/devicetree/bindings/arm/apple.yaml index 1e772c85206c..b23c8dc5a27d 100644 --- a/Documentation/devicetree/bindings/arm/apple.yaml +++ b/Documentation/devicetree/bindings/arm/apple.yaml @@ -12,12 +12,12 @@ maintainers: description: | ARM platforms using SoCs designed by Apple Inc., branded "Apple Silicon". - This currently includes devices based on the "M1" SoC, starting with the - three Mac models released in late 2020: + This currently includes devices based on the "M1" SoC: - Mac mini (M1, 2020) - MacBook Pro (13-inch, M1, 2020) - MacBook Air (M1, 2020) + - iMac (24-inch, M1, 2021) The compatible property should follow this format: @@ -56,6 +56,8 @@ properties: - apple,j274 # Mac mini (M1, 2020) - apple,j293 # MacBook Pro (13-inch, M1, 2020) - apple,j313 # MacBook Air (M1, 2020) + - apple,j456 # iMac (24-inch, 4x USB-C, M1, 2021) + - apple,j457 # iMac (24-inch, 2x USB-C, M1, 2021) - const: apple,t8103 - const: apple,arm-platform -- cgit v1.2.3-59-g8ed1b From 6f8260557d490364c2b49872127c379de9b141ac Mon Sep 17 00:00:00 2001 From: Hector Martin Date: Wed, 24 Nov 2021 15:12:03 +0900 Subject: dt-bindings: i2c: apple,i2c: Add power-domains property This will bind to the PMGR pwrstate nodes that control power/clock gating to SoC blocks. The i2c driver doesn't do runtime-pm yet, so initially this will just keep the domain on permanently. Acked-by: Rob Herring Signed-off-by: Hector Martin --- Documentation/devicetree/bindings/i2c/apple,i2c.yaml | 3 +++ 1 file changed, 3 insertions(+) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/i2c/apple,i2c.yaml b/Documentation/devicetree/bindings/i2c/apple,i2c.yaml index 82b953181a52..47dd6c107a6d 100644 --- a/Documentation/devicetree/bindings/i2c/apple,i2c.yaml +++ b/Documentation/devicetree/bindings/i2c/apple,i2c.yaml @@ -40,6 +40,9 @@ properties: used. This frequency is generated by dividing the reference clock. Allowed values are between ref_clk/(16*4) and ref_clk/(16*255). + power-domains: + maxItems: 1 + required: - compatible - reg -- cgit v1.2.3-59-g8ed1b From 364609125e2ca745c698ec157615ff179b239344 Mon Sep 17 00:00:00 2001 From: Hector Martin Date: Wed, 24 Nov 2021 15:13:15 +0900 Subject: dt-bindings: iommu: apple,dart: Add power-domains property This will bind to the PMGR pwrstate nodes that control power/clock gating to SoC blocks. The DART driver doesn't do runtime-pm yet, so initially this will just keep the domain on permanently. Acked-by: Rob Herring Signed-off-by: Hector Martin --- Documentation/devicetree/bindings/iommu/apple,dart.yaml | 3 +++ 1 file changed, 3 insertions(+) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/iommu/apple,dart.yaml b/Documentation/devicetree/bindings/iommu/apple,dart.yaml index 94aa9e9afa59..82ad669feef7 100644 --- a/Documentation/devicetree/bindings/iommu/apple,dart.yaml +++ b/Documentation/devicetree/bindings/iommu/apple,dart.yaml @@ -41,6 +41,9 @@ properties: Has to be one. The single cell describes the stream id emitted by a master to the IOMMU. + power-domains: + maxItems: 1 + required: - compatible - reg -- cgit v1.2.3-59-g8ed1b From 1ed162b56baae221da049ba8641ddd4fca33c0b9 Mon Sep 17 00:00:00 2001 From: Hector Martin Date: Wed, 24 Nov 2021 15:14:12 +0900 Subject: dt-bindings: pinctrl: apple,pinctrl: Add power-domains property This will bind to the PMGR pwrstate nodes that control power/clock gating to SoC blocks. The pinctrl driver doesn't do runtime-pm yet, so initially this will just keep the domain on permanently. Acked-by: Rob Herring Signed-off-by: Hector Martin --- Documentation/devicetree/bindings/pinctrl/apple,pinctrl.yaml | 3 +++ 1 file changed, 3 insertions(+) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/pinctrl/apple,pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/apple,pinctrl.yaml index 07b00de79755..200d411621e7 100644 --- a/Documentation/devicetree/bindings/pinctrl/apple,pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/apple,pinctrl.yaml @@ -50,6 +50,9 @@ properties: '#interrupt-cells': const: 2 + power-domains: + maxItems: 1 + patternProperties: '-pins$': type: object -- cgit v1.2.3-59-g8ed1b From 72baffdd26fb4e5b3c7215728e98e2681a9ebc4f Mon Sep 17 00:00:00 2001 From: Hector Martin Date: Wed, 24 Nov 2021 15:15:41 +0900 Subject: dt-bindings: interrupt-controller: apple,aic: Add power-domains property This will bind to the PMGR pwrstate nodes that control power/clock gating to SoC blocks. The AIC driver doesn't do runtime-pm and likely never will (since it is system-critical), but it makes sense to describe the power domain relationship the devicetree properly. Acked-by: Rob Herring Signed-off-by: Hector Martin --- Documentation/devicetree/bindings/interrupt-controller/apple,aic.yaml | 3 +++ 1 file changed, 3 insertions(+) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/interrupt-controller/apple,aic.yaml b/Documentation/devicetree/bindings/interrupt-controller/apple,aic.yaml index cf6c091a07b1..97359024709a 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/apple,aic.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/apple,aic.yaml @@ -65,6 +65,9 @@ properties: Specifies base physical address and size of the AIC registers. maxItems: 1 + power-domains: + maxItems: 1 + required: - compatible - '#interrupt-cells' -- cgit v1.2.3-59-g8ed1b From fcad81d944e7cb8f2d0aeaec0e4109638e873036 Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Wed, 1 Dec 2021 19:21:15 +0100 Subject: dt-bindings: arm: sunxi: Add Tanix TX6 mini Tanix TX6 mini is, as its name suggest, very similar to Tanix TX6, but with less features. It misses bluetooth support, it has less RAM, wifi supports only 2.4G, it comes with different IR remote, etc. Signed-off-by: Jernej Skrabec Signed-off-by: Maxime Ripard --- Documentation/devicetree/bindings/arm/sunxi.yaml | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/arm/sunxi.yaml b/Documentation/devicetree/bindings/arm/sunxi.yaml index 889128acf49a..c8a3102c0fde 100644 --- a/Documentation/devicetree/bindings/arm/sunxi.yaml +++ b/Documentation/devicetree/bindings/arm/sunxi.yaml @@ -808,6 +808,11 @@ properties: - const: oranth,tanix-tx6 - const: allwinner,sun50i-h6 + - description: Tanix TX6 mini + items: + - const: oranth,tanix-tx6-mini + - const: allwinner,sun50i-h6 + - description: TBS A711 Tablet items: - const: tbs-biometrics,a711 -- cgit v1.2.3-59-g8ed1b From 3e63d6a197d57f94abff0fbd71efd8f98e254e1c Mon Sep 17 00:00:00 2001 From: Oleksij Rempel Date: Mon, 22 Nov 2021 11:19:15 +0100 Subject: dt-bindings: vendor-prefixes: Add an entry for JOZ BV Add "joz" entry for JOZ BV: https://joz.nl/en/about-joz/ Signed-off-by: Oleksij Rempel Acked-by: Rob Herring Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index 66d6432fd781..6414f5fdcb91 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -593,6 +593,8 @@ patternProperties: description: JetHome (IP Sokolov P.A.) "^jianda,.*": description: Jiandangjing Technology Co., Ltd. + "^joz,.*": + description: JOZ BV "^kam,.*": description: Kamstrup A/S "^karo,.*": -- cgit v1.2.3-59-g8ed1b From 74fb79574d26fc79a04e5a75e137317870843e7d Mon Sep 17 00:00:00 2001 From: Oleksij Rempel Date: Mon, 22 Nov 2021 11:19:16 +0100 Subject: dt-bindings: arm: fsl: add JOZ Access Point Add imx6ull based JOZ Access Point. Signed-off-by: Oleksij Rempel Acked-by: Rob Herring Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 0b595b26061f..a0eb42595ee2 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -580,6 +580,7 @@ properties: items: - enum: - fsl,imx6ull-14x14-evk # i.MX6 UltraLiteLite 14x14 EVK Board + - joz,jozacp # JOZ Access Point - kontron,imx6ull-n6411-som # Kontron N6411 SOM - myir,imx6ull-mys-6ulx-eval # MYiR Tech iMX6ULL Evaluation Board - toradex,colibri-imx6ull # Colibri iMX6ULL Modules -- cgit v1.2.3-59-g8ed1b From 5a759dac6503e1432f5c30a01df483608b500a54 Mon Sep 17 00:00:00 2001 From: Matthias Schiffer Date: Mon, 22 Nov 2021 12:37:38 +0100 Subject: dt-bindings: arm: fsl: add TQ-Systems boards based on i.MX6Q/QP/DL The TQ-Systems MBa6x mainboard can be used with TQMa6 variants with i.MX6Q/QP/DL SoCs (TQMa6Q/QP/DL). The TQMa6Q and DL exist in two variants: The newer variants "A" have a hardware workaround for Erratum ERR006687, while variants "B" are missing such a workaround, so it needs to be handled in software. The erratum was fixed in i.MX6QP, so no "A" variant of the TQMa6QP exists. Signed-off-by: Matthias Schiffer Reviewed-by: Rob Herring Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 35 ++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index a0eb42595ee2..d6a3a67e4d37 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -323,6 +323,20 @@ properties: - const: toradex,apalis_imx6q - const: fsl,imx6q + - description: TQ-Systems TQMa6Q SoM (variant A) on MBa6x + items: + - const: tq,imx6q-mba6x-a + - const: tq,mba6a # Expected by bootloader, to be removed in the future + - const: tq,imx6q-tqma6q-a + - const: fsl,imx6q + + - description: TQ-Systems TQMa6Q SoM (variant B) on MBa6x + items: + - const: tq,imx6q-mba6x-b + - const: tq,mba6b # Expected by bootloader, to be removed in the future + - const: tq,imx6q-tqma6q-b + - const: fsl,imx6q + - description: i.MX6QP based Boards items: - enum: @@ -344,6 +358,13 @@ properties: - const: phytec,imx6qdl-pcm058 # PHYTEC phyCORE-i.MX6 - const: fsl,imx6qp + - description: TQ-Systems TQMa6QP SoM on MBa6x + items: + - const: tq,imx6qp-mba6x-b + - const: tq,mba6b # Expected by bootloader, to be removed in the future + - const: tq,imx6qp-tqma6qp-b + - const: fsl,imx6qp + - description: i.MX6DL based Boards items: - enum: @@ -482,6 +503,20 @@ properties: - const: dh,imx6s-dhcom-som - const: fsl,imx6dl + - description: TQ-Systems TQMa6DL SoM (variant A) on MBa6x + items: + - const: tq,imx6dl-mba6x-a + - const: tq,mba6a # Expected by bootloader, to be removed in the future + - const: tq,imx6dl-tqma6dl-a + - const: fsl,imx6dl + + - description: TQ-Systems TQMa6DL SoM (variant B) on MBa6x + items: + - const: tq,imx6dl-mba6x-b + - const: tq,mba6b # Expected by bootloader, to be removed in the future + - const: tq,imx6dl-tqma6dl-b + - const: fsl,imx6dl + - description: i.MX6SL based Boards items: - enum: -- cgit v1.2.3-59-g8ed1b From 97164c0419fc3985921f9be4c235748a68f9095e Mon Sep 17 00:00:00 2001 From: Michal Vokáč Date: Mon, 22 Nov 2021 17:25:19 +0100 Subject: dt-bindings: arm: fsl: Add Y Soft IOTA Crux/Crux+ boards MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add devicetree binding for Crux/Crux+ boards from the IOTA family. These boards have the very same HW configuration as the Orion board except the usage of Quad/QuadPlus SoC. Signed-off-by: Michal Vokáč Acked-by: Rob Herring Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index d6a3a67e4d37..9679e3cd946a 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -240,6 +240,7 @@ properties: - uniwest,imx6q-evi # Uniwest Evi - variscite,dt6customboard - wand,imx6q-wandboard # Wandboard i.MX6 Quad Board + - ysoft,imx6q-yapp4-crux # i.MX6 Quad Y Soft IOTA Crux board - zealz,imx6q-gk802 # Zealz GK802 - zii,imx6q-zii-rdu2 # ZII RDU2 Board - const: fsl,imx6q @@ -348,6 +349,7 @@ properties: - kvg,vicutp # Kverneland UT1P board - prt,prtwd3 # Protonic WD3 board - wand,imx6qp-wandboard # Wandboard i.MX6 QuadPlus Board + - ysoft,imx6qp-yapp4-crux-plus # i.MX6 Quad Plus Y Soft IOTA Crux+ board - zii,imx6qp-zii-rdu2 # ZII RDU2+ Board - const: fsl,imx6qp -- cgit v1.2.3-59-g8ed1b From 8355d48fd1ec1c01b5ab1f8071562cf3e3884214 Mon Sep 17 00:00:00 2001 From: Jacky Bai Date: Fri, 26 Nov 2021 15:40:00 +0800 Subject: dt-bindings: arm: fsl: Add binding for imx8ulp evk Add the dt binding for i.MX8ULP EVK board. i.MX 8ULP is part of the ULP family with emphasis on extreme low-power techniques using the 28 nm fully depleted silicon on insulator process. Like i.MX 7ULP, i.MX 8ULP continues to be based on asymmetric architecture, however will add a third DSP domain for advanced voice/audio capability and a Graphics domain where it is possible to access graphics resources from the application side or the realtime side. Reviewed-by: Dong Aisheng Acked-by: Rob Herring Signed-off-by: Jacky Bai Signed-off-by: Peng Fan Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 9679e3cd946a..6604aea7d646 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -872,6 +872,12 @@ properties: - const: toradex,colibri-imx8x - const: fsl,imx8qxp + - description: i.MX8ULP based Boards + items: + - enum: + - fsl,imx8ulp-evk # i.MX8ULP EVK Board + - const: fsl,imx8ulp + - description: Freescale Vybrid Platform Device Tree Bindings -- cgit v1.2.3-59-g8ed1b From ee6302d90db96e1f0a49305ba9db4969b378d585 Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Wed, 1 Dec 2021 08:29:42 +0100 Subject: dt-bindings: arm: fsl: add TQMa8MxML boards TQMa8MxML is a SOM family using NXP i.MX8MM[Q,QL,DL,S,SL] CPU MBa8Mx is an evaluation mainbord for this SOM The SOM needs a mainboard, therefore we provide two compatibles here: "tq,imx8mm-" for the module and "tq,imx8mm--" for the module on that mainboard Signed-off-by: Alexander Stein Acked-by: Rob Herring Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 6604aea7d646..79789e64f673 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -792,6 +792,17 @@ properties: - const: variscite,var-som-mx8mm - const: fsl,imx8mm + - description: + TQMa8MxML is a series of SOM featuring NXP i.MX8MM system-on-chip + variants. It is designed to be soldered on different carrier boards. + All variants (TQMa8M[Q,D,S][L]ML) use the same device tree, hence only + one compatible is needed. + items: + - enum: + - tq,imx8mm-tqma8mqml-mba8mx # TQ-Systems GmbH i.MX8MM TQMa8MQML SOM on MBa8Mx + - const: tq,imx8mm-tqma8mqml # TQ-Systems GmbH i.MX8MM TQMa8MQML SOM + - const: fsl,imx8mm + - description: i.MX8MN based Boards items: - enum: -- cgit v1.2.3-59-g8ed1b From 50ef92d89c12809fe8f98d0e0cab7b6765e10898 Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Wed, 1 Dec 2021 08:29:45 +0100 Subject: dt-bindings: arm: fsl: add TQMa8MxNL boards TQMa8MxNL is a SOM family using NXP i.MX8MN[Q,QL,DL,S,SL] CPU MBa8Mx is an evaluation mainbord for this SOM The SOM needs a mainboard, therefore we provide two compatibles here: "tq,imx8mn-" for the module and "tq,imx8mn--" for mainboards Signed-off-by: Alexander Stein Acked-by: Rob Herring Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 79789e64f673..a705eabe1cfc 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -818,6 +818,17 @@ properties: - const: variscite,var-som-mx8mn - const: fsl,imx8mn + - description: + TQMa8MxNL is a series of SOM featuring NXP i.MX8MN system-on-chip + variants. It is designed to be soldered on different carrier boards. + All variants (TQMa8M[Q,D,S][L]NL) use the same device tree, hence only + one compatible is needed. + items: + - enum: + - tq,imx8mn-tqma8mqnl-mba8mx # TQ-Systems GmbH i.MX8MN TQMa8MQNL SOM on MBa8Mx + - const: tq,imx8mn-tqma8mqnl # TQ-Systems GmbH i.MX8MN TQMa8MQNL SOM + - const: fsl,imx8mn + - description: i.MX8MP based Boards items: - enum: -- cgit v1.2.3-59-g8ed1b From 9aa637b5673ca100f219b13b16dbc19a0b77ef73 Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Wed, 1 Dec 2021 08:29:47 +0100 Subject: dt-bindings: arm: fsl: add TQMa8Mx boards TQMa8Mx is a SOM family using NXP i.MX8M[Q,QL, D] CPU MBa8Mx is a evaluation mainbord for this SOM The SOM needs a mainboard, therefore we provide two compatibles here: "tq,imx8mq-" for the module and "tq,imx8mq--" for the module on that mainboard Signed-off-by: Alexander Stein Acked-by: Rob Herring Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index a705eabe1cfc..c35076cc551d 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -865,6 +865,15 @@ properties: - const: purism,librem5 - const: fsl,imx8mq + - description: + TQMa8Mx is a series of SOM featuring NXP i.MX8MQ system-on-chip + variants. It is designed to be clicked on different carrier boards. + items: + - enum: + - tq,imx8mq-tqma8mq-mba8mx # TQ-Systems GmbH i.MX8MQ TQMa8Mx SOM on MBa8Mx + - const: tq,imx8mq-tqma8mq # TQ-Systems GmbH i.MX8MQ TQMa8Mx SOM + - const: fsl,imx8mq + - description: Zodiac Inflight Innovations Ultra Boards items: - enum: -- cgit v1.2.3-59-g8ed1b From 854b020b165fbdf040ab6872a75a6094803a6932 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Fri, 3 Dec 2021 22:24:34 +0530 Subject: dt-bindings: arm: stm32: Add Engicam i.Core STM32MP1 C.TOUCH 2.0 10.1" OF i.Core STM32MP1 is an EDIMM SoM based on STM32MP157A from Engicam. C.TOUCH 2.0 is a general purpose carrier board with capacitive touch interface support. 10.1" OF is a capacitive touch 10.1" Open Frame panel solutions. i.Core STM32MP1 needs to mount on top of C.TOUCH 2.0 carrier with pluged 10.1" OF for creating complete i.Core STM32MP1 C.TOUCH 2.0 10.1" Open Frame board. Add bindings for it. Signed-off-by: Jagan Teki Acked-by: Rob Herring Signed-off-by: Alexandre Torgue --- Documentation/devicetree/bindings/arm/stm32/stm32.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml index bcaf7be3ab37..b07720ea9611 100644 --- a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml +++ b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml @@ -77,6 +77,7 @@ properties: items: - enum: - engicam,icore-stm32mp1-ctouch2 # STM32MP1 Engicam i.Core STM32MP1 C.TOUCH 2.0 + - engicam,icore-stm32mp1-ctouch2-of10 # STM32MP1 Engicam i.Core STM32MP1 C.TOUCH 2.0 10.1" OF - engicam,icore-stm32mp1-edimm2.2 # STM32MP1 Engicam i.Core STM32MP1 EDIMM2.2 Starter Kit - const: engicam,icore-stm32mp1 # STM32MP1 Engicam i.Core STM32MP1 SoM - const: st,stm32mp157 -- cgit v1.2.3-59-g8ed1b From 1bf6751c8d8e2989b7b8611080b3b3b1bc0b83f4 Mon Sep 17 00:00:00 2001 From: Andrei Kartashev Date: Fri, 19 Nov 2021 15:00:56 +0300 Subject: dt-bindings: vendor-prefixes: add YADRO Add vendor prefix for YADRO (https://www.yadro.com/) Signed-off-by: Andrei Kartashev Acked-by: Rob Herring Link: https://lore.kernel.org/r/20211119120057.12118-2-a.kartashev@yadro.com Signed-off-by: Joel Stanley --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index 66d6432fd781..f0cb7dd11698 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -1350,6 +1350,8 @@ patternProperties: description: Shenzhen Xunlong Software CO.,Limited "^xylon,.*": description: Xylon + "^yadro,.*": + description: YADRO "^yamaha,.*": description: Yamaha Corporation "^yes-optoelectronics,.*": -- cgit v1.2.3-59-g8ed1b From 9e9652862ac253e7b589e6c624ac6f40df5fa297 Mon Sep 17 00:00:00 2001 From: Sven Peter Date: Tue, 30 Nov 2021 17:18:08 +0100 Subject: dt-bindings: watchdog: Add Apple Watchdog Apple SoCs come with a simple embedded watchdog. This watchdog is also required in order to reset the SoC. Reviewed-by: Mark Kettenis Reviewed-by: Rob Herring Signed-off-by: Sven Peter Reviewed-by: Guenter Roeck Signed-off-by: Hector Martin --- .../devicetree/bindings/watchdog/apple,wdt.yaml | 52 ++++++++++++++++++++++ MAINTAINERS | 1 + 2 files changed, 53 insertions(+) create mode 100644 Documentation/devicetree/bindings/watchdog/apple,wdt.yaml (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/watchdog/apple,wdt.yaml b/Documentation/devicetree/bindings/watchdog/apple,wdt.yaml new file mode 100644 index 000000000000..e58c56a6fdf6 --- /dev/null +++ b/Documentation/devicetree/bindings/watchdog/apple,wdt.yaml @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/watchdog/apple,wdt.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Apple SoC Watchdog + +allOf: + - $ref: "watchdog.yaml#" + +maintainers: + - Sven Peter + +properties: + compatible: + items: + - enum: + - apple,t8103-wdt + - apple,t6000-wdt + - const: apple,wdt + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - interrupts + +unevaluatedProperties: false + +examples: + - | + #include + #include + + wdt: watchdog@50000000 { + compatible = "apple,t8103-wdt", "apple,wdt"; + reg = <0x50000000 0x4000>; + clocks = <&clk>; + interrupts = ; + }; + +... diff --git a/MAINTAINERS b/MAINTAINERS index 7a2345ce8521..1e280e6abaf7 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1750,6 +1750,7 @@ F: Documentation/devicetree/bindings/interrupt-controller/apple,aic.yaml F: Documentation/devicetree/bindings/mailbox/apple,mailbox.yaml F: Documentation/devicetree/bindings/pci/apple,pcie.yaml F: Documentation/devicetree/bindings/pinctrl/apple,pinctrl.yaml +F: Documentation/devicetree/bindings/watchdog/apple,wdt.yaml F: arch/arm64/boot/dts/apple/ F: drivers/i2c/busses/i2c-pasemi-core.c F: drivers/i2c/busses/i2c-pasemi-platform.c -- cgit v1.2.3-59-g8ed1b From e8117f85b95b932069b9db73ccb3ee973ade2fc9 Mon Sep 17 00:00:00 2001 From: Hector Martin Date: Wed, 24 Nov 2021 16:34:16 +0900 Subject: dt-bindings: power: Add apple,pmgr-pwrstate binding This syscon child node represents a single SoC device controlled by the PMGR block. This layout allows us to declare all device power state controls (power/clock gating and reset) in the device tree, including dependencies, instead of hardcoding it into the driver. The register layout is uniform. Each pmgr-pwrstate node provides genpd and reset features, to be consumed by downstream device nodes. Future SoCs are expected to use backwards compatible registers, and the "apple,pmgr-pwrstate" represents any such interfaces (possibly with additional features gated by the more specific compatible), allowing them to be bound without driver updates. If a backwards incompatible change is introduced in future SoCs, it will require a new compatible, such as "apple,pmgr-pwrstate-v2". Reviewed-by: Mark Kettenis Reviewed-by: Rob Herring Signed-off-by: Hector Martin --- .../bindings/power/apple,pmgr-pwrstate.yaml | 71 ++++++++++++++++++++++ 1 file changed, 71 insertions(+) create mode 100644 Documentation/devicetree/bindings/power/apple,pmgr-pwrstate.yaml (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/power/apple,pmgr-pwrstate.yaml b/Documentation/devicetree/bindings/power/apple,pmgr-pwrstate.yaml new file mode 100644 index 000000000000..5056d08b8261 --- /dev/null +++ b/Documentation/devicetree/bindings/power/apple,pmgr-pwrstate.yaml @@ -0,0 +1,71 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/power/apple,pmgr-pwrstate.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Apple SoC PMGR Power States + +maintainers: + - Hector Martin + +allOf: + - $ref: "power-domain.yaml#" + +description: | + Apple SoCs include PMGR blocks responsible for power management, + which can control various clocks, resets, power states, and + performance features. This binding describes the device power + state registers, which control power states and resets. + + Each instance of a power controller within the PMGR syscon node + represents a generic power domain provider, as documented in + Documentation/devicetree/bindings/power/power-domain.yaml. + The provider controls a single SoC block. The power hierarchy is + represented via power-domains relationships between these nodes. + + See Documentation/devicetree/bindings/arm/apple/apple,pmgr.yaml + for the top-level PMGR node documentation. + +properties: + compatible: + items: + - enum: + - apple,t8103-pmgr-pwrstate + - apple,t6000-pmgr-pwrstate + - const: apple,pmgr-pwrstate + + reg: + maxItems: 1 + + "#power-domain-cells": + const: 0 + + "#reset-cells": + const: 0 + + power-domains: + description: + Reference to parent power domains. A domain may have multiple parents, + and all will be powered up when it is powered. + minItems: 1 + maxItems: 8 # Arbitrary, should be enough + + label: + description: + Specifies the name of the SoC domain being controlled. This is used to + name the power/reset domains. + + apple,always-on: + description: + Forces this power domain to always be powered up. + type: boolean + +required: + - compatible + - reg + - "#power-domain-cells" + - "#reset-cells" + - label + +additionalProperties: false -- cgit v1.2.3-59-g8ed1b From c83eeec79ff64f777cbd59a8bd15d0a3fe1f92c0 Mon Sep 17 00:00:00 2001 From: Hector Martin Date: Wed, 24 Nov 2021 16:34:17 +0900 Subject: dt-bindings: arm: apple: Add apple,pmgr binding The PMGR block in Apple Silicon SoCs is responsible for SoC power management. There are two PMGRs in T8103, with different register layouts but compatible registers. In order to support this as well as future SoC generations with backwards-compatible registers, we declare these blocks as syscons and bind to individual registers in child nodes. Each register controls one SoC device. The respective apple compatibles are defined in case device-specific quirks are necessary in the future, but currently these nodes are expected to be bound by the generic syscon driver. Reviewed-by: Mark Kettenis Reviewed-by: Rob Herring Signed-off-by: Hector Martin --- .../devicetree/bindings/arm/apple/apple,pmgr.yaml | 134 +++++++++++++++++++++ 1 file changed, 134 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/apple/apple,pmgr.yaml (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/arm/apple/apple,pmgr.yaml b/Documentation/devicetree/bindings/arm/apple/apple,pmgr.yaml new file mode 100644 index 000000000000..b6b5d3a912b3 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/apple/apple,pmgr.yaml @@ -0,0 +1,134 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/apple/apple,pmgr.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Apple SoC Power Manager (PMGR) + +maintainers: + - Hector Martin + +description: | + Apple SoCs include PMGR blocks responsible for power management, + which can control various clocks, resets, power states, and + performance features. This node represents the PMGR as a syscon, + with sub-nodes representing individual features. + +properties: + $nodename: + pattern: "^power-management@[0-9a-f]+$" + + compatible: + items: + - enum: + - apple,t8103-pmgr + - apple,t6000-pmgr + - const: apple,pmgr + - const: syscon + - const: simple-mfd + + reg: + maxItems: 1 + + "#address-cells": + const: 1 + + "#size-cells": + const: 1 + +patternProperties: + "power-controller@[0-9a-f]+$": + description: + The individual power management domains within this controller + type: object + $ref: /power/apple,pmgr-pwrstate.yaml# + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + soc { + #address-cells = <2>; + #size-cells = <2>; + + power-management@23b700000 { + compatible = "apple,t8103-pmgr", "apple,pmgr", "syscon", "simple-mfd"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x2 0x3b700000 0x0 0x14000>; + + ps_sio: power-controller@1c0 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x1c0 8>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "sio"; + apple,always-on; + }; + + ps_uart_p: power-controller@220 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x220 8>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart_p"; + power-domains = <&ps_sio>; + }; + + ps_uart0: power-controller@270 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x270 8>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart0"; + power-domains = <&ps_uart_p>; + }; + }; + + power-management@23d280000 { + compatible = "apple,t8103-pmgr", "apple,pmgr", "syscon", "simple-mfd"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x2 0x3d280000 0x0 0xc000>; + + ps_aop_filter: power-controller@4000 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x4000 8>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "aop_filter"; + }; + + ps_aop_base: power-controller@4010 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x4010 8>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "aop_base"; + power-domains = <&ps_aop_filter>; + }; + + ps_aop_shim: power-controller@4038 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x4038 8>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "aop_shim"; + power-domains = <&ps_aop_base>; + }; + + ps_aop_uart0: power-controller@4048 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x4048 8>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "aop_uart0"; + power-domains = <&ps_aop_shim>; + }; + }; + }; -- cgit v1.2.3-59-g8ed1b From d01986bec3887a3dbf61cbd821979f91cf0bb2dc Mon Sep 17 00:00:00 2001 From: Yoshihiro Shimoda Date: Wed, 1 Dec 2021 16:32:55 +0900 Subject: dt-bindings: arm: renesas: Document Renesas Spider boards Add device tree bindings documentation for Renesas R-Car S4-8 Spider CPU and BreakOut boards. Signed-off-by: Yoshihiro Shimoda Link: https://lore.kernel.org/r/20211201073308.1003945-2-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven --- Documentation/devicetree/bindings/arm/renesas.yaml | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/arm/renesas.yaml b/Documentation/devicetree/bindings/arm/renesas.yaml index 36197f53b310..6a9350ee690b 100644 --- a/Documentation/devicetree/bindings/arm/renesas.yaml +++ b/Documentation/devicetree/bindings/arm/renesas.yaml @@ -317,6 +317,14 @@ properties: - description: R-Car S4-8 (R8A779F0) items: + - enum: + - renesas,spider-cpu # Spider CPU board (RTP8A779F0ASKB0SC2S) + - const: renesas,r8a779f0 + + - items: + - enum: + - renesas,spider-breakout # Spider BreakOut board (RTP8A779F0ASKB0SB0S) + - const: renesas,spider-cpu - const: renesas,r8a779f0 - description: R-Car H3e (R8A779M0) -- cgit v1.2.3-59-g8ed1b From d824dade33bfe464a5304f1772de8735a46eec7c Mon Sep 17 00:00:00 2001 From: Hector Martin Date: Thu, 9 Dec 2021 13:44:59 +0900 Subject: dt-bindings: power: apple,pmgr-pwrstate: Add apple,min-state prop A few devices (DCP/DCPEXT) need to have the minimum power state for auto-PM configured. Add a property that allows the DT to specify this value. Reviewed-by: Rob Herring Signed-off-by: Hector Martin --- Documentation/devicetree/bindings/power/apple,pmgr-pwrstate.yaml | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/power/apple,pmgr-pwrstate.yaml b/Documentation/devicetree/bindings/power/apple,pmgr-pwrstate.yaml index 5056d08b8261..19a194980142 100644 --- a/Documentation/devicetree/bindings/power/apple,pmgr-pwrstate.yaml +++ b/Documentation/devicetree/bindings/power/apple,pmgr-pwrstate.yaml @@ -61,6 +61,14 @@ properties: Forces this power domain to always be powered up. type: boolean + apple,min-state: + description: + Specifies the minimum power state for auto-PM. + 0 = power gated, 4 = clock gated, 15 = on. + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 15 + required: - compatible - reg -- cgit v1.2.3-59-g8ed1b From e15b8c8563983c134869890d7a88aada33c52885 Mon Sep 17 00:00:00 2001 From: Hector Martin Date: Thu, 9 Dec 2021 14:09:58 +0900 Subject: dt-bindings: arm: apple: Add t6000/t6001 MacBook Pro 14/16" compatibles This adds the initial apple,t6000 platforms: - apple,j314s - MacBook Pro (14-inch, M1 Pro, 2021) - apple,j316s - MacBook Pro (16-inch, M1 Pro, 2021) And the initial apple,t6001 platforms: - apple,j314c - MacBook Pro (14-inch, M1 Max, 2021) - apple,j316c - MacBook Pro (16-inch, M1 Max, 2021) Reviewed-by: Mark Kettenis Acked-by: Rob Herring Signed-off-by: Hector Martin --- Documentation/devicetree/bindings/arm/apple.yaml | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/arm/apple.yaml b/Documentation/devicetree/bindings/arm/apple.yaml index b23c8dc5a27d..8d93e8a6cc18 100644 --- a/Documentation/devicetree/bindings/arm/apple.yaml +++ b/Documentation/devicetree/bindings/arm/apple.yaml @@ -19,6 +19,13 @@ description: | - MacBook Air (M1, 2020) - iMac (24-inch, M1, 2021) + And devices based on the "M1 Pro" and "M1 Max" SoCs: + + - MacBook Pro (14-inch, M1 Pro, 2021) + - MacBook Pro (14-inch, M1 Max, 2021) + - MacBook Pro (16-inch, M1 Pro, 2021) + - MacBook Pro (16-inch, M1 Max, 2021) + The compatible property should follow this format: compatible = "apple,", "apple,", "apple,arm-platform"; @@ -60,6 +67,20 @@ properties: - apple,j457 # iMac (24-inch, 2x USB-C, M1, 2021) - const: apple,t8103 - const: apple,arm-platform + - description: Apple M1 Pro SoC based platforms + items: + - enum: + - apple,j314s # MacBook Pro (14-inch, M1 Pro, 2021) + - apple,j316s # MacBook Pro (16-inch, M1 Pro, 2021) + - const: apple,t6000 + - const: apple,arm-platform + - description: Apple M1 Max SoC based platforms + items: + - enum: + - apple,j314c # MacBook Pro (14-inch, M1 Max, 2021) + - apple,j316c # MacBook Pro (16-inch, M1 Max, 2021) + - const: apple,t6001 + - const: apple,arm-platform additionalProperties: true -- cgit v1.2.3-59-g8ed1b From b66652c7517c80873258a00cccf56a2d133a5efe Mon Sep 17 00:00:00 2001 From: Hector Martin Date: Thu, 9 Dec 2021 14:09:59 +0900 Subject: dt-bindings: i2c: apple,i2c: Add apple,t6000-i2c compatible This block is compatible with t8103, so just add the new per-SoC compatible under apple,i2c. Reviewed-by: Mark Kettenis Reviewed-by: Sven Peter Acked-by: Rob Herring Signed-off-by: Hector Martin --- Documentation/devicetree/bindings/i2c/apple,i2c.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/i2c/apple,i2c.yaml b/Documentation/devicetree/bindings/i2c/apple,i2c.yaml index 47dd6c107a6d..4ac61fec90e2 100644 --- a/Documentation/devicetree/bindings/i2c/apple,i2c.yaml +++ b/Documentation/devicetree/bindings/i2c/apple,i2c.yaml @@ -21,7 +21,9 @@ allOf: properties: compatible: items: - - const: apple,t8103-i2c + - enum: + - apple,t8103-i2c + - apple,t6000-i2c - const: apple,i2c reg: -- cgit v1.2.3-59-g8ed1b From 42c2366a9cbedc32921f0e53e14b7bef1d536514 Mon Sep 17 00:00:00 2001 From: Hector Martin Date: Thu, 9 Dec 2021 14:10:00 +0900 Subject: dt-bindings: pci: apple,pcie: Add t6000 support This new SoC is compatible with the existing driver, but the block supports 4 downstream ports, so we need to adjust the binding to allow that. Reviewed-by: Mark Kettenis Acked-by: Rob Herring Signed-off-by: Hector Martin --- .../devicetree/bindings/pci/apple,pcie.yaml | 28 ++++++++++++++++------ 1 file changed, 21 insertions(+), 7 deletions(-) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/pci/apple,pcie.yaml b/Documentation/devicetree/bindings/pci/apple,pcie.yaml index ef1d424ec299..7f01e15fc81c 100644 --- a/Documentation/devicetree/bindings/pci/apple,pcie.yaml +++ b/Documentation/devicetree/bindings/pci/apple,pcie.yaml @@ -28,19 +28,17 @@ description: | distributed over the root ports as the OS sees fit by programming the PCIe controller's port registers. -allOf: - - $ref: /schemas/pci/pci-bus.yaml# - - $ref: /schemas/interrupt-controller/msi-controller.yaml# - properties: compatible: items: - - const: apple,t8103-pcie + - enum: + - apple,t8103-pcie + - apple,t6000-pcie - const: apple,pcie reg: minItems: 3 - maxItems: 5 + maxItems: 6 reg-names: minItems: 3 @@ -50,6 +48,7 @@ properties: - const: port0 - const: port1 - const: port2 + - const: port3 ranges: minItems: 2 @@ -59,7 +58,7 @@ properties: description: Interrupt specifiers, one for each root port. minItems: 1 - maxItems: 3 + maxItems: 4 msi-parent: true @@ -81,6 +80,21 @@ required: unevaluatedProperties: false +allOf: + - $ref: /schemas/pci/pci-bus.yaml# + - $ref: /schemas/interrupt-controller/msi-controller.yaml# + - if: + properties: + compatible: + contains: + const: apple,t8103-pcie + then: + properties: + reg: + maxItems: 5 + interrupts: + maxItems: 3 + examples: - | #include -- cgit v1.2.3-59-g8ed1b From cba9c615bec18792c32cc95f478884e24de9d1a5 Mon Sep 17 00:00:00 2001 From: Hector Martin Date: Thu, 9 Dec 2021 14:10:01 +0900 Subject: dt-bindings: pinctrl: apple,pinctrl: Add apple,t6000-pinctrl compatible This new SoC uses the same pinctrl hardware, so just add a new per-SoC compatible. Reviewed-by: Mark Kettenis Acked-by: Rob Herring Signed-off-by: Hector Martin --- Documentation/devicetree/bindings/pinctrl/apple,pinctrl.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/pinctrl/apple,pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/apple,pinctrl.yaml index 200d411621e7..572923d7023e 100644 --- a/Documentation/devicetree/bindings/pinctrl/apple,pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/apple,pinctrl.yaml @@ -17,7 +17,9 @@ description: | properties: compatible: items: - - const: apple,t8103-pinctrl + - enum: + - apple,t8103-pinctrl + - apple,t6000-pinctrl - const: apple,pinctrl reg: -- cgit v1.2.3-59-g8ed1b From 6b1caf4dea3e0a961b7a11cff6757ff74c1c34ea Mon Sep 17 00:00:00 2001 From: Aswath Govindraju Date: Tue, 7 Dec 2021 13:39:00 +0530 Subject: dt-bindings: arm: ti: Add bindings for J721s2 SoC Add binding for J721S2 SoC Signed-off-by: Aswath Govindraju Signed-off-by: Vignesh Raghavendra Reviewed-by: Kishon Vijay Abraham I Acked-by: Rob Herring Link: https://lore.kernel.org/r/20211207080904.14324-2-a-govindraju@ti.com --- Documentation/devicetree/bindings/arm/ti/k3.yaml | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/arm/ti/k3.yaml b/Documentation/devicetree/bindings/arm/ti/k3.yaml index cf327230fc0e..b03c10fa2e7a 100644 --- a/Documentation/devicetree/bindings/arm/ti/k3.yaml +++ b/Documentation/devicetree/bindings/arm/ti/k3.yaml @@ -53,6 +53,12 @@ properties: - ti,am642-sk - const: ti,am642 + - description: K3 J721s2 SoC + items: + - enum: + - ti,j721s2-evm + - const: ti,j721s2 + additionalProperties: true ... -- cgit v1.2.3-59-g8ed1b From ced795c2648aae44314aa8027e8e1d691ea6153f Mon Sep 17 00:00:00 2001 From: Ivan Bornyakov Date: Thu, 2 Dec 2021 08:57:24 +0300 Subject: dt-bindings: bus: imx-weim: add words about continuous bclk Document continuous Burst Clock option. With this option Burst Clock, if enabled, will output continuous clock, otherwise Burst Clock will output clock only when necessary. Signed-off-by: Ivan Bornyakov Reviewed-by: Rob Herring Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/bus/imx-weim.txt | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/bus/imx-weim.txt b/Documentation/devicetree/bindings/bus/imx-weim.txt index 1b1d1c5c21ea..e7f502070d77 100644 --- a/Documentation/devicetree/bindings/bus/imx-weim.txt +++ b/Documentation/devicetree/bindings/bus/imx-weim.txt @@ -48,6 +48,11 @@ Optional properties: devices, the presence of this property indicates that the weim bus should operate in Burst Clock Mode. + - fsl,continuous-burst-clk Make Burst Clock to output continuous clock. + Without this option Burst Clock will output clock + only when necessary. This takes effect only if + "fsl,burst-clk-enable" is set. + Timing property for child nodes. It is mandatory, not optional. - fsl,weim-cs-timing: The timing array, contains timing values for the -- cgit v1.2.3-59-g8ed1b From c4cacb5b80f4f1d83b8bcd6e16672d6732982414 Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Thu, 2 Dec 2021 08:38:26 -0600 Subject: dt-bindings: soc: imx: Add binding doc for spba bus Add binding doc for fsl,spba-bus. Signed-off-by: Adam Ford Reviewed-by: Rob Herring Signed-off-by: Shawn Guo --- .../devicetree/bindings/bus/fsl,spba-bus.yaml | 68 ++++++++++++++++++++++ 1 file changed, 68 insertions(+) create mode 100644 Documentation/devicetree/bindings/bus/fsl,spba-bus.yaml (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/bus/fsl,spba-bus.yaml b/Documentation/devicetree/bindings/bus/fsl,spba-bus.yaml new file mode 100644 index 000000000000..d42dbb0bbc2e --- /dev/null +++ b/Documentation/devicetree/bindings/bus/fsl,spba-bus.yaml @@ -0,0 +1,68 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bus/fsl,spba-bus.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Shared Peripherals Bus Interface + +maintainers: + - Shawn Guo + +description: | + A simple bus enabling access to shared peripherals. + + The "spba-bus" follows the "simple-bus" set of properties, as + specified in the Devicetree Specification. It is an extension of + "simple-bus" because the SDMA controller uses this compatible flag to + determine which peripherals are available to it and the range over which + the SDMA can access. There are no special clocks for the bus, because + the SDMA controller itself has its interrupt and clock assignments. + +select: + properties: + compatible: + contains: + const: fsl,spba-bus + required: + - compatible + +properties: + $nodename: + pattern: "^spba-bus(@[0-9a-f]+)?$" + + compatible: + items: + - const: fsl,spba-bus + - const: simple-bus + + '#address-cells': + enum: [ 1, 2 ] + + '#size-cells': + enum: [ 1, 2 ] + + reg: + maxItems: 1 + + ranges: true + +required: + - compatible + - '#address-cells' + - '#size-cells' + - reg + - ranges + +additionalProperties: + type: object + +examples: + - | + spba-bus@30000000 { + compatible = "fsl,spba-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x30000000 0x100000>; + ranges; + }; -- cgit v1.2.3-59-g8ed1b From 63aca69c224fd2a38e02598a8ce48b984c7e9c76 Mon Sep 17 00:00:00 2001 From: Ariel D'Alessandro Date: Fri, 10 Dec 2021 10:23:15 -0300 Subject: dt-bindings: Add vendor prefix for BSH Hausgeraete GmbH Document vendor prefix for BSH Hausgeraete GmbH ('BSH Home Appliances', B/S/H/) manufacturer. Signed-off-by: Ariel D'Alessandro Acked-by: Rob Herring Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index 6414f5fdcb91..b491666ba620 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -187,6 +187,8 @@ patternProperties: description: Shanghai Broadmobi Communication Technology Co.,Ltd. "^brcm,.*": description: Broadcom Corporation + "^bsh,.*": + description: BSH Hausgeraete GmbH "^buffalo,.*": description: Buffalo, Inc. "^bur,.*": -- cgit v1.2.3-59-g8ed1b From 50cee5eb406b9557f30a2824691b26d2a74f1a8a Mon Sep 17 00:00:00 2001 From: Ariel D'Alessandro Date: Fri, 10 Dec 2021 10:23:16 -0300 Subject: dt-bindings: arm: fsl: Add iMX8MN BSH SMM S2 boards Add bindings for BSH SystemMaster (SMM) S2 board family, which consists of: iMX8MN SMM S2 and iMX8MN SMM S2 PRO boards. Signed-off-by: Ariel D'Alessandro Acked-by: Rob Herring Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index c35076cc551d..d065721d65e9 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -807,6 +807,8 @@ properties: items: - enum: - beacon,imx8mn-beacon-kit # i.MX8MN Beacon Development Kit + - bsh,imx8mn-bsh-smm-s2 # i.MX8MN BSH SystemMaster S2 + - bsh,imx8mn-bsh-smm-s2pro # i.MX8MN BSH SystemMaster S2 PRO - fsl,imx8mn-ddr4-evk # i.MX8MN DDR4 EVK Board - fsl,imx8mn-evk # i.MX8MN LPDDR4 EVK Board - gw,imx8mn-gw7902 # i.MX8MM Gateworks Board -- cgit v1.2.3-59-g8ed1b From 8802266a103343da81fc99f7977273713e0e1980 Mon Sep 17 00:00:00 2001 From: Ariel D'Alessandro Date: Fri, 10 Dec 2021 10:23:18 -0300 Subject: dt-bindings: arm: fsl: Add BSH SMM-M2 IMX6ULZ SystemMaster board Add bindings for BSH SystemMaster (SMM) M2 IMX6ULZ board. Signed-off-by: Ariel D'Alessandro Acked-by: Rob Herring Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index d065721d65e9..97f6eebad76a 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -670,6 +670,7 @@ properties: - description: i.MX6ULZ based Boards items: - enum: + - bsh,imx6ulz-bsh-smm-m2 # i.MX6 ULZ BSH SystemMaster - fsl,imx6ulz-14x14-evk # i.MX6 ULZ 14x14 EVK Board - const: fsl,imx6ull # This seems odd. Should be last? - const: fsl,imx6ulz -- cgit v1.2.3-59-g8ed1b From 8f8ef3860d4403d1bf0887380f9e3376be092c40 Mon Sep 17 00:00:00 2001 From: Vamsi krishna Lanka Date: Mon, 6 Dec 2021 23:32:49 -0800 Subject: dt-bindings: clock: Add SDX65 GCC clock bindings Add device tree bindings for global clock controller on SDX65 SOCs. Signed-off-by: Vamsi Krishna Lanka Reviewed-by: Rob Herring Reviewed-by: Vinod Koul Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/e15509b2b7c9b600ab38c5269d4fac609c077b5b.1638861860.git.quic_vamslank@quicinc.com --- .../devicetree/bindings/clock/qcom,gcc-sdx65.yaml | 80 ++++++++++++++ include/dt-bindings/clock/qcom,gcc-sdx65.h | 122 +++++++++++++++++++++ 2 files changed, 202 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,gcc-sdx65.yaml create mode 100644 include/dt-bindings/clock/qcom,gcc-sdx65.h (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sdx65.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sdx65.yaml new file mode 100644 index 000000000000..16c4cdc7b4d6 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sdx65.yaml @@ -0,0 +1,80 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,gcc-sdx65.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Global Clock & Reset Controller Binding for SDX65 + +maintainers: + - Vamsi krishna Lanka + +description: | + Qualcomm global clock control module which supports the clocks, resets and + power domains on SDX65 + + See also: + - dt-bindings/clock/qcom,gcc-sdx65.h + +properties: + compatible: + const: qcom,gcc-sdx65 + + reg: + maxItems: 1 + + clocks: + items: + - description: Board XO source + - description: Board active XO source + - description: Sleep clock source + - description: PCIE Pipe clock source + - description: USB3 phy wrapper pipe clock source + - description: PLL test clock source (Optional clock) + minItems: 5 + + clock-names: + items: + - const: bi_tcxo + - const: bi_tcxo_ao + - const: sleep_clk + - const: pcie_pipe_clk + - const: usb3_phy_wrapper_gcc_usb30_pipe_clk + - const: core_bi_pll_test_se # Optional clock + minItems: 5 + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + + '#power-domain-cells': + const: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + - '#reset-cells' + - '#power-domain-cells' + +additionalProperties: false + +examples: + - | + #include + clock-controller@100000 { + compatible = "qcom,gcc-sdx65"; + reg = <0x100000 0x1f7400>; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>, + <&pcie_pipe_clk>, <&usb3_phy_wrapper_gcc_usb30_pipe_clk>, <&pll_test_clk>; + clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", + "pcie_pipe_clk", "usb3_phy_wrapper_gcc_usb30_pipe_clk", "core_bi_pll_test_se"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; +... diff --git a/include/dt-bindings/clock/qcom,gcc-sdx65.h b/include/dt-bindings/clock/qcom,gcc-sdx65.h new file mode 100644 index 000000000000..75ecc9237d8f --- /dev/null +++ b/include/dt-bindings/clock/qcom,gcc-sdx65.h @@ -0,0 +1,122 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SDX65_H +#define _DT_BINDINGS_CLK_QCOM_GCC_SDX65_H + +/* GCC clocks */ +#define GPLL0 0 +#define GPLL0_OUT_EVEN 1 +#define GCC_AHB_PCIE_LINK_CLK 2 +#define GCC_BLSP1_AHB_CLK 3 +#define GCC_BLSP1_QUP1_I2C_APPS_CLK 4 +#define GCC_BLSP1_QUP1_I2C_APPS_CLK_SRC 5 +#define GCC_BLSP1_QUP1_SPI_APPS_CLK 6 +#define GCC_BLSP1_QUP1_SPI_APPS_CLK_SRC 7 +#define GCC_BLSP1_QUP2_I2C_APPS_CLK 8 +#define GCC_BLSP1_QUP2_I2C_APPS_CLK_SRC 9 +#define GCC_BLSP1_QUP2_SPI_APPS_CLK 10 +#define GCC_BLSP1_QUP2_SPI_APPS_CLK_SRC 11 +#define GCC_BLSP1_QUP3_I2C_APPS_CLK 12 +#define GCC_BLSP1_QUP3_I2C_APPS_CLK_SRC 13 +#define GCC_BLSP1_QUP3_SPI_APPS_CLK 14 +#define GCC_BLSP1_QUP3_SPI_APPS_CLK_SRC 15 +#define GCC_BLSP1_QUP4_I2C_APPS_CLK 16 +#define GCC_BLSP1_QUP4_I2C_APPS_CLK_SRC 17 +#define GCC_BLSP1_QUP4_SPI_APPS_CLK 18 +#define GCC_BLSP1_QUP4_SPI_APPS_CLK_SRC 19 +#define GCC_BLSP1_SLEEP_CLK 20 +#define GCC_BLSP1_UART1_APPS_CLK 21 +#define GCC_BLSP1_UART1_APPS_CLK_SRC 22 +#define GCC_BLSP1_UART2_APPS_CLK 23 +#define GCC_BLSP1_UART2_APPS_CLK_SRC 24 +#define GCC_BLSP1_UART3_APPS_CLK 25 +#define GCC_BLSP1_UART3_APPS_CLK_SRC 26 +#define GCC_BLSP1_UART4_APPS_CLK 27 +#define GCC_BLSP1_UART4_APPS_CLK_SRC 28 +#define GCC_BOOT_ROM_AHB_CLK 29 +#define GCC_CPUSS_AHB_CLK 30 +#define GCC_CPUSS_AHB_CLK_SRC 31 +#define GCC_CPUSS_AHB_POSTDIV_CLK_SRC 32 +#define GCC_CPUSS_GNOC_CLK 33 +#define GCC_GP1_CLK 34 +#define GCC_GP1_CLK_SRC 35 +#define GCC_GP2_CLK 36 +#define GCC_GP2_CLK_SRC 37 +#define GCC_GP3_CLK 38 +#define GCC_GP3_CLK_SRC 39 +#define GCC_PCIE_0_CLKREF_EN 40 +#define GCC_PCIE_AUX_CLK 41 +#define GCC_PCIE_AUX_CLK_SRC 42 +#define GCC_PCIE_AUX_PHY_CLK_SRC 43 +#define GCC_PCIE_CFG_AHB_CLK 44 +#define GCC_PCIE_MSTR_AXI_CLK 45 +#define GCC_PCIE_PIPE_CLK 46 +#define GCC_PCIE_PIPE_CLK_SRC 47 +#define GCC_PCIE_RCHNG_PHY_CLK 48 +#define GCC_PCIE_RCHNG_PHY_CLK_SRC 49 +#define GCC_PCIE_SLEEP_CLK 50 +#define GCC_PCIE_SLV_AXI_CLK 51 +#define GCC_PCIE_SLV_Q2A_AXI_CLK 52 +#define GCC_PDM2_CLK 53 +#define GCC_PDM2_CLK_SRC 54 +#define GCC_PDM_AHB_CLK 55 +#define GCC_PDM_XO4_CLK 56 +#define GCC_RX1_USB2_CLKREF_EN 57 +#define GCC_SDCC1_AHB_CLK 58 +#define GCC_SDCC1_APPS_CLK 59 +#define GCC_SDCC1_APPS_CLK_SRC 60 +#define GCC_SPMI_FETCHER_AHB_CLK 61 +#define GCC_SPMI_FETCHER_CLK 62 +#define GCC_SPMI_FETCHER_CLK_SRC 63 +#define GCC_SYS_NOC_CPUSS_AHB_CLK 64 +#define GCC_USB30_MASTER_CLK 65 +#define GCC_USB30_MASTER_CLK_SRC 66 +#define GCC_USB30_MOCK_UTMI_CLK 67 +#define GCC_USB30_MOCK_UTMI_CLK_SRC 68 +#define GCC_USB30_MOCK_UTMI_POSTDIV_CLK_SRC 69 +#define GCC_USB30_MSTR_AXI_CLK 70 +#define GCC_USB30_SLEEP_CLK 71 +#define GCC_USB30_SLV_AHB_CLK 72 +#define GCC_USB3_PHY_AUX_CLK 73 +#define GCC_USB3_PHY_AUX_CLK_SRC 74 +#define GCC_USB3_PHY_PIPE_CLK 75 +#define GCC_USB3_PHY_PIPE_CLK_SRC 76 +#define GCC_USB3_PRIM_CLKREF_EN 77 +#define GCC_USB_PHY_CFG_AHB2PHY_CLK 78 +#define GCC_XO_DIV4_CLK 79 +#define GCC_XO_PCIE_LINK_CLK 80 + +/* GCC resets */ +#define GCC_BLSP1_QUP1_BCR 0 +#define GCC_BLSP1_QUP2_BCR 1 +#define GCC_BLSP1_QUP3_BCR 2 +#define GCC_BLSP1_QUP4_BCR 3 +#define GCC_BLSP1_UART1_BCR 4 +#define GCC_BLSP1_UART2_BCR 5 +#define GCC_BLSP1_UART3_BCR 6 +#define GCC_BLSP1_UART4_BCR 7 +#define GCC_PCIE_BCR 8 +#define GCC_PCIE_LINK_DOWN_BCR 9 +#define GCC_PCIE_NOCSR_COM_PHY_BCR 10 +#define GCC_PCIE_PHY_BCR 11 +#define GCC_PCIE_PHY_CFG_AHB_BCR 12 +#define GCC_PCIE_PHY_COM_BCR 13 +#define GCC_PCIE_PHY_NOCSR_COM_PHY_BCR 14 +#define GCC_PDM_BCR 15 +#define GCC_QUSB2PHY_BCR 16 +#define GCC_SDCC1_BCR 17 +#define GCC_SPMI_FETCHER_BCR 18 +#define GCC_TCSR_PCIE_BCR 19 +#define GCC_USB30_BCR 20 +#define GCC_USB3_PHY_BCR 21 +#define GCC_USB3PHY_PHY_BCR 22 +#define GCC_USB_PHY_CFG_AHB2PHY_BCR 23 + +/* GCC power domains */ +#define USB30_GDSC 0 +#define PCIE_GDSC 1 + +#endif -- cgit v1.2.3-59-g8ed1b From 3b338c9a6a2afd6db46d5d8e39ae4f5eef420bf8 Mon Sep 17 00:00:00 2001 From: Vamsi krishna Lanka Date: Fri, 29 Oct 2021 17:02:03 -0700 Subject: dt-bindings: arm: qcom: Document SDX65 platform and boards Document the SDX65 platform binding and also the boards using it. Signed-off-by: Vamsi Krishna Lanka Reviewed-by: Bjorn Andersson Acked-by: Rob Herring Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1635552125-16407-2-git-send-email-quic_vamslank@quicinc.com --- Documentation/devicetree/bindings/arm/qcom.yaml | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index c8808e0f9e64..2d613282816a 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -48,6 +48,7 @@ description: | sdx65 sm7225 sm8150 + sdx65 sm8250 sm8350 @@ -224,6 +225,11 @@ properties: - qcom,sdx65-mtp - const: qcom,sdx65 + - items: + - enum: + - qcom,sdx65-mtp + - const: qcom,sdx65 + - items: - enum: - qcom,ipq6018-cp01 -- cgit v1.2.3-59-g8ed1b From 72a0ca203ca7fae34fe61668906fe483b97d9039 Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Tue, 7 Dec 2021 17:10:02 +0530 Subject: dt-bindings: clock: Add SM8450 GCC clock bindings Add device tree bindings for global clock controller on SM8450 SoCs. Signed-off-by: Vinod Koul Reviewed-by: Stephen Boyd Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211207114003.100693-2-vkoul@kernel.org --- .../devicetree/bindings/clock/qcom,gcc-sm8450.yaml | 85 +++++++ include/dt-bindings/clock/qcom,gcc-sm8450.h | 244 +++++++++++++++++++++ 2 files changed, 329 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,gcc-sm8450.yaml create mode 100644 include/dt-bindings/clock/qcom,gcc-sm8450.h (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sm8450.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sm8450.yaml new file mode 100644 index 000000000000..58d98a766de6 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sm8450.yaml @@ -0,0 +1,85 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,gcc-sm8450.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Global Clock & Reset Controller Binding for SM8450 + +maintainers: + - Vinod Koul + +description: | + Qualcomm global clock control module which supports the clocks, resets and + power domains on SM8450 + + See also: + - dt-bindings/clock/qcom,gcc-sm8450.h + +properties: + compatible: + const: qcom,gcc-sm8450 + + clocks: + items: + - description: Board XO source + - description: Sleep clock source + - description: PCIE 0 Pipe clock source (Optional clock) + - description: PCIE 1 Pipe clock source (Optional clock) + - description: PCIE 1 Phy Auxillary clock source (Optional clock) + - description: UFS Phy Rx symbol 0 clock source (Optional clock) + - description: UFS Phy Rx symbol 1 clock source (Optional clock) + - description: UFS Phy Tx symbol 0 clock source (Optional clock) + - description: USB3 Phy wrapper pipe clock source (Optional clock) + minItems: 2 + + clock-names: + items: + - const: bi_tcxo + - const: sleep_clk + - const: pcie_0_pipe_clk # Optional clock + - const: pcie_1_pipe_clk # Optional clock + - const: pcie_1_phy_aux_clk # Optional clock + - const: ufs_phy_rx_symbol_0_clk # Optional clock + - const: ufs_phy_rx_symbol_1_clk # Optional clock + - const: ufs_phy_tx_symbol_0_clk # Optional clock + - const: usb3_phy_wrapper_gcc_usb30_pipe_clk # Optional clock + minItems: 2 + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + + '#power-domain-cells': + const: 1 + + reg: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + - '#reset-cells' + - '#power-domain-cells' + +additionalProperties: false + +examples: + - | + #include + clock-controller@100000 { + compatible = "qcom,gcc-sm8450"; + reg = <0x00100000 0x001f4200>; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>; + clock-names = "bi_tcxo", "sleep_clk"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + +... diff --git a/include/dt-bindings/clock/qcom,gcc-sm8450.h b/include/dt-bindings/clock/qcom,gcc-sm8450.h new file mode 100644 index 000000000000..cf1469312c4c --- /dev/null +++ b/include/dt-bindings/clock/qcom,gcc-sm8450.h @@ -0,0 +1,244 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2021, Linaro Limited + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SM8450_H +#define _DT_BINDINGS_CLK_QCOM_GCC_SM8450_H + +/* GCC HW clocks */ +#define CORE_BI_PLL_TEST_SE 0 +#define PCIE_0_PIPE_CLK 1 +#define PCIE_1_PHY_AUX_CLK 2 +#define PCIE_1_PIPE_CLK 3 +#define UFS_PHY_RX_SYMBOL_0_CLK 4 +#define UFS_PHY_RX_SYMBOL_1_CLK 5 +#define UFS_PHY_TX_SYMBOL_0_CLK 6 +#define USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK 7 + +/* GCC clocks */ +#define GCC_AGGRE_NOC_PCIE_0_AXI_CLK 8 +#define GCC_AGGRE_NOC_PCIE_1_AXI_CLK 9 +#define GCC_AGGRE_UFS_PHY_AXI_CLK 10 +#define GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK 11 +#define GCC_AGGRE_USB3_PRIM_AXI_CLK 12 +#define GCC_ANOC_PCIE_PWRCTL_CLK 13 +#define GCC_BOOT_ROM_AHB_CLK 14 +#define GCC_CAMERA_AHB_CLK 15 +#define GCC_CAMERA_HF_AXI_CLK 16 +#define GCC_CAMERA_SF_AXI_CLK 17 +#define GCC_CAMERA_XO_CLK 18 +#define GCC_CFG_NOC_PCIE_ANOC_AHB_CLK 19 +#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 20 +#define GCC_CPUSS_AHB_CLK 21 +#define GCC_CPUSS_AHB_CLK_SRC 22 +#define GCC_CPUSS_AHB_POSTDIV_CLK_SRC 23 +#define GCC_CPUSS_CONFIG_NOC_SF_CLK 24 +#define GCC_DDRSS_GPU_AXI_CLK 25 +#define GCC_DDRSS_PCIE_SF_TBU_CLK 26 +#define GCC_DISP_AHB_CLK 27 +#define GCC_DISP_HF_AXI_CLK 28 +#define GCC_DISP_SF_AXI_CLK 29 +#define GCC_DISP_XO_CLK 30 +#define GCC_EUSB3_0_CLKREF_EN 31 +#define GCC_GP1_CLK 32 +#define GCC_GP1_CLK_SRC 33 +#define GCC_GP2_CLK 34 +#define GCC_GP2_CLK_SRC 35 +#define GCC_GP3_CLK 36 +#define GCC_GP3_CLK_SRC 37 +#define GCC_GPLL0 38 +#define GCC_GPLL0_OUT_EVEN 39 +#define GCC_GPLL4 40 +#define GCC_GPLL9 41 +#define GCC_GPU_CFG_AHB_CLK 42 +#define GCC_GPU_GPLL0_CLK_SRC 43 +#define GCC_GPU_GPLL0_DIV_CLK_SRC 44 +#define GCC_GPU_MEMNOC_GFX_CLK 45 +#define GCC_GPU_SNOC_DVM_GFX_CLK 46 +#define GCC_PCIE_0_AUX_CLK 47 +#define GCC_PCIE_0_AUX_CLK_SRC 48 +#define GCC_PCIE_0_CFG_AHB_CLK 49 +#define GCC_PCIE_0_CLKREF_EN 50 +#define GCC_PCIE_0_MSTR_AXI_CLK 51 +#define GCC_PCIE_0_PHY_RCHNG_CLK 52 +#define GCC_PCIE_0_PHY_RCHNG_CLK_SRC 53 +#define GCC_PCIE_0_PIPE_CLK 54 +#define GCC_PCIE_0_PIPE_CLK_SRC 55 +#define GCC_PCIE_0_SLV_AXI_CLK 56 +#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 57 +#define GCC_PCIE_1_AUX_CLK 58 +#define GCC_PCIE_1_AUX_CLK_SRC 59 +#define GCC_PCIE_1_CFG_AHB_CLK 60 +#define GCC_PCIE_1_CLKREF_EN 61 +#define GCC_PCIE_1_MSTR_AXI_CLK 62 +#define GCC_PCIE_1_PHY_AUX_CLK 63 +#define GCC_PCIE_1_PHY_AUX_CLK_SRC 64 +#define GCC_PCIE_1_PHY_RCHNG_CLK 65 +#define GCC_PCIE_1_PHY_RCHNG_CLK_SRC 66 +#define GCC_PCIE_1_PIPE_CLK 67 +#define GCC_PCIE_1_PIPE_CLK_SRC 68 +#define GCC_PCIE_1_SLV_AXI_CLK 69 +#define GCC_PCIE_1_SLV_Q2A_AXI_CLK 70 +#define GCC_PDM2_CLK 71 +#define GCC_PDM2_CLK_SRC 72 +#define GCC_PDM_AHB_CLK 73 +#define GCC_PDM_XO4_CLK 74 +#define GCC_QMIP_CAMERA_NRT_AHB_CLK 75 +#define GCC_QMIP_CAMERA_RT_AHB_CLK 76 +#define GCC_QMIP_DISP_AHB_CLK 77 +#define GCC_QMIP_GPU_AHB_CLK 78 +#define GCC_QMIP_PCIE_AHB_CLK 79 +#define GCC_QMIP_VIDEO_CV_CPU_AHB_CLK 80 +#define GCC_QMIP_VIDEO_CVP_AHB_CLK 81 +#define GCC_QMIP_VIDEO_V_CPU_AHB_CLK 82 +#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 83 +#define GCC_QUPV3_WRAP0_CORE_2X_CLK 84 +#define GCC_QUPV3_WRAP0_CORE_CLK 85 +#define GCC_QUPV3_WRAP0_S0_CLK 86 +#define GCC_QUPV3_WRAP0_S0_CLK_SRC 87 +#define GCC_QUPV3_WRAP0_S1_CLK 88 +#define GCC_QUPV3_WRAP0_S1_CLK_SRC 89 +#define GCC_QUPV3_WRAP0_S2_CLK 90 +#define GCC_QUPV3_WRAP0_S2_CLK_SRC 91 +#define GCC_QUPV3_WRAP0_S3_CLK 92 +#define GCC_QUPV3_WRAP0_S3_CLK_SRC 93 +#define GCC_QUPV3_WRAP0_S4_CLK 94 +#define GCC_QUPV3_WRAP0_S4_CLK_SRC 95 +#define GCC_QUPV3_WRAP0_S5_CLK 96 +#define GCC_QUPV3_WRAP0_S5_CLK_SRC 97 +#define GCC_QUPV3_WRAP0_S6_CLK 98 +#define GCC_QUPV3_WRAP0_S6_CLK_SRC 99 +#define GCC_QUPV3_WRAP0_S7_CLK 100 +#define GCC_QUPV3_WRAP0_S7_CLK_SRC 101 +#define GCC_QUPV3_WRAP1_CORE_2X_CLK 102 +#define GCC_QUPV3_WRAP1_CORE_CLK 103 +#define GCC_QUPV3_WRAP1_S0_CLK 104 +#define GCC_QUPV3_WRAP1_S0_CLK_SRC 105 +#define GCC_QUPV3_WRAP1_S1_CLK 106 +#define GCC_QUPV3_WRAP1_S1_CLK_SRC 107 +#define GCC_QUPV3_WRAP1_S2_CLK 108 +#define GCC_QUPV3_WRAP1_S2_CLK_SRC 109 +#define GCC_QUPV3_WRAP1_S3_CLK 110 +#define GCC_QUPV3_WRAP1_S3_CLK_SRC 111 +#define GCC_QUPV3_WRAP1_S4_CLK 112 +#define GCC_QUPV3_WRAP1_S4_CLK_SRC 113 +#define GCC_QUPV3_WRAP1_S5_CLK 114 +#define GCC_QUPV3_WRAP1_S5_CLK_SRC 115 +#define GCC_QUPV3_WRAP1_S6_CLK 116 +#define GCC_QUPV3_WRAP1_S6_CLK_SRC 117 +#define GCC_QUPV3_WRAP2_CORE_2X_CLK 118 +#define GCC_QUPV3_WRAP2_CORE_CLK 119 +#define GCC_QUPV3_WRAP2_S0_CLK 120 +#define GCC_QUPV3_WRAP2_S0_CLK_SRC 121 +#define GCC_QUPV3_WRAP2_S1_CLK 122 +#define GCC_QUPV3_WRAP2_S1_CLK_SRC 123 +#define GCC_QUPV3_WRAP2_S2_CLK 124 +#define GCC_QUPV3_WRAP2_S2_CLK_SRC 125 +#define GCC_QUPV3_WRAP2_S3_CLK 126 +#define GCC_QUPV3_WRAP2_S3_CLK_SRC 127 +#define GCC_QUPV3_WRAP2_S4_CLK 128 +#define GCC_QUPV3_WRAP2_S4_CLK_SRC 129 +#define GCC_QUPV3_WRAP2_S5_CLK 130 +#define GCC_QUPV3_WRAP2_S5_CLK_SRC 131 +#define GCC_QUPV3_WRAP2_S6_CLK 132 +#define GCC_QUPV3_WRAP2_S6_CLK_SRC 133 +#define GCC_QUPV3_WRAP_0_M_AHB_CLK 134 +#define GCC_QUPV3_WRAP_0_S_AHB_CLK 135 +#define GCC_QUPV3_WRAP_1_M_AHB_CLK 136 +#define GCC_QUPV3_WRAP_1_S_AHB_CLK 137 +#define GCC_QUPV3_WRAP_2_M_AHB_CLK 138 +#define GCC_QUPV3_WRAP_2_S_AHB_CLK 139 +#define GCC_SDCC2_AHB_CLK 140 +#define GCC_SDCC2_APPS_CLK 141 +#define GCC_SDCC2_APPS_CLK_SRC 142 +#define GCC_SDCC2_AT_CLK 143 +#define GCC_SDCC4_AHB_CLK 144 +#define GCC_SDCC4_APPS_CLK 145 +#define GCC_SDCC4_APPS_CLK_SRC 146 +#define GCC_SDCC4_AT_CLK 147 +#define GCC_SYS_NOC_CPUSS_AHB_CLK 148 +#define GCC_UFS_0_CLKREF_EN 149 +#define GCC_UFS_PHY_AHB_CLK 150 +#define GCC_UFS_PHY_AXI_CLK 151 +#define GCC_UFS_PHY_AXI_CLK_SRC 152 +#define GCC_UFS_PHY_AXI_HW_CTL_CLK 153 +#define GCC_UFS_PHY_ICE_CORE_CLK 154 +#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 155 +#define GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK 156 +#define GCC_UFS_PHY_PHY_AUX_CLK 157 +#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 158 +#define GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK 159 +#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 160 +#define GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC 161 +#define GCC_UFS_PHY_RX_SYMBOL_1_CLK 162 +#define GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC 163 +#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 164 +#define GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC 165 +#define GCC_UFS_PHY_UNIPRO_CORE_CLK 166 +#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 167 +#define GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK 168 +#define GCC_USB30_PRIM_MASTER_CLK 169 +#define GCC_USB30_PRIM_MASTER_CLK_SRC 170 +#define GCC_USB30_PRIM_MOCK_UTMI_CLK 171 +#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 172 +#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC 173 +#define GCC_USB30_PRIM_SLEEP_CLK 174 +#define GCC_USB3_0_CLKREF_EN 175 +#define GCC_USB3_PRIM_PHY_AUX_CLK 176 +#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 177 +#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 178 +#define GCC_USB3_PRIM_PHY_PIPE_CLK 179 +#define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC 180 +#define GCC_VIDEO_AHB_CLK 181 +#define GCC_VIDEO_AXI0_CLK 182 +#define GCC_VIDEO_AXI1_CLK 183 +#define GCC_VIDEO_XO_CLK 184 + +/* GCC resets */ +#define GCC_CAMERA_BCR 0 +#define GCC_DISPLAY_BCR 1 +#define GCC_GPU_BCR 2 +#define GCC_MMSS_BCR 3 +#define GCC_PCIE_0_BCR 4 +#define GCC_PCIE_0_LINK_DOWN_BCR 5 +#define GCC_PCIE_0_NOCSR_COM_PHY_BCR 6 +#define GCC_PCIE_0_PHY_BCR 7 +#define GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR 8 +#define GCC_PCIE_1_BCR 9 +#define GCC_PCIE_1_LINK_DOWN_BCR 10 +#define GCC_PCIE_1_NOCSR_COM_PHY_BCR 11 +#define GCC_PCIE_1_PHY_BCR 12 +#define GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR 13 +#define GCC_PCIE_PHY_BCR 14 +#define GCC_PCIE_PHY_CFG_AHB_BCR 15 +#define GCC_PCIE_PHY_COM_BCR 16 +#define GCC_PDM_BCR 17 +#define GCC_QUPV3_WRAPPER_0_BCR 18 +#define GCC_QUPV3_WRAPPER_1_BCR 19 +#define GCC_QUPV3_WRAPPER_2_BCR 20 +#define GCC_QUSB2PHY_PRIM_BCR 21 +#define GCC_QUSB2PHY_SEC_BCR 22 +#define GCC_SDCC2_BCR 23 +#define GCC_SDCC4_BCR 24 +#define GCC_UFS_PHY_BCR 25 +#define GCC_USB30_PRIM_BCR 26 +#define GCC_USB3_DP_PHY_PRIM_BCR 27 +#define GCC_USB3_DP_PHY_SEC_BCR 28 +#define GCC_USB3_PHY_PRIM_BCR 29 +#define GCC_USB3_PHY_SEC_BCR 30 +#define GCC_USB3PHY_PHY_PRIM_BCR 31 +#define GCC_USB3PHY_PHY_SEC_BCR 32 +#define GCC_USB_PHY_CFG_AHB2PHY_BCR 33 +#define GCC_VIDEO_AXI0_CLK_ARES 34 +#define GCC_VIDEO_AXI1_CLK_ARES 35 +#define GCC_VIDEO_BCR 36 + +/* GCC power domains */ +#define PCIE_0_GDSC 0 +#define PCIE_1_GDSC 1 +#define UFS_PHY_GDSC 2 +#define USB30_PRIM_GDSC 3 + +#endif -- cgit v1.2.3-59-g8ed1b From d56a8e9c7af835a4f3f88b2ae34f4ba6f7085b7c Mon Sep 17 00:00:00 2001 From: Sam Protsenko Date: Tue, 14 Dec 2021 19:09:24 +0200 Subject: dt-bindings: soc: samsung: Fix I2C clocks order in USI binding example Now that HSI2C binding [1] is converted to dt-schema format, it reveals incorrect HSI2C clocks order in USI binding example: .../exynos-usi.example.dt.yaml: i2c@13820000: clock-names:0: 'hsi2c' was expected From schema: .../i2c-exynos5.yaml .../exynos-usi.example.dt.yaml: i2c@13820000: clock-names:1: 'hsi2c_pclk' was expected From schema: .../i2c-exynos5.yaml Change HSI2C clock order in USI binding example to satisfy HSI2C binding requirements and fix above warnings. [1] Documentation/devicetree/bindings/i2c/i2c-exynos5.yaml Signed-off-by: Sam Protsenko Link: https://lore.kernel.org/r/20211214170924.27998-1-semen.protsenko@linaro.org Signed-off-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/soc/samsung/exynos-usi.yaml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/soc/samsung/exynos-usi.yaml b/Documentation/devicetree/bindings/soc/samsung/exynos-usi.yaml index 0af4821fae5e..273f2d95a043 100644 --- a/Documentation/devicetree/bindings/soc/samsung/exynos-usi.yaml +++ b/Documentation/devicetree/bindings/soc/samsung/exynos-usi.yaml @@ -152,8 +152,8 @@ examples: interrupts = ; #address-cells = <1>; #size-cells = <0>; - clocks = <&cmu_peri 32>, <&cmu_peri 31>; - clock-names = "hsi2c_pclk", "hsi2c"; + clocks = <&cmu_peri 31>, <&cmu_peri 32>; + clock-names = "hsi2c", "hsi2c_pclk"; status = "disabled"; }; }; -- cgit v1.2.3-59-g8ed1b From 301f651614c3396d711a8cc3f92f6fb95b12f5c5 Mon Sep 17 00:00:00 2001 From: Hector Martin Date: Thu, 9 Dec 2021 13:50:42 +0900 Subject: dt-bindings: mailbox: apple,mailbox: Add power-domains property This will bind to the PMGR pwrstate nodes that control power/clock gating to SoC blocks. The mailbox driver doesn't do runtime-pm yet, so initially this will just keep the domain on permanently. Reviewed-by: Sven Peter Acked-by: Rob Herring Signed-off-by: Hector Martin --- Documentation/devicetree/bindings/mailbox/apple,mailbox.yaml | 3 +++ 1 file changed, 3 insertions(+) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/mailbox/apple,mailbox.yaml b/Documentation/devicetree/bindings/mailbox/apple,mailbox.yaml index 2c1704b34e7a..c4255f42e801 100644 --- a/Documentation/devicetree/bindings/mailbox/apple,mailbox.yaml +++ b/Documentation/devicetree/bindings/mailbox/apple,mailbox.yaml @@ -56,6 +56,9 @@ properties: "#mbox-cells": const: 0 + power-domains: + maxItems: 1 + required: - compatible - reg -- cgit v1.2.3-59-g8ed1b From c96ebc5fde274edcc02543dcfb6a1ee097f98070 Mon Sep 17 00:00:00 2001 From: David Virag Date: Mon, 6 Dec 2021 16:31:17 +0100 Subject: dt-bindings: arm: samsung: document jackpotlte board binding Add binding for the jackpotlte board (Samsung Galaxy A8 (2018)). Signed-off-by: David Virag Reviewed-by: Rob Herring Reviewed-by: Sam Protsenko Link: https://lore.kernel.org/r/20211206153124.427102-4-virag.david003@gmail.com Signed-off-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml index ef6dc14be4b5..d88571202713 100644 --- a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml +++ b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml @@ -199,6 +199,12 @@ properties: - samsung,exynos7-espresso # Samsung Exynos7 Espresso - const: samsung,exynos7 + - description: Exynos7885 based boards + items: + - enum: + - samsung,jackpotlte # Samsung Galaxy A8 (2018) + - const: samsung,exynos7885 + - description: Exynos Auto v9 based boards items: - enum: -- cgit v1.2.3-59-g8ed1b From 19ebf10e8d837c0a296274b571a681b0c2885e4e Mon Sep 17 00:00:00 2001 From: Sam Shih Date: Mon, 22 Nov 2021 20:32:21 +0800 Subject: dt-bindings: arm64: dts: mediatek: Add mt7986 series MT7986 series is Mediatek's new 4-core SoC, which is mainly for wifi-router application. The difference between mt7986a and mt7986b is that some pins do not exist on mt7986b. Signed-off-by: Sam Shih Acked-by: Rob Herring Link: https://lore.kernel.org/r/20211122123222.8016-2-sam.shih@mediatek.com Signed-off-by: Matthias Brugger --- Documentation/devicetree/bindings/arm/mediatek.yaml | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/arm/mediatek.yaml b/Documentation/devicetree/bindings/arm/mediatek.yaml index 723810cffce2..0ffe1acf1344 100644 --- a/Documentation/devicetree/bindings/arm/mediatek.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek.yaml @@ -77,6 +77,14 @@ properties: - enum: - mediatek,mt7629-rfb - const: mediatek,mt7629 + - items: + - enum: + - mediatek,mt7986a-rfb + - const: mediatek,mt7986a + - items: + - enum: + - mediatek,mt7986b-rfb + - const: mediatek,mt7986b - items: - enum: - mediatek,mt8127-moose -- cgit v1.2.3-59-g8ed1b From 8c970e7ee7ae9c41aa2432f234c7b382391200f2 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Mon, 13 Dec 2021 17:21:46 +0100 Subject: dt-bindings: memory: tegra: Update for Tegra194 The #interconnect-cells properties are required to hook up memory clients to the MC/EMC in interconnects properties. Add a description for these properties. For the nested EMC controller, the list of required properties was missing. Add it so that the validation can be more strict. Also, allow multiple reg entries required by Tegra194 and later. While at it, also remove the dummy BPMP node from the example because it is incomplete and fails validation. It's also not necessary for this file and the BPMP DT schema already has a full example. Signed-off-by: Thierry Reding Reviewed-by: Krzysztof Kozlowski Reviewed-by: Rob Herring Signed-off-by: Thierry Reding --- .../memory-controllers/nvidia,tegra186-mc.yaml | 78 +++++++++++++++++++--- 1 file changed, 67 insertions(+), 11 deletions(-) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml index 611bda38d187..b496564b1bdf 100644 --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml @@ -33,10 +33,12 @@ properties: - nvidia,tegra194-mc reg: - maxItems: 1 + minItems: 1 + maxItems: 3 interrupts: - maxItems: 1 + items: + - description: MC general interrupt "#address-cells": const: 2 @@ -48,6 +50,9 @@ properties: dma-ranges: true + "#interconnect-cells": + const: 1 + patternProperties: "^external-memory-controller@[0-9a-f]+$": description: @@ -65,10 +70,12 @@ patternProperties: - nvidia,tegra194-emc reg: - maxItems: 1 + minItems: 1 + maxItems: 2 interrupts: - maxItems: 1 + items: + - description: EMC general interrupt clocks: items: @@ -78,11 +85,65 @@ patternProperties: items: - const: emc + "#interconnect-cells": + const: 0 + nvidia,bpmp: $ref: /schemas/types.yaml#/definitions/phandle description: phandle of the node representing the BPMP + allOf: + - if: + properties: + compatible: + const: nvidia,tegra186-emc + then: + properties: + reg: + maxItems: 1 + + - if: + properties: + compatible: + const: nvidia,tegra194-emc + then: + properties: + reg: + minItems: 2 + + additionalProperties: false + + required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - "#interconnect-cells" + - nvidia,bpmp + +allOf: + - if: + properties: + compatible: + const: nvidia,tegra186-mc + then: + properties: + reg: + maxItems: 1 + + - if: + properties: + compatible: + const: nvidia,tegra194-mc + then: + properties: + reg: + minItems: 3 + +additionalProperties: false + required: - compatible - reg @@ -90,8 +151,6 @@ required: - "#address-cells" - "#size-cells" -additionalProperties: false - examples: - | #include @@ -124,12 +183,9 @@ examples: clocks = <&bpmp TEGRA186_CLK_EMC>; clock-names = "emc"; + #interconnect-cells = <0>; + nvidia,bpmp = <&bpmp>; }; }; }; - - bpmp: bpmp { - compatible = "nvidia,tegra186-bpmp"; - #clock-cells = <1>; - }; -- cgit v1.2.3-59-g8ed1b From c3859c1436e31461f27365ec6fc751c9bbeff3e2 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Mon, 13 Dec 2021 17:21:47 +0100 Subject: dt-bindings: memory: tegra: Add Tegra234 support Document the variant of the memory controller and external memory controllers found on Tegra234 and add some memory client and SMMU stream ID definitions for use in device tree files. Reviewed-by: Rob Herring Signed-off-by: Thierry Reding Reviewed-by: Krzysztof Kozlowski Signed-off-by: Thierry Reding --- .../memory-controllers/nvidia,tegra186-mc.yaml | 20 ++++++++++++++ include/dt-bindings/clock/tegra234-clock.h | 9 ++++++ include/dt-bindings/memory/tegra234-mc.h | 32 ++++++++++++++++++++++ 3 files changed, 61 insertions(+) create mode 100644 include/dt-bindings/memory/tegra234-mc.h (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml index b496564b1bdf..13c4c82fd0d3 100644 --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml @@ -31,6 +31,7 @@ properties: - enum: - nvidia,tegra186-mc - nvidia,tegra194-mc + - nvidia,tegra234-mc reg: minItems: 1 @@ -68,6 +69,7 @@ patternProperties: - enum: - nvidia,tegra186-emc - nvidia,tegra194-emc + - nvidia,tegra234-emc reg: minItems: 1 @@ -112,6 +114,15 @@ patternProperties: reg: minItems: 2 + - if: + properties: + compatible: + const: nvidia,tegra234-emc + then: + properties: + reg: + minItems: 2 + additionalProperties: false required: @@ -142,6 +153,15 @@ allOf: reg: minItems: 3 + - if: + properties: + compatible: + const: nvidia,tegra234-mc + then: + properties: + reg: + minItems: 3 + additionalProperties: false required: diff --git a/include/dt-bindings/clock/tegra234-clock.h b/include/dt-bindings/clock/tegra234-clock.h index 21ed0c732fb9..8d7e66e1b6ef 100644 --- a/include/dt-bindings/clock/tegra234-clock.h +++ b/include/dt-bindings/clock/tegra234-clock.h @@ -9,6 +9,15 @@ * @defgroup bpmp_clock_ids Clock ID's * @{ */ +/** + * @brief controls the EMC clock frequency. + * @details Doing a clk_set_rate on this clock will select the + * appropriate clock source, program the source rate and execute a + * specific sequence to switch to the new clock source for both memory + * controllers. This can be used to control the balance between memory + * throughput and memory controller power. + */ +#define TEGRA234_CLK_EMC 31U /** @brief output of gate CLK_ENB_FUSE */ #define TEGRA234_CLK_FUSE 40U /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4 */ diff --git a/include/dt-bindings/memory/tegra234-mc.h b/include/dt-bindings/memory/tegra234-mc.h new file mode 100644 index 000000000000..2662f70c15c6 --- /dev/null +++ b/include/dt-bindings/memory/tegra234-mc.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ + +#ifndef DT_BINDINGS_MEMORY_TEGRA234_MC_H +#define DT_BINDINGS_MEMORY_TEGRA234_MC_H + +/* special clients */ +#define TEGRA234_SID_INVALID 0x00 +#define TEGRA234_SID_PASSTHROUGH 0x7f + + +/* NISO1 stream IDs */ +#define TEGRA234_SID_SDMMC4 0x02 +#define TEGRA234_SID_BPMP 0x10 + +/* + * memory client IDs + */ + +/* sdmmcd memory read client */ +#define TEGRA234_MEMORY_CLIENT_SDMMCRAB 0x63 +/* sdmmcd memory write client */ +#define TEGRA234_MEMORY_CLIENT_SDMMCWAB 0x67 +/* BPMP read client */ +#define TEGRA234_MEMORY_CLIENT_BPMPR 0x93 +/* BPMP write client */ +#define TEGRA234_MEMORY_CLIENT_BPMPW 0x94 +/* BPMPDMA read client */ +#define TEGRA234_MEMORY_CLIENT_BPMPDMAR 0x95 +/* BPMPDMA write client */ +#define TEGRA234_MEMORY_CLIENT_BPMPDMAW 0x96 + +#endif -- cgit v1.2.3-59-g8ed1b From d875175d87268cbd6fa8a6ccfaeba6d9991527f0 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 12 Nov 2021 13:35:32 +0100 Subject: dt-bindings: tegra: Describe recent developer kits consistently Add descriptions to entries that were missing one and don't try to combine multiple entries into one to avoid confusion. Reviewed-by: Rob Herring Signed-off-by: Thierry Reding --- Documentation/devicetree/bindings/arm/tegra.yaml | 20 +++++++++++--------- 1 file changed, 11 insertions(+), 9 deletions(-) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/arm/tegra.yaml b/Documentation/devicetree/bindings/arm/tegra.yaml index d79d36ac0c44..0235b510e0b0 100644 --- a/Documentation/devicetree/bindings/arm/tegra.yaml +++ b/Documentation/devicetree/bindings/arm/tegra.yaml @@ -108,14 +108,17 @@ properties: - nvidia,p2571 - nvidia,p2894-0050-a08 - const: nvidia,tegra210 - - items: - - enum: - - nvidia,p2771-0000 - - nvidia,p3509-0000+p3636-0001 + - description: Jetson TX2 Developer Kit + items: + - const: nvidia,p2771-0000 - const: nvidia,tegra186 - - items: - - enum: - - nvidia,p2972-0000 + - description: Jetson TX2 NX Developer Kit + items: + - const: nvidia,p3509-0000+p3636-0001 + - const: nvidia,tegra186 + - description: Jetson AGX Xavier Developer Kit + items: + - const: nvidia,p2972-0000 - const: nvidia,tegra194 - description: Jetson Xavier NX items: @@ -134,8 +137,7 @@ properties: - const: nvidia,p3509-0000+p3668-0001 - const: nvidia,tegra194 - items: - - enum: - - nvidia,tegra234-vdk + - const: nvidia,tegra234-vdk - const: nvidia,tegra234 additionalProperties: true -- cgit v1.2.3-59-g8ed1b From b39cc79565771f7e9ffd262d3b735cbe1c718f66 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 12 Nov 2021 13:35:33 +0100 Subject: dt-bindings: tegra: Document Jetson AGX Orin (and devkit) Add the compatible strings for the Jetson AGX Orin and the corresponding developer kit. Reviewed-by: Rob Herring Signed-off-by: Thierry Reding --- Documentation/devicetree/bindings/arm/tegra.yaml | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/arm/tegra.yaml b/Documentation/devicetree/bindings/arm/tegra.yaml index 0235b510e0b0..3bd0920da274 100644 --- a/Documentation/devicetree/bindings/arm/tegra.yaml +++ b/Documentation/devicetree/bindings/arm/tegra.yaml @@ -139,5 +139,14 @@ properties: - items: - const: nvidia,tegra234-vdk - const: nvidia,tegra234 + - description: Jetson AGX Orin + items: + - const: nvidia,p3701-0000 + - const: nvidia,tegra234 + - description: Jetson AGX Orin Developer Kit + items: + - const: nvidia,p3737-0000+p3701-0000 + - const: nvidia,p3701-0000 + - const: nvidia,tegra234 additionalProperties: true -- cgit v1.2.3-59-g8ed1b From d9203d081a618fc8b3469b24f959495eaa138890 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 12 Nov 2021 13:35:35 +0100 Subject: dt-bindings: sram: Document NVIDIA Tegra SYSRAM Tegra SoCs have extra on-chip RAM that can be used for inter-processor communication. Tegra186 and later make use of it to establish a two-way channel between the CCPLEX and BPMP. Add missing compatible strings for Tegra186 and Tegra194 as well as a new compatible string for Tegra234. Reviewed-by: Rob Herring Signed-off-by: Thierry Reding --- Documentation/devicetree/bindings/sram/sram.yaml | 3 +++ 1 file changed, 3 insertions(+) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/sram/sram.yaml b/Documentation/devicetree/bindings/sram/sram.yaml index d4e418b6a1c1..668a9a41a775 100644 --- a/Documentation/devicetree/bindings/sram/sram.yaml +++ b/Documentation/devicetree/bindings/sram/sram.yaml @@ -31,6 +31,9 @@ properties: - amlogic,meson-gxbb-sram - arm,juno-sram-ns - atmel,sama5d2-securam + - nvidia,tegra186-sysram + - nvidia,tegra194-sysram + - nvidia,tegra234-sysram - qcom,rpm-msg-ram - rockchip,rk3288-pmu-sram -- cgit v1.2.3-59-g8ed1b From 57978838889d74ad3139cdf76ca2622e625f41e6 Mon Sep 17 00:00:00 2001 From: Jon Hunter Date: Wed, 17 Nov 2021 09:56:07 +0000 Subject: dt-bindings: Add YAML bindings for NVENC and NVJPG Add YAML device tree bindings for the Tegra NVENC and NVJPG Host1x engines. Signed-off-by: Jon Hunter Reviewed-by: Rob Herring Signed-off-by: Thierry Reding --- .../bindings/gpu/host1x/nvidia,tegra210-nvenc.yaml | 135 +++++++++++++++++++++ .../bindings/gpu/host1x/nvidia,tegra210-nvjpg.yaml | 94 ++++++++++++++ 2 files changed, 229 insertions(+) create mode 100644 Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra210-nvenc.yaml create mode 100644 Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra210-nvjpg.yaml (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra210-nvenc.yaml b/Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra210-nvenc.yaml new file mode 100644 index 000000000000..e63ae1a00818 --- /dev/null +++ b/Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra210-nvenc.yaml @@ -0,0 +1,135 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/gpu/host1x/nvidia,tegra210-nvenc.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Device tree binding for NVIDIA Tegra NVENC + +description: | + NVENC is the hardware video encoder present on NVIDIA Tegra210 + and newer chips. It is located on the Host1x bus and typically + programmed through Host1x channels. + +maintainers: + - Thierry Reding + - Mikko Perttunen + +properties: + $nodename: + pattern: "^nvenc@[0-9a-f]*$" + + compatible: + enum: + - nvidia,tegra210-nvenc + - nvidia,tegra186-nvenc + - nvidia,tegra194-nvenc + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: nvenc + + resets: + maxItems: 1 + + reset-names: + items: + - const: nvenc + + power-domains: + maxItems: 1 + + iommus: + maxItems: 1 + + dma-coherent: true + + interconnects: + minItems: 2 + maxItems: 3 + + interconnect-names: + minItems: 2 + maxItems: 3 + + nvidia,host1x-class: + description: | + Host1x class of the engine, used to specify the targeted engine + when programming the engine through Host1x channels or when + configuring engine-specific behavior in Host1x. + default: 0x21 + $ref: /schemas/types.yaml#/definitions/uint32 + +required: + - compatible + - reg + - clocks + - clock-names + - resets + - reset-names + - power-domains + +allOf: + - if: + properties: + compatible: + enum: + - nvidia,tegra210-nvenc + - nvidia,tegra186-nvenc + then: + properties: + interconnects: + items: + - description: DMA read memory client + - description: DMA write memory client + interconnect-names: + items: + - const: dma-mem + - const: write + - if: + properties: + compatible: + enum: + - nvidia,tegra194-nvenc + then: + properties: + interconnects: + items: + - description: DMA read memory client + - description: DMA read 2 memory client + - description: DMA write memory client + interconnect-names: + items: + - const: dma-mem + - const: read-1 + - const: write + +additionalProperties: false + +examples: + - | + #include + #include + #include + #include + + nvenc@154c0000 { + compatible = "nvidia,tegra186-nvenc"; + reg = <0x154c0000 0x40000>; + clocks = <&bpmp TEGRA186_CLK_NVENC>; + clock-names = "nvenc"; + resets = <&bpmp TEGRA186_RESET_NVENC>; + reset-names = "nvenc"; + + power-domains = <&bpmp TEGRA186_POWER_DOMAIN_MPE>; + interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVENCSRD &emc>, + <&mc TEGRA186_MEMORY_CLIENT_NVENCSWR &emc>; + interconnect-names = "dma-mem", "write"; + iommus = <&smmu TEGRA186_SID_NVENC>; + }; diff --git a/Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra210-nvjpg.yaml b/Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra210-nvjpg.yaml new file mode 100644 index 000000000000..8647404d67e4 --- /dev/null +++ b/Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra210-nvjpg.yaml @@ -0,0 +1,94 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/gpu/host1x/nvidia,tegra210-nvjpg.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Device tree binding for NVIDIA Tegra NVJPG + +description: | + NVJPG is the hardware JPEG decoder and encoder present on NVIDIA Tegra210 + and newer chips. It is located on the Host1x bus and typically programmed + through Host1x channels. + +maintainers: + - Thierry Reding + - Mikko Perttunen + +properties: + $nodename: + pattern: "^nvjpg@[0-9a-f]*$" + + compatible: + enum: + - nvidia,tegra210-nvjpg + - nvidia,tegra186-nvjpg + - nvidia,tegra194-nvjpg + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: nvjpg + + resets: + maxItems: 1 + + reset-names: + items: + - const: nvjpg + + power-domains: + maxItems: 1 + + iommus: + maxItems: 1 + + dma-coherent: true + + interconnects: + items: + - description: DMA read memory client + - description: DMA write memory client + + interconnect-names: + items: + - const: dma-mem + - const: write + +required: + - compatible + - reg + - clocks + - clock-names + - resets + - reset-names + - power-domains + +additionalProperties: false + +examples: + - | + #include + #include + #include + #include + + nvjpg@15380000 { + compatible = "nvidia,tegra186-nvjpg"; + reg = <0x15380000 0x40000>; + clocks = <&bpmp TEGRA186_CLK_NVJPG>; + clock-names = "nvjpg"; + resets = <&bpmp TEGRA186_RESET_NVJPG>; + reset-names = "nvjpg"; + + power-domains = <&bpmp TEGRA186_POWER_DOMAIN_NVJPG>; + interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVJPGSRD &emc>, + <&mc TEGRA186_MEMORY_CLIENT_NVJPGSWR &emc>; + interconnect-names = "dma-mem", "write"; + iommus = <&smmu TEGRA186_SID_NVJPG>; + }; -- cgit v1.2.3-59-g8ed1b From 51a0f370886a76b4b7bd39ca9bf917a571068aac Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 19 Nov 2021 15:38:24 +0100 Subject: dt-bindings: misc: Convert Tegra MISC to json-schema Convert the device tree bindings for the MISC register block found on NVIDIA Tegra SoCs from plain text to json-schema format. Reviewed-by: Rob Herring Signed-off-by: Thierry Reding --- .../bindings/misc/nvidia,tegra186-misc.txt | 14 ------ .../bindings/misc/nvidia,tegra186-misc.yaml | 43 ++++++++++++++++++ .../bindings/misc/nvidia,tegra20-apbmisc.txt | 17 -------- .../bindings/misc/nvidia,tegra20-apbmisc.yaml | 51 ++++++++++++++++++++++ 4 files changed, 94 insertions(+), 31 deletions(-) delete mode 100644 Documentation/devicetree/bindings/misc/nvidia,tegra186-misc.txt create mode 100644 Documentation/devicetree/bindings/misc/nvidia,tegra186-misc.yaml delete mode 100644 Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.txt create mode 100644 Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.yaml (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/misc/nvidia,tegra186-misc.txt b/Documentation/devicetree/bindings/misc/nvidia,tegra186-misc.txt deleted file mode 100644 index 43d777ed8316..000000000000 --- a/Documentation/devicetree/bindings/misc/nvidia,tegra186-misc.txt +++ /dev/null @@ -1,14 +0,0 @@ -NVIDIA Tegra186 (and later) MISC register block - -The MISC register block found on Tegra186 and later SoCs contains registers -that can be used to identify a given chip and various strapping options. - -Required properties: -- compatible: Must be: - - Tegra186: "nvidia,tegra186-misc" - - Tegra194: "nvidia,tegra194-misc" - - Tegra234: "nvidia,tegra234-misc" -- reg: Should contain 2 entries: The first entry gives the physical address - and length of the register region which contains revision and debug - features. The second entry specifies the physical address and length - of the register region indicating the strapping options. diff --git a/Documentation/devicetree/bindings/misc/nvidia,tegra186-misc.yaml b/Documentation/devicetree/bindings/misc/nvidia,tegra186-misc.yaml new file mode 100644 index 000000000000..cacb845868f4 --- /dev/null +++ b/Documentation/devicetree/bindings/misc/nvidia,tegra186-misc.yaml @@ -0,0 +1,43 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/misc/nvidia,tegra186-misc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra186 (and later) MISC register block + +maintainers: + - Thierry Reding + - Jon Hunter + +description: The MISC register block found on Tegra186 and later SoCs contains + registers that can be used to identify a given chip and various strapping + options. + +properties: + compatible: + enum: + - nvidia,tegra186-misc + - nvidia,tegra194-misc + - nvidia,tegra234-misc + + reg: + items: + - description: physical address and length of the registers which + contain revision and debug features + - description: physical address and length of the registers which + indicate strapping options + +additionalProperties: false + +required: + - compatible + - reg + +examples: + - | + misc@100000 { + compatible = "nvidia,tegra186-misc"; + reg = <0x00100000 0xf000>, + <0x0010f000 0x1000>; + }; diff --git a/Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.txt b/Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.txt deleted file mode 100644 index 83f6a251ba3e..000000000000 --- a/Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.txt +++ /dev/null @@ -1,17 +0,0 @@ -NVIDIA Tegra APBMISC block - -Required properties: -- compatible: Must be: - - Tegra20: "nvidia,tegra20-apbmisc" - - Tegra30: "nvidia,tegra30-apbmisc", "nvidia,tegra20-apbmisc" - - Tegra114: "nvidia,tegra114-apbmisc", "nvidia,tegra20-apbmisc" - - Tegra124: "nvidia,tegra124-apbmisc", "nvidia,tegra20-apbmisc" - - Tegra132: "nvidia,tegra124-apbmisc", "nvidia,tegra20-apbmisc" - - Tegra210: "nvidia,tegra210-apbmisc", "nvidia,tegra20-apbmisc" -- reg: Should contain 2 entries: the first entry gives the physical address - and length of the registers which contain revision and debug features. - The second entry gives the physical address and length of the - registers indicating the strapping options. - -Optional properties: -- nvidia,long-ram-code: If present, the RAM code is long (4 bit). If not, short (2 bit). diff --git a/Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.yaml b/Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.yaml new file mode 100644 index 000000000000..6f504fa74007 --- /dev/null +++ b/Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.yaml @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/misc/nvidia,tegra20-apbmisc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra APBMISC block + +maintainers: + - Thierry Reding + - Jon Hunter + +properties: + compatible: + oneOf: + - items: + - enum: + - nvidia,tegra210-apbmisc + - nvidia,tegra124-apbmisc + - nvidia,tegra114-apbmisc + - nvidia,tegra30-apbmisc + - const: nvidia,tegra20-apbmisc + + - items: + - const: nvidia,tegra20-apbmisc + + reg: + items: + - description: physical address and length of the registers which + contain revision and debug features + - description: physical address and length of the registers which + indicate strapping options + + nvidia,long-ram-code: + description: If present, the RAM code is long (4 bit). If not, short + (2 bit). + type: boolean + +additionalProperties: false + +required: + - compatible + - reg + +examples: + - | + apbmisc@70000800 { + compatible = "nvidia,tegra20-apbmisc"; + reg = <0x70000800 0x64>, /* Chip revision */ + <0x70000008 0x04>; /* Strapping options */ + }; -- cgit v1.2.3-59-g8ed1b From e1e06edd94d5b3171401a1435a17251102cc8494 Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Tue, 14 Dec 2021 18:46:21 -0600 Subject: dt-bindings: soc: add binding for i.MX8MN DISP blk-ctrl Add the DT binding for the i.MX8MN DISP blk-ctrl. Signed-off-by: Adam Ford Reviewed-by: Rob Herring Reviewed-by: Lucas Stach Signed-off-by: Shawn Guo --- .../bindings/soc/imx/fsl,imx8mn-disp-blk-ctrl.yaml | 97 ++++++++++++++++++++++ 1 file changed, 97 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/imx/fsl,imx8mn-disp-blk-ctrl.yaml (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/soc/imx/fsl,imx8mn-disp-blk-ctrl.yaml b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mn-disp-blk-ctrl.yaml new file mode 100644 index 000000000000..fbeaac399c50 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mn-disp-blk-ctrl.yaml @@ -0,0 +1,97 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/imx/fsl,imx8mn-disp-blk-ctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP i.MX8MN DISP blk-ctrl + +maintainers: + - Lucas Stach + +description: + The i.MX8MN DISP blk-ctrl is a top-level peripheral providing access to + the NoC and ensuring proper power sequencing of the display and MIPI CSI + peripherals located in the DISP domain of the SoC. + +properties: + compatible: + items: + - const: fsl,imx8mn-disp-blk-ctrl + - const: syscon + + reg: + maxItems: 1 + + '#power-domain-cells': + const: 1 + + power-domains: + minItems: 5 + maxItems: 5 + + power-domain-names: + items: + - const: bus + - const: isi + - const: lcdif + - const: mipi-dsi + - const: mipi-csi + + clocks: + minItems: 11 + maxItems: 11 + + clock-names: + items: + - const: disp_axi + - const: disp_apb + - const: disp_axi_root + - const: disp_apb_root + - const: lcdif-axi + - const: lcdif-apb + - const: lcdif-pix + - const: dsi-pclk + - const: dsi-ref + - const: csi-aclk + - const: csi-pclk + +required: + - compatible + - reg + - power-domains + - power-domain-names + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include + #include + + disp_blk_ctl: blk_ctrl@32e28000 { + compatible = "fsl,imx8mn-disp-blk-ctrl", "syscon"; + reg = <0x32e28000 0x100>; + power-domains = <&pgc_dispmix>, <&pgc_dispmix>, + <&pgc_dispmix>, <&pgc_mipi>, + <&pgc_mipi>; + power-domain-names = "bus", "isi", "lcdif", "mipi-dsi", + "mipi-csi"; + clocks = <&clk IMX8MN_CLK_DISP_AXI>, + <&clk IMX8MN_CLK_DISP_APB>, + <&clk IMX8MN_CLK_DISP_AXI_ROOT>, + <&clk IMX8MN_CLK_DISP_APB_ROOT>, + <&clk IMX8MN_CLK_DISP_AXI_ROOT>, + <&clk IMX8MN_CLK_DISP_APB_ROOT>, + <&clk IMX8MN_CLK_DISP_PIXEL_ROOT>, + <&clk IMX8MN_CLK_DSI_CORE>, + <&clk IMX8MN_CLK_DSI_PHY_REF>, + <&clk IMX8MN_CLK_CSI1_PHY_REF>, + <&clk IMX8MN_CLK_CAMERA_PIXEL_ROOT>; + clock-names = "disp_axi", "disp_apb", "disp_axi_root", "disp_apb_root", + "lcdif-axi", "lcdif-apb", "lcdif-pix", "dsi-pclk", + "dsi-ref", "csi-aclk", "csi-pclk"; + #power-domain-cells = <1>; + }; -- cgit v1.2.3-59-g8ed1b From e109c0acb835f81ef228c78d7ae76bbcf9470e20 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 19 Nov 2021 15:38:25 +0100 Subject: dt-bindings: mmc: tegra: Convert to json-schema Convert the NVIDIA Tegra SDHCI bindings from the free-form text format to json-schema. Reviewed-by: Rob Herring Signed-off-by: Thierry Reding --- .../bindings/mmc/nvidia,tegra20-sdhci.txt | 143 ---------- .../bindings/mmc/nvidia,tegra20-sdhci.yaml | 311 +++++++++++++++++++++ 2 files changed, 311 insertions(+), 143 deletions(-) delete mode 100644 Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt create mode 100644 Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.yaml (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt deleted file mode 100644 index 96c0b1440c9c..000000000000 --- a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt +++ /dev/null @@ -1,143 +0,0 @@ -* NVIDIA Tegra Secure Digital Host Controller - -This controller on Tegra family SoCs provides an interface for MMC, SD, -and SDIO types of memory cards. - -This file documents differences between the core properties described -by mmc.txt and the properties used by the sdhci-tegra driver. - -Required properties: -- compatible : should be one of: - - "nvidia,tegra20-sdhci": for Tegra20 - - "nvidia,tegra30-sdhci": for Tegra30 - - "nvidia,tegra114-sdhci": for Tegra114 - - "nvidia,tegra124-sdhci": for Tegra124 and Tegra132 - - "nvidia,tegra210-sdhci": for Tegra210 - - "nvidia,tegra186-sdhci": for Tegra186 - - "nvidia,tegra194-sdhci": for Tegra194 -- clocks: For Tegra210, Tegra186 and Tegra194 must contain two entries. - One for the module clock and one for the timeout clock. - For all other Tegra devices, must contain a single entry for - the module clock. See ../clocks/clock-bindings.txt for details. -- clock-names: For Tegra210, Tegra186 and Tegra194 must contain the - strings 'sdhci' and 'tmclk' to represent the module and - the timeout clocks, respectively. - For all other Tegra devices must contain the string 'sdhci' - to represent the module clock. -- resets : Must contain an entry for each entry in reset-names. - See ../reset/reset.txt for details. -- reset-names : Must include the following entries: - - sdhci - -Optional properties: -- power-gpios : Specify GPIOs for power control - -Example: - -sdhci@c8000200 { - compatible = "nvidia,tegra20-sdhci"; - reg = <0xc8000200 0x200>; - interrupts = <47>; - clocks = <&tegra_car 14>; - resets = <&tegra_car 14>; - reset-names = "sdhci"; - cd-gpios = <&gpio 69 0>; /* gpio PI5 */ - wp-gpios = <&gpio 57 0>; /* gpio PH1 */ - power-gpios = <&gpio 155 0>; /* gpio PT3 */ - bus-width = <8>; -}; - -Optional properties for Tegra210, Tegra186 and Tegra194: -- pinctrl-names, pinctrl-0, pinctrl-1 : Specify pad voltage - configurations. Valid pinctrl-names are "sdmmc-3v3" and "sdmmc-1v8" - for controllers supporting multiple voltage levels. The order of names - should correspond to the pin configuration states in pinctrl-0 and - pinctrl-1. -- pinctrl-names : "sdmmc-3v3-drv" and "sdmmc-1v8-drv" are applicable for - Tegra210 where pad config registers are in the pinmux register domain - for pull-up-strength and pull-down-strength values configuration when - using pads at 3V3 and 1V8 levels. -- nvidia,only-1-8-v : The presence of this property indicates that the - controller operates at a 1.8 V fixed I/O voltage. -- nvidia,pad-autocal-pull-up-offset-3v3, - nvidia,pad-autocal-pull-down-offset-3v3 : Specify drive strength - calibration offsets for 3.3 V signaling modes. -- nvidia,pad-autocal-pull-up-offset-1v8, - nvidia,pad-autocal-pull-down-offset-1v8 : Specify drive strength - calibration offsets for 1.8 V signaling modes. -- nvidia,pad-autocal-pull-up-offset-3v3-timeout, - nvidia,pad-autocal-pull-down-offset-3v3-timeout : Specify drive - strength used as a fallback in case the automatic calibration times - out on a 3.3 V signaling mode. -- nvidia,pad-autocal-pull-up-offset-1v8-timeout, - nvidia,pad-autocal-pull-down-offset-1v8-timeout : Specify drive - strength used as a fallback in case the automatic calibration times - out on a 1.8 V signaling mode. -- nvidia,pad-autocal-pull-up-offset-sdr104, - nvidia,pad-autocal-pull-down-offset-sdr104 : Specify drive strength - calibration offsets for SDR104 mode. -- nvidia,pad-autocal-pull-up-offset-hs400, - nvidia,pad-autocal-pull-down-offset-hs400 : Specify drive strength - calibration offsets for HS400 mode. -- nvidia,default-tap : Specify the default inbound sampling clock - trimmer value for non-tunable modes. -- nvidia,default-trim : Specify the default outbound clock trimmer - value. -- nvidia,dqs-trim : Specify DQS trim value for HS400 timing - - Notes on the pad calibration pull up and pulldown offset values: - - The property values are drive codes which are programmed into the - PD_OFFSET and PU_OFFSET sections of the - SDHCI_TEGRA_AUTO_CAL_CONFIG register. - - A higher value corresponds to higher drive strength. Please refer - to the reference manual of the SoC for correct values. - - The SDR104 and HS400 timing specific values are used in - corresponding modes if specified. - - Notes on tap and trim values: - - The values are used for compensating trace length differences - by adjusting the sampling point. - - The values are programmed to the Vendor Clock Control Register. - Please refer to the reference manual of the SoC for correct - values. - - The DQS trim values are only used on controllers which support - HS400 timing. Only SDMMC4 on Tegra210 and Tegra 186 supports - HS400. - -Example: -sdhci@700b0000 { - compatible = "nvidia,tegra124-sdhci"; - reg = <0x0 0x700b0000 0x0 0x200>; - interrupts = ; - clocks = <&tegra_car TEGRA210_CLK_SDMMC1>; - clock-names = "sdhci"; - resets = <&tegra_car 14>; - reset-names = "sdhci"; - pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; - pinctrl-0 = <&sdmmc1_3v3>; - pinctrl-1 = <&sdmmc1_1v8>; - nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>; - nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>; - nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>; - nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>; - status = "disabled"; -}; - -sdhci@700b0000 { - compatible = "nvidia,tegra210-sdhci"; - reg = <0x0 0x700b0000 0x0 0x200>; - interrupts = ; - clocks = <&tegra_car TEGRA210_CLK_SDMMC1>, - <&tegra_car TEGRA210_CLK_SDMMC_LEGACY>; - clock-names = "sdhci", "tmclk"; - resets = <&tegra_car 14>; - reset-names = "sdhci"; - pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; - pinctrl-0 = <&sdmmc1_3v3>; - pinctrl-1 = <&sdmmc1_1v8>; - nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>; - nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>; - nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>; - nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>; - status = "disabled"; -}; diff --git a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.yaml b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.yaml new file mode 100644 index 000000000000..f7a9fcc6bbbd --- /dev/null +++ b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.yaml @@ -0,0 +1,311 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mmc/nvidia,tegra20-sdhci.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra Secure Digital Host Controller + +maintainers: + - Thierry Reding + - Jon Hunter + +description: | + This controller on Tegra family SoCs provides an interface for MMC, SD, and + SDIO types of memory cards. + + This file documents differences between the core properties described by + mmc-controller.yaml and the properties for the Tegra SDHCI controller. + +properties: + compatible: + oneOf: + - enum: + - nvidia,tegra20-sdhci + - nvidia,tegra30-sdhci + - nvidia,tegra114-sdhci + - nvidia,tegra124-sdhci + - nvidia,tegra210-sdhci + - nvidia,tegra186-sdhci + - nvidia,tegra194-sdhci + + - items: + - const: nvidia,tegra132-sdhci + - const: nvidia,tegra124-sdhci + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + assigned-clocks: true + assigned-clock-parents: true + assigned-clock-rates: true + + clocks: + minItems: 1 + maxItems: 2 + + clock-names: + minItems: 1 + maxItems: 2 + + resets: + items: + - description: module reset + + reset-names: + items: + - const: sdhci + + power-gpios: + description: specify GPIOs for power control + maxItems: 1 + + interconnects: + items: + - description: memory read client + - description: memory write client + + interconnect-names: + items: + - const: dma-mem # read + - const: write + + iommus: + maxItems: 1 + + operating-points-v2: + $ref: "/schemas/types.yaml#/definitions/phandle" + + power-domains: + items: + - description: phandle to the core power domain + + nvidia,default-tap: + description: Specify the default inbound sampling clock trimmer value for + non-tunable modes. + + The values are used for compensating trace length differences by + adjusting the sampling point. The values are programmed to the Vendor + Clock Control Register. Please refer to the reference manual of the SoC + for correct values. + + The DQS trim values are only used on controllers which support HS400 + timing. Only SDMMC4 on Tegra210 and Tegra186 supports HS400. + $ref: "/schemas/types.yaml#/definitions/uint32" + + nvidia,default-trim: + description: Specify the default outbound clock trimmer value. + $ref: "/schemas/types.yaml#/definitions/uint32" + + nvidia,dqs-trim: + description: Specify DQS trim value for HS400 timing. + $ref: "/schemas/types.yaml#/definitions/uint32" + + nvidia,pad-autocal-pull-down-offset-1v8: + description: Specify drive strength calibration offsets for 1.8 V + signaling modes. + $ref: "/schemas/types.yaml#/definitions/uint32" + + nvidia,pad-autocal-pull-down-offset-1v8-timeout: + description: Specify drive strength used as a fallback in case the + automatic calibration times out on a 1.8 V signaling mode. + $ref: "/schemas/types.yaml#/definitions/uint32" + + nvidia,pad-autocal-pull-down-offset-3v3: + description: Specify drive strength calibration offsets for 3.3 V + signaling modes. + $ref: "/schemas/types.yaml#/definitions/uint32" + + nvidia,pad-autocal-pull-down-offset-3v3-timeout: + description: Specify drive strength used as a fallback in case the + automatic calibration times out on a 3.3 V signaling mode. + $ref: "/schemas/types.yaml#/definitions/uint32" + + nvidia,pad-autocal-pull-down-offset-sdr104: + description: Specify drive strength calibration offsets for SDR104 mode. + $ref: "/schemas/types.yaml#/definitions/uint32" + + nvidia,pad-autocal-pull-down-offset-hs400: + description: Specify drive strength calibration offsets for HS400 mode. + $ref: "/schemas/types.yaml#/definitions/uint32" + + nvidia,pad-autocal-pull-up-offset-1v8: + description: Specify drive strength calibration offsets for 1.8 V + signaling modes. + $ref: "/schemas/types.yaml#/definitions/uint32" + + nvidia,pad-autocal-pull-up-offset-1v8-timeout: + description: Specify drive strength used as a fallback in case the + automatic calibration times out on a 1.8 V signaling mode. + $ref: "/schemas/types.yaml#/definitions/uint32" + + nvidia,pad-autocal-pull-up-offset-3v3: + description: Specify drive strength calibration offsets for 3.3 V + signaling modes. + + The property values are drive codes which are programmed into the + PD_OFFSET and PU_OFFSET sections of the SDHCI_TEGRA_AUTO_CAL_CONFIG + register. A higher value corresponds to higher drive strength. Please + refer to the reference manual of the SoC for correct values. The SDR104 + and HS400 timing specific values are used in corresponding modes if + specified. + $ref: "/schemas/types.yaml#/definitions/uint32" + + nvidia,pad-autocal-pull-up-offset-3v3-timeout: + description: Specify drive strength used as a fallback in case the + automatic calibration times out on a 3.3 V signaling mode. + $ref: "/schemas/types.yaml#/definitions/uint32" + + nvidia,pad-autocal-pull-up-offset-sdr104: + description: Specify drive strength calibration offsets for SDR104 mode. + $ref: "/schemas/types.yaml#/definitions/uint32" + + nvidia,pad-autocal-pull-up-offset-hs400: + description: Specify drive strength calibration offsets for HS400 mode. + $ref: "/schemas/types.yaml#/definitions/uint32" + + nvidia,only-1-8v: + description: The presence of this property indicates that the controller + operates at a 1.8 V fixed I/O voltage. + $ref: "/schemas/types.yaml#/definitions/flag" + +required: + - compatible + - reg + - interrupts + - clocks + - resets + - reset-names + +allOf: + - $ref: "mmc-controller.yaml" + - if: + properties: + compatible: + contains: + enum: + - nvidia,tegra20-sdhci + - nvidia,tegra30-sdhci + - nvidia,tegra114-sdhci + - nvidia,tegra124-sdhci + clocks: + items: + - description: module clock + minItems: 1 + maxItems: 1 + else: + properties: + clocks: + items: + - description: module clock + - description: timeout clock + minItems: 2 + maxItems: 2 + clock-names: + items: + - const: sdhci + - const: tmclk + minItems: 2 + maxItems: 2 + required: + - clock-names + + - if: + properties: + compatible: + contains: + const: nvidia,tegra210-sdhci + then: + properties: + pinctrl-names: + oneOf: + - items: + - const: sdmmc-3v3 + description: pad configuration for 3.3 V + - const: sdmmc-1v8 + description: pad configuration for 1.8 V + - const: sdmmc-3v3-drv + description: pull-up/down configuration for 3.3 V + - const: sdmmc-1v8-drv + description: pull-up/down configuration for 1.8 V + - items: + - const: sdmmc-3v3-drv + description: pull-up/down configuration for 3.3 V + - const: sdmmc-1v8-drv + description: pull-up/down configuration for 1.8 V + - items: + - const: sdmmc-1v8-drv + description: pull-up/down configuration for 1.8 V + required: + - clock-names + - if: + properties: + compatible: + contains: + enum: + - nvidia,tegra186-sdhci + - nvidia,tegra194-sdhci + then: + properties: + pinctrl-names: + items: + - const: sdmmc-3v3 + description: pad configuration for 3.3 V + - const: sdmmc-1v8 + description: pad configuration for 1.8 V + required: + - clock-names + +unevaluatedProperties: false + +examples: + - | + #include + + mmc@c8000200 { + compatible = "nvidia,tegra20-sdhci"; + reg = <0xc8000200 0x200>; + interrupts = <47>; + clocks = <&tegra_car 14>; + resets = <&tegra_car 14>; + reset-names = "sdhci"; + cd-gpios = <&gpio 69 0>; /* gpio PI5 */ + wp-gpios = <&gpio 57 0>; /* gpio PH1 */ + power-gpios = <&gpio 155 0>; /* gpio PT3 */ + bus-width = <8>; + }; + + - | + #include + #include + + mmc@700b0000 { + compatible = "nvidia,tegra210-sdhci"; + reg = <0x700b0000 0x200>; + interrupts = ; + clocks = <&tegra_car TEGRA210_CLK_SDMMC1>, + <&tegra_car TEGRA210_CLK_SDMMC_LEGACY>; + clock-names = "sdhci", "tmclk"; + resets = <&tegra_car 14>; + reset-names = "sdhci"; + pinctrl-names = "sdmmc-3v3", "sdmmc-1v8", + "sdmmc-3v3-drv", "sdmmc-1v8-drv"; + pinctrl-0 = <&sdmmc1_3v3>; + pinctrl-1 = <&sdmmc1_1v8>; + pinctrl-2 = <&sdmmc1_3v3_drv>; + pinctrl-3 = <&sdmmc1_1v8_drv>; + nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>; + nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>; + nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>; + nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>; + nvidia,default-tap = <0x2>; + nvidia,default-trim = <0x4>; + assigned-clocks = <&tegra_car TEGRA210_CLK_SDMMC4>, + <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>, + <&tegra_car TEGRA210_CLK_PLL_C4>; + assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; + assigned-clock-rates = <200000000>, <1000000000>, <1000000000>; + }; -- cgit v1.2.3-59-g8ed1b From 068cf93f900267fb4aaf2b14ff369f80aa4b5406 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 19 Nov 2021 15:38:26 +0100 Subject: dt-bindings: mailbox: tegra: Convert to json-schema Convert the NVIDIA Tegra HSP bindings from the free-form text format to json-schema. Reviewed-by: Rob Herring Signed-off-by: Thierry Reding --- .../bindings/mailbox/nvidia,tegra186-hsp.txt | 72 ------------- .../bindings/mailbox/nvidia,tegra186-hsp.yaml | 111 +++++++++++++++++++++ 2 files changed, 111 insertions(+), 72 deletions(-) delete mode 100644 Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.txt create mode 100644 Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.yaml (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.txt b/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.txt deleted file mode 100644 index ff3eafc5a882..000000000000 --- a/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.txt +++ /dev/null @@ -1,72 +0,0 @@ -NVIDIA Tegra Hardware Synchronization Primitives (HSP) - -The HSP modules are used for the processors to share resources and communicate -together. It provides a set of hardware synchronization primitives for -interprocessor communication. So the interprocessor communication (IPC) -protocols can use hardware synchronization primitives, when operating between -two processors not in an SMP relationship. - -The features that HSP supported are shared mailboxes, shared semaphores, -arbitrated semaphores and doorbells. - -Required properties: -- name : Should be hsp -- compatible - Array of strings. - one of: - - "nvidia,tegra186-hsp" - - "nvidia,tegra194-hsp", "nvidia,tegra186-hsp" -- reg : Offset and length of the register set for the device. -- interrupt-names - Array of strings. - Contains a list of names for the interrupts described by the interrupt - property. May contain the following entries, in any order: - - "doorbell" - - "sharedN", where 'N' is a number from zero up to the number of - external interrupts supported by the HSP instance minus one. - Users of this binding MUST look up entries in the interrupt property - by name, using this interrupt-names property to do so. -- interrupts - Array of interrupt specifiers. - Must contain one entry per entry in the interrupt-names property, - in a matching order. -- #mbox-cells : Should be 2. - -The mbox specifier of the "mboxes" property in the client node should contain -two cells. The first cell determines the HSP type and the second cell is used -to identify the mailbox that the client is going to use. - -For doorbells, the second cell specifies the index of the doorbell to use. - -For shared mailboxes, the second cell is composed of two fields: -- bits 31..24: - A bit mask of flags that further specify how the shared mailbox will be - used. Valid flags are: - - bit 31: - Defines the direction of the mailbox. If set, the mailbox will be used - as a producer (i.e. used to send data). If cleared, the mailbox is the - consumer of data sent by a producer. - -- bits 23.. 0: - The index of the shared mailbox to use. The number of available mailboxes - may vary by instance of the HSP block and SoC generation. - -The following file contains definitions that can be used to construct mailbox -specifiers: - - - -Example: - -hsp_top0: hsp@3c00000 { - compatible = "nvidia,tegra186-hsp"; - reg = <0x0 0x03c00000 0x0 0xa0000>; - interrupts = ; - interrupt-names = "doorbell"; - #mbox-cells = <2>; -}; - -client { - ... - mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB TEGRA_HSP_DB_MASTER_XXX>; -}; diff --git a/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.yaml b/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.yaml new file mode 100644 index 000000000000..c43fc4c56f77 --- /dev/null +++ b/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.yaml @@ -0,0 +1,111 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mailbox/nvidia,tegra186-hsp.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra Hardware Synchronization Primitives (HSP) + +maintainers: + - Thierry Reding + - Jon Hunter + +description: | + The HSP modules are used for the processors to share resources and + communicate together. It provides a set of hardware synchronization + primitives for interprocessor communication. So the interprocessor + communication (IPC) protocols can use hardware synchronization + primitives, when operating between two processors not in an SMP + relationship. + + The features that HSP supported are shared mailboxes, shared + semaphores, arbitrated semaphores and doorbells. + + The mbox specifier of the "mboxes" property in the client node should + contain two cells. The first cell determines the HSP type and the + second cell is used to identify the mailbox that the client is going + to use. + + For doorbells, the second cell specifies the index of the doorbell to + use. + + For shared mailboxes, the second cell is composed of two fields: + - bits 31..24: + A bit mask of flags that further specify how the shared mailbox + will be used. Valid flags are: + - bit 31: + Defines the direction of the mailbox. If set, the mailbox + will be used as a producer (i.e. used to send data). If + cleared, the mailbox is the consumer of data sent by a + producer. + + - bits 23..0: + The index of the shared mailbox to use. The number of available + mailboxes may vary by instance of the HSP block and SoC + generation. + + The following file contains definitions that can be used to + construct mailbox specifiers: + + + +properties: + $nodename: + pattern: "^hsp@[0-9a-f]+$" + + compatible: + oneOf: + - const: nvidia,tegra186-hsp + - const: nvidia,tegra194-hsp + + reg: + maxItems: 1 + + interrupts: + minItems: 1 + maxItems: 9 + + interrupt-names: + oneOf: + # shared interrupts are optional + - items: + - const: doorbell + + - items: + - const: doorbell + - pattern: "^shared[0-7]$" + - pattern: "^shared[0-7]$" + - pattern: "^shared[0-7]$" + - pattern: "^shared[0-7]$" + - pattern: "^shared[0-7]$" + - pattern: "^shared[0-7]$" + - pattern: "^shared[0-7]$" + - pattern: "^shared[0-7]$" + + - items: + - pattern: "^shared[0-7]$" + - pattern: "^shared[0-7]$" + - pattern: "^shared[0-7]$" + - pattern: "^shared[0-7]$" + + "#mbox-cells": + const: 2 + +additionalProperties: false + +examples: + - | + #include + #include + + hsp_top0: hsp@3c00000 { + compatible = "nvidia,tegra186-hsp"; + reg = <0x03c00000 0xa0000>; + interrupts = ; + interrupt-names = "doorbell"; + #mbox-cells = <2>; + }; + + client { + mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB TEGRA_HSP_DB_MASTER_CCPLEX>; + }; -- cgit v1.2.3-59-g8ed1b From 0637af949a8c75d171a635eb0e41a9104f23bb6b Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 19 Nov 2021 15:38:27 +0100 Subject: dt-bindings: mailbox: tegra: Document Tegra234 HSP Add the compatible string for the HSP block found on the Tegra234 SoC. Acked-by: Rob Herring Signed-off-by: Thierry Reding --- Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.yaml | 3 +++ 1 file changed, 3 insertions(+) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.yaml b/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.yaml index c43fc4c56f77..9f7a7296b57f 100644 --- a/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.yaml +++ b/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.yaml @@ -57,6 +57,9 @@ properties: oneOf: - const: nvidia,tegra186-hsp - const: nvidia,tegra194-hsp + - items: + - const: nvidia,tegra234-hsp + - const: nvidia,tegra194-hsp reg: maxItems: 1 -- cgit v1.2.3-59-g8ed1b From 2f9df754d0c20da8a2f64c461c4567a38b289ef9 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 19 Nov 2021 15:38:28 +0100 Subject: dt-bindings: rtc: tegra: Convert to json-schema Convert the NVIDIA Tegra RTC bindings from the free-form text format to json-schema. Reviewed-by: Rob Herring Signed-off-by: Thierry Reding --- .../devicetree/bindings/rtc/nvidia,tegra20-rtc.txt | 24 --------- .../bindings/rtc/nvidia,tegra20-rtc.yaml | 60 ++++++++++++++++++++++ 2 files changed, 60 insertions(+), 24 deletions(-) delete mode 100644 Documentation/devicetree/bindings/rtc/nvidia,tegra20-rtc.txt create mode 100644 Documentation/devicetree/bindings/rtc/nvidia,tegra20-rtc.yaml (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/rtc/nvidia,tegra20-rtc.txt b/Documentation/devicetree/bindings/rtc/nvidia,tegra20-rtc.txt deleted file mode 100644 index b7d98ed3e098..000000000000 --- a/Documentation/devicetree/bindings/rtc/nvidia,tegra20-rtc.txt +++ /dev/null @@ -1,24 +0,0 @@ -NVIDIA Tegra20 real-time clock - -The Tegra RTC maintains seconds and milliseconds counters, and five alarm -registers. The alarms and other interrupts may wake the system from low-power -state. - -Required properties: - -- compatible : For Tegra20, must contain "nvidia,tegra20-rtc". Otherwise, - must contain '"nvidia,-rtc", "nvidia,tegra20-rtc"', where - can be tegra30, tegra114, tegra124, or tegra132. -- reg : Specifies base physical address and size of the registers. -- interrupts : A single interrupt specifier. -- clocks : Must contain one entry, for the module clock. - See ../clocks/clock-bindings.txt for details. - -Example: - -timer { - compatible = "nvidia,tegra20-rtc"; - reg = <0x7000e000 0x100>; - interrupts = <0 2 0x04>; - clocks = <&tegra_car 4>; -}; diff --git a/Documentation/devicetree/bindings/rtc/nvidia,tegra20-rtc.yaml b/Documentation/devicetree/bindings/rtc/nvidia,tegra20-rtc.yaml new file mode 100644 index 000000000000..94266de73cb9 --- /dev/null +++ b/Documentation/devicetree/bindings/rtc/nvidia,tegra20-rtc.yaml @@ -0,0 +1,60 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/rtc/nvidia,tegra20-rtc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra real-time clock + +maintainers: + - Thierry Reding + - Jon Hunter + +description: | + The Tegra RTC maintains seconds and milliseconds counters, and five + alarm registers. The alarms and other interrupts may wake the system + from low-power state. + +properties: + compatible: + oneOf: + - const: nvidia,tegra20-rtc + - items: + - enum: + - nvidia,tegra30-rtc + - nvidia,tegra114-rtc + - nvidia,tegra124-rtc + - nvidia,tegra210-rtc + - nvidia,tegra186-rtc + - nvidia,tegra194-rtc + - const: nvidia,tegra20-rtc + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: rtc + +additionalProperties: false + +required: + - compatible + - reg + - interrupts + - clocks + +examples: + - | + timer@7000e000 { + compatible = "nvidia,tegra20-rtc"; + reg = <0x7000e000 0x100>; + interrupts = <0 2 0x04>; + clocks = <&tegra_car 4>; + }; -- cgit v1.2.3-59-g8ed1b From aa8f488fd616e23ce03311f2365ab07eab9bd350 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 19 Nov 2021 15:38:29 +0100 Subject: dt-bindings: rtc: tegra: Document Tegra234 RTC Add the compatible string for the RTC block found on the Tegra234 SoC. Acked-by: Rob Herring Signed-off-by: Thierry Reding --- Documentation/devicetree/bindings/rtc/nvidia,tegra20-rtc.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/rtc/nvidia,tegra20-rtc.yaml b/Documentation/devicetree/bindings/rtc/nvidia,tegra20-rtc.yaml index 94266de73cb9..17d6280e5515 100644 --- a/Documentation/devicetree/bindings/rtc/nvidia,tegra20-rtc.yaml +++ b/Documentation/devicetree/bindings/rtc/nvidia,tegra20-rtc.yaml @@ -27,6 +27,7 @@ properties: - nvidia,tegra210-rtc - nvidia,tegra186-rtc - nvidia,tegra194-rtc + - nvidia,tegra234-rtc - const: nvidia,tegra20-rtc reg: -- cgit v1.2.3-59-g8ed1b From 25388844f92f0560961cb7dd374bcdf343d5b1f9 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 19 Nov 2021 15:38:30 +0100 Subject: dt-bindings: fuse: tegra: Convert to json-schema Convert the NVIDIA Tegra FUSE bindings from the free-form text format to json-schema. Reviewed-by: Rob Herring Signed-off-by: Thierry Reding --- .../bindings/fuse/nvidia,tegra20-fuse.txt | 42 ----------- .../bindings/fuse/nvidia,tegra20-fuse.yaml | 88 ++++++++++++++++++++++ 2 files changed, 88 insertions(+), 42 deletions(-) delete mode 100644 Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.txt create mode 100644 Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.yaml (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.txt b/Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.txt deleted file mode 100644 index b109911669e4..000000000000 --- a/Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.txt +++ /dev/null @@ -1,42 +0,0 @@ -NVIDIA Tegra20/Tegra30/Tegr114/Tegra124 fuse block. - -Required properties: -- compatible : For Tegra20, must contain "nvidia,tegra20-efuse". For Tegra30, - must contain "nvidia,tegra30-efuse". For Tegra114, must contain - "nvidia,tegra114-efuse". For Tegra124, must contain "nvidia,tegra124-efuse". - For Tegra132 must contain "nvidia,tegra132-efuse", "nvidia,tegra124-efuse". - For Tegra210 must contain "nvidia,tegra210-efuse". For Tegra186 must contain - "nvidia,tegra186-efuse". For Tegra194 must contain "nvidia,tegra194-efuse". - For Tegra234 must contain "nvidia,tegra234-efuse". - Details: - nvidia,tegra20-efuse: Tegra20 requires using APB DMA to read the fuse data - due to a hardware bug. Tegra20 also lacks certain information which is - available in later generations such as fab code, lot code, wafer id,.. - nvidia,tegra30-efuse, nvidia,tegra114-efuse and nvidia,tegra124-efuse: - The differences between these SoCs are the size of the efuse array, - the location of the spare (OEM programmable) bits and the location of - the speedo data. -- reg: Should contain 1 entry: the entry gives the physical address and length - of the fuse registers. -- clocks: Must contain an entry for each entry in clock-names. - See ../clocks/clock-bindings.txt for details. -- clock-names: Must include the following entries: - - fuse -- resets: Must contain an entry for each entry in reset-names. - See ../reset/reset.txt for details. -- reset-names: Must include the following entries: - - fuse - -Example: - - fuse@7000f800 { - compatible = "nvidia,tegra20-efuse"; - reg = <0x7000f800 0x400>, - <0x70000000 0x400>; - clocks = <&tegra_car TEGRA20_CLK_FUSE>; - clock-names = "fuse"; - resets = <&tegra_car 39>; - reset-names = "fuse"; - }; - - diff --git a/Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.yaml b/Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.yaml new file mode 100644 index 000000000000..2bd901dda976 --- /dev/null +++ b/Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.yaml @@ -0,0 +1,88 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/fuse/nvidia,tegra20-fuse.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra FUSE block + +maintainers: + - Thierry Reding + - Jon Hunter + +properties: + compatible: + oneOf: + - enum: + - nvidia,tegra20-efuse + - nvidia,tegra30-efuse + - nvidia,tegra114-efuse + - nvidia,tegra124-efuse + - nvidia,tegra210-efuse + - nvidia,tegra186-efuse + - nvidia,tegra194-efuse + + - items: + - const: nvidia,tegra132-efuse + - const: nvidia,tegra124-efuse + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: fuse + + resets: + maxItems: 1 + + reset-names: + items: + - const: fuse + + operating-points-v2: + $ref: "/schemas/types.yaml#/definitions/phandle" + + power-domains: + items: + - description: phandle to the core power domain + +additionalProperties: false + +required: + - compatible + - reg + - clocks + - clock-names + +if: + properties: + compatible: + contains: + enum: + - nvidia,tegra20-efuse + - nvidia,tegra30-efuse + - nvidia,tegra114-efuse + - nvidia,tegra124-efuse + - nvidia,tegra132-efuse + - nvidia,tegra210-efuse +then: + required: + - resets + - reset-names + +examples: + - | + #include + + fuse@7000f800 { + compatible = "nvidia,tegra20-efuse"; + reg = <0x7000f800 0x400>; + clocks = <&tegra_car TEGRA20_CLK_FUSE>; + clock-names = "fuse"; + resets = <&tegra_car 39>; + reset-names = "fuse"; + }; -- cgit v1.2.3-59-g8ed1b From f8dd779bcb4b5a0f891f82a3f23f337ce82da783 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 19 Nov 2021 15:38:31 +0100 Subject: dt-bindings: fuse: tegra: Document Tegra234 FUSE Add the compatible string for the FUSE block found on the Tegra234 SoC. Acked-by: Rob Herring Signed-off-by: Thierry Reding --- Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.yaml b/Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.yaml index 2bd901dda976..481901269872 100644 --- a/Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.yaml +++ b/Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.yaml @@ -21,6 +21,7 @@ properties: - nvidia,tegra210-efuse - nvidia,tegra186-efuse - nvidia,tegra194-efuse + - nvidia,tegra234-efuse - items: - const: nvidia,tegra132-efuse -- cgit v1.2.3-59-g8ed1b From d5de8b7608e9e710b18a080b322b11cb40a11efc Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 19 Nov 2021 15:38:32 +0100 Subject: dt-bindings: mmc: tegra: Document Tegra234 SDHCI Add the compatible string for the SDHCI block found on the Tegra234 SoC. Acked-by: Rob Herring Signed-off-by: Thierry Reding --- Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.yaml | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.yaml b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.yaml index f7a9fcc6bbbd..ce64b3498378 100644 --- a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.yaml +++ b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.yaml @@ -33,6 +33,12 @@ properties: - const: nvidia,tegra132-sdhci - const: nvidia,tegra124-sdhci + - items: + - enum: + - nvidia,tegra194-sdhci + - nvidia,tegra234-sdhci + - const: nvidia,tegra186-sdhci + reg: maxItems: 1 -- cgit v1.2.3-59-g8ed1b From 96b594d2a0932d1c9ae1c48144a63aabc972222d Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 19 Nov 2021 15:38:33 +0100 Subject: dt-bindings: serial: 8250: Document Tegra234 UART Add the compatible string for the UART found on the Tegra234 SoC. Acked-by: Rob Herring Signed-off-by: Thierry Reding --- Documentation/devicetree/bindings/serial/8250.yaml | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/serial/8250.yaml b/Documentation/devicetree/bindings/serial/8250.yaml index fa767440f281..3bab2f27b970 100644 --- a/Documentation/devicetree/bindings/serial/8250.yaml +++ b/Documentation/devicetree/bindings/serial/8250.yaml @@ -113,9 +113,10 @@ properties: - nvidia,tegra30-uart - nvidia,tegra114-uart - nvidia,tegra124-uart + - nvidia,tegra210-uart - nvidia,tegra186-uart - nvidia,tegra194-uart - - nvidia,tegra210-uart + - nvidia,tegra234-uart - const: nvidia,tegra20-uart reg: -- cgit v1.2.3-59-g8ed1b From 5cda3b25cb04222988786ebebe346a7655bde05a Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 19 Nov 2021 15:38:34 +0100 Subject: dt-bindings: tegra: pmc: Convert to json-schema Convert the NVIDIA Tegra186 (and later) PMC bindings from the free-form text format to json-schema. Reviewed-by: Rob Herring Signed-off-by: Thierry Reding --- .../bindings/arm/tegra/nvidia,tegra186-pmc.txt | 133 -------------- .../bindings/arm/tegra/nvidia,tegra186-pmc.yaml | 198 +++++++++++++++++++++ 2 files changed, 198 insertions(+), 133 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.txt create mode 100644 Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.yaml (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.txt deleted file mode 100644 index 576462fae27f..000000000000 --- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.txt +++ /dev/null @@ -1,133 +0,0 @@ -NVIDIA Tegra Power Management Controller (PMC) - -Required properties: -- compatible: Should contain one of the following: - - "nvidia,tegra186-pmc": for Tegra186 - - "nvidia,tegra194-pmc": for Tegra194 - - "nvidia,tegra234-pmc": for Tegra234 -- reg: Must contain an (offset, length) pair of the register set for each - entry in reg-names. -- reg-names: Must include the following entries: - - "pmc" - - "wake" - - "aotag" - - "scratch" - - "misc" (Only for Tegra194 and later) - -Optional properties: -- nvidia,invert-interrupt: If present, inverts the PMU interrupt signal. -- interrupt-controller: Identifies the node as an interrupt controller. -- #interrupt-cells: Specifies the number of cells needed to encode an - interrupt source. The value must be 2. - -Example: - -SoC DTSI: - - pmc@c3600000 { - compatible = "nvidia,tegra186-pmc"; - reg = <0 0x0c360000 0 0x10000>, - <0 0x0c370000 0 0x10000>, - <0 0x0c380000 0 0x10000>, - <0 0x0c390000 0 0x10000>; - reg-names = "pmc", "wake", "aotag", "scratch"; - }; - -Board DTS: - - pmc@c360000 { - nvidia,invert-interrupt; - }; - -== Pad Control == - -On Tegra SoCs a pad is a set of pins which are configured as a group. -The pin grouping is a fixed attribute of the hardware. The PMC can be -used to set pad power state and signaling voltage. A pad can be either -in active or power down mode. The support for power state and signaling -voltage configuration varies depending on the pad in question. 3.3 V and -1.8 V signaling voltages are supported on pins where software -controllable signaling voltage switching is available. - -Pad configurations are described with pin configuration nodes which -are placed under the pmc node and they are referred to by the pinctrl -client properties. For more information see -Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt. - -The following pads are present on Tegra186: -csia csib dsi mipi-bias -pex-clk-bias pex-clk3 pex-clk2 pex-clk1 -usb0 usb1 usb2 usb-bias -uart audio hsic dbg -hdmi-dp0 hdmi-dp1 pex-cntrl sdmmc2-hv -sdmmc4 cam dsib dsic -dsid csic csid csie -dsif spi ufs dmic-hv -edp sdmmc1-hv sdmmc3-hv conn -audio-hv ao-hv - -Required pin configuration properties: - - pins: A list of strings, each of which contains the name of a pad - to be configured. - -Optional pin configuration properties: - - low-power-enable: Configure the pad into power down mode - - low-power-disable: Configure the pad into active mode - - power-source: Must contain either TEGRA_IO_PAD_VOLTAGE_1V8 or - TEGRA_IO_PAD_VOLTAGE_3V3 to select between signaling voltages. - The values are defined in - include/dt-bindings/pinctrl/pinctrl-tegra-io-pad.h. - -Note: The power state can be configured on all of the above pads except - for ao-hv. Following pads have software configurable signaling - voltages: sdmmc2-hv, dmic-hv, sdmmc1-hv, sdmmc3-hv, audio-hv, - ao-hv. - -Pad configuration state example: - pmc: pmc@7000e400 { - compatible = "nvidia,tegra186-pmc"; - reg = <0 0x0c360000 0 0x10000>, - <0 0x0c370000 0 0x10000>, - <0 0x0c380000 0 0x10000>, - <0 0x0c390000 0 0x10000>; - reg-names = "pmc", "wake", "aotag", "scratch"; - - ... - - sdmmc1_3v3: sdmmc1-3v3 { - pins = "sdmmc1-hv"; - power-source = ; - }; - - sdmmc1_1v8: sdmmc1-1v8 { - pins = "sdmmc1-hv"; - power-source = ; - }; - - hdmi_off: hdmi-off { - pins = "hdmi"; - low-power-enable; - } - - hdmi_on: hdmi-on { - pins = "hdmi"; - low-power-disable; - } - }; - -Pinctrl client example: - sdmmc1: sdhci@3400000 { - ... - pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; - pinctrl-0 = <&sdmmc1_3v3>; - pinctrl-1 = <&sdmmc1_1v8>; - }; - - ... - - sor0: sor@15540000 { - ... - pinctrl-0 = <&hdmi_off>; - pinctrl-1 = <&hdmi_on>; - pinctrl-names = "hdmi-on", "hdmi-off"; - }; diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.yaml b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.yaml new file mode 100644 index 000000000000..0faa403f68c8 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.yaml @@ -0,0 +1,198 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra186-pmc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra Power Management Controller (PMC) + +maintainers: + - Thierry Reding + - Jon Hunter + +properties: + compatible: + enum: + - nvidia,tegra186-pmc + - nvidia,tegra194-pmc + - nvidia,tegra234-pmc + + reg: + minItems: 4 + maxItems: 5 + + reg-names: + minItems: 4 + items: + - const: pmc + - const: wake + - const: aotag + - const: scratch + - const: misc + + interrupt-controller: true + + "#interrupt-cells": + description: Specifies the number of cells needed to encode an + interrupt source. The value must be 2. + const: 2 + + nvidia,invert-interrupt: + description: If present, inverts the PMU interrupt signal. + $ref: /schemas/types.yaml#/definitions/flag + +if: + properties: + compatible: + contains: + const: nvidia,tegra186-pmc +then: + properties: + reg: + maxItems: 4 + + reg-names: + maxItems: 4 +else: + properties: + reg: + minItems: 5 + + reg-names: + minItems: 5 + +patternProperties: + "^[a-z0-9]+-[a-z0-9]+$": + if: + type: object + then: + description: | + These are pad configuration nodes. On Tegra SoCs a pad is a set of + pins which are configured as a group. The pin grouping is a fixed + attribute of the hardware. The PMC can be used to set pad power + state and signaling voltage. A pad can be either in active or + power down mode. The support for power state and signaling voltage + configuration varies depending on the pad in question. 3.3 V and + 1.8 V signaling voltages are supported on pins where software + controllable signaling voltage switching is available. + + Pad configurations are described with pin configuration nodes + which are placed under the pmc node and they are referred to by + the pinctrl client properties. For more information see + + Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt + + The following pads are present on Tegra186: + + csia, csib, dsi, mipi-bias, pex-clk-bias, pex-clk3, pex-clk2, + pex-clk1, usb0, usb1, usb2, usb-bias, uart, audio, hsic, dbg, + hdmi-dp0, hdmi-dp1, pex-cntrl, sdmmc2-hv, sdmmc4, cam, dsib, + dsic, dsid, csic, csid, csie, dsif, spi, ufs, dmic-hv, edp, + sdmmc1-hv, sdmmc3-hv, conn, audio-hv, ao-hv + + The following pads are present on Tegra194: + + csia, csib, mipi-bias, pex-clk-bias, pex-clk3, pex-clk2, + pex-clk1, eqos, pex-clk-2-bias, pex-clk-2, dap3, dap5, uart, + pwr-ctl, soc-gpio53, audio, gp-pwm2, gp-pwm3, soc-gpio12, + soc-gpio13, soc-gpio10, uart4, uart5, dbg, hdmi-dp3, hdmi-dp2, + hdmi-dp0, hdmi-dp1, pex-cntrl, pex-ctl2, pex-l0-rst, + pex-l1-rst, sdmmc4, pex-l5-rst, cam, csic, csid, csie, csif, + spi, ufs, csig, csih, edp, sdmmc1-hv, sdmmc3-hv, conn, + audio-hv, ao-hv + + properties: + pins: + $ref: /schemas/types.yaml#/definitions/string + description: Must contain the name of the pad(s) to be + configured. + + low-power-enable: + description: Configure the pad into power down mode. + $ref: /schemas/types.yaml#/definitions/flag + + low-power-disable: + description: Configure the pad into active mode. + $ref: /schemas/types.yaml#/definitions/flag + + power-source: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Must contain either TEGRA_IO_PAD_VOLTAGE_1V8 or + TEGRA_IO_PAD_VOLTAGE_3V3 to select between signalling + voltages. + + The values are defined in + + include/dt-bindings/pinctrl/pinctrl-tegra-io-pad.h + + The power state can be configured on all of the above pads + except for ao-hv. Following pads have software configurable + signaling voltages: sdmmc2-hv, dmic-hv, sdmmc1-hv, sdmmc3-hv, + audio-hv, ao-hv. + + phandle: true + + required: + - pins + + additionalProperties: false + +required: + - compatible + - reg + - reg-names + +additionalProperties: false + +dependencies: + interrupt-controller: ['#interrupt-cells'] + "#interrupt-cells": + required: + - interrupt-controller + +examples: + - | + #include + #include + #include + #include + #include + + pmc@c3600000 { + compatible = "nvidia,tegra186-pmc"; + reg = <0x0c360000 0x10000>, + <0x0c370000 0x10000>, + <0x0c380000 0x10000>, + <0x0c390000 0x10000>; + reg-names = "pmc", "wake", "aotag", "scratch"; + nvidia,invert-interrupt; + + sdmmc1_3v3: sdmmc1-3v3 { + pins = "sdmmc1-hv"; + power-source = ; + }; + + sdmmc1_1v8: sdmmc1-1v8 { + pins = "sdmmc1-hv"; + power-source = ; + }; + }; + + sdmmc1: mmc@3400000 { + compatible = "nvidia,tegra186-sdhci"; + reg = <0x03400000 0x10000>; + interrupts = ; + clocks = <&bpmp TEGRA186_CLK_SDMMC1>, + <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>; + clock-names = "sdhci", "tmclk"; + resets = <&bpmp TEGRA186_RESET_SDMMC1>; + reset-names = "sdhci"; + interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRA &emc>, + <&mc TEGRA186_MEMORY_CLIENT_SDMMCWA &emc>; + interconnect-names = "dma-mem", "write"; + iommus = <&smmu TEGRA186_SID_SDMMC1>; + pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; + pinctrl-0 = <&sdmmc1_3v3>; + pinctrl-1 = <&sdmmc1_1v8>; + }; -- cgit v1.2.3-59-g8ed1b From d289f9de8b952bac7805c82d3f9dfd6440f62c8c Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 19 Nov 2021 15:38:35 +0100 Subject: dt-bindings: firmware: tegra: Convert to json-schema Convert the NVIDIA Tegra186 (and later) BPMP bindings from the free-form text format to json-schema. Reviewed-by: Rob Herring Signed-off-by: Thierry Reding --- .../bindings/firmware/nvidia,tegra186-bpmp.txt | 107 ------------ .../bindings/firmware/nvidia,tegra186-bpmp.yaml | 186 +++++++++++++++++++++ 2 files changed, 186 insertions(+), 107 deletions(-) delete mode 100644 Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.txt create mode 100644 Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.yaml (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.txt b/Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.txt deleted file mode 100644 index e44a13bc06ed..000000000000 --- a/Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.txt +++ /dev/null @@ -1,107 +0,0 @@ -NVIDIA Tegra Boot and Power Management Processor (BPMP) - -The BPMP is a specific processor in Tegra chip, which is designed for -booting process handling and offloading the power management, clock -management, and reset control tasks from the CPU. The binding document -defines the resources that would be used by the BPMP firmware driver, -which can create the interprocessor communication (IPC) between the CPU -and BPMP. - -Required properties: -- compatible - Array of strings - One of: - - "nvidia,tegra186-bpmp" -- mboxes : The phandle of mailbox controller and the mailbox specifier. -- shmem : List of the phandle of the TX and RX shared memory area that - the IPC between CPU and BPMP is based on. -- #clock-cells : Should be 1. -- #power-domain-cells : Should be 1. -- #reset-cells : Should be 1. - -This node is a mailbox consumer. See the following files for details of -the mailbox subsystem, and the specifiers implemented by the relevant -provider(s): - -- .../mailbox/mailbox.txt -- .../mailbox/nvidia,tegra186-hsp.txt - -This node is a clock, power domain, and reset provider. See the following -files for general documentation of those features, and the specifiers -implemented by this node: - -- .../clock/clock-bindings.txt -- -- ../power/power-domain.yaml -- -- .../reset/reset.txt -- - -The BPMP implements some services which must be represented by separate nodes. -For example, it can provide access to certain I2C controllers, and the I2C -bindings represent each I2C controller as a device tree node. Such nodes should -be nested directly inside the main BPMP node. - -Software can determine whether a child node of the BPMP node represents a device -by checking for a compatible property. Any node with a compatible property -represents a device that can be instantiated. Nodes without a compatible -property may be used to provide configuration information regarding the BPMP -itself, although no such configuration nodes are currently defined by this -binding. - -The BPMP firmware defines no single global name-/numbering-space for such -services. Put another way, the numbering scheme for I2C buses is distinct from -the numbering scheme for any other service the BPMP may provide (e.g. a future -hypothetical SPI bus service). As such, child device nodes will have no reg -property, and the BPMP node will have no #address-cells or #size-cells property. - -The shared memory bindings for BPMP ------------------------------------ - -The shared memory area for the IPC TX and RX between CPU and BPMP are -predefined and work on top of sysram, which is an SRAM inside the chip. - -See ".../sram/sram.txt" for the bindings. - -Example: - -hsp_top0: hsp@3c00000 { - ... - #mbox-cells = <2>; -}; - -sysram@30000000 { - compatible = "nvidia,tegra186-sysram", "mmio-sram"; - reg = <0x0 0x30000000 0x0 0x50000>; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0 0x0 0x0 0x30000000 0x0 0x50000>; - - cpu_bpmp_tx: shmem@4e000 { - compatible = "nvidia,tegra186-bpmp-shmem"; - reg = <0x0 0x4e000 0x0 0x1000>; - label = "cpu-bpmp-tx"; - pool; - }; - - cpu_bpmp_rx: shmem@4f000 { - compatible = "nvidia,tegra186-bpmp-shmem"; - reg = <0x0 0x4f000 0x0 0x1000>; - label = "cpu-bpmp-rx"; - pool; - }; -}; - -bpmp { - compatible = "nvidia,tegra186-bpmp"; - mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB TEGRA_HSP_DB_MASTER_BPMP>; - shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>; - #clock-cells = <1>; - #power-domain-cells = <1>; - #reset-cells = <1>; - - i2c { - compatible = "..."; - ... - }; -}; diff --git a/Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.yaml b/Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.yaml new file mode 100644 index 000000000000..833c07f1685c --- /dev/null +++ b/Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.yaml @@ -0,0 +1,186 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/firmware/nvidia,tegra186-bpmp.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra Boot and Power Management Processor (BPMP) + +maintainers: + - Thierry Reding + - Jon Hunter + +description: | + The BPMP is a specific processor in Tegra chip, which is designed for + booting process handling and offloading the power management, clock + management, and reset control tasks from the CPU. The binding document + defines the resources that would be used by the BPMP firmware driver, + which can create the interprocessor communication (IPC) between the + CPU and BPMP. + + This node is a mailbox consumer. See the following files for details + of the mailbox subsystem, and the specifiers implemented by the + relevant provider(s): + + - .../mailbox/mailbox.txt + - .../mailbox/nvidia,tegra186-hsp.yaml + + This node is a clock, power domain, and reset provider. See the + following files for general documentation of those features, and the + specifiers implemented by this node: + + - .../clock/clock-bindings.txt + - + - ../power/power-domain.yaml + - + - .../reset/reset.txt + - + + The BPMP implements some services which must be represented by + separate nodes. For example, it can provide access to certain I2C + controllers, and the I2C bindings represent each I2C controller as a + device tree node. Such nodes should be nested directly inside the main + BPMP node. + + Software can determine whether a child node of the BPMP node + represents a device by checking for a compatible property. Any node + with a compatible property represents a device that can be + instantiated. Nodes without a compatible property may be used to + provide configuration information regarding the BPMP itself, although + no such configuration nodes are currently defined by this binding. + + The BPMP firmware defines no single global name-/numbering-space for + such services. Put another way, the numbering scheme for I2C buses is + distinct from the numbering scheme for any other service the BPMP may + provide (e.g. a future hypothetical SPI bus service). As such, child + device nodes will have no reg property, and the BPMP node will have no + "#address-cells" or "#size-cells" property. + + The shared memory area for the IPC TX and RX between CPU and BPMP are + predefined and work on top of sysram, which is an SRAM inside the + chip. See ".../sram/sram.yaml" for the bindings. + +properties: + compatible: + oneOf: + - items: + - enum: + - nvidia,tegra194-bpmp + - nvidia,tegra234-bpmp + - const: nvidia,tegra186-bpmp + - const: nvidia,tegra186-bpmp + + mboxes: + description: A phandle and channel specifier for the mailbox used to + communicate with the BPMP. + maxItems: 1 + + shmem: + description: List of the phandle to the TX and RX shared memory area + that the IPC between CPU and BPMP is based on. + minItems: 2 + maxItems: 2 + + "#clock-cells": + const: 1 + + "#power-domain-cells": + const: 1 + + "#reset-cells": + const: 1 + + interconnects: + items: + - description: memory read client + - description: memory write client + - description: DMA read client + - description: DMA write client + + interconnect-names: + items: + - const: read + - const: write + - const: dma-mem # dma-read + - const: dma-write + + iommus: + maxItems: 1 + + i2c: + type: object + + thermal: + type: object + +additionalProperties: false + +required: + - compatible + - mboxes + - shmem + - "#clock-cells" + - "#power-domain-cells" + - "#reset-cells" + +examples: + - | + #include + #include + #include + + hsp_top0: hsp@3c00000 { + compatible = "nvidia,tegra186-hsp"; + reg = <0x03c00000 0xa0000>; + interrupts = ; + interrupt-names = "doorbell"; + #mbox-cells = <2>; + }; + + sram@30000000 { + compatible = "nvidia,tegra186-sysram", "mmio-sram"; + reg = <0x30000000 0x50000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x30000000 0x50000>; + + cpu_bpmp_tx: sram@4e000 { + reg = <0x4e000 0x1000>; + label = "cpu-bpmp-tx"; + pool; + }; + + cpu_bpmp_rx: sram@4f000 { + reg = <0x4f000 0x1000>; + label = "cpu-bpmp-rx"; + pool; + }; + }; + + bpmp { + compatible = "nvidia,tegra186-bpmp"; + interconnects = <&mc TEGRA186_MEMORY_CLIENT_BPMPR &emc>, + <&mc TEGRA186_MEMORY_CLIENT_BPMPW &emc>, + <&mc TEGRA186_MEMORY_CLIENT_BPMPDMAR &emc>, + <&mc TEGRA186_MEMORY_CLIENT_BPMPDMAW &emc>; + interconnect-names = "read", "write", "dma-mem", "dma-write"; + iommus = <&smmu TEGRA186_SID_BPMP>; + mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB + TEGRA_HSP_DB_MASTER_BPMP>; + shmem = <&cpu_bpmp_tx>, <&cpu_bpmp_rx>; + #clock-cells = <1>; + #power-domain-cells = <1>; + #reset-cells = <1>; + + i2c { + compatible = "nvidia,tegra186-bpmp-i2c"; + nvidia,bpmp-bus-id = <5>; + #address-cells = <1>; + #size-cells = <0>; + }; + + thermal { + compatible = "nvidia,tegra186-bpmp-thermal"; + #thermal-sensor-cells = <1>; + }; + }; -- cgit v1.2.3-59-g8ed1b From a12e1b7812ff81236732abf0f361d59c32890f9a Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 19 Nov 2021 15:38:37 +0100 Subject: dt-bindings: thermal: tegra186-bpmp: Convert to json-schema Convert the Tegra186 (and later) BPMP thermal device tree bindings from the free-form text format to json-schema. Reviewed-by: Rob Herring Signed-off-by: Thierry Reding --- .../thermal/nvidia,tegra186-bpmp-thermal.txt | 33 ----------------- .../thermal/nvidia,tegra186-bpmp-thermal.yaml | 42 ++++++++++++++++++++++ 2 files changed, 42 insertions(+), 33 deletions(-) delete mode 100644 Documentation/devicetree/bindings/thermal/nvidia,tegra186-bpmp-thermal.txt create mode 100644 Documentation/devicetree/bindings/thermal/nvidia,tegra186-bpmp-thermal.yaml (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/thermal/nvidia,tegra186-bpmp-thermal.txt b/Documentation/devicetree/bindings/thermal/nvidia,tegra186-bpmp-thermal.txt deleted file mode 100644 index fc87f6aa1b8f..000000000000 --- a/Documentation/devicetree/bindings/thermal/nvidia,tegra186-bpmp-thermal.txt +++ /dev/null @@ -1,33 +0,0 @@ -NVIDIA Tegra186 BPMP thermal sensor - -In Tegra186, the BPMP (Boot and Power Management Processor) implements an -interface that is used to read system temperatures, including CPU cluster -and GPU temperatures. This binding describes the thermal sensor that is -exposed by BPMP. - -The BPMP thermal node must be located directly inside the main BPMP node. See -../firmware/nvidia,tegra186-bpmp.txt for details of the BPMP binding. - -This node represents a thermal sensor. See Documentation/devicetree/bindings/thermal/thermal-sensor.yaml for details of the -core thermal binding. - -Required properties: -- compatible: - Array of strings. - One of: - - "nvidia,tegra186-bpmp-thermal" - - "nvidia,tegra194-bpmp-thermal" -- #thermal-sensor-cells: Cell for sensor index. - Single-cell integer. - Must be <1>. - -Example: - -bpmp { - ... - - bpmp_thermal: thermal { - compatible = "nvidia,tegra186-bpmp-thermal"; - #thermal-sensor-cells = <1>; - }; -}; diff --git a/Documentation/devicetree/bindings/thermal/nvidia,tegra186-bpmp-thermal.yaml b/Documentation/devicetree/bindings/thermal/nvidia,tegra186-bpmp-thermal.yaml new file mode 100644 index 000000000000..c91fd07e4061 --- /dev/null +++ b/Documentation/devicetree/bindings/thermal/nvidia,tegra186-bpmp-thermal.yaml @@ -0,0 +1,42 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/thermal/nvidia,tegra186-bpmp-thermal.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra186 (and later) BPMP thermal sensor + +maintainers: + - Thierry Reding + - Jon Hunter + +description: | + In Tegra186, the BPMP (Boot and Power Management Processor) implements + an interface that is used to read system temperatures, including CPU + cluster and GPU temperatures. This binding describes the thermal + sensor that is exposed by BPMP. + + The BPMP thermal node must be located directly inside the main BPMP + node. See ../firmware/nvidia,tegra186-bpmp.yaml for details of the + BPMP binding. + + This node represents a thermal sensor. See + + Documentation/devicetree/bindings/thermal/thermal-sensor.yaml + + for details of the core thermal binding. + +properties: + compatible: + enum: + - nvidia,tegra186-bpmp-thermal + - nvidia,tegra194-bpmp-thermal + + '#thermal-sensor-cells': + $ref: /schemas/types.yaml#/definitions/uint32 + description: Number of cells needed in the phandle specifier to + identify a given sensor. Must be 1 and the single cell specifies + the sensor index. + const: 1 + +additionalProperties: false -- cgit v1.2.3-59-g8ed1b From 8461fe3e443b28dc44773c98c642d094caa1976d Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 19 Nov 2021 15:38:38 +0100 Subject: dt-bindings: serial: tegra-tcu: Convert to json-schema Convert the Tegra TCU device tree bindings to json-schema. Reviewed-by: Rob Herring Signed-off-by: Thierry Reding --- .../bindings/serial/nvidia,tegra194-tcu.txt | 35 -------------- .../bindings/serial/nvidia,tegra194-tcu.yaml | 56 ++++++++++++++++++++++ 2 files changed, 56 insertions(+), 35 deletions(-) delete mode 100644 Documentation/devicetree/bindings/serial/nvidia,tegra194-tcu.txt create mode 100644 Documentation/devicetree/bindings/serial/nvidia,tegra194-tcu.yaml (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/serial/nvidia,tegra194-tcu.txt b/Documentation/devicetree/bindings/serial/nvidia,tegra194-tcu.txt deleted file mode 100644 index 085a8591accd..000000000000 --- a/Documentation/devicetree/bindings/serial/nvidia,tegra194-tcu.txt +++ /dev/null @@ -1,35 +0,0 @@ -NVIDIA Tegra Combined UART (TCU) - -The TCU is a system for sharing a hardware UART instance among multiple -systems within the Tegra SoC. It is implemented through a mailbox- -based protocol where each "virtual UART" has a pair of mailboxes, one -for transmitting and one for receiving, that is used to communicate -with the hardware implementing the TCU. - -Required properties: -- name : Should be tcu -- compatible - Array of strings - One of: - - "nvidia,tegra194-tcu" -- mbox-names: - "rx" - Mailbox for receiving data from hardware UART - "tx" - Mailbox for transmitting data to hardware UART -- mboxes: Mailboxes corresponding to the mbox-names. - -This node is a mailbox consumer. See the following files for details of -the mailbox subsystem, and the specifiers implemented by the relevant -provider(s): - -- .../mailbox/mailbox.txt -- .../mailbox/nvidia,tegra186-hsp.txt - -Example bindings: ------------------ - -tcu: tcu { - compatible = "nvidia,tegra194-tcu"; - mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM 0>, - <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM 1>; - mbox-names = "rx", "tx"; -}; diff --git a/Documentation/devicetree/bindings/serial/nvidia,tegra194-tcu.yaml b/Documentation/devicetree/bindings/serial/nvidia,tegra194-tcu.yaml new file mode 100644 index 000000000000..7987eca0bb52 --- /dev/null +++ b/Documentation/devicetree/bindings/serial/nvidia,tegra194-tcu.yaml @@ -0,0 +1,56 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/serial/nvidia,tegra194-tcu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra Combined UART (TCU) + +maintainers: + - Thierry Reding + - Jonathan Hunter + +description: + The TCU is a system for sharing a hardware UART instance among multiple + systems within the Tegra SoC. It is implemented through a mailbox- + based protocol where each "virtual UART" has a pair of mailboxes, one + for transmitting and one for receiving, that is used to communicate + with the hardware implementing the TCU. + +properties: + $nodename: + pattern: "^serial(@.*)?$" + + compatible: + const: nvidia,tegra194-tcu + + mbox-names: + items: + - const: rx + - const: tx + + mboxes: + description: | + List of phandles to mailbox channels used for receiving and + transmitting data from and to the hardware UART. + items: + - description: mailbox for receiving data from hardware UART + - description: mailbox for transmitting data to hardware UART + +required: + - compatible + - mbox-names + - mboxes + +additionalProperties: false + +examples: + - | + #include + + tcu: serial { + compatible = "nvidia,tegra194-tcu"; + mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM 0>, + <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM 1>; + mbox-names = "rx", "tx"; + }; -- cgit v1.2.3-59-g8ed1b From cd1fe47862c71994390e810182785a4f4d371875 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 19 Nov 2021 15:38:39 +0100 Subject: dt-bindings: serial: Document Tegra234 TCU Add the compatible string for the TCU found on the Tegra234 SoC. Acked-by: Rob Herring Signed-off-by: Thierry Reding --- Documentation/devicetree/bindings/serial/nvidia,tegra194-tcu.yaml | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/serial/nvidia,tegra194-tcu.yaml b/Documentation/devicetree/bindings/serial/nvidia,tegra194-tcu.yaml index 7987eca0bb52..e2d111b3e0b0 100644 --- a/Documentation/devicetree/bindings/serial/nvidia,tegra194-tcu.yaml +++ b/Documentation/devicetree/bindings/serial/nvidia,tegra194-tcu.yaml @@ -22,7 +22,12 @@ properties: pattern: "^serial(@.*)?$" compatible: - const: nvidia,tegra194-tcu + oneOf: + - const: nvidia,tegra194-tcu + - items: + - enum: + - nvidia,tegra234-tcu + - const: nvidia,tegra194-tcu mbox-names: items: -- cgit v1.2.3-59-g8ed1b From a90901a5a373b364d1495dbd853d31f391c021a8 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Mon, 6 Dec 2021 16:55:59 +0100 Subject: dt-bindings: usb: tegra-xudc: Document interconnects and iommus properties Add the interconnects, interconnect-names and iommus properties to the device tree bindings for the Tegra XUDC controller. These are used to describe the device's paths to and from memory. Acked-by: Rob Herring Signed-off-by: Thierry Reding --- .../devicetree/bindings/usb/nvidia,tegra-xudc.yaml | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/usb/nvidia,tegra-xudc.yaml b/Documentation/devicetree/bindings/usb/nvidia,tegra-xudc.yaml index 8428415896ce..a39c76b89484 100644 --- a/Documentation/devicetree/bindings/usb/nvidia,tegra-xudc.yaml +++ b/Documentation/devicetree/bindings/usb/nvidia,tegra-xudc.yaml @@ -59,6 +59,19 @@ properties: - const: fs_src - const: hs_src + interconnects: + items: + - description: memory read client + - description: memory write client + + interconnect-names: + items: + - const: dma-mem # read + - const: write + + iommus: + maxItems: 1 + power-domains: items: - description: XUSBB(device) power-domain -- cgit v1.2.3-59-g8ed1b From b58db7135a1279ca77db9444701dbee02fa29fb7 Mon Sep 17 00:00:00 2001 From: Svyatoslav Ryhel Date: Sun, 12 Dec 2021 00:13:45 +0300 Subject: dt-bindings: ARM: tegra: Document ASUS Transformers Document Tegra20/30/114-based ASUS Transformer Series tablet devices. This group includes EeePad TF101, Prime TF201, Pad TF300T, TF300TG Infinity TF700T, TF701T. Signed-off-by: David Heidelberg Signed-off-by: Anton Bambura Signed-off-by: Svyatoslav Ryhel Acked-by: Rob Herring Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- Documentation/devicetree/bindings/arm/tegra.yaml | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/arm/tegra.yaml b/Documentation/devicetree/bindings/arm/tegra.yaml index 3bd0920da274..64b7b770a0dc 100644 --- a/Documentation/devicetree/bindings/arm/tegra.yaml +++ b/Documentation/devicetree/bindings/arm/tegra.yaml @@ -36,6 +36,9 @@ properties: - toradex,colibri_t20-iris - const: toradex,colibri_t20 - const: nvidia,tegra20 + - items: + - const: asus,tf101 + - const: nvidia,tegra20 - items: - const: acer,picasso - const: nvidia,tegra20 @@ -49,6 +52,18 @@ properties: - nvidia,cardhu-a04 - const: nvidia,cardhu - const: nvidia,tegra30 + - items: + - const: asus,tf201 + - const: nvidia,tegra30 + - items: + - const: asus,tf300t + - const: nvidia,tegra30 + - items: + - const: asus,tf300tg + - const: nvidia,tegra30 + - items: + - const: asus,tf700t + - const: nvidia,tegra30 - items: - const: toradex,apalis_t30-eval - const: toradex,apalis_t30 @@ -76,6 +91,7 @@ properties: - const: nvidia,tegra30 - items: - enum: + - asus,tf701t - nvidia,dalmore - nvidia,roth - nvidia,tn7 -- cgit v1.2.3-59-g8ed1b From f64de71a9383457345ca6cd653c02f5b80a695e3 Mon Sep 17 00:00:00 2001 From: David Heidelberg Date: Sun, 12 Dec 2021 00:13:46 +0300 Subject: dt-bindings: ARM: tegra: Document Pegatron Chagall Document Pegatron Chagall, which is Tegra30-based tablet device. Acked-by: Rob Herring Signed-off-by: David Heidelberg Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- Documentation/devicetree/bindings/arm/tegra.yaml | 3 +++ 1 file changed, 3 insertions(+) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/arm/tegra.yaml b/Documentation/devicetree/bindings/arm/tegra.yaml index 64b7b770a0dc..49841ca272ee 100644 --- a/Documentation/devicetree/bindings/arm/tegra.yaml +++ b/Documentation/devicetree/bindings/arm/tegra.yaml @@ -89,6 +89,9 @@ properties: - items: - const: ouya,ouya - const: nvidia,tegra30 + - items: + - const: pegatron,chagall + - const: nvidia,tegra30 - items: - enum: - asus,tf701t -- cgit v1.2.3-59-g8ed1b From d0e70d13048419913c4723793c9f600acd861b36 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Wed, 1 Dec 2021 02:23:11 +0300 Subject: dt-bindings: clock: tegra-car: Document new clock sub-nodes Document sub-nodes which describe Tegra SoC clocks that require a higher voltage of the core power domain in order to operate properly on a higher clock rates. Each node contains a phandle to OPP table and power domain. The root PLLs and system clocks don't have any specific device dedicated to them, clock controller is in charge of managing power for them. Reviewed-by: Rob Herring Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- .../bindings/clock/nvidia,tegra20-car.yaml | 37 ++++++++++++++++++++++ 1 file changed, 37 insertions(+) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.yaml b/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.yaml index 459d2a525393..f832abb7f11a 100644 --- a/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.yaml +++ b/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.yaml @@ -42,6 +42,36 @@ properties: "#reset-cells": const: 1 +patternProperties: + "^(sclk)|(pll-[cem])$": + type: object + properties: + compatible: + enum: + - nvidia,tegra20-sclk + - nvidia,tegra30-sclk + - nvidia,tegra30-pllc + - nvidia,tegra30-plle + - nvidia,tegra30-pllm + + operating-points-v2: true + + clocks: + items: + - description: node's clock + + power-domains: + maxItems: 1 + description: phandle to the core SoC power domain + + required: + - compatible + - operating-points-v2 + - clocks + - power-domains + + additionalProperties: false + required: - compatible - reg @@ -59,6 +89,13 @@ examples: reg = <0x60006000 0x1000>; #clock-cells = <1>; #reset-cells = <1>; + + sclk { + compatible = "nvidia,tegra20-sclk"; + operating-points-v2 = <&opp_table>; + clocks = <&tegra_car TEGRA20_CLK_SCLK>; + power-domains = <&domain>; + }; }; usb-controller@c5004000 { -- cgit v1.2.3-59-g8ed1b From 425a68a963698867a9b6a8d82fcd41354a01f0ab Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Wed, 1 Dec 2021 02:23:13 +0300 Subject: dt-bindings: host1x: Document OPP and power domain properties Document new DVFS OPP table and power domain properties of the Host1x bus and devices sitting on the bus. Reviewed-by: Rob Herring Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- .../display/tegra/nvidia,tegra20-host1x.txt | 49 ++++++++++++++++++++++ 1 file changed, 49 insertions(+) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt index 8a6d3e1ee306..62861a8fb5c6 100644 --- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt @@ -20,6 +20,18 @@ Required properties: - reset-names: Must include the following entries: - host1x +Optional properties: +- operating-points-v2: See ../bindings/opp/opp.txt for details. + - power-domains: Phandle to HEG or core power domain. + +For each opp entry in 'operating-points-v2' table of host1x and its modules: +- opp-supported-hw: One bitfield indicating: + On Tegra20: SoC process ID mask + On Tegra30+: SoC speedo ID mask + + A bitwise AND is performed against the value and if any bit + matches, the OPP gets enabled. + Each host1x client module having to perform DMA through the Memory Controller should have the interconnect endpoints set to the Memory Client and External Memory respectively. @@ -45,6 +57,8 @@ of the following host1x client modules: - interconnect-names: Must include name of the interconnect path for each interconnect entry. Consult TRM documentation for information about available memory clients, see MEMORY CONTROLLER section. + - operating-points-v2: See ../bindings/opp/opp.txt for details. + - power-domains: Phandle to MPE power domain. - vi: video input @@ -128,6 +142,8 @@ of the following host1x client modules: - interconnect-names: Must include name of the interconnect path for each interconnect entry. Consult TRM documentation for information about available memory clients, see MEMORY CONTROLLER section. + - operating-points-v2: See ../bindings/opp/opp.txt for details. + - power-domains: Phandle to VENC power domain. - epp: encoder pre-processor @@ -147,6 +163,8 @@ of the following host1x client modules: - interconnect-names: Must include name of the interconnect path for each interconnect entry. Consult TRM documentation for information about available memory clients, see MEMORY CONTROLLER section. + - operating-points-v2: See ../bindings/opp/opp.txt for details. + - power-domains: Phandle to HEG or core power domain. - isp: image signal processor @@ -166,6 +184,7 @@ of the following host1x client modules: - interconnect-names: Must include name of the interconnect path for each interconnect entry. Consult TRM documentation for information about available memory clients, see MEMORY CONTROLLER section. + - power-domains: Phandle to VENC or core power domain. - gr2d: 2D graphics engine @@ -185,6 +204,8 @@ of the following host1x client modules: - interconnect-names: Must include name of the interconnect path for each interconnect entry. Consult TRM documentation for information about available memory clients, see MEMORY CONTROLLER section. + - operating-points-v2: See ../bindings/opp/opp.txt for details. + - power-domains: Phandle to HEG or core power domain. - gr3d: 3D graphics engine @@ -209,6 +230,8 @@ of the following host1x client modules: - interconnect-names: Must include name of the interconnect path for each interconnect entry. Consult TRM documentation for information about available memory clients, see MEMORY CONTROLLER section. + - operating-points-v2: See ../bindings/opp/opp.txt for details. + - power-domains: Phandles to 3D or core power domain. - dc: display controller @@ -241,6 +264,8 @@ of the following host1x client modules: - interconnect-names: Must include name of the interconnect path for each interconnect entry. Consult TRM documentation for information about available memory clients, see MEMORY CONTROLLER section. + - operating-points-v2: See ../bindings/opp/opp.txt for details. + - power-domains: Phandle to core power domain. - hdmi: High Definition Multimedia Interface @@ -267,6 +292,7 @@ of the following host1x client modules: - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection - nvidia,edid: supplies a binary EDID blob - nvidia,panel: phandle of a display panel + - operating-points-v2: See ../bindings/opp/opp.txt for details. - tvo: TV encoder output @@ -277,6 +303,10 @@ of the following host1x client modules: - clocks: Must contain one entry, for the module clock. See ../clocks/clock-bindings.txt for details. + Optional properties: + - operating-points-v2: See ../bindings/opp/opp.txt for details. + - power-domains: Phandle to core power domain. + - dsi: display serial interface Required properties: @@ -305,6 +335,7 @@ of the following host1x client modules: - nvidia,panel: phandle of a display panel - nvidia,ganged-mode: contains a phandle to a second DSI controller to gang up with in order to support up to 8 data lanes + - operating-points-v2: See ../bindings/opp/opp.txt for details. - sor: serial output resource @@ -408,6 +439,8 @@ Example: clocks = <&tegra_car TEGRA20_CLK_HOST1X>; resets = <&tegra_car 28>; reset-names = "host1x"; + operating-points-v2 = <&dvfs_opp_table>; + power-domains = <&domain>; #address-cells = <1>; #size-cells = <1>; @@ -421,6 +454,8 @@ Example: clocks = <&tegra_car TEGRA20_CLK_MPE>; resets = <&tegra_car 60>; reset-names = "mpe"; + operating-points-v2 = <&dvfs_opp_table>; + power-domains = <&domain>; }; vi@54080000 { @@ -429,6 +464,7 @@ Example: interrupts = ; assigned-clocks = <&tegra_car TEGRA210_CLK_VI>; assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; + operating-points-v2 = <&dvfs_opp_table>; clocks = <&tegra_car TEGRA210_CLK_VI>; power-domains = <&pd_venc>; @@ -510,6 +546,8 @@ Example: clocks = <&tegra_car TEGRA20_CLK_EPP>; resets = <&tegra_car 19>; reset-names = "epp"; + operating-points-v2 = <&dvfs_opp_table>; + power-domains = <&domain>; }; isp { @@ -528,6 +566,8 @@ Example: clocks = <&tegra_car TEGRA20_CLK_GR2D>; resets = <&tegra_car 21>; reset-names = "2d"; + operating-points-v2 = <&dvfs_opp_table>; + power-domains = <&domain>; }; gr3d { @@ -536,6 +576,8 @@ Example: clocks = <&tegra_car TEGRA20_CLK_GR3D>; resets = <&tegra_car 24>; reset-names = "3d"; + operating-points-v2 = <&dvfs_opp_table>; + power-domains = <&domain>; }; dc@54200000 { @@ -547,6 +589,8 @@ Example: clock-names = "dc", "parent"; resets = <&tegra_car 27>; reset-names = "dc"; + operating-points-v2 = <&dvfs_opp_table>; + power-domains = <&domain>; interconnects = <&mc TEGRA20_MC_DISPLAY0A &emc>, <&mc TEGRA20_MC_DISPLAY0B &emc>, @@ -571,6 +615,8 @@ Example: clock-names = "dc", "parent"; resets = <&tegra_car 26>; reset-names = "dc"; + operating-points-v2 = <&dvfs_opp_table>; + power-domains = <&domain>; interconnects = <&mc TEGRA20_MC_DISPLAY0AB &emc>, <&mc TEGRA20_MC_DISPLAY0BB &emc>, @@ -596,6 +642,7 @@ Example: resets = <&tegra_car 51>; reset-names = "hdmi"; status = "disabled"; + operating-points-v2 = <&dvfs_opp_table>; }; tvo { @@ -604,6 +651,7 @@ Example: interrupts = <0 76 0x04>; clocks = <&tegra_car TEGRA20_CLK_TVO>; status = "disabled"; + operating-points-v2 = <&dvfs_opp_table>; }; dsi { @@ -615,6 +663,7 @@ Example: resets = <&tegra_car 48>; reset-names = "dsi"; status = "disabled"; + operating-points-v2 = <&dvfs_opp_table>; }; }; -- cgit v1.2.3-59-g8ed1b From 0c41e287f7541aee58c5a0c4437524fbdbf63bd9 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Wed, 1 Dec 2021 02:23:14 +0300 Subject: dt-bindings: host1x: Document Memory Client resets of Host1x, GR2D and GR3D Memory Client should be blocked before hardware reset is asserted in order to prevent memory corruption and hanging of memory controller. Document Memory Client resets of Host1x, GR2D and GR3D hardware units. Reviewed-by: Rob Herring Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- .../devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt index 62861a8fb5c6..e61999ce54e9 100644 --- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt @@ -19,6 +19,7 @@ Required properties: See ../reset/reset.txt for details. - reset-names: Must include the following entries: - host1x + - mc Optional properties: - operating-points-v2: See ../bindings/opp/opp.txt for details. @@ -198,6 +199,7 @@ of the following host1x client modules: See ../reset/reset.txt for details. - reset-names: Must include the following entries: - 2d + - mc Optional properties: - interconnects: Must contain entry for the GR2D memory clients. @@ -224,6 +226,8 @@ of the following host1x client modules: - reset-names: Must include the following entries: - 3d - 3d2 (Only required on SoCs with two 3D clocks) + - mc + - mc2 (Only required on SoCs with two 3D clocks) Optional properties: - interconnects: Must contain entry for the GR3D memory clients. -- cgit v1.2.3-59-g8ed1b From ccc3016261edc37d66123946ede157f8c22205da Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Wed, 1 Dec 2021 02:23:32 +0300 Subject: media: dt: bindings: tegra-vde: Convert to schema Convert NVIDIA Tegra video decoder binding to schema. Reviewed-by: Rob Herring Acked-by: Hans Verkuil Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- .../devicetree/bindings/media/nvidia,tegra-vde.txt | 64 ------------ .../bindings/media/nvidia,tegra-vde.yaml | 107 +++++++++++++++++++++ 2 files changed, 107 insertions(+), 64 deletions(-) delete mode 100644 Documentation/devicetree/bindings/media/nvidia,tegra-vde.txt create mode 100644 Documentation/devicetree/bindings/media/nvidia,tegra-vde.yaml (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/media/nvidia,tegra-vde.txt b/Documentation/devicetree/bindings/media/nvidia,tegra-vde.txt deleted file mode 100644 index 602169b8aa19..000000000000 --- a/Documentation/devicetree/bindings/media/nvidia,tegra-vde.txt +++ /dev/null @@ -1,64 +0,0 @@ -NVIDIA Tegra Video Decoder Engine - -Required properties: -- compatible : Must contain one of the following values: - - "nvidia,tegra20-vde" - - "nvidia,tegra30-vde" - - "nvidia,tegra114-vde" - - "nvidia,tegra124-vde" - - "nvidia,tegra132-vde" -- reg : Must contain an entry for each entry in reg-names. -- reg-names : Must include the following entries: - - sxe - - bsev - - mbe - - ppe - - mce - - tfe - - ppb - - vdma - - frameid -- iram : Must contain phandle to the mmio-sram device node that represents - IRAM region used by VDE. -- interrupts : Must contain an entry for each entry in interrupt-names. -- interrupt-names : Must include the following entries: - - sync-token - - bsev - - sxe -- clocks : Must include the following entries: - - vde -- resets : Must contain an entry for each entry in reset-names. -- reset-names : Should include the following entries: - - vde - -Optional properties: -- resets : Must contain an entry for each entry in reset-names. -- reset-names : Must include the following entries: - - mc -- iommus: Must contain phandle to the IOMMU device node. - -Example: - -video-codec@6001a000 { - compatible = "nvidia,tegra20-vde"; - reg = <0x6001a000 0x1000 /* Syntax Engine */ - 0x6001b000 0x1000 /* Video Bitstream Engine */ - 0x6001c000 0x100 /* Macroblock Engine */ - 0x6001c200 0x100 /* Post-processing Engine */ - 0x6001c400 0x100 /* Motion Compensation Engine */ - 0x6001c600 0x100 /* Transform Engine */ - 0x6001c800 0x100 /* Pixel prediction block */ - 0x6001ca00 0x100 /* Video DMA */ - 0x6001d800 0x300 /* Video frame controls */>; - reg-names = "sxe", "bsev", "mbe", "ppe", "mce", - "tfe", "ppb", "vdma", "frameid"; - iram = <&vde_pool>; /* IRAM region */ - interrupts = , /* Sync token interrupt */ - , /* BSE-V interrupt */ - ; /* SXE interrupt */ - interrupt-names = "sync-token", "bsev", "sxe"; - clocks = <&tegra_car TEGRA20_CLK_VDE>; - reset-names = "vde", "mc"; - resets = <&tegra_car 61>, <&mc TEGRA20_MC_RESET_VDE>; - iommus = <&mc TEGRA_SWGROUP_VDE>; -}; diff --git a/Documentation/devicetree/bindings/media/nvidia,tegra-vde.yaml b/Documentation/devicetree/bindings/media/nvidia,tegra-vde.yaml new file mode 100644 index 000000000000..c143aaa06346 --- /dev/null +++ b/Documentation/devicetree/bindings/media/nvidia,tegra-vde.yaml @@ -0,0 +1,107 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/nvidia,tegra-vde.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra Video Decoder Engine + +maintainers: + - Dmitry Osipenko + - Jon Hunter + - Thierry Reding + +properties: + compatible: + oneOf: + - items: + - enum: + - nvidia,tegra132-vde + - nvidia,tegra124-vde + - nvidia,tegra114-vde + - items: + - const: nvidia,tegra30-vde + - const: nvidia,tegra20-vde + - items: + - const: nvidia,tegra20-vde + + reg: + maxItems: 9 + + reg-names: + items: + - const: sxe + - const: bsev + - const: mbe + - const: ppe + - const: mce + - const: tfe + - const: ppb + - const: vdma + - const: frameid + + clocks: + maxItems: 1 + + resets: + maxItems: 2 + + reset-names: + items: + - const: vde + - const: mc + + interrupts: + maxItems: 3 + + interrupt-names: + items: + - const: sync-token + - const: bsev + - const: sxe + + iommus: + maxItems: 1 + + iram: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle of the SRAM MMIO node. + +required: + - compatible + - reg + - reg-names + - clocks + - resets + - reset-names + - interrupts + - interrupt-names + +additionalProperties: false + +examples: + - | + video-codec@6001a000 { + compatible = "nvidia,tegra20-vde"; + reg = <0x6001a000 0x1000>, /* Syntax Engine */ + <0x6001b000 0x1000>, /* Video Bitstream Engine */ + <0x6001c000 0x100>, /* Macroblock Engine */ + <0x6001c200 0x100>, /* Post-processing Engine */ + <0x6001c400 0x100>, /* Motion Compensation Engine */ + <0x6001c600 0x100>, /* Transform Engine */ + <0x6001c800 0x100>, /* Pixel prediction block */ + <0x6001ca00 0x100>, /* Video DMA */ + <0x6001d800 0x300>; /* Video frame controls */ + reg-names = "sxe", "bsev", "mbe", "ppe", "mce", + "tfe", "ppb", "vdma", "frameid"; + iram = <&iram>; /* IRAM MMIO region */ + interrupts = <0 9 4>, /* Sync token */ + <0 10 4>, /* BSE-V */ + <0 12 4>; /* SXE */ + interrupt-names = "sync-token", "bsev", "sxe"; + clocks = <&clk 61>; + reset-names = "vde", "mc"; + resets = <&rst 61>, <&mem 13>; + iommus = <&mem 15>; + }; -- cgit v1.2.3-59-g8ed1b From c9059a6bb993db31cd85f3a4081766af9e61be40 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Wed, 1 Dec 2021 02:23:33 +0300 Subject: media: dt: bindings: tegra-vde: Document OPP and power domain Document new OPP table and power domain properties of the video decoder hardware. Reviewed-by: Rob Herring Acked-by: Hans Verkuil Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- .../devicetree/bindings/media/nvidia,tegra-vde.yaml | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/media/nvidia,tegra-vde.yaml b/Documentation/devicetree/bindings/media/nvidia,tegra-vde.yaml index c143aaa06346..4ecdee1be37e 100644 --- a/Documentation/devicetree/bindings/media/nvidia,tegra-vde.yaml +++ b/Documentation/devicetree/bindings/media/nvidia,tegra-vde.yaml @@ -68,6 +68,16 @@ properties: description: Phandle of the SRAM MMIO node. + operating-points-v2: + description: + Should contain freqs and voltages and opp-supported-hw property, + which is a bitfield indicating SoC speedo or process ID mask. + + power-domains: + maxItems: 1 + description: + Phandle to the SoC core power domain. + required: - compatible - reg @@ -104,4 +114,6 @@ examples: reset-names = "vde", "mc"; resets = <&rst 61>, <&mem 13>; iommus = <&mem 15>; + operating-points-v2 = <&dvfs_opp_table>; + power-domains = <&domain>; }; -- cgit v1.2.3-59-g8ed1b From eafba51c545a165b29777cde1fc8b04781a0a8db Mon Sep 17 00:00:00 2001 From: Stefan Wahren Date: Wed, 15 Dec 2021 10:44:49 +0100 Subject: dt-bindings: soc: bcm: Convert brcm,bcm2835-vchiq to json-schema This converts the VCHIQ bindings to YAML format. Signed-off-by: Stefan Wahren Co-developed-by: Nicolas Saenz Julienne Signed-off-by: Nicolas Saenz Julienne Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/20211215094448.280796-1-nsaenz@kernel.org --- .../bindings/soc/bcm/brcm,bcm2835-vchiq.txt | 17 ------- .../bindings/soc/bcm/brcm,bcm2835-vchiq.yaml | 53 ++++++++++++++++++++++ 2 files changed, 53 insertions(+), 17 deletions(-) delete mode 100644 Documentation/devicetree/bindings/soc/bcm/brcm,bcm2835-vchiq.txt create mode 100644 Documentation/devicetree/bindings/soc/bcm/brcm,bcm2835-vchiq.yaml (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/soc/bcm/brcm,bcm2835-vchiq.txt b/Documentation/devicetree/bindings/soc/bcm/brcm,bcm2835-vchiq.txt deleted file mode 100644 index f331316183f6..000000000000 --- a/Documentation/devicetree/bindings/soc/bcm/brcm,bcm2835-vchiq.txt +++ /dev/null @@ -1,17 +0,0 @@ -Broadcom VCHIQ firmware services - -Required properties: - -- compatible: Should be "brcm,bcm2835-vchiq" on BCM2835, otherwise - "brcm,bcm2836-vchiq". -- reg: Physical base address and length of the doorbell register pair -- interrupts: The interrupt number - See bindings/interrupt-controller/brcm,bcm2835-armctrl-ic.txt - -Example: - -mailbox@7e00b840 { - compatible = "brcm,bcm2835-vchiq"; - reg = <0x7e00b840 0xf>; - interrupts = <0 2>; -}; diff --git a/Documentation/devicetree/bindings/soc/bcm/brcm,bcm2835-vchiq.yaml b/Documentation/devicetree/bindings/soc/bcm/brcm,bcm2835-vchiq.yaml new file mode 100644 index 000000000000..e04439b3355b --- /dev/null +++ b/Documentation/devicetree/bindings/soc/bcm/brcm,bcm2835-vchiq.yaml @@ -0,0 +1,53 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/bcm/brcm,bcm2835-vchiq.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom VCHIQ firmware services + +maintainers: + - Nicolas Saenz Julienne + +description: + The VCHIQ communication channel can be provided by BCM283x and Capri SoCs, + to communicate with the VPU-side OS services. + +properties: + compatible: + oneOf: + - description: BCM2835 based boards + items: + - enum: + - brcm,bcm2835-vchiq + + - description: BCM2836/BCM2837 based boards + items: + - enum: + - brcm,bcm2836-vchiq + - const: brcm,bcm2835-vchiq + + reg: + description: Physical base address and length of the doorbell register pair + minItems: 1 + + interrupts: + description: Interrupt number of the doorbell interrupt + minItems: 1 + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + mailbox@7e00b840 { + compatible = "brcm,bcm2835-vchiq"; + reg = <0x7e00b840 0xf>; + interrupts = <0 2>; + }; + +... -- cgit v1.2.3-59-g8ed1b From 2d6a1c7d57723efcb23a345d0ea5a10d76350390 Mon Sep 17 00:00:00 2001 From: Sam Protsenko Date: Fri, 17 Dec 2021 18:15:45 +0200 Subject: dt-bindings: Add vendor prefix for WinLink WinLink Co., Ltd is a hardware design and manufacturing company based in South Korea. Official web-site: [1]. [1] http://win-link.net/ Signed-off-by: Sam Protsenko Acked-by: Rob Herring Link: https://lore.kernel.org/r/20211217161549.24836-4-semen.protsenko@linaro.org Signed-off-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index 66d6432fd781..95a847dfd29a 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -1318,6 +1318,8 @@ patternProperties: description: Wiligear, Ltd. "^winbond,.*": description: Winbond Electronics corp. + "^winlink,.*": + description: WinLink Co., Ltd "^winstar,.*": description: Winstar Display Corp. "^wits,.*": -- cgit v1.2.3-59-g8ed1b From e1ba2f940ba4c4c3b4d0a520301a920591c421f9 Mon Sep 17 00:00:00 2001 From: Sam Protsenko Date: Fri, 17 Dec 2021 18:15:46 +0200 Subject: dt-bindings: arm: samsung: Document E850-96 board binding Add binding for the WinLink E850-96 board, which is based on Samsung Exynos850 SoC. Signed-off-by: Sam Protsenko Link: https://lore.kernel.org/r/20211217161549.24836-5-semen.protsenko@linaro.org Signed-off-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml index d88571202713..052cd94113d4 100644 --- a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml +++ b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml @@ -205,6 +205,12 @@ properties: - samsung,jackpotlte # Samsung Galaxy A8 (2018) - const: samsung,exynos7885 + - description: Exynos850 based boards + items: + - enum: + - winlink,e850-96 # WinLink E850-96 + - const: samsung,exynos850 + - description: Exynos Auto v9 based boards items: - enum: -- cgit v1.2.3-59-g8ed1b From bc9fd597b3009d3412022c7beb3fbb01c9d27b31 Mon Sep 17 00:00:00 2001 From: Joel Stanley Date: Wed, 17 Nov 2021 11:51:04 +0800 Subject: dt-bindings: aspeed: Add Secure Boot Controller bindings The secure boot controller was first introduced in the AST2600. Signed-off-by: Joel Stanley Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/20211117035106.321454-2-joel@jms.id.au Signed-off-by: Joel Stanley --- .../devicetree/bindings/arm/aspeed/aspeed,sbc.yaml | 37 ++++++++++++++++++++++ 1 file changed, 37 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/aspeed/aspeed,sbc.yaml (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/arm/aspeed/aspeed,sbc.yaml b/Documentation/devicetree/bindings/arm/aspeed/aspeed,sbc.yaml new file mode 100644 index 000000000000..c72aab706484 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/aspeed/aspeed,sbc.yaml @@ -0,0 +1,37 @@ +# SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) +# Copyright 2021 Joel Stanley, IBM Corp. +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/arm/aspeed/aspeed,sbc.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: ASPEED Secure Boot Controller + +maintainers: + - Joel Stanley + - Andrew Jeffery + +description: | + The ASPEED SoCs have a register bank for interacting with the secure boot + controller. + +properties: + compatible: + items: + - const: aspeed,ast2600-sbc + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + sbc: secure-boot-controller@1e6f2000 { + compatible = "aspeed,ast2600-sbc"; + reg = <0x1e6f2000 0x1000>; + }; -- cgit v1.2.3-59-g8ed1b From 002c42d37e45ff5b5248576c77437ccafb651454 Mon Sep 17 00:00:00 2001 From: Jae Hyun Yoo Date: Mon, 8 Nov 2021 11:01:56 -0800 Subject: dt-bindings: ipmi: bt-bmc: add 'clocks' as a required property If LPC BT driver is registered ahead of lpc-ctrl module, LPC BT hardware block will be enabled without heart beating of LCLK until lpc-ctrl enables the LCLK. This issue causes improper handling on host interrupts when the host sends interrupts in that time frame. Then kernel eventually forcibly disables the interrupt with dumping stack and printing a 'nobody cared this irq' message out. To prevent this issue, all LPC sub drivers should enable LCLK individually so this patch adds 'clocks' property as one of required properties to enable the LCLK by the LPC IBT driver. Note: dtsi change in this patch series should be applied along with, and dtbs should be re-compiled after applying this series since it's adding a new required property otherwise the driver will not be probed correctly. Signed-off-by: Jae Hyun Yoo Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/20211108190200.290957-3-jae.hyun.yoo@intel.com Signed-off-by: Joel Stanley --- Documentation/devicetree/bindings/ipmi/aspeed,ast2400-ibt-bmc.txt | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/ipmi/aspeed,ast2400-ibt-bmc.txt b/Documentation/devicetree/bindings/ipmi/aspeed,ast2400-ibt-bmc.txt index c9902fd4b38b..25f86da804b7 100644 --- a/Documentation/devicetree/bindings/ipmi/aspeed,ast2400-ibt-bmc.txt +++ b/Documentation/devicetree/bindings/ipmi/aspeed,ast2400-ibt-bmc.txt @@ -11,6 +11,7 @@ Required properties: "aspeed,ast2500-ibt-bmc" "aspeed,ast2600-ibt-bmc" - reg: physical address and size of the registers +- clocks: clock for the device Optional properties: @@ -23,4 +24,5 @@ Example: compatible = "aspeed,ast2400-ibt-bmc"; reg = <0x1e789140 0x18>; interrupts = <8>; + clocks = <&syscon ASPEED_CLK_GATE_LCLK>; }; -- cgit v1.2.3-59-g8ed1b