From fb6a691a23ca4bcf10bbda603e22021776d51d56 Mon Sep 17 00:00:00 2001 From: Manish Narani Date: Thu, 25 Oct 2018 11:36:57 +0530 Subject: dt: bindings: Document ZynqMP DDRC in Synopsys documentation Add information for ZynqMP DDRC which reports the single bit errors that are corrected and the double bit errors that are detected. Signed-off-by: Manish Narani Signed-off-by: Borislav Petkov Reviewed-by: Rob Herring CC: Mark Rutland CC: amit.kucheria@linaro.org CC: devicetree@vger.kernel.org CC: leoyang.li@nxp.com CC: linux-arm-kernel@lists.infradead.org CC: linux-edac CC: mchehab@kernel.org CC: michal.simek@xilinx.com CC: sudeep.holla@arm.com Link: http://lkml.kernel.org/r/1540447621-22870-3-git-send-email-manish.narani@xilinx.com --- .../bindings/memory-controllers/synopsys.txt | 27 ++++++++++++++++++---- 1 file changed, 22 insertions(+), 5 deletions(-) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/memory-controllers/synopsys.txt b/Documentation/devicetree/bindings/memory-controllers/synopsys.txt index a43d26d41e04..9d32762c47e1 100644 --- a/Documentation/devicetree/bindings/memory-controllers/synopsys.txt +++ b/Documentation/devicetree/bindings/memory-controllers/synopsys.txt @@ -1,15 +1,32 @@ Binding for Synopsys IntelliDDR Multi Protocol Memory Controller -This controller has an optional ECC support in half-bus width (16-bit) -configuration. The ECC controller corrects one bit error and detects -two bit errors. +The ZynqMP DDR ECC controller has an optional ECC support in 64-bit and 32-bit +bus width configurations. + +The Zynq DDR ECC controller has an optional ECC support in half-bus width +(16-bit) configuration. + +These both ECC controllers correct single bit ECC errors and detect double bit +ECC errors. Required properties: - - compatible: Should be 'xlnx,zynq-ddrc-a05' - - reg: Base address and size of the controllers memory area + - compatible: One of: + - 'xlnx,zynq-ddrc-a05' : Zynq DDR ECC controller + - 'xlnx,zynqmp-ddrc-2.40a' : ZynqMP DDR ECC controller + - reg: Should contain DDR controller registers location and length. + +Required properties for "xlnx,zynqmp-ddrc-2.40a": + - interrupts: Property with a value describing the interrupt number. Example: memory-controller@f8006000 { compatible = "xlnx,zynq-ddrc-a05"; reg = <0xf8006000 0x1000>; }; + + mc: memory-controller@fd070000 { + compatible = "xlnx,zynqmp-ddrc-2.40a"; + reg = <0x0 0xfd070000 0x0 0x30000>; + interrupt-parent = <&gic>; + interrupts = <0 112 4>; + }; -- cgit v1.2.3-59-g8ed1b