From f72f4f1ae498a3c93c23c3d0e600df92977e86b1 Mon Sep 17 00:00:00 2001 From: Jonathan Marek Date: Tue, 4 Dec 2018 10:16:57 -0500 Subject: drm/msm/mdp4: add lcdc-align-lsb flag to control lane alignment This allows controlling which of the 8 lanes are used for 6 bit color. Signed-off-by: Jonathan Marek Reviewed-by: Rob Herring Signed-off-by: Rob Clark --- Documentation/devicetree/bindings/display/msm/mdp4.txt | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/display/msm/mdp4.txt b/Documentation/devicetree/bindings/display/msm/mdp4.txt index 3c341a15ccdc..b07eeb38f709 100644 --- a/Documentation/devicetree/bindings/display/msm/mdp4.txt +++ b/Documentation/devicetree/bindings/display/msm/mdp4.txt @@ -38,6 +38,8 @@ Required properties: Optional properties: - clock-names: the following clocks are optional: * "lut_clk" +- qcom,lcdc-align-lsb: Boolean value indicating that LSB alignment should be + used for LCDC. This is only valid for 18bpp panels. Example: -- cgit v1.2.3-59-g8ed1b From e888c279579e9c2409899eb3a5e9ad5b9f91260e Mon Sep 17 00:00:00 2001 From: Jonathan Marek Date: Tue, 4 Dec 2018 10:17:01 -0500 Subject: dt-bindings: display: msm/gpu: document amd,imageon compatible Document the new amd,imageon compatible, used for non-qcom hardware that uses the drm/msm driver (iMX5). Signed-off-by: Jonathan Marek Reviewed-by: Rob Herring Signed-off-by: Rob Clark --- Documentation/devicetree/bindings/display/msm/gpu.txt | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/display/msm/gpu.txt b/Documentation/devicetree/bindings/display/msm/gpu.txt index 43fac0fe09bb..ac8df3b871f9 100644 --- a/Documentation/devicetree/bindings/display/msm/gpu.txt +++ b/Documentation/devicetree/bindings/display/msm/gpu.txt @@ -1,11 +1,13 @@ Qualcomm adreno/snapdragon GPU Required properties: -- compatible: "qcom,adreno-XYZ.W", "qcom,adreno" +- compatible: "qcom,adreno-XYZ.W", "qcom,adreno" or + "amd,imageon-XYZ.W", "amd,imageon" for example: "qcom,adreno-306.0", "qcom,adreno" Note that you need to list the less specific "qcom,adreno" (since this is what the device is matched on), in addition to the more specific with the chip-id. + If "amd,imageon" is used, there should be no top level msm device. - reg: Physical base address and length of the controller's registers. - interrupts: The interrupt signal from the gpu. - clocks: device clocks -- cgit v1.2.3-59-g8ed1b From fb42b5354d71b09d3dcfcf4e38b1e98b277a0fc8 Mon Sep 17 00:00:00 2001 From: Matthias Kaehlcke Date: Tue, 4 Dec 2018 14:42:27 -0800 Subject: dt-bindings: msm/dsi: Add ref clock for PHYs Allow the PHY drivers to get the ref clock from the DT. Signed-off-by: Matthias Kaehlcke Reviewed-by: Stephen Boyd Reviewed-by: Douglas Anderson Reviewed-by: Rob Herring Signed-off-by: Rob Clark --- Documentation/devicetree/bindings/display/msm/dsi.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree/bindings') diff --git a/Documentation/devicetree/bindings/display/msm/dsi.txt b/Documentation/devicetree/bindings/display/msm/dsi.txt index dfc743219bd8..9ae946942720 100644 --- a/Documentation/devicetree/bindings/display/msm/dsi.txt +++ b/Documentation/devicetree/bindings/display/msm/dsi.txt @@ -106,6 +106,7 @@ Required properties: - clocks: Phandles to device clocks. See [1] for details on clock bindings. - clock-names: the following clocks are required: * "iface" + * "ref" (only required for new DTS files/entries) For 28nm HPM/LP, 28nm 8960 PHYs: - vddio-supply: phandle to vdd-io regulator device node For 20nm PHY: -- cgit v1.2.3-59-g8ed1b