From f611dfdb8544b5ac4228f4e3cb3b06ce15b9c74b Mon Sep 17 00:00:00 2001 From: Leilk Liu Date: Thu, 1 Nov 2018 14:02:18 +0800 Subject: spi: mediatek: Add bindings for mediatek MT8183 soc platform This patch adds a DT binding documentation for the MT8183 soc. Signed-off-by: Leilk Liu Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/spi/spi-mt65xx.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/spi/spi-mt65xx.txt b/Documentation/devicetree/bindings/spi/spi-mt65xx.txt index 236dcb0faf37..7940940b43e6 100644 --- a/Documentation/devicetree/bindings/spi/spi-mt65xx.txt +++ b/Documentation/devicetree/bindings/spi/spi-mt65xx.txt @@ -8,6 +8,7 @@ Required properties: - mediatek,mt7622-spi: for mt7622 platforms - mediatek,mt8135-spi: for mt8135 platforms - mediatek,mt8173-spi: for mt8173 platforms + - mediatek,mt8183-spi: for mt8183 platforms - #address-cells: should be 1. -- cgit v1.2.3-59-g8ed1b From 4642f0bede4f3e0e460ae0e52286df606832b291 Mon Sep 17 00:00:00 2001 From: Keiji Hayashibara Date: Fri, 26 Oct 2018 14:58:44 +0900 Subject: spi: uniphier: fix incorrect property items This commit fixes incorrect property because it was different from the actual. The parameters of '#address-cells' and '#size-cells' were removed, and 'interrupts', 'pinctrl-names' and 'pinctrl-0' were added. Fixes: 4dcd5c2781f3 ("spi: add DT bindings for UniPhier SPI controller") Signed-off-by: Keiji Hayashibara Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/spi/spi-uniphier.txt | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/spi/spi-uniphier.txt b/Documentation/devicetree/bindings/spi/spi-uniphier.txt index 504a4ecfc7b1..b04e66a52de5 100644 --- a/Documentation/devicetree/bindings/spi/spi-uniphier.txt +++ b/Documentation/devicetree/bindings/spi/spi-uniphier.txt @@ -5,18 +5,20 @@ UniPhier SoCs have SCSSI which supports SPI single channel. Required properties: - compatible: should be "socionext,uniphier-scssi" - reg: address and length of the spi master registers - - #address-cells: must be <1>, see spi-bus.txt - - #size-cells: must be <0>, see spi-bus.txt - - clocks: A phandle to the clock for the device. - - resets: A phandle to the reset control for the device. + - interrupts: a single interrupt specifier + - pinctrl-names: should be "default" + - pinctrl-0: pin control state for the default mode + - clocks: a phandle to the clock for the device + - resets: a phandle to the reset control for the device Example: spi0: spi@54006000 { compatible = "socionext,uniphier-scssi"; reg = <0x54006000 0x100>; - #address-cells = <1>; - #size-cells = <0>; + interrupts = <0 39 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi0>; clocks = <&peri_clk 11>; resets = <&peri_rst 11>; }; -- cgit v1.2.3-59-g8ed1b From 2a35a643f138a97e3bfee0c599c72e5ca80ebe7c Mon Sep 17 00:00:00 2001 From: Keiji Hayashibara Date: Fri, 26 Oct 2018 14:58:45 +0900 Subject: spi: uniphier: re-add addressing properties In commit 7662d1dc17d4 ("spi: uniphier: fix incorrect property items") addressing properties of #address-cells and #size-cells were removed. Since it is not necessary to remove them, they are back again. Signed-off-by: Keiji Hayashibara Reviewed-by: Rob Herring Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/spi/spi-uniphier.txt | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/spi/spi-uniphier.txt b/Documentation/devicetree/bindings/spi/spi-uniphier.txt index b04e66a52de5..e1201573a29a 100644 --- a/Documentation/devicetree/bindings/spi/spi-uniphier.txt +++ b/Documentation/devicetree/bindings/spi/spi-uniphier.txt @@ -5,6 +5,8 @@ UniPhier SoCs have SCSSI which supports SPI single channel. Required properties: - compatible: should be "socionext,uniphier-scssi" - reg: address and length of the spi master registers + - #address-cells: must be <1>, see spi-bus.txt + - #size-cells: must be <0>, see spi-bus.txt - interrupts: a single interrupt specifier - pinctrl-names: should be "default" - pinctrl-0: pin control state for the default mode @@ -16,6 +18,8 @@ Example: spi0: spi@54006000 { compatible = "socionext,uniphier-scssi"; reg = <0x54006000 0x100>; + #address-cells = <1>; + #size-cells = <0>; interrupts = <0 39 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi0>; -- cgit v1.2.3-59-g8ed1b From 326e5c8d4a87512ee329efc1b45029767ec710bb Mon Sep 17 00:00:00 2001 From: Mason Yang Date: Wed, 17 Oct 2018 10:08:12 +0800 Subject: dt-binding: spi: Document Macronix controller bindings Document the bindings used by the Macronix controller. Signed-off-by: Mason Yang Reviewed-by: Boris Brezillon Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/spi/spi-mxic.txt | 34 ++++++++++++++++++++++ 1 file changed, 34 insertions(+) create mode 100644 Documentation/devicetree/bindings/spi/spi-mxic.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/spi/spi-mxic.txt b/Documentation/devicetree/bindings/spi/spi-mxic.txt new file mode 100644 index 000000000000..529f2dab2648 --- /dev/null +++ b/Documentation/devicetree/bindings/spi/spi-mxic.txt @@ -0,0 +1,34 @@ +Macronix SPI controller Device Tree Bindings +-------------------------------------------- + +Required properties: +- compatible: should be "mxicy,mx25f0a-spi" +- #address-cells: should be 1 +- #size-cells: should be 0 +- reg: should contain 2 entries, one for the registers and one for the direct + mapping area +- reg-names: should contain "regs" and "dirmap" +- interrupts: interrupt line connected to the SPI controller +- clock-names: should contain "ps_clk", "send_clk" and "send_dly_clk" +- clocks: should contain 3 entries for the "ps_clk", "send_clk" and + "send_dly_clk" clocks + +Example: + + spi@43c30000 { + compatible = "mxicy,mx25f0a-spi"; + reg = <0x43c30000 0x10000>, <0xa0000000 0x20000000>; + reg-names = "regs", "dirmap"; + clocks = <&clkwizard 0>, <&clkwizard 1>, <&clkc 18>; + clock-names = "send_clk", "send_dly_clk", "ps_clk"; + #address-cells = <1>; + #size-cells = <0>; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <25000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; + }; -- cgit v1.2.3-59-g8ed1b From a24626d72915fef2b38bb8467b3714f17efae6c0 Mon Sep 17 00:00:00 2001 From: Piotr Bugalski Date: Mon, 5 Nov 2018 11:36:25 +0100 Subject: dt-bindings: spi: QuadSPI driver for Atmel SAMA5D2 Atmel SAMA5D2 QuadSPI driver was moved from mtd to spi subsystem, this change is just moving DT-binding documentation. Suggested-by: Boris Brezillon Signed-off-by: Piotr Bugalski Reviewed-by: Rob Herring Signed-off-by: Mark Brown --- .../devicetree/bindings/mtd/atmel-quadspi.txt | 31 ---------------------- .../devicetree/bindings/spi/atmel-quadspi.txt | 31 ++++++++++++++++++++++ 2 files changed, 31 insertions(+), 31 deletions(-) delete mode 100644 Documentation/devicetree/bindings/mtd/atmel-quadspi.txt create mode 100644 Documentation/devicetree/bindings/spi/atmel-quadspi.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/mtd/atmel-quadspi.txt b/Documentation/devicetree/bindings/mtd/atmel-quadspi.txt deleted file mode 100644 index b93c1e2f25dd..000000000000 --- a/Documentation/devicetree/bindings/mtd/atmel-quadspi.txt +++ /dev/null @@ -1,31 +0,0 @@ -* Atmel Quad Serial Peripheral Interface (QSPI) - -Required properties: -- compatible: Should be "atmel,sama5d2-qspi". -- reg: Should contain the locations and lengths of the base registers - and the mapped memory. -- reg-names: Should contain the resource reg names: - - qspi_base: configuration register address space - - qspi_mmap: memory mapped address space -- interrupts: Should contain the interrupt for the device. -- clocks: The phandle of the clock needed by the QSPI controller. -- #address-cells: Should be <1>. -- #size-cells: Should be <0>. - -Example: - -spi@f0020000 { - compatible = "atmel,sama5d2-qspi"; - reg = <0xf0020000 0x100>, <0xd0000000 0x8000000>; - reg-names = "qspi_base", "qspi_mmap"; - interrupts = <52 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&spi0_clk>; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi0_default>; - - m25p80@0 { - ... - }; -}; diff --git a/Documentation/devicetree/bindings/spi/atmel-quadspi.txt b/Documentation/devicetree/bindings/spi/atmel-quadspi.txt new file mode 100644 index 000000000000..b93c1e2f25dd --- /dev/null +++ b/Documentation/devicetree/bindings/spi/atmel-quadspi.txt @@ -0,0 +1,31 @@ +* Atmel Quad Serial Peripheral Interface (QSPI) + +Required properties: +- compatible: Should be "atmel,sama5d2-qspi". +- reg: Should contain the locations and lengths of the base registers + and the mapped memory. +- reg-names: Should contain the resource reg names: + - qspi_base: configuration register address space + - qspi_mmap: memory mapped address space +- interrupts: Should contain the interrupt for the device. +- clocks: The phandle of the clock needed by the QSPI controller. +- #address-cells: Should be <1>. +- #size-cells: Should be <0>. + +Example: + +spi@f0020000 { + compatible = "atmel,sama5d2-qspi"; + reg = <0xf0020000 0x100>, <0xd0000000 0x8000000>; + reg-names = "qspi_base", "qspi_mmap"; + interrupts = <52 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&spi0_clk>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi0_default>; + + m25p80@0 { + ... + }; +}; -- cgit v1.2.3-59-g8ed1b From abc61f47a70f7c8331f00eff1ccb6557a9d4c224 Mon Sep 17 00:00:00 2001 From: Vignesh R Date: Wed, 7 Nov 2018 16:09:25 +0530 Subject: spi: omap-spi: Add compatible for AM654 SoC AM654 SoC has same McSPI IP as OMAP2+ platforms. Add new compatible to support McSPI on AM654 SoC. Signed-off-by: Vignesh R Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/spi/omap-spi.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/spi/omap-spi.txt b/Documentation/devicetree/bindings/spi/omap-spi.txt index 2ba5f9c023ac..487208c256c0 100644 --- a/Documentation/devicetree/bindings/spi/omap-spi.txt +++ b/Documentation/devicetree/bindings/spi/omap-spi.txt @@ -2,6 +2,7 @@ OMAP2+ McSPI device Required properties: - compatible : + - "ti,am654-mcspi" for AM654. - "ti,omap2-mcspi" for OMAP2 & OMAP3. - "ti,omap4-mcspi" for OMAP4+. - ti,spi-num-cs : Number of chipselect supported by the instance. -- cgit v1.2.3-59-g8ed1b From df80e0478972260bf285c5ed33f99b2424fba2af Mon Sep 17 00:00:00 2001 From: Fabrizio Castro Date: Thu, 1 Nov 2018 12:35:02 +0000 Subject: spi: rspi: Add r8a77470 to the compatible list Add r8a77470 to the list of examples with soctypes. No driver change is needed as "renesas,qspi" will activate the right code within the corresponding driver. Signed-off-by: Fabrizio Castro Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/spi/spi-rspi.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/spi/spi-rspi.txt b/Documentation/devicetree/bindings/spi/spi-rspi.txt index fc97ad64fbf2..421722b93992 100644 --- a/Documentation/devicetree/bindings/spi/spi-rspi.txt +++ b/Documentation/devicetree/bindings/spi/spi-rspi.txt @@ -15,6 +15,7 @@ Required properties: - "renesas,qspi-r8a7743" (RZ/G1M) - "renesas,qspi-r8a7744" (RZ/G1N) - "renesas,qspi-r8a7745" (RZ/G1E) + - "renesas,qspi-r8a77470" (RZ/G1C) - "renesas,qspi-r8a7790" (R-Car H2) - "renesas,qspi-r8a7791" (R-Car M2-W) - "renesas,qspi-r8a7792" (R-Car V2H) -- cgit v1.2.3-59-g8ed1b From aa66478aa538f839a96c836bba0bbc12ef2666f0 Mon Sep 17 00:00:00 2001 From: Lubomir Rintel Date: Tue, 13 Nov 2018 11:22:23 +0100 Subject: spi: pxa2xx: dt-bindings: Add spi-slave property This is used to indicate that the chip attached to this controller is a SPI master. Signed-off-by: Lubomir Rintel Reviewed-by: Rob Herring Acked-by: Pavel Machek Reviewed-by: Geert Uytterhoeven Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/spi/spi-pxa2xx.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/spi/spi-pxa2xx.txt b/Documentation/devicetree/bindings/spi/spi-pxa2xx.txt index 0335a9bd2e8a..89b2832283e3 100644 --- a/Documentation/devicetree/bindings/spi/spi-pxa2xx.txt +++ b/Documentation/devicetree/bindings/spi/spi-pxa2xx.txt @@ -11,6 +11,7 @@ Required properties: Optional properties: - cs-gpios: list of GPIO chip selects. See the SPI bus bindings, Documentation/devicetree/bindings/spi/spi-bus.txt +- spi-slave: Empty property indicating the SPI controller is used in slave mode. Child nodes represent devices on the SPI bus See ../spi/spi-bus.txt -- cgit v1.2.3-59-g8ed1b From 8ae13d0b0d4bb4af99bec8c50152f0c8f5cbcc06 Mon Sep 17 00:00:00 2001 From: Lubomir Rintel Date: Tue, 13 Nov 2018 11:22:26 +0100 Subject: spi: pxa2xx: dt-bindings: Add ready GPIO signal This this is used to let the SPI master know that our FIFO is filled and we're ready to service a transfer. Only useful in slave mode. A signal like this is used by an embedded controller on a OLPC XO 1.75 machine, that happens to be a SPI master. Signed-off-by: Lubomir Rintel Acked-by: Pavel Machek Reviewed-by: Geert Uytterhoeven Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/spi/spi-pxa2xx.txt | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/spi/spi-pxa2xx.txt b/Documentation/devicetree/bindings/spi/spi-pxa2xx.txt index 89b2832283e3..e30e0c2a4bce 100644 --- a/Documentation/devicetree/bindings/spi/spi-pxa2xx.txt +++ b/Documentation/devicetree/bindings/spi/spi-pxa2xx.txt @@ -12,6 +12,8 @@ Optional properties: - cs-gpios: list of GPIO chip selects. See the SPI bus bindings, Documentation/devicetree/bindings/spi/spi-bus.txt - spi-slave: Empty property indicating the SPI controller is used in slave mode. +- ready-gpios: GPIO used to signal a SPI master that the FIFO is filled + and we're ready to service a transfer. Only useful in slave mode. Child nodes represent devices on the SPI bus See ../spi/spi-bus.txt -- cgit v1.2.3-59-g8ed1b From 4ad26864df53b265976c4a3ae61b1e6cad92fe40 Mon Sep 17 00:00:00 2001 From: Tomer Maimon Date: Mon, 12 Nov 2018 18:42:31 +0200 Subject: dt-binding: spi: add NPCM PSPI controller documentation Added device tree binding documentation for Nuvoton BMC NPCM Peripheral SPI controller. Signed-off-by: Tomer Maimon Signed-off-by: Mark Brown --- .../devicetree/bindings/spi/nuvoton,npcm-pspi.txt | 35 ++++++++++++++++++++++ 1 file changed, 35 insertions(+) create mode 100644 Documentation/devicetree/bindings/spi/nuvoton,npcm-pspi.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/spi/nuvoton,npcm-pspi.txt b/Documentation/devicetree/bindings/spi/nuvoton,npcm-pspi.txt new file mode 100644 index 000000000000..99606b22e5c2 --- /dev/null +++ b/Documentation/devicetree/bindings/spi/nuvoton,npcm-pspi.txt @@ -0,0 +1,35 @@ +Nuvoton NPCM Peripheral Serial Peripheral Interface(PSPI) controller driver + +Nuvoton NPCM7xx SOC support two PSPI channels. + +Required properties: + - compatible : "nuvoton,npcm750-pspi" for NPCM7XX BMC + - #address-cells : should be 1. see spi-bus.txt + - #size-cells : should be 0. see spi-bus.txt + - specifies physical base address and size of the register. + - interrupts : contain PSPI interrupt. + - clocks : phandle of PSPI reference clock. + - clock-names: Should be "clk_apb5". + - pinctrl-names : a pinctrl state named "default" must be defined. + - pinctrl-0 : phandle referencing pin configuration of the device. + - cs-gpios: Specifies the gpio pins to be used for chipselects. + See: Documentation/devicetree/bindings/spi/spi-bus.txt + +Optional properties: +- clock-frequency : Input clock frequency to the PSPI block in Hz. + Default is 25000000 Hz. + +Example: + +spi0: spi@f0200000 { + compatible = "nuvoton,npcm750-pspi"; + reg = <0xf0200000 0x1000>; + pinctrl-names = "default"; + pinctrl-0 = <&pspi1_pins>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&clk NPCM7XX_CLK_APB5>; + clock-names = "clk_apb5"; + cs-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>; +}; -- cgit v1.2.3-59-g8ed1b From a1880d38674b1b7e120a231151298b2eb530b645 Mon Sep 17 00:00:00 2001 From: Leilk Liu Date: Tue, 27 Nov 2018 10:29:50 +0800 Subject: spi: mediatek: Add bindings for mediatek MT7629 soc platform This patch adds a DT binding documentation for the MT7629 soc. Signed-off-by: Leilk Liu Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/spi/spi-mt65xx.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/spi/spi-mt65xx.txt b/Documentation/devicetree/bindings/spi/spi-mt65xx.txt index 7940940b43e6..69c356767cf8 100644 --- a/Documentation/devicetree/bindings/spi/spi-mt65xx.txt +++ b/Documentation/devicetree/bindings/spi/spi-mt65xx.txt @@ -6,6 +6,7 @@ Required properties: - mediatek,mt2712-spi: for mt2712 platforms - mediatek,mt6589-spi: for mt6589 platforms - mediatek,mt7622-spi: for mt7622 platforms + - "mediatek,mt7629-spi", "mediatek,mt7622-spi": for mt7629 platforms - mediatek,mt8135-spi: for mt8135 platforms - mediatek,mt8173-spi: for mt8173 platforms - mediatek,mt8183-spi: for mt8183 platforms -- cgit v1.2.3-59-g8ed1b From 6ab4a3502923c20c5a6921868e787e5fd033409b Mon Sep 17 00:00:00 2001 From: Tomer Maimon Date: Tue, 4 Dec 2018 15:54:42 +0200 Subject: spi: Update NPCM PSPI controller documentation Update the PSPI NPCM binding document of the spi aliases use to define the spi ID number. Signed-off-by: Tomer Maimon Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/spi/nuvoton,npcm-pspi.txt | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/spi/nuvoton,npcm-pspi.txt b/Documentation/devicetree/bindings/spi/nuvoton,npcm-pspi.txt index 99606b22e5c2..1fd9a4406a1d 100644 --- a/Documentation/devicetree/bindings/spi/nuvoton,npcm-pspi.txt +++ b/Documentation/devicetree/bindings/spi/nuvoton,npcm-pspi.txt @@ -19,8 +19,16 @@ Optional properties: - clock-frequency : Input clock frequency to the PSPI block in Hz. Default is 25000000 Hz. +Aliases: +- All the SPI controller nodes should be represented in the aliases node using + the following format 'spi{n}' withe the correct numbered in "aliases" node. + Example: +aliases { + spi0 = &spi0; +}; + spi0: spi@f0200000 { compatible = "nuvoton,npcm750-pspi"; reg = <0xf0200000 0x1000>; -- cgit v1.2.3-59-g8ed1b From 62f82df488ce16f7068c7285820b2b7f7dcd7597 Mon Sep 17 00:00:00 2001 From: Clark Wang Date: Fri, 7 Dec 2018 02:50:41 +0000 Subject: doc: lpspi: Document DT bindings for LPSPI slave mode Add introductions of interrupt-parent and spi-slave. Signed-off-by: Clark Wang Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/spi/spi-fsl-lpspi.txt | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/spi/spi-fsl-lpspi.txt b/Documentation/devicetree/bindings/spi/spi-fsl-lpspi.txt index 8d178a4503cf..6cc3c6fe25a3 100644 --- a/Documentation/devicetree/bindings/spi/spi-fsl-lpspi.txt +++ b/Documentation/devicetree/bindings/spi/spi-fsl-lpspi.txt @@ -5,8 +5,11 @@ Required properties: - "fsl,imx7ulp-spi" for LPSPI compatible with the one integrated on i.MX7ULP soc - "fsl,imx8qxp-spi" for LPSPI compatible with the one integrated on i.MX8QXP soc - reg : address and length of the lpspi master registers +- interrupt-parent : core interrupt controller - interrupts : lpspi interrupt - clocks : lpspi clock specifier +- spi-slave : spi slave mode support. In slave mode, add this attribute without + value. In master mode, remove it. Examples: @@ -16,4 +19,5 @@ lpspi2: lpspi@40290000 { interrupt-parent = <&intc>; interrupts = ; clocks = <&clks IMX7ULP_CLK_LPSPI2>; + spi-slave; }; -- cgit v1.2.3-59-g8ed1b From 079e7f8709bb41cd0dc13efaffb24a0f17841955 Mon Sep 17 00:00:00 2001 From: Fabrizio Castro Date: Thu, 13 Dec 2018 20:19:57 +0000 Subject: spi: sh-msiof: Add r8a774c0 support Document RZ/G2E (R8A774C0) SoC bindings. Signed-off-by: Fabrizio Castro Reviewed-by: Geert Uytterhoeven Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/spi/sh-msiof.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/spi/sh-msiof.txt b/Documentation/devicetree/bindings/spi/sh-msiof.txt index 4b836ad17b19..37cf69586d10 100644 --- a/Documentation/devicetree/bindings/spi/sh-msiof.txt +++ b/Documentation/devicetree/bindings/spi/sh-msiof.txt @@ -5,6 +5,7 @@ Required properties: "renesas,msiof-r8a7744" (RZ/G1N) "renesas,msiof-r8a7745" (RZ/G1E) "renesas,msiof-r8a774a1" (RZ/G2M) + "renesas,msiof-r8a774c0" (RZ/G2E) "renesas,msiof-r8a7790" (R-Car H2) "renesas,msiof-r8a7791" (R-Car M2-W) "renesas,msiof-r8a7792" (R-Car V2H) -- cgit v1.2.3-59-g8ed1b