From 9909bc43a2e218a5a71a6245c36d86e4f587c74b Mon Sep 17 00:00:00 2001 From: "周琰杰 (Zhou Yanjie)" Date: Wed, 3 Jun 2020 02:33:54 +0800 Subject: dt-bindings: MIPS: Document Ingenic SoCs binding. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Document the available properties for the SoC root node and the CPU nodes of the devicetree for the Ingenic XBurst SoCs. Tested-by: H. Nikolaus Schaller Tested-by: Paul Boddie Signed-off-by: 周琰杰 (Zhou Yanjie) Reviewed-by: Rob Herring Signed-off-by: Thomas Bogendoerfer --- .../bindings/mips/ingenic/ingenic,cpu.yaml | 67 ++++++++++++++++++++++ 1 file changed, 67 insertions(+) create mode 100644 Documentation/devicetree/bindings/mips/ingenic/ingenic,cpu.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/mips/ingenic/ingenic,cpu.yaml b/Documentation/devicetree/bindings/mips/ingenic/ingenic,cpu.yaml new file mode 100644 index 000000000000..ee3423bfc56e --- /dev/null +++ b/Documentation/devicetree/bindings/mips/ingenic/ingenic,cpu.yaml @@ -0,0 +1,67 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mips/ingenic/ingenic,cpu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Bindings for Ingenic XBurst family CPUs + +maintainers: + - 周琰杰 (Zhou Yanjie) + +description: + Ingenic XBurst family CPUs shall have the following properties. + +properties: + compatible: + oneOf: + + - description: Ingenic XBurst®1 CPU Cores + enum: + - ingenic,xburst-mxu1.0 + - ingenic,xburst-fpu1.0-mxu1.1 + - ingenic,xburst-fpu2.0-mxu2.0 + + - description: Ingenic XBurst®2 CPU Cores + enum: + - ingenic,xburst2-fpu2.1-mxu2.1-smt + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + +required: + - device_type + - compatible + - reg + - clocks + +examples: + - | + #include + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "ingenic,xburst-fpu1.0-mxu1.1"; + reg = <0>; + + clocks = <&cgu JZ4780_CLK_CPU>; + clock-names = "cpu"; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "ingenic,xburst-fpu1.0-mxu1.1"; + reg = <1>; + + clocks = <&cgu JZ4780_CLK_CORE1>; + clock-names = "cpu"; + }; + }; +... -- cgit v1.2.3-59-g8ed1b From d23c9e06580fb414b7a223a50ac05474cc1414d9 Mon Sep 17 00:00:00 2001 From: Thomas Bogendoerfer Date: Thu, 2 Jul 2020 12:05:33 +0200 Subject: dt-bindings: MIPS: Fix tabs in Ingenic SoCs binding. While applying commit 9909bc43a2e2 ("dt-bindings: MIPS: Document Ingenic SoCs binding.") I've messed up by "fixing" indentation in a C style, which is wrong for yaml files. Replace tabs back to spaces. Fixes: 9909bc43a2e2 ("dt-bindings: MIPS: Document Ingenic SoCs binding.") Signed-off-by: Thomas Bogendoerfer --- .../bindings/mips/ingenic/ingenic,cpu.yaml | 32 +++++++++++----------- 1 file changed, 16 insertions(+), 16 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/mips/ingenic/ingenic,cpu.yaml b/Documentation/devicetree/bindings/mips/ingenic/ingenic,cpu.yaml index ee3423bfc56e..16fa03d65ad5 100644 --- a/Documentation/devicetree/bindings/mips/ingenic/ingenic,cpu.yaml +++ b/Documentation/devicetree/bindings/mips/ingenic/ingenic,cpu.yaml @@ -43,25 +43,25 @@ examples: #include cpus { - #address-cells = <1>; - #size-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "ingenic,xburst-fpu1.0-mxu1.1"; - reg = <0>; + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "ingenic,xburst-fpu1.0-mxu1.1"; + reg = <0>; - clocks = <&cgu JZ4780_CLK_CPU>; - clock-names = "cpu"; - }; + clocks = <&cgu JZ4780_CLK_CPU>; + clock-names = "cpu"; + }; - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "ingenic,xburst-fpu1.0-mxu1.1"; - reg = <1>; + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "ingenic,xburst-fpu1.0-mxu1.1"; + reg = <1>; - clocks = <&cgu JZ4780_CLK_CORE1>; - clock-names = "cpu"; - }; + clocks = <&cgu JZ4780_CLK_CORE1>; + clock-names = "cpu"; + }; }; ... -- cgit v1.2.3-59-g8ed1b From f8523d0e83613ab8d082cd504dc53a09fbba4889 Mon Sep 17 00:00:00 2001 From: Huacai Chen Date: Mon, 15 Jun 2020 14:04:16 +0800 Subject: MIPS: Loongson: Rename CPU device-tree binding Loongson-3A R1/R2/R3 and Loongson-3B R1/R2 use the same package naming in dts, and Loongson-3A R4 will be different. In cpu.h the classic 64bit Loongson processors are called Loongson64C (C for classic, pre Loongson- 3A R4), and the new 64bit Loongson processors are called Loongson64G (G for generic, Loongson-3A R4+). To keep consistency and make extensible, we rename the classic "loongson3" prefix to "loongson64c", and the new prefix for Loongson-3A R4+ will be "loongson64g". Signed-off-by: Huacai Chen Signed-off-by: Thomas Bogendoerfer --- .../devicetree/bindings/mips/loongson/devices.yaml | 8 +-- arch/mips/boot/dts/loongson/Makefile | 2 +- arch/mips/boot/dts/loongson/loongson3-package.dtsi | 64 ---------------------- .../boot/dts/loongson/loongson3_4core_rs780e.dts | 25 --------- .../boot/dts/loongson/loongson3_8core_rs780e.dts | 25 --------- .../boot/dts/loongson/loongson64c-package.dtsi | 64 ++++++++++++++++++++++ .../boot/dts/loongson/loongson64c_4core_rs780e.dts | 25 +++++++++ .../boot/dts/loongson/loongson64c_8core_rs780e.dts | 25 +++++++++ .../include/asm/mach-loongson64/builtin_dtbs.h | 4 +- arch/mips/loongson64/env.c | 4 +- 10 files changed, 123 insertions(+), 123 deletions(-) delete mode 100644 arch/mips/boot/dts/loongson/loongson3-package.dtsi delete mode 100644 arch/mips/boot/dts/loongson/loongson3_4core_rs780e.dts delete mode 100644 arch/mips/boot/dts/loongson/loongson3_8core_rs780e.dts create mode 100644 arch/mips/boot/dts/loongson/loongson64c-package.dtsi create mode 100644 arch/mips/boot/dts/loongson/loongson64c_4core_rs780e.dts create mode 100644 arch/mips/boot/dts/loongson/loongson64c_8core_rs780e.dts (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/mips/loongson/devices.yaml b/Documentation/devicetree/bindings/mips/loongson/devices.yaml index 74ed4e397a78..0516fe2b2897 100644 --- a/Documentation/devicetree/bindings/mips/loongson/devices.yaml +++ b/Documentation/devicetree/bindings/mips/loongson/devices.yaml @@ -17,11 +17,11 @@ properties: compatible: oneOf: - - description: Generic Loongson3 Quad Core + RS780E + - description: Classic Loongson64 Quad Core + RS780E items: - - const: loongson,loongson3-4core-rs780e + - const: loongson,loongson64c-4core-rs780e - - description: Generic Loongson3 Octa Core + RS780E + - description: Classic Loongson64 Octa Core + RS780E items: - - const: loongson,loongson3-8core-rs780e + - const: loongson,loongson64c-8core-rs780e ... diff --git a/arch/mips/boot/dts/loongson/Makefile b/arch/mips/boot/dts/loongson/Makefile index 56d379471262..aa5069a05da9 100644 --- a/arch/mips/boot/dts/loongson/Makefile +++ b/arch/mips/boot/dts/loongson/Makefile @@ -1,4 +1,4 @@ # SPDX_License_Identifier: GPL_2.0 -dtb-$(CONFIG_MACH_LOONGSON64) += loongson3_4core_rs780e.dtb loongson3_8core_rs780e.dtb +dtb-$(CONFIG_MACH_LOONGSON64) += loongson64c_4core_rs780e.dtb loongson64c_8core_rs780e.dtb obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y)) diff --git a/arch/mips/boot/dts/loongson/loongson3-package.dtsi b/arch/mips/boot/dts/loongson/loongson3-package.dtsi deleted file mode 100644 index 5bb876a4de52..000000000000 --- a/arch/mips/boot/dts/loongson/loongson3-package.dtsi +++ /dev/null @@ -1,64 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 - -#include - -/ { - #address-cells = <2>; - #size-cells = <2>; - - cpuintc: interrupt-controller { - #address-cells = <0>; - #interrupt-cells = <1>; - interrupt-controller; - compatible = "mti,cpu-interrupt-controller"; - }; - - package0: bus@1fe00000 { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <1>; - ranges = <0 0x1fe00000 0 0x1fe00000 0x100000 - 0 0x3ff00000 0 0x3ff00000 0x100000 - /* 3A HT Config Space */ - 0xefd 0xfb000000 0xefd 0xfb000000 0x10000000 - /* 3B HT Config Space */ - 0x1efd 0xfb000000 0x1efd 0xfb000000 0x10000000>; - - liointc: interrupt-controller@3ff01400 { - compatible = "loongson,liointc-1.0"; - reg = <0 0x3ff01400 0x64>; - - interrupt-controller; - #interrupt-cells = <2>; - - interrupt-parent = <&cpuintc>; - interrupts = <2>, <3>; - interrupt-names = "int0", "int1"; - - loongson,parent_int_map = <0xf0ffffff>, /* int0 */ - <0x0f000000>, /* int1 */ - <0x00000000>, /* int2 */ - <0x00000000>; /* int3 */ - - }; - - cpu_uart0: serial@1fe001e0 { - compatible = "ns16550a"; - reg = <0 0x1fe001e0 0x8>; - clock-frequency = <33000000>; - interrupt-parent = <&liointc>; - interrupts = <10 IRQ_TYPE_LEVEL_HIGH>; - no-loopback-test; - }; - - cpu_uart1: serial@1fe001e8 { - status = "disabled"; - compatible = "ns16550a"; - reg = <0 0x1fe001e8 0x8>; - clock-frequency = <33000000>; - interrupts = <10 IRQ_TYPE_LEVEL_HIGH>; - interrupt-parent = <&liointc>; - no-loopback-test; - }; - }; -}; diff --git a/arch/mips/boot/dts/loongson/loongson3_4core_rs780e.dts b/arch/mips/boot/dts/loongson/loongson3_4core_rs780e.dts deleted file mode 100644 index 6b5694ca0f95..000000000000 --- a/arch/mips/boot/dts/loongson/loongson3_4core_rs780e.dts +++ /dev/null @@ -1,25 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 - -/dts-v1/; - -#include "loongson3-package.dtsi" -#include "rs780e-pch.dtsi" - -/ { - compatible = "loongson,loongson3-4core-rs780e"; -}; - -&package0 { - htpic: interrupt-controller@efdfb000080 { - compatible = "loongson,htpic-1.0"; - reg = <0xefd 0xfb000080 0x40>; - interrupt-controller; - #interrupt-cells = <1>; - - interrupt-parent = <&liointc>; - interrupts = <24 IRQ_TYPE_LEVEL_HIGH>, - <25 IRQ_TYPE_LEVEL_HIGH>, - <26 IRQ_TYPE_LEVEL_HIGH>, - <27 IRQ_TYPE_LEVEL_HIGH>; - }; -}; diff --git a/arch/mips/boot/dts/loongson/loongson3_8core_rs780e.dts b/arch/mips/boot/dts/loongson/loongson3_8core_rs780e.dts deleted file mode 100644 index ffefa2f829b0..000000000000 --- a/arch/mips/boot/dts/loongson/loongson3_8core_rs780e.dts +++ /dev/null @@ -1,25 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 - -/dts-v1/; - -#include "loongson3-package.dtsi" -#include "rs780e-pch.dtsi" - -/ { - compatible = "loongson,loongson3-8core-rs780e"; -}; - -&package0 { - htpic: interrupt-controller@1efdfb000080 { - compatible = "loongson,htpic-1.0"; - reg = <0x1efd 0xfb000080 0x40>; - interrupt-controller; - #interrupt-cells = <1>; - - interrupt-parent = <&liointc>; - interrupts = <24 IRQ_TYPE_LEVEL_HIGH>, - <25 IRQ_TYPE_LEVEL_HIGH>, - <26 IRQ_TYPE_LEVEL_HIGH>, - <27 IRQ_TYPE_LEVEL_HIGH>; - }; -}; diff --git a/arch/mips/boot/dts/loongson/loongson64c-package.dtsi b/arch/mips/boot/dts/loongson/loongson64c-package.dtsi new file mode 100644 index 000000000000..5bb876a4de52 --- /dev/null +++ b/arch/mips/boot/dts/loongson/loongson64c-package.dtsi @@ -0,0 +1,64 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include + +/ { + #address-cells = <2>; + #size-cells = <2>; + + cpuintc: interrupt-controller { + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + compatible = "mti,cpu-interrupt-controller"; + }; + + package0: bus@1fe00000 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <1>; + ranges = <0 0x1fe00000 0 0x1fe00000 0x100000 + 0 0x3ff00000 0 0x3ff00000 0x100000 + /* 3A HT Config Space */ + 0xefd 0xfb000000 0xefd 0xfb000000 0x10000000 + /* 3B HT Config Space */ + 0x1efd 0xfb000000 0x1efd 0xfb000000 0x10000000>; + + liointc: interrupt-controller@3ff01400 { + compatible = "loongson,liointc-1.0"; + reg = <0 0x3ff01400 0x64>; + + interrupt-controller; + #interrupt-cells = <2>; + + interrupt-parent = <&cpuintc>; + interrupts = <2>, <3>; + interrupt-names = "int0", "int1"; + + loongson,parent_int_map = <0xf0ffffff>, /* int0 */ + <0x0f000000>, /* int1 */ + <0x00000000>, /* int2 */ + <0x00000000>; /* int3 */ + + }; + + cpu_uart0: serial@1fe001e0 { + compatible = "ns16550a"; + reg = <0 0x1fe001e0 0x8>; + clock-frequency = <33000000>; + interrupt-parent = <&liointc>; + interrupts = <10 IRQ_TYPE_LEVEL_HIGH>; + no-loopback-test; + }; + + cpu_uart1: serial@1fe001e8 { + status = "disabled"; + compatible = "ns16550a"; + reg = <0 0x1fe001e8 0x8>; + clock-frequency = <33000000>; + interrupts = <10 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&liointc>; + no-loopback-test; + }; + }; +}; diff --git a/arch/mips/boot/dts/loongson/loongson64c_4core_rs780e.dts b/arch/mips/boot/dts/loongson/loongson64c_4core_rs780e.dts new file mode 100644 index 000000000000..acd53a13cc7a --- /dev/null +++ b/arch/mips/boot/dts/loongson/loongson64c_4core_rs780e.dts @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0 + +/dts-v1/; + +#include "loongson64c-package.dtsi" +#include "rs780e-pch.dtsi" + +/ { + compatible = "loongson,loongson3-4core-rs780e"; +}; + +&package0 { + htpic: interrupt-controller@efdfb000080 { + compatible = "loongson,htpic-1.0"; + reg = <0xefd 0xfb000080 0x40>; + interrupt-controller; + #interrupt-cells = <1>; + + interrupt-parent = <&liointc>; + interrupts = <24 IRQ_TYPE_LEVEL_HIGH>, + <25 IRQ_TYPE_LEVEL_HIGH>, + <26 IRQ_TYPE_LEVEL_HIGH>, + <27 IRQ_TYPE_LEVEL_HIGH>; + }; +}; diff --git a/arch/mips/boot/dts/loongson/loongson64c_8core_rs780e.dts b/arch/mips/boot/dts/loongson/loongson64c_8core_rs780e.dts new file mode 100644 index 000000000000..433f9c3d01b8 --- /dev/null +++ b/arch/mips/boot/dts/loongson/loongson64c_8core_rs780e.dts @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0 + +/dts-v1/; + +#include "loongson64c-package.dtsi" +#include "rs780e-pch.dtsi" + +/ { + compatible = "loongson,loongson3-8core-rs780e"; +}; + +&package0 { + htpic: interrupt-controller@1efdfb000080 { + compatible = "loongson,htpic-1.0"; + reg = <0x1efd 0xfb000080 0x40>; + interrupt-controller; + #interrupt-cells = <1>; + + interrupt-parent = <&liointc>; + interrupts = <24 IRQ_TYPE_LEVEL_HIGH>, + <25 IRQ_TYPE_LEVEL_HIGH>, + <26 IRQ_TYPE_LEVEL_HIGH>, + <27 IRQ_TYPE_LEVEL_HIGH>; + }; +}; diff --git a/arch/mips/include/asm/mach-loongson64/builtin_dtbs.h b/arch/mips/include/asm/mach-loongson64/builtin_dtbs.h index 853c6d80887b..930c8a1c1e21 100644 --- a/arch/mips/include/asm/mach-loongson64/builtin_dtbs.h +++ b/arch/mips/include/asm/mach-loongson64/builtin_dtbs.h @@ -8,6 +8,6 @@ #ifndef __ASM_MACH_LOONGSON64_BUILTIN_DTBS_H_ #define __ASM_MACH_LOONGSON64_BUILTIN_DTBS_H_ -extern u32 __dtb_loongson3_4core_rs780e_begin[]; -extern u32 __dtb_loongson3_8core_rs780e_begin[]; +extern u32 __dtb_loongson64c_4core_rs780e_begin[]; +extern u32 __dtb_loongson64c_8core_rs780e_begin[]; #endif diff --git a/arch/mips/loongson64/env.c b/arch/mips/loongson64/env.c index d11bc346bbca..3e7caba8e788 100644 --- a/arch/mips/loongson64/env.c +++ b/arch/mips/loongson64/env.c @@ -133,11 +133,11 @@ void __init prom_init_env(void) case PRID_REV_LOONGSON3A_R2_1: case PRID_REV_LOONGSON3A_R3_0: case PRID_REV_LOONGSON3A_R3_1: - loongson_fdt_blob = __dtb_loongson3_4core_rs780e_begin; + loongson_fdt_blob = __dtb_loongson64c_4core_rs780e_begin; break; case PRID_REV_LOONGSON3B_R1: case PRID_REV_LOONGSON3B_R2: - loongson_fdt_blob = __dtb_loongson3_8core_rs780e_begin; + loongson_fdt_blob = __dtb_loongson64c_8core_rs780e_begin; break; default: break; -- cgit v1.2.3-59-g8ed1b From eef36f0ecd0dcd6ca646c7b3ac301fa18ff21085 Mon Sep 17 00:00:00 2001 From: Huacai Chen Date: Mon, 15 Jun 2020 14:04:17 +0800 Subject: dt-bindings: mips: Document two Loongson boards Document loongson64c-4core-ls7a and loongson64g-4core-ls7a, two boards with LS7A PCH. Signed-off-by: Huacai Chen Signed-off-by: Jiaxun Yang Signed-off-by: Thomas Bogendoerfer --- Documentation/devicetree/bindings/mips/loongson/devices.yaml | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/mips/loongson/devices.yaml b/Documentation/devicetree/bindings/mips/loongson/devices.yaml index 0516fe2b2897..88c5a29fd2be 100644 --- a/Documentation/devicetree/bindings/mips/loongson/devices.yaml +++ b/Documentation/devicetree/bindings/mips/loongson/devices.yaml @@ -17,6 +17,10 @@ properties: compatible: oneOf: + - description: Classic Loongson64 Quad Core + LS7A + items: + - const: loongson,loongson64c-4core-ls7a + - description: Classic Loongson64 Quad Core + RS780E items: - const: loongson,loongson64c-4core-rs780e @@ -24,4 +28,8 @@ properties: - description: Classic Loongson64 Octa Core + RS780E items: - const: loongson,loongson64c-8core-rs780e + + - description: Generic Loongson64 Quad Core + LS7A + items: + - const: loongson,loongson64g-4core-ls7a ... -- cgit v1.2.3-59-g8ed1b From cd79e378f11da125c87fcafeaf4d479513299de7 Mon Sep 17 00:00:00 2001 From: Paul Cercueil Date: Tue, 23 Jun 2020 20:24:26 +0200 Subject: dt-bindings: vendor-prefixes: Add YLM Shenzhen Yangliming Electronic Technology Co., Ltd., abbreviated YLM or YLMChina, and known as Anbernic in the rest of the world, is a Chinese manufacturer of handheld game consoles, some of which are known to be running Linux. Signed-off-by: Paul Cercueil Acked-by: Rob Herring Signed-off-by: Thomas Bogendoerfer --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index 9aeab66be85f..d24ecc7614fa 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -1167,6 +1167,8 @@ patternProperties: description: Shenzhen Xunlong Software CO.,Limited "^xylon,.*": description: Xylon + "^ylm,.*": + description: Shenzhen Yangliming Electronic Technology Co., Ltd. "^yna,.*": description: YSH & ATIL "^yones-toptech,.*": -- cgit v1.2.3-59-g8ed1b From 530043b86b5e63eb2fe7037ea8107da37b13bdbe Mon Sep 17 00:00:00 2001 From: Paul Cercueil Date: Tue, 23 Jun 2020 20:24:27 +0200 Subject: dt-bindings: MIPS: Add entry for the YLM RetroMini Add an entry to ingenic/devices.yaml for the JZ4725B-based YLM "RetroMini" RS-90. Signed-off-by: Paul Cercueil Acked-by: Rob Herring Signed-off-by: Thomas Bogendoerfer --- Documentation/devicetree/bindings/mips/ingenic/devices.yaml | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/mips/ingenic/devices.yaml b/Documentation/devicetree/bindings/mips/ingenic/devices.yaml index d1175030781a..07d8550a9b49 100644 --- a/Documentation/devicetree/bindings/mips/ingenic/devices.yaml +++ b/Documentation/devicetree/bindings/mips/ingenic/devices.yaml @@ -22,6 +22,11 @@ properties: - const: qi,lb60 - const: ingenic,jz4740 + - description: YLM RetroMini RS-90 + items: + - const: ylm,rs90 + - const: ingenic,jz4725b + - description: Game Consoles Worldwide GCW Zero items: - const: gcw,zero -- cgit v1.2.3-59-g8ed1b From 92404db74571c3174d45d8a156b724dad8f3a0e1 Mon Sep 17 00:00:00 2001 From: Paul Cercueil Date: Tue, 23 Jun 2020 20:24:28 +0200 Subject: dt-bindings: timer/ingenic,tcu: Add compatible strings for JZ4725B SoC Add compatible strings for the PWM and watchdog IPs on the Ingenic JZ4725B SoC. Signed-off-by: Paul Cercueil Acked-by: Rob Herring Signed-off-by: Thomas Bogendoerfer --- Documentation/devicetree/bindings/timer/ingenic,tcu.yaml | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/timer/ingenic,tcu.yaml b/Documentation/devicetree/bindings/timer/ingenic,tcu.yaml index 03893e6a2f57..371fb02a4351 100644 --- a/Documentation/devicetree/bindings/timer/ingenic,tcu.yaml +++ b/Documentation/devicetree/bindings/timer/ingenic,tcu.yaml @@ -116,7 +116,9 @@ patternProperties: - ingenic,jz4740-watchdog - ingenic,jz4780-watchdog - items: - - const: ingenic,jz4770-watchdog + - enum: + - ingenic,jz4770-watchdog + - ingenic,jz4725b-watchdog - const: ingenic,jz4740-watchdog reg: @@ -142,6 +144,7 @@ patternProperties: oneOf: - enum: - ingenic,jz4740-pwm + - ingenic,jz4725b-pwm - items: - enum: - ingenic,jz4770-pwm -- cgit v1.2.3-59-g8ed1b From 1c3dea35372cd07612573e99f820d5e6833bf53e Mon Sep 17 00:00:00 2001 From: "周琰杰 (Zhou Yanjie)" Date: Tue, 14 Jul 2020 13:32:26 +0800 Subject: dt-bindings: MIPS: Add X1830 based CU1830-Neo and fix bug in CU1000-Neo. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit 1.Add bindings for Ingenic X1830 based board, prepare for later dts. 2.The CU1000-Neo board actually uses X1000E instead of X1000, so the wrongly written "ingenic,x1000" in bindings should be changed to "ingenic,x1000e", the corresponding dts file modification will be made in a patch later in this series. Tested-by: 周正 (Zhou Zheng) Signed-off-by: 周琰杰 (Zhou Yanjie) Acked-by: Rob Herring Signed-off-by: Thomas Bogendoerfer --- Documentation/devicetree/bindings/mips/ingenic/devices.yaml | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/mips/ingenic/devices.yaml b/Documentation/devicetree/bindings/mips/ingenic/devices.yaml index 07d8550a9b49..83c86cbe4716 100644 --- a/Documentation/devicetree/bindings/mips/ingenic/devices.yaml +++ b/Documentation/devicetree/bindings/mips/ingenic/devices.yaml @@ -8,7 +8,8 @@ title: Ingenic XBurst based Platforms Device Tree Bindings maintainers: - 周琰杰 (Zhou Yanjie) -description: | + +description: Devices with a Ingenic XBurst CPU shall have the following properties. properties: @@ -37,8 +38,13 @@ properties: - const: img,ci20 - const: ingenic,jz4780 - - description: YSH & ATIL General Board CU Neo + - description: YSH & ATIL General Board, CU1000 Module with Neo Backplane items: - const: yna,cu1000-neo - - const: ingenic,x1000 + - const: ingenic,x1000e + + - description: YSH & ATIL General Board, CU1830 Module with Neo Backplane + items: + - const: yna,cu1830-neo + - const: ingenic,x1830 ... -- cgit v1.2.3-59-g8ed1b From 29cf195d33409b76a84cd8722967c96cc7162ca0 Mon Sep 17 00:00:00 2001 From: Serge Semin Date: Tue, 14 Jul 2020 15:57:47 +0300 Subject: dt-bindings: power: Convert mti,mips-cpc to DT schema It's a Cluster Power Controller embedded into the MIPS IP cores. Currently the corresponding dts node is supposed to have compatible and reg properties. Signed-off-by: Serge Semin Reviewed-by: Rob Herring Cc: Alexey Malahov Signed-off-by: Thomas Bogendoerfer --- .../devicetree/bindings/power/mti,mips-cpc.txt | 8 ----- .../devicetree/bindings/power/mti,mips-cpc.yaml | 35 ++++++++++++++++++++++ 2 files changed, 35 insertions(+), 8 deletions(-) delete mode 100644 Documentation/devicetree/bindings/power/mti,mips-cpc.txt create mode 100644 Documentation/devicetree/bindings/power/mti,mips-cpc.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/power/mti,mips-cpc.txt b/Documentation/devicetree/bindings/power/mti,mips-cpc.txt deleted file mode 100644 index c6b82511ae8a..000000000000 --- a/Documentation/devicetree/bindings/power/mti,mips-cpc.txt +++ /dev/null @@ -1,8 +0,0 @@ -Binding for MIPS Cluster Power Controller (CPC). - -This binding allows a system to specify where the CPC registers are -located. - -Required properties: -compatible : Should be "mti,mips-cpc". -regs: Should describe the address & size of the CPC register region. diff --git a/Documentation/devicetree/bindings/power/mti,mips-cpc.yaml b/Documentation/devicetree/bindings/power/mti,mips-cpc.yaml new file mode 100644 index 000000000000..ccdeaece169e --- /dev/null +++ b/Documentation/devicetree/bindings/power/mti,mips-cpc.yaml @@ -0,0 +1,35 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/power/mti,mips-cpc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MIPS Cluster Power Controller + +description: | + Defines a location of the MIPS Cluster Power Controller registers. + +maintainers: + - Paul Burton + +properties: + compatible: + const: mti,mips-cpc + + reg: + description: | + Base address and size of an unoccupied memory region, which will be + used to map the MIPS CPC registers block. + maxItems: 1 + +required: + - compatible + - reg + +examples: + - | + cpc@1bde0000 { + compatible = "mti,mips-cpc"; + reg = <0x1bde0000 0x8000>; + }; +... -- cgit v1.2.3-59-g8ed1b From e4fd970752ec663b80495117c706368087b4e486 Mon Sep 17 00:00:00 2001 From: Serge Semin Date: Tue, 14 Jul 2020 15:57:48 +0300 Subject: dt-bindings: interrupt-controller: Convert mti,gic to DT schema Modern device tree bindings are supposed to be created as YAML-files in accordance with DT schema. This commit replaces MIPS GIC legacy bare text binding with YAML file. As before the binding file states that the corresponding dts node is supposed to be compatible with MIPS Global Interrupt Controller indicated by the "mti,gic" compatible string and to provide a mandatory interrupt-controller and '#interrupt-cells' properties. There might be optional registers memory range, "mti,reserved-cpu-vectors" and "mti,reserved-ipi-vectors" properties specified. MIPS GIC also includes a free-running global timer, per-CPU count/compare timers, and a watchdog. Since currently the GIC Timer is only supported the DT schema expects an IRQ and clock-phandler charged timer sub-node with "mti,mips-gic-timer" compatible string. Signed-off-by: Serge Semin Reviewed-by: Rob Herring Signed-off-by: Thomas Bogendoerfer --- .../bindings/interrupt-controller/mips-gic.txt | 67 ---------- .../bindings/interrupt-controller/mti,gic.yaml | 148 +++++++++++++++++++++ 2 files changed, 148 insertions(+), 67 deletions(-) delete mode 100644 Documentation/devicetree/bindings/interrupt-controller/mips-gic.txt create mode 100644 Documentation/devicetree/bindings/interrupt-controller/mti,gic.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/interrupt-controller/mips-gic.txt b/Documentation/devicetree/bindings/interrupt-controller/mips-gic.txt deleted file mode 100644 index 173595305e26..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/mips-gic.txt +++ /dev/null @@ -1,67 +0,0 @@ -MIPS Global Interrupt Controller (GIC) - -The MIPS GIC routes external interrupts to individual VPEs and IRQ pins. -It also supports local (per-processor) interrupts and software-generated -interrupts which can be used as IPIs. The GIC also includes a free-running -global timer, per-CPU count/compare timers, and a watchdog. - -Required properties: -- compatible : Should be "mti,gic". -- interrupt-controller : Identifies the node as an interrupt controller -- #interrupt-cells : Specifies the number of cells needed to encode an - interrupt specifier. Should be 3. - - The first cell is the type of interrupt, local or shared. - See . - - The second cell is the GIC interrupt number. - - The third cell encodes the interrupt flags. - See for a list of valid - flags. - -Optional properties: -- reg : Base address and length of the GIC registers. If not present, - the base address reported by the hardware GCR_GIC_BASE will be used. -- mti,reserved-cpu-vectors : Specifies the list of CPU interrupt vectors - to which the GIC may not route interrupts. Valid values are 2 - 7. - This property is ignored if the CPU is started in EIC mode. -- mti,reserved-ipi-vectors : Specifies the range of GIC interrupts that are - reserved for IPIs. - It accepts 2 values, the 1st is the starting interrupt and the 2nd is the size - of the reserved range. - If not specified, the driver will allocate the last 2 * number of VPEs in the - system. - -Required properties for timer sub-node: -- compatible : Should be "mti,gic-timer". -- interrupts : Interrupt for the GIC local timer. - -Optional properties for timer sub-node: -- clocks : GIC timer operating clock. -- clock-frequency : Clock frequency at which the GIC timers operate. - -Note that one of clocks or clock-frequency must be specified. - -Example: - - gic: interrupt-controller@1bdc0000 { - compatible = "mti,gic"; - reg = <0x1bdc0000 0x20000>; - - interrupt-controller; - #interrupt-cells = <3>; - - mti,reserved-cpu-vectors = <7>; - mti,reserved-ipi-vectors = <40 8>; - - timer { - compatible = "mti,gic-timer"; - interrupts = ; - clock-frequency = <50000000>; - }; - }; - - uart@18101400 { - ... - interrupt-parent = <&gic>; - interrupts = ; - ... - }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/mti,gic.yaml b/Documentation/devicetree/bindings/interrupt-controller/mti,gic.yaml new file mode 100644 index 000000000000..9f0eb3addac4 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/mti,gic.yaml @@ -0,0 +1,148 @@ +# SPDX-License-Identifier: GPL-2.0-only +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/mti,gic.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MIPS Global Interrupt Controller + +maintainers: + - Paul Burton + - Thomas Bogendoerfer + +description: | + The MIPS GIC routes external interrupts to individual VPEs and IRQ pins. + It also supports local (per-processor) interrupts and software-generated + interrupts which can be used as IPIs. The GIC also includes a free-running + global timer, per-CPU count/compare timers, and a watchdog. + +properties: + compatible: + const: mti,gic + + "#interrupt-cells": + const: 3 + description: | + The 1st cell is the type of interrupt: local or shared defined in the + file 'dt-bindings/interrupt-controller/mips-gic.h'. The 2nd cell is the + GIC interrupt number. The 3d cell encodes the interrupt flags setting up + the IRQ trigger modes, which are defined in the file + 'dt-bindings/interrupt-controller/irq.h'. + + reg: + description: | + Base address and length of the GIC registers space. If not present, + the base address reported by the hardware GCR_GIC_BASE will be used. + maxItems: 1 + + interrupt-controller: true + + mti,reserved-cpu-vectors: + description: | + Specifies the list of CPU interrupt vectors to which the GIC may not + route interrupts. This property is ignored if the CPU is started in EIC + mode. + allOf: + - $ref: /schemas/types.yaml#definitions/uint32-array + - minItems: 1 + maxItems: 6 + uniqueItems: true + items: + minimum: 2 + maximum: 7 + + mti,reserved-ipi-vectors: + description: | + Specifies the range of GIC interrupts that are reserved for IPIs. + It accepts two values: the 1st is the starting interrupt and the 2nd is + the size of the reserved range. If not specified, the driver will + allocate the last (2 * number of VPEs in the system). + allOf: + - $ref: /schemas/types.yaml#definitions/uint32-array + - items: + - minimum: 0 + maximum: 254 + - minimum: 2 + maximum: 254 + + timer: + type: object + description: | + MIPS GIC includes a free-running global timer, per-CPU count/compare + timers, and a watchdog. Currently only the GIC Timer is supported. + properties: + compatible: + const: mti,gic-timer + + interrupts: + description: | + Interrupt for the GIC local timer, so normally it's suppose to be of + format. + maxItems: 1 + + clocks: + maxItems: 1 + + clock-frequency: true + + required: + - compatible + - interrupts + + oneOf: + - required: + - clocks + - required: + - clock-frequency + + additionalProperties: false + +unevaluatedProperties: false + +required: + - compatible + - "#interrupt-cells" + - interrupt-controller + +examples: + - | + #include + #include + + interrupt-controller@1bdc0000 { + compatible = "mti,gic"; + reg = <0x1bdc0000 0x20000>; + interrupt-controller; + #interrupt-cells = <3>; + mti,reserved-cpu-vectors = <7>; + mti,reserved-ipi-vectors = <40 8>; + + timer { + compatible = "mti,gic-timer"; + interrupts = ; + clock-frequency = <50000000>; + }; + }; + - | + #include + #include + + interrupt-controller@1bdc0000 { + compatible = "mti,gic"; + reg = <0x1bdc0000 0x20000>; + interrupt-controller; + #interrupt-cells = <3>; + + timer { + compatible = "mti,gic-timer"; + interrupts = ; + clocks = <&cpu_pll>; + }; + }; + - | + interrupt-controller { + compatible = "mti,gic"; + interrupt-controller; + #interrupt-cells = <3>; + }; +... -- cgit v1.2.3-59-g8ed1b From c9a56aa972f7c89b6e70e41cd04f4cadc5cc51d7 Mon Sep 17 00:00:00 2001 From: Serge Semin Date: Tue, 14 Jul 2020 15:57:49 +0300 Subject: dt-bindings: bus: Add MIPS CDMM controller It's a Common Device Memory Map controller embedded into the MIPS IP cores, which dts node is supposed to have compatible and reg properties. Signed-off-by: Serge Semin Reviewed-by: Rob Herring Signed-off-by: Thomas Bogendoerfer --- .../devicetree/bindings/bus/mti,mips-cdmm.yaml | 35 ++++++++++++++++++++++ 1 file changed, 35 insertions(+) create mode 100644 Documentation/devicetree/bindings/bus/mti,mips-cdmm.yaml (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/bus/mti,mips-cdmm.yaml b/Documentation/devicetree/bindings/bus/mti,mips-cdmm.yaml new file mode 100644 index 000000000000..9cc2d5f1beef --- /dev/null +++ b/Documentation/devicetree/bindings/bus/mti,mips-cdmm.yaml @@ -0,0 +1,35 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bus/mti,mips-cdmm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MIPS Common Device Memory Map + +description: | + Defines a location of the MIPS Common Device Memory Map registers. + +maintainers: + - James Hogan + +properties: + compatible: + const: mti,mips-cdmm + + reg: + description: | + Base address and size of an unoccupied memory region, which will be + used to map the MIPS CDMM registers block. + maxItems: 1 + +required: + - compatible + - reg + +examples: + - | + cdmm@1bde8000 { + compatible = "mti,mips-cdmm"; + reg = <0x1bde8000 0x8000>; + }; +... -- cgit v1.2.3-59-g8ed1b From a84a334f03c59fa9c0d682d13368611f7ca4f8ac Mon Sep 17 00:00:00 2001 From: Huacai Chen Date: Wed, 29 Jul 2020 14:58:36 +0800 Subject: dt-bindings: mips: Document Loongson kvm guest board Document loongson64v-4core-virtio, a virtio based kvm guest board for Loongson-3. Signed-off-by: Huacai Chen Signed-off-by: Jiaxun Yang Signed-off-by: Thomas Bogendoerfer --- Documentation/devicetree/bindings/mips/loongson/devices.yaml | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/mips/loongson/devices.yaml b/Documentation/devicetree/bindings/mips/loongson/devices.yaml index 88c5a29fd2be..d25e80aa8b2a 100644 --- a/Documentation/devicetree/bindings/mips/loongson/devices.yaml +++ b/Documentation/devicetree/bindings/mips/loongson/devices.yaml @@ -32,4 +32,8 @@ properties: - description: Generic Loongson64 Quad Core + LS7A items: - const: loongson,loongson64g-4core-ls7a + + - description: Virtual Loongson64 Quad Core + VirtIO + items: + - const: loongson,loongson64v-4core-virtio ... -- cgit v1.2.3-59-g8ed1b