From e5c0cd26d54e2e52792de2be3c32c9627168a06e Mon Sep 17 00:00:00 2001 From: Hans Verkuil Date: Thu, 8 Oct 2020 17:22:49 +0200 Subject: media: cec-core.rst/cec-ioc-g-mode.rst: fix typos in monitor-all description cec-core.rst was missing 'are', and cec-ioc-g-mode.rst was missing a comma. In both cases this made the description of the Monitor All functionality hard to read. Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- Documentation/driver-api/media/cec-core.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation/driver-api') diff --git a/Documentation/driver-api/media/cec-core.rst b/Documentation/driver-api/media/cec-core.rst index bc42982ac21e..9c6aff3b0ddf 100644 --- a/Documentation/driver-api/media/cec-core.rst +++ b/Documentation/driver-api/media/cec-core.rst @@ -143,7 +143,7 @@ To enable/disable the 'monitor all' mode:: int (*adap_monitor_all_enable)(struct cec_adapter *adap, bool enable); If enabled, then the adapter should be put in a mode to also monitor messages -that not for us. Not all hardware supports this and this function is only +that are not for us. Not all hardware supports this and this function is only called if the CEC_CAP_MONITOR_ALL capability is set. This callback is optional (some hardware may always be in 'monitor all' mode). -- cgit v1.2.3-59-g8ed1b From d3ed195bc761a1c5e5f1feae519318a4f91d258c Mon Sep 17 00:00:00 2001 From: Sakari Ailus Date: Tue, 13 Oct 2020 15:11:37 +0200 Subject: media: Documentation: v4l: Fix language Remove extra "is" from sentence explaining V4L2_CID_PIXEL_RATE may be used to tell the pixel rate used by a transmitter driver. Also call V4L2_CID_PIXEL_RATE a control. Signed-off-by: Sakari Ailus Reviewed-by: Laurent Pinchart Signed-off-by: Mauro Carvalho Chehab --- Documentation/driver-api/media/csi2.rst | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) (limited to 'Documentation/driver-api') diff --git a/Documentation/driver-api/media/csi2.rst b/Documentation/driver-api/media/csi2.rst index e1b838014906..e3bbc6baf0f0 100644 --- a/Documentation/driver-api/media/csi2.rst +++ b/Documentation/driver-api/media/csi2.rst @@ -28,10 +28,9 @@ interface elements must be present on the sub-device represents the CSI-2 transmitter. The V4L2_CID_LINK_FREQ control is used to tell the receiver driver the -frequency (and not the symbol rate) of the link. The -V4L2_CID_PIXEL_RATE is may be used by the receiver to obtain the pixel -rate the transmitter uses. The -:c:type:`v4l2_subdev_video_ops`->s_stream() callback provides an +frequency (and not the symbol rate) of the link. The V4L2_CID_PIXEL_RATE +control may be used by the receiver to obtain the pixel rate the transmitter +uses. The :c:type:`v4l2_subdev_video_ops`->s_stream() callback provides an ability to start and stop the stream. The value of the V4L2_CID_PIXEL_RATE is calculated as follows:: -- cgit v1.2.3-59-g8ed1b From 9d0a79e55a626165efb52bb15d714d231fc985e6 Mon Sep 17 00:00:00 2001 From: Sakari Ailus Date: Tue, 13 Oct 2020 16:02:27 +0200 Subject: media: Documentation: v4l: Document required controls on camera sensors Raw camera sensors connected to parallel or CSI-2 busses need to implement V4L2_CID_LINK_FREQ control so receiver drivers can configure the hardware accordingly. Document this. Also say V4L2_CID_PIXEL_RATE is recommended for such hardware. Signed-off-by: Sakari Ailus Signed-off-by: Mauro Carvalho Chehab --- Documentation/driver-api/media/camera-sensor.rst | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'Documentation/driver-api') diff --git a/Documentation/driver-api/media/camera-sensor.rst b/Documentation/driver-api/media/camera-sensor.rst index 4d1ae12b9b4d..ffb0cad8137a 100644 --- a/Documentation/driver-api/media/camera-sensor.rst +++ b/Documentation/driver-api/media/camera-sensor.rst @@ -132,3 +132,16 @@ used to obtain device's power state after the power state transition: The function returns a non-zero value if it succeeded getting the power count or runtime PM was disabled, in either of which cases the driver may proceed to access the device. + +Controls +-------- + +For camera sensors that are connected to a bus where transmitter and receiver +require common configuration set by drivers, such as CSI-2 or parallel (BT.601 +or BT.656) bus, the ``V4L2_CID_LINK_FREQ`` control is mandatory on transmitter +drivers. Receiver drivers can use the ``V4L2_CID_LINK_FREQ`` to query the +frequency used on the bus. + +The transmitter drivers should also implement ``V4L2_CID_PIXEL_RATE`` control in +order to tell the maximum pixel rate to the receiver. This is required on raw +camera sensors. -- cgit v1.2.3-59-g8ed1b From fe209bf531d65012a157e7033119b0ebdeaa0935 Mon Sep 17 00:00:00 2001 From: Randy Dunlap Date: Sat, 4 Jul 2020 05:44:53 +0200 Subject: media: Documentation/driver-api: media/cec-core: drop doubled word Drop the doubled word "the". Signed-off-by: Randy Dunlap Cc: Jonathan Corbet Cc: linux-doc@vger.kernel.org Signed-off-by: Mauro Carvalho Chehab --- Documentation/driver-api/media/cec-core.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation/driver-api') diff --git a/Documentation/driver-api/media/cec-core.rst b/Documentation/driver-api/media/cec-core.rst index 9c6aff3b0ddf..a26dc87eee8f 100644 --- a/Documentation/driver-api/media/cec-core.rst +++ b/Documentation/driver-api/media/cec-core.rst @@ -335,7 +335,7 @@ So this must work: $ cat einj.txt >error-inj The first callback is called when this file is read and it should show the -the current error injection state:: +current error injection state:: int (*error_inj_show)(struct cec_adapter *adap, struct seq_file *sf); -- cgit v1.2.3-59-g8ed1b From eeee0dfda6d51a6c1ee5959680bcf299fcd5cfa9 Mon Sep 17 00:00:00 2001 From: Randy Dunlap Date: Sat, 4 Jul 2020 05:45:01 +0200 Subject: media: Documentation/driver-api: media/v4l2-controls: drop doubled words Drop the doubled words "type" and "the". Signed-off-by: Randy Dunlap Cc: Jonathan Corbet Cc: linux-doc@vger.kernel.org Signed-off-by: Mauro Carvalho Chehab --- Documentation/driver-api/media/v4l2-controls.rst | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'Documentation/driver-api') diff --git a/Documentation/driver-api/media/v4l2-controls.rst b/Documentation/driver-api/media/v4l2-controls.rst index 77f42ea3bac7..b2e91804829b 100644 --- a/Documentation/driver-api/media/v4l2-controls.rst +++ b/Documentation/driver-api/media/v4l2-controls.rst @@ -335,7 +335,7 @@ current and new values: union v4l2_ctrl_ptr p_new; union v4l2_ctrl_ptr p_cur; -If the control has a simple s32 type type, then: +If the control has a simple s32 type, then: .. code-block:: c @@ -349,7 +349,7 @@ Within the control ops you can freely use these. The val and cur.val speak for themselves. The p_char pointers point to character buffers of length ctrl->maximum + 1, and are always 0-terminated. -Unless the control is marked volatile the p_cur field points to the the +Unless the control is marked volatile the p_cur field points to the current cached control value. When you create a new control this value is made identical to the default value. After calling v4l2_ctrl_handler_setup() this value is passed to the hardware. It is generally a good idea to call this -- cgit v1.2.3-59-g8ed1b From 3cf80a75e16a1146645b869a579748e945da6c42 Mon Sep 17 00:00:00 2001 From: Randy Dunlap Date: Sat, 4 Jul 2020 05:44:55 +0200 Subject: media: Documentation/driver-api: media/v4l2-dev: drop doubled word Drop the doubled word "device". Signed-off-by: Randy Dunlap Cc: Jonathan Corbet Cc: linux-doc@vger.kernel.org Signed-off-by: Mauro Carvalho Chehab --- Documentation/driver-api/media/v4l2-dev.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation/driver-api') diff --git a/Documentation/driver-api/media/v4l2-dev.rst b/Documentation/driver-api/media/v4l2-dev.rst index 666330af31ed..99e3b5fa7444 100644 --- a/Documentation/driver-api/media/v4l2-dev.rst +++ b/Documentation/driver-api/media/v4l2-dev.rst @@ -212,7 +212,7 @@ types exist: ========================== ==================== ============================== The last argument gives you a certain amount of control over the device -device node number used (i.e. the X in ``videoX``). Normally you will pass -1 +node number used (i.e. the X in ``videoX``). Normally you will pass -1 to let the v4l2 framework pick the first free number. But sometimes users want to select a specific node number. It is common that drivers allow the user to select a specific device node number through a driver module -- cgit v1.2.3-59-g8ed1b From 1785c8290489bb4b9f2897b7f545fd06e1f6d226 Mon Sep 17 00:00:00 2001 From: Randy Dunlap Date: Sat, 4 Jul 2020 05:44:54 +0200 Subject: media: Documentation/driver-api: media/dtv-frontend: drop doubled word Drop the doubled word "errors". Signed-off-by: Randy Dunlap Cc: Jonathan Corbet Cc: linux-doc@vger.kernel.org Signed-off-by: Mauro Carvalho Chehab --- Documentation/driver-api/media/dtv-frontend.rst | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'Documentation/driver-api') diff --git a/Documentation/driver-api/media/dtv-frontend.rst b/Documentation/driver-api/media/dtv-frontend.rst index 91f77fe58e83..ea43cdb5b0e4 100644 --- a/Documentation/driver-api/media/dtv-frontend.rst +++ b/Documentation/driver-api/media/dtv-frontend.rst @@ -244,7 +244,7 @@ Carrier Signal to Noise ratio (:ref:`DTV-STAT-CNR`) Having it available after inner FEC is more common. Bit counts post-FEC (:ref:`DTV-STAT-POST-ERROR-BIT-COUNT` and :ref:`DTV-STAT-POST-TOTAL-BIT-COUNT`) - - Those counters measure the number of bits and bit errors errors after + - Those counters measure the number of bits and bit errors after the forward error correction (FEC) on the inner coding block (after Viterbi, LDPC or other inner code). @@ -253,7 +253,7 @@ Bit counts post-FEC (:ref:`DTV-STAT-POST-ERROR-BIT-COUNT` and :ref:`DTV-STAT-POS see :c:type:`fe_status`). Bit counts pre-FEC (:ref:`DTV-STAT-PRE-ERROR-BIT-COUNT` and :ref:`DTV-STAT-PRE-TOTAL-BIT-COUNT`) - - Those counters measure the number of bits and bit errors errors before + - Those counters measure the number of bits and bit errors before the forward error correction (FEC) on the inner coding block (before Viterbi, LDPC or other inner code). @@ -263,7 +263,7 @@ Bit counts pre-FEC (:ref:`DTV-STAT-PRE-ERROR-BIT-COUNT` and :ref:`DTV-STAT-PRE-T after ``FE_HAS_VITERBI``, see :c:type:`fe_status`). Block counts (:ref:`DTV-STAT-ERROR-BLOCK-COUNT` and :ref:`DTV-STAT-TOTAL-BLOCK-COUNT`) - - Those counters measure the number of blocks and block errors errors after + - Those counters measure the number of blocks and block errors after the forward error correction (FEC) on the inner coding block (before Viterbi, LDPC or other inner code). -- cgit v1.2.3-59-g8ed1b From 1ec0b899c2b776c0c2dd03044b171a52b5211570 Mon Sep 17 00:00:00 2001 From: Sakari Ailus Date: Mon, 3 Feb 2020 10:39:24 +0100 Subject: media: ccs: Add the generator for CCS register definitions and limits Add register definitions of the MIPI CCS 1.1 standard. The CCS driver makes extended use of device's capability registers that are dependent on CCS version. This involves having an in-memory data structure for limit and capability information, creating that data structure and accessing it. The register definitions as well as the definitions of this data structure are generated from a text file using a Perl script. Add the generator script to make it easy to update the generated files. Signed-off-by: Sakari Ailus Signed-off-by: Mauro Carvalho Chehab --- .../driver-api/media/drivers/ccs/ccs-regs.txt | 1041 ++++++++++++++++++++ .../driver-api/media/drivers/ccs/mk-ccs-regs | 433 ++++++++ MAINTAINERS | 1 + 3 files changed, 1475 insertions(+) create mode 100644 Documentation/driver-api/media/drivers/ccs/ccs-regs.txt create mode 100755 Documentation/driver-api/media/drivers/ccs/mk-ccs-regs (limited to 'Documentation/driver-api') diff --git a/Documentation/driver-api/media/drivers/ccs/ccs-regs.txt b/Documentation/driver-api/media/drivers/ccs/ccs-regs.txt new file mode 100644 index 000000000000..93f0131aa304 --- /dev/null +++ b/Documentation/driver-api/media/drivers/ccs/ccs-regs.txt @@ -0,0 +1,1041 @@ +# Copyright (C) 2019--2020 Intel Corporation +# SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause + +# register rflags +# - f field LSB MSB rflags +# - e enum value # after a field +# - e enum value [LSB MSB] +# - b bool bit +# - l arg name min max elsize [discontig...] +# +# rflags +# 8, 16, 32 register bits (default is 8) +# v1.1 defined in version 1.1 +# f formula +# float_ireal iReal or IEEE 754; 32 bits +# ireal unsigned iReal + +# general status registers +module_model_id 0x0000 16 +module_revision_number_major 0x0002 8 +frame_count 0x0005 8 +pixel_order 0x0006 8 +- e GRBG 0 +- e RGGB 1 +- e BGGR 2 +- e GBRG 3 +MIPI_CCS_version 0x0007 8 +- e v1_0 0x10 +- e v1_1 0x11 +- f major 4 7 +- f minor 0 3 +data_pedestal 0x0008 16 +module_manufacturer_id 0x000e 16 +module_revision_number_minor 0x0010 8 +module_date_year 0x0012 8 +module_date_month 0x0013 8 +module_date_day 0x0014 8 +module_date_phase 0x0015 8 +- f 0 2 +- e ts 0 +- e es 1 +- e cs 2 +- e mp 3 +sensor_model_id 0x0016 16 +sensor_revision_number 0x0018 8 +sensor_firmware_version 0x001a 8 +serial_number 0x001c 32 +sensor_manufacturer_id 0x0020 16 +sensor_revision_number_16 0x0022 16 + +# frame format description registers +frame_format_model_type 0x0040 8 +- e 2-byte 1 +- e 4-byte 2 +frame_format_model_subtype 0x0041 8 +- f rows 0 3 +- f columns 4 7 +frame_format_descriptor(n) 0x0042 16 f +- l n 0 14 2 +- f pixels 0 11 +- f pcode 12 15 +- e embedded 1 +- e dummy_pixel 2 +- e black_pixel 3 +- e dark_pixel 4 +- e visible_pixel 5 +- e manuf_specific_0 8 +- e manuf_specific_1 9 +- e manuf_specific_2 10 +- e manuf_specific_3 11 +- e manuf_specific_4 12 +- e manuf_specific_5 13 +- e manuf_specific_6 14 +frame_format_descriptor_4(n) 0x0060 32 f +- l n 0 7 4 +- f pixels 0 15 +- f pcode 28 31 +- e embedded 1 +- e dummy_pixel 2 +- e black_pixel 3 +- e dark_pixel 4 +- e visible_pixel 5 +- e manuf_specific_0 8 +- e manuf_specific_1 9 +- e manuf_specific_2 10 +- e manuf_specific_3 11 +- e manuf_specific_4 12 +- e manuf_specific_5 13 +- e manuf_specific_6 14 + +# analog gain description registers +analog_gain_capability 0x0080 16 +- e global 0 +- e alternate_global 2 +analog_gain_code_min 0x0084 16 +analog_gain_code_max 0x0086 16 +analog_gain_code_step 0x0088 16 +analog_gain_type 0x008a 16 +analog_gain_m0 0x008c 16 +analog_gain_c0 0x008e 16 +analog_gain_m1 0x0090 16 +analog_gain_c1 0x0092 16 +analog_linear_gain_min 0x0094 16 v1.1 +analog_linear_gain_max 0x0096 16 v1.1 +analog_linear_gain_step_size 0x0098 16 v1.1 +analog_exponential_gain_min 0x009a 16 v1.1 +analog_exponential_gain_max 0x009c 16 v1.1 +analog_exponential_gain_step_size 0x009e 16 v1.1 + +# data format description registers +data_format_model_type 0x00c0 8 +- e normal 1 +- e extended 2 +data_format_model_subtype 0x00c1 8 +- f rows 0 3 +- f columns 4 7 +data_format_descriptor(n) 0x00c2 16 f +- l n 0 15 2 +- f compressed 0 7 +- f uncompressed 8 15 + +# general set-up registers +mode_select 0x0100 8 +- e software_standby 0 +- e streaming 1 +image_orientation 0x0101 8 +- b horizontal_mirror 0 +- b vertical_flip 1 +software_reset 0x0103 8 +- e off 0 +- e on 1 +grouped_parameter_hold 0x0104 8 +mask_corrupted_frames 0x0105 8 +- e allow 0 +- e mask 1 +fast_standby_ctrl 0x0106 8 +- e complete_frames 0 +- e frame_truncation 1 +CCI_address_ctrl 0x0107 8 +2nd_CCI_if_ctrl 0x0108 8 +- b enable 0 +- b ack 1 +2nd_CCI_address_ctrl 0x0109 8 +CSI_channel_identifier 0x0110 8 +CSI_signaling_mode 0x0111 8 +- e csi_2_dphy 2 +- e csi_2_cphy 3 +CSI_data_format 0x0112 16 +CSI_lane_mode 0x0114 8 +DPCM_Frame_DT 0x011d 8 +Bottom_embedded_data_DT 0x011e 8 +Bottom_embedded_data_VC 0x011f 8 + +gain_mode 0x0120 8 +- e global 0 +- e alternate 1 +ADC_bit_depth 0x0121 8 +emb_data_ctrl 0x0122 v1.1 +- b raw8_packing_for_raw16 0 +- b raw10_packing_for_raw20 1 +- b raw12_packing_for_raw24 2 + +GPIO_TRIG_mode 0x0130 8 +extclk_frequency_mhz 0x0136 16 ireal +temp_sensor_ctrl 0x0138 8 +- b enable 0 +temp_sensor_mode 0x0139 8 +temp_sensor_output 0x013a 8 + +# integration time registers +fine_integration_time 0x0200 16 +coarse_integration_time 0x0202 16 + +# analog gain registers +analog_gain_code_global 0x0204 16 +analog_linear_gain_global 0x0206 16 v1.1 +analog_exponential_gain_global 0x0208 16 v1.1 + +# digital gain registers +digital_gain_global 0x020e 16 + +# hdr control registers +Short_analog_gain_global 0x0216 16 +Short_digital_gain_global 0x0218 16 + +HDR_mode 0x0220 8 +- b enabled 0 +- b separate_analog_gain 1 +- b upscaling 2 +- b reset_sync 3 +- b timing_mode 4 +- b exposure_ctrl_direct 5 +- b separate_digital_gain 6 +HDR_resolution_reduction 0x0221 8 +- f row 0 3 +- f column 4 7 +Exposure_ratio 0x0222 8 +HDR_internal_bit_depth 0x0223 8 +Direct_short_integration_time 0x0224 16 +Short_analog_linear_gain_global 0x0226 16 v1.1 +Short_analog_exponential_gain_global 0x0228 16 v1.1 + +# clock set-up registers +vt_pix_clk_div 0x0300 16 +vt_sys_clk_div 0x0302 16 +pre_pll_clk_div 0x0304 16 +#vt_pre_pll_clk_div 0x0304 16 +pll_multiplier 0x0306 16 +#vt_pll_multiplier 0x0306 16 +op_pix_clk_div 0x0308 16 +op_sys_clk_div 0x030a 16 +op_pre_pll_clk_div 0x030c 16 +op_pll_multiplier 0x031e 16 +pll_mode 0x0310 8 +- f 0 0 +- e single 0 +- e dual 1 +op_pix_clk_div_rev 0x0312 16 v1.1 +op_sys_clk_div_rev 0x0314 16 v1.1 + +# frame timing registers +frame_length_lines 0x0340 16 +line_length_pck 0x0342 16 + +# image size registers +x_addr_start 0x0344 16 +y_addr_start 0x0346 16 +x_addr_end 0x0348 16 +y_addr_end 0x034a 16 +x_output_size 0x034c 16 +y_output_size 0x034e 16 + +# timing mode registers +Frame_length_ctrl 0x0350 8 +- b automatic 0 +Timing_mode_ctrl 0x0352 8 +- b manual_readout 0 +- b delayed_exposure 1 +Start_readout_rs 0x0353 8 +- b manual_readout_start 0 +Frame_margin 0x0354 16 + +# sub-sampling registers +x_even_inc 0x0380 16 +x_odd_inc 0x0382 16 +y_even_inc 0x0384 16 +y_odd_inc 0x0386 16 + +# monochrome readout registers +monochrome_en 0x0390 v1.1 +- e enabled 0 + +# image scaling registers +Scaling_mode 0x0400 16 +- e no_scaling 0 +- e horizontal 1 +scale_m 0x0404 16 +scale_n 0x0406 16 +digital_crop_x_offset 0x0408 16 +digital_crop_y_offset 0x040a 16 +digital_crop_image_width 0x040c 16 +digital_crop_image_height 0x040e 16 + +# image compression registers +compression_mode 0x0500 16 +- e none 0 +- e dpcm_pcm_simple 1 + +# test pattern registers +test_pattern_mode 0x0600 16 +- e none 0 +- e solid_color 1 +- e color_bars 2 +- e fade_to_grey 3 +- e pn9 4 +- e color_tile 5 +test_data_red 0x0602 16 +test_data_greenR 0x0604 16 +test_data_blue 0x0606 16 +test_data_greenB 0x0608 16 +value_step_size_smooth 0x060a 8 +value_step_size_quantised 0x060b 8 + +# phy configuration registers +tclk_post 0x0800 8 +ths_prepare 0x0801 8 +ths_zero_min 0x0802 8 +ths_trail 0x0803 8 +tclk_trail_min 0x0804 8 +tclk_prepare 0x0805 8 +tclk_zero 0x0806 8 +tlpx 0x0807 8 +phy_ctrl 0x0808 8 +- e auto 0 +- e UI 1 +- e manual 2 +tclk_post_ex 0x080a 16 +ths_prepare_ex 0x080c 16 +ths_zero_min_ex 0x080e 16 +ths_trail_ex 0x0810 16 +tclk_trail_min_ex 0x0812 16 +tclk_prepare_ex 0x0814 16 +tclk_zero_ex 0x0816 16 +tlpx_ex 0x0818 16 + +# link rate register +requested_link_rate 0x0820 32 u16.16 + +# equalization control registers +DPHY_equalization_mode 0x0824 8 v1.1 +- b eq2 0 +PHY_equalization_ctrl 0x0825 8 v1.1 +- b enable 0 + +# d-phy preamble control registers +DPHY_preamble_ctrl 0x0826 8 v1.1 +- b enable 0 +DPHY_preamble_length 0x0826 8 v1.1 + +# d-phy spread spectrum control registers +PHY_SSC_ctrl 0x0828 8 v1.1 +- b enable 0 + +# manual lp control register +manual_LP_ctrl 0x0829 8 v1.1 +- b enable 0 + +# additional phy configuration registers +twakeup 0x082a v1.1 +tinit 0x082b v1.1 +ths_exit 0x082c v1.1 +ths_exit_ex 0x082e 16 v1.1 + +# phy calibration configuration registers +PHY_periodic_calibration_ctrl 0x0830 8 +- b frame_blanking 0 +PHY_periodic_calibration_interval 0x0831 8 +PHY_init_calibration_ctrl 0x0832 8 +- b stream_start 0 +DPHY_calibration_mode 0x0833 8 v1.1 +- b also_alternate 0 +CPHY_calibration_mode 0x0834 8 v1.1 +- e format_1 0 +- e format_2 1 +- e format_3 2 +t3_calpreamble_length 0x0835 8 v1.1 +t3_calpreamble_length_per 0x0836 8 v1.1 +t3_calaltseq_length 0x0837 8 v1.1 +t3_calaltseq_length_per 0x0838 8 v1.1 +FM2_init_seed 0x083a 16 v1.1 +t3_caludefseq_length 0x083c 16 v1.1 +t3_caludefseq_length_per 0x083e 16 v1.1 + +# c-phy manual control registers +TGR_Preamble_Length 0x0841 8 +- b preamable_prog_seq 7 +- f begin_preamble_length 0 5 +TGR_Post_Length 0x0842 8 +- f post_length 0 4 +TGR_Preamble_Prog_Sequence(n2) 0x0843 +- l n2 0 6 1 +- f symbol_n_1 3 5 +- f symbol_n 0 2 +t3_prepare 0x084e 16 +t3_lpx 0x0850 16 + +# alps control register +ALPS_ctrl 0x085a 8 +- b lvlp_dphy 0 +- b lvlp_cphy 1 +- b alp_cphy 2 + +# lrte control registers +TX_REG_CSI_EPD_EN_SSP_cphy 0x0860 16 +TX_REG_CSI_EPD_OP_SLP_cphy 0x0862 16 +TX_REG_CSI_EPD_EN_SSP_dphy 0x0864 16 +TX_REG_CSI_EPD_OP_SLP_dphy 0x0866 16 +TX_REG_CSI_EPD_MISC_OPTION_cphy 0x0868 v1.1 +TX_REG_CSI_EPD_MISC_OPTION_dphy 0x0869 v1.1 + +# scrambling control registers +Scrambling_ctrl 0x0870 +- b enabled 0 +- f 2 3 +- e 1_seed_cphy 0 +- e 4_seed_cphy 3 +lane_seed_value(seed, lane) 0x0872 16 +- l seed 0 3 0x10 +- l lane 0 7 0x2 + +# usl control registers +TX_USL_REV_ENTRY 0x08c0 16 v1.1 +TX_USL_REV_Clock_Counter 0x08c2 16 v1.1 +TX_USL_REV_LP_Counter 0x08c4 16 v1.1 +TX_USL_REV_Frame_Counter 0x08c6 16 v1.1 +TX_USL_REV_Chronological_Timer 0x08c8 16 v1.1 +TX_USL_FWD_ENTRY 0x08ca 16 v1.1 +TX_USL_GPIO 0x08cc 16 v1.1 +TX_USL_Operation 0x08ce 16 v1.1 +- b reset 0 +TX_USL_ALP_ctrl 0x08d0 16 v1.1 +- b clock_pause 0 +TX_USL_APP_BTA_ACK_TIMEOUT 0x08d2 16 v1.1 +TX_USL_SNS_BTA_ACK_TIMEOUT 0x08d2 16 v1.1 +USL_Clock_Mode_d_ctrl 0x08d2 v1.1 +- b cont_clock_standby 0 +- b cont_clock_vblank 1 +- b cont_clock_hblank 2 + +# binning configuration registers +binning_mode 0x0900 8 +binning_type 0x0901 8 +binning_weighting 0x0902 8 + +# data transfer interface registers +data_transfer_if_1_ctrl 0x0a00 8 +- b enable 0 +- b write 1 +- b clear_error 2 +data_transfer_if_1_status 0x0a01 8 +- b read_if_ready 0 +- b write_if_ready 1 +- b data_corrupted 2 +- b improper_if_usage 3 +data_transfer_if_1_page_select 0x0a02 8 +data_transfer_if_1_data(p) 0x0a04 8 f +- l p 0 63 1 + +# image processing and sensor correction configuration registers +shading_correction_en 0x0b00 8 +- b enable 0 +luminance_correction_level 0x0b01 8 +green_imbalance_filter_en 0x0b02 8 +- b enable 0 +mapped_defect_correct_en 0x0b05 8 +- b enable 0 +single_defect_correct_en 0x0b06 8 +- b enable 0 +dynamic_couplet_correct_en 0x0b08 8 +- b enable 0 +combined_defect_correct_en 0x0b0a 8 +- b enable 0 +module_specific_correction_en 0x0b0c 8 +- b enable 0 +dynamic_triplet_defect_correct_en 0x0b13 8 +- b enable 0 +NF_ctrl 0x0b15 8 +- b luma 0 +- b chroma 1 +- b combined 2 + +# optical black pixel readout registers +OB_readout_control 0x0b30 8 +- b enable 0 +- b interleaving 1 +OB_virtual_channel 0x0b31 8 +OB_DT 0x0b32 8 +OB_data_format 0x0b33 8 + +# color temperature feedback registers +color_temperature 0x0b8c 16 +absolute_gain_greenr 0x0b8e 16 +absolute_gain_red 0x0b90 16 +absolute_gain_blue 0x0b92 16 +absolute_gain_greenb 0x0b94 16 + +# cfa conversion registers +CFA_conversion_ctrl 0x0ba0 v1.1 +- b bayer_conversion_enable 0 + +# flash strobe and sa strobe control registers +flash_strobe_adjustment 0x0c12 8 +flash_strobe_start_point 0x0c14 16 +tflash_strobe_delay_rs_ctrl 0x0c16 16 +tflash_strobe_width_high_rs_ctrl 0x0c18 16 +flash_mode_rs 0x0c1a 8 +- b continuous 0 +- b truncate 1 +- b async 3 +flash_trigger_rs 0x0c1b 8 +flash_status 0x0c1c 8 +- b retimed 0 +sa_strobe_mode 0x0c1d 8 +- b continuous 0 +- b truncate 1 +- b async 3 +- b adjust_edge 4 +sa_strobe_start_point 0x0c1e 16 +tsa_strobe_delay_ctrl 0x0c20 16 +tsa_strobe_width_ctrl 0x0c22 16 +sa_strobe_trigger 0x0c24 8 +sa_strobe_status 0x0c25 8 +- b retimed 0 +tSA_strobe_re_delay_ctrl 0x0c30 16 +tSA_strobe_fe_delay_ctrl 0x0c32 16 + +# pdaf control registers +PDAF_ctrl 0x0d00 16 +- b enable 0 +- b processed 1 +- b interleaved 2 +- b visible_pdaf_correction 3 +PDAF_VC 0x0d02 8 +PDAF_DT 0x0d03 8 +pd_x_addr_start 0x0d04 16 +pd_y_addr_start 0x0d06 16 +pd_x_addr_end 0x0d08 16 +pd_y_addr_end 0x0d0a 16 + +# bracketing interface configuration registers +bracketing_LUT_ctrl 0x0e00 8 +bracketing_LUT_mode 0x0e01 8 +- b continue_streaming 0 +- b loop_mode 1 +bracketing_LUT_entry_ctrl 0x0e02 8 +bracketing_LUT_frame(n) 0x0e10 v1.1 f +- l n 0 0xef 1 + +# integration time and gain parameter limit registers +integration_time_capability 0x1000 16 +- b fine 0 +coarse_integration_time_min 0x1004 16 +coarse_integration_time_max_margin 0x1006 16 +fine_integration_time_min 0x1008 16 +fine_integration_time_max_margin 0x100a 16 + +# digital gain parameter limit registers +digital_gain_capability 0x1081 +- e none 0 +- e global 2 +digital_gain_min 0x1084 16 +digital_gain_max 0x1086 16 +digital_gain_step_size 0x1088 16 + +# data pedestal capability registers +Pedestal_capability 0x10e0 8 v1.1 + +# adc capability registers +ADC_capability 0x10f0 8 +- b bit_depth_ctrl 0 +ADC_bit_depth_capability 0x10f4 32 v1.1 + +# video timing parameter limit registers +min_ext_clk_freq_mhz 0x1100 32 float_ireal +max_ext_clk_freq_mhz 0x1104 32 float_ireal +min_pre_pll_clk_div 0x1108 16 +# min_vt_pre_pll_clk_div 0x1108 16 +max_pre_pll_clk_div 0x110a 16 +# max_vt_pre_pll_clk_div 0x110a 16 +min_pll_ip_clk_freq_mhz 0x110c 32 float_ireal +# min_vt_pll_ip_clk_freq_mhz 0x110c 32 float_ireal +max_pll_ip_clk_freq_mhz 0x1110 32 float_ireal +# max_vt_pll_ip_clk_freq_mhz 0x1110 32 float_ireal +min_pll_multiplier 0x1114 16 +# min_vt_pll_multiplier 0x1114 16 +max_pll_multiplier 0x1116 16 +# max_vt_pll_multiplier 0x1116 16 +min_pll_op_clk_freq_mhz 0x1118 32 float_ireal +max_pll_op_clk_freq_mhz 0x111c 32 float_ireal + +# video timing set-up capability registers +min_vt_sys_clk_div 0x1120 16 +max_vt_sys_clk_div 0x1122 16 +min_vt_sys_clk_freq_mhz 0x1124 32 float_ireal +max_vt_sys_clk_freq_mhz 0x1128 32 float_ireal +min_vt_pix_clk_freq_mhz 0x112c 32 float_ireal +max_vt_pix_clk_freq_mhz 0x1130 32 float_ireal +min_vt_pix_clk_div 0x1134 16 +max_vt_pix_clk_div 0x1136 16 +clock_calculation 0x1138 +- b lane_speed 0 +- b link_decoupled 1 +- b dual_pll_op_sys_ddr 2 +- b dual_pll_op_pix_ddr 3 +num_of_vt_lanes 0x1139 +num_of_op_lanes 0x113a +op_bits_per_lane 0x113b 8 v1.1 + +# frame timing parameter limits +min_frame_length_lines 0x1140 16 +max_frame_length_lines 0x1142 16 +min_line_length_pck 0x1144 16 +max_line_length_pck 0x1146 16 +min_line_blanking_pck 0x1148 16 +min_frame_blanking_lines 0x114a 16 +min_line_length_pck_step_size 0x114c +timing_mode_capability 0x114d +- b auto_frame_length 0 +- b rolling_shutter_manual_readout 2 +- b delayed_exposure_start 3 +- b manual_exposure_embedded_data 4 +frame_margin_max_value 0x114e 16 +frame_margin_min_value 0x1150 +gain_delay_type 0x1151 +- e fixed 0 +- e variable 1 + +# output clock set-up capability registers +min_op_sys_clk_div 0x1160 16 +max_op_sys_clk_div 0x1162 16 +min_op_sys_clk_freq_mhz 0x1164 32 float_ireal +max_op_sys_clk_freq_mhz 0x1168 32 float_ireal +min_op_pix_clk_div 0x116c 16 +max_op_pix_clk_div 0x116e 16 +min_op_pix_clk_freq_mhz 0x1170 32 float_ireal +max_op_pix_clk_freq_mhz 0x1174 32 float_ireal + +# image size parameter limit registers +x_addr_min 0x1180 16 +y_addr_min 0x1182 16 +x_addr_max 0x1184 16 +y_addr_max 0x1186 16 +min_x_output_size 0x1188 16 +min_y_output_size 0x118a 16 +max_x_output_size 0x118c 16 +max_y_output_size 0x118e 16 + +x_addr_start_div_constant 0x1190 v1.1 +y_addr_start_div_constant 0x1191 v1.1 +x_addr_end_div_constant 0x1192 v1.1 +y_addr_end_div_constant 0x1193 v1.1 +x_size_div 0x1194 v1.1 +y_size_div 0x1195 v1.1 +x_output_div 0x1196 v1.1 +y_output_div 0x1197 v1.1 +non_flexible_resolution_support 0x1198 v1.1 +- b new_pix_addr 0 +- b new_output_res 1 +- b output_crop_no_pad 2 +- b output_size_lane_dep 3 + +min_op_pre_pll_clk_div 0x11a0 16 +max_op_pre_pll_clk_div 0x11a2 16 +min_op_pll_ip_clk_freq_mhz 0x11a4 32 float_ireal +max_op_pll_ip_clk_freq_mhz 0x11a8 32 float_ireal +min_op_pll_multiplier 0x11ac 16 +max_op_pll_multiplier 0x11ae 16 +min_op_pll_op_clk_freq_mhz 0x11b0 32 float_ireal +max_op_pll_op_clk_freq_mhz 0x11b4 32 float_ireal +clock_tree_pll_capability 0x11b8 8 +- b dual_pll 0 +- b single_pll 1 +- b ext_divider 2 +- b flexible_op_pix_clk_div 3 +clock_capa_type_capability 0x11b9 v1.1 +- b ireal 0 + +# sub-sampling parameters limit registers +min_even_inc 0x11c0 16 +min_odd_inc 0x11c2 16 +max_even_inc 0x11c4 16 +max_odd_inc 0x11c6 16 +aux_subsamp_capability 0x11c8 v1.1 +- b factor_power_of_2 1 +aux_subsamp_mono_capability 0x11c9 v1.1 +- b factor_power_of_2 1 +monochrome_capability 0x11ca v1.1 +- e inc_odd 0 +- e inc_even 1 +pixel_readout_capability 0x11cb v1.1 +- e bayer 0 +- e monochrome 1 +- e bayer_and_mono 2 +min_even_inc_mono 0x11cc 16 v1.1 +max_even_inc_mono 0x11ce 16 v1.1 +min_odd_inc_mono 0x11d0 16 v1.1 +max_odd_inc_mono 0x11d2 16 v1.1 +min_even_inc_bc2 0x11d4 16 v1.1 +max_even_inc_bc2 0x11d6 16 v1.1 +min_odd_inc_bc2 0x11d8 16 v1.1 +max_odd_inc_bc2 0x11da 16 v1.1 +min_even_inc_mono_bc2 0x11dc 16 v1.1 +max_even_inc_mono_bc2 0x11de 16 v1.1 +min_odd_inc_mono_bc2 0x11f0 16 v1.1 +max_odd_inc_mono_bc2 0x11f2 16 v1.1 + +# image scaling limit parameters +scaling_capability 0x1200 16 +- e none 0 +- e horizontal 1 +- e reserved 2 +scaler_m_min 0x1204 16 +scaler_m_max 0x1206 16 +scaler_n_min 0x1208 16 +scaler_n_max 0x120a 16 +digital_crop_capability 0x120e +- e none 0 +- e input_crop 1 + +# hdr limit registers +hdr_capability_1 0x1210 +- b 2x2_binning 0 +- b combined_analog_gain 1 +- b separate_analog_gain 2 +- b upscaling 3 +- b reset_sync 4 +- b direct_short_exp_timing 5 +- b direct_short_exp_synthesis 6 +min_hdr_bit_depth 0x1211 +hdr_resolution_sub_types 0x1212 +hdr_resolution_sub_type(n) 0x1213 +- l n 0 1 1 +- f row 0 3 +- f column 4 7 +hdr_capability_2 0x121b +- b combined_digital_gain 0 +- b separate_digital_gain 1 +- b timing_mode 3 +- b synthesis_mode 4 +max_hdr_bit_depth 0x121c + +# usl capability register +usl_support_capability 0x1230 v1.1 +- b clock_tree 0 +- b rev_clock_tree 1 +- b rev_clock_calc 2 +usl_clock_mode_d_capability 0x1231 v1.1 +- b cont_clock_standby 0 +- b cont_clock_vblank 1 +- b cont_clock_hblank 2 +- b noncont_clock_standby 3 +- b noncont_clock_vblank 4 +- b noncont_clock_hblank 5 +min_op_sys_clk_div_rev 0x1234 v1.1 +max_op_sys_clk_div_rev 0x1236 v1.1 +min_op_pix_clk_div_rev 0x1238 v1.1 +max_op_pix_clk_div_rev 0x123a v1.1 +min_op_sys_clk_freq_rev_mhz 0x123c 32 v1.1 float_ireal +max_op_sys_clk_freq_rev_mhz 0x1240 32 v1.1 float_ireal +min_op_pix_clk_freq_rev_mhz 0x1244 32 v1.1 float_ireal +max_op_pix_clk_freq_rev_mhz 0x1248 32 v1.1 float_ireal +max_bitrate_rev_d_mode_mbps 0x124c 32 v1.1 ireal +max_symrate_rev_c_mode_msps 0x1250 32 v1.1 ireal + +# image compression capability registers +compression_capability 0x1300 +- b dpcm_pcm_simple 0 + +# test mode capability registers +test_mode_capability 0x1310 16 +- b solid_color 0 +- b color_bars 1 +- b fade_to_grey 2 +- b pn9 3 +- b color_tile 5 +pn9_data_format1 0x1312 +pn9_data_format2 0x1313 +pn9_data_format3 0x1314 +pn9_data_format4 0x1315 +pn9_misc_capability 0x1316 +- f num_pixels 0 2 +- b compression 3 +test_pattern_capability 0x1317 v1.1 +- b no_repeat 1 +pattern_size_div_m1 0x1318 v1.1 + +# fifo capability registers +fifo_support_capability 0x1502 +- e none 0 +- e derating 1 +- e derating_overrating 2 + +# csi-2 capability registers +phy_ctrl_capability 0x1600 +- b auto_phy_ctl 0 +- b ui_phy_ctl 1 +- b dphy_time_ui_reg_1_ctl 2 +- b dphy_time_ui_reg_2_ctl 3 +- b dphy_time_ctl 4 +- b dphy_ext_time_ui_reg_1_ctl 5 +- b dphy_ext_time_ui_reg_2_ctl 6 +- b dphy_ext_time_ctl 7 +csi_dphy_lane_mode_capability 0x1601 +- b 1_lane 0 +- b 2_lane 1 +- b 3_lane 2 +- b 4_lane 3 +- b 5_lane 4 +- b 6_lane 5 +- b 7_lane 6 +- b 8_lane 7 +csi_signaling_mode_capability 0x1602 +- b csi_dphy 2 +- b csi_cphy 3 +fast_standby_capability 0x1603 +- e no_frame_truncation 0 +- e frame_truncation 1 +csi_address_control_capability 0x1604 +- b cci_addr_change 0 +- b 2nd_cci_addr 1 +- b sw_changeable_2nd_cci_addr 2 +data_type_capability 0x1605 +- b dpcm_programmable 0 +- b bottom_embedded_dt_programmable 1 +- b bottom_embedded_vc_programmable 2 +- b ext_vc_range 3 +csi_cphy_lane_mode_capability 0x1606 +- b 1_lane 0 +- b 2_lane 1 +- b 3_lane 2 +- b 4_lane 3 +- b 5_lane 4 +- b 6_lane 5 +- b 7_lane 6 +- b 8_lane 7 +emb_data_capability 0x1607 v1.1 +- b two_bytes_per_raw16 0 +- b two_bytes_per_raw20 1 +- b two_bytes_per_raw24 2 +- b no_one_byte_per_raw16 3 +- b no_one_byte_per_raw20 4 +- b no_one_byte_per_raw24 5 +max_per_lane_bitrate_lane_d_mode_mbps(n) 0x1608 32 ireal +- l n 0 7 4 4,0x32 +temp_sensor_capability 0x1618 +- b supported 0 +- b CCS_format 1 +- b reset_0x80 2 +max_per_lane_bitrate_lane_c_mode_mbps(n) 0x161a 32 ireal +- l n 0 7 4 4,0x30 +dphy_equalization_capability 0x162b +- b equalization_ctrl 0 +- b eq1 1 +- b eq2 2 +cphy_equalization_capability 0x162c +- b equalization_ctrl 0 +dphy_preamble_capability 0x162d +- b preamble_seq_ctrl 0 +dphy_ssc_capability 0x162e +- b supported 0 +cphy_calibration_capability 0x162f +- b manual 0 +- b manual_streaming 1 +- b format_1_ctrl 2 +- b format_2_ctrl 3 +- b format_3_ctrl 4 +dphy_calibration_capability 0x1630 +- b manual 0 +- b manual_streaming 1 +- b alternate_seq 2 +phy_ctrl_capability_2 0x1631 +- b tgr_length 0 +- b tgr_preamble_prog_seq 1 +- b extra_cphy_manual_timing 2 +- b clock_based_manual_cdphy 3 +- b clock_based_manual_dphy 4 +- b clock_based_manual_cphy 5 +- b manual_lp_dphy 6 +- b manual_lp_cphy 7 +lrte_cphy_capability 0x1632 +- b pdq_short 0 +- b spacer_short 1 +- b pdq_long 2 +- b spacer_long 3 +- b spacer_no_pdq 4 +lrte_dphy_capability 0x1633 +- b pdq_short_opt1 0 +- b spacer_short_opt1 1 +- b pdq_long_opt1 2 +- b spacer_long_opt1 3 +- b spacer_short_opt2 4 +- b spacer_long_opt2 5 +- b spacer_no_pdq_opt1 6 +- b spacer_variable_opt2 7 +alps_capability_dphy 0x1634 +- e lvlp_not_supported 0 0x3 +- e lvlp_supported 1 0x3 +- e controllable_lvlp 2 0x3 +alps_capability_cphy 0x1635 +- e lvlp_not_supported 0 0x3 +- e lvlp_supported 1 0x3 +- e controllable_lvlp 2 0x3 +- e alp_not_supported 0xc 0xc +- e alp_supported 0xd 0xc +- e controllable_alp 0xe 0xc +scrambling_capability 0x1636 +- b scrambling_supported 0 +- f max_seeds_per_lane_c 1 2 +- e 1 0 +- e 4 3 +- f num_seed_regs 3 5 +- e 0 0 +- e 1 1 +- e 4 4 +- b num_seed_per_lane 6 +dphy_manual_constant 0x1637 +cphy_manual_constant 0x1638 +CSI2_interface_capability_misc 0x1639 v1.1 +- b eotp_short_pkt_opt2 0 +PHY_ctrl_capability_3 0x165c v1.1 +- b dphy_timing_not_multiple 0 +- b dphy_min_timing_value_1 1 +- b twakeup_supported 2 +- b tinit_supported 3 +- b ths_exit_supported 4 +- b cphy_timing_not_multiple 5 +- b cphy_min_timing_value_1 6 +dphy_sf 0x165d v1.1 +cphy_sf 0x165e v1.1 +- f twakeup 0 3 +- f tinit 4 7 +dphy_limits_1 0x165f v1.1 +- f ths_prepare 0 3 +- f ths_zero 4 7 +dphy_limits_2 0x1660 v1.1 +- f ths_trail 0 3 +- f tclk_trail_min 4 7 +dphy_limits_3 0x1661 v1.1 +- f tclk_prepare 0 3 +- f tclk_zero 4 7 +dphy_limits_4 0x1662 v1.1 +- f tclk_post 0 3 +- f tlpx 4 7 +dphy_limits_5 0x1663 v1.1 +- f ths_exit 0 3 +- f twakeup 4 7 +dphy_limits_6 0x1664 v1.1 +- f tinit 0 3 +cphy_limits_1 0x1665 v1.1 +- f t3_prepare_max 0 3 +- f t3_lpx_max 4 7 +cphy_limits_2 0x1666 v1.1 +- f ths_exit_max 0 3 +- f twakeup_max 4 7 +cphy_limits_3 0x1667 v1.1 +- f tinit_max 0 3 + +# binning capability registers +min_frame_length_lines_bin 0x1700 16 +max_frame_length_lines_bin 0x1702 16 +min_line_length_pck_bin 0x1704 16 +max_line_length_pck_bin 0x1706 16 +min_line_blanking_pck_bin 0x1708 16 +fine_integration_time_min_bin 0x170a 16 +fine_integration_time_max_margin_bin 0x170c 16 +binning_capability 0x1710 +- e unsupported 0 +- e binning_then_subsampling 1 +- e subsampling_then_binning 2 +binning_weighting_capability 0x1711 +- b averaged 0 +- b summed 1 +- b bayer_corrected 2 +- b module_specific_weight 3 +binning_sub_types 0x1712 +binning_sub_type(n) 0x1713 +- l n 0 63 1 +- f row 0 3 +- f column 4 7 +binning_weighting_mono_capability 0x1771 v1.1 +- b averaged 0 +- b summed 1 +- b bayer_corrected 2 +- b module_specific_weight 3 +binning_sub_types_mono 0x1772 v1.1 +binning_sub_type_mono(n) 0x1773 v1.1 f +- l n 0 63 1 + +# data transfer interface capability registers +data_transfer_if_capability 0x1800 +- b supported 0 +- b polling 2 + +# sensor correction capability registers +shading_correction_capability 0x1900 +- b color_shading 0 +- b luminance_correction 1 +green_imbalance_capability 0x1901 +- b supported 0 +module_specific_correction_capability 0x1903 +defect_correction_capability 0x1904 16 +- b mapped_defect 0 +- b dynamic_couplet 2 +- b dynamic_single 5 +- b combined_dynamic 8 +defect_correction_capability_2 0x1906 16 +- b dynamic_triplet 3 +nf_capability 0x1908 +- b luma 0 +- b chroma 1 +- b combined 2 + +# optical black readout capability registers +ob_readout_capability 0x1980 +- b controllable_readout 0 +- b visible_pixel_readout 1 +- b different_vc_readout 2 +- b different_dt_readout 3 +- b prog_data_format 4 + +# color feedback capability registers +color_feedback_capability 0x1987 +- b kelvin 0 +- b awb_gain 1 + +# cfa pattern capability registers +CFA_pattern_capability 0x1990 v1.1 +- e bayer 0 +- e monochrome 1 +- e 4x4_quad_bayer 2 +- e vendor_specific 3 +CFA_pattern_conversion_capability 0x1991 v1.1 +- b bayer 0 + +# timer capability registers +flash_mode_capability 0x1a02 +- b single_strobe 0 +sa_strobe_mode_capability 0x1a03 +- b fixed_width 0 +- b edge_ctrl 1 + +# soft reset capability registers +reset_max_delay 0x1a10 v1.1 +reset_min_time 0x1a11 v1.1 + +# pdaf capability registers +pdaf_capability_1 0x1b80 +- b supported 0 +- b processed_bottom_embedded 1 +- b processed_interleaved 2 +- b raw_bottom_embedded 3 +- b raw_interleaved 4 +- b visible_pdaf_correction 5 +- b vc_interleaving 6 +- b dt_interleaving 7 +pdaf_capability_2 0x1b81 +- b ROI 0 +- b after_digital_crop 1 +- b ctrl_retimed 2 + +# bracketing interface capability registers +bracketing_lut_capability_1 0x1c00 +- b coarse_integration 0 +- b global_analog_gain 1 +- b flash 4 +- b global_digital_gain 5 +- b alternate_global_analog_gain 6 +bracketing_lut_capability_2 0x1c01 +- b single_bracketing_mode 0 +- b looped_bracketing_mode 1 +bracketing_lut_size 0x1c02 diff --git a/Documentation/driver-api/media/drivers/ccs/mk-ccs-regs b/Documentation/driver-api/media/drivers/ccs/mk-ccs-regs new file mode 100755 index 000000000000..3d6a2a7aac3a --- /dev/null +++ b/Documentation/driver-api/media/drivers/ccs/mk-ccs-regs @@ -0,0 +1,433 @@ +#!/usr/bin/perl -w +# SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause +# Copyright (C) 2019--2020 Intel Corporation + +use Getopt::Long qw(:config no_ignore_case); +use File::Basename; + +my $ccsregs = "ccs-regs.txt"; +my $header; +my $regarray; +my $limitc; +my $limith; +my $kernel; +my $help; + +GetOptions("ccsregs|c=s" => \$ccsregs, + "header|e=s" => \$header, + "regarray|r=s" => \$regarray, + "limitc|l=s" => \$limitc, + "limith|L=s" => \$limith, + "kernel|k" => \$kernel, + "help|h" => \$help) or die "can't parse options"; + +$help = 1 if ! defined $header || ! defined $limitc || ! defined $limith; + +if (defined $help) { + print <\n#include \n"; +my $uint32_t = ! defined $kernel ? 'uint32_t' : 'u32'; +my $uint16_t = ! defined $kernel ? 'uint16_t' : 'u16'; + +open(my $R, "< $ccsregs") or die "can't open $ccsregs"; + +open(my $H, "> $header") or die "can't open $header"; +my $A; +if (defined $regarray) { + open($A, "> $regarray") or die "can't open $regarray"; +} +open(my $LC, "> $limitc") or die "can't open $limitc"; +open(my $LH, "> $limith") or die "can't open $limith"; + +my %this; + +sub is_limit_reg($) { + my $addr = hex $_[0]; + + return 0 if $addr < 0x40; # weed out status registers + return 0 if $addr >= 0x100 && $addr < 0xfff; # weed out configuration registers + + return 1; +} + +my $uc_header = basename uc $header; +$uc_header =~ s/[^A-Z0-9]/_/g; + +my $copyright = "/* Copyright (C) 2019--2020 Intel Corporation */\n"; +my $license = "SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause"; + +for my $fh ($A, $LC) { + print $fh "// $license\n$copyright\n" if defined $fh; +} + +for my $fh ($H, $LH) { + print $fh "/* $license */\n$copyright\n"; +} + +sub bit_def($) { + my $bit = shift @_; + + return "BIT($bit)" if defined $kernel; + return "(1U << $bit)" if $bit =~ /^[a-zA-Z0-9_]+$/; + return "(1U << ($bit))"; +} + +print $H <\n\n" if defined $kernel; + +print $H < +#include +#include "ccs-extra.h" +#include "ccs-regs.h" + +EOF + if defined $A; + +my $uc_limith = basename uc $limith; +$uc_limith =~ s/[^A-Z0-9]/_/g; + +print $LH <{elsize}; + my $h = $this->{argparams}; + + foreach my $arg (@{$this->{args}}) { + my $apref = $h->{$arg}; + + $size *= $apref->{max} - $apref->{min} + 1; + } + + return $size; +} + +sub print_args($$$) { + my ($this, $postfix, $is_same_reg) = @_; + my ($args, $argparams, $name) = + ($this->{args}, $this->{argparams}, $this->{name}); + my $varname = "ccs_reg_arg_" . (lc $name) . $postfix; + my @mins; + my @sorted_args = @{$this->{sorted_args}}; + my $lim_arg; + my $size = arr_size($this); + + $argdescs .= "static const struct ccs_reg_arg " . $varname . "[] = {\n"; + + foreach my $sorted_arg (@sorted_args) { + push @mins, $argparams->{$sorted_arg}->{min}; + } + + foreach my $sorted_arg (@sorted_args) { + my $h = $argparams->{$sorted_arg}; + + $argdescs .= "\t{ \"$sorted_arg\", $h->{min}, $h->{max}, $h->{elsize} },\n"; + + $lim_arg .= defined $lim_arg ? ", $h->{min}" : "$h->{min}"; + } + + $argdescs .= "};\n\n"; + + $reglist .= "\t{ CCS_R_" . (uc $name) . "(" . (join ",", (@mins)) . + "), $size, sizeof($varname) / sizeof(*$varname)," . + " \"" . (lc $name) . "\", $varname },\n"; + + print $LC tabconv sprintf "\t{ CCS_R_" . (uc $name) . "($lim_arg), " . + $size . ", " . ($is_same_reg ? "CCS_L_FL_SAME_REG" : "0") . + ", \"$name" . (defined $this->{discontig} ? " $lim_arg" : "") . "\" },\n" + if is_limit_reg $this->{base_addr}; +} + +my $hdr_data; + +while (<$R>) { + chop; + s/^\s*//; + next if /^[#;]/ || /^$/; + if (s/^-\s*//) { + if (s/^b\s*//) { + my ($bit, $addr) = split /\t+/; + $bit = uc $bit; + $hdr_data .= sprintf "#define %-62s %s", "CCS_" . (uc ${this{name}}) ."_$bit", bit_def($addr) . "\n"; + } elsif (s/^f\s*//) { + s/[,\.-]/_/g; + my @a = split /\s+/; + my ($msb, $lsb, $this_field) = reverse @a; + @a = ( { "name" => "SHIFT", "addr" => $lsb, "fmt" => "%uU", }, + { "name" => "MASK", "addr" => (1 << ($msb + 1)) - 1 - ((1 << $lsb) - 1), "fmt" => "0x%" . join(".", ($this{"elsize"} >> 2) x 2) . "x" } ); + $this{"field"} = $this_field; + foreach my $ar (@a) { + #print $ar->{fmt}."\n"; + $hdr_data .= sprintf "#define %-62s " . $ar->{"fmt"} . "\n", "CCS_" . (uc $this{"name"}) . (defined $this_field ? "_" . uc $this_field : "") . "_" . $ar->{"name"}, $ar->{"addr"} . "\n"; + } + } elsif (s/^e\s*//) { + s/[,\.-]/_/g; + my ($enum, $addr) = split /\s+/; + $enum = uc $enum; + $hdr_data .= sprintf "#define %-62s %s", "CCS_" . (uc ${this{name}}) . (defined $this{"field"} ? "_" . uc $this{"field"} : "") ."_$enum", $addr . ($addr =~ /0x/i ? "" : "U") . "\n"; + } elsif (s/^l\s*//) { + my ($arg, $min, $max, $elsize, @discontig) = split /\s+/; + my $size; + + foreach my $num ($min, $max) { + $num = hex $num if $num =~ /0x/i; + } + + $hdr_data .= sprintf "#define %-62s %s", "CCS_LIM_" . (uc ${this{name}} . "_MIN_$arg"), $min . ($min =~ /0x/i ? "" : "U") . "\n"; + $hdr_data .= sprintf "#define %-62s %s", "CCS_LIM_" . (uc ${this{name}} . "_MAX_$arg"), $max . ($max =~ /0x/i ? "" : "U") . "\n"; + + my $h = $this{argparams}; + + $h->{$arg} = { "min" => $min, + "max" => $max, + "elsize" => $elsize =~ /^0x/ ? hex $elsize : $elsize, + "discontig" => \@discontig }; + + $this{discontig} = $arg if @discontig; + + next if $#{$this{args}} + 1 != scalar keys %{$this{argparams}}; + + my $reg_formula = "($this{addr}"; + my $lim_formula; + + foreach my $arg (@{$this{args}}) { + my $d = $h->{$arg}->{discontig}; + my $times = $h->{$arg}->{elsize} != 1 ? + " * " . $h->{$arg}->{elsize} : ""; + + if (@$d) { + my ($lim, $offset) = split /,/, $d->[0]; + + $reg_formula .= " + (($arg) < $lim ? ($arg)$times : $offset + (($arg) - $lim)$times)"; + } else { + $reg_formula .= " + ($arg)$times"; + } + + $lim_formula .= (defined $lim_formula ? " + " : "") . "($arg)$times"; + } + + $reg_formula .= ")\n"; + $lim_formula =~ s/^\(([a-z0-9]+)\)$/$1/i; + + print $H tabconv sprintf("#define %-62s %s", "CCS_R_" . (uc $this{name}) . + $this{arglist}, $reg_formula); + + print $H tabconv $hdr_data; + undef $hdr_data; + + # Sort arguments in descending order by size + @{$this{sorted_args}} = sort { + $h->{$a}->{elsize} <= $h->{$b}->{elsize} + } @{$this{args}}; + + if (defined $this{discontig}) { + my $da = $this{argparams}->{$this{discontig}}; + my ($first_discontig) = split /,/, $da->{discontig}->[0]; + my $max = $da->{max}; + + $da->{max} = $first_discontig - 1; + print_args(\%this, "", 0); + + $da->{min} = $da->{max} + 1; + $da->{max} = $max; + print_args(\%this, $first_discontig, 1); + } else { + print_args(\%this, "", 0); + } + + next unless is_limit_reg $this{base_addr}; + + print $LH tabconv sprintf "#define %-63s%s\n", + "CCS_L_" . (uc $this{name}) . "_OFFSET(" . + (join ", ", @{$this{args}}) . ")", "($lim_formula)"; + } + + if (! @{$this{args}}) { + print $H tabconv($hdr_data); + undef $hdr_data; + } + + next; + } + + my ($name, $addr, @flags) = split /\t+/, $_; + my $args = []; + + my $sp; + + ($name, $addr, $args) = name_split($name, $addr) if /\(.*\)/; + + $name =~ s/[,\.-]/_/g; + + my $flagstring = ""; + my $size = elem_size(@flags); + $flagstring .= "| CCS_FL_16BIT " if $size eq "2"; + $flagstring .= "| CCS_FL_32BIT " if $size eq "4"; + $flagstring .= "| CCS_FL_FLOAT_IREAL " if grep /^float_ireal$/, @flags; + $flagstring .= "| CCS_FL_IREAL " if grep /^ireal$/, @flags; + $flagstring =~ s/^\| //; + $flagstring =~ s/ $//; + $flagstring = "($flagstring)" if $flagstring =~ /\|/; + my $base_addr = $addr; + $addr = "($addr | $flagstring)" if $flagstring ne ""; + + my $arglist = @$args ? "(" . (join ", ", @$args) . ")" : ""; + $hdr_data .= sprintf "#define %-62s %s\n", "CCS_R_" . (uc $name), $addr + if !@$args; + + $name =~ s/\(.*//; + + %this = ( name => $name, + addr => $addr, + base_addr => $base_addr, + argparams => {}, + args => $args, + arglist => $arglist, + elsize => $size, + ); + + if (!@$args) { + $reglist .= "\t{ CCS_R_" . (uc $name) . ", 1, 0, \"" . (lc $name) . "\", NULL },\n"; + print $H tabconv $hdr_data; + undef $hdr_data; + + print $LC tabconv sprintf "\t{ CCS_R_" . (uc $name) . ", " . + $this{elsize} . ", 0, \"$name\" },\n" + if is_limit_reg $this{base_addr}; + } + + print $LH tabconv sprintf "#define %-63s%s\n", + "CCS_L_" . (uc $this{name}), $limitcount++ + if is_limit_reg $this{base_addr}; +} + +if (defined $A) { + print $A $argdescs, $reglist; + + print $A "\t{ 0 }\n"; + + print $A "};\n"; +} + +print $H "\n#endif /* __${uc_header}__ */\n"; + +print $LH tabconv sprintf "#define %-63s%s\n", "CCS_L_LAST", $limitcount; + +print $LH "\n#endif /* __${uc_limith}__ */\n"; + +print $LC "\t{ 0 } /* Guardian */\n"; +print $LC "};\n"; + +close($R); +close($H); +close($A) if defined $A; +close($LC); +close($LH); diff --git a/MAINTAINERS b/MAINTAINERS index a22392994667..0864fe0f945a 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -16108,6 +16108,7 @@ M: Sakari Ailus L: linux-media@vger.kernel.org S: Maintained F: Documentation/devicetree/bindings/media/i2c/nokia,smia.txt +F: Documentation/driver-api/media/drivers/ccs/ F: drivers/media/i2c/smiapp-pll.c F: drivers/media/i2c/smiapp-pll.h F: drivers/media/i2c/smiapp/ -- cgit v1.2.3-59-g8ed1b From 4ad97bfb1a7ee826b7f253750ba47f2e991c12ec Mon Sep 17 00:00:00 2001 From: Sakari Ailus Date: Thu, 5 Nov 2020 17:08:23 +0100 Subject: media: Documentation: ccs: Add CCS driver documentation Document the MIPI CCS driver and the C register definition generator. Signed-off-by: Sakari Ailus Signed-off-by: Mauro Carvalho Chehab --- Documentation/driver-api/media/drivers/ccs/ccs.rst | 82 ++++++++++++++++++++++ Documentation/driver-api/media/drivers/index.rst | 1 + 2 files changed, 83 insertions(+) create mode 100644 Documentation/driver-api/media/drivers/ccs/ccs.rst (limited to 'Documentation/driver-api') diff --git a/Documentation/driver-api/media/drivers/ccs/ccs.rst b/Documentation/driver-api/media/drivers/ccs/ccs.rst new file mode 100644 index 000000000000..9164c9fa8b42 --- /dev/null +++ b/Documentation/driver-api/media/drivers/ccs/ccs.rst @@ -0,0 +1,82 @@ +.. SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause + +.. include:: + +MIPI CCS camera sensor driver +============================= + +The MIPI CCS camera sensor driver is a generic driver for `MIPI CCS +`_ compliant +camera sensors. It exposes three sub-devices representing the pixel array, +the binner and the scaler. + +As the capabilities of individual devices vary, the driver exposes +interfaces based on the capabilities that exist in hardware. + +Pixel Array sub-device +---------------------- + +The pixel array sub-device represents the camera sensor's pixel matrix, as well +as analogue crop functionality present in many compliant devices. The analogue +crop is configured using the ``V4L2_SEL_TGT_CROP`` on the source pad (0) of the +entity. The size of the pixel matrix can be obtained by getting the +``V4L2_SEL_TGT_NATIVE_SIZE`` target. + +Binner +------ + +The binner sub-device represents the binning functionality on the sensor. For +that purpose, selection target ``V4L2_SEL_TGT_COMPOSE`` is supported on the +sink pad (0). + +Additionally, if a device has no scaler or digital crop functionality, the +source pad (1) expses another digital crop selection rectangle that can only +crop at the end of the lines and frames. + +Scaler +------ + +The scaler sub-device represents the digital crop and scaling functionality of +the sensor. The V4L2 selection target ``V4L2_SEL_TGT_CROP`` is used to +configure the digital crop on the sink pad (0) when digital crop is supported. +Scaling is configured using selection target ``V4L2_SEL_TGT_COMPOSE`` on the +sink pad (0) as well. + +Additionally, if the scaler sub-device exists, its source pad (1) exposes +another digital crop selection rectangle that can only crop at the end of the +lines and frames. + +Digital and analogue crop +------------------------- + +Digital crop functionality is referred to as cropping that effectively works by +dropping some data on the floor. Analogue crop, on the other hand, means that +the cropped information is never retrieved. In case of camera sensors, the +analogue data is never read from the pixel matrix that are outside the +configured selection rectangle that designates crop. The difference has an +effect in device timing and likely also in power consumption. + +Register definition generator +----------------------------- + +The ccs-regs.txt file contains MIPI CCS register definitions that are used +to produce C source code files for definitions that can be better used by +programs written in C language. As there are many dependencies between the +produced files, please do not modify them manually as it's error-prone and +in vain, but instead change the script producing them. + +Usage +~~~~~ + +Conventionally the script is called this way to update the CCS driver +definitions: + +.. code-block:: none + + $ Documentation/driver-api/media/drivers/ccs/mk-ccs-regs -k \ + -e drivers/media/i2c/ccs/ccs-regs.h \ + -L drivers/media/i2c/ccs/ccs-limits.h \ + -l drivers/media/i2c/ccs/ccs-limits.c \ + -c Documentation/driver-api/media/drivers/ccs/ccs-regs.txt + +**Copyright** |copy| 2020 Intel Corporation diff --git a/Documentation/driver-api/media/drivers/index.rst b/Documentation/driver-api/media/drivers/index.rst index eb7011782863..426cda633bf0 100644 --- a/Documentation/driver-api/media/drivers/index.rst +++ b/Documentation/driver-api/media/drivers/index.rst @@ -26,6 +26,7 @@ Video4Linux (V4L) drivers tuners vimc-devel zoran + ccs/ccs Digital TV drivers -- cgit v1.2.3-59-g8ed1b From 3bf10ebc6d12503edb3430234341491bdc9fff09 Mon Sep 17 00:00:00 2001 From: Sakari Ailus Date: Wed, 2 Dec 2020 15:16:57 +0100 Subject: media: Documentation: ccs: Rename ccs-regs.txt as ccs-regs.asc As documentation used to be in .txt files before converting to ReST, rename ccs-regs.txt to avoid it being taken as documentation that pre-dates ReST conversion and so target for further conversion to ReST. Signed-off-by: Sakari Ailus Signed-off-by: Mauro Carvalho Chehab --- .../driver-api/media/drivers/ccs/ccs-regs.asc | 1041 ++++++++++++++++++++ .../driver-api/media/drivers/ccs/ccs-regs.txt | 1041 -------------------- Documentation/driver-api/media/drivers/ccs/ccs.rst | 4 +- .../driver-api/media/drivers/ccs/mk-ccs-regs | 4 +- 4 files changed, 1045 insertions(+), 1045 deletions(-) create mode 100644 Documentation/driver-api/media/drivers/ccs/ccs-regs.asc delete mode 100644 Documentation/driver-api/media/drivers/ccs/ccs-regs.txt (limited to 'Documentation/driver-api') diff --git a/Documentation/driver-api/media/drivers/ccs/ccs-regs.asc b/Documentation/driver-api/media/drivers/ccs/ccs-regs.asc new file mode 100644 index 000000000000..93f0131aa304 --- /dev/null +++ b/Documentation/driver-api/media/drivers/ccs/ccs-regs.asc @@ -0,0 +1,1041 @@ +# Copyright (C) 2019--2020 Intel Corporation +# SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause + +# register rflags +# - f field LSB MSB rflags +# - e enum value # after a field +# - e enum value [LSB MSB] +# - b bool bit +# - l arg name min max elsize [discontig...] +# +# rflags +# 8, 16, 32 register bits (default is 8) +# v1.1 defined in version 1.1 +# f formula +# float_ireal iReal or IEEE 754; 32 bits +# ireal unsigned iReal + +# general status registers +module_model_id 0x0000 16 +module_revision_number_major 0x0002 8 +frame_count 0x0005 8 +pixel_order 0x0006 8 +- e GRBG 0 +- e RGGB 1 +- e BGGR 2 +- e GBRG 3 +MIPI_CCS_version 0x0007 8 +- e v1_0 0x10 +- e v1_1 0x11 +- f major 4 7 +- f minor 0 3 +data_pedestal 0x0008 16 +module_manufacturer_id 0x000e 16 +module_revision_number_minor 0x0010 8 +module_date_year 0x0012 8 +module_date_month 0x0013 8 +module_date_day 0x0014 8 +module_date_phase 0x0015 8 +- f 0 2 +- e ts 0 +- e es 1 +- e cs 2 +- e mp 3 +sensor_model_id 0x0016 16 +sensor_revision_number 0x0018 8 +sensor_firmware_version 0x001a 8 +serial_number 0x001c 32 +sensor_manufacturer_id 0x0020 16 +sensor_revision_number_16 0x0022 16 + +# frame format description registers +frame_format_model_type 0x0040 8 +- e 2-byte 1 +- e 4-byte 2 +frame_format_model_subtype 0x0041 8 +- f rows 0 3 +- f columns 4 7 +frame_format_descriptor(n) 0x0042 16 f +- l n 0 14 2 +- f pixels 0 11 +- f pcode 12 15 +- e embedded 1 +- e dummy_pixel 2 +- e black_pixel 3 +- e dark_pixel 4 +- e visible_pixel 5 +- e manuf_specific_0 8 +- e manuf_specific_1 9 +- e manuf_specific_2 10 +- e manuf_specific_3 11 +- e manuf_specific_4 12 +- e manuf_specific_5 13 +- e manuf_specific_6 14 +frame_format_descriptor_4(n) 0x0060 32 f +- l n 0 7 4 +- f pixels 0 15 +- f pcode 28 31 +- e embedded 1 +- e dummy_pixel 2 +- e black_pixel 3 +- e dark_pixel 4 +- e visible_pixel 5 +- e manuf_specific_0 8 +- e manuf_specific_1 9 +- e manuf_specific_2 10 +- e manuf_specific_3 11 +- e manuf_specific_4 12 +- e manuf_specific_5 13 +- e manuf_specific_6 14 + +# analog gain description registers +analog_gain_capability 0x0080 16 +- e global 0 +- e alternate_global 2 +analog_gain_code_min 0x0084 16 +analog_gain_code_max 0x0086 16 +analog_gain_code_step 0x0088 16 +analog_gain_type 0x008a 16 +analog_gain_m0 0x008c 16 +analog_gain_c0 0x008e 16 +analog_gain_m1 0x0090 16 +analog_gain_c1 0x0092 16 +analog_linear_gain_min 0x0094 16 v1.1 +analog_linear_gain_max 0x0096 16 v1.1 +analog_linear_gain_step_size 0x0098 16 v1.1 +analog_exponential_gain_min 0x009a 16 v1.1 +analog_exponential_gain_max 0x009c 16 v1.1 +analog_exponential_gain_step_size 0x009e 16 v1.1 + +# data format description registers +data_format_model_type 0x00c0 8 +- e normal 1 +- e extended 2 +data_format_model_subtype 0x00c1 8 +- f rows 0 3 +- f columns 4 7 +data_format_descriptor(n) 0x00c2 16 f +- l n 0 15 2 +- f compressed 0 7 +- f uncompressed 8 15 + +# general set-up registers +mode_select 0x0100 8 +- e software_standby 0 +- e streaming 1 +image_orientation 0x0101 8 +- b horizontal_mirror 0 +- b vertical_flip 1 +software_reset 0x0103 8 +- e off 0 +- e on 1 +grouped_parameter_hold 0x0104 8 +mask_corrupted_frames 0x0105 8 +- e allow 0 +- e mask 1 +fast_standby_ctrl 0x0106 8 +- e complete_frames 0 +- e frame_truncation 1 +CCI_address_ctrl 0x0107 8 +2nd_CCI_if_ctrl 0x0108 8 +- b enable 0 +- b ack 1 +2nd_CCI_address_ctrl 0x0109 8 +CSI_channel_identifier 0x0110 8 +CSI_signaling_mode 0x0111 8 +- e csi_2_dphy 2 +- e csi_2_cphy 3 +CSI_data_format 0x0112 16 +CSI_lane_mode 0x0114 8 +DPCM_Frame_DT 0x011d 8 +Bottom_embedded_data_DT 0x011e 8 +Bottom_embedded_data_VC 0x011f 8 + +gain_mode 0x0120 8 +- e global 0 +- e alternate 1 +ADC_bit_depth 0x0121 8 +emb_data_ctrl 0x0122 v1.1 +- b raw8_packing_for_raw16 0 +- b raw10_packing_for_raw20 1 +- b raw12_packing_for_raw24 2 + +GPIO_TRIG_mode 0x0130 8 +extclk_frequency_mhz 0x0136 16 ireal +temp_sensor_ctrl 0x0138 8 +- b enable 0 +temp_sensor_mode 0x0139 8 +temp_sensor_output 0x013a 8 + +# integration time registers +fine_integration_time 0x0200 16 +coarse_integration_time 0x0202 16 + +# analog gain registers +analog_gain_code_global 0x0204 16 +analog_linear_gain_global 0x0206 16 v1.1 +analog_exponential_gain_global 0x0208 16 v1.1 + +# digital gain registers +digital_gain_global 0x020e 16 + +# hdr control registers +Short_analog_gain_global 0x0216 16 +Short_digital_gain_global 0x0218 16 + +HDR_mode 0x0220 8 +- b enabled 0 +- b separate_analog_gain 1 +- b upscaling 2 +- b reset_sync 3 +- b timing_mode 4 +- b exposure_ctrl_direct 5 +- b separate_digital_gain 6 +HDR_resolution_reduction 0x0221 8 +- f row 0 3 +- f column 4 7 +Exposure_ratio 0x0222 8 +HDR_internal_bit_depth 0x0223 8 +Direct_short_integration_time 0x0224 16 +Short_analog_linear_gain_global 0x0226 16 v1.1 +Short_analog_exponential_gain_global 0x0228 16 v1.1 + +# clock set-up registers +vt_pix_clk_div 0x0300 16 +vt_sys_clk_div 0x0302 16 +pre_pll_clk_div 0x0304 16 +#vt_pre_pll_clk_div 0x0304 16 +pll_multiplier 0x0306 16 +#vt_pll_multiplier 0x0306 16 +op_pix_clk_div 0x0308 16 +op_sys_clk_div 0x030a 16 +op_pre_pll_clk_div 0x030c 16 +op_pll_multiplier 0x031e 16 +pll_mode 0x0310 8 +- f 0 0 +- e single 0 +- e dual 1 +op_pix_clk_div_rev 0x0312 16 v1.1 +op_sys_clk_div_rev 0x0314 16 v1.1 + +# frame timing registers +frame_length_lines 0x0340 16 +line_length_pck 0x0342 16 + +# image size registers +x_addr_start 0x0344 16 +y_addr_start 0x0346 16 +x_addr_end 0x0348 16 +y_addr_end 0x034a 16 +x_output_size 0x034c 16 +y_output_size 0x034e 16 + +# timing mode registers +Frame_length_ctrl 0x0350 8 +- b automatic 0 +Timing_mode_ctrl 0x0352 8 +- b manual_readout 0 +- b delayed_exposure 1 +Start_readout_rs 0x0353 8 +- b manual_readout_start 0 +Frame_margin 0x0354 16 + +# sub-sampling registers +x_even_inc 0x0380 16 +x_odd_inc 0x0382 16 +y_even_inc 0x0384 16 +y_odd_inc 0x0386 16 + +# monochrome readout registers +monochrome_en 0x0390 v1.1 +- e enabled 0 + +# image scaling registers +Scaling_mode 0x0400 16 +- e no_scaling 0 +- e horizontal 1 +scale_m 0x0404 16 +scale_n 0x0406 16 +digital_crop_x_offset 0x0408 16 +digital_crop_y_offset 0x040a 16 +digital_crop_image_width 0x040c 16 +digital_crop_image_height 0x040e 16 + +# image compression registers +compression_mode 0x0500 16 +- e none 0 +- e dpcm_pcm_simple 1 + +# test pattern registers +test_pattern_mode 0x0600 16 +- e none 0 +- e solid_color 1 +- e color_bars 2 +- e fade_to_grey 3 +- e pn9 4 +- e color_tile 5 +test_data_red 0x0602 16 +test_data_greenR 0x0604 16 +test_data_blue 0x0606 16 +test_data_greenB 0x0608 16 +value_step_size_smooth 0x060a 8 +value_step_size_quantised 0x060b 8 + +# phy configuration registers +tclk_post 0x0800 8 +ths_prepare 0x0801 8 +ths_zero_min 0x0802 8 +ths_trail 0x0803 8 +tclk_trail_min 0x0804 8 +tclk_prepare 0x0805 8 +tclk_zero 0x0806 8 +tlpx 0x0807 8 +phy_ctrl 0x0808 8 +- e auto 0 +- e UI 1 +- e manual 2 +tclk_post_ex 0x080a 16 +ths_prepare_ex 0x080c 16 +ths_zero_min_ex 0x080e 16 +ths_trail_ex 0x0810 16 +tclk_trail_min_ex 0x0812 16 +tclk_prepare_ex 0x0814 16 +tclk_zero_ex 0x0816 16 +tlpx_ex 0x0818 16 + +# link rate register +requested_link_rate 0x0820 32 u16.16 + +# equalization control registers +DPHY_equalization_mode 0x0824 8 v1.1 +- b eq2 0 +PHY_equalization_ctrl 0x0825 8 v1.1 +- b enable 0 + +# d-phy preamble control registers +DPHY_preamble_ctrl 0x0826 8 v1.1 +- b enable 0 +DPHY_preamble_length 0x0826 8 v1.1 + +# d-phy spread spectrum control registers +PHY_SSC_ctrl 0x0828 8 v1.1 +- b enable 0 + +# manual lp control register +manual_LP_ctrl 0x0829 8 v1.1 +- b enable 0 + +# additional phy configuration registers +twakeup 0x082a v1.1 +tinit 0x082b v1.1 +ths_exit 0x082c v1.1 +ths_exit_ex 0x082e 16 v1.1 + +# phy calibration configuration registers +PHY_periodic_calibration_ctrl 0x0830 8 +- b frame_blanking 0 +PHY_periodic_calibration_interval 0x0831 8 +PHY_init_calibration_ctrl 0x0832 8 +- b stream_start 0 +DPHY_calibration_mode 0x0833 8 v1.1 +- b also_alternate 0 +CPHY_calibration_mode 0x0834 8 v1.1 +- e format_1 0 +- e format_2 1 +- e format_3 2 +t3_calpreamble_length 0x0835 8 v1.1 +t3_calpreamble_length_per 0x0836 8 v1.1 +t3_calaltseq_length 0x0837 8 v1.1 +t3_calaltseq_length_per 0x0838 8 v1.1 +FM2_init_seed 0x083a 16 v1.1 +t3_caludefseq_length 0x083c 16 v1.1 +t3_caludefseq_length_per 0x083e 16 v1.1 + +# c-phy manual control registers +TGR_Preamble_Length 0x0841 8 +- b preamable_prog_seq 7 +- f begin_preamble_length 0 5 +TGR_Post_Length 0x0842 8 +- f post_length 0 4 +TGR_Preamble_Prog_Sequence(n2) 0x0843 +- l n2 0 6 1 +- f symbol_n_1 3 5 +- f symbol_n 0 2 +t3_prepare 0x084e 16 +t3_lpx 0x0850 16 + +# alps control register +ALPS_ctrl 0x085a 8 +- b lvlp_dphy 0 +- b lvlp_cphy 1 +- b alp_cphy 2 + +# lrte control registers +TX_REG_CSI_EPD_EN_SSP_cphy 0x0860 16 +TX_REG_CSI_EPD_OP_SLP_cphy 0x0862 16 +TX_REG_CSI_EPD_EN_SSP_dphy 0x0864 16 +TX_REG_CSI_EPD_OP_SLP_dphy 0x0866 16 +TX_REG_CSI_EPD_MISC_OPTION_cphy 0x0868 v1.1 +TX_REG_CSI_EPD_MISC_OPTION_dphy 0x0869 v1.1 + +# scrambling control registers +Scrambling_ctrl 0x0870 +- b enabled 0 +- f 2 3 +- e 1_seed_cphy 0 +- e 4_seed_cphy 3 +lane_seed_value(seed, lane) 0x0872 16 +- l seed 0 3 0x10 +- l lane 0 7 0x2 + +# usl control registers +TX_USL_REV_ENTRY 0x08c0 16 v1.1 +TX_USL_REV_Clock_Counter 0x08c2 16 v1.1 +TX_USL_REV_LP_Counter 0x08c4 16 v1.1 +TX_USL_REV_Frame_Counter 0x08c6 16 v1.1 +TX_USL_REV_Chronological_Timer 0x08c8 16 v1.1 +TX_USL_FWD_ENTRY 0x08ca 16 v1.1 +TX_USL_GPIO 0x08cc 16 v1.1 +TX_USL_Operation 0x08ce 16 v1.1 +- b reset 0 +TX_USL_ALP_ctrl 0x08d0 16 v1.1 +- b clock_pause 0 +TX_USL_APP_BTA_ACK_TIMEOUT 0x08d2 16 v1.1 +TX_USL_SNS_BTA_ACK_TIMEOUT 0x08d2 16 v1.1 +USL_Clock_Mode_d_ctrl 0x08d2 v1.1 +- b cont_clock_standby 0 +- b cont_clock_vblank 1 +- b cont_clock_hblank 2 + +# binning configuration registers +binning_mode 0x0900 8 +binning_type 0x0901 8 +binning_weighting 0x0902 8 + +# data transfer interface registers +data_transfer_if_1_ctrl 0x0a00 8 +- b enable 0 +- b write 1 +- b clear_error 2 +data_transfer_if_1_status 0x0a01 8 +- b read_if_ready 0 +- b write_if_ready 1 +- b data_corrupted 2 +- b improper_if_usage 3 +data_transfer_if_1_page_select 0x0a02 8 +data_transfer_if_1_data(p) 0x0a04 8 f +- l p 0 63 1 + +# image processing and sensor correction configuration registers +shading_correction_en 0x0b00 8 +- b enable 0 +luminance_correction_level 0x0b01 8 +green_imbalance_filter_en 0x0b02 8 +- b enable 0 +mapped_defect_correct_en 0x0b05 8 +- b enable 0 +single_defect_correct_en 0x0b06 8 +- b enable 0 +dynamic_couplet_correct_en 0x0b08 8 +- b enable 0 +combined_defect_correct_en 0x0b0a 8 +- b enable 0 +module_specific_correction_en 0x0b0c 8 +- b enable 0 +dynamic_triplet_defect_correct_en 0x0b13 8 +- b enable 0 +NF_ctrl 0x0b15 8 +- b luma 0 +- b chroma 1 +- b combined 2 + +# optical black pixel readout registers +OB_readout_control 0x0b30 8 +- b enable 0 +- b interleaving 1 +OB_virtual_channel 0x0b31 8 +OB_DT 0x0b32 8 +OB_data_format 0x0b33 8 + +# color temperature feedback registers +color_temperature 0x0b8c 16 +absolute_gain_greenr 0x0b8e 16 +absolute_gain_red 0x0b90 16 +absolute_gain_blue 0x0b92 16 +absolute_gain_greenb 0x0b94 16 + +# cfa conversion registers +CFA_conversion_ctrl 0x0ba0 v1.1 +- b bayer_conversion_enable 0 + +# flash strobe and sa strobe control registers +flash_strobe_adjustment 0x0c12 8 +flash_strobe_start_point 0x0c14 16 +tflash_strobe_delay_rs_ctrl 0x0c16 16 +tflash_strobe_width_high_rs_ctrl 0x0c18 16 +flash_mode_rs 0x0c1a 8 +- b continuous 0 +- b truncate 1 +- b async 3 +flash_trigger_rs 0x0c1b 8 +flash_status 0x0c1c 8 +- b retimed 0 +sa_strobe_mode 0x0c1d 8 +- b continuous 0 +- b truncate 1 +- b async 3 +- b adjust_edge 4 +sa_strobe_start_point 0x0c1e 16 +tsa_strobe_delay_ctrl 0x0c20 16 +tsa_strobe_width_ctrl 0x0c22 16 +sa_strobe_trigger 0x0c24 8 +sa_strobe_status 0x0c25 8 +- b retimed 0 +tSA_strobe_re_delay_ctrl 0x0c30 16 +tSA_strobe_fe_delay_ctrl 0x0c32 16 + +# pdaf control registers +PDAF_ctrl 0x0d00 16 +- b enable 0 +- b processed 1 +- b interleaved 2 +- b visible_pdaf_correction 3 +PDAF_VC 0x0d02 8 +PDAF_DT 0x0d03 8 +pd_x_addr_start 0x0d04 16 +pd_y_addr_start 0x0d06 16 +pd_x_addr_end 0x0d08 16 +pd_y_addr_end 0x0d0a 16 + +# bracketing interface configuration registers +bracketing_LUT_ctrl 0x0e00 8 +bracketing_LUT_mode 0x0e01 8 +- b continue_streaming 0 +- b loop_mode 1 +bracketing_LUT_entry_ctrl 0x0e02 8 +bracketing_LUT_frame(n) 0x0e10 v1.1 f +- l n 0 0xef 1 + +# integration time and gain parameter limit registers +integration_time_capability 0x1000 16 +- b fine 0 +coarse_integration_time_min 0x1004 16 +coarse_integration_time_max_margin 0x1006 16 +fine_integration_time_min 0x1008 16 +fine_integration_time_max_margin 0x100a 16 + +# digital gain parameter limit registers +digital_gain_capability 0x1081 +- e none 0 +- e global 2 +digital_gain_min 0x1084 16 +digital_gain_max 0x1086 16 +digital_gain_step_size 0x1088 16 + +# data pedestal capability registers +Pedestal_capability 0x10e0 8 v1.1 + +# adc capability registers +ADC_capability 0x10f0 8 +- b bit_depth_ctrl 0 +ADC_bit_depth_capability 0x10f4 32 v1.1 + +# video timing parameter limit registers +min_ext_clk_freq_mhz 0x1100 32 float_ireal +max_ext_clk_freq_mhz 0x1104 32 float_ireal +min_pre_pll_clk_div 0x1108 16 +# min_vt_pre_pll_clk_div 0x1108 16 +max_pre_pll_clk_div 0x110a 16 +# max_vt_pre_pll_clk_div 0x110a 16 +min_pll_ip_clk_freq_mhz 0x110c 32 float_ireal +# min_vt_pll_ip_clk_freq_mhz 0x110c 32 float_ireal +max_pll_ip_clk_freq_mhz 0x1110 32 float_ireal +# max_vt_pll_ip_clk_freq_mhz 0x1110 32 float_ireal +min_pll_multiplier 0x1114 16 +# min_vt_pll_multiplier 0x1114 16 +max_pll_multiplier 0x1116 16 +# max_vt_pll_multiplier 0x1116 16 +min_pll_op_clk_freq_mhz 0x1118 32 float_ireal +max_pll_op_clk_freq_mhz 0x111c 32 float_ireal + +# video timing set-up capability registers +min_vt_sys_clk_div 0x1120 16 +max_vt_sys_clk_div 0x1122 16 +min_vt_sys_clk_freq_mhz 0x1124 32 float_ireal +max_vt_sys_clk_freq_mhz 0x1128 32 float_ireal +min_vt_pix_clk_freq_mhz 0x112c 32 float_ireal +max_vt_pix_clk_freq_mhz 0x1130 32 float_ireal +min_vt_pix_clk_div 0x1134 16 +max_vt_pix_clk_div 0x1136 16 +clock_calculation 0x1138 +- b lane_speed 0 +- b link_decoupled 1 +- b dual_pll_op_sys_ddr 2 +- b dual_pll_op_pix_ddr 3 +num_of_vt_lanes 0x1139 +num_of_op_lanes 0x113a +op_bits_per_lane 0x113b 8 v1.1 + +# frame timing parameter limits +min_frame_length_lines 0x1140 16 +max_frame_length_lines 0x1142 16 +min_line_length_pck 0x1144 16 +max_line_length_pck 0x1146 16 +min_line_blanking_pck 0x1148 16 +min_frame_blanking_lines 0x114a 16 +min_line_length_pck_step_size 0x114c +timing_mode_capability 0x114d +- b auto_frame_length 0 +- b rolling_shutter_manual_readout 2 +- b delayed_exposure_start 3 +- b manual_exposure_embedded_data 4 +frame_margin_max_value 0x114e 16 +frame_margin_min_value 0x1150 +gain_delay_type 0x1151 +- e fixed 0 +- e variable 1 + +# output clock set-up capability registers +min_op_sys_clk_div 0x1160 16 +max_op_sys_clk_div 0x1162 16 +min_op_sys_clk_freq_mhz 0x1164 32 float_ireal +max_op_sys_clk_freq_mhz 0x1168 32 float_ireal +min_op_pix_clk_div 0x116c 16 +max_op_pix_clk_div 0x116e 16 +min_op_pix_clk_freq_mhz 0x1170 32 float_ireal +max_op_pix_clk_freq_mhz 0x1174 32 float_ireal + +# image size parameter limit registers +x_addr_min 0x1180 16 +y_addr_min 0x1182 16 +x_addr_max 0x1184 16 +y_addr_max 0x1186 16 +min_x_output_size 0x1188 16 +min_y_output_size 0x118a 16 +max_x_output_size 0x118c 16 +max_y_output_size 0x118e 16 + +x_addr_start_div_constant 0x1190 v1.1 +y_addr_start_div_constant 0x1191 v1.1 +x_addr_end_div_constant 0x1192 v1.1 +y_addr_end_div_constant 0x1193 v1.1 +x_size_div 0x1194 v1.1 +y_size_div 0x1195 v1.1 +x_output_div 0x1196 v1.1 +y_output_div 0x1197 v1.1 +non_flexible_resolution_support 0x1198 v1.1 +- b new_pix_addr 0 +- b new_output_res 1 +- b output_crop_no_pad 2 +- b output_size_lane_dep 3 + +min_op_pre_pll_clk_div 0x11a0 16 +max_op_pre_pll_clk_div 0x11a2 16 +min_op_pll_ip_clk_freq_mhz 0x11a4 32 float_ireal +max_op_pll_ip_clk_freq_mhz 0x11a8 32 float_ireal +min_op_pll_multiplier 0x11ac 16 +max_op_pll_multiplier 0x11ae 16 +min_op_pll_op_clk_freq_mhz 0x11b0 32 float_ireal +max_op_pll_op_clk_freq_mhz 0x11b4 32 float_ireal +clock_tree_pll_capability 0x11b8 8 +- b dual_pll 0 +- b single_pll 1 +- b ext_divider 2 +- b flexible_op_pix_clk_div 3 +clock_capa_type_capability 0x11b9 v1.1 +- b ireal 0 + +# sub-sampling parameters limit registers +min_even_inc 0x11c0 16 +min_odd_inc 0x11c2 16 +max_even_inc 0x11c4 16 +max_odd_inc 0x11c6 16 +aux_subsamp_capability 0x11c8 v1.1 +- b factor_power_of_2 1 +aux_subsamp_mono_capability 0x11c9 v1.1 +- b factor_power_of_2 1 +monochrome_capability 0x11ca v1.1 +- e inc_odd 0 +- e inc_even 1 +pixel_readout_capability 0x11cb v1.1 +- e bayer 0 +- e monochrome 1 +- e bayer_and_mono 2 +min_even_inc_mono 0x11cc 16 v1.1 +max_even_inc_mono 0x11ce 16 v1.1 +min_odd_inc_mono 0x11d0 16 v1.1 +max_odd_inc_mono 0x11d2 16 v1.1 +min_even_inc_bc2 0x11d4 16 v1.1 +max_even_inc_bc2 0x11d6 16 v1.1 +min_odd_inc_bc2 0x11d8 16 v1.1 +max_odd_inc_bc2 0x11da 16 v1.1 +min_even_inc_mono_bc2 0x11dc 16 v1.1 +max_even_inc_mono_bc2 0x11de 16 v1.1 +min_odd_inc_mono_bc2 0x11f0 16 v1.1 +max_odd_inc_mono_bc2 0x11f2 16 v1.1 + +# image scaling limit parameters +scaling_capability 0x1200 16 +- e none 0 +- e horizontal 1 +- e reserved 2 +scaler_m_min 0x1204 16 +scaler_m_max 0x1206 16 +scaler_n_min 0x1208 16 +scaler_n_max 0x120a 16 +digital_crop_capability 0x120e +- e none 0 +- e input_crop 1 + +# hdr limit registers +hdr_capability_1 0x1210 +- b 2x2_binning 0 +- b combined_analog_gain 1 +- b separate_analog_gain 2 +- b upscaling 3 +- b reset_sync 4 +- b direct_short_exp_timing 5 +- b direct_short_exp_synthesis 6 +min_hdr_bit_depth 0x1211 +hdr_resolution_sub_types 0x1212 +hdr_resolution_sub_type(n) 0x1213 +- l n 0 1 1 +- f row 0 3 +- f column 4 7 +hdr_capability_2 0x121b +- b combined_digital_gain 0 +- b separate_digital_gain 1 +- b timing_mode 3 +- b synthesis_mode 4 +max_hdr_bit_depth 0x121c + +# usl capability register +usl_support_capability 0x1230 v1.1 +- b clock_tree 0 +- b rev_clock_tree 1 +- b rev_clock_calc 2 +usl_clock_mode_d_capability 0x1231 v1.1 +- b cont_clock_standby 0 +- b cont_clock_vblank 1 +- b cont_clock_hblank 2 +- b noncont_clock_standby 3 +- b noncont_clock_vblank 4 +- b noncont_clock_hblank 5 +min_op_sys_clk_div_rev 0x1234 v1.1 +max_op_sys_clk_div_rev 0x1236 v1.1 +min_op_pix_clk_div_rev 0x1238 v1.1 +max_op_pix_clk_div_rev 0x123a v1.1 +min_op_sys_clk_freq_rev_mhz 0x123c 32 v1.1 float_ireal +max_op_sys_clk_freq_rev_mhz 0x1240 32 v1.1 float_ireal +min_op_pix_clk_freq_rev_mhz 0x1244 32 v1.1 float_ireal +max_op_pix_clk_freq_rev_mhz 0x1248 32 v1.1 float_ireal +max_bitrate_rev_d_mode_mbps 0x124c 32 v1.1 ireal +max_symrate_rev_c_mode_msps 0x1250 32 v1.1 ireal + +# image compression capability registers +compression_capability 0x1300 +- b dpcm_pcm_simple 0 + +# test mode capability registers +test_mode_capability 0x1310 16 +- b solid_color 0 +- b color_bars 1 +- b fade_to_grey 2 +- b pn9 3 +- b color_tile 5 +pn9_data_format1 0x1312 +pn9_data_format2 0x1313 +pn9_data_format3 0x1314 +pn9_data_format4 0x1315 +pn9_misc_capability 0x1316 +- f num_pixels 0 2 +- b compression 3 +test_pattern_capability 0x1317 v1.1 +- b no_repeat 1 +pattern_size_div_m1 0x1318 v1.1 + +# fifo capability registers +fifo_support_capability 0x1502 +- e none 0 +- e derating 1 +- e derating_overrating 2 + +# csi-2 capability registers +phy_ctrl_capability 0x1600 +- b auto_phy_ctl 0 +- b ui_phy_ctl 1 +- b dphy_time_ui_reg_1_ctl 2 +- b dphy_time_ui_reg_2_ctl 3 +- b dphy_time_ctl 4 +- b dphy_ext_time_ui_reg_1_ctl 5 +- b dphy_ext_time_ui_reg_2_ctl 6 +- b dphy_ext_time_ctl 7 +csi_dphy_lane_mode_capability 0x1601 +- b 1_lane 0 +- b 2_lane 1 +- b 3_lane 2 +- b 4_lane 3 +- b 5_lane 4 +- b 6_lane 5 +- b 7_lane 6 +- b 8_lane 7 +csi_signaling_mode_capability 0x1602 +- b csi_dphy 2 +- b csi_cphy 3 +fast_standby_capability 0x1603 +- e no_frame_truncation 0 +- e frame_truncation 1 +csi_address_control_capability 0x1604 +- b cci_addr_change 0 +- b 2nd_cci_addr 1 +- b sw_changeable_2nd_cci_addr 2 +data_type_capability 0x1605 +- b dpcm_programmable 0 +- b bottom_embedded_dt_programmable 1 +- b bottom_embedded_vc_programmable 2 +- b ext_vc_range 3 +csi_cphy_lane_mode_capability 0x1606 +- b 1_lane 0 +- b 2_lane 1 +- b 3_lane 2 +- b 4_lane 3 +- b 5_lane 4 +- b 6_lane 5 +- b 7_lane 6 +- b 8_lane 7 +emb_data_capability 0x1607 v1.1 +- b two_bytes_per_raw16 0 +- b two_bytes_per_raw20 1 +- b two_bytes_per_raw24 2 +- b no_one_byte_per_raw16 3 +- b no_one_byte_per_raw20 4 +- b no_one_byte_per_raw24 5 +max_per_lane_bitrate_lane_d_mode_mbps(n) 0x1608 32 ireal +- l n 0 7 4 4,0x32 +temp_sensor_capability 0x1618 +- b supported 0 +- b CCS_format 1 +- b reset_0x80 2 +max_per_lane_bitrate_lane_c_mode_mbps(n) 0x161a 32 ireal +- l n 0 7 4 4,0x30 +dphy_equalization_capability 0x162b +- b equalization_ctrl 0 +- b eq1 1 +- b eq2 2 +cphy_equalization_capability 0x162c +- b equalization_ctrl 0 +dphy_preamble_capability 0x162d +- b preamble_seq_ctrl 0 +dphy_ssc_capability 0x162e +- b supported 0 +cphy_calibration_capability 0x162f +- b manual 0 +- b manual_streaming 1 +- b format_1_ctrl 2 +- b format_2_ctrl 3 +- b format_3_ctrl 4 +dphy_calibration_capability 0x1630 +- b manual 0 +- b manual_streaming 1 +- b alternate_seq 2 +phy_ctrl_capability_2 0x1631 +- b tgr_length 0 +- b tgr_preamble_prog_seq 1 +- b extra_cphy_manual_timing 2 +- b clock_based_manual_cdphy 3 +- b clock_based_manual_dphy 4 +- b clock_based_manual_cphy 5 +- b manual_lp_dphy 6 +- b manual_lp_cphy 7 +lrte_cphy_capability 0x1632 +- b pdq_short 0 +- b spacer_short 1 +- b pdq_long 2 +- b spacer_long 3 +- b spacer_no_pdq 4 +lrte_dphy_capability 0x1633 +- b pdq_short_opt1 0 +- b spacer_short_opt1 1 +- b pdq_long_opt1 2 +- b spacer_long_opt1 3 +- b spacer_short_opt2 4 +- b spacer_long_opt2 5 +- b spacer_no_pdq_opt1 6 +- b spacer_variable_opt2 7 +alps_capability_dphy 0x1634 +- e lvlp_not_supported 0 0x3 +- e lvlp_supported 1 0x3 +- e controllable_lvlp 2 0x3 +alps_capability_cphy 0x1635 +- e lvlp_not_supported 0 0x3 +- e lvlp_supported 1 0x3 +- e controllable_lvlp 2 0x3 +- e alp_not_supported 0xc 0xc +- e alp_supported 0xd 0xc +- e controllable_alp 0xe 0xc +scrambling_capability 0x1636 +- b scrambling_supported 0 +- f max_seeds_per_lane_c 1 2 +- e 1 0 +- e 4 3 +- f num_seed_regs 3 5 +- e 0 0 +- e 1 1 +- e 4 4 +- b num_seed_per_lane 6 +dphy_manual_constant 0x1637 +cphy_manual_constant 0x1638 +CSI2_interface_capability_misc 0x1639 v1.1 +- b eotp_short_pkt_opt2 0 +PHY_ctrl_capability_3 0x165c v1.1 +- b dphy_timing_not_multiple 0 +- b dphy_min_timing_value_1 1 +- b twakeup_supported 2 +- b tinit_supported 3 +- b ths_exit_supported 4 +- b cphy_timing_not_multiple 5 +- b cphy_min_timing_value_1 6 +dphy_sf 0x165d v1.1 +cphy_sf 0x165e v1.1 +- f twakeup 0 3 +- f tinit 4 7 +dphy_limits_1 0x165f v1.1 +- f ths_prepare 0 3 +- f ths_zero 4 7 +dphy_limits_2 0x1660 v1.1 +- f ths_trail 0 3 +- f tclk_trail_min 4 7 +dphy_limits_3 0x1661 v1.1 +- f tclk_prepare 0 3 +- f tclk_zero 4 7 +dphy_limits_4 0x1662 v1.1 +- f tclk_post 0 3 +- f tlpx 4 7 +dphy_limits_5 0x1663 v1.1 +- f ths_exit 0 3 +- f twakeup 4 7 +dphy_limits_6 0x1664 v1.1 +- f tinit 0 3 +cphy_limits_1 0x1665 v1.1 +- f t3_prepare_max 0 3 +- f t3_lpx_max 4 7 +cphy_limits_2 0x1666 v1.1 +- f ths_exit_max 0 3 +- f twakeup_max 4 7 +cphy_limits_3 0x1667 v1.1 +- f tinit_max 0 3 + +# binning capability registers +min_frame_length_lines_bin 0x1700 16 +max_frame_length_lines_bin 0x1702 16 +min_line_length_pck_bin 0x1704 16 +max_line_length_pck_bin 0x1706 16 +min_line_blanking_pck_bin 0x1708 16 +fine_integration_time_min_bin 0x170a 16 +fine_integration_time_max_margin_bin 0x170c 16 +binning_capability 0x1710 +- e unsupported 0 +- e binning_then_subsampling 1 +- e subsampling_then_binning 2 +binning_weighting_capability 0x1711 +- b averaged 0 +- b summed 1 +- b bayer_corrected 2 +- b module_specific_weight 3 +binning_sub_types 0x1712 +binning_sub_type(n) 0x1713 +- l n 0 63 1 +- f row 0 3 +- f column 4 7 +binning_weighting_mono_capability 0x1771 v1.1 +- b averaged 0 +- b summed 1 +- b bayer_corrected 2 +- b module_specific_weight 3 +binning_sub_types_mono 0x1772 v1.1 +binning_sub_type_mono(n) 0x1773 v1.1 f +- l n 0 63 1 + +# data transfer interface capability registers +data_transfer_if_capability 0x1800 +- b supported 0 +- b polling 2 + +# sensor correction capability registers +shading_correction_capability 0x1900 +- b color_shading 0 +- b luminance_correction 1 +green_imbalance_capability 0x1901 +- b supported 0 +module_specific_correction_capability 0x1903 +defect_correction_capability 0x1904 16 +- b mapped_defect 0 +- b dynamic_couplet 2 +- b dynamic_single 5 +- b combined_dynamic 8 +defect_correction_capability_2 0x1906 16 +- b dynamic_triplet 3 +nf_capability 0x1908 +- b luma 0 +- b chroma 1 +- b combined 2 + +# optical black readout capability registers +ob_readout_capability 0x1980 +- b controllable_readout 0 +- b visible_pixel_readout 1 +- b different_vc_readout 2 +- b different_dt_readout 3 +- b prog_data_format 4 + +# color feedback capability registers +color_feedback_capability 0x1987 +- b kelvin 0 +- b awb_gain 1 + +# cfa pattern capability registers +CFA_pattern_capability 0x1990 v1.1 +- e bayer 0 +- e monochrome 1 +- e 4x4_quad_bayer 2 +- e vendor_specific 3 +CFA_pattern_conversion_capability 0x1991 v1.1 +- b bayer 0 + +# timer capability registers +flash_mode_capability 0x1a02 +- b single_strobe 0 +sa_strobe_mode_capability 0x1a03 +- b fixed_width 0 +- b edge_ctrl 1 + +# soft reset capability registers +reset_max_delay 0x1a10 v1.1 +reset_min_time 0x1a11 v1.1 + +# pdaf capability registers +pdaf_capability_1 0x1b80 +- b supported 0 +- b processed_bottom_embedded 1 +- b processed_interleaved 2 +- b raw_bottom_embedded 3 +- b raw_interleaved 4 +- b visible_pdaf_correction 5 +- b vc_interleaving 6 +- b dt_interleaving 7 +pdaf_capability_2 0x1b81 +- b ROI 0 +- b after_digital_crop 1 +- b ctrl_retimed 2 + +# bracketing interface capability registers +bracketing_lut_capability_1 0x1c00 +- b coarse_integration 0 +- b global_analog_gain 1 +- b flash 4 +- b global_digital_gain 5 +- b alternate_global_analog_gain 6 +bracketing_lut_capability_2 0x1c01 +- b single_bracketing_mode 0 +- b looped_bracketing_mode 1 +bracketing_lut_size 0x1c02 diff --git a/Documentation/driver-api/media/drivers/ccs/ccs-regs.txt b/Documentation/driver-api/media/drivers/ccs/ccs-regs.txt deleted file mode 100644 index 93f0131aa304..000000000000 --- a/Documentation/driver-api/media/drivers/ccs/ccs-regs.txt +++ /dev/null @@ -1,1041 +0,0 @@ -# Copyright (C) 2019--2020 Intel Corporation -# SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause - -# register rflags -# - f field LSB MSB rflags -# - e enum value # after a field -# - e enum value [LSB MSB] -# - b bool bit -# - l arg name min max elsize [discontig...] -# -# rflags -# 8, 16, 32 register bits (default is 8) -# v1.1 defined in version 1.1 -# f formula -# float_ireal iReal or IEEE 754; 32 bits -# ireal unsigned iReal - -# general status registers -module_model_id 0x0000 16 -module_revision_number_major 0x0002 8 -frame_count 0x0005 8 -pixel_order 0x0006 8 -- e GRBG 0 -- e RGGB 1 -- e BGGR 2 -- e GBRG 3 -MIPI_CCS_version 0x0007 8 -- e v1_0 0x10 -- e v1_1 0x11 -- f major 4 7 -- f minor 0 3 -data_pedestal 0x0008 16 -module_manufacturer_id 0x000e 16 -module_revision_number_minor 0x0010 8 -module_date_year 0x0012 8 -module_date_month 0x0013 8 -module_date_day 0x0014 8 -module_date_phase 0x0015 8 -- f 0 2 -- e ts 0 -- e es 1 -- e cs 2 -- e mp 3 -sensor_model_id 0x0016 16 -sensor_revision_number 0x0018 8 -sensor_firmware_version 0x001a 8 -serial_number 0x001c 32 -sensor_manufacturer_id 0x0020 16 -sensor_revision_number_16 0x0022 16 - -# frame format description registers -frame_format_model_type 0x0040 8 -- e 2-byte 1 -- e 4-byte 2 -frame_format_model_subtype 0x0041 8 -- f rows 0 3 -- f columns 4 7 -frame_format_descriptor(n) 0x0042 16 f -- l n 0 14 2 -- f pixels 0 11 -- f pcode 12 15 -- e embedded 1 -- e dummy_pixel 2 -- e black_pixel 3 -- e dark_pixel 4 -- e visible_pixel 5 -- e manuf_specific_0 8 -- e manuf_specific_1 9 -- e manuf_specific_2 10 -- e manuf_specific_3 11 -- e manuf_specific_4 12 -- e manuf_specific_5 13 -- e manuf_specific_6 14 -frame_format_descriptor_4(n) 0x0060 32 f -- l n 0 7 4 -- f pixels 0 15 -- f pcode 28 31 -- e embedded 1 -- e dummy_pixel 2 -- e black_pixel 3 -- e dark_pixel 4 -- e visible_pixel 5 -- e manuf_specific_0 8 -- e manuf_specific_1 9 -- e manuf_specific_2 10 -- e manuf_specific_3 11 -- e manuf_specific_4 12 -- e manuf_specific_5 13 -- e manuf_specific_6 14 - -# analog gain description registers -analog_gain_capability 0x0080 16 -- e global 0 -- e alternate_global 2 -analog_gain_code_min 0x0084 16 -analog_gain_code_max 0x0086 16 -analog_gain_code_step 0x0088 16 -analog_gain_type 0x008a 16 -analog_gain_m0 0x008c 16 -analog_gain_c0 0x008e 16 -analog_gain_m1 0x0090 16 -analog_gain_c1 0x0092 16 -analog_linear_gain_min 0x0094 16 v1.1 -analog_linear_gain_max 0x0096 16 v1.1 -analog_linear_gain_step_size 0x0098 16 v1.1 -analog_exponential_gain_min 0x009a 16 v1.1 -analog_exponential_gain_max 0x009c 16 v1.1 -analog_exponential_gain_step_size 0x009e 16 v1.1 - -# data format description registers -data_format_model_type 0x00c0 8 -- e normal 1 -- e extended 2 -data_format_model_subtype 0x00c1 8 -- f rows 0 3 -- f columns 4 7 -data_format_descriptor(n) 0x00c2 16 f -- l n 0 15 2 -- f compressed 0 7 -- f uncompressed 8 15 - -# general set-up registers -mode_select 0x0100 8 -- e software_standby 0 -- e streaming 1 -image_orientation 0x0101 8 -- b horizontal_mirror 0 -- b vertical_flip 1 -software_reset 0x0103 8 -- e off 0 -- e on 1 -grouped_parameter_hold 0x0104 8 -mask_corrupted_frames 0x0105 8 -- e allow 0 -- e mask 1 -fast_standby_ctrl 0x0106 8 -- e complete_frames 0 -- e frame_truncation 1 -CCI_address_ctrl 0x0107 8 -2nd_CCI_if_ctrl 0x0108 8 -- b enable 0 -- b ack 1 -2nd_CCI_address_ctrl 0x0109 8 -CSI_channel_identifier 0x0110 8 -CSI_signaling_mode 0x0111 8 -- e csi_2_dphy 2 -- e csi_2_cphy 3 -CSI_data_format 0x0112 16 -CSI_lane_mode 0x0114 8 -DPCM_Frame_DT 0x011d 8 -Bottom_embedded_data_DT 0x011e 8 -Bottom_embedded_data_VC 0x011f 8 - -gain_mode 0x0120 8 -- e global 0 -- e alternate 1 -ADC_bit_depth 0x0121 8 -emb_data_ctrl 0x0122 v1.1 -- b raw8_packing_for_raw16 0 -- b raw10_packing_for_raw20 1 -- b raw12_packing_for_raw24 2 - -GPIO_TRIG_mode 0x0130 8 -extclk_frequency_mhz 0x0136 16 ireal -temp_sensor_ctrl 0x0138 8 -- b enable 0 -temp_sensor_mode 0x0139 8 -temp_sensor_output 0x013a 8 - -# integration time registers -fine_integration_time 0x0200 16 -coarse_integration_time 0x0202 16 - -# analog gain registers -analog_gain_code_global 0x0204 16 -analog_linear_gain_global 0x0206 16 v1.1 -analog_exponential_gain_global 0x0208 16 v1.1 - -# digital gain registers -digital_gain_global 0x020e 16 - -# hdr control registers -Short_analog_gain_global 0x0216 16 -Short_digital_gain_global 0x0218 16 - -HDR_mode 0x0220 8 -- b enabled 0 -- b separate_analog_gain 1 -- b upscaling 2 -- b reset_sync 3 -- b timing_mode 4 -- b exposure_ctrl_direct 5 -- b separate_digital_gain 6 -HDR_resolution_reduction 0x0221 8 -- f row 0 3 -- f column 4 7 -Exposure_ratio 0x0222 8 -HDR_internal_bit_depth 0x0223 8 -Direct_short_integration_time 0x0224 16 -Short_analog_linear_gain_global 0x0226 16 v1.1 -Short_analog_exponential_gain_global 0x0228 16 v1.1 - -# clock set-up registers -vt_pix_clk_div 0x0300 16 -vt_sys_clk_div 0x0302 16 -pre_pll_clk_div 0x0304 16 -#vt_pre_pll_clk_div 0x0304 16 -pll_multiplier 0x0306 16 -#vt_pll_multiplier 0x0306 16 -op_pix_clk_div 0x0308 16 -op_sys_clk_div 0x030a 16 -op_pre_pll_clk_div 0x030c 16 -op_pll_multiplier 0x031e 16 -pll_mode 0x0310 8 -- f 0 0 -- e single 0 -- e dual 1 -op_pix_clk_div_rev 0x0312 16 v1.1 -op_sys_clk_div_rev 0x0314 16 v1.1 - -# frame timing registers -frame_length_lines 0x0340 16 -line_length_pck 0x0342 16 - -# image size registers -x_addr_start 0x0344 16 -y_addr_start 0x0346 16 -x_addr_end 0x0348 16 -y_addr_end 0x034a 16 -x_output_size 0x034c 16 -y_output_size 0x034e 16 - -# timing mode registers -Frame_length_ctrl 0x0350 8 -- b automatic 0 -Timing_mode_ctrl 0x0352 8 -- b manual_readout 0 -- b delayed_exposure 1 -Start_readout_rs 0x0353 8 -- b manual_readout_start 0 -Frame_margin 0x0354 16 - -# sub-sampling registers -x_even_inc 0x0380 16 -x_odd_inc 0x0382 16 -y_even_inc 0x0384 16 -y_odd_inc 0x0386 16 - -# monochrome readout registers -monochrome_en 0x0390 v1.1 -- e enabled 0 - -# image scaling registers -Scaling_mode 0x0400 16 -- e no_scaling 0 -- e horizontal 1 -scale_m 0x0404 16 -scale_n 0x0406 16 -digital_crop_x_offset 0x0408 16 -digital_crop_y_offset 0x040a 16 -digital_crop_image_width 0x040c 16 -digital_crop_image_height 0x040e 16 - -# image compression registers -compression_mode 0x0500 16 -- e none 0 -- e dpcm_pcm_simple 1 - -# test pattern registers -test_pattern_mode 0x0600 16 -- e none 0 -- e solid_color 1 -- e color_bars 2 -- e fade_to_grey 3 -- e pn9 4 -- e color_tile 5 -test_data_red 0x0602 16 -test_data_greenR 0x0604 16 -test_data_blue 0x0606 16 -test_data_greenB 0x0608 16 -value_step_size_smooth 0x060a 8 -value_step_size_quantised 0x060b 8 - -# phy configuration registers -tclk_post 0x0800 8 -ths_prepare 0x0801 8 -ths_zero_min 0x0802 8 -ths_trail 0x0803 8 -tclk_trail_min 0x0804 8 -tclk_prepare 0x0805 8 -tclk_zero 0x0806 8 -tlpx 0x0807 8 -phy_ctrl 0x0808 8 -- e auto 0 -- e UI 1 -- e manual 2 -tclk_post_ex 0x080a 16 -ths_prepare_ex 0x080c 16 -ths_zero_min_ex 0x080e 16 -ths_trail_ex 0x0810 16 -tclk_trail_min_ex 0x0812 16 -tclk_prepare_ex 0x0814 16 -tclk_zero_ex 0x0816 16 -tlpx_ex 0x0818 16 - -# link rate register -requested_link_rate 0x0820 32 u16.16 - -# equalization control registers -DPHY_equalization_mode 0x0824 8 v1.1 -- b eq2 0 -PHY_equalization_ctrl 0x0825 8 v1.1 -- b enable 0 - -# d-phy preamble control registers -DPHY_preamble_ctrl 0x0826 8 v1.1 -- b enable 0 -DPHY_preamble_length 0x0826 8 v1.1 - -# d-phy spread spectrum control registers -PHY_SSC_ctrl 0x0828 8 v1.1 -- b enable 0 - -# manual lp control register -manual_LP_ctrl 0x0829 8 v1.1 -- b enable 0 - -# additional phy configuration registers -twakeup 0x082a v1.1 -tinit 0x082b v1.1 -ths_exit 0x082c v1.1 -ths_exit_ex 0x082e 16 v1.1 - -# phy calibration configuration registers -PHY_periodic_calibration_ctrl 0x0830 8 -- b frame_blanking 0 -PHY_periodic_calibration_interval 0x0831 8 -PHY_init_calibration_ctrl 0x0832 8 -- b stream_start 0 -DPHY_calibration_mode 0x0833 8 v1.1 -- b also_alternate 0 -CPHY_calibration_mode 0x0834 8 v1.1 -- e format_1 0 -- e format_2 1 -- e format_3 2 -t3_calpreamble_length 0x0835 8 v1.1 -t3_calpreamble_length_per 0x0836 8 v1.1 -t3_calaltseq_length 0x0837 8 v1.1 -t3_calaltseq_length_per 0x0838 8 v1.1 -FM2_init_seed 0x083a 16 v1.1 -t3_caludefseq_length 0x083c 16 v1.1 -t3_caludefseq_length_per 0x083e 16 v1.1 - -# c-phy manual control registers -TGR_Preamble_Length 0x0841 8 -- b preamable_prog_seq 7 -- f begin_preamble_length 0 5 -TGR_Post_Length 0x0842 8 -- f post_length 0 4 -TGR_Preamble_Prog_Sequence(n2) 0x0843 -- l n2 0 6 1 -- f symbol_n_1 3 5 -- f symbol_n 0 2 -t3_prepare 0x084e 16 -t3_lpx 0x0850 16 - -# alps control register -ALPS_ctrl 0x085a 8 -- b lvlp_dphy 0 -- b lvlp_cphy 1 -- b alp_cphy 2 - -# lrte control registers -TX_REG_CSI_EPD_EN_SSP_cphy 0x0860 16 -TX_REG_CSI_EPD_OP_SLP_cphy 0x0862 16 -TX_REG_CSI_EPD_EN_SSP_dphy 0x0864 16 -TX_REG_CSI_EPD_OP_SLP_dphy 0x0866 16 -TX_REG_CSI_EPD_MISC_OPTION_cphy 0x0868 v1.1 -TX_REG_CSI_EPD_MISC_OPTION_dphy 0x0869 v1.1 - -# scrambling control registers -Scrambling_ctrl 0x0870 -- b enabled 0 -- f 2 3 -- e 1_seed_cphy 0 -- e 4_seed_cphy 3 -lane_seed_value(seed, lane) 0x0872 16 -- l seed 0 3 0x10 -- l lane 0 7 0x2 - -# usl control registers -TX_USL_REV_ENTRY 0x08c0 16 v1.1 -TX_USL_REV_Clock_Counter 0x08c2 16 v1.1 -TX_USL_REV_LP_Counter 0x08c4 16 v1.1 -TX_USL_REV_Frame_Counter 0x08c6 16 v1.1 -TX_USL_REV_Chronological_Timer 0x08c8 16 v1.1 -TX_USL_FWD_ENTRY 0x08ca 16 v1.1 -TX_USL_GPIO 0x08cc 16 v1.1 -TX_USL_Operation 0x08ce 16 v1.1 -- b reset 0 -TX_USL_ALP_ctrl 0x08d0 16 v1.1 -- b clock_pause 0 -TX_USL_APP_BTA_ACK_TIMEOUT 0x08d2 16 v1.1 -TX_USL_SNS_BTA_ACK_TIMEOUT 0x08d2 16 v1.1 -USL_Clock_Mode_d_ctrl 0x08d2 v1.1 -- b cont_clock_standby 0 -- b cont_clock_vblank 1 -- b cont_clock_hblank 2 - -# binning configuration registers -binning_mode 0x0900 8 -binning_type 0x0901 8 -binning_weighting 0x0902 8 - -# data transfer interface registers -data_transfer_if_1_ctrl 0x0a00 8 -- b enable 0 -- b write 1 -- b clear_error 2 -data_transfer_if_1_status 0x0a01 8 -- b read_if_ready 0 -- b write_if_ready 1 -- b data_corrupted 2 -- b improper_if_usage 3 -data_transfer_if_1_page_select 0x0a02 8 -data_transfer_if_1_data(p) 0x0a04 8 f -- l p 0 63 1 - -# image processing and sensor correction configuration registers -shading_correction_en 0x0b00 8 -- b enable 0 -luminance_correction_level 0x0b01 8 -green_imbalance_filter_en 0x0b02 8 -- b enable 0 -mapped_defect_correct_en 0x0b05 8 -- b enable 0 -single_defect_correct_en 0x0b06 8 -- b enable 0 -dynamic_couplet_correct_en 0x0b08 8 -- b enable 0 -combined_defect_correct_en 0x0b0a 8 -- b enable 0 -module_specific_correction_en 0x0b0c 8 -- b enable 0 -dynamic_triplet_defect_correct_en 0x0b13 8 -- b enable 0 -NF_ctrl 0x0b15 8 -- b luma 0 -- b chroma 1 -- b combined 2 - -# optical black pixel readout registers -OB_readout_control 0x0b30 8 -- b enable 0 -- b interleaving 1 -OB_virtual_channel 0x0b31 8 -OB_DT 0x0b32 8 -OB_data_format 0x0b33 8 - -# color temperature feedback registers -color_temperature 0x0b8c 16 -absolute_gain_greenr 0x0b8e 16 -absolute_gain_red 0x0b90 16 -absolute_gain_blue 0x0b92 16 -absolute_gain_greenb 0x0b94 16 - -# cfa conversion registers -CFA_conversion_ctrl 0x0ba0 v1.1 -- b bayer_conversion_enable 0 - -# flash strobe and sa strobe control registers -flash_strobe_adjustment 0x0c12 8 -flash_strobe_start_point 0x0c14 16 -tflash_strobe_delay_rs_ctrl 0x0c16 16 -tflash_strobe_width_high_rs_ctrl 0x0c18 16 -flash_mode_rs 0x0c1a 8 -- b continuous 0 -- b truncate 1 -- b async 3 -flash_trigger_rs 0x0c1b 8 -flash_status 0x0c1c 8 -- b retimed 0 -sa_strobe_mode 0x0c1d 8 -- b continuous 0 -- b truncate 1 -- b async 3 -- b adjust_edge 4 -sa_strobe_start_point 0x0c1e 16 -tsa_strobe_delay_ctrl 0x0c20 16 -tsa_strobe_width_ctrl 0x0c22 16 -sa_strobe_trigger 0x0c24 8 -sa_strobe_status 0x0c25 8 -- b retimed 0 -tSA_strobe_re_delay_ctrl 0x0c30 16 -tSA_strobe_fe_delay_ctrl 0x0c32 16 - -# pdaf control registers -PDAF_ctrl 0x0d00 16 -- b enable 0 -- b processed 1 -- b interleaved 2 -- b visible_pdaf_correction 3 -PDAF_VC 0x0d02 8 -PDAF_DT 0x0d03 8 -pd_x_addr_start 0x0d04 16 -pd_y_addr_start 0x0d06 16 -pd_x_addr_end 0x0d08 16 -pd_y_addr_end 0x0d0a 16 - -# bracketing interface configuration registers -bracketing_LUT_ctrl 0x0e00 8 -bracketing_LUT_mode 0x0e01 8 -- b continue_streaming 0 -- b loop_mode 1 -bracketing_LUT_entry_ctrl 0x0e02 8 -bracketing_LUT_frame(n) 0x0e10 v1.1 f -- l n 0 0xef 1 - -# integration time and gain parameter limit registers -integration_time_capability 0x1000 16 -- b fine 0 -coarse_integration_time_min 0x1004 16 -coarse_integration_time_max_margin 0x1006 16 -fine_integration_time_min 0x1008 16 -fine_integration_time_max_margin 0x100a 16 - -# digital gain parameter limit registers -digital_gain_capability 0x1081 -- e none 0 -- e global 2 -digital_gain_min 0x1084 16 -digital_gain_max 0x1086 16 -digital_gain_step_size 0x1088 16 - -# data pedestal capability registers -Pedestal_capability 0x10e0 8 v1.1 - -# adc capability registers -ADC_capability 0x10f0 8 -- b bit_depth_ctrl 0 -ADC_bit_depth_capability 0x10f4 32 v1.1 - -# video timing parameter limit registers -min_ext_clk_freq_mhz 0x1100 32 float_ireal -max_ext_clk_freq_mhz 0x1104 32 float_ireal -min_pre_pll_clk_div 0x1108 16 -# min_vt_pre_pll_clk_div 0x1108 16 -max_pre_pll_clk_div 0x110a 16 -# max_vt_pre_pll_clk_div 0x110a 16 -min_pll_ip_clk_freq_mhz 0x110c 32 float_ireal -# min_vt_pll_ip_clk_freq_mhz 0x110c 32 float_ireal -max_pll_ip_clk_freq_mhz 0x1110 32 float_ireal -# max_vt_pll_ip_clk_freq_mhz 0x1110 32 float_ireal -min_pll_multiplier 0x1114 16 -# min_vt_pll_multiplier 0x1114 16 -max_pll_multiplier 0x1116 16 -# max_vt_pll_multiplier 0x1116 16 -min_pll_op_clk_freq_mhz 0x1118 32 float_ireal -max_pll_op_clk_freq_mhz 0x111c 32 float_ireal - -# video timing set-up capability registers -min_vt_sys_clk_div 0x1120 16 -max_vt_sys_clk_div 0x1122 16 -min_vt_sys_clk_freq_mhz 0x1124 32 float_ireal -max_vt_sys_clk_freq_mhz 0x1128 32 float_ireal -min_vt_pix_clk_freq_mhz 0x112c 32 float_ireal -max_vt_pix_clk_freq_mhz 0x1130 32 float_ireal -min_vt_pix_clk_div 0x1134 16 -max_vt_pix_clk_div 0x1136 16 -clock_calculation 0x1138 -- b lane_speed 0 -- b link_decoupled 1 -- b dual_pll_op_sys_ddr 2 -- b dual_pll_op_pix_ddr 3 -num_of_vt_lanes 0x1139 -num_of_op_lanes 0x113a -op_bits_per_lane 0x113b 8 v1.1 - -# frame timing parameter limits -min_frame_length_lines 0x1140 16 -max_frame_length_lines 0x1142 16 -min_line_length_pck 0x1144 16 -max_line_length_pck 0x1146 16 -min_line_blanking_pck 0x1148 16 -min_frame_blanking_lines 0x114a 16 -min_line_length_pck_step_size 0x114c -timing_mode_capability 0x114d -- b auto_frame_length 0 -- b rolling_shutter_manual_readout 2 -- b delayed_exposure_start 3 -- b manual_exposure_embedded_data 4 -frame_margin_max_value 0x114e 16 -frame_margin_min_value 0x1150 -gain_delay_type 0x1151 -- e fixed 0 -- e variable 1 - -# output clock set-up capability registers -min_op_sys_clk_div 0x1160 16 -max_op_sys_clk_div 0x1162 16 -min_op_sys_clk_freq_mhz 0x1164 32 float_ireal -max_op_sys_clk_freq_mhz 0x1168 32 float_ireal -min_op_pix_clk_div 0x116c 16 -max_op_pix_clk_div 0x116e 16 -min_op_pix_clk_freq_mhz 0x1170 32 float_ireal -max_op_pix_clk_freq_mhz 0x1174 32 float_ireal - -# image size parameter limit registers -x_addr_min 0x1180 16 -y_addr_min 0x1182 16 -x_addr_max 0x1184 16 -y_addr_max 0x1186 16 -min_x_output_size 0x1188 16 -min_y_output_size 0x118a 16 -max_x_output_size 0x118c 16 -max_y_output_size 0x118e 16 - -x_addr_start_div_constant 0x1190 v1.1 -y_addr_start_div_constant 0x1191 v1.1 -x_addr_end_div_constant 0x1192 v1.1 -y_addr_end_div_constant 0x1193 v1.1 -x_size_div 0x1194 v1.1 -y_size_div 0x1195 v1.1 -x_output_div 0x1196 v1.1 -y_output_div 0x1197 v1.1 -non_flexible_resolution_support 0x1198 v1.1 -- b new_pix_addr 0 -- b new_output_res 1 -- b output_crop_no_pad 2 -- b output_size_lane_dep 3 - -min_op_pre_pll_clk_div 0x11a0 16 -max_op_pre_pll_clk_div 0x11a2 16 -min_op_pll_ip_clk_freq_mhz 0x11a4 32 float_ireal -max_op_pll_ip_clk_freq_mhz 0x11a8 32 float_ireal -min_op_pll_multiplier 0x11ac 16 -max_op_pll_multiplier 0x11ae 16 -min_op_pll_op_clk_freq_mhz 0x11b0 32 float_ireal -max_op_pll_op_clk_freq_mhz 0x11b4 32 float_ireal -clock_tree_pll_capability 0x11b8 8 -- b dual_pll 0 -- b single_pll 1 -- b ext_divider 2 -- b flexible_op_pix_clk_div 3 -clock_capa_type_capability 0x11b9 v1.1 -- b ireal 0 - -# sub-sampling parameters limit registers -min_even_inc 0x11c0 16 -min_odd_inc 0x11c2 16 -max_even_inc 0x11c4 16 -max_odd_inc 0x11c6 16 -aux_subsamp_capability 0x11c8 v1.1 -- b factor_power_of_2 1 -aux_subsamp_mono_capability 0x11c9 v1.1 -- b factor_power_of_2 1 -monochrome_capability 0x11ca v1.1 -- e inc_odd 0 -- e inc_even 1 -pixel_readout_capability 0x11cb v1.1 -- e bayer 0 -- e monochrome 1 -- e bayer_and_mono 2 -min_even_inc_mono 0x11cc 16 v1.1 -max_even_inc_mono 0x11ce 16 v1.1 -min_odd_inc_mono 0x11d0 16 v1.1 -max_odd_inc_mono 0x11d2 16 v1.1 -min_even_inc_bc2 0x11d4 16 v1.1 -max_even_inc_bc2 0x11d6 16 v1.1 -min_odd_inc_bc2 0x11d8 16 v1.1 -max_odd_inc_bc2 0x11da 16 v1.1 -min_even_inc_mono_bc2 0x11dc 16 v1.1 -max_even_inc_mono_bc2 0x11de 16 v1.1 -min_odd_inc_mono_bc2 0x11f0 16 v1.1 -max_odd_inc_mono_bc2 0x11f2 16 v1.1 - -# image scaling limit parameters -scaling_capability 0x1200 16 -- e none 0 -- e horizontal 1 -- e reserved 2 -scaler_m_min 0x1204 16 -scaler_m_max 0x1206 16 -scaler_n_min 0x1208 16 -scaler_n_max 0x120a 16 -digital_crop_capability 0x120e -- e none 0 -- e input_crop 1 - -# hdr limit registers -hdr_capability_1 0x1210 -- b 2x2_binning 0 -- b combined_analog_gain 1 -- b separate_analog_gain 2 -- b upscaling 3 -- b reset_sync 4 -- b direct_short_exp_timing 5 -- b direct_short_exp_synthesis 6 -min_hdr_bit_depth 0x1211 -hdr_resolution_sub_types 0x1212 -hdr_resolution_sub_type(n) 0x1213 -- l n 0 1 1 -- f row 0 3 -- f column 4 7 -hdr_capability_2 0x121b -- b combined_digital_gain 0 -- b separate_digital_gain 1 -- b timing_mode 3 -- b synthesis_mode 4 -max_hdr_bit_depth 0x121c - -# usl capability register -usl_support_capability 0x1230 v1.1 -- b clock_tree 0 -- b rev_clock_tree 1 -- b rev_clock_calc 2 -usl_clock_mode_d_capability 0x1231 v1.1 -- b cont_clock_standby 0 -- b cont_clock_vblank 1 -- b cont_clock_hblank 2 -- b noncont_clock_standby 3 -- b noncont_clock_vblank 4 -- b noncont_clock_hblank 5 -min_op_sys_clk_div_rev 0x1234 v1.1 -max_op_sys_clk_div_rev 0x1236 v1.1 -min_op_pix_clk_div_rev 0x1238 v1.1 -max_op_pix_clk_div_rev 0x123a v1.1 -min_op_sys_clk_freq_rev_mhz 0x123c 32 v1.1 float_ireal -max_op_sys_clk_freq_rev_mhz 0x1240 32 v1.1 float_ireal -min_op_pix_clk_freq_rev_mhz 0x1244 32 v1.1 float_ireal -max_op_pix_clk_freq_rev_mhz 0x1248 32 v1.1 float_ireal -max_bitrate_rev_d_mode_mbps 0x124c 32 v1.1 ireal -max_symrate_rev_c_mode_msps 0x1250 32 v1.1 ireal - -# image compression capability registers -compression_capability 0x1300 -- b dpcm_pcm_simple 0 - -# test mode capability registers -test_mode_capability 0x1310 16 -- b solid_color 0 -- b color_bars 1 -- b fade_to_grey 2 -- b pn9 3 -- b color_tile 5 -pn9_data_format1 0x1312 -pn9_data_format2 0x1313 -pn9_data_format3 0x1314 -pn9_data_format4 0x1315 -pn9_misc_capability 0x1316 -- f num_pixels 0 2 -- b compression 3 -test_pattern_capability 0x1317 v1.1 -- b no_repeat 1 -pattern_size_div_m1 0x1318 v1.1 - -# fifo capability registers -fifo_support_capability 0x1502 -- e none 0 -- e derating 1 -- e derating_overrating 2 - -# csi-2 capability registers -phy_ctrl_capability 0x1600 -- b auto_phy_ctl 0 -- b ui_phy_ctl 1 -- b dphy_time_ui_reg_1_ctl 2 -- b dphy_time_ui_reg_2_ctl 3 -- b dphy_time_ctl 4 -- b dphy_ext_time_ui_reg_1_ctl 5 -- b dphy_ext_time_ui_reg_2_ctl 6 -- b dphy_ext_time_ctl 7 -csi_dphy_lane_mode_capability 0x1601 -- b 1_lane 0 -- b 2_lane 1 -- b 3_lane 2 -- b 4_lane 3 -- b 5_lane 4 -- b 6_lane 5 -- b 7_lane 6 -- b 8_lane 7 -csi_signaling_mode_capability 0x1602 -- b csi_dphy 2 -- b csi_cphy 3 -fast_standby_capability 0x1603 -- e no_frame_truncation 0 -- e frame_truncation 1 -csi_address_control_capability 0x1604 -- b cci_addr_change 0 -- b 2nd_cci_addr 1 -- b sw_changeable_2nd_cci_addr 2 -data_type_capability 0x1605 -- b dpcm_programmable 0 -- b bottom_embedded_dt_programmable 1 -- b bottom_embedded_vc_programmable 2 -- b ext_vc_range 3 -csi_cphy_lane_mode_capability 0x1606 -- b 1_lane 0 -- b 2_lane 1 -- b 3_lane 2 -- b 4_lane 3 -- b 5_lane 4 -- b 6_lane 5 -- b 7_lane 6 -- b 8_lane 7 -emb_data_capability 0x1607 v1.1 -- b two_bytes_per_raw16 0 -- b two_bytes_per_raw20 1 -- b two_bytes_per_raw24 2 -- b no_one_byte_per_raw16 3 -- b no_one_byte_per_raw20 4 -- b no_one_byte_per_raw24 5 -max_per_lane_bitrate_lane_d_mode_mbps(n) 0x1608 32 ireal -- l n 0 7 4 4,0x32 -temp_sensor_capability 0x1618 -- b supported 0 -- b CCS_format 1 -- b reset_0x80 2 -max_per_lane_bitrate_lane_c_mode_mbps(n) 0x161a 32 ireal -- l n 0 7 4 4,0x30 -dphy_equalization_capability 0x162b -- b equalization_ctrl 0 -- b eq1 1 -- b eq2 2 -cphy_equalization_capability 0x162c -- b equalization_ctrl 0 -dphy_preamble_capability 0x162d -- b preamble_seq_ctrl 0 -dphy_ssc_capability 0x162e -- b supported 0 -cphy_calibration_capability 0x162f -- b manual 0 -- b manual_streaming 1 -- b format_1_ctrl 2 -- b format_2_ctrl 3 -- b format_3_ctrl 4 -dphy_calibration_capability 0x1630 -- b manual 0 -- b manual_streaming 1 -- b alternate_seq 2 -phy_ctrl_capability_2 0x1631 -- b tgr_length 0 -- b tgr_preamble_prog_seq 1 -- b extra_cphy_manual_timing 2 -- b clock_based_manual_cdphy 3 -- b clock_based_manual_dphy 4 -- b clock_based_manual_cphy 5 -- b manual_lp_dphy 6 -- b manual_lp_cphy 7 -lrte_cphy_capability 0x1632 -- b pdq_short 0 -- b spacer_short 1 -- b pdq_long 2 -- b spacer_long 3 -- b spacer_no_pdq 4 -lrte_dphy_capability 0x1633 -- b pdq_short_opt1 0 -- b spacer_short_opt1 1 -- b pdq_long_opt1 2 -- b spacer_long_opt1 3 -- b spacer_short_opt2 4 -- b spacer_long_opt2 5 -- b spacer_no_pdq_opt1 6 -- b spacer_variable_opt2 7 -alps_capability_dphy 0x1634 -- e lvlp_not_supported 0 0x3 -- e lvlp_supported 1 0x3 -- e controllable_lvlp 2 0x3 -alps_capability_cphy 0x1635 -- e lvlp_not_supported 0 0x3 -- e lvlp_supported 1 0x3 -- e controllable_lvlp 2 0x3 -- e alp_not_supported 0xc 0xc -- e alp_supported 0xd 0xc -- e controllable_alp 0xe 0xc -scrambling_capability 0x1636 -- b scrambling_supported 0 -- f max_seeds_per_lane_c 1 2 -- e 1 0 -- e 4 3 -- f num_seed_regs 3 5 -- e 0 0 -- e 1 1 -- e 4 4 -- b num_seed_per_lane 6 -dphy_manual_constant 0x1637 -cphy_manual_constant 0x1638 -CSI2_interface_capability_misc 0x1639 v1.1 -- b eotp_short_pkt_opt2 0 -PHY_ctrl_capability_3 0x165c v1.1 -- b dphy_timing_not_multiple 0 -- b dphy_min_timing_value_1 1 -- b twakeup_supported 2 -- b tinit_supported 3 -- b ths_exit_supported 4 -- b cphy_timing_not_multiple 5 -- b cphy_min_timing_value_1 6 -dphy_sf 0x165d v1.1 -cphy_sf 0x165e v1.1 -- f twakeup 0 3 -- f tinit 4 7 -dphy_limits_1 0x165f v1.1 -- f ths_prepare 0 3 -- f ths_zero 4 7 -dphy_limits_2 0x1660 v1.1 -- f ths_trail 0 3 -- f tclk_trail_min 4 7 -dphy_limits_3 0x1661 v1.1 -- f tclk_prepare 0 3 -- f tclk_zero 4 7 -dphy_limits_4 0x1662 v1.1 -- f tclk_post 0 3 -- f tlpx 4 7 -dphy_limits_5 0x1663 v1.1 -- f ths_exit 0 3 -- f twakeup 4 7 -dphy_limits_6 0x1664 v1.1 -- f tinit 0 3 -cphy_limits_1 0x1665 v1.1 -- f t3_prepare_max 0 3 -- f t3_lpx_max 4 7 -cphy_limits_2 0x1666 v1.1 -- f ths_exit_max 0 3 -- f twakeup_max 4 7 -cphy_limits_3 0x1667 v1.1 -- f tinit_max 0 3 - -# binning capability registers -min_frame_length_lines_bin 0x1700 16 -max_frame_length_lines_bin 0x1702 16 -min_line_length_pck_bin 0x1704 16 -max_line_length_pck_bin 0x1706 16 -min_line_blanking_pck_bin 0x1708 16 -fine_integration_time_min_bin 0x170a 16 -fine_integration_time_max_margin_bin 0x170c 16 -binning_capability 0x1710 -- e unsupported 0 -- e binning_then_subsampling 1 -- e subsampling_then_binning 2 -binning_weighting_capability 0x1711 -- b averaged 0 -- b summed 1 -- b bayer_corrected 2 -- b module_specific_weight 3 -binning_sub_types 0x1712 -binning_sub_type(n) 0x1713 -- l n 0 63 1 -- f row 0 3 -- f column 4 7 -binning_weighting_mono_capability 0x1771 v1.1 -- b averaged 0 -- b summed 1 -- b bayer_corrected 2 -- b module_specific_weight 3 -binning_sub_types_mono 0x1772 v1.1 -binning_sub_type_mono(n) 0x1773 v1.1 f -- l n 0 63 1 - -# data transfer interface capability registers -data_transfer_if_capability 0x1800 -- b supported 0 -- b polling 2 - -# sensor correction capability registers -shading_correction_capability 0x1900 -- b color_shading 0 -- b luminance_correction 1 -green_imbalance_capability 0x1901 -- b supported 0 -module_specific_correction_capability 0x1903 -defect_correction_capability 0x1904 16 -- b mapped_defect 0 -- b dynamic_couplet 2 -- b dynamic_single 5 -- b combined_dynamic 8 -defect_correction_capability_2 0x1906 16 -- b dynamic_triplet 3 -nf_capability 0x1908 -- b luma 0 -- b chroma 1 -- b combined 2 - -# optical black readout capability registers -ob_readout_capability 0x1980 -- b controllable_readout 0 -- b visible_pixel_readout 1 -- b different_vc_readout 2 -- b different_dt_readout 3 -- b prog_data_format 4 - -# color feedback capability registers -color_feedback_capability 0x1987 -- b kelvin 0 -- b awb_gain 1 - -# cfa pattern capability registers -CFA_pattern_capability 0x1990 v1.1 -- e bayer 0 -- e monochrome 1 -- e 4x4_quad_bayer 2 -- e vendor_specific 3 -CFA_pattern_conversion_capability 0x1991 v1.1 -- b bayer 0 - -# timer capability registers -flash_mode_capability 0x1a02 -- b single_strobe 0 -sa_strobe_mode_capability 0x1a03 -- b fixed_width 0 -- b edge_ctrl 1 - -# soft reset capability registers -reset_max_delay 0x1a10 v1.1 -reset_min_time 0x1a11 v1.1 - -# pdaf capability registers -pdaf_capability_1 0x1b80 -- b supported 0 -- b processed_bottom_embedded 1 -- b processed_interleaved 2 -- b raw_bottom_embedded 3 -- b raw_interleaved 4 -- b visible_pdaf_correction 5 -- b vc_interleaving 6 -- b dt_interleaving 7 -pdaf_capability_2 0x1b81 -- b ROI 0 -- b after_digital_crop 1 -- b ctrl_retimed 2 - -# bracketing interface capability registers -bracketing_lut_capability_1 0x1c00 -- b coarse_integration 0 -- b global_analog_gain 1 -- b flash 4 -- b global_digital_gain 5 -- b alternate_global_analog_gain 6 -bracketing_lut_capability_2 0x1c01 -- b single_bracketing_mode 0 -- b looped_bracketing_mode 1 -bracketing_lut_size 0x1c02 diff --git a/Documentation/driver-api/media/drivers/ccs/ccs.rst b/Documentation/driver-api/media/drivers/ccs/ccs.rst index 9164c9fa8b42..f49e971f2d92 100644 --- a/Documentation/driver-api/media/drivers/ccs/ccs.rst +++ b/Documentation/driver-api/media/drivers/ccs/ccs.rst @@ -59,7 +59,7 @@ effect in device timing and likely also in power consumption. Register definition generator ----------------------------- -The ccs-regs.txt file contains MIPI CCS register definitions that are used +The ccs-regs.asc file contains MIPI CCS register definitions that are used to produce C source code files for definitions that can be better used by programs written in C language. As there are many dependencies between the produced files, please do not modify them manually as it's error-prone and @@ -77,6 +77,6 @@ definitions: -e drivers/media/i2c/ccs/ccs-regs.h \ -L drivers/media/i2c/ccs/ccs-limits.h \ -l drivers/media/i2c/ccs/ccs-limits.c \ - -c Documentation/driver-api/media/drivers/ccs/ccs-regs.txt + -c Documentation/driver-api/media/drivers/ccs/ccs-regs.asc **Copyright** |copy| 2020 Intel Corporation diff --git a/Documentation/driver-api/media/drivers/ccs/mk-ccs-regs b/Documentation/driver-api/media/drivers/ccs/mk-ccs-regs index 3d6a2a7aac3a..6668deaf2f19 100755 --- a/Documentation/driver-api/media/drivers/ccs/mk-ccs-regs +++ b/Documentation/driver-api/media/drivers/ccs/mk-ccs-regs @@ -5,7 +5,7 @@ use Getopt::Long qw(:config no_ignore_case); use File::Basename; -my $ccsregs = "ccs-regs.txt"; +my $ccsregs = "ccs-regs.asc"; my $header; my $regarray; my $limitc; @@ -27,7 +27,7 @@ if (defined $help) { print < Date: Wed, 2 Dec 2020 15:18:19 +0100 Subject: media: Documentation: ccs: Reorder SPDX and copyright notice lines Move the SPDX tag to the top, placing the copyright notice after that. This aligns the file with existing practices. Signed-off-by: Sakari Ailus Signed-off-by: Mauro Carvalho Chehab --- Documentation/driver-api/media/drivers/ccs/ccs-regs.asc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation/driver-api') diff --git a/Documentation/driver-api/media/drivers/ccs/ccs-regs.asc b/Documentation/driver-api/media/drivers/ccs/ccs-regs.asc index 93f0131aa304..f2042acc8a45 100644 --- a/Documentation/driver-api/media/drivers/ccs/ccs-regs.asc +++ b/Documentation/driver-api/media/drivers/ccs/ccs-regs.asc @@ -1,5 +1,5 @@ -# Copyright (C) 2019--2020 Intel Corporation # SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause +# Copyright (C) 2019--2020 Intel Corporation # register rflags # - f field LSB MSB rflags -- cgit v1.2.3-59-g8ed1b