From a0d49a8f77f26609036a05e7832393b6279554db Mon Sep 17 00:00:00 2001 From: Conor Dooley Date: Tue, 27 Sep 2022 12:19:13 +0100 Subject: dt-bindings: riscv: microchip: document icicle reference design The icicle kit reference design's v2022.09 release made some changes to the memory map - including adding the ability to read the fabric clock controllers via the system controller bus & making the PCI controller work with upstream Linux. While the PCI was not working in the v2022.03 design, so nothing is broken there in terms of backwards compatibility, the fabric clocks used in the v2022.03 design were chosen by the individual run of the synthesis tool. In the v2022.09 reference design, the clocks are fixed to use the "north west" fabric Clock Conditioning Circuitry. In the v2022.10 release, the memory map on the DDR side is also changing, so to avoid making a breaking change here twice, jump over the v2022.09 release and straight to the v2022.10 one. Make use of a new compatible to denote that v2022.{09,10} reference design releases are not backwards compatible. Acked-by: Krzysztof Kozlowski Signed-off-by: Conor Dooley --- Documentation/devicetree/bindings/riscv/microchip.yaml | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/riscv/microchip.yaml b/Documentation/devicetree/bindings/riscv/microchip.yaml index 1aa7336a9672..5c1ad2108049 100644 --- a/Documentation/devicetree/bindings/riscv/microchip.yaml +++ b/Documentation/devicetree/bindings/riscv/microchip.yaml @@ -17,12 +17,18 @@ properties: $nodename: const: '/' compatible: - items: - - enum: - - microchip,mpfs-icicle-kit - - microchip,mpfs-icicle-reference-rtlv2203 - - sundance,polarberry - - const: microchip,mpfs + oneOf: + - items: + - enum: + - microchip,mpfs-icicle-reference-rtlv2203 + - microchip,mpfs-icicle-reference-rtlv2210 + - const: microchip,mpfs-icicle-kit + - const: microchip,mpfs + + - items: + - enum: + - sundance,polarberry + - const: microchip,mpfs additionalProperties: true -- cgit v1.2.3-59-g8ed1b From 0ebdc51787dbb8ef8d259daa98b8fd35babf8970 Mon Sep 17 00:00:00 2001 From: Conor Dooley Date: Tue, 27 Sep 2022 12:19:14 +0100 Subject: dt-bindings: riscv: microchip: document the aries m100pfsevp Add a compatible for the Aries Embedded M100PFSEVP SOM + EVK platform. Link: https://www.aries-embedded.com/polarfire-soc-fpga-microsemi-m100pfs-som-mpfs025t-pcie-serdes Signed-off-by: Conor Dooley Acked-by: Rob Herring --- Documentation/devicetree/bindings/riscv/microchip.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/riscv/microchip.yaml b/Documentation/devicetree/bindings/riscv/microchip.yaml index 5c1ad2108049..681cedc5578f 100644 --- a/Documentation/devicetree/bindings/riscv/microchip.yaml +++ b/Documentation/devicetree/bindings/riscv/microchip.yaml @@ -27,6 +27,7 @@ properties: - items: - enum: + - aries,m100pfsevp - sundance,polarberry - const: microchip,mpfs -- cgit v1.2.3-59-g8ed1b From db3d481698efe8a7a943ecbba9491648c5a49ef3 Mon Sep 17 00:00:00 2001 From: Shravan Chippa Date: Tue, 27 Sep 2022 12:19:15 +0100 Subject: dt-bindings: riscv: microchip: document the sev kit Update devicetree bindings document with PolarFire SoC Video Kit, known by its "sev-kit" product code. Link: https://onlinedocs.microchip.com/pr/GUID-404D3738-DC76-46BA-8683-6A77E837C2DD-en-US-1/index.html?GUID-065AEBEE-7B2C-4895-8579-B1D73D797F06 Signed-off-by: Shravan Chippa Reviewed-by: Krzysztof Kozlowski Signed-off-by: Conor Dooley --- Documentation/devicetree/bindings/riscv/microchip.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/riscv/microchip.yaml b/Documentation/devicetree/bindings/riscv/microchip.yaml index 681cedc5578f..2b8c6a695e99 100644 --- a/Documentation/devicetree/bindings/riscv/microchip.yaml +++ b/Documentation/devicetree/bindings/riscv/microchip.yaml @@ -28,6 +28,7 @@ properties: - items: - enum: - aries,m100pfsevp + - microchip,mpfs-sev-kit - sundance,polarberry - const: microchip,mpfs -- cgit v1.2.3-59-g8ed1b From abbb388d335f8c400d1baecb15d360fa0062de77 Mon Sep 17 00:00:00 2001 From: Conor Dooley Date: Mon, 10 Oct 2022 23:17:05 +0100 Subject: dt-bindings: riscv: update microchip.yaml's maintainership Daire and I are the platform maintainers for Microchip's RISC-V FPGAs. Update the maintainers in microchip.yaml to reflect this and explicitly add the binding to the SoC's MAINTAINERS entry. Acked-by: Krzysztof Kozlowski Signed-off-by: Conor Dooley Link: https://lore.kernel.org/r/20221010221704.2161221-3-conor@kernel.org/ Signed-off-by: Palmer Dabbelt --- Documentation/devicetree/bindings/riscv/microchip.yaml | 4 ++-- MAINTAINERS | 1 + 2 files changed, 3 insertions(+), 2 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/riscv/microchip.yaml b/Documentation/devicetree/bindings/riscv/microchip.yaml index 1aa7336a9672..9faf8447332b 100644 --- a/Documentation/devicetree/bindings/riscv/microchip.yaml +++ b/Documentation/devicetree/bindings/riscv/microchip.yaml @@ -7,8 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Microchip PolarFire SoC-based boards device tree bindings maintainers: - - Cyril Jean - - Lewis Hanly + - Conor Dooley + - Daire McNamara description: Microchip PolarFire SoC-based boards diff --git a/MAINTAINERS b/MAINTAINERS index 94cf47ea5f80..b3415857a812 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -17651,6 +17651,7 @@ F: Documentation/devicetree/bindings/i2c/microchip,corei2c.yaml F: Documentation/devicetree/bindings/mailbox/microchip,mpfs-mailbox.yaml F: Documentation/devicetree/bindings/net/can/microchip,mpfs-can.yaml F: Documentation/devicetree/bindings/pwm/microchip,corepwm.yaml +F: Documentation/devicetree/bindings/riscv/microchip.yaml F: Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-controller.yaml F: Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml F: Documentation/devicetree/bindings/usb/microchip,mpfs-musb.yaml -- cgit v1.2.3-59-g8ed1b From 06267eb2decaa6baac81bbd882265a8e7782dba4 Mon Sep 17 00:00:00 2001 From: Palmer Dabbelt Date: Thu, 28 Jul 2022 14:07:15 -0700 Subject: doc: RISC-V: Document that misaligned accesses are supported The RISC-V ISA manual used to mandate that misaligned accesses were supported in user mode, but that requirement was removed in 2018 via riscv-isa-manual commit 61cadb9 ("Provide new description of misaligned load/store behavior compatible with privileged architecture."). Since the Linux uABI was already frozen at that point it's just been demoted to part of the uABI, but that was never written down. Link: https://lore.kernel.org/r/20220728210715.17214-1-palmer@rivosinc.com Signed-off-by: Palmer Dabbelt --- Documentation/riscv/index.rst | 1 + Documentation/riscv/uabi.rst | 6 ++++++ 2 files changed, 7 insertions(+) create mode 100644 Documentation/riscv/uabi.rst (limited to 'Documentation') diff --git a/Documentation/riscv/index.rst b/Documentation/riscv/index.rst index e23b876ad6eb..2e5b18fbb145 100644 --- a/Documentation/riscv/index.rst +++ b/Documentation/riscv/index.rst @@ -8,6 +8,7 @@ RISC-V architecture boot-image-header vm-layout patch-acceptance + uabi features diff --git a/Documentation/riscv/uabi.rst b/Documentation/riscv/uabi.rst new file mode 100644 index 000000000000..21a82cfb6c4d --- /dev/null +++ b/Documentation/riscv/uabi.rst @@ -0,0 +1,6 @@ +.. SPDX-License-Identifier: GPL-2.0 + +RISC-V Linux User ABI +===================== + +Misaligned accesses are supported in userspace, but they may perform poorly. -- cgit v1.2.3-59-g8ed1b From 826249942679a110353e71a1d92764fcf43e7cf7 Mon Sep 17 00:00:00 2001 From: Conor Dooley Date: Tue, 23 Aug 2022 19:33:17 +0100 Subject: dt-bindings: timer: sifive,clint: add legacy riscv compatible While "real" hardware might not use the compatible string "riscv,clint0" it is present in the driver & QEMU uses it for automatically generated virt machine dtbs. To avoid dt-validate problems with QEMU produced dtbs, such as the following, add it to the binding. riscv-virt.dtb: clint@2000000: compatible:0: 'sifive,clint0' is not one of ['sifive,fu540-c000-clint', 'starfive,jh7100-clint', 'canaan,k210-clint'] Reported-by: Rob Herring Link: https://lore.kernel.org/linux-riscv/20220803170552.GA2250266-robh@kernel.org/ Reviewed-by: Rob Herring Signed-off-by: Conor Dooley Reviewed-by: Heiko Stuebner Link: https://lore.kernel.org/r/20220823183319.3314940-2-mail@conchuod.ie Signed-off-by: Palmer Dabbelt --- .../devicetree/bindings/timer/sifive,clint.yaml | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Documentation/devicetree/bindings/timer/sifive,clint.yaml index e64f46339079..bbad24165837 100644 --- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml +++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml @@ -22,12 +22,18 @@ description: properties: compatible: - items: - - enum: - - sifive,fu540-c000-clint - - starfive,jh7100-clint - - canaan,k210-clint - - const: sifive,clint0 + oneOf: + - items: + - enum: + - sifive,fu540-c000-clint + - starfive,jh7100-clint + - canaan,k210-clint + - const: sifive,clint0 + - items: + - const: sifive,clint0 + - const: riscv,clint0 + deprecated: true + description: For the QEMU virt machine only description: Should be ",-clint" and "sifive,clint". -- cgit v1.2.3-59-g8ed1b From 6e965c9bd7388762b302dca5852eb25cbe9cc085 Mon Sep 17 00:00:00 2001 From: Conor Dooley Date: Tue, 23 Aug 2022 19:33:18 +0100 Subject: dt-bindings: interrupt-controller: sifive,plic: add legacy riscv compatible While "real" hardware might not use the compatible string "riscv,plic0" it is present in the driver & QEMU uses it for automatically generated virt machine dtbs. To avoid dt-validate problems with QEMU produced dtbs, such as the following, add it to the binding. riscv-virt.dtb: plic@c000000: compatible: 'oneOf' conditional failed, one must be fixed: 'sifive,plic-1.0.0' is not one of ['sifive,fu540-c000-plic', 'starfive,jh7100-plic', 'canaan,k210-plic'] 'sifive,plic-1.0.0' is not one of ['allwinner,sun20i-d1-plic'] 'sifive,plic-1.0.0' was expected 'thead,c900-plic' was expected riscv-virt.dtb: plic@c000000: '#address-cells' is a required property Reported-by: Rob Herring Link: https://lore.kernel.org/linux-riscv/20220803170552.GA2250266-robh@kernel.org/ Reviewed-by: Rob Herring Signed-off-by: Conor Dooley Reviewed-by: Heiko Stuebner Link: https://lore.kernel.org/r/20220823183319.3314940-3-mail@conchuod.ie Signed-off-by: Palmer Dabbelt --- .../devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml index 92e0f8c3eff2..99e01f4d0a69 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml @@ -66,6 +66,11 @@ properties: - enum: - allwinner,sun20i-d1-plic - const: thead,c900-plic + - items: + - const: sifive,plic-1.0.0 + - const: riscv,plic0 + deprecated: true + description: For the QEMU virt machine only reg: maxItems: 1 -- cgit v1.2.3-59-g8ed1b From 299824e68bd0fac60f8352c940fd731fde609de1 Mon Sep 17 00:00:00 2001 From: Conor Dooley Date: Tue, 23 Aug 2022 19:33:19 +0100 Subject: dt-bindings: riscv: add new riscv,isa strings for emulators The QEMU virt and spike machines currently export a riscv,isa string of "rv64imafdcsuh", While the RISC-V foundation has been ratifying a bunch of extenstions etc, the kernel has remained relatively static with what hardware is supported - but the same is not true of QEMU. Using the virt machine and running dt-validate on the dumped dtb fails, partly due to the unexpected isa string. Rather than enumerate the many many possbilities, change the pattern to a regex, with the following assumptions: - ima are required - the single letter order is fixed & we don't care about things that can't even do "ima" - the standard multi letter extensions are all in a "_z" format where the first letter of is a valid single letter extension - _s & _h are used for supervisor and hyper visor extensions - convention says that after the first two chars, a standard multi letter extension name could be an english word (ifencei anyone?) so it's not worth restricting the charset - as the above is just convention, don't apply any charset restrictions to reduce future churn - vendor ISA extensions begind with _x and have no charset restrictions - we don't care about an e extension from an OS pov - that attempting to validate the contents of the multiletter extensions with dt-validate beyond the formatting is a futile, massively verbose or unwieldy exercise at best The following limitations also apply: - multi letter extension ordering is not enforced. dt-schema does not appear to allow for named match groups, so the resulting regex would be even more of a headache - ditto for the numbered extensions Finally, add me as a maintainer of the binding so that when it breaks in the future, I can be held responsible! Reported-by: Rob Herring Link: https://lore.kernel.org/linux-riscv/20220803170552.GA2250266-robh@kernel.org/ Reviewed-by: Andrew Jones Acked-by: Guo Ren Signed-off-by: Conor Dooley Acked-by: Heiko Stuebner Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/20220823183319.3314940-4-mail@conchuod.ie Signed-off-by: Palmer Dabbelt --- Documentation/devicetree/bindings/riscv/cpus.yaml | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index 873dd12f6e89..90a7cabf58fe 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -9,6 +9,7 @@ title: RISC-V bindings for 'cpus' DT nodes maintainers: - Paul Walmsley - Palmer Dabbelt + - Conor Dooley description: | This document uses some terminology common to the RISC-V community @@ -79,9 +80,7 @@ properties: insensitive, letters in the riscv,isa string must be all lowercase to simplify parsing. $ref: "/schemas/types.yaml#/definitions/string" - enum: - - rv64imac - - rv64imafdc + pattern: ^rv(?:64|32)imaf?d?q?c?b?v?k?h?(?:_[hsxz](?:[a-z])+)*$ # RISC-V requires 'timebase-frequency' in /cpus, so disallow it here timebase-frequency: false -- cgit v1.2.3-59-g8ed1b From 44dce4b084f83f41922ed8c2a2c7d148254848bb Mon Sep 17 00:00:00 2001 From: Zong Li Date: Tue, 13 Sep 2022 06:18:11 +0000 Subject: dt-bindings: sifive-ccache: change Sifive L2 cache to Composable cache Since composable cache may be L3 cache if private L2 cache exists, we should use its original name Composable cache to prevent confusion. Signed-off-by: Zong Li Suggested-by: Conor Dooley Suggested-by: Ben Dooks Reviewed-by: Conor Dooley Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/20220913061817.22564-2-zong.li@sifive.com Signed-off-by: Palmer Dabbelt --- .../devicetree/bindings/riscv/sifive,ccache0.yaml | 164 +++++++++++++++++++++ .../devicetree/bindings/riscv/sifive-l2-cache.yaml | 146 ------------------ 2 files changed, 164 insertions(+), 146 deletions(-) create mode 100644 Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml delete mode 100644 Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml b/Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml new file mode 100644 index 000000000000..bf3f07421f7e --- /dev/null +++ b/Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml @@ -0,0 +1,164 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright (C) 2020 SiFive, Inc. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/riscv/sifive,ccache0.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: SiFive Composable Cache Controller + +maintainers: + - Sagar Kadam + - Paul Walmsley + +description: + The SiFive Composable Cache Controller is used to provide access to fast copies + of memory for masters in a Core Complex. The Composable Cache Controller also + acts as directory-based coherency manager. + All the properties in ePAPR/DeviceTree specification applies for this platform. + +select: + properties: + compatible: + contains: + enum: + - sifive,ccache0 + - sifive,fu540-c000-ccache + - sifive,fu740-c000-ccache + + required: + - compatible + +properties: + compatible: + oneOf: + - items: + - enum: + - sifive,ccache0 + - sifive,fu540-c000-ccache + - sifive,fu740-c000-ccache + - const: cache + - items: + - const: microchip,mpfs-ccache + - const: sifive,fu540-c000-ccache + - const: cache + + cache-block-size: + const: 64 + + cache-level: + enum: [2, 3] + + cache-sets: + enum: [1024, 2048] + + cache-size: + const: 2097152 + + cache-unified: true + + interrupts: + minItems: 3 + items: + - description: DirError interrupt + - description: DataError interrupt + - description: DataFail interrupt + - description: DirFail interrupt + + reg: + maxItems: 1 + + next-level-cache: true + + memory-region: + maxItems: 1 + description: | + The reference to the reserved-memory for the L2 Loosely Integrated Memory region. + The reserved memory node should be defined as per the bindings in reserved-memory.txt. + +allOf: + - $ref: /schemas/cache-controller.yaml# + + - if: + properties: + compatible: + contains: + enum: + - sifive,fu740-c000-ccache + - microchip,mpfs-ccache + + then: + properties: + interrupts: + description: | + Must contain entries for DirError, DataError, DataFail, DirFail signals. + minItems: 4 + + else: + properties: + interrupts: + description: | + Must contain entries for DirError, DataError and DataFail signals. + maxItems: 3 + + - if: + properties: + compatible: + contains: + const: sifive,fu740-c000-ccache + + then: + properties: + cache-sets: + const: 2048 + + else: + properties: + cache-sets: + const: 1024 + + - if: + properties: + compatible: + contains: + const: sifive,ccache0 + + then: + properties: + cache-level: + enum: [2, 3] + + else: + properties: + cache-level: + const: 2 + +additionalProperties: false + +required: + - compatible + - cache-block-size + - cache-level + - cache-sets + - cache-size + - cache-unified + - interrupts + - reg + +examples: + - | + cache-controller@2010000 { + compatible = "sifive,fu540-c000-ccache", "cache"; + cache-block-size = <64>; + cache-level = <2>; + cache-sets = <1024>; + cache-size = <2097152>; + cache-unified; + reg = <0x2010000 0x1000>; + interrupt-parent = <&plic0>; + interrupts = <1>, + <2>, + <3>; + next-level-cache = <&L25>; + memory-region = <&l2_lim>; + }; diff --git a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml b/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml deleted file mode 100644 index ca3b9be58058..000000000000 --- a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml +++ /dev/null @@ -1,146 +0,0 @@ -# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) -# Copyright (C) 2020 SiFive, Inc. -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/riscv/sifive-l2-cache.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: SiFive L2 Cache Controller - -maintainers: - - Sagar Kadam - - Paul Walmsley - -description: - The SiFive Level 2 Cache Controller is used to provide access to fast copies - of memory for masters in a Core Complex. The Level 2 Cache Controller also - acts as directory-based coherency manager. - All the properties in ePAPR/DeviceTree specification applies for this platform. - -select: - properties: - compatible: - contains: - enum: - - sifive,fu540-c000-ccache - - sifive,fu740-c000-ccache - - required: - - compatible - -properties: - compatible: - oneOf: - - items: - - enum: - - sifive,fu540-c000-ccache - - sifive,fu740-c000-ccache - - const: cache - - items: - - const: microchip,mpfs-ccache - - const: sifive,fu540-c000-ccache - - const: cache - - cache-block-size: - const: 64 - - cache-level: - const: 2 - - cache-sets: - enum: [1024, 2048] - - cache-size: - const: 2097152 - - cache-unified: true - - interrupts: - minItems: 3 - items: - - description: DirError interrupt - - description: DataError interrupt - - description: DataFail interrupt - - description: DirFail interrupt - - reg: - maxItems: 1 - - next-level-cache: true - - memory-region: - maxItems: 1 - description: | - The reference to the reserved-memory for the L2 Loosely Integrated Memory region. - The reserved memory node should be defined as per the bindings in reserved-memory.txt. - -allOf: - - $ref: /schemas/cache-controller.yaml# - - - if: - properties: - compatible: - contains: - enum: - - sifive,fu740-c000-ccache - - microchip,mpfs-ccache - - then: - properties: - interrupts: - description: | - Must contain entries for DirError, DataError, DataFail, DirFail signals. - minItems: 4 - - else: - properties: - interrupts: - description: | - Must contain entries for DirError, DataError and DataFail signals. - maxItems: 3 - - - if: - properties: - compatible: - contains: - const: sifive,fu740-c000-ccache - - then: - properties: - cache-sets: - const: 2048 - - else: - properties: - cache-sets: - const: 1024 - -additionalProperties: false - -required: - - compatible - - cache-block-size - - cache-level - - cache-sets - - cache-size - - cache-unified - - interrupts - - reg - -examples: - - | - cache-controller@2010000 { - compatible = "sifive,fu540-c000-ccache", "cache"; - cache-block-size = <64>; - cache-level = <2>; - cache-sets = <1024>; - cache-size = <2097152>; - cache-unified; - reg = <0x2010000 0x1000>; - interrupt-parent = <&plic0>; - interrupts = <1>, - <2>, - <3>; - next-level-cache = <&L25>; - memory-region = <&l2_lim>; - }; -- cgit v1.2.3-59-g8ed1b