From 2bb8ad9b44c528a7f8c0e9120b85b9ecc69b2bbe Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Fri, 18 Jul 2014 18:58:57 +0200 Subject: iio: exynos-adc: add experimental touchscreen support This adds support for the touchscreen on Samsung s3c64xx. The driver is completely untested but shows roughly how it could be done, following the example of the at91 driver. compared to the old plat-samsung/adc driver, there is no support for prioritizing ts over other clients, nor for oversampling. From my reading of the code, the priorities didn't actually have any effect at all, but the oversampling might be needed. Verifying this driver is the main issue that is currently holding up multiplatform support for s3c64xx, so any help in testing is very much appreciated. The current version uses the IS_REACHABLE() that is going to be introduced in the linux-media tree, please comment this out for testing. Signed-off-by: Arnd Bergmann Acked-by: Dmitry Torokhov --- Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt | 3 +++ 1 file changed, 3 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt b/Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt index f46ca9a316a2..ccaaec6014bd 100644 --- a/Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt +++ b/Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt @@ -47,6 +47,9 @@ Required properties: - samsung,syscon-phandle Contains the PMU system controller node (To access the ADC_PHY register on Exynos5250/5420/5800/3250) +Optional properties: +- has-touchscreen: If present, indicates that a touchscreen is + connected an usable. Note: child nodes can be added for auto probing from device tree. -- cgit v1.2.3-59-g8ed1b From 4c25c5d2985c1db482cfe59ed9b3a07829a60ba9 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Fri, 30 Jan 2015 10:45:33 +0100 Subject: ARM: pxa: make more mach/*.h files local Lots of header files are never included outside of a mach-pxa directory and do not need to be made visible in include/mach, so let's just move them all down one level. Signed-off-by: Arnd Bergmann --- Documentation/arm/pxa/mfp.txt | 26 +- arch/arm/mach-pxa/am200epd.c | 4 +- arch/arm/mach-pxa/am300epd.c | 4 +- arch/arm/mach-pxa/balloon3.c | 6 +- arch/arm/mach-pxa/capc7117.c | 4 +- arch/arm/mach-pxa/cm-x255.c | 2 +- arch/arm/mach-pxa/cm-x270.c | 2 +- arch/arm/mach-pxa/cm-x2xx.c | 4 +- arch/arm/mach-pxa/cm-x300.c | 4 +- arch/arm/mach-pxa/colibri-evalboard.c | 6 +- arch/arm/mach-pxa/colibri-pxa270-income.c | 4 +- arch/arm/mach-pxa/colibri-pxa270.c | 4 +- arch/arm/mach-pxa/colibri-pxa300.c | 4 +- arch/arm/mach-pxa/colibri-pxa320.c | 8 +- arch/arm/mach-pxa/colibri-pxa3xx.c | 4 +- arch/arm/mach-pxa/colibri.h | 69 +++ arch/arm/mach-pxa/corgi.c | 6 +- arch/arm/mach-pxa/corgi_pm.c | 2 +- arch/arm/mach-pxa/csb726.c | 4 +- arch/arm/mach-pxa/csb726.h | 28 ++ arch/arm/mach-pxa/devices.c | 2 +- arch/arm/mach-pxa/em-x270.c | 4 +- arch/arm/mach-pxa/eseries-irq.h | 28 ++ arch/arm/mach-pxa/eseries.c | 6 +- arch/arm/mach-pxa/ezx.c | 2 +- arch/arm/mach-pxa/gumstix.c | 6 +- arch/arm/mach-pxa/gumstix.h | 92 ++++ arch/arm/mach-pxa/h5000.c | 6 +- arch/arm/mach-pxa/h5000.h | 113 +++++ arch/arm/mach-pxa/himalaya.c | 2 +- arch/arm/mach-pxa/hx4700.c | 2 +- arch/arm/mach-pxa/icontrol.c | 4 +- arch/arm/mach-pxa/idp.c | 4 +- arch/arm/mach-pxa/idp.h | 198 ++++++++ arch/arm/mach-pxa/include/mach/colibri.h | 69 --- arch/arm/mach-pxa/include/mach/csb726.h | 28 -- arch/arm/mach-pxa/include/mach/eseries-irq.h | 28 -- arch/arm/mach-pxa/include/mach/gumstix.h | 92 ---- arch/arm/mach-pxa/include/mach/h5000.h | 113 ----- arch/arm/mach-pxa/include/mach/idp.h | 198 -------- arch/arm/mach-pxa/include/mach/littleton.h | 13 - arch/arm/mach-pxa/include/mach/lpd270.h | 43 -- arch/arm/mach-pxa/include/mach/mfp-pxa25x.h | 225 --------- arch/arm/mach-pxa/include/mach/mfp-pxa27x.h | 471 ------------------ arch/arm/mach-pxa/include/mach/mfp-pxa2xx.h | 142 ------ arch/arm/mach-pxa/include/mach/mfp-pxa300.h | 575 ---------------------- arch/arm/mach-pxa/include/mach/mfp-pxa320.h | 461 ----------------- arch/arm/mach-pxa/include/mach/mfp-pxa3xx.h | 158 ------ arch/arm/mach-pxa/include/mach/mfp-pxa930.h | 498 ------------------- arch/arm/mach-pxa/include/mach/mioa701.h | 75 --- arch/arm/mach-pxa/include/mach/mxm8x10.h | 21 - arch/arm/mach-pxa/include/mach/palm27x.h | 81 --- arch/arm/mach-pxa/include/mach/palmt5.h | 86 ---- arch/arm/mach-pxa/include/mach/palmte2.h | 68 --- arch/arm/mach-pxa/include/mach/palmtreo.h | 68 --- arch/arm/mach-pxa/include/mach/palmz72.h | 84 ---- arch/arm/mach-pxa/include/mach/pcm027.h | 86 ---- arch/arm/mach-pxa/include/mach/pcm990_baseboard.h | 212 -------- arch/arm/mach-pxa/include/mach/pm.h | 40 -- arch/arm/mach-pxa/include/mach/pxa25x.h | 9 - arch/arm/mach-pxa/include/mach/pxa27x-udc.h | 257 ---------- arch/arm/mach-pxa/include/mach/pxa27x.h | 25 - arch/arm/mach-pxa/include/mach/pxa300.h | 7 - arch/arm/mach-pxa/include/mach/pxa320.h | 8 - arch/arm/mach-pxa/include/mach/pxa3xx.h | 8 - arch/arm/mach-pxa/include/mach/pxa930.h | 7 - arch/arm/mach-pxa/include/mach/regs-rtc.h | 23 - arch/arm/mach-pxa/include/mach/regs-u2d.h | 200 -------- arch/arm/mach-pxa/include/mach/sharpsl_pm.h | 113 ----- arch/arm/mach-pxa/include/mach/tosa_bt.h | 22 - arch/arm/mach-pxa/include/mach/udc.h | 8 - arch/arm/mach-pxa/include/mach/viper.h | 94 ---- arch/arm/mach-pxa/include/mach/zeus.h | 85 ---- arch/arm/mach-pxa/include/mach/zylonite.h | 42 -- arch/arm/mach-pxa/littleton.c | 4 +- arch/arm/mach-pxa/littleton.h | 13 + arch/arm/mach-pxa/lpd270.c | 4 +- arch/arm/mach-pxa/lpd270.h | 43 ++ arch/arm/mach-pxa/lubbock.c | 6 +- arch/arm/mach-pxa/magician.c | 6 +- arch/arm/mach-pxa/mainstone.c | 2 +- arch/arm/mach-pxa/mfp-pxa25x.h | 225 +++++++++ arch/arm/mach-pxa/mfp-pxa27x.h | 471 ++++++++++++++++++ arch/arm/mach-pxa/mfp-pxa2xx.c | 2 +- arch/arm/mach-pxa/mfp-pxa2xx.h | 142 ++++++ arch/arm/mach-pxa/mfp-pxa300.h | 575 ++++++++++++++++++++++ arch/arm/mach-pxa/mfp-pxa320.h | 461 +++++++++++++++++ arch/arm/mach-pxa/mfp-pxa3xx.c | 2 +- arch/arm/mach-pxa/mfp-pxa3xx.h | 158 ++++++ arch/arm/mach-pxa/mfp-pxa930.h | 498 +++++++++++++++++++ arch/arm/mach-pxa/mioa701.c | 10 +- arch/arm/mach-pxa/mioa701.h | 75 +++ arch/arm/mach-pxa/mp900.c | 2 +- arch/arm/mach-pxa/mxm8x10.c | 4 +- arch/arm/mach-pxa/mxm8x10.h | 21 + arch/arm/mach-pxa/palm27x.c | 6 +- arch/arm/mach-pxa/palm27x.h | 81 +++ arch/arm/mach-pxa/palmld.c | 4 +- arch/arm/mach-pxa/palmt5.c | 8 +- arch/arm/mach-pxa/palmt5.h | 86 ++++ arch/arm/mach-pxa/palmtc.c | 4 +- arch/arm/mach-pxa/palmte2.c | 6 +- arch/arm/mach-pxa/palmte2.h | 68 +++ arch/arm/mach-pxa/palmtreo.c | 10 +- arch/arm/mach-pxa/palmtreo.h | 68 +++ arch/arm/mach-pxa/palmtx.c | 6 +- arch/arm/mach-pxa/palmz72.c | 10 +- arch/arm/mach-pxa/palmz72.h | 84 ++++ arch/arm/mach-pxa/pcm027.c | 4 +- arch/arm/mach-pxa/pcm027.h | 86 ++++ arch/arm/mach-pxa/pcm990-baseboard.c | 4 +- arch/arm/mach-pxa/pcm990_baseboard.h | 212 ++++++++ arch/arm/mach-pxa/pm.c | 2 +- arch/arm/mach-pxa/pm.h | 40 ++ arch/arm/mach-pxa/poodle.c | 4 +- arch/arm/mach-pxa/pxa25x.c | 4 +- arch/arm/mach-pxa/pxa25x.h | 9 + arch/arm/mach-pxa/pxa27x-udc.h | 257 ++++++++++ arch/arm/mach-pxa/pxa27x.c | 4 +- arch/arm/mach-pxa/pxa27x.h | 25 + arch/arm/mach-pxa/pxa2xx.c | 2 +- arch/arm/mach-pxa/pxa300.c | 2 +- arch/arm/mach-pxa/pxa300.h | 7 + arch/arm/mach-pxa/pxa320.c | 2 +- arch/arm/mach-pxa/pxa320.h | 8 + arch/arm/mach-pxa/pxa3xx-ulpi.c | 2 +- arch/arm/mach-pxa/pxa3xx.c | 2 +- arch/arm/mach-pxa/pxa3xx.h | 8 + arch/arm/mach-pxa/pxa930.c | 2 +- arch/arm/mach-pxa/pxa930.h | 7 + arch/arm/mach-pxa/raumfeld.c | 2 +- arch/arm/mach-pxa/regs-rtc.h | 23 + arch/arm/mach-pxa/regs-u2d.h | 200 ++++++++ arch/arm/mach-pxa/saar.c | 2 +- arch/arm/mach-pxa/sharpsl_pm.c | 6 +- arch/arm/mach-pxa/sharpsl_pm.h | 113 +++++ arch/arm/mach-pxa/spitz.c | 6 +- arch/arm/mach-pxa/spitz_pm.c | 4 +- arch/arm/mach-pxa/stargate2.c | 6 +- arch/arm/mach-pxa/tavorevb.c | 2 +- arch/arm/mach-pxa/tosa-bt.c | 2 +- arch/arm/mach-pxa/tosa.c | 6 +- arch/arm/mach-pxa/tosa_bt.h | 22 + arch/arm/mach-pxa/trizeps4.c | 2 +- arch/arm/mach-pxa/udc.h | 8 + arch/arm/mach-pxa/viper.c | 4 +- arch/arm/mach-pxa/viper.h | 94 ++++ arch/arm/mach-pxa/vpac270.c | 6 +- arch/arm/mach-pxa/xcep.c | 2 +- arch/arm/mach-pxa/z2.c | 6 +- arch/arm/mach-pxa/zeus.c | 10 +- arch/arm/mach-pxa/zeus.h | 85 ++++ arch/arm/mach-pxa/zylonite.c | 4 +- arch/arm/mach-pxa/zylonite.h | 42 ++ arch/arm/mach-pxa/zylonite_pxa300.c | 4 +- arch/arm/mach-pxa/zylonite_pxa320.c | 4 +- drivers/clk/pxa/clk-pxa25x.c | 1 - 157 files changed, 5015 insertions(+), 5016 deletions(-) create mode 100644 arch/arm/mach-pxa/colibri.h create mode 100644 arch/arm/mach-pxa/csb726.h create mode 100644 arch/arm/mach-pxa/eseries-irq.h create mode 100644 arch/arm/mach-pxa/gumstix.h create mode 100644 arch/arm/mach-pxa/h5000.h create mode 100644 arch/arm/mach-pxa/idp.h delete mode 100644 arch/arm/mach-pxa/include/mach/colibri.h delete mode 100644 arch/arm/mach-pxa/include/mach/csb726.h delete mode 100644 arch/arm/mach-pxa/include/mach/eseries-irq.h delete mode 100644 arch/arm/mach-pxa/include/mach/gumstix.h delete mode 100644 arch/arm/mach-pxa/include/mach/h5000.h delete mode 100644 arch/arm/mach-pxa/include/mach/idp.h delete mode 100644 arch/arm/mach-pxa/include/mach/littleton.h delete mode 100644 arch/arm/mach-pxa/include/mach/lpd270.h delete mode 100644 arch/arm/mach-pxa/include/mach/mfp-pxa25x.h delete mode 100644 arch/arm/mach-pxa/include/mach/mfp-pxa27x.h delete mode 100644 arch/arm/mach-pxa/include/mach/mfp-pxa2xx.h delete mode 100644 arch/arm/mach-pxa/include/mach/mfp-pxa300.h delete mode 100644 arch/arm/mach-pxa/include/mach/mfp-pxa320.h delete mode 100644 arch/arm/mach-pxa/include/mach/mfp-pxa3xx.h delete mode 100644 arch/arm/mach-pxa/include/mach/mfp-pxa930.h delete mode 100644 arch/arm/mach-pxa/include/mach/mioa701.h delete mode 100644 arch/arm/mach-pxa/include/mach/mxm8x10.h delete mode 100644 arch/arm/mach-pxa/include/mach/palm27x.h delete mode 100644 arch/arm/mach-pxa/include/mach/palmt5.h delete mode 100644 arch/arm/mach-pxa/include/mach/palmte2.h delete mode 100644 arch/arm/mach-pxa/include/mach/palmtreo.h delete mode 100644 arch/arm/mach-pxa/include/mach/palmz72.h delete mode 100644 arch/arm/mach-pxa/include/mach/pcm027.h delete mode 100644 arch/arm/mach-pxa/include/mach/pcm990_baseboard.h delete mode 100644 arch/arm/mach-pxa/include/mach/pm.h delete mode 100644 arch/arm/mach-pxa/include/mach/pxa25x.h delete mode 100644 arch/arm/mach-pxa/include/mach/pxa27x-udc.h delete mode 100644 arch/arm/mach-pxa/include/mach/pxa27x.h delete mode 100644 arch/arm/mach-pxa/include/mach/pxa300.h delete mode 100644 arch/arm/mach-pxa/include/mach/pxa320.h delete mode 100644 arch/arm/mach-pxa/include/mach/pxa3xx.h delete mode 100644 arch/arm/mach-pxa/include/mach/pxa930.h delete mode 100644 arch/arm/mach-pxa/include/mach/regs-rtc.h delete mode 100644 arch/arm/mach-pxa/include/mach/regs-u2d.h delete mode 100644 arch/arm/mach-pxa/include/mach/sharpsl_pm.h delete mode 100644 arch/arm/mach-pxa/include/mach/tosa_bt.h delete mode 100644 arch/arm/mach-pxa/include/mach/udc.h delete mode 100644 arch/arm/mach-pxa/include/mach/viper.h delete mode 100644 arch/arm/mach-pxa/include/mach/zeus.h delete mode 100644 arch/arm/mach-pxa/include/mach/zylonite.h create mode 100644 arch/arm/mach-pxa/littleton.h create mode 100644 arch/arm/mach-pxa/lpd270.h create mode 100644 arch/arm/mach-pxa/mfp-pxa25x.h create mode 100644 arch/arm/mach-pxa/mfp-pxa27x.h create mode 100644 arch/arm/mach-pxa/mfp-pxa2xx.h create mode 100644 arch/arm/mach-pxa/mfp-pxa300.h create mode 100644 arch/arm/mach-pxa/mfp-pxa320.h create mode 100644 arch/arm/mach-pxa/mfp-pxa3xx.h create mode 100644 arch/arm/mach-pxa/mfp-pxa930.h create mode 100644 arch/arm/mach-pxa/mioa701.h create mode 100644 arch/arm/mach-pxa/mxm8x10.h create mode 100644 arch/arm/mach-pxa/palm27x.h create mode 100644 arch/arm/mach-pxa/palmt5.h create mode 100644 arch/arm/mach-pxa/palmte2.h create mode 100644 arch/arm/mach-pxa/palmtreo.h create mode 100644 arch/arm/mach-pxa/palmz72.h create mode 100644 arch/arm/mach-pxa/pcm027.h create mode 100644 arch/arm/mach-pxa/pcm990_baseboard.h create mode 100644 arch/arm/mach-pxa/pm.h create mode 100644 arch/arm/mach-pxa/pxa25x.h create mode 100644 arch/arm/mach-pxa/pxa27x-udc.h create mode 100644 arch/arm/mach-pxa/pxa27x.h create mode 100644 arch/arm/mach-pxa/pxa300.h create mode 100644 arch/arm/mach-pxa/pxa320.h create mode 100644 arch/arm/mach-pxa/pxa3xx.h create mode 100644 arch/arm/mach-pxa/pxa930.h create mode 100644 arch/arm/mach-pxa/regs-rtc.h create mode 100644 arch/arm/mach-pxa/regs-u2d.h create mode 100644 arch/arm/mach-pxa/sharpsl_pm.h create mode 100644 arch/arm/mach-pxa/tosa_bt.h create mode 100644 arch/arm/mach-pxa/udc.h create mode 100644 arch/arm/mach-pxa/viper.h create mode 100644 arch/arm/mach-pxa/zeus.h create mode 100644 arch/arm/mach-pxa/zylonite.h (limited to 'Documentation') diff --git a/Documentation/arm/pxa/mfp.txt b/Documentation/arm/pxa/mfp.txt index a179e5bc02c9..0b7cab978c02 100644 --- a/Documentation/arm/pxa/mfp.txt +++ b/Documentation/arm/pxa/mfp.txt @@ -49,7 +49,7 @@ to this new MFP mechanism, here are several key points: internal controllers like PWM, SSP and UART, with 128 internal signals which can be routed to external through one or more MFPs (e.g. GPIO<0> can be routed through either MFP_PIN_GPIO0 as well as MFP_PIN_GPIO0_2, - see arch/arm/mach-pxa/mach/include/mfp-pxa300.h) + see arch/arm/mach-pxa/mfp-pxa300.h) 2. Alternate function configuration is removed from this GPIO controller, the remaining functions are pure GPIO-specific, i.e. @@ -76,11 +76,11 @@ For board code writers, here are some guidelines: 1. include ONE of the following header files in your .c: - - #include - - #include - - #include - - #include - - #include + - #include "mfp-pxa25x.h" + - #include "mfp-pxa27x.h" + - #include "mfp-pxa300.h" + - #include "mfp-pxa320.h" + - #include "mfp-pxa930.h" NOTE: only one file in your .c, depending on the processors used, because pin configuration definitions may conflict in these file (i.e. @@ -203,20 +203,20 @@ make them effective there-after. 1. Unified pin definitions - enum constants for all configurable pins 2. processor-neutral bit definitions for a possible MFP configuration - - arch/arm/mach-pxa/include/mach/mfp-pxa3xx.h + - arch/arm/mach-pxa/mfp-pxa3xx.h for PXA3xx specific MFPR register bit definitions and PXA3xx common pin configurations - - arch/arm/mach-pxa/include/mach/mfp-pxa2xx.h + - arch/arm/mach-pxa/mfp-pxa2xx.h for PXA2xx specific definitions and PXA25x/PXA27x common pin configurations - - arch/arm/mach-pxa/include/mach/mfp-pxa25x.h - arch/arm/mach-pxa/include/mach/mfp-pxa27x.h - arch/arm/mach-pxa/include/mach/mfp-pxa300.h - arch/arm/mach-pxa/include/mach/mfp-pxa320.h - arch/arm/mach-pxa/include/mach/mfp-pxa930.h + - arch/arm/mach-pxa/mfp-pxa25x.h + arch/arm/mach-pxa/mfp-pxa27x.h + arch/arm/mach-pxa/mfp-pxa300.h + arch/arm/mach-pxa/mfp-pxa320.h + arch/arm/mach-pxa/mfp-pxa930.h for processor specific definitions diff --git a/arch/arm/mach-pxa/am200epd.c b/arch/arm/mach-pxa/am200epd.c index 12fb0f4ae359..50e18ed37fa6 100644 --- a/arch/arm/mach-pxa/am200epd.c +++ b/arch/arm/mach-pxa/am200epd.c @@ -30,8 +30,8 @@ #include #include -#include -#include +#include "pxa25x.h" +#include "gumstix.h" #include #include "generic.h" diff --git a/arch/arm/mach-pxa/am300epd.c b/arch/arm/mach-pxa/am300epd.c index 8b90c4f2d430..17d08abeeb17 100644 --- a/arch/arm/mach-pxa/am300epd.c +++ b/arch/arm/mach-pxa/am300epd.c @@ -28,8 +28,8 @@ #include #include -#include -#include +#include "gumstix.h" +#include "mfp-pxa25x.h" #include #include diff --git a/arch/arm/mach-pxa/balloon3.c b/arch/arm/mach-pxa/balloon3.c index a727282bfa99..782a0a883c01 100644 --- a/arch/arm/mach-pxa/balloon3.c +++ b/arch/arm/mach-pxa/balloon3.c @@ -42,13 +42,13 @@ #include #include -#include +#include "pxa27x.h" #include #include #include #include -#include -#include +#include "udc.h" +#include "pxa27x-udc.h" #include #include diff --git a/arch/arm/mach-pxa/capc7117.c b/arch/arm/mach-pxa/capc7117.c index bf366b39fa61..1c3cbfca9f40 100644 --- a/arch/arm/mach-pxa/capc7117.c +++ b/arch/arm/mach-pxa/capc7117.c @@ -29,8 +29,8 @@ #include #include -#include -#include +#include "pxa320.h" +#include "mxm8x10.h" #include "generic.h" diff --git a/arch/arm/mach-pxa/cm-x255.c b/arch/arm/mach-pxa/cm-x255.c index be751470d37b..b592f79a1742 100644 --- a/arch/arm/mach-pxa/cm-x255.c +++ b/arch/arm/mach-pxa/cm-x255.c @@ -22,7 +22,7 @@ #include #include -#include +#include "pxa25x.h" #include "generic.h" diff --git a/arch/arm/mach-pxa/cm-x270.c b/arch/arm/mach-pxa/cm-x270.c index 2503db9e3253..fa5f51d633a3 100644 --- a/arch/arm/mach-pxa/cm-x270.c +++ b/arch/arm/mach-pxa/cm-x270.c @@ -21,7 +21,7 @@ #include #include -#include +#include "pxa27x.h" #include #include diff --git a/arch/arm/mach-pxa/cm-x2xx.c b/arch/arm/mach-pxa/cm-x2xx.c index a17a91eb8e9a..f2d801160079 100644 --- a/arch/arm/mach-pxa/cm-x2xx.c +++ b/arch/arm/mach-pxa/cm-x2xx.c @@ -22,9 +22,9 @@ #include #include -#include +#include "pxa25x.h" #undef GPIO24_SSP1_SFRM -#include +#include "pxa27x.h" #include #include #include diff --git a/arch/arm/mach-pxa/cm-x300.c b/arch/arm/mach-pxa/cm-x300.c index a7dae60810e8..5f5ac7c8faf0 100644 --- a/arch/arm/mach-pxa/cm-x300.c +++ b/arch/arm/mach-pxa/cm-x300.c @@ -47,8 +47,8 @@ #include #include -#include -#include +#include "pxa300.h" +#include "pxa27x-udc.h" #include #include #include diff --git a/arch/arm/mach-pxa/colibri-evalboard.c b/arch/arm/mach-pxa/colibri-evalboard.c index 638b0bb88426..dc44fbbe5073 100644 --- a/arch/arm/mach-pxa/colibri-evalboard.c +++ b/arch/arm/mach-pxa/colibri-evalboard.c @@ -22,11 +22,11 @@ #include #include -#include -#include +#include "pxa27x.h" +#include "colibri.h" #include #include -#include +#include "pxa27x-udc.h" #include "generic.h" #include "devices.h" diff --git a/arch/arm/mach-pxa/colibri-pxa270-income.c b/arch/arm/mach-pxa/colibri-pxa270-income.c index db20d25daaab..8cff770e6a00 100644 --- a/arch/arm/mach-pxa/colibri-pxa270-income.c +++ b/arch/arm/mach-pxa/colibri-pxa270-income.c @@ -30,8 +30,8 @@ #include #include #include -#include -#include +#include "pxa27x.h" +#include "pxa27x-udc.h" #include #include "devices.h" diff --git a/arch/arm/mach-pxa/colibri-pxa270.c b/arch/arm/mach-pxa/colibri-pxa270.c index 3503826333c7..e68acdd0cdbb 100644 --- a/arch/arm/mach-pxa/colibri-pxa270.c +++ b/arch/arm/mach-pxa/colibri-pxa270.c @@ -27,8 +27,8 @@ #include #include -#include -#include +#include "colibri.h" +#include "pxa27x.h" #include "devices.h" #include "generic.h" diff --git a/arch/arm/mach-pxa/colibri-pxa300.c b/arch/arm/mach-pxa/colibri-pxa300.c index f1a1ac1fbd85..6a5558d95d4e 100644 --- a/arch/arm/mach-pxa/colibri-pxa300.c +++ b/arch/arm/mach-pxa/colibri-pxa300.c @@ -22,8 +22,8 @@ #include #include -#include -#include +#include "pxa300.h" +#include "colibri.h" #include #include #include diff --git a/arch/arm/mach-pxa/colibri-pxa320.c b/arch/arm/mach-pxa/colibri-pxa320.c index f6cc8b0ab82f..17067a3039a8 100644 --- a/arch/arm/mach-pxa/colibri-pxa320.c +++ b/arch/arm/mach-pxa/colibri-pxa320.c @@ -23,13 +23,13 @@ #include #include -#include -#include +#include "pxa320.h" +#include "colibri.h" #include #include #include -#include -#include +#include "pxa27x-udc.h" +#include "udc.h" #include "generic.h" #include "devices.h" diff --git a/arch/arm/mach-pxa/colibri-pxa3xx.c b/arch/arm/mach-pxa/colibri-pxa3xx.c index 8240291ab8cf..b04431bb4ba7 100644 --- a/arch/arm/mach-pxa/colibri-pxa3xx.c +++ b/arch/arm/mach-pxa/colibri-pxa3xx.c @@ -22,8 +22,8 @@ #include #include #include -#include -#include +#include "mfp-pxa300.h" +#include "colibri.h" #include #include #include diff --git a/arch/arm/mach-pxa/colibri.h b/arch/arm/mach-pxa/colibri.h new file mode 100644 index 000000000000..cb4236e98a0f --- /dev/null +++ b/arch/arm/mach-pxa/colibri.h @@ -0,0 +1,69 @@ +#ifndef _COLIBRI_H_ +#define _COLIBRI_H_ + +#include +#include + +/* + * base board glue for PXA270 module + */ + +enum { + COLIBRI_EVALBOARD = 0, + COLIBRI_PXA270_INCOME, +}; + +#if defined(CONFIG_MACH_COLIBRI_EVALBOARD) +extern void colibri_evalboard_init(void); +#else +static inline void colibri_evalboard_init(void) {} +#endif + +#if defined(CONFIG_MACH_COLIBRI_PXA270_INCOME) +extern void colibri_pxa270_income_boardinit(void); +#else +static inline void colibri_pxa270_income_boardinit(void) {} +#endif + +/* + * common settings for all modules + */ + +#if defined(CONFIG_MMC_PXA) || defined(CONFIG_MMC_PXA_MODULE) +extern void colibri_pxa3xx_init_mmc(mfp_cfg_t *pins, int len, int detect_pin); +#else +static inline void colibri_pxa3xx_init_mmc(mfp_cfg_t *pins, int len, int detect_pin) {} +#endif + +#if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULE) +extern void colibri_pxa3xx_init_lcd(int bl_pin); +#else +static inline void colibri_pxa3xx_init_lcd(int bl_pin) {} +#endif + +#if defined(CONFIG_AX88796) +extern void colibri_pxa3xx_init_eth(struct ax_plat_data *plat_data); +#endif + +#if defined(CONFIG_MTD_NAND_PXA3xx) || defined(CONFIG_MTD_NAND_PXA3xx_MODULE) +extern void colibri_pxa3xx_init_nand(void); +#else +static inline void colibri_pxa3xx_init_nand(void) {} +#endif + +/* physical memory regions */ +#define COLIBRI_SDRAM_BASE 0xa0000000 /* SDRAM region */ + +/* GPIO definitions for Colibri PXA270 */ +#define GPIO114_COLIBRI_PXA270_ETH_IRQ 114 +#define GPIO0_COLIBRI_PXA270_SD_DETECT 0 +#define GPIO113_COLIBRI_PXA270_TS_IRQ 113 + +/* GPIO definitions for Colibri PXA300/310 */ +#define GPIO13_COLIBRI_PXA300_SD_DETECT 13 + +/* GPIO definitions for Colibri PXA320 */ +#define GPIO28_COLIBRI_PXA320_SD_DETECT 28 + +#endif /* _COLIBRI_H_ */ + diff --git a/arch/arm/mach-pxa/corgi.c b/arch/arm/mach-pxa/corgi.c index 89f790dda93e..dc109dc3a622 100644 --- a/arch/arm/mach-pxa/corgi.c +++ b/arch/arm/mach-pxa/corgi.c @@ -48,12 +48,12 @@ #include #include -#include +#include "pxa25x.h" #include #include -#include +#include "udc.h" #include -#include +#include "sharpsl_pm.h" #include #include diff --git a/arch/arm/mach-pxa/corgi_pm.c b/arch/arm/mach-pxa/corgi_pm.c index 7a39efc50865..d9206811be9b 100644 --- a/arch/arm/mach-pxa/corgi_pm.c +++ b/arch/arm/mach-pxa/corgi_pm.c @@ -27,7 +27,7 @@ #include #include -#include +#include "sharpsl_pm.h" #include "generic.h" diff --git a/arch/arm/mach-pxa/csb726.c b/arch/arm/mach-pxa/csb726.c index fadfff8feaef..bf19b8426d2c 100644 --- a/arch/arm/mach-pxa/csb726.c +++ b/arch/arm/mach-pxa/csb726.c @@ -21,8 +21,8 @@ #include #include -#include -#include +#include "csb726.h" +#include "pxa27x.h" #include #include #include diff --git a/arch/arm/mach-pxa/csb726.h b/arch/arm/mach-pxa/csb726.h new file mode 100644 index 000000000000..f1f2a78cfd16 --- /dev/null +++ b/arch/arm/mach-pxa/csb726.h @@ -0,0 +1,28 @@ +/* + * Support for Cogent CSB726 + * + * Copyright (c) 2008 Dmitry Baryshkov + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ +#ifndef CSB726_H +#define CSB726_H + +#include /* PXA_GPIO_TO_IRQ */ + +#define CSB726_GPIO_IRQ_LAN 52 +#define CSB726_GPIO_IRQ_SM501 53 +#define CSB726_GPIO_MMC_DETECT 100 +#define CSB726_GPIO_MMC_RO 101 + +#define CSB726_FLASH_SIZE (64 * 1024 * 1024) +#define CSB726_FLASH_uMON (8 * 1024 * 1024) + +#define CSB726_IRQ_LAN PXA_GPIO_TO_IRQ(CSB726_GPIO_IRQ_LAN) +#define CSB726_IRQ_SM501 PXA_GPIO_TO_IRQ(CSB726_GPIO_IRQ_SM501) + +#endif + diff --git a/arch/arm/mach-pxa/devices.c b/arch/arm/mach-pxa/devices.c index 2a6e0ae2b920..597c697c39ae 100644 --- a/arch/arm/mach-pxa/devices.c +++ b/arch/arm/mach-pxa/devices.c @@ -6,7 +6,7 @@ #include #include -#include +#include "udc.h" #include #include #include diff --git a/arch/arm/mach-pxa/em-x270.c b/arch/arm/mach-pxa/em-x270.c index 9d7072b04045..be5c44657d28 100644 --- a/arch/arm/mach-pxa/em-x270.c +++ b/arch/arm/mach-pxa/em-x270.c @@ -39,8 +39,8 @@ #include #include -#include -#include +#include "pxa27x.h" +#include "pxa27x-udc.h" #include #include #include diff --git a/arch/arm/mach-pxa/eseries-irq.h b/arch/arm/mach-pxa/eseries-irq.h new file mode 100644 index 000000000000..de292b269c63 --- /dev/null +++ b/arch/arm/mach-pxa/eseries-irq.h @@ -0,0 +1,28 @@ +/* + * eseries-irq.h + * + * Copyright (C) Ian Molton + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#define ANGELX_IRQ_BASE (IRQ_BOARD_START+8) +#define IRQ_ANGELX(n) (ANGELX_IRQ_BASE + (n)) + +#define ANGELX_RDY0_IRQ IRQ_ANGELX(0) +#define ANGELX_ST0_IRQ IRQ_ANGELX(1) +#define ANGELX_CD0_IRQ IRQ_ANGELX(2) +#define ANGELX_RDY1_IRQ IRQ_ANGELX(3) +#define ANGELX_ST1_IRQ IRQ_ANGELX(4) +#define ANGELX_CD1_IRQ IRQ_ANGELX(5) + +#define TMIO_IRQ_BASE (IRQ_BOARD_START+0) +#define IRQ_TMIO(n) (TMIO_IRQ_BASE + (n)) + +#define TMIO_SD_IRQ IRQ_TMIO(1) +#define TMIO_USB_IRQ IRQ_TMIO(2) + +#define ESERIES_NR_IRQS (IRQ_BOARD_START + 16) diff --git a/arch/arm/mach-pxa/eseries.c b/arch/arm/mach-pxa/eseries.c index 16dc95f68125..0b00b226f54b 100644 --- a/arch/arm/mach-pxa/eseries.c +++ b/arch/arm/mach-pxa/eseries.c @@ -31,12 +31,12 @@ #include #include -#include +#include "pxa25x.h" #include -#include +#include "eseries-irq.h" #include #include -#include +#include "udc.h" #include #include "devices.h" diff --git a/arch/arm/mach-pxa/ezx.c b/arch/arm/mach-pxa/ezx.c index 9a9c15bfcd34..f987ae3eff6c 100644 --- a/arch/arm/mach-pxa/ezx.c +++ b/arch/arm/mach-pxa/ezx.c @@ -29,7 +29,7 @@ #include #include -#include +#include "pxa27x.h" #include #include #include diff --git a/arch/arm/mach-pxa/gumstix.c b/arch/arm/mach-pxa/gumstix.c index f6c76a3ee3b2..6815a9357774 100644 --- a/arch/arm/mach-pxa/gumstix.c +++ b/arch/arm/mach-pxa/gumstix.c @@ -40,10 +40,10 @@ #include #include -#include +#include "pxa25x.h" #include -#include -#include +#include "udc.h" +#include "gumstix.h" #include "generic.h" diff --git a/arch/arm/mach-pxa/gumstix.h b/arch/arm/mach-pxa/gumstix.h new file mode 100644 index 000000000000..825f2d1260ae --- /dev/null +++ b/arch/arm/mach-pxa/gumstix.h @@ -0,0 +1,92 @@ +/* + * arch/arm/mach-pxa/include/mach/gumstix.h + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include /* PXA_GPIO_TO_IRQ */ + +/* BTRESET - Reset line to Bluetooth module, active low signal. */ +#define GPIO_GUMSTIX_BTRESET 7 +#define GPIO_GUMSTIX_BTRESET_MD (GPIO_GUMSTIX_BTRESET | GPIO_OUT) + + +/* +GPIOn - Input from MAX823 (or equiv), normalizing USB +5V into a clean +interrupt signal for determining cable presence. On the gumstix F, +this moves to GPIO17 and GPIO37. */ + +/* GPIOx - Connects to USB D+ and used as a pull-up after GPIOn +has detected a cable insertion; driven low otherwise. */ + +#define GPIO_GUMSTIX_USB_GPIOn 35 +#define GPIO_GUMSTIX_USB_GPIOx 41 + +/* usb state change */ +#define GUMSTIX_USB_INTR_IRQ PXA_GPIO_TO_IRQ(GPIO_GUMSTIX_USB_GPIOn) + +#define GPIO_GUMSTIX_USB_GPIOn_MD (GPIO_GUMSTIX_USB_GPIOn | GPIO_IN) +#define GPIO_GUMSTIX_USB_GPIOx_CON_MD (GPIO_GUMSTIX_USB_GPIOx | GPIO_OUT) +#define GPIO_GUMSTIX_USB_GPIOx_DIS_MD (GPIO_GUMSTIX_USB_GPIOx | GPIO_IN) + +/* + * SD/MMC definitions + */ +#define GUMSTIX_GPIO_nSD_WP 22 /* SD Write Protect */ +#define GUMSTIX_GPIO_nSD_DETECT 11 /* MMC/SD Card Detect */ +#define GUMSTIX_IRQ_GPIO_nSD_DETECT PXA_GPIO_TO_IRQ(GUMSTIX_GPIO_nSD_DETECT) + +/* + * SMC Ethernet definitions + * ETH_RST provides a hardware reset line to the ethernet chip + * ETH is the IRQ line in from the ethernet chip to the PXA + */ +#define GPIO_GUMSTIX_ETH0_RST 80 +#define GPIO_GUMSTIX_ETH0_RST_MD (GPIO_GUMSTIX_ETH0_RST | GPIO_OUT) +#define GPIO_GUMSTIX_ETH1_RST 52 +#define GPIO_GUMSTIX_ETH1_RST_MD (GPIO_GUMSTIX_ETH1_RST | GPIO_OUT) + +#define GPIO_GUMSTIX_ETH0 36 +#define GPIO_GUMSTIX_ETH0_MD (GPIO_GUMSTIX_ETH0 | GPIO_IN) +#define GUMSTIX_ETH0_IRQ PXA_GPIO_TO_IRQ(GPIO_GUMSTIX_ETH0) +#define GPIO_GUMSTIX_ETH1 27 +#define GPIO_GUMSTIX_ETH1_MD (GPIO_GUMSTIX_ETH1 | GPIO_IN) +#define GUMSTIX_ETH1_IRQ PXA_GPIO_TO_IRQ(GPIO_GUMSTIX_ETH1) + + +/* CF reset line */ +#define GPIO8_RESET 8 + +/* CF slot 0 */ +#define GPIO4_nBVD1 4 +#define GPIO4_nSTSCHG GPIO4_nBVD1 +#define GPIO11_nCD 11 +#define GPIO26_PRDY_nBSY 26 +#define GUMSTIX_S0_nSTSCHG_IRQ PXA_GPIO_TO_IRQ(GPIO4_nSTSCHG) +#define GUMSTIX_S0_nCD_IRQ PXA_GPIO_TO_IRQ(GPIO11_nCD) +#define GUMSTIX_S0_PRDY_nBSY_IRQ PXA_GPIO_TO_IRQ(GPIO26_PRDY_nBSY) + +/* CF slot 1 */ +#define GPIO18_nBVD1 18 +#define GPIO18_nSTSCHG GPIO18_nBVD1 +#define GPIO36_nCD 36 +#define GPIO27_PRDY_nBSY 27 +#define GUMSTIX_S1_nSTSCHG_IRQ PXA_GPIO_TO_IRQ(GPIO18_nSTSCHG) +#define GUMSTIX_S1_nCD_IRQ PXA_GPIO_TO_IRQ(GPIO36_nCD) +#define GUMSTIX_S1_PRDY_nBSY_IRQ PXA_GPIO_TO_IRQ(GPIO27_PRDY_nBSY) + +/* CF GPIO line modes */ +#define GPIO4_nSTSCHG_MD (GPIO4_nSTSCHG | GPIO_IN) +#define GPIO8_RESET_MD (GPIO8_RESET | GPIO_OUT) +#define GPIO11_nCD_MD (GPIO11_nCD | GPIO_IN) +#define GPIO18_nSTSCHG_MD (GPIO18_nSTSCHG | GPIO_IN) +#define GPIO26_PRDY_nBSY_MD (GPIO26_PRDY_nBSY | GPIO_IN) +#define GPIO27_PRDY_nBSY_MD (GPIO27_PRDY_nBSY | GPIO_IN) +#define GPIO36_nCD_MD (GPIO36_nCD | GPIO_IN) + +/* for expansion boards that can't be programatically detected */ +extern int am200_init(void); +extern int am300_init(void); + diff --git a/arch/arm/mach-pxa/h5000.c b/arch/arm/mach-pxa/h5000.c index 875ec3351499..be2a9c3fd55b 100644 --- a/arch/arm/mach-pxa/h5000.c +++ b/arch/arm/mach-pxa/h5000.c @@ -30,9 +30,9 @@ #include #include -#include -#include -#include +#include "pxa25x.h" +#include "h5000.h" +#include "udc.h" #include #include "generic.h" diff --git a/arch/arm/mach-pxa/h5000.h b/arch/arm/mach-pxa/h5000.h new file mode 100644 index 000000000000..252461fd2ac8 --- /dev/null +++ b/arch/arm/mach-pxa/h5000.h @@ -0,0 +1,113 @@ +/* + * Hardware definitions for HP iPAQ h5xxx Handheld Computers + * + * Copyright(20)02 Hewlett-Packard Company. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * COMPAQ COMPUTER CORPORATION MAKES NO WARRANTIES, EXPRESSED OR IMPLIED, + * AS TO THE USEFULNESS OR CORRECTNESS OF THIS CODE OR ITS + * FITNESS FOR ANY PARTICULAR PURPOSE. + * + * Author: Jamey Hicks + */ + +#ifndef __ASM_ARCH_H5000_H +#define __ASM_ARCH_H5000_H + +#include "mfp-pxa25x.h" + +/* + * CPU GPIOs + */ + +#define H5000_GPIO_POWER_BUTTON (0) +#define H5000_GPIO_RESET_BUTTON_N (1) +#define H5000_GPIO_OPT_INT (2) +#define H5000_GPIO_BACKUP_POWER (3) +#define H5000_GPIO_ACTION_BUTTON (4) +#define H5000_GPIO_COM_DCD_SOMETHING (5) /* what is this really ? */ +/* 6 not connected */ +#define H5000_GPIO_RESET_BUTTON_AGAIN_N (7) /* connected to gpio 1 as well */ +/* 8 not connected */ +#define H5000_GPIO_RSO_N (9) /* reset output from max1702 which regulates 3.3 and 2.5 */ +#define H5000_GPIO_ASIC_INT_N (10) /* from companion asic */ +#define H5000_GPIO_BT_ENV_0 (11) /* to LMX9814, set to 1 according to regdump */ +/*(12) not connected */ +#define H5000_GPIO_BT_ENV_1 (13) /* to LMX9814, set to 1 according to regdump */ +#define H5000_GPIO_BT_WU (14) /* from LMX9814, Defined as HOST_WAKEUP in the LMX9820 data sheet */ +/*(15) is CS1# */ +/*(16) not connected */ +/*(17) not connected */ +/*(18) is pcmcia ready */ +/*(19) is dreq1 */ +/*(20) is dreq0 */ +#define H5000_GPIO_OE_RD_NWR (21) /* output enable on rd/nwr signal to companion asic */ +/*(22) is not connected */ +#define H5000_GPIO_OPT_SPI_CLK (23) /* to extension pack */ +#define H5000_GPIO_OPT_SPI_CS_N (24) /* to extension pack */ +#define H5000_GPIO_OPT_SPI_DOUT (25) /* to extension pack */ +#define H5000_GPIO_OPT_SPI_DIN (26) /* to extension pack */ +/*(27) not connected */ +#define H5000_GPIO_I2S_BITCLK (28) /* connected to AC97 codec */ +#define H5000_GPIO_I2S_DATAOUT (29) /* connected to AC97 codec */ +#define H5000_GPIO_I2S_DATAIN (30) /* connected to AC97 codec */ +#define H5000_GPIO_I2S_LRCLK (31) /* connected to AC97 codec */ +#define H5000_GPIO_I2S_SYSCLK (32) /* connected to AC97 codec */ +/*(33) is CS5# */ +#define H5000_GPIO_COM_RXD (34) /* connected to cradle/cable connector */ +#define H5000_GPIO_COM_CTS (35) /* connected to cradle/cable connector */ +#define H5000_GPIO_COM_DCD (36) /* connected to cradle/cable connector */ +#define H5000_GPIO_COM_DSR (37) /* connected to cradle/cable connector */ +#define H5000_GPIO_COM_RI (38) /* connected to cradle/cable connector */ +#define H5000_GPIO_COM_TXD (39) /* connected to cradle/cable connector */ +#define H5000_GPIO_COM_DTR (40) /* connected to cradle/cable connector */ +#define H5000_GPIO_COM_RTS (41) /* connected to cradle/cable connector */ + +#define H5000_GPIO_BT_RXD (42) /* connected to BT (LMX9814) */ +#define H5000_GPIO_BT_TXD (43) /* connected to BT (LMX9814) */ +#define H5000_GPIO_BT_CTS (44) /* connected to BT (LMX9814) */ +#define H5000_GPIO_BT_RTS (45) /* connected to BT (LMX9814) */ + +#define H5000_GPIO_IRDA_RXD (46) +#define H5000_GPIO_IRDA_TXD (47) + +#define H5000_GPIO_POE_N (48) /* used for pcmcia */ +#define H5000_GPIO_PWE_N (49) /* used for pcmcia */ +#define H5000_GPIO_PIOR_N (50) /* used for pcmcia */ +#define H5000_GPIO_PIOW_N (51) /* used for pcmcia */ +#define H5000_GPIO_PCE1_N (52) /* used for pcmcia */ +#define H5000_GPIO_PCE2_N (53) /* used for pcmcia */ +#define H5000_GPIO_PSKTSEL (54) /* used for pcmcia */ +#define H5000_GPIO_PREG_N (55) /* used for pcmcia */ +#define H5000_GPIO_PWAIT_N (56) /* used for pcmcia */ +#define H5000_GPIO_IOIS16_N (57) /* used for pcmcia */ + +#define H5000_GPIO_IRDA_SD (58) /* to hsdl3002 sd */ +/*(59) not connected */ +#define H5000_GPIO_POWER_SD_N (60) /* controls power to SD */ +#define H5000_GPIO_POWER_RS232_N (61) /* inverted FORCEON to rs232 transceiver */ +#define H5000_GPIO_POWER_ACCEL_N (62) /* controls power to accel */ +/*(63) is not connected */ +#define H5000_GPIO_OPT_NVRAM (64) /* controls power to expansion pack */ +#define H5000_GPIO_CHG_EN (65) /* to sc801 en */ +#define H5000_GPIO_USB_PULLUP (66) /* USB d+ pullup via 1.5K resistor */ +#define H5000_GPIO_BT_2V8_N (67) /* 2.8V used by bluetooth */ +#define H5000_GPIO_EXT_CHG_RATE (68) /* enables external charging rate */ +/*(69) is not connected */ +#define H5000_GPIO_CIR_RESET (70) /* consumer IR reset */ +#define H5000_GPIO_POWER_LIGHT_SENSOR_N (71) +#define H5000_GPIO_BT_M_RESET (72) +#define H5000_GPIO_STD_CHG_RATE (73) +#define H5000_GPIO_SD_WP_N (74) +#define H5000_GPIO_MOTOR_ON_N (75) /* external pullup on this */ +#define H5000_GPIO_HEADPHONE_DETECT (76) +#define H5000_GPIO_USB_CHG_RATE (77) /* select rate for charging via usb */ +/*(78) is CS2# */ +/*(79) is CS3# */ +/*(80) is CS4# */ + +#endif /* __ASM_ARCH_H5000_H */ diff --git a/arch/arm/mach-pxa/himalaya.c b/arch/arm/mach-pxa/himalaya.c index 7a8d749a07b8..70e9c06595f6 100644 --- a/arch/arm/mach-pxa/himalaya.c +++ b/arch/arm/mach-pxa/himalaya.c @@ -24,7 +24,7 @@ #include #include -#include +#include "pxa25x.h" #include "generic.h" diff --git a/arch/arm/mach-pxa/hx4700.c b/arch/arm/mach-pxa/hx4700.c index b076a835eb21..4a2f9aba93ea 100644 --- a/arch/arm/mach-pxa/hx4700.c +++ b/arch/arm/mach-pxa/hx4700.c @@ -44,7 +44,7 @@ #include #include -#include +#include "pxa27x.h" #include #include diff --git a/arch/arm/mach-pxa/icontrol.c b/arch/arm/mach-pxa/icontrol.c index a1869f9b6219..cbaf4f6edcda 100644 --- a/arch/arm/mach-pxa/icontrol.c +++ b/arch/arm/mach-pxa/icontrol.c @@ -20,8 +20,8 @@ #include #include -#include -#include +#include "pxa320.h" +#include "mxm8x10.h" #include #include diff --git a/arch/arm/mach-pxa/idp.c b/arch/arm/mach-pxa/idp.c index f6d02e4cbcda..c410d84b243d 100644 --- a/arch/arm/mach-pxa/idp.c +++ b/arch/arm/mach-pxa/idp.c @@ -31,8 +31,8 @@ #include #include -#include -#include +#include "pxa25x.h" +#include "idp.h" #include #include #include diff --git a/arch/arm/mach-pxa/idp.h b/arch/arm/mach-pxa/idp.h new file mode 100644 index 000000000000..7182ff92b732 --- /dev/null +++ b/arch/arm/mach-pxa/idp.h @@ -0,0 +1,198 @@ +/* + * arch/arm/mach-pxa/include/mach/idp.h + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Copyright (c) 2001 Cliff Brake, Accelent Systems Inc. + * + * 2001-09-13: Cliff Brake + * Initial code + * + * 2005-02-15: Cliff Brake + * + * Changes for 2.6 kernel. + */ + + +/* + * Note: this file must be safe to include in assembly files + * + * Support for the Vibren PXA255 IDP requires rev04 or later + * IDP hardware. + */ + +#include /* PXA_GPIO_TO_IRQ */ + +#define IDP_FLASH_PHYS (PXA_CS0_PHYS) +#define IDP_ALT_FLASH_PHYS (PXA_CS1_PHYS) +#define IDP_MEDIAQ_PHYS (PXA_CS3_PHYS) +#define IDP_IDE_PHYS (PXA_CS5_PHYS + 0x03000000) +#define IDP_ETH_PHYS (PXA_CS5_PHYS + 0x03400000) +#define IDP_COREVOLT_PHYS (PXA_CS5_PHYS + 0x03800000) +#define IDP_CPLD_PHYS (PXA_CS5_PHYS + 0x03C00000) + + +/* + * virtual memory map + */ + +#define IDP_COREVOLT_VIRT (0xf0000000) +#define IDP_COREVOLT_SIZE (1*1024*1024) + +#define IDP_CPLD_VIRT (IDP_COREVOLT_VIRT + IDP_COREVOLT_SIZE) +#define IDP_CPLD_SIZE (1*1024*1024) + +#if (IDP_CPLD_VIRT + IDP_CPLD_SIZE) > 0xfc000000 +#error Your custom IO space is getting a bit large !! +#endif + +#define CPLD_P2V(x) ((x) - IDP_CPLD_PHYS + IDP_CPLD_VIRT) +#define CPLD_V2P(x) ((x) - IDP_CPLD_VIRT + IDP_CPLD_PHYS) + +#ifndef __ASSEMBLY__ +# define __CPLD_REG(x) (*((volatile unsigned long *)CPLD_P2V(x))) +#else +# define __CPLD_REG(x) CPLD_P2V(x) +#endif + +/* board level registers in the CPLD: (offsets from CPLD_VIRT) */ + +#define _IDP_CPLD_REV (IDP_CPLD_PHYS + 0x00) +#define _IDP_CPLD_PERIPH_PWR (IDP_CPLD_PHYS + 0x04) +#define _IDP_CPLD_LED_CONTROL (IDP_CPLD_PHYS + 0x08) +#define _IDP_CPLD_KB_COL_HIGH (IDP_CPLD_PHYS + 0x0C) +#define _IDP_CPLD_KB_COL_LOW (IDP_CPLD_PHYS + 0x10) +#define _IDP_CPLD_PCCARD_EN (IDP_CPLD_PHYS + 0x14) +#define _IDP_CPLD_GPIOH_DIR (IDP_CPLD_PHYS + 0x18) +#define _IDP_CPLD_GPIOH_VALUE (IDP_CPLD_PHYS + 0x1C) +#define _IDP_CPLD_GPIOL_DIR (IDP_CPLD_PHYS + 0x20) +#define _IDP_CPLD_GPIOL_VALUE (IDP_CPLD_PHYS + 0x24) +#define _IDP_CPLD_PCCARD_PWR (IDP_CPLD_PHYS + 0x28) +#define _IDP_CPLD_MISC_CTRL (IDP_CPLD_PHYS + 0x2C) +#define _IDP_CPLD_LCD (IDP_CPLD_PHYS + 0x30) +#define _IDP_CPLD_FLASH_WE (IDP_CPLD_PHYS + 0x34) + +#define _IDP_CPLD_KB_ROW (IDP_CPLD_PHYS + 0x50) +#define _IDP_CPLD_PCCARD0_STATUS (IDP_CPLD_PHYS + 0x54) +#define _IDP_CPLD_PCCARD1_STATUS (IDP_CPLD_PHYS + 0x58) +#define _IDP_CPLD_MISC_STATUS (IDP_CPLD_PHYS + 0x5C) + +/* FPGA register virtual addresses */ + +#define IDP_CPLD_REV __CPLD_REG(_IDP_CPLD_REV) +#define IDP_CPLD_PERIPH_PWR __CPLD_REG(_IDP_CPLD_PERIPH_PWR) +#define IDP_CPLD_LED_CONTROL __CPLD_REG(_IDP_CPLD_LED_CONTROL) +#define IDP_CPLD_KB_COL_HIGH __CPLD_REG(_IDP_CPLD_KB_COL_HIGH) +#define IDP_CPLD_KB_COL_LOW __CPLD_REG(_IDP_CPLD_KB_COL_LOW) +#define IDP_CPLD_PCCARD_EN __CPLD_REG(_IDP_CPLD_PCCARD_EN) +#define IDP_CPLD_GPIOH_DIR __CPLD_REG(_IDP_CPLD_GPIOH_DIR) +#define IDP_CPLD_GPIOH_VALUE __CPLD_REG(_IDP_CPLD_GPIOH_VALUE) +#define IDP_CPLD_GPIOL_DIR __CPLD_REG(_IDP_CPLD_GPIOL_DIR) +#define IDP_CPLD_GPIOL_VALUE __CPLD_REG(_IDP_CPLD_GPIOL_VALUE) +#define IDP_CPLD_PCCARD_PWR __CPLD_REG(_IDP_CPLD_PCCARD_PWR) +#define IDP_CPLD_MISC_CTRL __CPLD_REG(_IDP_CPLD_MISC_CTRL) +#define IDP_CPLD_LCD __CPLD_REG(_IDP_CPLD_LCD) +#define IDP_CPLD_FLASH_WE __CPLD_REG(_IDP_CPLD_FLASH_WE) + +#define IDP_CPLD_KB_ROW __CPLD_REG(_IDP_CPLD_KB_ROW) +#define IDP_CPLD_PCCARD0_STATUS __CPLD_REG(_IDP_CPLD_PCCARD0_STATUS) +#define IDP_CPLD_PCCARD1_STATUS __CPLD_REG(_IDP_CPLD_PCCARD1_STATUS) +#define IDP_CPLD_MISC_STATUS __CPLD_REG(_IDP_CPLD_MISC_STATUS) + + +/* + * Bit masks for various registers + */ + +// IDP_CPLD_PCCARD_PWR +#define PCC0_PWR0 (1 << 0) +#define PCC0_PWR1 (1 << 1) +#define PCC0_PWR2 (1 << 2) +#define PCC0_PWR3 (1 << 3) +#define PCC1_PWR0 (1 << 4) +#define PCC1_PWR1 (1 << 5) +#define PCC1_PWR2 (1 << 6) +#define PCC1_PWR3 (1 << 7) + +// IDP_CPLD_PCCARD_EN +#define PCC0_RESET (1 << 6) +#define PCC1_RESET (1 << 7) +#define PCC0_ENABLE (1 << 0) +#define PCC1_ENABLE (1 << 1) + +// IDP_CPLD_PCCARDx_STATUS +#define _PCC_WRPROT (1 << 7) // 7-4 read as low true +#define _PCC_RESET (1 << 6) +#define _PCC_IRQ (1 << 5) +#define _PCC_INPACK (1 << 4) +#define PCC_BVD2 (1 << 3) +#define PCC_BVD1 (1 << 2) +#define PCC_VS2 (1 << 1) +#define PCC_VS1 (1 << 0) + +/* A listing of interrupts used by external hardware devices */ + +#define TOUCH_PANEL_IRQ PXA_GPIO_TO_IRQ(5) +#define IDE_IRQ PXA_GPIO_TO_IRQ(21) + +#define TOUCH_PANEL_IRQ_EDGE IRQ_TYPE_EDGE_FALLING + +#define ETHERNET_IRQ PXA_GPIO_TO_IRQ(4) +#define ETHERNET_IRQ_EDGE IRQ_TYPE_EDGE_RISING + +#define IDE_IRQ_EDGE IRQ_TYPE_EDGE_RISING + +#define PCMCIA_S0_CD_VALID PXA_GPIO_TO_IRQ(7) +#define PCMCIA_S0_CD_VALID_EDGE IRQ_TYPE_EDGE_BOTH + +#define PCMCIA_S1_CD_VALID PXA_GPIO_TO_IRQ(8) +#define PCMCIA_S1_CD_VALID_EDGE IRQ_TYPE_EDGE_BOTH + +#define PCMCIA_S0_RDYINT PXA_GPIO_TO_IRQ(19) +#define PCMCIA_S1_RDYINT PXA_GPIO_TO_IRQ(22) + + +/* + * Macros for LED Driver + */ + +/* leds 0 = ON */ +#define IDP_HB_LED (1<<5) +#define IDP_BUSY_LED (1<<6) + +#define IDP_LEDS_MASK (IDP_HB_LED | IDP_BUSY_LED) + +/* + * macros for MTD driver + */ + +#define FLASH_WRITE_PROTECT_DISABLE() ((IDP_CPLD_FLASH_WE) &= ~(0x1)) +#define FLASH_WRITE_PROTECT_ENABLE() ((IDP_CPLD_FLASH_WE) |= (0x1)) + +/* + * macros for matrix keyboard driver + */ + +#define KEYBD_MATRIX_NUMBER_INPUTS 7 +#define KEYBD_MATRIX_NUMBER_OUTPUTS 14 + +#define KEYBD_MATRIX_INVERT_OUTPUT_LOGIC FALSE +#define KEYBD_MATRIX_INVERT_INPUT_LOGIC FALSE + +#define KEYBD_MATRIX_SETTLING_TIME_US 100 +#define KEYBD_MATRIX_KEYSTATE_DEBOUNCE_CONSTANT 2 + +#define KEYBD_MATRIX_SET_OUTPUTS(outputs) \ +{\ + IDP_CPLD_KB_COL_LOW = outputs;\ + IDP_CPLD_KB_COL_HIGH = outputs >> 7;\ +} + +#define KEYBD_MATRIX_GET_INPUTS(inputs) \ +{\ + inputs = (IDP_CPLD_KB_ROW & 0x7f);\ +} + + diff --git a/arch/arm/mach-pxa/include/mach/colibri.h b/arch/arm/mach-pxa/include/mach/colibri.h deleted file mode 100644 index cb4236e98a0f..000000000000 --- a/arch/arm/mach-pxa/include/mach/colibri.h +++ /dev/null @@ -1,69 +0,0 @@ -#ifndef _COLIBRI_H_ -#define _COLIBRI_H_ - -#include -#include - -/* - * base board glue for PXA270 module - */ - -enum { - COLIBRI_EVALBOARD = 0, - COLIBRI_PXA270_INCOME, -}; - -#if defined(CONFIG_MACH_COLIBRI_EVALBOARD) -extern void colibri_evalboard_init(void); -#else -static inline void colibri_evalboard_init(void) {} -#endif - -#if defined(CONFIG_MACH_COLIBRI_PXA270_INCOME) -extern void colibri_pxa270_income_boardinit(void); -#else -static inline void colibri_pxa270_income_boardinit(void) {} -#endif - -/* - * common settings for all modules - */ - -#if defined(CONFIG_MMC_PXA) || defined(CONFIG_MMC_PXA_MODULE) -extern void colibri_pxa3xx_init_mmc(mfp_cfg_t *pins, int len, int detect_pin); -#else -static inline void colibri_pxa3xx_init_mmc(mfp_cfg_t *pins, int len, int detect_pin) {} -#endif - -#if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULE) -extern void colibri_pxa3xx_init_lcd(int bl_pin); -#else -static inline void colibri_pxa3xx_init_lcd(int bl_pin) {} -#endif - -#if defined(CONFIG_AX88796) -extern void colibri_pxa3xx_init_eth(struct ax_plat_data *plat_data); -#endif - -#if defined(CONFIG_MTD_NAND_PXA3xx) || defined(CONFIG_MTD_NAND_PXA3xx_MODULE) -extern void colibri_pxa3xx_init_nand(void); -#else -static inline void colibri_pxa3xx_init_nand(void) {} -#endif - -/* physical memory regions */ -#define COLIBRI_SDRAM_BASE 0xa0000000 /* SDRAM region */ - -/* GPIO definitions for Colibri PXA270 */ -#define GPIO114_COLIBRI_PXA270_ETH_IRQ 114 -#define GPIO0_COLIBRI_PXA270_SD_DETECT 0 -#define GPIO113_COLIBRI_PXA270_TS_IRQ 113 - -/* GPIO definitions for Colibri PXA300/310 */ -#define GPIO13_COLIBRI_PXA300_SD_DETECT 13 - -/* GPIO definitions for Colibri PXA320 */ -#define GPIO28_COLIBRI_PXA320_SD_DETECT 28 - -#endif /* _COLIBRI_H_ */ - diff --git a/arch/arm/mach-pxa/include/mach/csb726.h b/arch/arm/mach-pxa/include/mach/csb726.h deleted file mode 100644 index 00cfbbbf73f7..000000000000 --- a/arch/arm/mach-pxa/include/mach/csb726.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - * Support for Cogent CSB726 - * - * Copyright (c) 2008 Dmitry Baryshkov - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - */ -#ifndef CSB726_H -#define CSB726_H - -#include "irqs.h" /* PXA_GPIO_TO_IRQ */ - -#define CSB726_GPIO_IRQ_LAN 52 -#define CSB726_GPIO_IRQ_SM501 53 -#define CSB726_GPIO_MMC_DETECT 100 -#define CSB726_GPIO_MMC_RO 101 - -#define CSB726_FLASH_SIZE (64 * 1024 * 1024) -#define CSB726_FLASH_uMON (8 * 1024 * 1024) - -#define CSB726_IRQ_LAN PXA_GPIO_TO_IRQ(CSB726_GPIO_IRQ_LAN) -#define CSB726_IRQ_SM501 PXA_GPIO_TO_IRQ(CSB726_GPIO_IRQ_SM501) - -#endif - diff --git a/arch/arm/mach-pxa/include/mach/eseries-irq.h b/arch/arm/mach-pxa/include/mach/eseries-irq.h deleted file mode 100644 index de292b269c63..000000000000 --- a/arch/arm/mach-pxa/include/mach/eseries-irq.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - * eseries-irq.h - * - * Copyright (C) Ian Molton - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - */ - -#define ANGELX_IRQ_BASE (IRQ_BOARD_START+8) -#define IRQ_ANGELX(n) (ANGELX_IRQ_BASE + (n)) - -#define ANGELX_RDY0_IRQ IRQ_ANGELX(0) -#define ANGELX_ST0_IRQ IRQ_ANGELX(1) -#define ANGELX_CD0_IRQ IRQ_ANGELX(2) -#define ANGELX_RDY1_IRQ IRQ_ANGELX(3) -#define ANGELX_ST1_IRQ IRQ_ANGELX(4) -#define ANGELX_CD1_IRQ IRQ_ANGELX(5) - -#define TMIO_IRQ_BASE (IRQ_BOARD_START+0) -#define IRQ_TMIO(n) (TMIO_IRQ_BASE + (n)) - -#define TMIO_SD_IRQ IRQ_TMIO(1) -#define TMIO_USB_IRQ IRQ_TMIO(2) - -#define ESERIES_NR_IRQS (IRQ_BOARD_START + 16) diff --git a/arch/arm/mach-pxa/include/mach/gumstix.h b/arch/arm/mach-pxa/include/mach/gumstix.h deleted file mode 100644 index f7df27bbb42e..000000000000 --- a/arch/arm/mach-pxa/include/mach/gumstix.h +++ /dev/null @@ -1,92 +0,0 @@ -/* - * arch/arm/mach-pxa/include/mach/gumstix.h - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include "irqs.h" /* PXA_GPIO_TO_IRQ */ - -/* BTRESET - Reset line to Bluetooth module, active low signal. */ -#define GPIO_GUMSTIX_BTRESET 7 -#define GPIO_GUMSTIX_BTRESET_MD (GPIO_GUMSTIX_BTRESET | GPIO_OUT) - - -/* -GPIOn - Input from MAX823 (or equiv), normalizing USB +5V into a clean -interrupt signal for determining cable presence. On the gumstix F, -this moves to GPIO17 and GPIO37. */ - -/* GPIOx - Connects to USB D+ and used as a pull-up after GPIOn -has detected a cable insertion; driven low otherwise. */ - -#define GPIO_GUMSTIX_USB_GPIOn 35 -#define GPIO_GUMSTIX_USB_GPIOx 41 - -/* usb state change */ -#define GUMSTIX_USB_INTR_IRQ PXA_GPIO_TO_IRQ(GPIO_GUMSTIX_USB_GPIOn) - -#define GPIO_GUMSTIX_USB_GPIOn_MD (GPIO_GUMSTIX_USB_GPIOn | GPIO_IN) -#define GPIO_GUMSTIX_USB_GPIOx_CON_MD (GPIO_GUMSTIX_USB_GPIOx | GPIO_OUT) -#define GPIO_GUMSTIX_USB_GPIOx_DIS_MD (GPIO_GUMSTIX_USB_GPIOx | GPIO_IN) - -/* - * SD/MMC definitions - */ -#define GUMSTIX_GPIO_nSD_WP 22 /* SD Write Protect */ -#define GUMSTIX_GPIO_nSD_DETECT 11 /* MMC/SD Card Detect */ -#define GUMSTIX_IRQ_GPIO_nSD_DETECT PXA_GPIO_TO_IRQ(GUMSTIX_GPIO_nSD_DETECT) - -/* - * SMC Ethernet definitions - * ETH_RST provides a hardware reset line to the ethernet chip - * ETH is the IRQ line in from the ethernet chip to the PXA - */ -#define GPIO_GUMSTIX_ETH0_RST 80 -#define GPIO_GUMSTIX_ETH0_RST_MD (GPIO_GUMSTIX_ETH0_RST | GPIO_OUT) -#define GPIO_GUMSTIX_ETH1_RST 52 -#define GPIO_GUMSTIX_ETH1_RST_MD (GPIO_GUMSTIX_ETH1_RST | GPIO_OUT) - -#define GPIO_GUMSTIX_ETH0 36 -#define GPIO_GUMSTIX_ETH0_MD (GPIO_GUMSTIX_ETH0 | GPIO_IN) -#define GUMSTIX_ETH0_IRQ PXA_GPIO_TO_IRQ(GPIO_GUMSTIX_ETH0) -#define GPIO_GUMSTIX_ETH1 27 -#define GPIO_GUMSTIX_ETH1_MD (GPIO_GUMSTIX_ETH1 | GPIO_IN) -#define GUMSTIX_ETH1_IRQ PXA_GPIO_TO_IRQ(GPIO_GUMSTIX_ETH1) - - -/* CF reset line */ -#define GPIO8_RESET 8 - -/* CF slot 0 */ -#define GPIO4_nBVD1 4 -#define GPIO4_nSTSCHG GPIO4_nBVD1 -#define GPIO11_nCD 11 -#define GPIO26_PRDY_nBSY 26 -#define GUMSTIX_S0_nSTSCHG_IRQ PXA_GPIO_TO_IRQ(GPIO4_nSTSCHG) -#define GUMSTIX_S0_nCD_IRQ PXA_GPIO_TO_IRQ(GPIO11_nCD) -#define GUMSTIX_S0_PRDY_nBSY_IRQ PXA_GPIO_TO_IRQ(GPIO26_PRDY_nBSY) - -/* CF slot 1 */ -#define GPIO18_nBVD1 18 -#define GPIO18_nSTSCHG GPIO18_nBVD1 -#define GPIO36_nCD 36 -#define GPIO27_PRDY_nBSY 27 -#define GUMSTIX_S1_nSTSCHG_IRQ PXA_GPIO_TO_IRQ(GPIO18_nSTSCHG) -#define GUMSTIX_S1_nCD_IRQ PXA_GPIO_TO_IRQ(GPIO36_nCD) -#define GUMSTIX_S1_PRDY_nBSY_IRQ PXA_GPIO_TO_IRQ(GPIO27_PRDY_nBSY) - -/* CF GPIO line modes */ -#define GPIO4_nSTSCHG_MD (GPIO4_nSTSCHG | GPIO_IN) -#define GPIO8_RESET_MD (GPIO8_RESET | GPIO_OUT) -#define GPIO11_nCD_MD (GPIO11_nCD | GPIO_IN) -#define GPIO18_nSTSCHG_MD (GPIO18_nSTSCHG | GPIO_IN) -#define GPIO26_PRDY_nBSY_MD (GPIO26_PRDY_nBSY | GPIO_IN) -#define GPIO27_PRDY_nBSY_MD (GPIO27_PRDY_nBSY | GPIO_IN) -#define GPIO36_nCD_MD (GPIO36_nCD | GPIO_IN) - -/* for expansion boards that can't be programatically detected */ -extern int am200_init(void); -extern int am300_init(void); - diff --git a/arch/arm/mach-pxa/include/mach/h5000.h b/arch/arm/mach-pxa/include/mach/h5000.h deleted file mode 100644 index 2a5ae3802787..000000000000 --- a/arch/arm/mach-pxa/include/mach/h5000.h +++ /dev/null @@ -1,113 +0,0 @@ -/* - * Hardware definitions for HP iPAQ h5xxx Handheld Computers - * - * Copyright(20)02 Hewlett-Packard Company. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * COMPAQ COMPUTER CORPORATION MAKES NO WARRANTIES, EXPRESSED OR IMPLIED, - * AS TO THE USEFULNESS OR CORRECTNESS OF THIS CODE OR ITS - * FITNESS FOR ANY PARTICULAR PURPOSE. - * - * Author: Jamey Hicks - */ - -#ifndef __ASM_ARCH_H5000_H -#define __ASM_ARCH_H5000_H - -#include - -/* - * CPU GPIOs - */ - -#define H5000_GPIO_POWER_BUTTON (0) -#define H5000_GPIO_RESET_BUTTON_N (1) -#define H5000_GPIO_OPT_INT (2) -#define H5000_GPIO_BACKUP_POWER (3) -#define H5000_GPIO_ACTION_BUTTON (4) -#define H5000_GPIO_COM_DCD_SOMETHING (5) /* what is this really ? */ -/* 6 not connected */ -#define H5000_GPIO_RESET_BUTTON_AGAIN_N (7) /* connected to gpio 1 as well */ -/* 8 not connected */ -#define H5000_GPIO_RSO_N (9) /* reset output from max1702 which regulates 3.3 and 2.5 */ -#define H5000_GPIO_ASIC_INT_N (10) /* from companion asic */ -#define H5000_GPIO_BT_ENV_0 (11) /* to LMX9814, set to 1 according to regdump */ -/*(12) not connected */ -#define H5000_GPIO_BT_ENV_1 (13) /* to LMX9814, set to 1 according to regdump */ -#define H5000_GPIO_BT_WU (14) /* from LMX9814, Defined as HOST_WAKEUP in the LMX9820 data sheet */ -/*(15) is CS1# */ -/*(16) not connected */ -/*(17) not connected */ -/*(18) is pcmcia ready */ -/*(19) is dreq1 */ -/*(20) is dreq0 */ -#define H5000_GPIO_OE_RD_NWR (21) /* output enable on rd/nwr signal to companion asic */ -/*(22) is not connected */ -#define H5000_GPIO_OPT_SPI_CLK (23) /* to extension pack */ -#define H5000_GPIO_OPT_SPI_CS_N (24) /* to extension pack */ -#define H5000_GPIO_OPT_SPI_DOUT (25) /* to extension pack */ -#define H5000_GPIO_OPT_SPI_DIN (26) /* to extension pack */ -/*(27) not connected */ -#define H5000_GPIO_I2S_BITCLK (28) /* connected to AC97 codec */ -#define H5000_GPIO_I2S_DATAOUT (29) /* connected to AC97 codec */ -#define H5000_GPIO_I2S_DATAIN (30) /* connected to AC97 codec */ -#define H5000_GPIO_I2S_LRCLK (31) /* connected to AC97 codec */ -#define H5000_GPIO_I2S_SYSCLK (32) /* connected to AC97 codec */ -/*(33) is CS5# */ -#define H5000_GPIO_COM_RXD (34) /* connected to cradle/cable connector */ -#define H5000_GPIO_COM_CTS (35) /* connected to cradle/cable connector */ -#define H5000_GPIO_COM_DCD (36) /* connected to cradle/cable connector */ -#define H5000_GPIO_COM_DSR (37) /* connected to cradle/cable connector */ -#define H5000_GPIO_COM_RI (38) /* connected to cradle/cable connector */ -#define H5000_GPIO_COM_TXD (39) /* connected to cradle/cable connector */ -#define H5000_GPIO_COM_DTR (40) /* connected to cradle/cable connector */ -#define H5000_GPIO_COM_RTS (41) /* connected to cradle/cable connector */ - -#define H5000_GPIO_BT_RXD (42) /* connected to BT (LMX9814) */ -#define H5000_GPIO_BT_TXD (43) /* connected to BT (LMX9814) */ -#define H5000_GPIO_BT_CTS (44) /* connected to BT (LMX9814) */ -#define H5000_GPIO_BT_RTS (45) /* connected to BT (LMX9814) */ - -#define H5000_GPIO_IRDA_RXD (46) -#define H5000_GPIO_IRDA_TXD (47) - -#define H5000_GPIO_POE_N (48) /* used for pcmcia */ -#define H5000_GPIO_PWE_N (49) /* used for pcmcia */ -#define H5000_GPIO_PIOR_N (50) /* used for pcmcia */ -#define H5000_GPIO_PIOW_N (51) /* used for pcmcia */ -#define H5000_GPIO_PCE1_N (52) /* used for pcmcia */ -#define H5000_GPIO_PCE2_N (53) /* used for pcmcia */ -#define H5000_GPIO_PSKTSEL (54) /* used for pcmcia */ -#define H5000_GPIO_PREG_N (55) /* used for pcmcia */ -#define H5000_GPIO_PWAIT_N (56) /* used for pcmcia */ -#define H5000_GPIO_IOIS16_N (57) /* used for pcmcia */ - -#define H5000_GPIO_IRDA_SD (58) /* to hsdl3002 sd */ -/*(59) not connected */ -#define H5000_GPIO_POWER_SD_N (60) /* controls power to SD */ -#define H5000_GPIO_POWER_RS232_N (61) /* inverted FORCEON to rs232 transceiver */ -#define H5000_GPIO_POWER_ACCEL_N (62) /* controls power to accel */ -/*(63) is not connected */ -#define H5000_GPIO_OPT_NVRAM (64) /* controls power to expansion pack */ -#define H5000_GPIO_CHG_EN (65) /* to sc801 en */ -#define H5000_GPIO_USB_PULLUP (66) /* USB d+ pullup via 1.5K resistor */ -#define H5000_GPIO_BT_2V8_N (67) /* 2.8V used by bluetooth */ -#define H5000_GPIO_EXT_CHG_RATE (68) /* enables external charging rate */ -/*(69) is not connected */ -#define H5000_GPIO_CIR_RESET (70) /* consumer IR reset */ -#define H5000_GPIO_POWER_LIGHT_SENSOR_N (71) -#define H5000_GPIO_BT_M_RESET (72) -#define H5000_GPIO_STD_CHG_RATE (73) -#define H5000_GPIO_SD_WP_N (74) -#define H5000_GPIO_MOTOR_ON_N (75) /* external pullup on this */ -#define H5000_GPIO_HEADPHONE_DETECT (76) -#define H5000_GPIO_USB_CHG_RATE (77) /* select rate for charging via usb */ -/*(78) is CS2# */ -/*(79) is CS3# */ -/*(80) is CS4# */ - -#endif /* __ASM_ARCH_H5000_H */ diff --git a/arch/arm/mach-pxa/include/mach/idp.h b/arch/arm/mach-pxa/include/mach/idp.h deleted file mode 100644 index 7e63f4680271..000000000000 --- a/arch/arm/mach-pxa/include/mach/idp.h +++ /dev/null @@ -1,198 +0,0 @@ -/* - * arch/arm/mach-pxa/include/mach/idp.h - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * Copyright (c) 2001 Cliff Brake, Accelent Systems Inc. - * - * 2001-09-13: Cliff Brake - * Initial code - * - * 2005-02-15: Cliff Brake - * - * Changes for 2.6 kernel. - */ - - -/* - * Note: this file must be safe to include in assembly files - * - * Support for the Vibren PXA255 IDP requires rev04 or later - * IDP hardware. - */ - -#include "irqs.h" /* PXA_GPIO_TO_IRQ */ - -#define IDP_FLASH_PHYS (PXA_CS0_PHYS) -#define IDP_ALT_FLASH_PHYS (PXA_CS1_PHYS) -#define IDP_MEDIAQ_PHYS (PXA_CS3_PHYS) -#define IDP_IDE_PHYS (PXA_CS5_PHYS + 0x03000000) -#define IDP_ETH_PHYS (PXA_CS5_PHYS + 0x03400000) -#define IDP_COREVOLT_PHYS (PXA_CS5_PHYS + 0x03800000) -#define IDP_CPLD_PHYS (PXA_CS5_PHYS + 0x03C00000) - - -/* - * virtual memory map - */ - -#define IDP_COREVOLT_VIRT (0xf0000000) -#define IDP_COREVOLT_SIZE (1*1024*1024) - -#define IDP_CPLD_VIRT (IDP_COREVOLT_VIRT + IDP_COREVOLT_SIZE) -#define IDP_CPLD_SIZE (1*1024*1024) - -#if (IDP_CPLD_VIRT + IDP_CPLD_SIZE) > 0xfc000000 -#error Your custom IO space is getting a bit large !! -#endif - -#define CPLD_P2V(x) ((x) - IDP_CPLD_PHYS + IDP_CPLD_VIRT) -#define CPLD_V2P(x) ((x) - IDP_CPLD_VIRT + IDP_CPLD_PHYS) - -#ifndef __ASSEMBLY__ -# define __CPLD_REG(x) (*((volatile unsigned long *)CPLD_P2V(x))) -#else -# define __CPLD_REG(x) CPLD_P2V(x) -#endif - -/* board level registers in the CPLD: (offsets from CPLD_VIRT) */ - -#define _IDP_CPLD_REV (IDP_CPLD_PHYS + 0x00) -#define _IDP_CPLD_PERIPH_PWR (IDP_CPLD_PHYS + 0x04) -#define _IDP_CPLD_LED_CONTROL (IDP_CPLD_PHYS + 0x08) -#define _IDP_CPLD_KB_COL_HIGH (IDP_CPLD_PHYS + 0x0C) -#define _IDP_CPLD_KB_COL_LOW (IDP_CPLD_PHYS + 0x10) -#define _IDP_CPLD_PCCARD_EN (IDP_CPLD_PHYS + 0x14) -#define _IDP_CPLD_GPIOH_DIR (IDP_CPLD_PHYS + 0x18) -#define _IDP_CPLD_GPIOH_VALUE (IDP_CPLD_PHYS + 0x1C) -#define _IDP_CPLD_GPIOL_DIR (IDP_CPLD_PHYS + 0x20) -#define _IDP_CPLD_GPIOL_VALUE (IDP_CPLD_PHYS + 0x24) -#define _IDP_CPLD_PCCARD_PWR (IDP_CPLD_PHYS + 0x28) -#define _IDP_CPLD_MISC_CTRL (IDP_CPLD_PHYS + 0x2C) -#define _IDP_CPLD_LCD (IDP_CPLD_PHYS + 0x30) -#define _IDP_CPLD_FLASH_WE (IDP_CPLD_PHYS + 0x34) - -#define _IDP_CPLD_KB_ROW (IDP_CPLD_PHYS + 0x50) -#define _IDP_CPLD_PCCARD0_STATUS (IDP_CPLD_PHYS + 0x54) -#define _IDP_CPLD_PCCARD1_STATUS (IDP_CPLD_PHYS + 0x58) -#define _IDP_CPLD_MISC_STATUS (IDP_CPLD_PHYS + 0x5C) - -/* FPGA register virtual addresses */ - -#define IDP_CPLD_REV __CPLD_REG(_IDP_CPLD_REV) -#define IDP_CPLD_PERIPH_PWR __CPLD_REG(_IDP_CPLD_PERIPH_PWR) -#define IDP_CPLD_LED_CONTROL __CPLD_REG(_IDP_CPLD_LED_CONTROL) -#define IDP_CPLD_KB_COL_HIGH __CPLD_REG(_IDP_CPLD_KB_COL_HIGH) -#define IDP_CPLD_KB_COL_LOW __CPLD_REG(_IDP_CPLD_KB_COL_LOW) -#define IDP_CPLD_PCCARD_EN __CPLD_REG(_IDP_CPLD_PCCARD_EN) -#define IDP_CPLD_GPIOH_DIR __CPLD_REG(_IDP_CPLD_GPIOH_DIR) -#define IDP_CPLD_GPIOH_VALUE __CPLD_REG(_IDP_CPLD_GPIOH_VALUE) -#define IDP_CPLD_GPIOL_DIR __CPLD_REG(_IDP_CPLD_GPIOL_DIR) -#define IDP_CPLD_GPIOL_VALUE __CPLD_REG(_IDP_CPLD_GPIOL_VALUE) -#define IDP_CPLD_PCCARD_PWR __CPLD_REG(_IDP_CPLD_PCCARD_PWR) -#define IDP_CPLD_MISC_CTRL __CPLD_REG(_IDP_CPLD_MISC_CTRL) -#define IDP_CPLD_LCD __CPLD_REG(_IDP_CPLD_LCD) -#define IDP_CPLD_FLASH_WE __CPLD_REG(_IDP_CPLD_FLASH_WE) - -#define IDP_CPLD_KB_ROW __CPLD_REG(_IDP_CPLD_KB_ROW) -#define IDP_CPLD_PCCARD0_STATUS __CPLD_REG(_IDP_CPLD_PCCARD0_STATUS) -#define IDP_CPLD_PCCARD1_STATUS __CPLD_REG(_IDP_CPLD_PCCARD1_STATUS) -#define IDP_CPLD_MISC_STATUS __CPLD_REG(_IDP_CPLD_MISC_STATUS) - - -/* - * Bit masks for various registers - */ - -// IDP_CPLD_PCCARD_PWR -#define PCC0_PWR0 (1 << 0) -#define PCC0_PWR1 (1 << 1) -#define PCC0_PWR2 (1 << 2) -#define PCC0_PWR3 (1 << 3) -#define PCC1_PWR0 (1 << 4) -#define PCC1_PWR1 (1 << 5) -#define PCC1_PWR2 (1 << 6) -#define PCC1_PWR3 (1 << 7) - -// IDP_CPLD_PCCARD_EN -#define PCC0_RESET (1 << 6) -#define PCC1_RESET (1 << 7) -#define PCC0_ENABLE (1 << 0) -#define PCC1_ENABLE (1 << 1) - -// IDP_CPLD_PCCARDx_STATUS -#define _PCC_WRPROT (1 << 7) // 7-4 read as low true -#define _PCC_RESET (1 << 6) -#define _PCC_IRQ (1 << 5) -#define _PCC_INPACK (1 << 4) -#define PCC_BVD2 (1 << 3) -#define PCC_BVD1 (1 << 2) -#define PCC_VS2 (1 << 1) -#define PCC_VS1 (1 << 0) - -/* A listing of interrupts used by external hardware devices */ - -#define TOUCH_PANEL_IRQ PXA_GPIO_TO_IRQ(5) -#define IDE_IRQ PXA_GPIO_TO_IRQ(21) - -#define TOUCH_PANEL_IRQ_EDGE IRQ_TYPE_EDGE_FALLING - -#define ETHERNET_IRQ PXA_GPIO_TO_IRQ(4) -#define ETHERNET_IRQ_EDGE IRQ_TYPE_EDGE_RISING - -#define IDE_IRQ_EDGE IRQ_TYPE_EDGE_RISING - -#define PCMCIA_S0_CD_VALID PXA_GPIO_TO_IRQ(7) -#define PCMCIA_S0_CD_VALID_EDGE IRQ_TYPE_EDGE_BOTH - -#define PCMCIA_S1_CD_VALID PXA_GPIO_TO_IRQ(8) -#define PCMCIA_S1_CD_VALID_EDGE IRQ_TYPE_EDGE_BOTH - -#define PCMCIA_S0_RDYINT PXA_GPIO_TO_IRQ(19) -#define PCMCIA_S1_RDYINT PXA_GPIO_TO_IRQ(22) - - -/* - * Macros for LED Driver - */ - -/* leds 0 = ON */ -#define IDP_HB_LED (1<<5) -#define IDP_BUSY_LED (1<<6) - -#define IDP_LEDS_MASK (IDP_HB_LED | IDP_BUSY_LED) - -/* - * macros for MTD driver - */ - -#define FLASH_WRITE_PROTECT_DISABLE() ((IDP_CPLD_FLASH_WE) &= ~(0x1)) -#define FLASH_WRITE_PROTECT_ENABLE() ((IDP_CPLD_FLASH_WE) |= (0x1)) - -/* - * macros for matrix keyboard driver - */ - -#define KEYBD_MATRIX_NUMBER_INPUTS 7 -#define KEYBD_MATRIX_NUMBER_OUTPUTS 14 - -#define KEYBD_MATRIX_INVERT_OUTPUT_LOGIC FALSE -#define KEYBD_MATRIX_INVERT_INPUT_LOGIC FALSE - -#define KEYBD_MATRIX_SETTLING_TIME_US 100 -#define KEYBD_MATRIX_KEYSTATE_DEBOUNCE_CONSTANT 2 - -#define KEYBD_MATRIX_SET_OUTPUTS(outputs) \ -{\ - IDP_CPLD_KB_COL_LOW = outputs;\ - IDP_CPLD_KB_COL_HIGH = outputs >> 7;\ -} - -#define KEYBD_MATRIX_GET_INPUTS(inputs) \ -{\ - inputs = (IDP_CPLD_KB_ROW & 0x7f);\ -} - - diff --git a/arch/arm/mach-pxa/include/mach/littleton.h b/arch/arm/mach-pxa/include/mach/littleton.h deleted file mode 100644 index 8066be54e9f5..000000000000 --- a/arch/arm/mach-pxa/include/mach/littleton.h +++ /dev/null @@ -1,13 +0,0 @@ -#ifndef __ASM_ARCH_LITTLETON_H -#define __ASM_ARCH_LITTLETON_H - -#define LITTLETON_ETH_PHYS 0x30000000 - -#define LITTLETON_GPIO_LCD_CS (17) - -#define EXT0_GPIO_BASE (PXA_NR_BUILTIN_GPIO) -#define EXT0_GPIO(x) (EXT0_GPIO_BASE + (x)) - -#define LITTLETON_NR_IRQS (IRQ_BOARD_START + 8) - -#endif /* __ASM_ARCH_LITTLETON_H */ diff --git a/arch/arm/mach-pxa/include/mach/lpd270.h b/arch/arm/mach-pxa/include/mach/lpd270.h deleted file mode 100644 index 4edc712a2de8..000000000000 --- a/arch/arm/mach-pxa/include/mach/lpd270.h +++ /dev/null @@ -1,43 +0,0 @@ -/* - * arch/arm/mach-pxa/include/mach/lpd270.h - * - * Author: Lennert Buytenhek - * Created: Feb 10, 2006 - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef __ASM_ARCH_LPD270_H -#define __ASM_ARCH_LPD270_H - -#define LPD270_CPLD_PHYS PXA_CS2_PHYS -#define LPD270_CPLD_VIRT IOMEM(0xf0000000) -#define LPD270_CPLD_SIZE 0x00100000 - -#define LPD270_ETH_PHYS (PXA_CS2_PHYS + 0x01000000) - -/* CPLD registers */ -#define LPD270_CPLD_REG(x) (LPD270_CPLD_VIRT + (x)) -#define LPD270_CONTROL LPD270_CPLD_REG(0x00) -#define LPD270_PERIPHERAL0 LPD270_CPLD_REG(0x04) -#define LPD270_PERIPHERAL1 LPD270_CPLD_REG(0x08) -#define LPD270_CPLD_REVISION LPD270_CPLD_REG(0x14) -#define LPD270_EEPROM_SPI_ITF LPD270_CPLD_REG(0x20) -#define LPD270_MODE_PINS LPD270_CPLD_REG(0x24) -#define LPD270_EGPIO LPD270_CPLD_REG(0x30) -#define LPD270_INT_MASK LPD270_CPLD_REG(0x40) -#define LPD270_INT_STATUS LPD270_CPLD_REG(0x50) - -#define LPD270_INT_AC97 (1 << 4) /* AC'97 CODEC IRQ */ -#define LPD270_INT_ETHERNET (1 << 3) /* Ethernet controller IRQ */ -#define LPD270_INT_USBC (1 << 2) /* USB client cable detection IRQ */ - -#define LPD270_IRQ(x) (IRQ_BOARD_START + (x)) -#define LPD270_USBC_IRQ LPD270_IRQ(2) -#define LPD270_ETHERNET_IRQ LPD270_IRQ(3) -#define LPD270_AC97_IRQ LPD270_IRQ(4) -#define LPD270_NR_IRQS (IRQ_BOARD_START + 5) - -#endif diff --git a/arch/arm/mach-pxa/include/mach/mfp-pxa25x.h b/arch/arm/mach-pxa/include/mach/mfp-pxa25x.h deleted file mode 100644 index cafadc33dfd8..000000000000 --- a/arch/arm/mach-pxa/include/mach/mfp-pxa25x.h +++ /dev/null @@ -1,225 +0,0 @@ -#ifndef __ASM_ARCH_MFP_PXA25X_H -#define __ASM_ARCH_MFP_PXA25X_H - -#include - -/* GPIO */ -#define GPIO2_GPIO MFP_CFG_IN(GPIO2, AF0) -#define GPIO3_GPIO MFP_CFG_IN(GPIO3, AF0) -#define GPIO4_GPIO MFP_CFG_IN(GPIO4, AF0) -#define GPIO5_GPIO MFP_CFG_IN(GPIO5, AF0) -#define GPIO6_GPIO MFP_CFG_IN(GPIO6, AF0) -#define GPIO7_GPIO MFP_CFG_IN(GPIO7, AF0) -#define GPIO8_GPIO MFP_CFG_IN(GPIO8, AF0) - -#define GPIO1_RST MFP_CFG_IN(GPIO1, AF1) - -/* Crystal and Clock Signals */ -#define GPIO10_RTCCLK MFP_CFG_OUT(GPIO10, AF1, DRIVE_LOW) -#define GPIO70_RTCCLK MFP_CFG_OUT(GPIO70, AF1, DRIVE_LOW) -#define GPIO7_48MHz MFP_CFG_OUT(GPIO7, AF1, DRIVE_LOW) -#define GPIO11_3_6MHz MFP_CFG_OUT(GPIO11, AF1, DRIVE_LOW) -#define GPIO71_3_6MHz MFP_CFG_OUT(GPIO71, AF1, DRIVE_LOW) -#define GPIO12_32KHz MFP_CFG_OUT(GPIO12, AF1, DRIVE_LOW) -#define GPIO72_32kHz MFP_CFG_OUT(GPIO72, AF1, DRIVE_LOW) - -/* SDRAM and Static Memory I/O Signals */ -#define GPIO15_nCS_1 MFP_CFG_OUT(GPIO15, AF2, DRIVE_HIGH) -#define GPIO78_nCS_2 MFP_CFG_OUT(GPIO78, AF2, DRIVE_HIGH) -#define GPIO79_nCS_3 MFP_CFG_OUT(GPIO79, AF2, DRIVE_HIGH) -#define GPIO80_nCS_4 MFP_CFG_OUT(GPIO80, AF2, DRIVE_HIGH) -#define GPIO33_nCS_5 MFP_CFG_OUT(GPIO33, AF2, DRIVE_HIGH) - -/* Miscellaneous I/O and DMA Signals */ -#define GPIO18_RDY MFP_CFG_IN(GPIO18, AF1) -#define GPIO20_DREQ_0 MFP_CFG_IN(GPIO20, AF1) -#define GPIO19_DREQ_1 MFP_CFG_IN(GPIO19, AF1) - -/* Alternate Bus Master Mode I/O Signals */ -#define GPIO13_MBGNT MFP_CFG_OUT(GPIO13, AF2, DRIVE_LOW) -#define GPIO73_MBGNT MFP_CFG_OUT(GPIO73, AF1, DRIVE_LOW) -#define GPIO14_MBREQ MFP_CFG_IN(GPIO14, AF1) -#define GPIO66_MBREQ MFP_CFG_IN(GPIO66, AF1) - -/* PC CARD */ -#define GPIO52_nPCE_1 MFP_CFG_OUT(GPIO52, AF2, DRIVE_HIGH) -#define GPIO53_nPCE_2 MFP_CFG_OUT(GPIO53, AF2, DRIVE_HIGH) -#define GPIO55_nPREG MFP_CFG_OUT(GPIO55, AF2, DRIVE_HIGH) -#define GPIO50_nPIOR MFP_CFG_OUT(GPIO50, AF2, DRIVE_HIGH) -#define GPIO51_nPIOW MFP_CFG_OUT(GPIO51, AF2, DRIVE_HIGH) -#define GPIO49_nPWE MFP_CFG_OUT(GPIO49, AF2, DRIVE_HIGH) -#define GPIO48_nPOE MFP_CFG_OUT(GPIO48, AF2, DRIVE_HIGH) -#define GPIO57_nIOIS16 MFP_CFG_IN(GPIO57, AF1) -#define GPIO56_nPWAIT MFP_CFG_IN(GPIO56, AF1) -#define GPIO54_nPSKTSEL MFP_CFG_OUT(GPIO54, AF2, DRIVE_HIGH) - -/* FFUART */ -#define GPIO34_FFUART_RXD MFP_CFG_IN(GPIO34, AF1) -#define GPIO35_FFUART_CTS MFP_CFG_IN(GPIO35, AF1) -#define GPIO36_FFUART_DCD MFP_CFG_IN(GPIO36, AF1) -#define GPIO37_FFUART_DSR MFP_CFG_IN(GPIO37, AF1) -#define GPIO38_FFUART_RI MFP_CFG_IN(GPIO38, AF1) -#define GPIO39_FFUART_TXD MFP_CFG_OUT(GPIO39, AF2, DRIVE_HIGH) -#define GPIO40_FFUART_DTR MFP_CFG_OUT(GPIO40, AF2, DRIVE_HIGH) -#define GPIO41_FFUART_RTS MFP_CFG_OUT(GPIO41, AF2, DRIVE_HIGH) - -/* BTUART */ -#define GPIO42_BTUART_RXD MFP_CFG_IN(GPIO42, AF1) -#define GPIO43_BTUART_TXD MFP_CFG_OUT(GPIO43, AF2, DRIVE_HIGH) -#define GPIO44_BTUART_CTS MFP_CFG_IN(GPIO44, AF1) -#define GPIO45_BTUART_RTS MFP_CFG_OUT(GPIO45, AF2, DRIVE_HIGH) - -/* STUART */ -#define GPIO46_STUART_RXD MFP_CFG_IN(GPIO46, AF2) -#define GPIO47_STUART_TXD MFP_CFG_OUT(GPIO47, AF1, DRIVE_HIGH) - -/* HWUART */ -#define GPIO42_HWUART_RXD MFP_CFG_IN(GPIO42, AF3) -#define GPIO43_HWUART_TXD MFP_CFG_OUT(GPIO43, AF3, DRIVE_HIGH) -#define GPIO44_HWUART_CTS MFP_CFG_IN(GPIO44, AF3) -#define GPIO45_HWUART_RTS MFP_CFG_OUT(GPIO45, AF3, DRIVE_HIGH) -#define GPIO48_HWUART_TXD MFP_CFG_OUT(GPIO48, AF1, DRIVE_HIGH) -#define GPIO49_HWUART_RXD MFP_CFG_IN(GPIO49, AF1) -#define GPIO50_HWUART_CTS MFP_CFG_IN(GPIO50, AF1) -#define GPIO51_HWUART_RTS MFP_CFG_OUT(GPIO51, AF1, DRIVE_HIGH) - -/* FICP */ -#define GPIO46_FICP_RXD MFP_CFG_IN(GPIO46, AF1) -#define GPIO47_FICP_TXD MFP_CFG_OUT(GPIO47, AF2, DRIVE_HIGH) - -/* PWM 0/1 */ -#define GPIO16_PWM0_OUT MFP_CFG_OUT(GPIO16, AF2, DRIVE_LOW) -#define GPIO17_PWM1_OUT MFP_CFG_OUT(GPIO17, AF2, DRIVE_LOW) - -/* AC97 */ -#define GPIO28_AC97_BITCLK MFP_CFG_IN(GPIO28, AF1) -#define GPIO29_AC97_SDATA_IN_0 MFP_CFG_IN(GPIO29, AF1) -#define GPIO30_AC97_SDATA_OUT MFP_CFG_OUT(GPIO30, AF2, DRIVE_LOW) -#define GPIO31_AC97_SYNC MFP_CFG_OUT(GPIO31, AF2, DRIVE_LOW) -#define GPIO32_AC97_SDATA_IN_1 MFP_CFG_IN(GPIO32, AF1) - -/* I2S */ -#define GPIO28_I2S_BITCLK_IN MFP_CFG_IN(GPIO28, AF2) -#define GPIO28_I2S_BITCLK_OUT MFP_CFG_OUT(GPIO28, AF1, DRIVE_LOW) -#define GPIO29_I2S_SDATA_IN MFP_CFG_IN(GPIO29, AF2) -#define GPIO30_I2S_SDATA_OUT MFP_CFG_OUT(GPIO30, AF1, DRIVE_LOW) -#define GPIO31_I2S_SYNC MFP_CFG_OUT(GPIO31, AF1, DRIVE_LOW) -#define GPIO32_I2S_SYSCLK MFP_CFG_OUT(GPIO32, AF1, DRIVE_LOW) - -/* SSP 1 */ -#define GPIO23_SSP1_SCLK MFP_CFG_OUT(GPIO23, AF2, DRIVE_LOW) -#define GPIO24_SSP1_SFRM MFP_CFG_OUT(GPIO24, AF2, DRIVE_LOW) -#define GPIO25_SSP1_TXD MFP_CFG_OUT(GPIO25, AF2, DRIVE_LOW) -#define GPIO26_SSP1_RXD MFP_CFG_IN(GPIO26, AF1) -#define GPIO27_SSP1_EXTCLK MFP_CFG_IN(GPIO27, AF1) - -/* SSP 2 - NSSP */ -#define GPIO81_SSP2_CLK_OUT MFP_CFG_OUT(GPIO81, AF1, DRIVE_LOW) -#define GPIO81_SSP2_CLK_IN MFP_CFG_IN(GPIO81, AF1) -#define GPIO82_SSP2_FRM_OUT MFP_CFG_OUT(GPIO82, AF1, DRIVE_LOW) -#define GPIO82_SSP2_FRM_IN MFP_CFG_IN(GPIO82, AF1) -#define GPIO83_SSP2_TXD MFP_CFG_OUT(GPIO83, AF1, DRIVE_LOW) -#define GPIO83_SSP2_RXD MFP_CFG_IN(GPIO83, AF2) -#define GPIO84_SSP2_TXD MFP_CFG_OUT(GPIO84, AF1, DRIVE_LOW) -#define GPIO84_SSP2_RXD MFP_CFG_IN(GPIO84, AF2) - -/* MMC */ -#define GPIO6_MMC_CLK MFP_CFG_OUT(GPIO6, AF1, DRIVE_LOW) -#define GPIO8_MMC_CS0 MFP_CFG_OUT(GPIO8, AF1, DRIVE_LOW) -#define GPIO9_MMC_CS1 MFP_CFG_OUT(GPIO9, AF1, DRIVE_LOW) -#define GPIO34_MMC_CS0 MFP_CFG_OUT(GPIO34, AF2, DRIVE_LOW) -#define GPIO39_MMC_CS1 MFP_CFG_OUT(GPIO39, AF1, DRIVE_LOW) -#define GPIO53_MMC_CLK MFP_CFG_OUT(GPIO53, AF1, DRIVE_LOW) -#define GPIO54_MMC_CLK MFP_CFG_OUT(GPIO54, AF1, DRIVE_LOW) -#define GPIO69_MMC_CLK MFP_CFG_OUT(GPIO69, AF1, DRIVE_LOW) -#define GPIO67_MMC_CS0 MFP_CFG_OUT(GPIO67, AF1, DRIVE_LOW) -#define GPIO68_MMC_CS1 MFP_CFG_OUT(GPIO68, AF1, DRIVE_LOW) - -/* LCD */ -#define GPIO58_LCD_LDD_0 MFP_CFG_OUT(GPIO58, AF2, DRIVE_LOW) -#define GPIO59_LCD_LDD_1 MFP_CFG_OUT(GPIO59, AF2, DRIVE_LOW) -#define GPIO60_LCD_LDD_2 MFP_CFG_OUT(GPIO60, AF2, DRIVE_LOW) -#define GPIO61_LCD_LDD_3 MFP_CFG_OUT(GPIO61, AF2, DRIVE_LOW) -#define GPIO62_LCD_LDD_4 MFP_CFG_OUT(GPIO62, AF2, DRIVE_LOW) -#define GPIO63_LCD_LDD_5 MFP_CFG_OUT(GPIO63, AF2, DRIVE_LOW) -#define GPIO64_LCD_LDD_6 MFP_CFG_OUT(GPIO64, AF2, DRIVE_LOW) -#define GPIO65_LCD_LDD_7 MFP_CFG_OUT(GPIO65, AF2, DRIVE_LOW) -#define GPIO66_LCD_LDD_8 MFP_CFG_OUT(GPIO66, AF2, DRIVE_LOW) -#define GPIO67_LCD_LDD_9 MFP_CFG_OUT(GPIO67, AF2, DRIVE_LOW) -#define GPIO68_LCD_LDD_10 MFP_CFG_OUT(GPIO68, AF2, DRIVE_LOW) -#define GPIO69_LCD_LDD_11 MFP_CFG_OUT(GPIO69, AF2, DRIVE_LOW) -#define GPIO70_LCD_LDD_12 MFP_CFG_OUT(GPIO70, AF2, DRIVE_LOW) -#define GPIO71_LCD_LDD_13 MFP_CFG_OUT(GPIO71, AF2, DRIVE_LOW) -#define GPIO72_LCD_LDD_14 MFP_CFG_OUT(GPIO72, AF2, DRIVE_LOW) -#define GPIO73_LCD_LDD_15 MFP_CFG_OUT(GPIO73, AF2, DRIVE_LOW) -#define GPIO74_LCD_FCLK MFP_CFG_OUT(GPIO74, AF2, DRIVE_LOW) -#define GPIO75_LCD_LCLK MFP_CFG_OUT(GPIO75, AF2, DRIVE_LOW) -#define GPIO76_LCD_PCLK MFP_CFG_OUT(GPIO76, AF2, DRIVE_LOW) -#define GPIO77_LCD_BIAS MFP_CFG_OUT(GPIO77, AF2, DRIVE_LOW) - -#ifdef CONFIG_CPU_PXA26x -/* GPIO */ -#define GPIO85_GPIO MFP_CFG_IN(GPIO85, AF0) -#define GPIO86_GPIO MFP_CFG_IN(GPIO86, AF1) -#define GPIO87_GPIO MFP_CFG_IN(GPIO87, AF1) -#define GPIO88_GPIO MFP_CFG_IN(GPIO88, AF1) -#define GPIO89_GPIO MFP_CFG_IN(GPIO89, AF1) - -/* SDRAM */ -#define GPIO86_nSDCS2 MFP_CFG_OUT(GPIO86, AF0, DRIVE_HIGH) -#define GPIO87_nSDCS3 MFP_CFG_OUT(GPIO87, AF0, DRIVE_HIGH) -#define GPIO88_RDnWR MFP_CFG_OUT(GPIO88, AF0, DRIVE_HIGH) - -/* USB */ -#define GPIO9_USB_RCV MFP_CFG_IN(GPIO9, AF1) -#define GPIO32_USB_VP MFP_CFG_IN(GPIO32, AF2) -#define GPIO34_USB_VM MFP_CFG_IN(GPIO34, AF2) -#define GPIO39_USB_VPO MFP_CFG_OUT(GPIO39, AF3, DRIVE_LOW) -#define GPIO56_USB_VMO MFP_CFG_OUT(GPIO56, AF1, DRIVE_LOW) -#define GPIO57_USB_nOE MFP_CFG_OUT(GPIO57, AF1, DRIVE_HIGH) - -/* ASSP */ -#define GPIO28_ASSP_BITCLK_IN MFP_CFG_IN(GPIO28, AF3) -#define GPIO28_ASSP_BITCLK_OUT MFP_CFG_OUT(GPIO28, AF3, DRIVE_LOW) -#define GPIO29_ASSP_RXD MFP_CFG_IN(GPIO29, AF3) -#define GPIO30_ASSP_TXD MFP_CFG_OUT(GPIO30, AF3, DRIVE_LOW) -#define GPIO31_ASSP_SFRM_IN MFP_CFG_IN(GPIO31, AF1) -#define GPIO31_ASSP_SFRM_OUT MFP_CFG_OUT(GPIO31, AF3, DRIVE_LOW) - -/* AC97 */ -#define GPIO89_AC97_nRESET MFP_CFG_OUT(GPIO89, AF0, DRIVE_HIGH) -#endif /* CONFIG_CPU_PXA26x */ - -/* commonly used pin configurations */ -#define GPIOxx_LCD_16BPP \ - GPIO58_LCD_LDD_0, \ - GPIO59_LCD_LDD_1, \ - GPIO60_LCD_LDD_2, \ - GPIO61_LCD_LDD_3, \ - GPIO62_LCD_LDD_4, \ - GPIO63_LCD_LDD_5, \ - GPIO64_LCD_LDD_6, \ - GPIO65_LCD_LDD_7, \ - GPIO66_LCD_LDD_8, \ - GPIO67_LCD_LDD_9, \ - GPIO68_LCD_LDD_10, \ - GPIO69_LCD_LDD_11, \ - GPIO70_LCD_LDD_12, \ - GPIO71_LCD_LDD_13, \ - GPIO72_LCD_LDD_14, \ - GPIO73_LCD_LDD_15 - -#define GPIOxx_LCD_DSTN_16BPP \ - GPIOxx_LCD_16BPP, \ - GPIO74_LCD_FCLK, \ - GPIO75_LCD_LCLK, \ - GPIO76_LCD_PCLK - -#define GPIOxx_LCD_TFT_16BPP \ - GPIOxx_LCD_16BPP, \ - GPIO74_LCD_FCLK, \ - GPIO75_LCD_LCLK, \ - GPIO76_LCD_PCLK, \ - GPIO77_LCD_BIAS - -#endif /* __ASM_ARCH_MFP_PXA25X_H */ diff --git a/arch/arm/mach-pxa/include/mach/mfp-pxa27x.h b/arch/arm/mach-pxa/include/mach/mfp-pxa27x.h deleted file mode 100644 index b6132aa95dc0..000000000000 --- a/arch/arm/mach-pxa/include/mach/mfp-pxa27x.h +++ /dev/null @@ -1,471 +0,0 @@ -#ifndef __ASM_ARCH_MFP_PXA27X_H -#define __ASM_ARCH_MFP_PXA27X_H - -/* - * NOTE: for those special-function bidirectional GPIOs, as described - * in the "PXA27x Developer's Manual" Section 24.4.2.1, only its input - * alternative is preserved, the direction is actually selected by the - * specific controller, and this should work in most cases. - */ - -#include - -/* Note: GPIO3/GPIO4 will be driven by Power I2C when PCFR/PI2C_EN - * bit is set, regardless of the GPIO configuration - */ -#define GPIO3_GPIO MFP_CFG_IN(GPIO3, AF0) -#define GPIO4_GPIO MFP_CFG_IN(GPIO4, AF0) - -/* GPIO */ -#define GPIO85_GPIO MFP_CFG_IN(GPIO85, AF0) -#define GPIO86_GPIO MFP_CFG_IN(GPIO86, AF0) -#define GPIO87_GPIO MFP_CFG_IN(GPIO87, AF0) -#define GPIO88_GPIO MFP_CFG_IN(GPIO88, AF0) -#define GPIO89_GPIO MFP_CFG_IN(GPIO89, AF0) -#define GPIO90_GPIO MFP_CFG_IN(GPIO90, AF0) -#define GPIO91_GPIO MFP_CFG_IN(GPIO91, AF0) -#define GPIO92_GPIO MFP_CFG_IN(GPIO92, AF0) -#define GPIO93_GPIO MFP_CFG_IN(GPIO93, AF0) -#define GPIO94_GPIO MFP_CFG_IN(GPIO94, AF0) -#define GPIO95_GPIO MFP_CFG_IN(GPIO95, AF0) -#define GPIO96_GPIO MFP_CFG_IN(GPIO96, AF0) -#define GPIO97_GPIO MFP_CFG_IN(GPIO97, AF0) -#define GPIO98_GPIO MFP_CFG_IN(GPIO98, AF0) -#define GPIO99_GPIO MFP_CFG_IN(GPIO99, AF0) -#define GPIO100_GPIO MFP_CFG_IN(GPIO100, AF0) -#define GPIO101_GPIO MFP_CFG_IN(GPIO101, AF0) -#define GPIO102_GPIO MFP_CFG_IN(GPIO102, AF0) -#define GPIO103_GPIO MFP_CFG_IN(GPIO103, AF0) -#define GPIO104_GPIO MFP_CFG_IN(GPIO104, AF0) -#define GPIO105_GPIO MFP_CFG_IN(GPIO105, AF0) -#define GPIO106_GPIO MFP_CFG_IN(GPIO106, AF0) -#define GPIO107_GPIO MFP_CFG_IN(GPIO107, AF0) -#define GPIO108_GPIO MFP_CFG_IN(GPIO108, AF0) -#define GPIO109_GPIO MFP_CFG_IN(GPIO109, AF0) -#define GPIO110_GPIO MFP_CFG_IN(GPIO110, AF0) -#define GPIO111_GPIO MFP_CFG_IN(GPIO111, AF0) -#define GPIO112_GPIO MFP_CFG_IN(GPIO112, AF0) -#define GPIO113_GPIO MFP_CFG_IN(GPIO113, AF0) -#define GPIO114_GPIO MFP_CFG_IN(GPIO114, AF0) -#define GPIO115_GPIO MFP_CFG_IN(GPIO115, AF0) -#define GPIO116_GPIO MFP_CFG_IN(GPIO116, AF0) -#define GPIO117_GPIO MFP_CFG_IN(GPIO117, AF0) -#define GPIO118_GPIO MFP_CFG_IN(GPIO118, AF0) -#define GPIO119_GPIO MFP_CFG_IN(GPIO119, AF0) -#define GPIO120_GPIO MFP_CFG_IN(GPIO120, AF0) - -/* Crystal and Clock Signals */ -#define GPIO9_HZ_CLK MFP_CFG_OUT(GPIO9, AF1, DRIVE_LOW) -#define GPIO10_HZ_CLK MFP_CFG_OUT(GPIO10, AF1, DRIVE_LOW) -#define GPIO11_48_MHz MFP_CFG_OUT(GPIO11, AF3, DRIVE_LOW) -#define GPIO12_48_MHz MFP_CFG_OUT(GPIO12, AF3, DRIVE_LOW) -#define GPIO13_CLK_EXT MFP_CFG_IN(GPIO13, AF1) - -/* OS Timer Signals */ -#define GPIO11_EXT_SYNC_0 MFP_CFG_IN(GPIO11, AF1) -#define GPIO12_EXT_SYNC_1 MFP_CFG_IN(GPIO12, AF1) -#define GPIO9_CHOUT_0 MFP_CFG_OUT(GPIO9, AF3, DRIVE_LOW) -#define GPIO10_CHOUT_1 MFP_CFG_OUT(GPIO10, AF3, DRIVE_LOW) -#define GPIO11_CHOUT_0 MFP_CFG_OUT(GPIO11, AF1, DRIVE_LOW) -#define GPIO12_CHOUT_1 MFP_CFG_OUT(GPIO12, AF1, DRIVE_LOW) - -/* SDRAM and Static Memory I/O Signals */ -#define GPIO20_nSDCS_2 MFP_CFG_OUT(GPIO20, AF1, DRIVE_HIGH) -#define GPIO21_nSDCS_3 MFP_CFG_OUT(GPIO21, AF1, DRIVE_HIGH) -#define GPIO15_nCS_1 MFP_CFG_OUT(GPIO15, AF2, DRIVE_HIGH) -#define GPIO78_nCS_2 MFP_CFG_OUT(GPIO78, AF2, DRIVE_HIGH) -#define GPIO79_nCS_3 MFP_CFG_OUT(GPIO79, AF2, DRIVE_HIGH) -#define GPIO80_nCS_4 MFP_CFG_OUT(GPIO80, AF2, DRIVE_HIGH) -#define GPIO33_nCS_5 MFP_CFG_OUT(GPIO33, AF2, DRIVE_HIGH) - -/* Miscellaneous I/O and DMA Signals */ -#define GPIO21_DVAL_0 MFP_CFG_OUT(GPIO21, AF2, DRIVE_HIGH) -#define GPIO116_DVAL_0 MFP_CFG_OUT(GPIO116, AF1, DRIVE_HIGH) -#define GPIO33_DVAL_1 MFP_CFG_OUT(GPIO33, AF1, DRIVE_HIGH) -#define GPIO96_DVAL_1 MFP_CFG_OUT(GPIO96, AF2, DRIVE_HIGH) -#define GPIO18_RDY MFP_CFG_IN(GPIO18, AF1) -#define GPIO20_DREQ_0 MFP_CFG_IN(GPIO20, AF1) -#define GPIO115_DREQ_0 MFP_CFG_IN(GPIO115, AF1) -#define GPIO80_DREQ_1 MFP_CFG_IN(GPIO80, AF1) -#define GPIO97_DREQ_1 MFP_CFG_IN(GPIO97, AF2) -#define GPIO85_DREQ_2 MFP_CFG_IN(GPIO85, AF2) -#define GPIO100_DREQ_2 MFP_CFG_IN(GPIO100, AF2) - -/* Alternate Bus Master Mode I/O Signals */ -#define GPIO20_MBREQ MFP_CFG_IN(GPIO20, AF2) -#define GPIO80_MBREQ MFP_CFG_IN(GPIO80, AF2) -#define GPIO96_MBREQ MFP_CFG_IN(GPIO96, AF2) -#define GPIO115_MBREQ MFP_CFG_IN(GPIO115, AF3) -#define GPIO21_MBGNT MFP_CFG_OUT(GPIO21, AF3, DRIVE_LOW) -#define GPIO33_MBGNT MFP_CFG_OUT(GPIO33, AF3, DRIVE_LOW) -#define GPIO97_MBGNT MFP_CFG_OUT(GPIO97, AF2, DRIVE_LOW) -#define GPIO116_MBGNT MFP_CFG_OUT(GPIO116, AF3, DRIVE_LOW) - -/* PC CARD */ -#define GPIO15_nPCE_1 MFP_CFG_OUT(GPIO15, AF1, DRIVE_HIGH) -#define GPIO85_nPCE_1 MFP_CFG_OUT(GPIO85, AF1, DRIVE_HIGH) -#define GPIO86_nPCE_1 MFP_CFG_OUT(GPIO86, AF1, DRIVE_HIGH) -#define GPIO102_nPCE_1 MFP_CFG_OUT(GPIO102, AF1, DRIVE_HIGH) -#define GPIO54_nPCE_2 MFP_CFG_OUT(GPIO54, AF2, DRIVE_HIGH) -#define GPIO78_nPCE_2 MFP_CFG_OUT(GPIO78, AF1, DRIVE_HIGH) -#define GPIO87_nPCE_2 MFP_CFG_IN(GPIO87, AF1) -#define GPIO55_nPREG MFP_CFG_OUT(GPIO55, AF2, DRIVE_HIGH) -#define GPIO50_nPIOR MFP_CFG_OUT(GPIO50, AF2, DRIVE_HIGH) -#define GPIO51_nPIOW MFP_CFG_OUT(GPIO51, AF2, DRIVE_HIGH) -#define GPIO49_nPWE MFP_CFG_OUT(GPIO49, AF2, DRIVE_HIGH) -#define GPIO48_nPOE MFP_CFG_OUT(GPIO48, AF2, DRIVE_HIGH) -#define GPIO57_nIOIS16 MFP_CFG_IN(GPIO57, AF1) -#define GPIO56_nPWAIT MFP_CFG_IN(GPIO56, AF1) -#define GPIO79_PSKTSEL MFP_CFG_OUT(GPIO79, AF1, DRIVE_HIGH) -#define GPIO104_PSKTSEL MFP_CFG_OUT(GPIO104, AF1, DRIVE_HIGH) - -/* I2C */ -#define GPIO117_I2C_SCL MFP_CFG_IN(GPIO117, AF1) -#define GPIO118_I2C_SDA MFP_CFG_IN(GPIO118, AF1) - -/* FFUART */ -#define GPIO9_FFUART_CTS MFP_CFG_IN(GPIO9, AF3) -#define GPIO26_FFUART_CTS MFP_CFG_IN(GPIO26, AF3) -#define GPIO35_FFUART_CTS MFP_CFG_IN(GPIO35, AF1) -#define GPIO100_FFUART_CTS MFP_CFG_IN(GPIO100, AF3) -#define GPIO10_FFUART_DCD MFP_CFG_IN(GPIO10, AF1) -#define GPIO36_FFUART_DCD MFP_CFG_IN(GPIO36, AF1) -#define GPIO33_FFUART_DSR MFP_CFG_IN(GPIO33, AF2) -#define GPIO37_FFUART_DSR MFP_CFG_IN(GPIO37, AF1) -#define GPIO38_FFUART_RI MFP_CFG_IN(GPIO38, AF1) -#define GPIO89_FFUART_RI MFP_CFG_IN(GPIO89, AF3) -#define GPIO19_FFUART_RXD MFP_CFG_IN(GPIO19, AF3) -#define GPIO33_FFUART_RXD MFP_CFG_IN(GPIO33, AF1) -#define GPIO34_FFUART_RXD MFP_CFG_IN(GPIO34, AF1) -#define GPIO41_FFUART_RXD MFP_CFG_IN(GPIO41, AF1) -#define GPIO53_FFUART_RXD MFP_CFG_IN(GPIO53, AF1) -#define GPIO85_FFUART_RXD MFP_CFG_IN(GPIO85, AF1) -#define GPIO96_FFUART_RXD MFP_CFG_IN(GPIO96, AF3) -#define GPIO102_FFUART_RXD MFP_CFG_IN(GPIO102, AF3) -#define GPIO16_FFUART_TXD MFP_CFG_OUT(GPIO16, AF3, DRIVE_HIGH) -#define GPIO37_FFUART_TXD MFP_CFG_OUT(GPIO37, AF3, DRIVE_HIGH) -#define GPIO39_FFUART_TXD MFP_CFG_OUT(GPIO39, AF2, DRIVE_HIGH) -#define GPIO83_FFUART_TXD MFP_CFG_OUT(GPIO83, AF2, DRIVE_HIGH) -#define GPIO99_FFUART_TXD MFP_CFG_OUT(GPIO99, AF3, DRIVE_HIGH) -#define GPIO27_FFUART_RTS MFP_CFG_OUT(GPIO27, AF3, DRIVE_HIGH) -#define GPIO41_FFUART_RTS MFP_CFG_OUT(GPIO41, AF2, DRIVE_HIGH) -#define GPIO83_FFUART_RTS MFP_CFG_OUT(GPIO83, AF3, DRIVE_HIGH) -#define GPIO98_FFUART_RTS MFP_CFG_OUT(GPIO98, AF3, DRIVE_HIGH) -#define GPIO40_FFUART_DTR MFP_CFG_OUT(GPIO40, AF2, DRIVE_HIGH) -#define GPIO82_FFUART_DTR MFP_CFG_OUT(GPIO82, AF3, DRIVE_HIGH) - -/* BTUART */ -#define GPIO44_BTUART_CTS MFP_CFG_IN(GPIO44, AF1) -#define GPIO42_BTUART_RXD MFP_CFG_IN(GPIO42, AF1) -#define GPIO45_BTUART_RTS MFP_CFG_OUT(GPIO45, AF2, DRIVE_HIGH) -#define GPIO45_BTUART_RTS_LPM_LOW MFP_CFG_OUT(GPIO45, AF2, DRIVE_LOW) -#define GPIO43_BTUART_TXD MFP_CFG_OUT(GPIO43, AF2, DRIVE_HIGH) -#define GPIO43_BTUART_TXD_LPM_LOW MFP_CFG_OUT(GPIO43, AF2, DRIVE_LOW) - -/* STUART */ -#define GPIO46_STUART_RXD MFP_CFG_IN(GPIO46, AF2) -#define GPIO47_STUART_TXD MFP_CFG_OUT(GPIO47, AF1, DRIVE_HIGH) - -/* FICP */ -#define GPIO42_FICP_RXD MFP_CFG_IN(GPIO42, AF2) -#define GPIO46_FICP_RXD MFP_CFG_IN(GPIO46, AF1) -#define GPIO43_FICP_TXD MFP_CFG_OUT(GPIO43, AF1, DRIVE_HIGH) -#define GPIO47_FICP_TXD MFP_CFG_OUT(GPIO47, AF2, DRIVE_HIGH) - -/* PWM 0/1/2/3 */ -#define GPIO11_PWM2_OUT MFP_CFG_OUT(GPIO11, AF2, DRIVE_LOW) -#define GPIO12_PWM3_OUT MFP_CFG_OUT(GPIO12, AF2, DRIVE_LOW) -#define GPIO16_PWM0_OUT MFP_CFG_OUT(GPIO16, AF2, DRIVE_LOW) -#define GPIO17_PWM1_OUT MFP_CFG_OUT(GPIO17, AF2, DRIVE_LOW) -#define GPIO38_PWM1_OUT MFP_CFG_OUT(GPIO38, AF3, DRIVE_LOW) -#define GPIO46_PWM2_OUT MFP_CFG_OUT(GPIO46, AF2, DRIVE_LOW) -#define GPIO47_PWM3_OUT MFP_CFG_OUT(GPIO47, AF3, DRIVE_LOW) -#define GPIO79_PWM2_OUT MFP_CFG_OUT(GPIO79, AF3, DRIVE_LOW) -#define GPIO80_PWM3_OUT MFP_CFG_OUT(GPIO80, AF3, DRIVE_LOW) -#define GPIO115_PWM1_OUT MFP_CFG_OUT(GPIO115, AF3, DRIVE_LOW) - -/* AC97 */ -#define GPIO31_AC97_SYNC MFP_CFG_OUT(GPIO31, AF2, DRIVE_LOW) -#define GPIO94_AC97_SYNC MFP_CFG_OUT(GPIO94, AF1, DRIVE_LOW) -#define GPIO30_AC97_SDATA_OUT MFP_CFG_OUT(GPIO30, AF2, DRIVE_LOW) -#define GPIO93_AC97_SDATA_OUT MFP_CFG_OUT(GPIO93, AF1, DRIVE_LOW) -#define GPIO45_AC97_SYSCLK MFP_CFG_OUT(GPIO45, AF1, DRIVE_LOW) -#define GPIO89_AC97_SYSCLK MFP_CFG_OUT(GPIO89, AF1, DRIVE_LOW) -#define GPIO98_AC97_SYSCLK MFP_CFG_OUT(GPIO98, AF1, DRIVE_LOW) -#define GPIO95_AC97_nRESET MFP_CFG_OUT(GPIO95, AF1, DRIVE_LOW) -#define GPIO113_AC97_nRESET MFP_CFG_OUT(GPIO113, AF2, DRIVE_LOW) -#define GPIO28_AC97_BITCLK MFP_CFG_IN(GPIO28, AF1) -#define GPIO29_AC97_SDATA_IN_0 MFP_CFG_IN(GPIO29, AF1) -#define GPIO116_AC97_SDATA_IN_0 MFP_CFG_IN(GPIO116, AF2) -#define GPIO99_AC97_SDATA_IN_1 MFP_CFG_IN(GPIO99, AF2) - -/* I2S */ -#define GPIO28_I2S_BITCLK_IN MFP_CFG_IN(GPIO28, AF2) -#define GPIO28_I2S_BITCLK_OUT MFP_CFG_OUT(GPIO28, AF1, DRIVE_LOW) -#define GPIO29_I2S_SDATA_IN MFP_CFG_IN(GPIO29, AF2) -#define GPIO30_I2S_SDATA_OUT MFP_CFG_OUT(GPIO30, AF1, DRIVE_LOW) -#define GPIO31_I2S_SYNC MFP_CFG_OUT(GPIO31, AF1, DRIVE_LOW) -#define GPIO113_I2S_SYSCLK MFP_CFG_OUT(GPIO113, AF1, DRIVE_LOW) - -/* SSP 1 */ -#define GPIO23_SSP1_SCLK_IN MFP_CFG_IN(GPIO23, AF2) -#define GPIO23_SSP1_SCLK MFP_CFG_OUT(GPIO23, AF2, DRIVE_LOW) -#define GPIO29_SSP1_SCLK MFP_CFG_IN(GPIO29, AF3) -#define GPIO27_SSP1_SYSCLK MFP_CFG_OUT(GPIO27, AF1, DRIVE_LOW) -#define GPIO53_SSP1_SYSCLK MFP_CFG_OUT(GPIO53, AF3, DRIVE_LOW) -#define GPIO24_SSP1_SFRM MFP_CFG_IN(GPIO24, AF2) -#define GPIO28_SSP1_SFRM MFP_CFG_IN(GPIO28, AF3) -#define GPIO25_SSP1_TXD MFP_CFG_OUT(GPIO25, AF2, DRIVE_LOW) -#define GPIO57_SSP1_TXD MFP_CFG_OUT(GPIO57, AF3, DRIVE_LOW) -#define GPIO26_SSP1_RXD MFP_CFG_IN(GPIO26, AF1) -#define GPIO27_SSP1_SCLKEN MFP_CFG_IN(GPIO27, AF2) - -/* SSP 2 */ -#define GPIO19_SSP2_SCLK MFP_CFG_IN(GPIO19, AF1) -#define GPIO22_SSP2_SCLK MFP_CFG_IN(GPIO22, AF3) -#define GPIO29_SSP2_SCLK MFP_CFG_OUT(GPIO29, AF3, DRIVE_LOW) -#define GPIO36_SSP2_SCLK MFP_CFG_IN(GPIO36, AF2) -#define GPIO50_SSP2_SCLK MFP_CFG_IN(GPIO50, AF3) -#define GPIO22_SSP2_SYSCLK MFP_CFG_OUT(GPIO22, AF2, DRIVE_LOW) -#define GPIO14_SSP2_SFRM MFP_CFG_IN(GPIO14, AF2) -#define GPIO37_SSP2_SFRM MFP_CFG_IN(GPIO37, AF2) -#define GPIO87_SSP2_SFRM MFP_CFG_OUT(GPIO87, AF3, DRIVE_LOW) -#define GPIO88_SSP2_SFRM MFP_CFG_IN(GPIO88, AF3) -#define GPIO13_SSP2_TXD MFP_CFG_OUT(GPIO13, AF1, DRIVE_LOW) -#define GPIO38_SSP2_TXD MFP_CFG_OUT(GPIO38, AF2, DRIVE_LOW) -#define GPIO87_SSP2_TXD MFP_CFG_OUT(GPIO87, AF1, DRIVE_LOW) -#define GPIO89_SSP2_TXD MFP_CFG_OUT(GPIO89, AF3, DRIVE_LOW) -#define GPIO11_SSP2_RXD MFP_CFG_IN(GPIO11, AF2) -#define GPIO29_SSP2_RXD MFP_CFG_OUT(GPIO29, AF1, DRIVE_LOW) -#define GPIO40_SSP2_RXD MFP_CFG_IN(GPIO40, AF1) -#define GPIO86_SSP2_RXD MFP_CFG_IN(GPIO86, AF1) -#define GPIO88_SSP2_RXD MFP_CFG_IN(GPIO88, AF2) -#define GPIO22_SSP2_EXTCLK MFP_CFG_IN(GPIO22, AF1) -#define GPIO27_SSP2_EXTCLK MFP_CFG_IN(GPIO27, AF1) -#define GPIO22_SSP2_SCLKEN MFP_CFG_IN(GPIO22, AF2) -#define GPIO23_SSP2_SCLKEN MFP_CFG_IN(GPIO23, AF2) - -/* SSP 3 */ -#define GPIO34_SSP3_SCLK MFP_CFG_IN(GPIO34, AF3) -#define GPIO40_SSP3_SCLK MFP_CFG_OUT(GPIO40, AF3, DRIVE_LOW) -#define GPIO52_SSP3_SCLK MFP_CFG_IN(GPIO52, AF2) -#define GPIO84_SSP3_SCLK MFP_CFG_IN(GPIO84, AF1) -#define GPIO45_SSP3_SYSCLK MFP_CFG_OUT(GPIO45, AF3, DRIVE_LOW) -#define GPIO35_SSP3_SFRM MFP_CFG_IN(GPIO35, AF3) -#define GPIO39_SSP3_SFRM MFP_CFG_IN(GPIO39, AF3) -#define GPIO83_SSP3_SFRM MFP_CFG_IN(GPIO83, AF1) -#define GPIO35_SSP3_TXD MFP_CFG_OUT(GPIO35, AF3, DRIVE_LOW) -#define GPIO38_SSP3_TXD MFP_CFG_OUT(GPIO38, AF1, DRIVE_LOW) -#define GPIO81_SSP3_TXD MFP_CFG_OUT(GPIO81, AF1, DRIVE_LOW) -#define GPIO41_SSP3_RXD MFP_CFG_IN(GPIO41, AF3) -#define GPIO82_SSP3_RXD MFP_CFG_IN(GPIO82, AF1) -#define GPIO89_SSP3_RXD MFP_CFG_IN(GPIO89, AF1) - -/* MMC */ -#define GPIO32_MMC_CLK MFP_CFG_OUT(GPIO32, AF2, DRIVE_LOW) -#define GPIO92_MMC_DAT_0 MFP_CFG_IN(GPIO92, AF1) -#define GPIO109_MMC_DAT_1 MFP_CFG_IN(GPIO109, AF1) -#define GPIO110_MMC_DAT_2 MFP_CFG_IN(GPIO110, AF1) -#define GPIO111_MMC_DAT_3 MFP_CFG_IN(GPIO111, AF1) -#define GPIO112_MMC_CMD MFP_CFG_IN(GPIO112, AF1) - -/* LCD */ -#define GPIO58_LCD_LDD_0 MFP_CFG_OUT(GPIO58, AF2, DRIVE_LOW) -#define GPIO59_LCD_LDD_1 MFP_CFG_OUT(GPIO59, AF2, DRIVE_LOW) -#define GPIO60_LCD_LDD_2 MFP_CFG_OUT(GPIO60, AF2, DRIVE_LOW) -#define GPIO61_LCD_LDD_3 MFP_CFG_OUT(GPIO61, AF2, DRIVE_LOW) -#define GPIO62_LCD_LDD_4 MFP_CFG_OUT(GPIO62, AF2, DRIVE_LOW) -#define GPIO63_LCD_LDD_5 MFP_CFG_OUT(GPIO63, AF2, DRIVE_LOW) -#define GPIO64_LCD_LDD_6 MFP_CFG_OUT(GPIO64, AF2, DRIVE_LOW) -#define GPIO65_LCD_LDD_7 MFP_CFG_OUT(GPIO65, AF2, DRIVE_LOW) -#define GPIO66_LCD_LDD_8 MFP_CFG_OUT(GPIO66, AF2, DRIVE_LOW) -#define GPIO67_LCD_LDD_9 MFP_CFG_OUT(GPIO67, AF2, DRIVE_LOW) -#define GPIO68_LCD_LDD_10 MFP_CFG_OUT(GPIO68, AF2, DRIVE_LOW) -#define GPIO69_LCD_LDD_11 MFP_CFG_OUT(GPIO69, AF2, DRIVE_LOW) -#define GPIO70_LCD_LDD_12 MFP_CFG_OUT(GPIO70, AF2, DRIVE_LOW) -#define GPIO71_LCD_LDD_13 MFP_CFG_OUT(GPIO71, AF2, DRIVE_LOW) -#define GPIO72_LCD_LDD_14 MFP_CFG_OUT(GPIO72, AF2, DRIVE_LOW) -#define GPIO73_LCD_LDD_15 MFP_CFG_OUT(GPIO73, AF2, DRIVE_LOW) -#define GPIO86_LCD_LDD_16 MFP_CFG_OUT(GPIO86, AF2, DRIVE_LOW) -#define GPIO87_LCD_LDD_17 MFP_CFG_OUT(GPIO87, AF2, DRIVE_LOW) -#define GPIO74_LCD_FCLK MFP_CFG_OUT(GPIO74, AF2, DRIVE_LOW) -#define GPIO75_LCD_LCLK MFP_CFG_OUT(GPIO75, AF2, DRIVE_LOW) -#define GPIO76_LCD_PCLK MFP_CFG_OUT(GPIO76, AF2, DRIVE_LOW) -#define GPIO77_LCD_BIAS MFP_CFG_OUT(GPIO77, AF2, DRIVE_LOW) -#define GPIO14_LCD_VSYNC MFP_CFG_IN(GPIO14, AF1) -#define GPIO19_LCD_CS MFP_CFG_OUT(GPIO19, AF2, DRIVE_LOW) - -/* Keypad */ -#define GPIO93_KP_DKIN_0 MFP_CFG_IN(GPIO93, AF1) -#define GPIO94_KP_DKIN_1 MFP_CFG_IN(GPIO94, AF1) -#define GPIO95_KP_DKIN_2 MFP_CFG_IN(GPIO95, AF1) -#define GPIO96_KP_DKIN_3 MFP_CFG_IN(GPIO96, AF1) -#define GPIO97_KP_DKIN_4 MFP_CFG_IN(GPIO97, AF1) -#define GPIO98_KP_DKIN_5 MFP_CFG_IN(GPIO98, AF1) -#define GPIO99_KP_DKIN_6 MFP_CFG_IN(GPIO99, AF1) -#define GPIO13_KP_KDIN_7 MFP_CFG_IN(GPIO13, AF2) -#define GPIO100_KP_MKIN_0 MFP_CFG_IN(GPIO100, AF1) -#define GPIO101_KP_MKIN_1 MFP_CFG_IN(GPIO101, AF1) -#define GPIO102_KP_MKIN_2 MFP_CFG_IN(GPIO102, AF1) -#define GPIO34_KP_MKIN_3 MFP_CFG_IN(GPIO34, AF2) -#define GPIO37_KP_MKIN_3 MFP_CFG_IN(GPIO37, AF3) -#define GPIO97_KP_MKIN_3 MFP_CFG_IN(GPIO97, AF3) -#define GPIO98_KP_MKIN_4 MFP_CFG_IN(GPIO98, AF3) -#define GPIO38_KP_MKIN_4 MFP_CFG_IN(GPIO38, AF2) -#define GPIO39_KP_MKIN_4 MFP_CFG_IN(GPIO39, AF1) -#define GPIO16_KP_MKIN_5 MFP_CFG_IN(GPIO16, AF1) -#define GPIO90_KP_MKIN_5 MFP_CFG_IN(GPIO90, AF1) -#define GPIO99_KP_MKIN_5 MFP_CFG_IN(GPIO99, AF3) -#define GPIO17_KP_MKIN_6 MFP_CFG_IN(GPIO17, AF1) -#define GPIO91_KP_MKIN_6 MFP_CFG_IN(GPIO91, AF1) -#define GPIO95_KP_MKIN_6 MFP_CFG_IN(GPIO95, AF3) -#define GPIO13_KP_MKIN_7 MFP_CFG_IN(GPIO13, AF3) -#define GPIO36_KP_MKIN_7 MFP_CFG_IN(GPIO36, AF3) -#define GPIO103_KP_MKOUT_0 MFP_CFG_OUT(GPIO103, AF2, DRIVE_HIGH) -#define GPIO104_KP_MKOUT_1 MFP_CFG_OUT(GPIO104, AF2, DRIVE_HIGH) -#define GPIO105_KP_MKOUT_2 MFP_CFG_OUT(GPIO105, AF2, DRIVE_HIGH) -#define GPIO106_KP_MKOUT_3 MFP_CFG_OUT(GPIO106, AF2, DRIVE_HIGH) -#define GPIO107_KP_MKOUT_4 MFP_CFG_OUT(GPIO107, AF2, DRIVE_HIGH) -#define GPIO108_KP_MKOUT_5 MFP_CFG_OUT(GPIO108, AF2, DRIVE_HIGH) -#define GPIO35_KP_MKOUT_6 MFP_CFG_OUT(GPIO35, AF2, DRIVE_HIGH) -#define GPIO22_KP_MKOUT_7 MFP_CFG_OUT(GPIO22, AF1, DRIVE_HIGH) -#define GPIO40_KP_MKOUT_6 MFP_CFG_OUT(GPIO40, AF1, DRIVE_HIGH) -#define GPIO41_KP_MKOUT_7 MFP_CFG_OUT(GPIO41, AF1, DRIVE_HIGH) -#define GPIO96_KP_MKOUT_6 MFP_CFG_OUT(GPIO96, AF3, DRIVE_HIGH) - -/* USB P3 */ -#define GPIO10_USB_P3_5 MFP_CFG_IN(GPIO10, AF3) -#define GPIO11_USB_P3_1 MFP_CFG_IN(GPIO11, AF3) -#define GPIO30_USB_P3_2 MFP_CFG_OUT(GPIO30, AF3, DRIVE_LOW) -#define GPIO31_USB_P3_6 MFP_CFG_OUT(GPIO31, AF3, DRIVE_LOW) -#define GPIO56_USB_P3_4 MFP_CFG_OUT(GPIO56, AF1, DRIVE_LOW) -#define GPIO86_USB_P3_5 MFP_CFG_IN(GPIO86, AF3) -#define GPIO87_USB_P3_1 MFP_CFG_IN(GPIO87, AF3) -#define GPIO90_USB_P3_5 MFP_CFG_IN(GPIO90, AF2) -#define GPIO91_USB_P3_1 MFP_CFG_IN(GPIO91, AF2) -#define GPIO113_USB_P3_3 MFP_CFG_IN(GPIO113, AF3) - -/* USB P2 */ -#define GPIO34_USB_P2_2 MFP_CFG_OUT(GPIO34, AF1, DRIVE_LOW) -#define GPIO35_USB_P2_1 MFP_CFG_IN(GPIO35, AF2) -#define GPIO36_USB_P2_4 MFP_CFG_OUT(GPIO36, AF1, DRIVE_LOW) -#define GPIO37_USB_P2_8 MFP_CFG_OUT(GPIO37, AF1, DRIVE_LOW) -#define GPIO38_USB_P2_3 MFP_CFG_IN(GPIO38, AF3) -#define GPIO39_USB_P2_6 MFP_CFG_OUT(GPIO39, AF1, DRIVE_LOW) -#define GPIO40_USB_P2_5 MFP_CFG_IN(GPIO40, AF3) -#define GPIO41_USB_P2_7 MFP_CFG_IN(GPIO41, AF2) -#define GPIO53_USB_P2_3 MFP_CFG_IN(GPIO53, AF2) - -/* USB Host Port 1/2 */ -#define GPIO88_USBH1_PWR MFP_CFG_IN(GPIO88, AF1) -#define GPIO89_USBH1_PEN MFP_CFG_OUT(GPIO89, AF2, DRIVE_LOW) -#define GPIO119_USBH2_PWR MFP_CFG_IN(GPIO119, AF1) -#define GPIO120_USBH2_PEN MFP_CFG_OUT(GPIO120, AF2, DRIVE_LOW) - -/* QCI - default to Master Mode: CIF_FV/CIF_LV Direction In */ -#define GPIO115_CIF_DD_3 MFP_CFG_IN(GPIO115, AF2) -#define GPIO116_CIF_DD_2 MFP_CFG_IN(GPIO116, AF1) -#define GPIO12_CIF_DD_7 MFP_CFG_IN(GPIO12, AF2) -#define GPIO17_CIF_DD_6 MFP_CFG_IN(GPIO17, AF2) -#define GPIO23_CIF_MCLK MFP_CFG_OUT(GPIO23, AF1, DRIVE_LOW) -#define GPIO24_CIF_FV MFP_CFG_IN(GPIO24, AF1) -#define GPIO25_CIF_LV MFP_CFG_IN(GPIO25, AF1) -#define GPIO26_CIF_PCLK MFP_CFG_IN(GPIO26, AF2) -#define GPIO27_CIF_DD_0 MFP_CFG_IN(GPIO27, AF3) -#define GPIO42_CIF_MCLK MFP_CFG_OUT(GPIO42, AF3, DRIVE_LOW) -#define GPIO43_CIF_FV MFP_CFG_IN(GPIO43, AF3) -#define GPIO44_CIF_LV MFP_CFG_IN(GPIO44, AF3) -#define GPIO45_CIF_PCLK MFP_CFG_IN(GPIO45, AF3) -#define GPIO47_CIF_DD_0 MFP_CFG_IN(GPIO47, AF1) -#define GPIO48_CIF_DD_5 MFP_CFG_IN(GPIO48, AF1) -#define GPIO50_CIF_DD_3 MFP_CFG_IN(GPIO50, AF1) -#define GPIO51_CIF_DD_2 MFP_CFG_IN(GPIO51, AF1) -#define GPIO52_CIF_DD_4 MFP_CFG_IN(GPIO52, AF1) -#define GPIO53_CIF_MCLK MFP_CFG_OUT(GPIO53, AF2, DRIVE_LOW) -#define GPIO54_CIF_PCLK MFP_CFG_IN(GPIO54, AF3) -#define GPIO55_CIF_DD_1 MFP_CFG_IN(GPIO55, AF1) -#define GPIO81_CIF_DD_0 MFP_CFG_IN(GPIO81, AF2) -#define GPIO82_CIF_DD_5 MFP_CFG_IN(GPIO82, AF3) -#define GPIO83_CIF_DD_4 MFP_CFG_IN(GPIO83, AF3) -#define GPIO84_CIF_FV MFP_CFG_IN(GPIO84, AF3) -#define GPIO85_CIF_LV MFP_CFG_IN(GPIO85, AF3) -#define GPIO90_CIF_DD_4 MFP_CFG_IN(GPIO90, AF3) -#define GPIO91_CIF_DD_5 MFP_CFG_IN(GPIO91, AF3) -#define GPIO93_CIF_DD_6 MFP_CFG_IN(GPIO93, AF2) -#define GPIO94_CIF_DD_5 MFP_CFG_IN(GPIO94, AF2) -#define GPIO95_CIF_DD_4 MFP_CFG_IN(GPIO95, AF2) -#define GPIO98_CIF_DD_0 MFP_CFG_IN(GPIO98, AF2) -#define GPIO103_CIF_DD_3 MFP_CFG_IN(GPIO103, AF1) -#define GPIO104_CIF_DD_2 MFP_CFG_IN(GPIO104, AF1) -#define GPIO105_CIF_DD_1 MFP_CFG_IN(GPIO105, AF1) -#define GPIO106_CIF_DD_9 MFP_CFG_IN(GPIO106, AF1) -#define GPIO107_CIF_DD_8 MFP_CFG_IN(GPIO107, AF1) -#define GPIO108_CIF_DD_7 MFP_CFG_IN(GPIO108, AF1) -#define GPIO114_CIF_DD_1 MFP_CFG_IN(GPIO114, AF1) - -/* Universal Subscriber ID Interface */ -#define GPIO114_UVS0 MFP_CFG_OUT(GPIO114, AF2, DRIVE_LOW) -#define GPIO115_nUVS1 MFP_CFG_OUT(GPIO115, AF2, DRIVE_LOW) -#define GPIO116_nUVS2 MFP_CFG_OUT(GPIO116, AF2, DRIVE_LOW) -#define GPIO14_UCLK MFP_CFG_OUT(GPIO14, AF3, DRIVE_LOW) -#define GPIO91_UCLK MFP_CFG_OUT(GPIO91, AF2, DRIVE_LOW) -#define GPIO19_nURST MFP_CFG_OUT(GPIO19, AF3, DRIVE_LOW) -#define GPIO90_nURST MFP_CFG_OUT(GPIO90, AF2, DRIVE_LOW) -#define GPIO116_UDET MFP_CFG_IN(GPIO116, AF3) -#define GPIO114_UEN MFP_CFG_OUT(GPIO114, AF1, DRIVE_LOW) -#define GPIO115_UEN MFP_CFG_OUT(GPIO115, AF1, DRIVE_LOW) - -/* Mobile Scalable Link (MSL) Interface */ -#define GPIO81_BB_OB_DAT_0 MFP_CFG_OUT(GPIO81, AF2, DRIVE_LOW) -#define GPIO48_BB_OB_DAT_1 MFP_CFG_OUT(GPIO48, AF1, DRIVE_LOW) -#define GPIO50_BB_OB_DAT_2 MFP_CFG_OUT(GPIO50, AF1, DRIVE_LOW) -#define GPIO51_BB_OB_DAT_3 MFP_CFG_OUT(GPIO51, AF1, DRIVE_LOW) -#define GPIO52_BB_OB_CLK MFP_CFG_OUT(GPIO52, AF1, DRIVE_LOW) -#define GPIO53_BB_OB_STB MFP_CFG_OUT(GPIO53, AF1, DRIVE_LOW) -#define GPIO54_BB_OB_WAIT MFP_CFG_IN(GPIO54, AF2) -#define GPIO82_BB_IB_DAT_0 MFP_CFG_IN(GPIO82, AF2) -#define GPIO55_BB_IB_DAT_1 MFP_CFG_IN(GPIO55, AF2) -#define GPIO56_BB_IB_DAT_2 MFP_CFG_IN(GPIO56, AF2) -#define GPIO57_BB_IB_DAT_3 MFP_CFG_IN(GPIO57, AF2) -#define GPIO83_BB_IB_CLK MFP_CFG_IN(GPIO83, AF2) -#define GPIO84_BB_IB_STB MFP_CFG_IN(GPIO84, AF2) -#define GPIO85_BB_IB_WAIT MFP_CFG_OUT(GPIO85, AF2, DRIVE_LOW) - -/* Memory Stick Host Controller */ -#define GPIO92_MSBS MFP_CFG_OUT(GPIO92, AF2, DRIVE_LOW) -#define GPIO109_MSSDIO MFP_CFG_IN(GPIO109, AF2) -#define GPIO112_nMSINS MFP_CFG_IN(GPIO112, AF2) -#define GPIO32_MSSCLK MFP_CFG_OUT(GPIO32, AF1, DRIVE_LOW) - -/* commonly used pin configurations */ -#define GPIOxx_LCD_16BPP \ - GPIO58_LCD_LDD_0, \ - GPIO59_LCD_LDD_1, \ - GPIO60_LCD_LDD_2, \ - GPIO61_LCD_LDD_3, \ - GPIO62_LCD_LDD_4, \ - GPIO63_LCD_LDD_5, \ - GPIO64_LCD_LDD_6, \ - GPIO65_LCD_LDD_7, \ - GPIO66_LCD_LDD_8, \ - GPIO67_LCD_LDD_9, \ - GPIO68_LCD_LDD_10, \ - GPIO69_LCD_LDD_11, \ - GPIO70_LCD_LDD_12, \ - GPIO71_LCD_LDD_13, \ - GPIO72_LCD_LDD_14, \ - GPIO73_LCD_LDD_15 - -#define GPIOxx_LCD_TFT_16BPP \ - GPIOxx_LCD_16BPP, \ - GPIO74_LCD_FCLK, \ - GPIO75_LCD_LCLK, \ - GPIO76_LCD_PCLK, \ - GPIO77_LCD_BIAS - -/* these enable a work-around for a hw bug in pxa27x during ac97 warm reset */ -#define GPIO113_AC97_nRESET_GPIO_HIGH MFP_CFG_OUT(GPIO113, AF0, DEFAULT) -#define GPIO95_AC97_nRESET_GPIO_HIGH MFP_CFG_OUT(GPIO95, AF0, DEFAULT) - -extern int keypad_set_wake(unsigned int on); -#endif /* __ASM_ARCH_MFP_PXA27X_H */ diff --git a/arch/arm/mach-pxa/include/mach/mfp-pxa2xx.h b/arch/arm/mach-pxa/include/mach/mfp-pxa2xx.h deleted file mode 100644 index cbf51ae81855..000000000000 --- a/arch/arm/mach-pxa/include/mach/mfp-pxa2xx.h +++ /dev/null @@ -1,142 +0,0 @@ -#ifndef __ASM_ARCH_MFP_PXA2XX_H -#define __ASM_ARCH_MFP_PXA2XX_H - -#include - -/* - * the following MFP_xxx bit definitions in mfp.h are re-used for pxa2xx: - * - * MFP_PIN(x) - * MFP_AFx - * MFP_LPM_DRIVE_{LOW, HIGH} - * MFP_LPM_EDGE_x - * - * other MFP_x bit definitions will be ignored - * - * and adds the below two bits specifically for pxa2xx: - * - * bit 23 - Input/Output (PXA2xx specific) - * bit 24 - Wakeup Enable(PXA2xx specific) - * bit 25 - Keep Output (PXA2xx specific) - */ - -#define MFP_DIR_IN (0x0 << 23) -#define MFP_DIR_OUT (0x1 << 23) -#define MFP_DIR_MASK (0x1 << 23) -#define MFP_DIR(x) (((x) >> 23) & 0x1) - -#define MFP_LPM_CAN_WAKEUP (0x1 << 24) - -/* - * MFP_LPM_KEEP_OUTPUT must be specified for pins that need to - * retain their last output level (low or high). - * Note: MFP_LPM_KEEP_OUTPUT has no effect on pins configured for input. - */ -#define MFP_LPM_KEEP_OUTPUT (0x1 << 25) - -#define WAKEUP_ON_EDGE_RISE (MFP_LPM_CAN_WAKEUP | MFP_LPM_EDGE_RISE) -#define WAKEUP_ON_EDGE_FALL (MFP_LPM_CAN_WAKEUP | MFP_LPM_EDGE_FALL) -#define WAKEUP_ON_EDGE_BOTH (MFP_LPM_CAN_WAKEUP | MFP_LPM_EDGE_BOTH) - -/* specifically for enabling wakeup on keypad GPIOs */ -#define WAKEUP_ON_LEVEL_HIGH (MFP_LPM_CAN_WAKEUP) - -#define MFP_CFG_IN(pin, af) \ - ((MFP_CFG_DEFAULT & ~(MFP_AF_MASK | MFP_DIR_MASK)) |\ - (MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_DIR_IN)) - -/* NOTE: pins configured as output _must_ provide a low power state, - * and this state should help to minimize the power dissipation. - */ -#define MFP_CFG_OUT(pin, af, state) \ - ((MFP_CFG_DEFAULT & ~(MFP_AF_MASK | MFP_DIR_MASK | MFP_LPM_STATE_MASK)) |\ - (MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_DIR_OUT | MFP_LPM_##state)) - -/* Common configurations for pxa25x and pxa27x - * - * Note: pins configured as GPIO are always initialized to input - * so not to cause any side effect - */ -#define GPIO0_GPIO MFP_CFG_IN(GPIO0, AF0) -#define GPIO1_GPIO MFP_CFG_IN(GPIO1, AF0) -#define GPIO9_GPIO MFP_CFG_IN(GPIO9, AF0) -#define GPIO10_GPIO MFP_CFG_IN(GPIO10, AF0) -#define GPIO11_GPIO MFP_CFG_IN(GPIO11, AF0) -#define GPIO12_GPIO MFP_CFG_IN(GPIO12, AF0) -#define GPIO13_GPIO MFP_CFG_IN(GPIO13, AF0) -#define GPIO14_GPIO MFP_CFG_IN(GPIO14, AF0) -#define GPIO15_GPIO MFP_CFG_IN(GPIO15, AF0) -#define GPIO16_GPIO MFP_CFG_IN(GPIO16, AF0) -#define GPIO17_GPIO MFP_CFG_IN(GPIO17, AF0) -#define GPIO18_GPIO MFP_CFG_IN(GPIO18, AF0) -#define GPIO19_GPIO MFP_CFG_IN(GPIO19, AF0) -#define GPIO20_GPIO MFP_CFG_IN(GPIO20, AF0) -#define GPIO21_GPIO MFP_CFG_IN(GPIO21, AF0) -#define GPIO22_GPIO MFP_CFG_IN(GPIO22, AF0) -#define GPIO23_GPIO MFP_CFG_IN(GPIO23, AF0) -#define GPIO24_GPIO MFP_CFG_IN(GPIO24, AF0) -#define GPIO25_GPIO MFP_CFG_IN(GPIO25, AF0) -#define GPIO26_GPIO MFP_CFG_IN(GPIO26, AF0) -#define GPIO27_GPIO MFP_CFG_IN(GPIO27, AF0) -#define GPIO28_GPIO MFP_CFG_IN(GPIO28, AF0) -#define GPIO29_GPIO MFP_CFG_IN(GPIO29, AF0) -#define GPIO30_GPIO MFP_CFG_IN(GPIO30, AF0) -#define GPIO31_GPIO MFP_CFG_IN(GPIO31, AF0) -#define GPIO32_GPIO MFP_CFG_IN(GPIO32, AF0) -#define GPIO33_GPIO MFP_CFG_IN(GPIO33, AF0) -#define GPIO34_GPIO MFP_CFG_IN(GPIO34, AF0) -#define GPIO35_GPIO MFP_CFG_IN(GPIO35, AF0) -#define GPIO36_GPIO MFP_CFG_IN(GPIO36, AF0) -#define GPIO37_GPIO MFP_CFG_IN(GPIO37, AF0) -#define GPIO38_GPIO MFP_CFG_IN(GPIO38, AF0) -#define GPIO39_GPIO MFP_CFG_IN(GPIO39, AF0) -#define GPIO40_GPIO MFP_CFG_IN(GPIO40, AF0) -#define GPIO41_GPIO MFP_CFG_IN(GPIO41, AF0) -#define GPIO42_GPIO MFP_CFG_IN(GPIO42, AF0) -#define GPIO43_GPIO MFP_CFG_IN(GPIO43, AF0) -#define GPIO44_GPIO MFP_CFG_IN(GPIO44, AF0) -#define GPIO45_GPIO MFP_CFG_IN(GPIO45, AF0) -#define GPIO46_GPIO MFP_CFG_IN(GPIO46, AF0) -#define GPIO47_GPIO MFP_CFG_IN(GPIO47, AF0) -#define GPIO48_GPIO MFP_CFG_IN(GPIO48, AF0) -#define GPIO49_GPIO MFP_CFG_IN(GPIO49, AF0) -#define GPIO50_GPIO MFP_CFG_IN(GPIO50, AF0) -#define GPIO51_GPIO MFP_CFG_IN(GPIO51, AF0) -#define GPIO52_GPIO MFP_CFG_IN(GPIO52, AF0) -#define GPIO53_GPIO MFP_CFG_IN(GPIO53, AF0) -#define GPIO54_GPIO MFP_CFG_IN(GPIO54, AF0) -#define GPIO55_GPIO MFP_CFG_IN(GPIO55, AF0) -#define GPIO56_GPIO MFP_CFG_IN(GPIO56, AF0) -#define GPIO57_GPIO MFP_CFG_IN(GPIO57, AF0) -#define GPIO58_GPIO MFP_CFG_IN(GPIO58, AF0) -#define GPIO59_GPIO MFP_CFG_IN(GPIO59, AF0) -#define GPIO60_GPIO MFP_CFG_IN(GPIO60, AF0) -#define GPIO61_GPIO MFP_CFG_IN(GPIO61, AF0) -#define GPIO62_GPIO MFP_CFG_IN(GPIO62, AF0) -#define GPIO63_GPIO MFP_CFG_IN(GPIO63, AF0) -#define GPIO64_GPIO MFP_CFG_IN(GPIO64, AF0) -#define GPIO65_GPIO MFP_CFG_IN(GPIO65, AF0) -#define GPIO66_GPIO MFP_CFG_IN(GPIO66, AF0) -#define GPIO67_GPIO MFP_CFG_IN(GPIO67, AF0) -#define GPIO68_GPIO MFP_CFG_IN(GPIO68, AF0) -#define GPIO69_GPIO MFP_CFG_IN(GPIO69, AF0) -#define GPIO70_GPIO MFP_CFG_IN(GPIO70, AF0) -#define GPIO71_GPIO MFP_CFG_IN(GPIO71, AF0) -#define GPIO72_GPIO MFP_CFG_IN(GPIO72, AF0) -#define GPIO73_GPIO MFP_CFG_IN(GPIO73, AF0) -#define GPIO74_GPIO MFP_CFG_IN(GPIO74, AF0) -#define GPIO75_GPIO MFP_CFG_IN(GPIO75, AF0) -#define GPIO76_GPIO MFP_CFG_IN(GPIO76, AF0) -#define GPIO77_GPIO MFP_CFG_IN(GPIO77, AF0) -#define GPIO78_GPIO MFP_CFG_IN(GPIO78, AF0) -#define GPIO79_GPIO MFP_CFG_IN(GPIO79, AF0) -#define GPIO80_GPIO MFP_CFG_IN(GPIO80, AF0) -#define GPIO81_GPIO MFP_CFG_IN(GPIO81, AF0) -#define GPIO82_GPIO MFP_CFG_IN(GPIO82, AF0) -#define GPIO83_GPIO MFP_CFG_IN(GPIO83, AF0) -#define GPIO84_GPIO MFP_CFG_IN(GPIO84, AF0) - -extern void pxa2xx_mfp_config(unsigned long *mfp_cfgs, int num); -extern void pxa2xx_mfp_set_lpm(int mfp, unsigned long lpm); -extern int gpio_set_wake(unsigned int gpio, unsigned int on); -#endif /* __ASM_ARCH_MFP_PXA2XX_H */ diff --git a/arch/arm/mach-pxa/include/mach/mfp-pxa300.h b/arch/arm/mach-pxa/include/mach/mfp-pxa300.h deleted file mode 100644 index 4e1287070d21..000000000000 --- a/arch/arm/mach-pxa/include/mach/mfp-pxa300.h +++ /dev/null @@ -1,575 +0,0 @@ -/* - * arch/arm/mach-pxa/include/mach/mfp-pxa300.h - * - * PXA300/PXA310 specific MFP configuration definitions - * - * Copyright (C) 2007 Marvell International Ltd. - * 2007-08-21: eric miao - * initial version - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef __ASM_ARCH_MFP_PXA300_H -#define __ASM_ARCH_MFP_PXA300_H - -#include - -/* GPIO */ -#define GPIO46_GPIO MFP_CFG(GPIO46, AF1) -#define GPIO49_GPIO MFP_CFG(GPIO49, AF3) -#define GPIO50_GPIO MFP_CFG(GPIO50, AF2) -#define GPIO51_GPIO MFP_CFG(GPIO51, AF3) -#define GPIO52_GPIO MFP_CFG(GPIO52, AF3) -#define GPIO56_GPIO MFP_CFG(GPIO56, AF0) -#define GPIO58_GPIO MFP_CFG(GPIO58, AF0) -#define GPIO59_GPIO MFP_CFG(GPIO59, AF0) -#define GPIO60_GPIO MFP_CFG(GPIO60, AF0) -#define GPIO61_GPIO MFP_CFG(GPIO61, AF0) -#define GPIO62_GPIO MFP_CFG(GPIO62, AF0) - -#ifdef CONFIG_CPU_PXA310 -#define GPIO7_2_GPIO MFP_CFG(GPIO7_2, AF0) -#define GPIO8_2_GPIO MFP_CFG(GPIO8_2, AF0) -#define GPIO9_2_GPIO MFP_CFG(GPIO9_2, AF0) -#define GPIO10_2_GPIO MFP_CFG(GPIO10_2, AF0) -#define GPIO11_2_GPIO MFP_CFG(GPIO11_2, AF0) -#define GPIO12_2_GPIO MFP_CFG(GPIO12_2, AF0) -#endif - -/* Chip Select */ -#define GPIO1_nCS2 MFP_CFG(GPIO1, AF1) -#define GPIO2_nCS3 MFP_CFG(GPIO2, AF1) - -/* AC97 */ -#define GPIO23_AC97_nACRESET MFP_CFG(GPIO23, AF1) -#define GPIO24_AC97_SYSCLK MFP_CFG(GPIO24, AF1) -#define GPIO29_AC97_BITCLK MFP_CFG(GPIO29, AF1) -#define GPIO25_AC97_SDATA_IN_0 MFP_CFG(GPIO25, AF1) -#define GPIO26_AC97_SDATA_IN_1 MFP_CFG(GPIO26, AF1) -#define GPIO17_AC97_SDATA_IN_2 MFP_CFG(GPIO17, AF3) -#define GPIO21_AC97_SDATA_IN_2 MFP_CFG(GPIO21, AF2) -#define GPIO18_AC97_SDATA_IN_3 MFP_CFG(GPIO18, AF3) -#define GPIO22_AC97_SDATA_IN_3 MFP_CFG(GPIO22, AF2) -#define GPIO27_AC97_SDATA_OUT MFP_CFG(GPIO27, AF1) -#define GPIO28_AC97_SYNC MFP_CFG(GPIO28, AF1) - -/* I2C */ -#define GPIO21_I2C_SCL MFP_CFG_LPM(GPIO21, AF1, PULL_HIGH) -#define GPIO22_I2C_SDA MFP_CFG_LPM(GPIO22, AF1, PULL_HIGH) - -/* QCI */ -#define GPIO39_CI_DD_0 MFP_CFG_DRV(GPIO39, AF1, DS04X) -#define GPIO40_CI_DD_1 MFP_CFG_DRV(GPIO40, AF1, DS04X) -#define GPIO41_CI_DD_2 MFP_CFG_DRV(GPIO41, AF1, DS04X) -#define GPIO42_CI_DD_3 MFP_CFG_DRV(GPIO42, AF1, DS04X) -#define GPIO43_CI_DD_4 MFP_CFG_DRV(GPIO43, AF1, DS04X) -#define GPIO44_CI_DD_5 MFP_CFG_DRV(GPIO44, AF1, DS04X) -#define GPIO45_CI_DD_6 MFP_CFG_DRV(GPIO45, AF1, DS04X) -#define GPIO46_CI_DD_7 MFP_CFG_DRV(GPIO46, AF0, DS04X) -#define GPIO47_CI_DD_8 MFP_CFG_DRV(GPIO47, AF1, DS04X) -#define GPIO48_CI_DD_9 MFP_CFG_DRV(GPIO48, AF1, DS04X) -#define GPIO49_CI_MCLK MFP_CFG_DRV(GPIO49, AF0, DS04X) -#define GPIO50_CI_PCLK MFP_CFG_DRV(GPIO50, AF0, DS04X) -#define GPIO51_CI_HSYNC MFP_CFG_DRV(GPIO51, AF0, DS04X) -#define GPIO52_CI_VSYNC MFP_CFG_DRV(GPIO52, AF0, DS04X) - -/* KEYPAD */ -#define GPIO3_KP_DKIN_6 MFP_CFG_LPM(GPIO3, AF2, FLOAT) -#define GPIO4_KP_DKIN_7 MFP_CFG_LPM(GPIO4, AF2, FLOAT) -#define GPIO16_KP_DKIN_6 MFP_CFG_LPM(GPIO16, AF6, FLOAT) -#define GPIO83_KP_DKIN_2 MFP_CFG_LPM(GPIO83, AF5, FLOAT) -#define GPIO84_KP_DKIN_1 MFP_CFG_LPM(GPIO84, AF5, FLOAT) -#define GPIO85_KP_DKIN_0 MFP_CFG_LPM(GPIO85, AF3, FLOAT) -#define GPIO86_KP_DKIN_1 MFP_CFG_LPM(GPIO86, AF3, FLOAT) -#define GPIO87_KP_DKIN_2 MFP_CFG_LPM(GPIO87, AF3, FLOAT) -#define GPIO88_KP_DKIN_3 MFP_CFG_LPM(GPIO88, AF3, FLOAT) -#define GPIO89_KP_DKIN_3 MFP_CFG_LPM(GPIO89, AF3, FLOAT) -#define GPIO107_KP_DKIN_0 MFP_CFG_LPM(GPIO107, AF2, FLOAT) -#define GPIO108_KP_DKIN_1 MFP_CFG_LPM(GPIO108, AF2, FLOAT) -#define GPIO109_KP_DKIN_2 MFP_CFG_LPM(GPIO109, AF2, FLOAT) -#define GPIO110_KP_DKIN_3 MFP_CFG_LPM(GPIO110, AF2, FLOAT) -#define GPIO111_KP_DKIN_4 MFP_CFG_LPM(GPIO111, AF2, FLOAT) -#define GPIO112_KP_DKIN_5 MFP_CFG_LPM(GPIO112, AF2, FLOAT) -#define GPIO113_KP_DKIN_6 MFP_CFG_LPM(GPIO113, AF2, FLOAT) -#define GPIO114_KP_DKIN_7 MFP_CFG_LPM(GPIO114, AF2, FLOAT) -#define GPIO115_KP_DKIN_0 MFP_CFG_LPM(GPIO115, AF2, FLOAT) -#define GPIO116_KP_DKIN_1 MFP_CFG_LPM(GPIO116, AF2, FLOAT) -#define GPIO117_KP_DKIN_2 MFP_CFG_LPM(GPIO117, AF2, FLOAT) -#define GPIO118_KP_DKIN_3 MFP_CFG_LPM(GPIO118, AF2, FLOAT) -#define GPIO119_KP_DKIN_4 MFP_CFG_LPM(GPIO119, AF2, FLOAT) -#define GPIO120_KP_DKIN_5 MFP_CFG_LPM(GPIO120, AF2, FLOAT) -#define GPIO121_KP_DKIN_6 MFP_CFG_LPM(GPIO121, AF2, FLOAT) -#define GPIO122_KP_DKIN_5 MFP_CFG_LPM(GPIO122, AF2, FLOAT) -#define GPIO123_KP_DKIN_4 MFP_CFG_LPM(GPIO123, AF2, FLOAT) -#define GPIO124_KP_DKIN_3 MFP_CFG_LPM(GPIO124, AF2, FLOAT) -#define GPIO127_KP_DKIN_0 MFP_CFG_LPM(GPIO127, AF5, FLOAT) -#define GPIO0_2_KP_DKIN_0 MFP_CFG_LPM(GPIO0_2, AF2, FLOAT) -#define GPIO1_2_KP_DKIN_1 MFP_CFG_LPM(GPIO1_2, AF2, FLOAT) -#define GPIO2_2_KP_DKIN_6 MFP_CFG_LPM(GPIO2_2, AF2, FLOAT) -#define GPIO3_2_KP_DKIN_7 MFP_CFG_LPM(GPIO3_2, AF2, FLOAT) -#define GPIO4_2_KP_DKIN_1 MFP_CFG_LPM(GPIO4_2, AF2, FLOAT) -#define GPIO5_2_KP_DKIN_0 MFP_CFG_LPM(GPIO5_2, AF2, FLOAT) - -#define GPIO5_KP_MKIN_0 MFP_CFG_LPM(GPIO5, AF2, FLOAT) -#define GPIO6_KP_MKIN_1 MFP_CFG_LPM(GPIO6, AF2, FLOAT) -#define GPIO9_KP_MKIN_6 MFP_CFG_LPM(GPIO9, AF3, FLOAT) -#define GPIO10_KP_MKIN_7 MFP_CFG_LPM(GPIO10, AF3, FLOAT) -#define GPIO70_KP_MKIN_6 MFP_CFG_LPM(GPIO70, AF3, FLOAT) -#define GPIO71_KP_MKIN_7 MFP_CFG_LPM(GPIO71, AF3, FLOAT) -#define GPIO100_KP_MKIN_6 MFP_CFG_LPM(GPIO100, AF7, FLOAT) -#define GPIO101_KP_MKIN_7 MFP_CFG_LPM(GPIO101, AF7, FLOAT) -#define GPIO112_KP_MKIN_6 MFP_CFG_LPM(GPIO112, AF4, FLOAT) -#define GPIO113_KP_MKIN_7 MFP_CFG_LPM(GPIO113, AF4, FLOAT) -#define GPIO115_KP_MKIN_0 MFP_CFG_LPM(GPIO115, AF1, FLOAT) -#define GPIO116_KP_MKIN_1 MFP_CFG_LPM(GPIO116, AF1, FLOAT) -#define GPIO117_KP_MKIN_2 MFP_CFG_LPM(GPIO117, AF1, FLOAT) -#define GPIO118_KP_MKIN_3 MFP_CFG_LPM(GPIO118, AF1, FLOAT) -#define GPIO119_KP_MKIN_4 MFP_CFG_LPM(GPIO119, AF1, FLOAT) -#define GPIO120_KP_MKIN_5 MFP_CFG_LPM(GPIO120, AF1, FLOAT) -#define GPIO125_KP_MKIN_2 MFP_CFG_LPM(GPIO125, AF2, FLOAT) -#define GPIO2_2_KP_MKIN_6 MFP_CFG_LPM(GPIO2_2, AF1, FLOAT) -#define GPIO3_2_KP_MKIN_7 MFP_CFG_LPM(GPIO3_2, AF1, FLOAT) - -#define GPIO7_KP_MKOUT_5 MFP_CFG_LPM(GPIO7, AF1, DRIVE_HIGH) -#define GPIO11_KP_MKOUT_5 MFP_CFG_LPM(GPIO11, AF3, DRIVE_HIGH) -#define GPIO12_KP_MKOUT_6 MFP_CFG_LPM(GPIO12, AF3, DRIVE_HIGH) -#define GPIO13_KP_MKOUT_7 MFP_CFG_LPM(GPIO13, AF3, DRIVE_HIGH) -#define GPIO19_KP_MKOUT_4 MFP_CFG_LPM(GPIO19, AF3, DRIVE_HIGH) -#define GPIO20_KP_MKOUT_5 MFP_CFG_LPM(GPIO20, AF3, DRIVE_HIGH) -#define GPIO38_KP_MKOUT_5 MFP_CFG_LPM(GPIO38, AF5, DRIVE_HIGH) -#define GPIO53_KP_MKOUT_6 MFP_CFG_LPM(GPIO53, AF5, DRIVE_HIGH) -#define GPIO78_KP_MKOUT_7 MFP_CFG_LPM(GPIO78, AF5, DRIVE_HIGH) -#define GPIO85_KP_MKOUT_0 MFP_CFG_LPM(GPIO85, AF2, DRIVE_HIGH) -#define GPIO86_KP_MKOUT_1 MFP_CFG_LPM(GPIO86, AF2, DRIVE_HIGH) -#define GPIO87_KP_MKOUT_2 MFP_CFG_LPM(GPIO87, AF2, DRIVE_HIGH) -#define GPIO88_KP_MKOUT_3 MFP_CFG_LPM(GPIO88, AF2, DRIVE_HIGH) -#define GPIO104_KP_MKOUT_6 MFP_CFG_LPM(GPIO104, AF5, DRIVE_HIGH) -#define GPIO105_KP_MKOUT_7 MFP_CFG_LPM(GPIO105, AF5, DRIVE_HIGH) -#define GPIO121_KP_MKOUT_0 MFP_CFG_LPM(GPIO121, AF1, DRIVE_HIGH) -#define GPIO122_KP_MKOUT_1 MFP_CFG_LPM(GPIO122, AF1, DRIVE_HIGH) -#define GPIO123_KP_MKOUT_2 MFP_CFG_LPM(GPIO123, AF1, DRIVE_HIGH) -#define GPIO124_KP_MKOUT_3 MFP_CFG_LPM(GPIO124, AF1, DRIVE_HIGH) -#define GPIO125_KP_MKOUT_4 MFP_CFG_LPM(GPIO125, AF1, DRIVE_HIGH) -#define GPIO126_KP_MKOUT_7 MFP_CFG_LPM(GPIO126, AF4, DRIVE_HIGH) -#define GPIO5_2_KP_MKOUT_6 MFP_CFG_LPM(GPIO5_2, AF1, DRIVE_HIGH) -#define GPIO4_2_KP_MKOUT_5 MFP_CFG_LPM(GPIO4_2, AF1, DRIVE_HIGH) -#define GPIO6_2_KP_MKOUT_7 MFP_CFG_LPM(GPIO6_2, AF1, DRIVE_HIGH) - -/* LCD */ -#define GPIO54_LCD_LDD_0 MFP_CFG_DRV(GPIO54, AF1, DS01X) -#define GPIO55_LCD_LDD_1 MFP_CFG_DRV(GPIO55, AF1, DS01X) -#define GPIO56_LCD_LDD_2 MFP_CFG_DRV(GPIO56, AF1, DS01X) -#define GPIO57_LCD_LDD_3 MFP_CFG_DRV(GPIO57, AF1, DS01X) -#define GPIO58_LCD_LDD_4 MFP_CFG_DRV(GPIO58, AF1, DS01X) -#define GPIO59_LCD_LDD_5 MFP_CFG_DRV(GPIO59, AF1, DS01X) -#define GPIO60_LCD_LDD_6 MFP_CFG_DRV(GPIO60, AF1, DS01X) -#define GPIO61_LCD_LDD_7 MFP_CFG_DRV(GPIO61, AF1, DS01X) -#define GPIO62_LCD_LDD_8 MFP_CFG_DRV(GPIO62, AF1, DS01X) -#define GPIO63_LCD_LDD_9 MFP_CFG_DRV(GPIO63, AF1, DS01X) -#define GPIO64_LCD_LDD_10 MFP_CFG_DRV(GPIO64, AF1, DS01X) -#define GPIO65_LCD_LDD_11 MFP_CFG_DRV(GPIO65, AF1, DS01X) -#define GPIO66_LCD_LDD_12 MFP_CFG_DRV(GPIO66, AF1, DS01X) -#define GPIO67_LCD_LDD_13 MFP_CFG_DRV(GPIO67, AF1, DS01X) -#define GPIO68_LCD_LDD_14 MFP_CFG_DRV(GPIO68, AF1, DS01X) -#define GPIO69_LCD_LDD_15 MFP_CFG_DRV(GPIO69, AF1, DS01X) -#define GPIO70_LCD_LDD_16 MFP_CFG_DRV(GPIO70, AF1, DS01X) -#define GPIO71_LCD_LDD_17 MFP_CFG_DRV(GPIO71, AF1, DS01X) -#define GPIO62_LCD_CS_N MFP_CFG_DRV(GPIO62, AF2, DS01X) -#define GPIO72_LCD_FCLK MFP_CFG_DRV(GPIO72, AF1, DS01X) -#define GPIO73_LCD_LCLK MFP_CFG_DRV(GPIO73, AF1, DS01X) -#define GPIO74_LCD_PCLK MFP_CFG_DRV(GPIO74, AF1, DS02X) -#define GPIO75_LCD_BIAS MFP_CFG_DRV(GPIO75, AF1, DS01X) -#define GPIO76_LCD_VSYNC MFP_CFG_DRV(GPIO76, AF2, DS01X) - -#define GPIO15_LCD_CS_N MFP_CFG_DRV(GPIO15, AF2, DS01X) -#define GPIO127_LCD_CS_N MFP_CFG_DRV(GPIO127, AF1, DS01X) -#define GPIO63_LCD_VSYNC MFP_CFG_DRV(GPIO63, AF2, DS01X) - -/* Mini-LCD */ -#define GPIO72_MLCD_FCLK MFP_CFG_DRV(GPIO72, AF7, DS08X) -#define GPIO73_MLCD_LCLK MFP_CFG_DRV(GPIO73, AF7, DS08X) -#define GPIO54_MLCD_LDD_0 MFP_CFG_DRV(GPIO54, AF7, DS08X) -#define GPIO55_MLCD_LDD_1 MFP_CFG_DRV(GPIO55, AF7, DS08X) -#define GPIO56_MLCD_LDD_2 MFP_CFG_DRV(GPIO56, AF7, DS08X) -#define GPIO57_MLCD_LDD_3 MFP_CFG_DRV(GPIO57, AF7, DS08X) -#define GPIO58_MLCD_LDD_4 MFP_CFG_DRV(GPIO58, AF7, DS08X) -#define GPIO59_MLCD_LDD_5 MFP_CFG_DRV(GPIO59, AF7, DS08X) -#define GPIO60_MLCD_LDD_6 MFP_CFG_DRV(GPIO60, AF7, DS08X) -#define GPIO61_MLCD_LDD_7 MFP_CFG_DRV(GPIO61, AF7, DS08X) -#define GPIO62_MLCD_LDD_8 MFP_CFG_DRV(GPIO62, AF7, DS08X) -#define GPIO63_MLCD_LDD_9 MFP_CFG_DRV(GPIO63, AF7, DS08X) -#define GPIO64_MLCD_LDD_10 MFP_CFG_DRV(GPIO64, AF7, DS08X) -#define GPIO65_MLCD_LDD_11 MFP_CFG_DRV(GPIO65, AF7, DS08X) -#define GPIO66_MLCD_LDD_12 MFP_CFG_DRV(GPIO66, AF7, DS08X) -#define GPIO67_MLCD_LDD_13 MFP_CFG_DRV(GPIO67, AF7, DS08X) -#define GPIO68_MLCD_LDD_14 MFP_CFG_DRV(GPIO68, AF7, DS08X) -#define GPIO69_MLCD_LDD_15 MFP_CFG_DRV(GPIO69, AF7, DS08X) -#define GPIO74_MLCD_PCLK MFP_CFG_DRV(GPIO74, AF7, DS08X) -#define GPIO75_MLCD_BIAS MFP_CFG_DRV(GPIO75, AF2, DS08X) - -/* MMC1 */ -#define GPIO7_MMC1_CLK MFP_CFG_LPM(GPIO7, AF4, DRIVE_HIGH) -#define GPIO8_MMC1_CMD MFP_CFG_LPM(GPIO8, AF4, DRIVE_HIGH) -#define GPIO14_MMC1_CMD MFP_CFG_LPM(GPIO14, AF5, DRIVE_HIGH) -#define GPIO15_MMC1_CMD MFP_CFG_LPM(GPIO15, AF5, DRIVE_HIGH) -#define GPIO3_MMC1_DAT0 MFP_CFG_LPM(GPIO3, AF4, DRIVE_HIGH) -#define GPIO4_MMC1_DAT1 MFP_CFG_LPM(GPIO4, AF4, DRIVE_HIGH) -#define GPIO5_MMC1_DAT2 MFP_CFG_LPM(GPIO5, AF4, DRIVE_HIGH) -#define GPIO6_MMC1_DAT3 MFP_CFG_LPM(GPIO6, AF4, DRIVE_HIGH) - -/* MMC2 */ -#define GPIO9_MMC2_DAT0 MFP_CFG_LPM(GPIO9, AF4, PULL_HIGH) -#define GPIO10_MMC2_DAT1 MFP_CFG_LPM(GPIO10, AF4, PULL_HIGH) -#define GPIO11_MMC2_DAT2 MFP_CFG_LPM(GPIO11, AF4, PULL_HIGH) -#define GPIO12_MMC2_DAT3 MFP_CFG_LPM(GPIO12, AF4, PULL_HIGH) -#define GPIO13_MMC2_CLK MFP_CFG_LPM(GPIO13, AF4, PULL_HIGH) -#define GPIO14_MMC2_CMD MFP_CFG_LPM(GPIO14, AF4, PULL_HIGH) -#define GPIO77_MMC2_DAT0 MFP_CFG_LPM(GPIO77, AF4, PULL_HIGH) -#define GPIO78_MMC2_DAT1 MFP_CFG_LPM(GPIO78, AF4, PULL_HIGH) -#define GPIO79_MMC2_DAT2 MFP_CFG_LPM(GPIO79, AF4, PULL_HIGH) -#define GPIO80_MMC2_DAT3 MFP_CFG_LPM(GPIO80, AF4, PULL_HIGH) -#define GPIO81_MMC2_CLK MFP_CFG_LPM(GPIO81, AF4, PULL_HIGH) -#define GPIO82_MMC2_CMD MFP_CFG_LPM(GPIO82, AF4, PULL_HIGH) - -/* SSP1 */ -#define GPIO89_SSP1_EXTCLK MFP_CFG(GPIO89, AF1) -#define GPIO90_SSP1_SYSCLK MFP_CFG(GPIO90, AF1) -#define GPIO15_SSP1_SCLK MFP_CFG(GPIO15, AF6) -#define GPIO16_SSP1_FRM MFP_CFG(GPIO16, AF2) -#define GPIO33_SSP1_SCLK MFP_CFG(GPIO33, AF5) -#define GPIO34_SSP1_FRM MFP_CFG(GPIO34, AF5) -#define GPIO85_SSP1_SCLK MFP_CFG(GPIO85, AF1) -#define GPIO86_SSP1_FRM MFP_CFG(GPIO86, AF1) -#define GPIO18_SSP1_TXD MFP_CFG(GPIO18, AF7) -#define GPIO18_SSP1_RXD MFP_CFG(GPIO18, AF2) -#define GPIO20_SSP1_TXD MFP_CFG(GPIO20, AF2) -#define GPIO20_SSP1_RXD MFP_CFG(GPIO20, AF7) -#define GPIO35_SSP1_TXD MFP_CFG(GPIO35, AF5) -#define GPIO35_SSP1_RXD MFP_CFG(GPIO35, AF4) -#define GPIO36_SSP1_TXD MFP_CFG(GPIO36, AF5) -#define GPIO36_SSP1_RXD MFP_CFG(GPIO36, AF6) -#define GPIO87_SSP1_TXD MFP_CFG(GPIO87, AF1) -#define GPIO87_SSP1_RXD MFP_CFG(GPIO87, AF6) -#define GPIO88_SSP1_TXD MFP_CFG(GPIO88, AF6) -#define GPIO88_SSP1_RXD MFP_CFG(GPIO88, AF1) - -/* SSP2 */ -#define GPIO29_SSP2_EXTCLK MFP_CFG(GPIO29, AF2) -#define GPIO23_SSP2_SCLK MFP_CFG(GPIO23, AF2) -#define GPIO17_SSP2_FRM MFP_CFG(GPIO17, AF2) -#define GPIO25_SSP2_SCLK MFP_CFG(GPIO25, AF2) -#define GPIO26_SSP2_FRM MFP_CFG(GPIO26, AF2) -#define GPIO33_SSP2_SCLK MFP_CFG(GPIO33, AF6) -#define GPIO34_SSP2_FRM MFP_CFG(GPIO34, AF6) -#define GPIO64_SSP2_SCLK MFP_CFG(GPIO64, AF2) -#define GPIO65_SSP2_FRM MFP_CFG(GPIO65, AF2) -#define GPIO19_SSP2_TXD MFP_CFG(GPIO19, AF2) -#define GPIO19_SSP2_RXD MFP_CFG(GPIO19, AF7) -#define GPIO24_SSP2_TXD MFP_CFG(GPIO24, AF5) -#define GPIO24_SSP2_RXD MFP_CFG(GPIO24, AF4) -#define GPIO27_SSP2_TXD MFP_CFG(GPIO27, AF2) -#define GPIO27_SSP2_RXD MFP_CFG(GPIO27, AF5) -#define GPIO28_SSP2_TXD MFP_CFG(GPIO28, AF5) -#define GPIO28_SSP2_RXD MFP_CFG(GPIO28, AF2) -#define GPIO35_SSP2_TXD MFP_CFG(GPIO35, AF7) -#define GPIO35_SSP2_RXD MFP_CFG(GPIO35, AF6) -#define GPIO66_SSP2_TXD MFP_CFG(GPIO66, AF4) -#define GPIO66_SSP2_RXD MFP_CFG(GPIO66, AF2) -#define GPIO67_SSP2_TXD MFP_CFG(GPIO67, AF2) -#define GPIO67_SSP2_RXD MFP_CFG(GPIO67, AF4) -#define GPIO36_SSP2_TXD MFP_CFG(GPIO36, AF7) - -/* SSP3 */ -#define GPIO69_SSP3_FRM MFP_CFG_X(GPIO69, AF2, DS08X, DRIVE_LOW) -#define GPIO68_SSP3_SCLK MFP_CFG_X(GPIO68, AF2, DS08X, FLOAT) -#define GPIO92_SSP3_FRM MFP_CFG_X(GPIO92, AF1, DS08X, DRIVE_LOW) -#define GPIO91_SSP3_SCLK MFP_CFG_X(GPIO91, AF1, DS08X, FLOAT) -#define GPIO70_SSP3_TXD MFP_CFG_X(GPIO70, AF2, DS08X, DRIVE_LOW) -#define GPIO70_SSP3_RXD MFP_CFG_X(GPIO70, AF5, DS08X, FLOAT) -#define GPIO71_SSP3_TXD MFP_CFG_X(GPIO71, AF5, DS08X, DRIVE_LOW) -#define GPIO71_SSP3_RXD MFP_CFG_X(GPIO71, AF2, DS08X, FLOAT) -#define GPIO93_SSP3_TXD MFP_CFG_X(GPIO93, AF1, DS08X, DRIVE_LOW) -#define GPIO93_SSP3_RXD MFP_CFG_X(GPIO93, AF5, DS08X, FLOAT) -#define GPIO94_SSP3_TXD MFP_CFG_X(GPIO94, AF5, DS08X, DRIVE_LOW) -#define GPIO94_SSP3_RXD MFP_CFG_X(GPIO94, AF1, DS08X, FLOAT) - -/* SSP4 */ -#define GPIO95_SSP4_SCLK MFP_CFG_LPM(GPIO95, AF1, PULL_HIGH) -#define GPIO96_SSP4_FRM MFP_CFG_LPM(GPIO96, AF1, PULL_HIGH) -#define GPIO97_SSP4_TXD MFP_CFG_LPM(GPIO97, AF1, PULL_HIGH) -#define GPIO97_SSP4_RXD MFP_CFG_LPM(GPIO97, AF5, PULL_HIGH) -#define GPIO98_SSP4_TXD MFP_CFG_LPM(GPIO98, AF5, PULL_HIGH) -#define GPIO98_SSP4_RXD MFP_CFG_LPM(GPIO98, AF1, PULL_HIGH) - -/* UART1 */ -#define GPIO32_UART1_CTS MFP_CFG_LPM(GPIO32, AF2, FLOAT) -#define GPIO37_UART1_CTS MFP_CFG_LPM(GPIO37, AF4, FLOAT) -#define GPIO79_UART1_CTS MFP_CFG_LPM(GPIO79, AF1, FLOAT) -#define GPIO84_UART1_CTS MFP_CFG_LPM(GPIO84, AF3, FLOAT) -#define GPIO101_UART1_CTS MFP_CFG_LPM(GPIO101, AF1, FLOAT) -#define GPIO106_UART1_CTS MFP_CFG_LPM(GPIO106, AF6, FLOAT) - -#define GPIO32_UART1_RTS MFP_CFG_LPM(GPIO32, AF4, FLOAT) -#define GPIO37_UART1_RTS MFP_CFG_LPM(GPIO37, AF2, FLOAT) -#define GPIO79_UART1_RTS MFP_CFG_LPM(GPIO79, AF3, FLOAT) -#define GPIO84_UART1_RTS MFP_CFG_LPM(GPIO84, AF1, FLOAT) -#define GPIO101_UART1_RTS MFP_CFG_LPM(GPIO101, AF6, FLOAT) -#define GPIO106_UART1_RTS MFP_CFG_LPM(GPIO106, AF1, FLOAT) - -#define GPIO34_UART1_DSR MFP_CFG_LPM(GPIO34, AF2, FLOAT) -#define GPIO36_UART1_DSR MFP_CFG_LPM(GPIO36, AF4, FLOAT) -#define GPIO81_UART1_DSR MFP_CFG_LPM(GPIO81, AF1, FLOAT) -#define GPIO83_UART1_DSR MFP_CFG_LPM(GPIO83, AF3, FLOAT) -#define GPIO103_UART1_DSR MFP_CFG_LPM(GPIO103, AF1, FLOAT) -#define GPIO105_UART1_DSR MFP_CFG_LPM(GPIO105, AF6, FLOAT) - -#define GPIO34_UART1_DTR MFP_CFG_LPM(GPIO34, AF4, FLOAT) -#define GPIO36_UART1_DTR MFP_CFG_LPM(GPIO36, AF2, FLOAT) -#define GPIO81_UART1_DTR MFP_CFG_LPM(GPIO81, AF3, FLOAT) -#define GPIO83_UART1_DTR MFP_CFG_LPM(GPIO83, AF1, FLOAT) -#define GPIO103_UART1_DTR MFP_CFG_LPM(GPIO103, AF6, FLOAT) -#define GPIO105_UART1_DTR MFP_CFG_LPM(GPIO105, AF1, FLOAT) - -#define GPIO35_UART1_RI MFP_CFG_LPM(GPIO35, AF2, FLOAT) -#define GPIO82_UART1_RI MFP_CFG_LPM(GPIO82, AF1, FLOAT) -#define GPIO104_UART1_RI MFP_CFG_LPM(GPIO104, AF1, FLOAT) - -#define GPIO33_UART1_DCD MFP_CFG_LPM(GPIO33, AF2, FLOAT) -#define GPIO80_UART1_DCD MFP_CFG_LPM(GPIO80, AF1, FLOAT) -#define GPIO102_UART1_DCD MFP_CFG_LPM(GPIO102, AF1, FLOAT) - -#define GPIO30_UART1_RXD MFP_CFG_LPM(GPIO30, AF2, FLOAT) -#define GPIO31_UART1_RXD MFP_CFG_LPM(GPIO31, AF4, FLOAT) -#define GPIO77_UART1_RXD MFP_CFG_LPM(GPIO77, AF1, FLOAT) -#define GPIO78_UART1_RXD MFP_CFG_LPM(GPIO78, AF3, FLOAT) -#define GPIO99_UART1_RXD MFP_CFG_LPM(GPIO99, AF1, FLOAT) -#define GPIO100_UART1_RXD MFP_CFG_LPM(GPIO100, AF6, FLOAT) -#define GPIO102_UART1_RXD MFP_CFG_LPM(GPIO102, AF6, FLOAT) -#define GPIO104_UART1_RXD MFP_CFG_LPM(GPIO104, AF4, FLOAT) - -#define GPIO30_UART1_TXD MFP_CFG_LPM(GPIO30, AF4, FLOAT) -#define GPIO31_UART1_TXD MFP_CFG_LPM(GPIO31, AF2, FLOAT) -#define GPIO77_UART1_TXD MFP_CFG_LPM(GPIO77, AF3, FLOAT) -#define GPIO78_UART1_TXD MFP_CFG_LPM(GPIO78, AF1, FLOAT) -#define GPIO99_UART1_TXD MFP_CFG_LPM(GPIO99, AF6, FLOAT) -#define GPIO100_UART1_TXD MFP_CFG_LPM(GPIO100, AF1, FLOAT) -#define GPIO102_UART1_TXD MFP_CFG_LPM(GPIO102, AF4, FLOAT) - -/* UART2 */ -#define GPIO15_UART2_CTS MFP_CFG_LPM(GPIO15, AF3, FLOAT) -#define GPIO16_UART2_CTS MFP_CFG_LPM(GPIO16, AF5, FLOAT) -#define GPIO111_UART2_CTS MFP_CFG_LPM(GPIO111, AF3, FLOAT) -#define GPIO114_UART2_CTS MFP_CFG_LPM(GPIO114, AF1, FLOAT) - -#define GPIO15_UART2_RTS MFP_CFG_LPM(GPIO15, AF4, FLOAT) -#define GPIO16_UART2_RTS MFP_CFG_LPM(GPIO16, AF4, FLOAT) -#define GPIO114_UART2_RTS MFP_CFG_LPM(GPIO114, AF3, FLOAT) -#define GPIO111_UART2_RTS MFP_CFG_LPM(GPIO111, AF1, FLOAT) - -#define GPIO18_UART2_RXD MFP_CFG_LPM(GPIO18, AF5, FLOAT) -#define GPIO19_UART2_RXD MFP_CFG_LPM(GPIO19, AF4, FLOAT) -#define GPIO112_UART2_RXD MFP_CFG_LPM(GPIO112, AF1, FLOAT) -#define GPIO113_UART2_RXD MFP_CFG_LPM(GPIO113, AF3, FLOAT) - -#define GPIO18_UART2_TXD MFP_CFG_LPM(GPIO18, AF4, FLOAT) -#define GPIO19_UART2_TXD MFP_CFG_LPM(GPIO19, AF5, FLOAT) -#define GPIO112_UART2_TXD MFP_CFG_LPM(GPIO112, AF3, FLOAT) -#define GPIO113_UART2_TXD MFP_CFG_LPM(GPIO113, AF1, FLOAT) - -/* UART3 */ -#define GPIO91_UART3_CTS MFP_CFG_LPM(GPIO91, AF2, FLOAT) -#define GPIO92_UART3_CTS MFP_CFG_LPM(GPIO92, AF4, FLOAT) -#define GPIO107_UART3_CTS MFP_CFG_LPM(GPIO107, AF1, FLOAT) -#define GPIO108_UART3_CTS MFP_CFG_LPM(GPIO108, AF3, FLOAT) - -#define GPIO91_UART3_RTS MFP_CFG_LPM(GPIO91, AF4, FLOAT) -#define GPIO92_UART3_RTS MFP_CFG_LPM(GPIO92, AF2, FLOAT) -#define GPIO107_UART3_RTS MFP_CFG_LPM(GPIO107, AF3, FLOAT) -#define GPIO108_UART3_RTS MFP_CFG_LPM(GPIO108, AF1, FLOAT) - -#define GPIO7_UART3_RXD MFP_CFG_LPM(GPIO7, AF2, FLOAT) -#define GPIO8_UART3_RXD MFP_CFG_LPM(GPIO8, AF6, FLOAT) -#define GPIO93_UART3_RXD MFP_CFG_LPM(GPIO93, AF4, FLOAT) -#define GPIO94_UART3_RXD MFP_CFG_LPM(GPIO94, AF2, FLOAT) -#define GPIO109_UART3_RXD MFP_CFG_LPM(GPIO109, AF3, FLOAT) -#define GPIO110_UART3_RXD MFP_CFG_LPM(GPIO110, AF1, FLOAT) - -#define GPIO7_UART3_TXD MFP_CFG_LPM(GPIO7, AF6, FLOAT) -#define GPIO8_UART3_TXD MFP_CFG_LPM(GPIO8, AF2, FLOAT) -#define GPIO93_UART3_TXD MFP_CFG_LPM(GPIO93, AF2, FLOAT) -#define GPIO94_UART3_TXD MFP_CFG_LPM(GPIO94, AF4, FLOAT) -#define GPIO109_UART3_TXD MFP_CFG_LPM(GPIO109, AF1, FLOAT) -#define GPIO110_UART3_TXD MFP_CFG_LPM(GPIO110, AF3, FLOAT) - -/* USB Host */ -#define GPIO0_2_USBH_PEN MFP_CFG(GPIO0_2, AF1) -#define GPIO1_2_USBH_PWR MFP_CFG(GPIO1_2, AF1) - -/* USB P3 */ -#define GPIO77_USB_P3_1 MFP_CFG(GPIO77, AF2) -#define GPIO78_USB_P3_2 MFP_CFG(GPIO78, AF2) -#define GPIO79_USB_P3_3 MFP_CFG(GPIO79, AF2) -#define GPIO80_USB_P3_4 MFP_CFG(GPIO80, AF2) -#define GPIO81_USB_P3_5 MFP_CFG(GPIO81, AF2) -#define GPIO82_USB_P3_6 MFP_CFG(GPIO82, AF2) - -/* PWM */ -#define GPIO17_PWM0_OUT MFP_CFG(GPIO17, AF1) -#define GPIO18_PWM1_OUT MFP_CFG(GPIO18, AF1) -#define GPIO19_PWM2_OUT MFP_CFG(GPIO19, AF1) -#define GPIO20_PWM3_OUT MFP_CFG(GPIO20, AF1) - -/* CIR */ -#define GPIO8_CIR_OUT MFP_CFG(GPIO8, AF5) -#define GPIO16_CIR_OUT MFP_CFG(GPIO16, AF3) - -#define GPIO20_OW_DQ_IN MFP_CFG(GPIO20, AF5) -#define GPIO126_OW_DQ MFP_CFG(GPIO126, AF2) - -#define GPIO0_DF_RDY MFP_CFG(GPIO0, AF1) -#define GPIO7_CLK_BYPASS_XSC MFP_CFG(GPIO7, AF7) -#define GPIO17_EXT_SYNC_MVT_0 MFP_CFG(GPIO17, AF6) -#define GPIO18_EXT_SYNC_MVT_1 MFP_CFG(GPIO18, AF6) -#define GPIO19_OST_CHOUT_MVT_0 MFP_CFG(GPIO19, AF6) -#define GPIO20_OST_CHOUT_MVT_1 MFP_CFG(GPIO20, AF6) -#define GPIO49_48M_CLK MFP_CFG(GPIO49, AF2) -#define GPIO126_EXT_CLK MFP_CFG(GPIO126, AF3) -#define GPIO127_CLK_BYPASS_GB MFP_CFG(GPIO127, AF7) -#define GPIO71_EXT_MATCH_MVT MFP_CFG(GPIO71, AF6) - -#define GPIO3_uIO_IN MFP_CFG(GPIO3, AF1) - -#define GPIO4_uSIM_CARD_STATE MFP_CFG(GPIO4, AF1) -#define GPIO5_uSIM_uCLK MFP_CFG(GPIO5, AF1) -#define GPIO6_uSIM_uRST MFP_CFG(GPIO6, AF1) -#define GPIO16_uSIM_UVS_0 MFP_CFG(GPIO16, AF1) - -#define GPIO9_SCIO MFP_CFG(GPIO9, AF1) -#define GPIO20_RTC_MVT MFP_CFG(GPIO20, AF4) -#define GPIO126_RTC_MVT MFP_CFG(GPIO126, AF1) - -/* - * PXA300 specific MFP configurations - */ -#ifdef CONFIG_CPU_PXA300 -#define GPIO99_USB_P2_2 MFP_CFG(GPIO99, AF2) -#define GPIO99_USB_P2_5 MFP_CFG(GPIO99, AF3) -#define GPIO99_USB_P2_6 MFP_CFG(GPIO99, AF4) -#define GPIO100_USB_P2_2 MFP_CFG(GPIO100, AF4) -#define GPIO100_USB_P2_5 MFP_CFG(GPIO100, AF5) -#define GPIO101_USB_P2_1 MFP_CFG(GPIO101, AF2) -#define GPIO102_USB_P2_4 MFP_CFG(GPIO102, AF2) -#define GPIO104_USB_P2_3 MFP_CFG(GPIO104, AF2) -#define GPIO105_USB_P2_5 MFP_CFG(GPIO105, AF2) -#define GPIO100_USB_P2_6 MFP_CFG(GPIO100, AF2) -#define GPIO106_USB_P2_7 MFP_CFG(GPIO106, AF2) -#define GPIO103_USB_P2_8 MFP_CFG(GPIO103, AF2) - -/* U2D UTMI */ -#define GPIO38_UTM_CLK MFP_CFG(GPIO38, AF1) -#define GPIO26_U2D_RXERROR MFP_CFG(GPIO26, AF3) -#define GPIO50_U2D_RXERROR MFP_CFG(GPIO50, AF1) -#define GPIO89_U2D_RXERROR MFP_CFG(GPIO89, AF5) -#define GPIO24_UTM_RXVALID MFP_CFG(GPIO24, AF3) -#define GPIO48_UTM_RXVALID MFP_CFG(GPIO48, AF2) -#define GPIO87_UTM_RXVALID MFP_CFG(GPIO87, AF5) -#define GPIO25_UTM_RXACTIVE MFP_CFG(GPIO25, AF3) -#define GPIO47_UTM_RXACTIVE MFP_CFG(GPIO47, AF2) -#define GPIO49_UTM_RXACTIVE MFP_CFG(GPIO49, AF1) -#define GPIO88_UTM_RXACTIVE MFP_CFG(GPIO88, AF5) -#define GPIO53_UTM_TXREADY MFP_CFG(GPIO53, AF1) -#define GPIO67_UTM_LINESTATE_0 MFP_CFG(GPIO67, AF3) -#define GPIO92_UTM_LINESTATE_0 MFP_CFG(GPIO92, AF3) -#define GPIO104_UTM_LINESTATE_0 MFP_CFG(GPIO104, AF3) -#define GPIO109_UTM_LINESTATE_0 MFP_CFG(GPIO109, AF4) -#define GPIO68_UTM_LINESTATE_1 MFP_CFG(GPIO68, AF3) -#define GPIO93_UTM_LINESTATE_1 MFP_CFG(GPIO93, AF3) -#define GPIO105_UTM_LINESTATE_1 MFP_CFG(GPIO105, AF3) -#define GPIO27_U2D_OPMODE_0 MFP_CFG(GPIO27, AF4) -#define GPIO51_U2D_OPMODE_0 MFP_CFG(GPIO51, AF2) -#define GPIO90_U2D_OPMODE_0 MFP_CFG(GPIO90, AF7) -#define GPIO28_U2D_OPMODE_1 MFP_CFG(GPIO28, AF4) -#define GPIO52_U2D_OPMODE_1 MFP_CFG(GPIO52, AF2) -#define GPIO106_U2D_OPMODE_1 MFP_CFG(GPIO106, AF3) -#define GPIO110_U2D_OPMODE_1 MFP_CFG(GPIO110, AF5) -#define GPIO76_U2D_RESET MFP_CFG(GPIO76, AF1) -#define GPIO95_U2D_RESET MFP_CFG(GPIO95, AF2) -#define GPIO100_U2D_RESET MFP_CFG(GPIO100, AF3) -#define GPIO66_U2D_SUSPEND MFP_CFG(GPIO66, AF3) -#define GPIO98_U2D_SUSPEND MFP_CFG(GPIO98, AF2) -#define GPIO103_U2D_SUSPEND MFP_CFG(GPIO103, AF3) -#define GPIO65_U2D_TERM_SEL MFP_CFG(GPIO65, AF5) -#define GPIO97_U2D_TERM_SEL MFP_CFG(GPIO97, AF3) -#define GPIO102_U2D_TERM_SEL MFP_CFG(GPIO102, AF5) -#define GPIO29_U2D_TXVALID MFP_CFG(GPIO29, AF3) -#define GPIO52_U2D_TXVALID MFP_CFG(GPIO52, AF4) -#define GPIO69_U2D_TXVALID MFP_CFG(GPIO69, AF3) -#define GPIO85_U2D_TXVALID MFP_CFG(GPIO85, AF7) -#define GPIO64_U2D_XCVR_SEL MFP_CFG(GPIO64, AF5) -#define GPIO96_U2D_XCVR_SEL MFP_CFG(GPIO96, AF3) -#define GPIO101_U2D_XCVR_SEL MFP_CFG(GPIO101, AF5) -#define GPIO30_UTM_PHYDATA_0 MFP_CFG(GPIO30, AF3) -#define GPIO31_UTM_PHYDATA_1 MFP_CFG(GPIO31, AF3) -#define GPIO32_UTM_PHYDATA_2 MFP_CFG(GPIO32, AF3) -#define GPIO33_UTM_PHYDATA_3 MFP_CFG(GPIO33, AF3) -#define GPIO34_UTM_PHYDATA_4 MFP_CFG(GPIO34, AF3) -#define GPIO35_UTM_PHYDATA_5 MFP_CFG(GPIO35, AF3) -#define GPIO36_UTM_PHYDATA_6 MFP_CFG(GPIO36, AF3) -#define GPIO37_UTM_PHYDATA_7 MFP_CFG(GPIO37, AF3) -#define GPIO39_UTM_PHYDATA_0 MFP_CFG(GPIO39, AF3) -#define GPIO40_UTM_PHYDATA_1 MFP_CFG(GPIO40, AF3) -#define GPIO41_UTM_PHYDATA_2 MFP_CFG(GPIO41, AF3) -#define GPIO42_UTM_PHYDATA_3 MFP_CFG(GPIO42, AF3) -#define GPIO43_UTM_PHYDATA_4 MFP_CFG(GPIO43, AF3) -#define GPIO44_UTM_PHYDATA_5 MFP_CFG(GPIO44, AF3) -#define GPIO45_UTM_PHYDATA_6 MFP_CFG(GPIO45, AF3) -#define GPIO46_UTM_PHYDATA_7 MFP_CFG(GPIO46, AF3) -#endif /* CONFIG_CPU_PXA300 */ - -/* - * PXA310 specific MFP configurations - */ -#ifdef CONFIG_CPU_PXA310 -/* USB P2 */ -#define GPIO36_USB_P2_1 MFP_CFG(GPIO36, AF1) -#define GPIO30_USB_P2_2 MFP_CFG(GPIO30, AF1) -#define GPIO35_USB_P2_3 MFP_CFG(GPIO35, AF1) -#define GPIO32_USB_P2_4 MFP_CFG(GPIO32, AF1) -#define GPIO34_USB_P2_5 MFP_CFG(GPIO34, AF1) -#define GPIO31_USB_P2_6 MFP_CFG(GPIO31, AF1) - -/* MMC1 */ -#define GPIO24_MMC1_CMD MFP_CFG(GPIO24, AF3) -#define GPIO29_MMC1_DAT0 MFP_CFG(GPIO29, AF3) - -/* MMC3 */ -#define GPIO103_MMC3_CLK MFP_CFG(GPIO103, AF2) -#define GPIO105_MMC3_CMD MFP_CFG(GPIO105, AF2) -#define GPIO11_2_MMC3_CLK MFP_CFG(GPIO11_2, AF1) -#define GPIO12_2_MMC3_CMD MFP_CFG(GPIO12_2, AF1) -#define GPIO7_2_MMC3_DAT0 MFP_CFG(GPIO7_2, AF1) -#define GPIO8_2_MMC3_DAT1 MFP_CFG(GPIO8_2, AF1) -#define GPIO9_2_MMC3_DAT2 MFP_CFG(GPIO9_2, AF1) -#define GPIO10_2_MMC3_DAT3 MFP_CFG(GPIO10_2, AF1) - -/* ULPI */ -#define GPIO38_ULPI_CLK MFP_CFG(GPIO38, AF1) -#define GPIO30_ULPI_DATA_OUT_0 MFP_CFG(GPIO30, AF3) -#define GPIO31_ULPI_DATA_OUT_1 MFP_CFG(GPIO31, AF3) -#define GPIO32_ULPI_DATA_OUT_2 MFP_CFG(GPIO32, AF3) -#define GPIO33_ULPI_DATA_OUT_3 MFP_CFG(GPIO33, AF3) -#define GPIO34_ULPI_DATA_OUT_4 MFP_CFG(GPIO34, AF3) -#define GPIO35_ULPI_DATA_OUT_5 MFP_CFG(GPIO35, AF3) -#define GPIO36_ULPI_DATA_OUT_6 MFP_CFG(GPIO36, AF3) -#define GPIO37_ULPI_DATA_OUT_7 MFP_CFG(GPIO37, AF3) -#define GPIO33_ULPI_OTG_INTR MFP_CFG(GPIO33, AF1) - -#define ULPI_DIR MFP_CFG_DRV(ULPI_DIR, AF0, DS01X) -#define ULPI_NXT MFP_CFG_DRV(ULPI_NXT, AF0, DS01X) -#define ULPI_STP MFP_CFG_DRV(ULPI_STP, AF0, DS01X) -#endif /* CONFIG_CPU_PXA310 */ - -#endif /* __ASM_ARCH_MFP_PXA300_H */ diff --git a/arch/arm/mach-pxa/include/mach/mfp-pxa320.h b/arch/arm/mach-pxa/include/mach/mfp-pxa320.h deleted file mode 100644 index 3ce4682eabb6..000000000000 --- a/arch/arm/mach-pxa/include/mach/mfp-pxa320.h +++ /dev/null @@ -1,461 +0,0 @@ -/* - * arch/arm/mach-pxa/include/mach/mfp-pxa320.h - * - * PXA320 specific MFP configuration definitions - * - * Copyright (C) 2007 Marvell International Ltd. - * 2007-08-21: eric miao - * initial version - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef __ASM_ARCH_MFP_PXA320_H -#define __ASM_ARCH_MFP_PXA320_H - -#include - -/* GPIO */ -#define GPIO46_GPIO MFP_CFG(GPIO46, AF0) -#define GPIO49_GPIO MFP_CFG(GPIO49, AF0) -#define GPIO50_GPIO MFP_CFG(GPIO50, AF0) -#define GPIO51_GPIO MFP_CFG(GPIO51, AF0) -#define GPIO52_GPIO MFP_CFG(GPIO52, AF0) - -#define GPIO7_2_GPIO MFP_CFG(GPIO7_2, AF0) -#define GPIO8_2_GPIO MFP_CFG(GPIO8_2, AF0) -#define GPIO9_2_GPIO MFP_CFG(GPIO9_2, AF0) -#define GPIO10_2_GPIO MFP_CFG(GPIO10_2, AF0) -#define GPIO11_2_GPIO MFP_CFG(GPIO11_2, AF0) -#define GPIO12_2_GPIO MFP_CFG(GPIO12_2, AF0) -#define GPIO13_2_GPIO MFP_CFG(GPIO13_2, AF0) -#define GPIO14_2_GPIO MFP_CFG(GPIO14_2, AF0) -#define GPIO15_2_GPIO MFP_CFG(GPIO15_2, AF0) -#define GPIO16_2_GPIO MFP_CFG(GPIO16_2, AF0) -#define GPIO17_2_GPIO MFP_CFG(GPIO17_2, AF0) - -/* Chip Select */ -#define GPIO3_nCS2 MFP_CFG(GPIO3, AF1) -#define GPIO4_nCS3 MFP_CFG(GPIO4, AF1) - -/* AC97 */ -#define GPIO34_AC97_SYSCLK MFP_CFG(GPIO34, AF1) -#define GPIO39_AC97_BITCLK MFP_CFG(GPIO39, AF1) -#define GPIO40_AC97_nACRESET MFP_CFG(GPIO40, AF1) -#define GPIO35_AC97_SDATA_IN_0 MFP_CFG(GPIO35, AF1) -#define GPIO36_AC97_SDATA_IN_1 MFP_CFG(GPIO36, AF1) -#define GPIO32_AC97_SDATA_IN_2 MFP_CFG(GPIO32, AF2) -#define GPIO33_AC97_SDATA_IN_3 MFP_CFG(GPIO33, AF2) -#define GPIO11_AC97_SDATA_IN_2 MFP_CFG(GPIO11, AF3) -#define GPIO12_AC97_SDATA_IN_3 MFP_CFG(GPIO12, AF3) -#define GPIO37_AC97_SDATA_OUT MFP_CFG(GPIO37, AF1) -#define GPIO38_AC97_SYNC MFP_CFG(GPIO38, AF1) - -/* I2C */ -#define GPIO32_I2C_SCL MFP_CFG_LPM(GPIO32, AF1, PULL_HIGH) -#define GPIO33_I2C_SDA MFP_CFG_LPM(GPIO33, AF1, PULL_HIGH) - -/* QCI */ -#define GPIO49_CI_DD_0 MFP_CFG_DRV(GPIO49, AF1, DS04X) -#define GPIO50_CI_DD_1 MFP_CFG_DRV(GPIO50, AF1, DS04X) -#define GPIO51_CI_DD_2 MFP_CFG_DRV(GPIO51, AF1, DS04X) -#define GPIO52_CI_DD_3 MFP_CFG_DRV(GPIO52, AF1, DS04X) -#define GPIO53_CI_DD_4 MFP_CFG_DRV(GPIO53, AF1, DS04X) -#define GPIO54_CI_DD_5 MFP_CFG_DRV(GPIO54, AF1, DS04X) -#define GPIO55_CI_DD_6 MFP_CFG_DRV(GPIO55, AF1, DS04X) -#define GPIO56_CI_DD_7 MFP_CFG_DRV(GPIO56, AF0, DS04X) -#define GPIO57_CI_DD_8 MFP_CFG_DRV(GPIO57, AF1, DS04X) -#define GPIO58_CI_DD_9 MFP_CFG_DRV(GPIO58, AF1, DS04X) -#define GPIO59_CI_MCLK MFP_CFG_DRV(GPIO59, AF0, DS04X) -#define GPIO60_CI_PCLK MFP_CFG_DRV(GPIO60, AF0, DS04X) -#define GPIO61_CI_HSYNC MFP_CFG_DRV(GPIO61, AF0, DS04X) -#define GPIO62_CI_VSYNC MFP_CFG_DRV(GPIO62, AF0, DS04X) - -#define GPIO31_CIR_OUT MFP_CFG(GPIO31, AF5) - -#define GPIO0_2_CLK_EXT MFP_CFG(GPIO0_2, AF3) -#define GPIO0_DRQ MFP_CFG(GPIO0, AF2) -#define GPIO11_EXT_SYNC0 MFP_CFG(GPIO11, AF5) -#define GPIO12_EXT_SYNC1 MFP_CFG(GPIO12, AF6) -#define GPIO0_2_HZ_CLK MFP_CFG(GPIO0_2, AF1) -#define GPIO14_HZ_CLK MFP_CFG(GPIO14, AF4) -#define GPIO30_ICP_RXD MFP_CFG(GPIO30, AF1) -#define GPIO31_ICP_TXD MFP_CFG(GPIO31, AF1) - -#define GPIO83_KP_DKIN_0 MFP_CFG_LPM(GPIO83, AF3, FLOAT) -#define GPIO84_KP_DKIN_1 MFP_CFG_LPM(GPIO84, AF3, FLOAT) -#define GPIO85_KP_DKIN_2 MFP_CFG_LPM(GPIO85, AF3, FLOAT) -#define GPIO86_KP_DKIN_3 MFP_CFG_LPM(GPIO86, AF3, FLOAT) - -#define GPIO105_KP_DKIN_0 MFP_CFG_LPM(GPIO105, AF2, FLOAT) -#define GPIO106_KP_DKIN_1 MFP_CFG_LPM(GPIO106, AF2, FLOAT) -#define GPIO107_KP_DKIN_2 MFP_CFG_LPM(GPIO107, AF2, FLOAT) -#define GPIO108_KP_DKIN_3 MFP_CFG_LPM(GPIO108, AF2, FLOAT) -#define GPIO109_KP_DKIN_4 MFP_CFG_LPM(GPIO109, AF2, FLOAT) -#define GPIO110_KP_DKIN_5 MFP_CFG_LPM(GPIO110, AF2, FLOAT) -#define GPIO111_KP_DKIN_6 MFP_CFG_LPM(GPIO111, AF2, FLOAT) -#define GPIO112_KP_DKIN_7 MFP_CFG_LPM(GPIO112, AF2, FLOAT) - -#define GPIO113_KP_DKIN_0 MFP_CFG_LPM(GPIO113, AF2, FLOAT) -#define GPIO114_KP_DKIN_1 MFP_CFG_LPM(GPIO114, AF2, FLOAT) -#define GPIO115_KP_DKIN_2 MFP_CFG_LPM(GPIO115, AF2, FLOAT) -#define GPIO116_KP_DKIN_3 MFP_CFG_LPM(GPIO116, AF2, FLOAT) -#define GPIO117_KP_DKIN_4 MFP_CFG_LPM(GPIO117, AF2, FLOAT) -#define GPIO118_KP_DKIN_5 MFP_CFG_LPM(GPIO118, AF2, FLOAT) -#define GPIO119_KP_DKIN_6 MFP_CFG_LPM(GPIO119, AF2, FLOAT) -#define GPIO120_KP_DKIN_7 MFP_CFG_LPM(GPIO120, AF2, FLOAT) - -#define GPIO127_KP_DKIN_0 MFP_CFG_LPM(GPIO127, AF2, FLOAT) -#define GPIO126_KP_DKIN_1 MFP_CFG_LPM(GPIO126, AF2, FLOAT) - -#define GPIO2_2_KP_DKIN_0 MFP_CFG_LPM(GPIO2_2, AF2, FLOAT) -#define GPIO3_2_KP_DKIN_1 MFP_CFG_LPM(GPIO3_2, AF2, FLOAT) -#define GPIO125_KP_DKIN_2 MFP_CFG_LPM(GPIO125, AF2, FLOAT) -#define GPIO124_KP_DKIN_3 MFP_CFG_LPM(GPIO124, AF2, FLOAT) -#define GPIO123_KP_DKIN_4 MFP_CFG_LPM(GPIO123, AF2, FLOAT) -#define GPIO122_KP_DKIN_5 MFP_CFG_LPM(GPIO122, AF2, FLOAT) -#define GPIO121_KP_DKIN_6 MFP_CFG_LPM(GPIO121, AF2, FLOAT) -#define GPIO4_2_KP_DKIN_7 MFP_CFG_LPM(GPIO4_2, AF2, FLOAT) - -#define GPIO113_KP_MKIN_0 MFP_CFG_LPM(GPIO113, AF1, FLOAT) -#define GPIO114_KP_MKIN_1 MFP_CFG_LPM(GPIO114, AF1, FLOAT) -#define GPIO115_KP_MKIN_2 MFP_CFG_LPM(GPIO115, AF1, FLOAT) -#define GPIO116_KP_MKIN_3 MFP_CFG_LPM(GPIO116, AF1, FLOAT) -#define GPIO117_KP_MKIN_4 MFP_CFG_LPM(GPIO117, AF1, FLOAT) -#define GPIO118_KP_MKIN_5 MFP_CFG_LPM(GPIO118, AF1, FLOAT) -#define GPIO119_KP_MKIN_6 MFP_CFG_LPM(GPIO119, AF1, FLOAT) -#define GPIO120_KP_MKIN_7 MFP_CFG_LPM(GPIO120, AF1, FLOAT) - -#define GPIO83_KP_MKOUT_0 MFP_CFG_LPM(GPIO83, AF2, DRIVE_HIGH) -#define GPIO84_KP_MKOUT_1 MFP_CFG_LPM(GPIO84, AF2, DRIVE_HIGH) -#define GPIO85_KP_MKOUT_2 MFP_CFG_LPM(GPIO85, AF2, DRIVE_HIGH) -#define GPIO86_KP_MKOUT_3 MFP_CFG_LPM(GPIO86, AF2, DRIVE_HIGH) -#define GPIO13_KP_MKOUT_4 MFP_CFG_LPM(GPIO13, AF3, DRIVE_HIGH) -#define GPIO14_KP_MKOUT_5 MFP_CFG_LPM(GPIO14, AF3, DRIVE_HIGH) - -#define GPIO121_KP_MKOUT_0 MFP_CFG_LPM(GPIO121, AF1, DRIVE_HIGH) -#define GPIO122_KP_MKOUT_1 MFP_CFG_LPM(GPIO122, AF1, DRIVE_HIGH) -#define GPIO123_KP_MKOUT_2 MFP_CFG_LPM(GPIO123, AF1, DRIVE_HIGH) -#define GPIO124_KP_MKOUT_3 MFP_CFG_LPM(GPIO124, AF1, DRIVE_HIGH) -#define GPIO125_KP_MKOUT_4 MFP_CFG_LPM(GPIO125, AF1, DRIVE_HIGH) -#define GPIO126_KP_MKOUT_5 MFP_CFG_LPM(GPIO126, AF1, DRIVE_HIGH) -#define GPIO127_KP_MKOUT_6 MFP_CFG_LPM(GPIO127, AF1, DRIVE_HIGH) -#define GPIO5_2_KP_MKOUT_7 MFP_CFG_LPM(GPIO5_2, AF1, DRIVE_HIGH) - -/* LCD */ -#define GPIO6_2_LCD_LDD_0 MFP_CFG_DRV(GPIO6_2, AF1, DS01X) -#define GPIO7_2_LCD_LDD_1 MFP_CFG_DRV(GPIO7_2, AF1, DS01X) -#define GPIO8_2_LCD_LDD_2 MFP_CFG_DRV(GPIO8_2, AF1, DS01X) -#define GPIO9_2_LCD_LDD_3 MFP_CFG_DRV(GPIO9_2, AF1, DS01X) -#define GPIO10_2_LCD_LDD_4 MFP_CFG_DRV(GPIO10_2, AF1, DS01X) -#define GPIO11_2_LCD_LDD_5 MFP_CFG_DRV(GPIO11_2, AF1, DS01X) -#define GPIO12_2_LCD_LDD_6 MFP_CFG_DRV(GPIO12_2, AF1, DS01X) -#define GPIO13_2_LCD_LDD_7 MFP_CFG_DRV(GPIO13_2, AF1, DS01X) -#define GPIO63_LCD_LDD_8 MFP_CFG_DRV(GPIO63, AF1, DS01X) -#define GPIO64_LCD_LDD_9 MFP_CFG_DRV(GPIO64, AF1, DS01X) -#define GPIO65_LCD_LDD_10 MFP_CFG_DRV(GPIO65, AF1, DS01X) -#define GPIO66_LCD_LDD_11 MFP_CFG_DRV(GPIO66, AF1, DS01X) -#define GPIO67_LCD_LDD_12 MFP_CFG_DRV(GPIO67, AF1, DS01X) -#define GPIO68_LCD_LDD_13 MFP_CFG_DRV(GPIO68, AF1, DS01X) -#define GPIO69_LCD_LDD_14 MFP_CFG_DRV(GPIO69, AF1, DS01X) -#define GPIO70_LCD_LDD_15 MFP_CFG_DRV(GPIO70, AF1, DS01X) -#define GPIO71_LCD_LDD_16 MFP_CFG_DRV(GPIO71, AF1, DS01X) -#define GPIO72_LCD_LDD_17 MFP_CFG_DRV(GPIO72, AF1, DS01X) -#define GPIO73_LCD_CS_N MFP_CFG_DRV(GPIO73, AF2, DS01X) -#define GPIO74_LCD_VSYNC MFP_CFG_DRV(GPIO74, AF2, DS01X) -#define GPIO14_2_LCD_FCLK MFP_CFG_DRV(GPIO14_2, AF1, DS01X) -#define GPIO15_2_LCD_LCLK MFP_CFG_DRV(GPIO15_2, AF1, DS01X) -#define GPIO16_2_LCD_PCLK MFP_CFG_DRV(GPIO16_2, AF1, DS01X) -#define GPIO17_2_LCD_BIAS MFP_CFG_DRV(GPIO17_2, AF1, DS01X) -#define GPIO64_LCD_VSYNC MFP_CFG_DRV(GPIO64, AF2, DS01X) -#define GPIO63_LCD_CS_N MFP_CFG_DRV(GPIO63, AF2, DS01X) - -#define GPIO6_2_MLCD_DD_0 MFP_CFG_DRV(GPIO6_2, AF7, DS08X) -#define GPIO7_2_MLCD_DD_1 MFP_CFG_DRV(GPIO7_2, AF7, DS08X) -#define GPIO8_2_MLCD_DD_2 MFP_CFG_DRV(GPIO8_2, AF7, DS08X) -#define GPIO9_2_MLCD_DD_3 MFP_CFG_DRV(GPIO9_2, AF7, DS08X) -#define GPIO10_2_MLCD_DD_4 MFP_CFG_DRV(GPIO10_2, AF7, DS08X) -#define GPIO11_2_MLCD_DD_5 MFP_CFG_DRV(GPIO11_2, AF7, DS08X) -#define GPIO12_2_MLCD_DD_6 MFP_CFG_DRV(GPIO12_2, AF7, DS08X) -#define GPIO13_2_MLCD_DD_7 MFP_CFG_DRV(GPIO13_2, AF7, DS08X) -#define GPIO63_MLCD_DD_8 MFP_CFG_DRV(GPIO63, AF7, DS08X) -#define GPIO64_MLCD_DD_9 MFP_CFG_DRV(GPIO64, AF7, DS08X) -#define GPIO65_MLCD_DD_10 MFP_CFG_DRV(GPIO65, AF7, DS08X) -#define GPIO66_MLCD_DD_11 MFP_CFG_DRV(GPIO66, AF7, DS08X) -#define GPIO67_MLCD_DD_12 MFP_CFG_DRV(GPIO67, AF7, DS08X) -#define GPIO68_MLCD_DD_13 MFP_CFG_DRV(GPIO68, AF7, DS08X) -#define GPIO69_MLCD_DD_14 MFP_CFG_DRV(GPIO69, AF7, DS08X) -#define GPIO70_MLCD_DD_15 MFP_CFG_DRV(GPIO70, AF7, DS08X) -#define GPIO71_MLCD_DD_16 MFP_CFG_DRV(GPIO71, AF7, DS08X) -#define GPIO72_MLCD_DD_17 MFP_CFG_DRV(GPIO72, AF7, DS08X) -#define GPIO73_MLCD_CS MFP_CFG_DRV(GPIO73, AF7, DS08X) -#define GPIO74_MLCD_VSYNC MFP_CFG_DRV(GPIO74, AF7, DS08X) -#define GPIO14_2_MLCD_FCLK MFP_CFG_DRV(GPIO14_2, AF7, DS08X) -#define GPIO15_2_MLCD_LCLK MFP_CFG_DRV(GPIO15_2, AF7, DS08X) -#define GPIO16_2_MLCD_PCLK MFP_CFG_DRV(GPIO16_2, AF7, DS08X) -#define GPIO17_2_MLCD_BIAS MFP_CFG_DRV(GPIO17_2, AF7, DS08X) - -/* MMC1 */ -#define GPIO9_MMC1_CMD MFP_CFG_LPM(GPIO9, AF4, DRIVE_HIGH) -#define GPIO22_MMC1_CLK MFP_CFG_LPM(GPIO22, AF4, DRIVE_HIGH) -#define GPIO23_MMC1_CMD MFP_CFG_LPM(GPIO23, AF4, DRIVE_HIGH) -#define GPIO30_MMC1_CLK MFP_CFG_LPM(GPIO30, AF4, DRIVE_HIGH) -#define GPIO31_MMC1_CMD MFP_CFG_LPM(GPIO31, AF4, DRIVE_HIGH) -#define GPIO5_MMC1_DAT0 MFP_CFG_LPM(GPIO5, AF4, DRIVE_HIGH) -#define GPIO6_MMC1_DAT1 MFP_CFG_LPM(GPIO6, AF4, DRIVE_HIGH) -#define GPIO7_MMC1_DAT2 MFP_CFG_LPM(GPIO7, AF4, DRIVE_HIGH) -#define GPIO8_MMC1_DAT3 MFP_CFG_LPM(GPIO8, AF4, DRIVE_HIGH) -#define GPIO18_MMC1_DAT0 MFP_CFG_LPM(GPIO18, AF4, DRIVE_HIGH) -#define GPIO19_MMC1_DAT1 MFP_CFG_LPM(GPIO19, AF4, DRIVE_HIGH) -#define GPIO20_MMC1_DAT2 MFP_CFG_LPM(GPIO20, AF4, DRIVE_HIGH) -#define GPIO21_MMC1_DAT3 MFP_CFG_LPM(GPIO21, AF4, DRIVE_HIGH) - -#define GPIO28_MMC2_CLK MFP_CFG_LPM(GPIO28, AF4, PULL_HIGH) -#define GPIO29_MMC2_CMD MFP_CFG_LPM(GPIO29, AF4, PULL_HIGH) -#define GPIO30_MMC2_CLK MFP_CFG_LPM(GPIO30, AF3, PULL_HIGH) -#define GPIO31_MMC2_CMD MFP_CFG_LPM(GPIO31, AF3, PULL_HIGH) -#define GPIO79_MMC2_CLK MFP_CFG_LPM(GPIO79, AF4, PULL_HIGH) -#define GPIO80_MMC2_CMD MFP_CFG_LPM(GPIO80, AF4, PULL_HIGH) - -#define GPIO5_MMC2_DAT0 MFP_CFG_LPM(GPIO5, AF2, PULL_HIGH) -#define GPIO6_MMC2_DAT1 MFP_CFG_LPM(GPIO6, AF2, PULL_HIGH) -#define GPIO7_MMC2_DAT2 MFP_CFG_LPM(GPIO7, AF2, PULL_HIGH) -#define GPIO8_MMC2_DAT3 MFP_CFG_LPM(GPIO8, AF2, PULL_HIGH) -#define GPIO24_MMC2_DAT0 MFP_CFG_LPM(GPIO24, AF4, PULL_HIGH) -#define GPIO75_MMC2_DAT0 MFP_CFG_LPM(GPIO75, AF4, PULL_HIGH) -#define GPIO25_MMC2_DAT1 MFP_CFG_LPM(GPIO25, AF4, PULL_HIGH) -#define GPIO76_MMC2_DAT1 MFP_CFG_LPM(GPIO76, AF4, PULL_HIGH) -#define GPIO26_MMC2_DAT2 MFP_CFG_LPM(GPIO26, AF4, PULL_HIGH) -#define GPIO77_MMC2_DAT2 MFP_CFG_LPM(GPIO77, AF4, PULL_HIGH) -#define GPIO27_MMC2_DAT3 MFP_CFG_LPM(GPIO27, AF4, PULL_HIGH) -#define GPIO78_MMC2_DAT3 MFP_CFG_LPM(GPIO78, AF4, PULL_HIGH) - -/* 1-Wire */ -#define GPIO14_ONE_WIRE MFP_CFG_LPM(GPIO14, AF5, FLOAT) -#define GPIO0_2_ONE_WIRE MFP_CFG_LPM(GPIO0_2, AF2, FLOAT) - -/* SSP1 */ -#define GPIO87_SSP1_EXTCLK MFP_CFG(GPIO87, AF1) -#define GPIO88_SSP1_SYSCLK MFP_CFG(GPIO88, AF1) -#define GPIO83_SSP1_SCLK MFP_CFG(GPIO83, AF1) -#define GPIO84_SSP1_SFRM MFP_CFG(GPIO84, AF1) -#define GPIO85_SSP1_RXD MFP_CFG(GPIO85, AF6) -#define GPIO85_SSP1_TXD MFP_CFG(GPIO85, AF1) -#define GPIO86_SSP1_RXD MFP_CFG(GPIO86, AF1) -#define GPIO86_SSP1_TXD MFP_CFG(GPIO86, AF6) - -/* SSP2 */ -#define GPIO39_SSP2_EXTCLK MFP_CFG(GPIO39, AF2) -#define GPIO40_SSP2_SYSCLK MFP_CFG(GPIO40, AF2) -#define GPIO12_SSP2_SCLK MFP_CFG(GPIO12, AF2) -#define GPIO35_SSP2_SCLK MFP_CFG(GPIO35, AF2) -#define GPIO36_SSP2_SFRM MFP_CFG(GPIO36, AF2) -#define GPIO37_SSP2_RXD MFP_CFG(GPIO37, AF5) -#define GPIO37_SSP2_TXD MFP_CFG(GPIO37, AF2) -#define GPIO38_SSP2_RXD MFP_CFG(GPIO38, AF2) -#define GPIO38_SSP2_TXD MFP_CFG(GPIO38, AF5) - -#define GPIO69_SSP3_SCLK MFP_CFG_X(GPIO69, AF2, DS08X, FLOAT) -#define GPIO70_SSP3_FRM MFP_CFG_X(GPIO70, AF2, DS08X, DRIVE_LOW) -#define GPIO89_SSP3_SCLK MFP_CFG_X(GPIO89, AF1, DS08X, FLOAT) -#define GPIO90_SSP3_FRM MFP_CFG_X(GPIO90, AF1, DS08X, DRIVE_LOW) -#define GPIO71_SSP3_RXD MFP_CFG_X(GPIO71, AF5, DS08X, FLOAT) -#define GPIO71_SSP3_TXD MFP_CFG_X(GPIO71, AF2, DS08X, DRIVE_LOW) -#define GPIO72_SSP3_RXD MFP_CFG_X(GPIO72, AF2, DS08X, FLOAT) -#define GPIO72_SSP3_TXD MFP_CFG_X(GPIO72, AF5, DS08X, DRIVE_LOW) -#define GPIO91_SSP3_RXD MFP_CFG_X(GPIO91, AF5, DS08X, FLOAT) -#define GPIO91_SSP3_TXD MFP_CFG_X(GPIO91, AF1, DS08X, DRIVE_LOW) -#define GPIO92_SSP3_RXD MFP_CFG_X(GPIO92, AF1, DS08X, FLOAT) -#define GPIO92_SSP3_TXD MFP_CFG_X(GPIO92, AF5, DS08X, DRIVE_LOW) - -#define GPIO93_SSP4_SCLK MFP_CFG_LPM(GPIO93, AF1, PULL_HIGH) -#define GPIO94_SSP4_FRM MFP_CFG_LPM(GPIO94, AF1, PULL_HIGH) -#define GPIO94_SSP4_RXD MFP_CFG_LPM(GPIO94, AF5, PULL_HIGH) -#define GPIO95_SSP4_RXD MFP_CFG_LPM(GPIO95, AF5, PULL_HIGH) -#define GPIO95_SSP4_TXD MFP_CFG_LPM(GPIO95, AF1, PULL_HIGH) -#define GPIO96_SSP4_RXD MFP_CFG_LPM(GPIO96, AF1, PULL_HIGH) -#define GPIO96_SSP4_TXD MFP_CFG_LPM(GPIO96, AF5, PULL_HIGH) - -/* UART1 */ -#define GPIO41_UART1_RXD MFP_CFG_LPM(GPIO41, AF2, FLOAT) -#define GPIO41_UART1_TXD MFP_CFG_LPM(GPIO41, AF4, FLOAT) -#define GPIO42_UART1_RXD MFP_CFG_LPM(GPIO42, AF4, FLOAT) -#define GPIO42_UART1_TXD MFP_CFG_LPM(GPIO42, AF2, FLOAT) -#define GPIO75_UART1_RXD MFP_CFG_LPM(GPIO75, AF1, FLOAT) -#define GPIO76_UART1_RXD MFP_CFG_LPM(GPIO76, AF3, FLOAT) -#define GPIO76_UART1_TXD MFP_CFG_LPM(GPIO76, AF1, FLOAT) -#define GPIO97_UART1_RXD MFP_CFG_LPM(GPIO97, AF1, FLOAT) -#define GPIO97_UART1_TXD MFP_CFG_LPM(GPIO97, AF6, FLOAT) -#define GPIO98_UART1_RXD MFP_CFG_LPM(GPIO98, AF6, FLOAT) -#define GPIO98_UART1_TXD MFP_CFG_LPM(GPIO98, AF1, FLOAT) -#define GPIO43_UART1_CTS MFP_CFG_LPM(GPIO43, AF2, FLOAT) -#define GPIO43_UART1_RTS MFP_CFG_LPM(GPIO43, AF4, FLOAT) -#define GPIO48_UART1_CTS MFP_CFG_LPM(GPIO48, AF4, FLOAT) -#define GPIO48_UART1_RTS MFP_CFG_LPM(GPIO48, AF2, FLOAT) -#define GPIO77_UART1_CTS MFP_CFG_LPM(GPIO77, AF1, FLOAT) -#define GPIO82_UART1_RTS MFP_CFG_LPM(GPIO82, AF1, FLOAT) -#define GPIO82_UART1_CTS MFP_CFG_LPM(GPIO82, AF3, FLOAT) -#define GPIO99_UART1_CTS MFP_CFG_LPM(GPIO99, AF1, FLOAT) -#define GPIO99_UART1_RTS MFP_CFG_LPM(GPIO99, AF6, FLOAT) -#define GPIO104_UART1_CTS MFP_CFG_LPM(GPIO104, AF6, FLOAT) -#define GPIO104_UART1_RTS MFP_CFG_LPM(GPIO104, AF1, FLOAT) -#define GPIO45_UART1_DTR MFP_CFG_LPM(GPIO45, AF4, FLOAT) -#define GPIO45_UART1_DSR MFP_CFG_LPM(GPIO45, AF2, FLOAT) -#define GPIO47_UART1_DTR MFP_CFG_LPM(GPIO47, AF2, FLOAT) -#define GPIO47_UART1_DSR MFP_CFG_LPM(GPIO47, AF4, FLOAT) -#define GPIO79_UART1_DSR MFP_CFG_LPM(GPIO79, AF1, FLOAT) -#define GPIO81_UART1_DTR MFP_CFG_LPM(GPIO81, AF1, FLOAT) -#define GPIO81_UART1_DSR MFP_CFG_LPM(GPIO81, AF3, FLOAT) -#define GPIO101_UART1_DTR MFP_CFG_LPM(GPIO101, AF6, FLOAT) -#define GPIO101_UART1_DSR MFP_CFG_LPM(GPIO101, AF1, FLOAT) -#define GPIO103_UART1_DTR MFP_CFG_LPM(GPIO103, AF1, FLOAT) -#define GPIO103_UART1_DSR MFP_CFG_LPM(GPIO103, AF6, FLOAT) -#define GPIO44_UART1_DCD MFP_CFG_LPM(GPIO44, AF2, FLOAT) -#define GPIO78_UART1_DCD MFP_CFG_LPM(GPIO78, AF1, FLOAT) -#define GPIO100_UART1_DCD MFP_CFG_LPM(GPIO100, AF1, FLOAT) -#define GPIO46_UART1_RI MFP_CFG_LPM(GPIO46, AF2, FLOAT) -#define GPIO80_UART1_RI MFP_CFG_LPM(GPIO80, AF1, FLOAT) -#define GPIO102_UART1_RI MFP_CFG_LPM(GPIO102, AF1, FLOAT) - -/* UART2 */ -#define GPIO109_UART2_CTS MFP_CFG_LPM(GPIO109, AF3, FLOAT) -#define GPIO109_UART2_RTS MFP_CFG_LPM(GPIO109, AF1, FLOAT) -#define GPIO112_UART2_CTS MFP_CFG_LPM(GPIO112, AF1, FLOAT) -#define GPIO112_UART2_RTS MFP_CFG_LPM(GPIO112, AF3, FLOAT) -#define GPIO110_UART2_RXD MFP_CFG_LPM(GPIO110, AF1, FLOAT) -#define GPIO110_UART2_TXD MFP_CFG_LPM(GPIO110, AF3, FLOAT) -#define GPIO111_UART2_RXD MFP_CFG_LPM(GPIO111, AF3, FLOAT) -#define GPIO111_UART2_TXD MFP_CFG_LPM(GPIO111, AF1, FLOAT) - -/* UART3 */ -#define GPIO89_UART3_CTS MFP_CFG_LPM(GPIO89, AF2, FLOAT) -#define GPIO89_UART3_RTS MFP_CFG_LPM(GPIO89, AF4, FLOAT) -#define GPIO90_UART3_CTS MFP_CFG_LPM(GPIO90, AF4, FLOAT) -#define GPIO90_UART3_RTS MFP_CFG_LPM(GPIO90, AF2, FLOAT) -#define GPIO105_UART3_CTS MFP_CFG_LPM(GPIO105, AF1, FLOAT) -#define GPIO105_UART3_RTS MFP_CFG_LPM(GPIO105, AF3, FLOAT) -#define GPIO106_UART3_CTS MFP_CFG_LPM(GPIO106, AF3, FLOAT) -#define GPIO106_UART3_RTS MFP_CFG_LPM(GPIO106, AF1, FLOAT) -#define GPIO30_UART3_RXD MFP_CFG_LPM(GPIO30, AF2, FLOAT) -#define GPIO30_UART3_TXD MFP_CFG_LPM(GPIO30, AF6, FLOAT) -#define GPIO31_UART3_RXD MFP_CFG_LPM(GPIO31, AF6, FLOAT) -#define GPIO31_UART3_TXD MFP_CFG_LPM(GPIO31, AF2, FLOAT) -#define GPIO91_UART3_RXD MFP_CFG_LPM(GPIO91, AF4, FLOAT) -#define GPIO91_UART3_TXD MFP_CFG_LPM(GPIO91, AF2, FLOAT) -#define GPIO92_UART3_RXD MFP_CFG_LPM(GPIO92, AF2, FLOAT) -#define GPIO92_UART3_TXD MFP_CFG_LPM(GPIO92, AF4, FLOAT) -#define GPIO107_UART3_RXD MFP_CFG_LPM(GPIO107, AF3, FLOAT) -#define GPIO107_UART3_TXD MFP_CFG_LPM(GPIO107, AF1, FLOAT) -#define GPIO108_UART3_RXD MFP_CFG_LPM(GPIO108, AF1, FLOAT) -#define GPIO108_UART3_TXD MFP_CFG_LPM(GPIO108, AF3, FLOAT) - - -/* USB 2.0 UTMI */ -#define GPIO10_UTM_CLK MFP_CFG(GPIO10, AF1) -#define GPIO36_U2D_RXERROR MFP_CFG(GPIO36, AF3) -#define GPIO60_U2D_RXERROR MFP_CFG(GPIO60, AF1) -#define GPIO87_U2D_RXERROR MFP_CFG(GPIO87, AF5) -#define GPIO34_UTM_RXVALID MFP_CFG(GPIO34, AF3) -#define GPIO58_UTM_RXVALID MFP_CFG(GPIO58, AF2) -#define GPIO85_UTM_RXVALID MFP_CFG(GPIO85, AF5) -#define GPIO35_UTM_RXACTIVE MFP_CFG(GPIO35, AF3) -#define GPIO59_UTM_RXACTIVE MFP_CFG(GPIO59, AF1) -#define GPIO86_UTM_RXACTIVE MFP_CFG(GPIO86, AF5) -#define GPIO73_UTM_TXREADY MFP_CFG(GPIO73, AF1) -#define GPIO68_UTM_LINESTATE_0 MFP_CFG(GPIO68, AF3) -#define GPIO90_UTM_LINESTATE_0 MFP_CFG(GPIO90, AF3) -#define GPIO102_UTM_LINESTATE_0 MFP_CFG(GPIO102, AF3) -#define GPIO107_UTM_LINESTATE_0 MFP_CFG(GPIO107, AF4) -#define GPIO69_UTM_LINESTATE_1 MFP_CFG(GPIO69, AF3) -#define GPIO91_UTM_LINESTATE_1 MFP_CFG(GPIO91, AF3) -#define GPIO103_UTM_LINESTATE_1 MFP_CFG(GPIO103, AF3) - -#define GPIO41_U2D_PHYDATA_0 MFP_CFG(GPIO41, AF3) -#define GPIO42_U2D_PHYDATA_1 MFP_CFG(GPIO42, AF3) -#define GPIO43_U2D_PHYDATA_2 MFP_CFG(GPIO43, AF3) -#define GPIO44_U2D_PHYDATA_3 MFP_CFG(GPIO44, AF3) -#define GPIO45_U2D_PHYDATA_4 MFP_CFG(GPIO45, AF3) -#define GPIO46_U2D_PHYDATA_5 MFP_CFG(GPIO46, AF3) -#define GPIO47_U2D_PHYDATA_6 MFP_CFG(GPIO47, AF3) -#define GPIO48_U2D_PHYDATA_7 MFP_CFG(GPIO48, AF3) - -#define GPIO49_U2D_PHYDATA_0 MFP_CFG(GPIO49, AF3) -#define GPIO50_U2D_PHYDATA_1 MFP_CFG(GPIO50, AF3) -#define GPIO51_U2D_PHYDATA_2 MFP_CFG(GPIO51, AF3) -#define GPIO52_U2D_PHYDATA_3 MFP_CFG(GPIO52, AF3) -#define GPIO53_U2D_PHYDATA_4 MFP_CFG(GPIO53, AF3) -#define GPIO54_U2D_PHYDATA_5 MFP_CFG(GPIO54, AF3) -#define GPIO55_U2D_PHYDATA_6 MFP_CFG(GPIO55, AF3) -#define GPIO56_U2D_PHYDATA_7 MFP_CFG(GPIO56, AF3) - -#define GPIO37_U2D_OPMODE0 MFP_CFG(GPIO37, AF4) -#define GPIO61_U2D_OPMODE0 MFP_CFG(GPIO61, AF2) -#define GPIO88_U2D_OPMODE0 MFP_CFG(GPIO88, AF7) - -#define GPIO38_U2D_OPMODE1 MFP_CFG(GPIO38, AF4) -#define GPIO62_U2D_OPMODE1 MFP_CFG(GPIO62, AF2) -#define GPIO104_U2D_OPMODE1 MFP_CFG(GPIO104, AF4) -#define GPIO108_U2D_OPMODE1 MFP_CFG(GPIO108, AF5) - -#define GPIO74_U2D_RESET MFP_CFG(GPIO74, AF1) -#define GPIO93_U2D_RESET MFP_CFG(GPIO93, AF2) -#define GPIO98_U2D_RESET MFP_CFG(GPIO98, AF3) - -#define GPIO67_U2D_SUSPEND MFP_CFG(GPIO67, AF3) -#define GPIO96_U2D_SUSPEND MFP_CFG(GPIO96, AF2) -#define GPIO101_U2D_SUSPEND MFP_CFG(GPIO101, AF3) - -#define GPIO66_U2D_TERM_SEL MFP_CFG(GPIO66, AF5) -#define GPIO95_U2D_TERM_SEL MFP_CFG(GPIO95, AF3) -#define GPIO97_U2D_TERM_SEL MFP_CFG(GPIO97, AF7) -#define GPIO100_U2D_TERM_SEL MFP_CFG(GPIO100, AF5) - -#define GPIO39_U2D_TXVALID MFP_CFG(GPIO39, AF4) -#define GPIO70_U2D_TXVALID MFP_CFG(GPIO70, AF5) -#define GPIO83_U2D_TXVALID MFP_CFG(GPIO83, AF7) - -#define GPIO65_U2D_XCVR_SEL MFP_CFG(GPIO65, AF5) -#define GPIO94_U2D_XCVR_SEL MFP_CFG(GPIO94, AF3) -#define GPIO99_U2D_XCVR_SEL MFP_CFG(GPIO99, AF5) - -/* USB Host 1.1 */ -#define GPIO2_2_USBH_PEN MFP_CFG(GPIO2_2, AF1) -#define GPIO3_2_USBH_PWR MFP_CFG(GPIO3_2, AF1) - -/* USB P2 */ -#define GPIO97_USB_P2_2 MFP_CFG(GPIO97, AF2) -#define GPIO97_USB_P2_6 MFP_CFG(GPIO97, AF4) -#define GPIO98_USB_P2_2 MFP_CFG(GPIO98, AF4) -#define GPIO98_USB_P2_6 MFP_CFG(GPIO98, AF2) -#define GPIO99_USB_P2_1 MFP_CFG(GPIO99, AF2) -#define GPIO100_USB_P2_4 MFP_CFG(GPIO100, AF2) -#define GPIO101_USB_P2_8 MFP_CFG(GPIO101, AF2) -#define GPIO102_USB_P2_3 MFP_CFG(GPIO102, AF2) -#define GPIO103_USB_P2_5 MFP_CFG(GPIO103, AF2) -#define GPIO104_USB_P2_7 MFP_CFG(GPIO104, AF2) - -/* USB P3 */ -#define GPIO75_USB_P3_1 MFP_CFG(GPIO75, AF2) -#define GPIO76_USB_P3_2 MFP_CFG(GPIO76, AF2) -#define GPIO77_USB_P3_3 MFP_CFG(GPIO77, AF2) -#define GPIO78_USB_P3_4 MFP_CFG(GPIO78, AF2) -#define GPIO79_USB_P3_5 MFP_CFG(GPIO79, AF2) -#define GPIO80_USB_P3_6 MFP_CFG(GPIO80, AF2) - -#define GPIO13_CHOUT0 MFP_CFG(GPIO13, AF6) -#define GPIO14_CHOUT1 MFP_CFG(GPIO14, AF6) - -#define GPIO2_RDY MFP_CFG(GPIO2, AF1) -#define GPIO5_NPIOR MFP_CFG(GPIO5, AF3) -#define GPIO6_NPIOW MFP_CFG(GPIO6, AF3) -#define GPIO7_NPIOS16 MFP_CFG(GPIO7, AF3) -#define GPIO8_NPWAIT MFP_CFG(GPIO8, AF3) - -#define GPIO11_PWM0_OUT MFP_CFG(GPIO11, AF1) -#define GPIO12_PWM1_OUT MFP_CFG(GPIO12, AF1) -#define GPIO13_PWM2_OUT MFP_CFG(GPIO13, AF1) -#define GPIO14_PWM3_OUT MFP_CFG(GPIO14, AF1) - -#endif /* __ASM_ARCH_MFP_PXA320_H */ diff --git a/arch/arm/mach-pxa/include/mach/mfp-pxa3xx.h b/arch/arm/mach-pxa/include/mach/mfp-pxa3xx.h deleted file mode 100644 index d375195d982b..000000000000 --- a/arch/arm/mach-pxa/include/mach/mfp-pxa3xx.h +++ /dev/null @@ -1,158 +0,0 @@ -#ifndef __ASM_ARCH_MFP_PXA3XX_H -#define __ASM_ARCH_MFP_PXA3XX_H - -#include - -#define MFPR_BASE (0x40e10000) - -/* PXA3xx common MFP configurations - processor specific ones defined - * in mfp-pxa300.h and mfp-pxa320.h - */ -#define GPIO0_GPIO MFP_CFG(GPIO0, AF0) -#define GPIO1_GPIO MFP_CFG(GPIO1, AF0) -#define GPIO2_GPIO MFP_CFG(GPIO2, AF0) -#define GPIO3_GPIO MFP_CFG(GPIO3, AF0) -#define GPIO4_GPIO MFP_CFG(GPIO4, AF0) -#define GPIO5_GPIO MFP_CFG(GPIO5, AF0) -#define GPIO6_GPIO MFP_CFG(GPIO6, AF0) -#define GPIO7_GPIO MFP_CFG(GPIO7, AF0) -#define GPIO8_GPIO MFP_CFG(GPIO8, AF0) -#define GPIO9_GPIO MFP_CFG(GPIO9, AF0) -#define GPIO10_GPIO MFP_CFG(GPIO10, AF0) -#define GPIO11_GPIO MFP_CFG(GPIO11, AF0) -#define GPIO12_GPIO MFP_CFG(GPIO12, AF0) -#define GPIO13_GPIO MFP_CFG(GPIO13, AF0) -#define GPIO14_GPIO MFP_CFG(GPIO14, AF0) -#define GPIO15_GPIO MFP_CFG(GPIO15, AF0) -#define GPIO16_GPIO MFP_CFG(GPIO16, AF0) -#define GPIO17_GPIO MFP_CFG(GPIO17, AF0) -#define GPIO18_GPIO MFP_CFG(GPIO18, AF0) -#define GPIO19_GPIO MFP_CFG(GPIO19, AF0) -#define GPIO20_GPIO MFP_CFG(GPIO20, AF0) -#define GPIO21_GPIO MFP_CFG(GPIO21, AF0) -#define GPIO22_GPIO MFP_CFG(GPIO22, AF0) -#define GPIO23_GPIO MFP_CFG(GPIO23, AF0) -#define GPIO24_GPIO MFP_CFG(GPIO24, AF0) -#define GPIO25_GPIO MFP_CFG(GPIO25, AF0) -#define GPIO26_GPIO MFP_CFG(GPIO26, AF0) -#define GPIO27_GPIO MFP_CFG(GPIO27, AF0) -#define GPIO28_GPIO MFP_CFG(GPIO28, AF0) -#define GPIO29_GPIO MFP_CFG(GPIO29, AF0) -#define GPIO30_GPIO MFP_CFG(GPIO30, AF0) -#define GPIO31_GPIO MFP_CFG(GPIO31, AF0) -#define GPIO32_GPIO MFP_CFG(GPIO32, AF0) -#define GPIO33_GPIO MFP_CFG(GPIO33, AF0) -#define GPIO34_GPIO MFP_CFG(GPIO34, AF0) -#define GPIO35_GPIO MFP_CFG(GPIO35, AF0) -#define GPIO36_GPIO MFP_CFG(GPIO36, AF0) -#define GPIO37_GPIO MFP_CFG(GPIO37, AF0) -#define GPIO38_GPIO MFP_CFG(GPIO38, AF0) -#define GPIO39_GPIO MFP_CFG(GPIO39, AF0) -#define GPIO40_GPIO MFP_CFG(GPIO40, AF0) -#define GPIO41_GPIO MFP_CFG(GPIO41, AF0) -#define GPIO42_GPIO MFP_CFG(GPIO42, AF0) -#define GPIO43_GPIO MFP_CFG(GPIO43, AF0) -#define GPIO44_GPIO MFP_CFG(GPIO44, AF0) -#define GPIO45_GPIO MFP_CFG(GPIO45, AF0) - -#define GPIO47_GPIO MFP_CFG(GPIO47, AF0) -#define GPIO48_GPIO MFP_CFG(GPIO48, AF0) - -#define GPIO53_GPIO MFP_CFG(GPIO53, AF0) -#define GPIO54_GPIO MFP_CFG(GPIO54, AF0) -#define GPIO55_GPIO MFP_CFG(GPIO55, AF0) - -#define GPIO57_GPIO MFP_CFG(GPIO57, AF0) - -#define GPIO63_GPIO MFP_CFG(GPIO63, AF0) -#define GPIO64_GPIO MFP_CFG(GPIO64, AF0) -#define GPIO65_GPIO MFP_CFG(GPIO65, AF0) -#define GPIO66_GPIO MFP_CFG(GPIO66, AF0) -#define GPIO67_GPIO MFP_CFG(GPIO67, AF0) -#define GPIO68_GPIO MFP_CFG(GPIO68, AF0) -#define GPIO69_GPIO MFP_CFG(GPIO69, AF0) -#define GPIO70_GPIO MFP_CFG(GPIO70, AF0) -#define GPIO71_GPIO MFP_CFG(GPIO71, AF0) -#define GPIO72_GPIO MFP_CFG(GPIO72, AF0) -#define GPIO73_GPIO MFP_CFG(GPIO73, AF0) -#define GPIO74_GPIO MFP_CFG(GPIO74, AF0) -#define GPIO75_GPIO MFP_CFG(GPIO75, AF0) -#define GPIO76_GPIO MFP_CFG(GPIO76, AF0) -#define GPIO77_GPIO MFP_CFG(GPIO77, AF0) -#define GPIO78_GPIO MFP_CFG(GPIO78, AF0) -#define GPIO79_GPIO MFP_CFG(GPIO79, AF0) -#define GPIO80_GPIO MFP_CFG(GPIO80, AF0) -#define GPIO81_GPIO MFP_CFG(GPIO81, AF0) -#define GPIO82_GPIO MFP_CFG(GPIO82, AF0) -#define GPIO83_GPIO MFP_CFG(GPIO83, AF0) -#define GPIO84_GPIO MFP_CFG(GPIO84, AF0) -#define GPIO85_GPIO MFP_CFG(GPIO85, AF0) -#define GPIO86_GPIO MFP_CFG(GPIO86, AF0) -#define GPIO87_GPIO MFP_CFG(GPIO87, AF0) -#define GPIO88_GPIO MFP_CFG(GPIO88, AF0) -#define GPIO89_GPIO MFP_CFG(GPIO89, AF0) -#define GPIO90_GPIO MFP_CFG(GPIO90, AF0) -#define GPIO91_GPIO MFP_CFG(GPIO91, AF0) -#define GPIO92_GPIO MFP_CFG(GPIO92, AF0) -#define GPIO93_GPIO MFP_CFG(GPIO93, AF0) -#define GPIO94_GPIO MFP_CFG(GPIO94, AF0) -#define GPIO95_GPIO MFP_CFG(GPIO95, AF0) -#define GPIO96_GPIO MFP_CFG(GPIO96, AF0) -#define GPIO97_GPIO MFP_CFG(GPIO97, AF0) -#define GPIO98_GPIO MFP_CFG(GPIO98, AF0) -#define GPIO99_GPIO MFP_CFG(GPIO99, AF0) -#define GPIO100_GPIO MFP_CFG(GPIO100, AF0) -#define GPIO101_GPIO MFP_CFG(GPIO101, AF0) -#define GPIO102_GPIO MFP_CFG(GPIO102, AF0) -#define GPIO103_GPIO MFP_CFG(GPIO103, AF0) -#define GPIO104_GPIO MFP_CFG(GPIO104, AF0) -#define GPIO105_GPIO MFP_CFG(GPIO105, AF0) -#define GPIO106_GPIO MFP_CFG(GPIO106, AF0) -#define GPIO107_GPIO MFP_CFG(GPIO107, AF0) -#define GPIO108_GPIO MFP_CFG(GPIO108, AF0) -#define GPIO109_GPIO MFP_CFG(GPIO109, AF0) -#define GPIO110_GPIO MFP_CFG(GPIO110, AF0) -#define GPIO111_GPIO MFP_CFG(GPIO111, AF0) -#define GPIO112_GPIO MFP_CFG(GPIO112, AF0) -#define GPIO113_GPIO MFP_CFG(GPIO113, AF0) -#define GPIO114_GPIO MFP_CFG(GPIO114, AF0) -#define GPIO115_GPIO MFP_CFG(GPIO115, AF0) -#define GPIO116_GPIO MFP_CFG(GPIO116, AF0) -#define GPIO117_GPIO MFP_CFG(GPIO117, AF0) -#define GPIO118_GPIO MFP_CFG(GPIO118, AF0) -#define GPIO119_GPIO MFP_CFG(GPIO119, AF0) -#define GPIO120_GPIO MFP_CFG(GPIO120, AF0) -#define GPIO121_GPIO MFP_CFG(GPIO121, AF0) -#define GPIO122_GPIO MFP_CFG(GPIO122, AF0) -#define GPIO123_GPIO MFP_CFG(GPIO123, AF0) -#define GPIO124_GPIO MFP_CFG(GPIO124, AF0) -#define GPIO125_GPIO MFP_CFG(GPIO125, AF0) -#define GPIO126_GPIO MFP_CFG(GPIO126, AF0) -#define GPIO127_GPIO MFP_CFG(GPIO127, AF0) - -#define GPIO0_2_GPIO MFP_CFG(GPIO0_2, AF0) -#define GPIO1_2_GPIO MFP_CFG(GPIO1_2, AF0) -#define GPIO2_2_GPIO MFP_CFG(GPIO2_2, AF0) -#define GPIO3_2_GPIO MFP_CFG(GPIO3_2, AF0) -#define GPIO4_2_GPIO MFP_CFG(GPIO4_2, AF0) -#define GPIO5_2_GPIO MFP_CFG(GPIO5_2, AF0) -#define GPIO6_2_GPIO MFP_CFG(GPIO6_2, AF0) - -/* NOTE: usage of these two functions is not recommended, - * use pxa3xx_mfp_config() instead. - */ -static inline unsigned long pxa3xx_mfp_read(int mfp) -{ - return mfp_read(mfp); -} - -static inline void pxa3xx_mfp_write(int mfp, unsigned long val) -{ - mfp_write(mfp, val); -} - -static inline void pxa3xx_mfp_config(unsigned long *mfp_cfg, int num) -{ - mfp_config(mfp_cfg, num); -} -#endif /* __ASM_ARCH_MFP_PXA3XX_H */ diff --git a/arch/arm/mach-pxa/include/mach/mfp-pxa930.h b/arch/arm/mach-pxa/include/mach/mfp-pxa930.h deleted file mode 100644 index 04f7c97044f3..000000000000 --- a/arch/arm/mach-pxa/include/mach/mfp-pxa930.h +++ /dev/null @@ -1,498 +0,0 @@ -/* - * arch/arm/mach-pxa/include/mach/mfp-pxa930.h - * - * PXA930 specific MFP configuration definitions - * - * Copyright (C) 2007-2008 Marvell International Ltd. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef __ASM_ARCH_MFP_PXA9xx_H -#define __ASM_ARCH_MFP_PXA9xx_H - -#include - -/* GPIO */ -#define GPIO46_GPIO MFP_CFG(GPIO46, AF0) -#define GPIO49_GPIO MFP_CFG(GPIO49, AF0) -#define GPIO50_GPIO MFP_CFG(GPIO50, AF0) -#define GPIO51_GPIO MFP_CFG(GPIO51, AF0) -#define GPIO52_GPIO MFP_CFG(GPIO52, AF0) -#define GPIO56_GPIO MFP_CFG(GPIO56, AF0) -#define GPIO58_GPIO MFP_CFG(GPIO58, AF0) -#define GPIO59_GPIO MFP_CFG(GPIO59, AF0) -#define GPIO60_GPIO MFP_CFG(GPIO60, AF0) -#define GPIO61_GPIO MFP_CFG(GPIO61, AF0) -#define GPIO62_GPIO MFP_CFG(GPIO62, AF0) - -#define GSIM_UCLK_GPIO_79 MFP_CFG(GSIM_UCLK, AF0) -#define GSIM_UIO_GPIO_80 MFP_CFG(GSIM_UIO, AF0) -#define GSIM_nURST_GPIO_81 MFP_CFG(GSIM_nURST, AF0) -#define GSIM_UDET_GPIO_82 MFP_CFG(GSIM_UDET, AF0) - -#define DF_IO15_GPIO_28 MFP_CFG(DF_IO15, AF0) -#define DF_IO14_GPIO_29 MFP_CFG(DF_IO14, AF0) -#define DF_IO13_GPIO_30 MFP_CFG(DF_IO13, AF0) -#define DF_IO12_GPIO_31 MFP_CFG(DF_IO12, AF0) -#define DF_IO11_GPIO_32 MFP_CFG(DF_IO11, AF0) -#define DF_IO10_GPIO_33 MFP_CFG(DF_IO10, AF0) -#define DF_IO9_GPIO_34 MFP_CFG(DF_IO9, AF0) -#define DF_IO8_GPIO_35 MFP_CFG(DF_IO8, AF0) -#define DF_IO7_GPIO_36 MFP_CFG(DF_IO7, AF0) -#define DF_IO6_GPIO_37 MFP_CFG(DF_IO6, AF0) -#define DF_IO5_GPIO_38 MFP_CFG(DF_IO5, AF0) -#define DF_IO4_GPIO_39 MFP_CFG(DF_IO4, AF0) -#define DF_IO3_GPIO_40 MFP_CFG(DF_IO3, AF0) -#define DF_IO2_GPIO_41 MFP_CFG(DF_IO2, AF0) -#define DF_IO1_GPIO_42 MFP_CFG(DF_IO1, AF0) -#define DF_IO0_GPIO_43 MFP_CFG(DF_IO0, AF0) -#define DF_nCS0_GPIO_44 MFP_CFG(DF_nCS0, AF0) -#define DF_nCS1_GPIO_45 MFP_CFG(DF_nCS1, AF0) -#define DF_nWE_GPIO_46 MFP_CFG(DF_nWE, AF0) -#define DF_nRE_nOE_GPIO_47 MFP_CFG(DF_nRE_nOE, AF0) -#define DF_CLE_nOE_GPIO_48 MFP_CFG(DF_CLE_nOE, AF0) -#define DF_nADV1_ALE_GPIO_49 MFP_CFG(DF_nADV1_ALE, AF0) -#define DF_nADV2_ALE_GPIO_50 MFP_CFG(DF_nADV2_ALE, AF0) -#define DF_INT_RnB_GPIO_51 MFP_CFG(DF_INT_RnB, AF0) -#define DF_SCLK_E_GPIO_52 MFP_CFG(DF_SCLK_E, AF0) - -#define DF_ADDR0_GPIO_53 MFP_CFG(DF_ADDR0, AF0) -#define DF_ADDR1_GPIO_54 MFP_CFG(DF_ADDR1, AF0) -#define DF_ADDR2_GPIO_55 MFP_CFG(DF_ADDR2, AF0) -#define DF_ADDR3_GPIO_56 MFP_CFG(DF_ADDR3, AF0) -#define nXCVREN_GPIO_57 MFP_CFG(nXCVREN, AF0) -#define nLUA_GPIO_58 MFP_CFG(nLUA, AF0) -#define nLLA_GPIO_59 MFP_CFG(nLLA, AF0) -#define nBE0_GPIO_60 MFP_CFG(nBE0, AF0) -#define nBE1_GPIO_61 MFP_CFG(nBE1, AF0) -#define RDY_GPIO_62 MFP_CFG(RDY, AF0) -#define PMIC_INT_GPIO83 MFP_CFG_LPM(PMIC_INT, AF0, PULL_HIGH) - -/* Chip Select */ -#define DF_nCS0_nCS2 MFP_CFG_LPM(DF_nCS0, AF3, PULL_HIGH) -#define DF_nCS1_nCS3 MFP_CFG_LPM(DF_nCS1, AF3, PULL_HIGH) - -/* AC97 */ -#define GPIO83_BAC97_SYSCLK MFP_CFG(GPIO83, AF3) -#define GPIO84_BAC97_SDATA_IN0 MFP_CFG(GPIO84, AF3) -#define GPIO85_BAC97_BITCLK MFP_CFG(GPIO85, AF3) -#define GPIO86_BAC97_nRESET MFP_CFG(GPIO86, AF3) -#define GPIO87_BAC97_SYNC MFP_CFG(GPIO87, AF3) -#define GPIO88_BAC97_SDATA_OUT MFP_CFG(GPIO88, AF3) - -/* I2C */ -#define GPIO39_CI2C_SCL MFP_CFG_LPM(GPIO39, AF3, PULL_HIGH) -#define GPIO40_CI2C_SDA MFP_CFG_LPM(GPIO40, AF3, PULL_HIGH) - -#define GPIO51_CI2C_SCL MFP_CFG_LPM(GPIO51, AF3, PULL_HIGH) -#define GPIO52_CI2C_SDA MFP_CFG_LPM(GPIO52, AF3, PULL_HIGH) - -#define GPIO63_CI2C_SCL MFP_CFG_LPM(GPIO63, AF4, PULL_HIGH) -#define GPIO64_CI2C_SDA MFP_CFG_LPM(GPIO64, AF4, PULL_HIGH) - -#define GPIO73_CI2C_SCL MFP_CFG_LPM(GPIO73, AF1, PULL_HIGH) -#define GPIO74_CI2C_SDA MFP_CFG_LPM(GPIO74, AF1, PULL_HIGH) - -#define GPIO77_CI2C_SCL MFP_CFG_LPM(GPIO77, AF2, PULL_HIGH) -#define GPIO78_CI2C_SDA MFP_CFG_LPM(GPIO78, AF2, PULL_HIGH) - -#define GPIO89_CI2C_SCL MFP_CFG_LPM(GPIO89, AF1, PULL_HIGH) -#define GPIO90_CI2C_SDA MFP_CFG_LPM(GPIO90, AF1, PULL_HIGH) - -#define GPIO95_CI2C_SCL MFP_CFG_LPM(GPIO95, AF1, PULL_HIGH) -#define GPIO96_CI2C_SDA MFP_CFG_LPM(GPIO96, AF1, PULL_HIGH) - -#define GPIO97_CI2C_SCL MFP_CFG_LPM(GPIO97, AF3, PULL_HIGH) -#define GPIO98_CI2C_SDA MFP_CFG_LPM(GPIO98, AF3, PULL_HIGH) - -/* QCI */ -#define GPIO63_CI_DD_9 MFP_CFG_LPM(GPIO63, AF1, PULL_LOW) -#define GPIO64_CI_DD_8 MFP_CFG_LPM(GPIO64, AF1, PULL_LOW) -#define GPIO65_CI_DD_7 MFP_CFG_LPM(GPIO65, AF1, PULL_LOW) -#define GPIO66_CI_DD_6 MFP_CFG_LPM(GPIO66, AF1, PULL_LOW) -#define GPIO67_CI_DD_5 MFP_CFG_LPM(GPIO67, AF1, PULL_LOW) -#define GPIO68_CI_DD_4 MFP_CFG_LPM(GPIO68, AF1, PULL_LOW) -#define GPIO69_CI_DD_3 MFP_CFG_LPM(GPIO69, AF1, PULL_LOW) -#define GPIO70_CI_DD_2 MFP_CFG_LPM(GPIO70, AF1, PULL_LOW) -#define GPIO71_CI_DD_1 MFP_CFG_LPM(GPIO71, AF1, PULL_LOW) -#define GPIO72_CI_DD_0 MFP_CFG_LPM(GPIO72, AF1, PULL_LOW) -#define GPIO73_CI_HSYNC MFP_CFG_LPM(GPIO73, AF1, PULL_LOW) -#define GPIO74_CI_VSYNC MFP_CFG_LPM(GPIO74, AF1, PULL_LOW) -#define GPIO75_CI_MCLK MFP_CFG_LPM(GPIO75, AF1, PULL_LOW) -#define GPIO76_CI_PCLK MFP_CFG_LPM(GPIO76, AF1, PULL_LOW) - -/* KEYPAD */ -#define GPIO4_KP_DKIN_4 MFP_CFG_LPM(GPIO4, AF3, FLOAT) -#define GPIO5_KP_DKIN_5 MFP_CFG_LPM(GPIO5, AF3, FLOAT) -#define GPIO6_KP_DKIN_6 MFP_CFG_LPM(GPIO6, AF3, FLOAT) -#define GPIO7_KP_DKIN_7 MFP_CFG_LPM(GPIO7, AF3, FLOAT) -#define GPIO8_KP_DKIN_4 MFP_CFG_LPM(GPIO8, AF3, FLOAT) -#define GPIO9_KP_DKIN_5 MFP_CFG_LPM(GPIO9, AF3, FLOAT) -#define GPIO10_KP_DKIN_6 MFP_CFG_LPM(GPIO10, AF3, FLOAT) -#define GPIO11_KP_DKIN_7 MFP_CFG_LPM(GPIO11, AF3, FLOAT) - -#define GPIO12_KP_DKIN_0 MFP_CFG_LPM(GPIO12, AF2, FLOAT) -#define GPIO13_KP_DKIN_1 MFP_CFG_LPM(GPIO13, AF2, FLOAT) -#define GPIO14_KP_DKIN_2 MFP_CFG_LPM(GPIO14, AF2, FLOAT) -#define GPIO15_KP_DKIN_3 MFP_CFG_LPM(GPIO15, AF2, FLOAT) - -#define GPIO41_KP_DKIN_0 MFP_CFG_LPM(GPIO41, AF2, FLOAT) -#define GPIO42_KP_DKIN_1 MFP_CFG_LPM(GPIO42, AF2, FLOAT) -#define GPIO43_KP_DKIN_2 MFP_CFG_LPM(GPIO43, AF2, FLOAT) -#define GPIO44_KP_DKIN_3 MFP_CFG_LPM(GPIO44, AF2, FLOAT) -#define GPIO41_KP_DKIN_4 MFP_CFG_LPM(GPIO41, AF4, FLOAT) -#define GPIO42_KP_DKIN_5 MFP_CFG_LPM(GPIO42, AF4, FLOAT) - -#define GPIO0_KP_MKIN_0 MFP_CFG_LPM(GPIO0, AF1, FLOAT) -#define GPIO2_KP_MKIN_1 MFP_CFG_LPM(GPIO2, AF1, FLOAT) -#define GPIO4_KP_MKIN_2 MFP_CFG_LPM(GPIO4, AF1, FLOAT) -#define GPIO6_KP_MKIN_3 MFP_CFG_LPM(GPIO6, AF1, FLOAT) -#define GPIO8_KP_MKIN_4 MFP_CFG_LPM(GPIO8, AF1, FLOAT) -#define GPIO10_KP_MKIN_5 MFP_CFG_LPM(GPIO10, AF1, FLOAT) -#define GPIO12_KP_MKIN_6 MFP_CFG_LPM(GPIO12, AF1, FLOAT) -#define GPIO14_KP_MKIN_7 MFP_CFG(GPIO14, AF1) -#define GPIO35_KP_MKIN_5 MFP_CFG(GPIO35, AF4) - -#define GPIO1_KP_MKOUT_0 MFP_CFG_LPM(GPIO1, AF1, DRIVE_HIGH) -#define GPIO3_KP_MKOUT_1 MFP_CFG_LPM(GPIO3, AF1, DRIVE_HIGH) -#define GPIO5_KP_MKOUT_2 MFP_CFG_LPM(GPIO5, AF1, DRIVE_HIGH) -#define GPIO7_KP_MKOUT_3 MFP_CFG_LPM(GPIO7, AF1, DRIVE_HIGH) -#define GPIO9_KP_MKOUT_4 MFP_CFG_LPM(GPIO9, AF1, DRIVE_HIGH) -#define GPIO11_KP_MKOUT_5 MFP_CFG_LPM(GPIO11, AF1, DRIVE_HIGH) -#define GPIO13_KP_MKOUT_6 MFP_CFG_LPM(GPIO13, AF1, DRIVE_HIGH) -#define GPIO15_KP_MKOUT_7 MFP_CFG_LPM(GPIO15, AF1, DRIVE_HIGH) -#define GPIO36_KP_MKOUT_5 MFP_CFG_LPM(GPIO36, AF4, DRIVE_HIGH) - -/* LCD */ -#define GPIO17_LCD_FCLK_RD MFP_CFG(GPIO17, AF1) -#define GPIO18_LCD_LCLK_A0 MFP_CFG(GPIO18, AF1) -#define GPIO19_LCD_PCLK_WR MFP_CFG(GPIO19, AF1) -#define GPIO20_LCD_BIAS MFP_CFG(GPIO20, AF1) -#define GPIO21_LCD_CS MFP_CFG(GPIO21, AF1) -#define GPIO22_LCD_CS2 MFP_CFG(GPIO22, AF2) -#define GPIO22_LCD_VSYNC MFP_CFG(GPIO22, AF1) -#define GPIO23_LCD_DD0 MFP_CFG(GPIO23, AF1) -#define GPIO24_LCD_DD1 MFP_CFG(GPIO24, AF1) -#define GPIO25_LCD_DD2 MFP_CFG(GPIO25, AF1) -#define GPIO26_LCD_DD3 MFP_CFG(GPIO26, AF1) -#define GPIO27_LCD_DD4 MFP_CFG(GPIO27, AF1) -#define GPIO28_LCD_DD5 MFP_CFG(GPIO28, AF1) -#define GPIO29_LCD_DD6 MFP_CFG(GPIO29, AF1) -#define GPIO30_LCD_DD7 MFP_CFG(GPIO30, AF1) -#define GPIO31_LCD_DD8 MFP_CFG(GPIO31, AF1) -#define GPIO32_LCD_DD9 MFP_CFG(GPIO32, AF1) -#define GPIO33_LCD_DD10 MFP_CFG(GPIO33, AF1) -#define GPIO34_LCD_DD11 MFP_CFG(GPIO34, AF1) -#define GPIO35_LCD_DD12 MFP_CFG(GPIO35, AF1) -#define GPIO36_LCD_DD13 MFP_CFG(GPIO36, AF1) -#define GPIO37_LCD_DD14 MFP_CFG(GPIO37, AF1) -#define GPIO38_LCD_DD15 MFP_CFG(GPIO38, AF1) -#define GPIO39_LCD_DD16 MFP_CFG(GPIO39, AF1) -#define GPIO40_LCD_DD17 MFP_CFG(GPIO40, AF1) -#define GPIO41_LCD_CS2 MFP_CFG(GPIO41, AF3) -#define GPIO42_LCD_VSYNC2 MFP_CFG(GPIO42, AF3) -#define GPIO44_LCD_DD7 MFP_CFG(GPIO44, AF1) - -/* Mini-LCD */ -#define GPIO17_MLCD_FCLK MFP_CFG(GPIO17, AF3) -#define GPIO18_MLCD_LCLK MFP_CFG(GPIO18, AF3) -#define GPIO19_MLCD_PCLK MFP_CFG(GPIO19, AF3) -#define GPIO20_MLCD_BIAS MFP_CFG(GPIO20, AF3) -#define GPIO23_MLCD_DD0 MFP_CFG(GPIO23, AF3) -#define GPIO24_MLCD_DD1 MFP_CFG(GPIO24, AF3) -#define GPIO25_MLCD_DD2 MFP_CFG(GPIO25, AF3) -#define GPIO26_MLCD_DD3 MFP_CFG(GPIO26, AF3) -#define GPIO27_MLCD_DD4 MFP_CFG(GPIO27, AF3) -#define GPIO28_MLCD_DD5 MFP_CFG(GPIO28, AF3) -#define GPIO29_MLCD_DD6 MFP_CFG(GPIO29, AF3) -#define GPIO30_MLCD_DD7 MFP_CFG(GPIO30, AF3) -#define GPIO31_MLCD_DD8 MFP_CFG(GPIO31, AF3) -#define GPIO32_MLCD_DD9 MFP_CFG(GPIO32, AF3) -#define GPIO33_MLCD_DD10 MFP_CFG(GPIO33, AF3) -#define GPIO34_MLCD_DD11 MFP_CFG(GPIO34, AF3) -#define GPIO35_MLCD_DD12 MFP_CFG(GPIO35, AF3) -#define GPIO36_MLCD_DD13 MFP_CFG(GPIO36, AF3) -#define GPIO37_MLCD_DD14 MFP_CFG(GPIO37, AF3) -#define GPIO38_MLCD_DD15 MFP_CFG(GPIO38, AF3) -#define GPIO44_MLCD_DD7 MFP_CFG(GPIO44, AF5) - -/* MMC1 */ -#define GPIO10_MMC1_DAT3 MFP_CFG(GPIO10, AF4) -#define GPIO11_MMC1_DAT2 MFP_CFG(GPIO11, AF4) -#define GPIO12_MMC1_DAT1 MFP_CFG(GPIO12, AF4) -#define GPIO13_MMC1_DAT0 MFP_CFG(GPIO13, AF4) -#define GPIO14_MMC1_CMD MFP_CFG(GPIO14, AF4) -#define GPIO15_MMC1_CLK MFP_CFG(GPIO15, AF4) -#define GPIO55_MMC1_CMD MFP_CFG(GPIO55, AF3) -#define GPIO56_MMC1_CLK MFP_CFG(GPIO56, AF3) -#define GPIO57_MMC1_DAT0 MFP_CFG(GPIO57, AF3) -#define GPIO58_MMC1_DAT1 MFP_CFG(GPIO58, AF3) -#define GPIO59_MMC1_DAT2 MFP_CFG(GPIO59, AF3) -#define GPIO60_MMC1_DAT3 MFP_CFG(GPIO60, AF3) - -#define DF_ADDR0_MMC1_CLK MFP_CFG(DF_ADDR0, AF2) -#define DF_ADDR1_MMC1_CMD MFP_CFG(DF_ADDR1, AF2) -#define DF_ADDR2_MMC1_DAT0 MFP_CFG(DF_ADDR2, AF2) -#define DF_ADDR3_MMC1_DAT1 MFP_CFG(DF_ADDR3, AF3) -#define nXCVREN_MMC1_DAT2 MFP_CFG(nXCVREN, AF2) - -/* MMC2 */ -#define GPIO31_MMC2_CMD MFP_CFG(GPIO31, AF7) -#define GPIO32_MMC2_CLK MFP_CFG(GPIO32, AF7) -#define GPIO33_MMC2_DAT0 MFP_CFG(GPIO33, AF7) -#define GPIO34_MMC2_DAT1 MFP_CFG(GPIO34, AF7) -#define GPIO35_MMC2_DAT2 MFP_CFG(GPIO35, AF7) -#define GPIO36_MMC2_DAT3 MFP_CFG(GPIO36, AF7) - -#define GPIO101_MMC2_DAT3 MFP_CFG(GPIO101, AF1) -#define GPIO102_MMC2_DAT2 MFP_CFG(GPIO102, AF1) -#define GPIO103_MMC2_DAT1 MFP_CFG(GPIO103, AF1) -#define GPIO104_MMC2_DAT0 MFP_CFG(GPIO104, AF1) -#define GPIO105_MMC2_CMD MFP_CFG(GPIO105, AF1) -#define GPIO106_MMC2_CLK MFP_CFG(GPIO106, AF1) - -#define DF_IO10_MMC2_DAT3 MFP_CFG(DF_IO10, AF3) -#define DF_IO11_MMC2_DAT2 MFP_CFG(DF_IO11, AF3) -#define DF_IO12_MMC2_DAT1 MFP_CFG(DF_IO12, AF3) -#define DF_IO13_MMC2_DAT0 MFP_CFG(DF_IO13, AF3) -#define DF_IO14_MMC2_CLK MFP_CFG(DF_IO14, AF3) -#define DF_IO15_MMC2_CMD MFP_CFG(DF_IO15, AF3) - -/* BSSP1 */ -#define GPIO12_BSSP1_CLK MFP_CFG(GPIO12, AF3) -#define GPIO13_BSSP1_FRM MFP_CFG(GPIO13, AF3) -#define GPIO14_BSSP1_RXD MFP_CFG(GPIO14, AF3) -#define GPIO15_BSSP1_TXD MFP_CFG(GPIO15, AF3) -#define GPIO97_BSSP1_CLK MFP_CFG(GPIO97, AF5) -#define GPIO98_BSSP1_FRM MFP_CFG(GPIO98, AF5) - -/* BSSP2 */ -#define GPIO84_BSSP2_SDATA_IN MFP_CFG(GPIO84, AF1) -#define GPIO85_BSSP2_BITCLK MFP_CFG(GPIO85, AF1) -#define GPIO86_BSSP2_SYSCLK MFP_CFG(GPIO86, AF1) -#define GPIO87_BSSP2_SYNC MFP_CFG(GPIO87, AF1) -#define GPIO88_BSSP2_DATA_OUT MFP_CFG(GPIO88, AF1) -#define GPIO86_BSSP2_SDATA_IN MFP_CFG(GPIO86, AF4) - -/* BSSP3 */ -#define GPIO79_BSSP3_CLK MFP_CFG(GPIO79, AF1) -#define GPIO80_BSSP3_FRM MFP_CFG(GPIO80, AF1) -#define GPIO81_BSSP3_TXD MFP_CFG(GPIO81, AF1) -#define GPIO82_BSSP3_RXD MFP_CFG(GPIO82, AF1) -#define GPIO83_BSSP3_SYSCLK MFP_CFG(GPIO83, AF1) - -/* BSSP4 */ -#define GPIO43_BSSP4_CLK MFP_CFG(GPIO43, AF4) -#define GPIO44_BSSP4_FRM MFP_CFG(GPIO44, AF4) -#define GPIO45_BSSP4_TXD MFP_CFG(GPIO45, AF4) -#define GPIO46_BSSP4_RXD MFP_CFG(GPIO46, AF4) - -#define GPIO51_BSSP4_CLK MFP_CFG(GPIO51, AF4) -#define GPIO52_BSSP4_FRM MFP_CFG(GPIO52, AF4) -#define GPIO53_BSSP4_TXD MFP_CFG(GPIO53, AF4) -#define GPIO54_BSSP4_RXD MFP_CFG(GPIO54, AF4) - -/* GSSP1 */ -#define GPIO79_GSSP1_CLK MFP_CFG(GPIO79, AF2) -#define GPIO80_GSSP1_FRM MFP_CFG(GPIO80, AF2) -#define GPIO81_GSSP1_TXD MFP_CFG(GPIO81, AF2) -#define GPIO82_GSSP1_RXD MFP_CFG(GPIO82, AF2) -#define GPIO83_GSSP1_SYSCLK MFP_CFG(GPIO83, AF2) - -#define GPIO93_GSSP1_CLK MFP_CFG(GPIO93, AF4) -#define GPIO94_GSSP1_FRM MFP_CFG(GPIO94, AF4) -#define GPIO95_GSSP1_TXD MFP_CFG(GPIO95, AF4) -#define GPIO96_GSSP1_RXD MFP_CFG(GPIO96, AF4) - -/* GSSP2 */ -#define GPIO47_GSSP2_CLK MFP_CFG(GPIO47, AF4) -#define GPIO48_GSSP2_FRM MFP_CFG(GPIO48, AF4) -#define GPIO49_GSSP2_RXD MFP_CFG(GPIO49, AF4) -#define GPIO50_GSSP2_TXD MFP_CFG(GPIO50, AF4) - -#define GPIO69_GSSP2_CLK MFP_CFG(GPIO69, AF4) -#define GPIO70_GSSP2_FRM MFP_CFG(GPIO70, AF4) -#define GPIO71_GSSP2_RXD MFP_CFG(GPIO71, AF4) -#define GPIO72_GSSP2_TXD MFP_CFG(GPIO72, AF4) - -#define GPIO84_GSSP2_RXD MFP_CFG(GPIO84, AF2) -#define GPIO85_GSSP2_CLK MFP_CFG(GPIO85, AF2) -#define GPIO86_GSSP2_SYSCLK MFP_CFG(GPIO86, AF2) -#define GPIO87_GSSP2_FRM MFP_CFG(GPIO87, AF2) -#define GPIO88_GSSP2_TXD MFP_CFG(GPIO88, AF2) -#define GPIO86_GSSP2_RXD MFP_CFG(GPIO86, AF5) - -#define GPIO103_GSSP2_CLK MFP_CFG(GPIO103, AF2) -#define GPIO104_GSSP2_FRM MFP_CFG(GPIO104, AF2) -#define GPIO105_GSSP2_RXD MFP_CFG(GPIO105, AF2) -#define GPIO106_GSSP2_TXD MFP_CFG(GPIO106, AF2) - -/* UART1 - FFUART */ -#define GPIO47_UART1_DSR_N MFP_CFG(GPIO47, AF1) -#define GPIO48_UART1_DTR_N MFP_CFG(GPIO48, AF1) -#define GPIO49_UART1_RI MFP_CFG(GPIO49, AF1) -#define GPIO50_UART1_DCD MFP_CFG(GPIO50, AF1) -#define GPIO51_UART1_CTS MFP_CFG(GPIO51, AF1) -#define GPIO52_UART1_RTS MFP_CFG(GPIO52, AF1) -#define GPIO53_UART1_RXD MFP_CFG(GPIO53, AF1) -#define GPIO54_UART1_TXD MFP_CFG(GPIO54, AF1) - -#define GPIO63_UART1_TXD MFP_CFG(GPIO63, AF2) -#define GPIO64_UART1_RXD MFP_CFG(GPIO64, AF2) -#define GPIO65_UART1_DSR MFP_CFG(GPIO65, AF2) -#define GPIO66_UART1_DTR MFP_CFG(GPIO66, AF2) -#define GPIO67_UART1_RI MFP_CFG(GPIO67, AF2) -#define GPIO68_UART1_DCD MFP_CFG(GPIO68, AF2) -#define GPIO69_UART1_CTS MFP_CFG(GPIO69, AF2) -#define GPIO70_UART1_RTS MFP_CFG(GPIO70, AF2) - -#define GPIO53_UART1_TXD MFP_CFG(GPIO53, AF2) -#define GPIO54_UART1_RXD MFP_CFG(GPIO54, AF2) - -/* UART2 - BTUART */ -#define GPIO91_UART2_RXD MFP_CFG(GPIO91, AF1) -#define GPIO92_UART2_TXD MFP_CFG(GPIO92, AF1) -#define GPIO93_UART2_CTS MFP_CFG(GPIO93, AF1) -#define GPIO94_UART2_RTS MFP_CFG(GPIO94, AF1) - -/* UART3 - STUART */ -#define GPIO43_UART3_RTS MFP_CFG(GPIO43, AF3) -#define GPIO44_UART3_CTS MFP_CFG(GPIO44, AF3) -#define GPIO45_UART3_RXD MFP_CFG(GPIO45, AF3) -#define GPIO46_UART3_TXD MFP_CFG(GPIO46, AF3) - -#define GPIO75_UART3_RTS MFP_CFG(GPIO75, AF5) -#define GPIO76_UART3_CTS MFP_CFG(GPIO76, AF5) -#define GPIO77_UART3_TXD MFP_CFG(GPIO77, AF5) -#define GPIO78_UART3_RXD MFP_CFG(GPIO78, AF5) - -/* DFI */ -#define DF_IO0_DF_IO0 MFP_CFG(DF_IO0, AF2) -#define DF_IO1_DF_IO1 MFP_CFG(DF_IO1, AF2) -#define DF_IO2_DF_IO2 MFP_CFG(DF_IO2, AF2) -#define DF_IO3_DF_IO3 MFP_CFG(DF_IO3, AF2) -#define DF_IO4_DF_IO4 MFP_CFG(DF_IO4, AF2) -#define DF_IO5_DF_IO5 MFP_CFG(DF_IO5, AF2) -#define DF_IO6_DF_IO6 MFP_CFG(DF_IO6, AF2) -#define DF_IO7_DF_IO7 MFP_CFG(DF_IO7, AF2) -#define DF_IO8_DF_IO8 MFP_CFG(DF_IO8, AF2) -#define DF_IO9_DF_IO9 MFP_CFG(DF_IO9, AF2) -#define DF_IO10_DF_IO10 MFP_CFG(DF_IO10, AF2) -#define DF_IO11_DF_IO11 MFP_CFG(DF_IO11, AF2) -#define DF_IO12_DF_IO12 MFP_CFG(DF_IO12, AF2) -#define DF_IO13_DF_IO13 MFP_CFG(DF_IO13, AF2) -#define DF_IO14_DF_IO14 MFP_CFG(DF_IO14, AF2) -#define DF_IO15_DF_IO15 MFP_CFG(DF_IO15, AF2) -#define DF_nADV1_ALE_DF_nADV1 MFP_CFG(DF_nADV1_ALE, AF2) -#define DF_nADV2_ALE_DF_nADV2 MFP_CFG(DF_nADV2_ALE, AF2) -#define DF_nCS0_DF_nCS0 MFP_CFG(DF_nCS0, AF2) -#define DF_nCS1_DF_nCS1 MFP_CFG(DF_nCS1, AF2) -#define DF_nRE_nOE_DF_nOE MFP_CFG(DF_nRE_nOE, AF2) -#define DF_nWE_DF_nWE MFP_CFG(DF_nWE, AF2) - -/* DFI - NAND */ -#define DF_CLE_nOE_ND_CLE MFP_CFG_LPM(DF_CLE_nOE, AF1, PULL_HIGH) -#define DF_INT_RnB_ND_INT_RnB MFP_CFG_LPM(DF_INT_RnB, AF1, PULL_LOW) -#define DF_IO0_ND_IO0 MFP_CFG_LPM(DF_IO0, AF1, PULL_LOW) -#define DF_IO1_ND_IO1 MFP_CFG_LPM(DF_IO1, AF1, PULL_LOW) -#define DF_IO2_ND_IO2 MFP_CFG_LPM(DF_IO2, AF1, PULL_LOW) -#define DF_IO3_ND_IO3 MFP_CFG_LPM(DF_IO3, AF1, PULL_LOW) -#define DF_IO4_ND_IO4 MFP_CFG_LPM(DF_IO4, AF1, PULL_LOW) -#define DF_IO5_ND_IO5 MFP_CFG_LPM(DF_IO5, AF1, PULL_LOW) -#define DF_IO6_ND_IO6 MFP_CFG_LPM(DF_IO6, AF1, PULL_LOW) -#define DF_IO7_ND_IO7 MFP_CFG_LPM(DF_IO7, AF1, PULL_LOW) -#define DF_IO8_ND_IO8 MFP_CFG_LPM(DF_IO8, AF1, PULL_LOW) -#define DF_IO9_ND_IO9 MFP_CFG_LPM(DF_IO9, AF1, PULL_LOW) -#define DF_IO10_ND_IO10 MFP_CFG_LPM(DF_IO10, AF1, PULL_LOW) -#define DF_IO11_ND_IO11 MFP_CFG_LPM(DF_IO11, AF1, PULL_LOW) -#define DF_IO12_ND_IO12 MFP_CFG_LPM(DF_IO12, AF1, PULL_LOW) -#define DF_IO13_ND_IO13 MFP_CFG_LPM(DF_IO13, AF1, PULL_LOW) -#define DF_IO14_ND_IO14 MFP_CFG_LPM(DF_IO14, AF1, PULL_LOW) -#define DF_IO15_ND_IO15 MFP_CFG_LPM(DF_IO15, AF1, PULL_LOW) -#define DF_nADV1_ALE_ND_ALE MFP_CFG_LPM(DF_nADV1_ALE, AF1, PULL_HIGH) -#define DF_nADV2_ALE_ND_ALE MFP_CFG_LPM(DF_nADV2_ALE, AF1, PULL_HIGH) -#define DF_nADV2_ALE_nCS3 MFP_CFG_LPM(DF_nADV2_ALE, AF3, PULL_HIGH) -#define DF_nCS0_ND_nCS0 MFP_CFG_LPM(DF_nCS0, AF1, PULL_HIGH) -#define DF_nCS1_ND_nCS1 MFP_CFG_LPM(DF_nCS1, AF1, PULL_HIGH) -#define DF_nRE_nOE_ND_nRE MFP_CFG_LPM(DF_nRE_nOE, AF1, PULL_HIGH) -#define DF_nWE_ND_nWE MFP_CFG_LPM(DF_nWE, AF1, PULL_HIGH) - -/* PWM */ -#define GPIO41_PWM0 MFP_CFG_LPM(GPIO41, AF1, PULL_LOW) -#define GPIO42_PWM1 MFP_CFG_LPM(GPIO42, AF1, PULL_LOW) -#define GPIO43_PWM3 MFP_CFG_LPM(GPIO43, AF1, PULL_LOW) -#define GPIO20_PWM0 MFP_CFG_LPM(GPIO20, AF2, PULL_LOW) -#define GPIO21_PWM2 MFP_CFG_LPM(GPIO21, AF3, PULL_LOW) -#define GPIO22_PWM3 MFP_CFG_LPM(GPIO22, AF3, PULL_LOW) -#define GPIO32_PWM0 MFP_CFG_LPM(GPIO32, AF4, PULL_LOW) - -/* CIR */ -#define GPIO46_CIR_OUT MFP_CFG(GPIO46, AF1) -#define GPIO77_CIR_OUT MFP_CFG(GPIO77, AF3) - -/* USB P2 */ -#define GPIO0_USB_P2_7 MFP_CFG(GPIO0, AF3) -#define GPIO15_USB_P2_7 MFP_CFG(GPIO15, AF5) -#define GPIO16_USB_P2_7 MFP_CFG(GPIO16, AF2) -#define GPIO48_USB_P2_7 MFP_CFG(GPIO48, AF7) -#define GPIO49_USB_P2_7 MFP_CFG(GPIO49, AF6) -#define DF_IO9_USB_P2_7 MFP_CFG(DF_IO9, AF3) - -#define GPIO48_USB_P2_8 MFP_CFG(GPIO48, AF2) -#define GPIO50_USB_P2_7 MFP_CFG_X(GPIO50, AF2, DS02X, FLOAT) -#define GPIO51_USB_P2_5 MFP_CFG(GPIO51, AF2) -#define GPIO47_USB_P2_4 MFP_CFG(GPIO47, AF2) -#define GPIO53_USB_P2_3 MFP_CFG(GPIO53, AF2) -#define GPIO54_USB_P2_6 MFP_CFG(GPIO54, AF2) -#define GPIO49_USB_P2_2 MFP_CFG(GPIO49, AF2) -#define GPIO52_USB_P2_1 MFP_CFG(GPIO52, AF2) - -#define GPIO63_USB_P2_8 MFP_CFG(GPIO63, AF3) -#define GPIO64_USB_P2_7 MFP_CFG(GPIO64, AF3) -#define GPIO65_USB_P2_6 MFP_CFG(GPIO65, AF3) -#define GPIO66_USG_P2_5 MFP_CFG(GPIO66, AF3) -#define GPIO67_USB_P2_4 MFP_CFG(GPIO67, AF3) -#define GPIO68_USB_P2_3 MFP_CFG(GPIO68, AF3) -#define GPIO69_USB_P2_2 MFP_CFG(GPIO69, AF3) -#define GPIO70_USB_P2_1 MFP_CFG(GPIO70, AF3) - -/* ULPI */ -#define GPIO31_USB_ULPI_D0 MFP_CFG(GPIO31, AF4) -#define GPIO30_USB_ULPI_D1 MFP_CFG(GPIO30, AF7) -#define GPIO33_USB_ULPI_D2 MFP_CFG(GPIO33, AF5) -#define GPIO34_USB_ULPI_D3 MFP_CFG(GPIO34, AF5) -#define GPIO35_USB_ULPI_D4 MFP_CFG(GPIO35, AF5) -#define GPIO36_USB_ULPI_D5 MFP_CFG(GPIO36, AF5) -#define GPIO41_USB_ULPI_D6 MFP_CFG(GPIO41, AF5) -#define GPIO42_USB_ULPI_D7 MFP_CFG(GPIO42, AF5) -#define GPIO37_USB_ULPI_DIR MFP_CFG(GPIO37, AF4) -#define GPIO38_USB_ULPI_CLK MFP_CFG(GPIO38, AF4) -#define GPIO39_USB_ULPI_STP MFP_CFG(GPIO39, AF4) -#define GPIO40_USB_ULPI_NXT MFP_CFG(GPIO40, AF4) - -#define GPIO3_CLK26MOUTDMD MFP_CFG(GPIO3, AF3) -#define GPIO40_CLK26MOUTDMD MFP_CFG(GPIO40, AF7) -#define GPIO94_CLK26MOUTDMD MFP_CFG(GPIO94, AF5) -#define GPIO104_CLK26MOUTDMD MFP_CFG(GPIO104, AF4) -#define DF_ADDR1_CLK26MOUTDMD MFP_CFG(DF_ADDR2, AF3) -#define DF_ADDR3_CLK26MOUTDMD MFP_CFG(DF_ADDR3, AF3) - -#define GPIO14_CLK26MOUT MFP_CFG(GPIO14, AF5) -#define GPIO38_CLK26MOUT MFP_CFG(GPIO38, AF7) -#define GPIO92_CLK26MOUT MFP_CFG(GPIO92, AF5) -#define GPIO105_CLK26MOUT MFP_CFG(GPIO105, AF4) - -#define GPIO2_CLK13MOUTDMD MFP_CFG(GPIO2, AF3) -#define GPIO39_CLK13MOUTDMD MFP_CFG(GPIO39, AF7) -#define GPIO50_CLK13MOUTDMD MFP_CFG(GPIO50, AF3) -#define GPIO93_CLK13MOUTDMD MFP_CFG(GPIO93, AF5) -#define GPIO103_CLK13MOUTDMD MFP_CFG(GPIO103, AF4) -#define DF_ADDR2_CLK13MOUTDMD MFP_CFG(DF_ADDR2, AF3) - -/* 1 wire */ -#define GPIO95_OW_DQ_IN MFP_CFG(GPIO95, AF5) - -#endif /* __ASM_ARCH_MFP_PXA9xx_H */ diff --git a/arch/arm/mach-pxa/include/mach/mioa701.h b/arch/arm/mach-pxa/include/mach/mioa701.h deleted file mode 100644 index e57f5c724e8a..000000000000 --- a/arch/arm/mach-pxa/include/mach/mioa701.h +++ /dev/null @@ -1,75 +0,0 @@ -#ifndef _MIOA701_H_ -#define _MIOA701_H_ - -#define MIO_CFG_IN(pin, af) \ - ((MFP_CFG_DEFAULT & ~(MFP_AF_MASK | MFP_DIR_MASK)) |\ - (MFP_PIN(pin) | MFP_##af | MFP_DIR_IN)) - -#define MIO_CFG_OUT(pin, af, state) \ - ((MFP_CFG_DEFAULT & ~(MFP_AF_MASK | MFP_DIR_MASK | MFP_LPM_STATE_MASK)) |\ - (MFP_PIN(pin) | MFP_##af | MFP_DIR_OUT | MFP_LPM_##state)) - -/* Global GPIOs */ -#define GPIO9_CHARGE_EN 9 -#define GPIO18_POWEROFF 18 -#define GPIO87_LCD_POWER 87 -#define GPIO96_AC_DETECT 96 -#define GPIO80_MAYBE_CHARGE_VDROP 80 /* Drop of 88mV */ - -/* USB */ -#define GPIO13_nUSB_DETECT 13 -#define GPIO22_USB_ENABLE 22 - -/* SDIO bits */ -#define GPIO78_SDIO_RO 78 -#define GPIO15_SDIO_INSERT 15 -#define GPIO91_SDIO_EN 91 - -/* Bluetooth */ -#define GPIO14_BT_nACTIVITY 14 -#define GPIO83_BT_ON 83 -#define GPIO77_BT_UNKNOWN1 77 -#define GPIO86_BT_MAYBE_nRESET 86 - -/* GPS */ -#define GPIO23_GPS_UNKNOWN1 23 -#define GPIO26_GPS_ON 26 -#define GPIO27_GPS_RESET 27 -#define GPIO106_GPS_UNKNOWN2 106 -#define GPIO107_GPS_UNKNOWN3 107 - -/* GSM */ -#define GPIO24_GSM_MOD_RESET_CMD 24 -#define GPIO88_GSM_nMOD_ON_CMD 88 -#define GPIO90_GSM_nMOD_OFF_CMD 90 -#define GPIO114_GSM_nMOD_DTE_UART_STATE 114 -#define GPIO25_GSM_MOD_ON_STATE 25 -#define GPIO113_GSM_EVENT 113 - -/* SOUND */ -#define GPIO12_HPJACK_INSERT 12 - -/* LEDS */ -#define GPIO10_LED_nCharging 10 -#define GPIO97_LED_nBlue 97 -#define GPIO98_LED_nOrange 98 -#define GPIO82_LED_nVibra 82 -#define GPIO115_LED_nKeyboard 115 - -/* Keyboard */ -#define GPIO0_KEY_POWER 0 -#define GPIO93_KEY_VOLUME_UP 93 -#define GPIO94_KEY_VOLUME_DOWN 94 - -/* Camera */ -#define GPIO56_MT9M111_nOE 56 - -extern struct input_dev *mioa701_evdev; -extern void mioa701_gpio_lpm_set(unsigned long mfp_pin); - -/* Assembler externals mioa701_bootresume.S */ -extern u32 mioa701_bootstrap; -extern u32 mioa701_jumpaddr; -extern u32 mioa701_bootstrap_lg; - -#endif /* _MIOA701_H */ diff --git a/arch/arm/mach-pxa/include/mach/mxm8x10.h b/arch/arm/mach-pxa/include/mach/mxm8x10.h deleted file mode 100644 index ffa15665a418..000000000000 --- a/arch/arm/mach-pxa/include/mach/mxm8x10.h +++ /dev/null @@ -1,21 +0,0 @@ -#ifndef __MACH_MXM_8X10_H -#define __MACH_MXM_8X10_H - -#define MXM_8X10_ETH_PHYS 0x13000000 - -#if defined(CONFIG_MMC) - -#define MXM_8X10_SD_nCD (72) -#define MXM_8X10_SD_WP (84) - -extern void mxm_8x10_mmc_init(void); -#else -static inline void mxm_8x10_mmc_init(void) {} -#endif - -extern void mxm_8x10_usb_host_init(void); -extern void mxm_8x10_ac97_init(void); - -extern void mxm_8x10_barebones_init(void); - -#endif /* __MACH_MXM_8X10_H */ diff --git a/arch/arm/mach-pxa/include/mach/palm27x.h b/arch/arm/mach-pxa/include/mach/palm27x.h deleted file mode 100644 index d4eac3d6ffb5..000000000000 --- a/arch/arm/mach-pxa/include/mach/palm27x.h +++ /dev/null @@ -1,81 +0,0 @@ -/* - * Common functions for Palm LD, T5, TX, Z72 - * - * Copyright (C) 2010 - * Marek Vasut - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - */ -#ifndef __INCLUDE_MACH_PALM27X__ -#define __INCLUDE_MACH_PALM27X__ - -#if defined(CONFIG_MMC_PXA) || defined(CONFIG_MMC_PXA_MODULE) -extern void __init palm27x_mmc_init(int detect, int ro, int power, - int power_inverted); -#else -static inline void palm27x_mmc_init(int detect, int ro, int power, - int power_inverted) -{} -#endif - -#if defined(CONFIG_SUSPEND) -extern void __init palm27x_pm_init(unsigned long str_base); -#else -static inline void palm27x_pm_init(unsigned long str_base) {} -#endif - -#if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULE) -extern struct pxafb_mode_info palm_320x480_lcd_mode; -extern struct pxafb_mode_info palm_320x320_lcd_mode; -extern struct pxafb_mode_info palm_320x320_new_lcd_mode; -extern void __init palm27x_lcd_init(int power, - struct pxafb_mode_info *mode); -#else -#define palm27x_lcd_init(power, mode) do {} while (0) -#endif - -#if defined(CONFIG_USB_PXA27X) || \ - defined(CONFIG_USB_PXA27X_MODULE) -extern void __init palm27x_udc_init(int vbus, int pullup, - int vbus_inverted); -#else -static inline void palm27x_udc_init(int vbus, int pullup, int vbus_inverted) {} -#endif - -#if defined(CONFIG_IRDA) || defined(CONFIG_IRDA_MODULE) -extern void __init palm27x_irda_init(int pwdn); -#else -static inline void palm27x_irda_init(int pwdn) {} -#endif - -#if defined(CONFIG_TOUCHSCREEN_WM97XX) || \ - defined(CONFIG_TOUCHSCREEN_WM97XX_MODULE) -extern void __init palm27x_ac97_init(int minv, int maxv, int jack, - int reset); -#else -static inline void palm27x_ac97_init(int minv, int maxv, int jack, int reset) {} -#endif - -#if defined(CONFIG_BACKLIGHT_PWM) || defined(CONFIG_BACKLIGHT_PWM_MODULE) -extern void __init palm27x_pwm_init(int bl, int lcd); -#else -static inline void palm27x_pwm_init(int bl, int lcd) {} -#endif - -#if defined(CONFIG_PDA_POWER) || defined(CONFIG_PDA_POWER_MODULE) -extern void __init palm27x_power_init(int ac, int usb); -#else -static inline void palm27x_power_init(int ac, int usb) {} -#endif - -#if defined(CONFIG_REGULATOR_MAX1586) || \ - defined(CONFIG_REGULATOR_MAX1586_MODULE) -extern void __init palm27x_pmic_init(void); -#else -static inline void palm27x_pmic_init(void) {} -#endif - -#endif /* __INCLUDE_MACH_PALM27X__ */ diff --git a/arch/arm/mach-pxa/include/mach/palmt5.h b/arch/arm/mach-pxa/include/mach/palmt5.h deleted file mode 100644 index e342c5921405..000000000000 --- a/arch/arm/mach-pxa/include/mach/palmt5.h +++ /dev/null @@ -1,86 +0,0 @@ -/* - * GPIOs and interrupts for Palm Tungsten|T5 Handheld Computer - * - * Authors: Ales Snuparek - * Marek Vasut - * Justin Kendrick - * RichardT5 - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - */ - -#ifndef _INCLUDE_PALMT5_H_ -#define _INCLUDE_PALMT5_H_ - -#include "irqs.h" /* PXA_GPIO_TO_IRQ */ - -/** HERE ARE GPIOs **/ - -/* GPIOs */ -#define GPIO_NR_PALMT5_GPIO_RESET 1 - -#define GPIO_NR_PALMT5_POWER_DETECT 90 -#define GPIO_NR_PALMT5_HOTSYNC_BUTTON_N 10 -#define GPIO_NR_PALMT5_EARPHONE_DETECT 107 - -/* SD/MMC */ -#define GPIO_NR_PALMT5_SD_DETECT_N 14 -#define GPIO_NR_PALMT5_SD_POWER 114 -#define GPIO_NR_PALMT5_SD_READONLY 115 - -/* TOUCHSCREEN */ -#define GPIO_NR_PALMT5_WM9712_IRQ 27 - -/* IRDA - disable GPIO connected to SD pin of tranceiver (TFBS4710?) ? */ -#define GPIO_NR_PALMT5_IR_DISABLE 40 - -/* USB */ -#define GPIO_NR_PALMT5_USB_DETECT_N 15 -#define GPIO_NR_PALMT5_USB_PULLUP 93 - -/* LCD/BACKLIGHT */ -#define GPIO_NR_PALMT5_BL_POWER 84 -#define GPIO_NR_PALMT5_LCD_POWER 96 - -/* BLUETOOTH */ -#define GPIO_NR_PALMT5_BT_POWER 17 -#define GPIO_NR_PALMT5_BT_RESET 83 - -/* INTERRUPTS */ -#define IRQ_GPIO_PALMT5_SD_DETECT_N PXA_GPIO_TO_IRQ(GPIO_NR_PALMT5_SD_DETECT_N) -#define IRQ_GPIO_PALMT5_WM9712_IRQ PXA_GPIO_TO_IRQ(GPIO_NR_PALMT5_WM9712_IRQ) -#define IRQ_GPIO_PALMT5_USB_DETECT PXA_GPIO_TO_IRQ(GPIO_NR_PALMT5_USB_DETECT) -#define IRQ_GPIO_PALMT5_GPIO_RESET PXA_GPIO_TO_IRQ(GPIO_NR_PALMT5_GPIO_RESET) - -/** HERE ARE INIT VALUES **/ - -/* Various addresses */ -#define PALMT5_PHYS_RAM_START 0xa0000000 -#define PALMT5_PHYS_IO_START 0x40000000 -#define PALMT5_STR_BASE 0xa0200000 - -/* TOUCHSCREEN */ -#define AC97_LINK_FRAME 21 - -/* BATTERY */ -#define PALMT5_BAT_MAX_VOLTAGE 4000 /* 4.00v current voltage */ -#define PALMT5_BAT_MIN_VOLTAGE 3550 /* 3.55v critical voltage */ -#define PALMT5_BAT_MAX_CURRENT 0 /* unknown */ -#define PALMT5_BAT_MIN_CURRENT 0 /* unknown */ -#define PALMT5_BAT_MAX_CHARGE 1 /* unknown */ -#define PALMT5_BAT_MIN_CHARGE 1 /* unknown */ -#define PALMT5_MAX_LIFE_MINS 360 /* on-life in minutes */ - -#define PALMT5_BAT_MEASURE_DELAY (HZ * 1) - -/* BACKLIGHT */ -#define PALMT5_MAX_INTENSITY 0xFE -#define PALMT5_DEFAULT_INTENSITY 0x7E -#define PALMT5_LIMIT_MASK 0x7F -#define PALMT5_PRESCALER 0x3F -#define PALMT5_PERIOD_NS 3500 - -#endif diff --git a/arch/arm/mach-pxa/include/mach/palmte2.h b/arch/arm/mach-pxa/include/mach/palmte2.h deleted file mode 100644 index f89e989a7637..000000000000 --- a/arch/arm/mach-pxa/include/mach/palmte2.h +++ /dev/null @@ -1,68 +0,0 @@ -/* - * GPIOs and interrupts for Palm Tungsten|E2 Handheld Computer - * - * Author: - * Carlos Eduardo Medaglia Dyonisio - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - */ - -#ifndef _INCLUDE_PALMTE2_H_ -#define _INCLUDE_PALMTE2_H_ - -/** HERE ARE GPIOs **/ - -/* GPIOs */ -#define GPIO_NR_PALMTE2_POWER_DETECT 9 -#define GPIO_NR_PALMTE2_HOTSYNC_BUTTON_N 4 -#define GPIO_NR_PALMTE2_EARPHONE_DETECT 15 - -/* SD/MMC */ -#define GPIO_NR_PALMTE2_SD_DETECT_N 10 -#define GPIO_NR_PALMTE2_SD_POWER 55 -#define GPIO_NR_PALMTE2_SD_READONLY 51 - -/* IRDA - disable GPIO connected to SD pin of tranceiver (TFBS4710?) ? */ -#define GPIO_NR_PALMTE2_IR_DISABLE 48 - -/* USB */ -#define GPIO_NR_PALMTE2_USB_DETECT_N 35 -#define GPIO_NR_PALMTE2_USB_PULLUP 53 - -/* LCD/BACKLIGHT */ -#define GPIO_NR_PALMTE2_BL_POWER 56 -#define GPIO_NR_PALMTE2_LCD_POWER 37 - -/* KEYS */ -#define GPIO_NR_PALMTE2_KEY_NOTES 5 -#define GPIO_NR_PALMTE2_KEY_TASKS 7 -#define GPIO_NR_PALMTE2_KEY_CALENDAR 11 -#define GPIO_NR_PALMTE2_KEY_CONTACTS 13 -#define GPIO_NR_PALMTE2_KEY_CENTER 14 -#define GPIO_NR_PALMTE2_KEY_LEFT 19 -#define GPIO_NR_PALMTE2_KEY_RIGHT 20 -#define GPIO_NR_PALMTE2_KEY_DOWN 21 -#define GPIO_NR_PALMTE2_KEY_UP 22 - -/** HERE ARE INIT VALUES **/ - -/* BACKLIGHT */ -#define PALMTE2_MAX_INTENSITY 0xFE -#define PALMTE2_DEFAULT_INTENSITY 0x7E -#define PALMTE2_LIMIT_MASK 0x7F -#define PALMTE2_PRESCALER 0x3F -#define PALMTE2_PERIOD_NS 3500 - -/* BATTERY */ -#define PALMTE2_BAT_MAX_VOLTAGE 4000 /* 4.00v current voltage */ -#define PALMTE2_BAT_MIN_VOLTAGE 3550 /* 3.55v critical voltage */ -#define PALMTE2_BAT_MAX_CURRENT 0 /* unknown */ -#define PALMTE2_BAT_MIN_CURRENT 0 /* unknown */ -#define PALMTE2_BAT_MAX_CHARGE 1 /* unknown */ -#define PALMTE2_BAT_MIN_CHARGE 1 /* unknown */ -#define PALMTE2_MAX_LIFE_MINS 360 /* on-life in minutes */ - -#endif diff --git a/arch/arm/mach-pxa/include/mach/palmtreo.h b/arch/arm/mach-pxa/include/mach/palmtreo.h deleted file mode 100644 index 714b6574393e..000000000000 --- a/arch/arm/mach-pxa/include/mach/palmtreo.h +++ /dev/null @@ -1,68 +0,0 @@ -/* - * GPIOs and interrupts for Palm Treo smartphones - * - * currently supported: - * Palm Treo 680 (GSM) - * Palm Centro 685 (GSM) - * - * Author: Tomas Cech - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * find more info at www.hackndev.com - * - */ - -#ifndef _INCLUDE_TREO_H_ -#define _INCLUDE_TREO_H_ - -/* GPIOs */ -#define GPIO_NR_TREO_POWER_DETECT 0 -#define GPIO_NR_TREO_AMP_EN 27 -#define GPIO_NR_TREO_GREEN_LED 20 -#define GPIO_NR_TREO_RED_LED 79 -#define GPIO_NR_TREO_SD_DETECT_N 113 -#define GPIO_NR_TREO_EP_DETECT_N 116 -#define GPIO_NR_TREO_USB_DETECT 1 -#define GPIO_NR_TREO_USB_PULLUP 114 -#define GPIO_NR_TREO_GSM_POWER 40 -#define GPIO_NR_TREO_GSM_RESET 87 -#define GPIO_NR_TREO_GSM_WAKE 57 -#define GPIO_NR_TREO_GSM_HOST_WAKE 14 -#define GPIO_NR_TREO_GSM_TRIGGER 10 -#define GPIO_NR_TREO_IR_EN 115 -#define GPIO_NR_TREO_IR_TXD 47 -#define GPIO_NR_TREO_BL_POWER 38 -#define GPIO_NR_TREO_LCD_POWER 25 - -/* Treo680 specific GPIOs */ -#define GPIO_NR_TREO680_SD_READONLY 33 -#define GPIO_NR_TREO680_SD_POWER 42 -#define GPIO_NR_TREO680_VIBRATE_EN 44 -#define GPIO_NR_TREO680_KEYB_BL 24 -#define GPIO_NR_TREO680_BT_EN 43 -#define GPIO_NR_TREO680_LCD_POWER 77 -#define GPIO_NR_TREO680_LCD_EN 86 -#define GPIO_NR_TREO680_LCD_EN_N 25 - -/* Centro685 specific GPIOs */ -#define GPIO_NR_CENTRO_SD_POWER 21 -#define GPIO_NR_CENTRO_VIBRATE_EN 22 -#define GPIO_NR_CENTRO_KEYB_BL 33 -#define GPIO_NR_CENTRO_BT_EN 80 - -/* Various addresses */ -#define TREO_PHYS_RAM_START 0xa0000000 -#define TREO_PHYS_IO_START 0x40000000 -#define TREO_STR_BASE 0xa2000000 - -/* BACKLIGHT */ -#define TREO_MAX_INTENSITY 254 -#define TREO_DEFAULT_INTENSITY 160 -#define TREO_LIMIT_MASK 0x7F -#define TREO_PRESCALER 63 -#define TREO_PERIOD_NS 3500 - -#endif diff --git a/arch/arm/mach-pxa/include/mach/palmz72.h b/arch/arm/mach-pxa/include/mach/palmz72.h deleted file mode 100644 index 0d4700a79612..000000000000 --- a/arch/arm/mach-pxa/include/mach/palmz72.h +++ /dev/null @@ -1,84 +0,0 @@ -/* - * GPIOs and interrupts for Palm Zire72 Handheld Computer - * - * Authors: Alex Osborne - * Jan Herman <2hp@seznam.cz> - * Sergey Lapin - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - */ - -#ifndef _INCLUDE_PALMZ72_H_ -#define _INCLUDE_PALMZ72_H_ - -/* Power and control */ -#define GPIO_NR_PALMZ72_GPIO_RESET 1 -#define GPIO_NR_PALMZ72_POWER_DETECT 0 - -/* SD/MMC */ -#define GPIO_NR_PALMZ72_SD_DETECT_N 14 -#define GPIO_NR_PALMZ72_SD_POWER_N 98 -#define GPIO_NR_PALMZ72_SD_RO 115 - -/* Touchscreen */ -#define GPIO_NR_PALMZ72_WM9712_IRQ 27 - -/* IRDA - disable GPIO connected to SD pin of tranceiver (TFBS4710?) ? */ -#define GPIO_NR_PALMZ72_IR_DISABLE 49 - -/* USB */ -#define GPIO_NR_PALMZ72_USB_DETECT_N 15 -#define GPIO_NR_PALMZ72_USB_PULLUP 95 - -/* LCD/Backlight */ -#define GPIO_NR_PALMZ72_BL_POWER 20 -#define GPIO_NR_PALMZ72_LCD_POWER 96 - -/* LED */ -#define GPIO_NR_PALMZ72_LED_GREEN 88 - -/* Bluetooth */ -#define GPIO_NR_PALMZ72_BT_POWER 17 -#define GPIO_NR_PALMZ72_BT_RESET 83 - -/* Camera */ -#define GPIO_NR_PALMZ72_CAM_PWDN 56 -#define GPIO_NR_PALMZ72_CAM_RESET 57 -#define GPIO_NR_PALMZ72_CAM_POWER 91 - -/** Initial values **/ - -/* Battery */ -#define PALMZ72_BAT_MAX_VOLTAGE 4000 /* 4.00v current voltage */ -#define PALMZ72_BAT_MIN_VOLTAGE 3550 /* 3.55v critical voltage */ -#define PALMZ72_BAT_MAX_CURRENT 0 /* unknown */ -#define PALMZ72_BAT_MIN_CURRENT 0 /* unknown */ -#define PALMZ72_BAT_MAX_CHARGE 1 /* unknown */ -#define PALMZ72_BAT_MIN_CHARGE 1 /* unknown */ -#define PALMZ72_MAX_LIFE_MINS 360 /* on-life in minutes */ - -/* Backlight */ -#define PALMZ72_MAX_INTENSITY 0xFE -#define PALMZ72_DEFAULT_INTENSITY 0x7E -#define PALMZ72_LIMIT_MASK 0x7F -#define PALMZ72_PRESCALER 0x3F -#define PALMZ72_PERIOD_NS 3500 - -#ifdef CONFIG_PM -struct palmz72_resume_info { - u32 magic0; /* 0x0 */ - u32 magic1; /* 0x4 */ - u32 resume_addr; /* 0x8 */ - u32 pad[11]; /* 0xc..0x37 */ - u32 arm_control; /* 0x38 */ - u32 aux_control; /* 0x3c */ - u32 ttb; /* 0x40 */ - u32 domain_access; /* 0x44 */ - u32 process_id; /* 0x48 */ -}; -#endif -#endif - diff --git a/arch/arm/mach-pxa/include/mach/pcm027.h b/arch/arm/mach-pxa/include/mach/pcm027.h deleted file mode 100644 index 86ebd7b6c960..000000000000 --- a/arch/arm/mach-pxa/include/mach/pcm027.h +++ /dev/null @@ -1,86 +0,0 @@ -/* - * arch/arm/mach-pxa/include/mach/pcm027.h - * - * (c) 2003 Phytec Messtechnik GmbH - * (c) 2007 Juergen Beisert - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - -/* - * Definitions of CPU card resources only - */ - -#include "irqs.h" /* PXA_GPIO_TO_IRQ */ - -/* phyCORE-PXA270 (PCM027) Interrupts */ -#define PCM027_IRQ(x) (IRQ_BOARD_START + (x)) -#define PCM027_BTDET_IRQ PCM027_IRQ(0) -#define PCM027_FF_RI_IRQ PCM027_IRQ(1) -#define PCM027_MMCDET_IRQ PCM027_IRQ(2) -#define PCM027_PM_5V_IRQ PCM027_IRQ(3) - -#define PCM027_NR_IRQS (IRQ_BOARD_START + 32) - -/* I2C RTC */ -#define PCM027_RTC_IRQ_GPIO 0 -#define PCM027_RTC_IRQ PXA_GPIO_TO_IRQ(PCM027_RTC_IRQ_GPIO) -#define PCM027_RTC_IRQ_EDGE IRQ_TYPE_EDGE_FALLING -#define ADR_PCM027_RTC 0x51 /* I2C address */ - -/* I2C EEPROM */ -#define ADR_PCM027_EEPROM 0x54 /* I2C address */ - -/* Ethernet chip (SMSC91C111) */ -#define PCM027_ETH_IRQ_GPIO 52 -#define PCM027_ETH_IRQ PXA_GPIO_TO_IRQ(PCM027_ETH_IRQ_GPIO) -#define PCM027_ETH_IRQ_EDGE IRQ_TYPE_EDGE_RISING -#define PCM027_ETH_PHYS PXA_CS5_PHYS -#define PCM027_ETH_SIZE (1*1024*1024) - -/* CAN controller SJA1000 (unsupported yet) */ -#define PCM027_CAN_IRQ_GPIO 114 -#define PCM027_CAN_IRQ PXA_GPIO_TO_IRQ(PCM027_CAN_IRQ_GPIO) -#define PCM027_CAN_IRQ_EDGE IRQ_TYPE_EDGE_FALLING -#define PCM027_CAN_PHYS 0x22000000 -#define PCM027_CAN_SIZE 0x100 - -/* SPI GPIO expander (unsupported yet) */ -#define PCM027_EGPIO_IRQ_GPIO 27 -#define PCM027_EGPIO_IRQ PXA_GPIO_TO_IRQ(PCM027_EGPIO_IRQ_GPIO) -#define PCM027_EGPIO_IRQ_EDGE IRQ_TYPE_EDGE_FALLING -#define PCM027_EGPIO_CS 24 -/* - * TODO: Switch this pin from dedicated usage to GPIO if - * more than the MAX7301 device is connected to this SPI bus - */ -#define PCM027_EGPIO_CS_MODE GPIO24_SFRM_MD - -/* Flash memory */ -#define PCM027_FLASH_PHYS 0x00000000 -#define PCM027_FLASH_SIZE 0x02000000 - -/* onboard LEDs connected to GPIO */ -#define PCM027_LED_CPU 90 -#define PCM027_LED_HEARD_BEAT 91 - -/* - * This CPU module needs a baseboard to work. After basic initializing - * its own devices, it calls baseboard's init function. - * TODO: Add your own basebaord init function and call it from - * inside pcm027_init(). This example here is for the developmen board. - * Refer pcm990-baseboard.c - */ -extern void pcm990_baseboard_init(void); diff --git a/arch/arm/mach-pxa/include/mach/pcm990_baseboard.h b/arch/arm/mach-pxa/include/mach/pcm990_baseboard.h deleted file mode 100644 index 7e544c14967e..000000000000 --- a/arch/arm/mach-pxa/include/mach/pcm990_baseboard.h +++ /dev/null @@ -1,212 +0,0 @@ -/* - * arch/arm/mach-pxa/include/mach/pcm990_baseboard.h - * - * (c) 2003 Phytec Messtechnik GmbH - * (c) 2007 Juergen Beisert - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - -#include -#include "irqs.h" /* PXA_GPIO_TO_IRQ */ - -/* - * definitions relevant only when the PCM-990 - * development base board is in use - */ - -/* CPLD's interrupt controller is connected to PCM-027 GPIO 9 */ -#define PCM990_CTRL_INT_IRQ_GPIO 9 -#define PCM990_CTRL_INT_IRQ PXA_GPIO_TO_IRQ(PCM990_CTRL_INT_IRQ_GPIO) -#define PCM990_CTRL_INT_IRQ_EDGE IRQ_TYPE_EDGE_RISING -#define PCM990_CTRL_PHYS PXA_CS1_PHYS /* 16-Bit */ -#define PCM990_CTRL_SIZE (1*1024*1024) - -#define PCM990_CTRL_PWR_IRQ_GPIO 14 -#define PCM990_CTRL_PWR_IRQ PXA_GPIO_TO_IRQ(PCM990_CTRL_PWR_IRQ_GPIO) -#define PCM990_CTRL_PWR_IRQ_EDGE IRQ_TYPE_EDGE_RISING - -/* visible CPLD (U7) registers */ -#define PCM990_CTRL_REG0 0x0000 /* RESET REGISTER */ -#define PCM990_CTRL_SYSRES 0x0001 /* System RESET REGISTER */ -#define PCM990_CTRL_RESOUT 0x0002 /* RESETOUT Enable REGISTER */ -#define PCM990_CTRL_RESGPIO 0x0004 /* RESETGPIO Enable REGISTER */ - -#define PCM990_CTRL_REG1 0x0002 /* Power REGISTER */ -#define PCM990_CTRL_5VOFF 0x0001 /* Disable 5V Regulators */ -#define PCM990_CTRL_CANPWR 0x0004 /* Enable CANPWR ADUM */ -#define PCM990_CTRL_PM_5V 0x0008 /* Read 5V OK */ - -#define PCM990_CTRL_REG2 0x0004 /* LED REGISTER */ -#define PCM990_CTRL_LEDPWR 0x0001 /* POWER LED enable */ -#define PCM990_CTRL_LEDBAS 0x0002 /* BASIS LED enable */ -#define PCM990_CTRL_LEDUSR 0x0004 /* USER LED enable */ - -#define PCM990_CTRL_REG3 0x0006 /* LCD CTRL REGISTER 3 */ -#define PCM990_CTRL_LCDPWR 0x0001 /* RW LCD Power on */ -#define PCM990_CTRL_LCDON 0x0002 /* RW LCD Latch on */ -#define PCM990_CTRL_LCDPOS1 0x0004 /* RW POS 1 */ -#define PCM990_CTRL_LCDPOS2 0x0008 /* RW POS 2 */ - -#define PCM990_CTRL_REG4 0x0008 /* MMC1 CTRL REGISTER 4 */ -#define PCM990_CTRL_MMC1PWR 0x0001 /* RW MMC1 Power on */ - -#define PCM990_CTRL_REG5 0x000A /* MMC2 CTRL REGISTER 5 */ -#define PCM990_CTRL_MMC2PWR 0x0001 /* RW MMC2 Power on */ -#define PCM990_CTRL_MMC2LED 0x0002 /* RW MMC2 LED */ -#define PCM990_CTRL_MMC2DE 0x0004 /* R MMC2 Card detect */ -#define PCM990_CTRL_MMC2WP 0x0008 /* R MMC2 Card write protect */ - -#define PCM990_CTRL_INTSETCLR 0x000C /* Interrupt Clear REGISTER */ -#define PCM990_CTRL_INTC0 0x0001 /* Clear Reg BT Detect */ -#define PCM990_CTRL_INTC1 0x0002 /* Clear Reg FR RI */ -#define PCM990_CTRL_INTC2 0x0004 /* Clear Reg MMC1 Detect */ -#define PCM990_CTRL_INTC3 0x0008 /* Clear Reg PM_5V off */ - -#define PCM990_CTRL_INTMSKENA 0x000E /* Interrupt Enable REGISTER */ -#define PCM990_CTRL_ENAINT0 0x0001 /* Enable Int BT Detect */ -#define PCM990_CTRL_ENAINT1 0x0002 /* Enable Int FR RI */ -#define PCM990_CTRL_ENAINT2 0x0004 /* Enable Int MMC1 Detect */ -#define PCM990_CTRL_ENAINT3 0x0008 /* Enable Int PM_5V off */ - -#define PCM990_CTRL_REG8 0x0014 /* Uart REGISTER */ -#define PCM990_CTRL_FFSD 0x0001 /* BT Uart Enable */ -#define PCM990_CTRL_BTSD 0x0002 /* FF Uart Enable */ -#define PCM990_CTRL_FFRI 0x0004 /* FF Uart RI detect */ -#define PCM990_CTRL_BTRX 0x0008 /* BT Uart Rx detect */ - -#define PCM990_CTRL_REG9 0x0010 /* AC97 Flash REGISTER */ -#define PCM990_CTRL_FLWP 0x0001 /* pC Flash Write Protect */ -#define PCM990_CTRL_FLDIS 0x0002 /* pC Flash Disable */ -#define PCM990_CTRL_AC97ENA 0x0004 /* Enable AC97 Expansion */ - -#define PCM990_CTRL_REG10 0x0012 /* GPS-REGISTER */ -#define PCM990_CTRL_GPSPWR 0x0004 /* GPS-Modul Power on */ -#define PCM990_CTRL_GPSENA 0x0008 /* GPS-Modul Enable */ - -#define PCM990_CTRL_REG11 0x0014 /* Accu REGISTER */ -#define PCM990_CTRL_ACENA 0x0001 /* Charge Enable */ -#define PCM990_CTRL_ACSEL 0x0002 /* Charge Akku -> DC Enable */ -#define PCM990_CTRL_ACPRES 0x0004 /* DC Present */ -#define PCM990_CTRL_ACALARM 0x0008 /* Error Akku */ - -/* - * IDE - */ -#define PCM990_IDE_IRQ_GPIO 13 -#define PCM990_IDE_IRQ PXA_GPIO_TO_IRQ(PCM990_IDE_IRQ_GPIO) -#define PCM990_IDE_IRQ_EDGE IRQ_TYPE_EDGE_RISING -#define PCM990_IDE_PLD_PHYS 0x20000000 /* 16 bit wide */ -#define PCM990_IDE_PLD_BASE 0xee000000 -#define PCM990_IDE_PLD_SIZE (1*1024*1024) - -/* visible CPLD (U6) registers */ -#define PCM990_IDE_PLD_REG0 0x1000 /* OFFSET IDE REGISTER 0 */ -#define PCM990_IDE_PM5V 0x0004 /* R System VCC_5V */ -#define PCM990_IDE_STBY 0x0008 /* R System StandBy */ - -#define PCM990_IDE_PLD_REG1 0x1002 /* OFFSET IDE REGISTER 1 */ -#define PCM990_IDE_IDEMODE 0x0001 /* R TrueIDE Mode */ -#define PCM990_IDE_DMAENA 0x0004 /* RW DMA Enable */ -#define PCM990_IDE_DMA1_0 0x0008 /* RW 1=DREQ1 0=DREQ0 */ - -#define PCM990_IDE_PLD_REG2 0x1004 /* OFFSET IDE REGISTER 2 */ -#define PCM990_IDE_RESENA 0x0001 /* RW IDE Reset Bit enable */ -#define PCM990_IDE_RES 0x0002 /* RW IDE Reset Bit */ -#define PCM990_IDE_RDY 0x0008 /* RDY */ - -#define PCM990_IDE_PLD_REG3 0x1006 /* OFFSET IDE REGISTER 3 */ -#define PCM990_IDE_IDEOE 0x0001 /* RW Latch on Databus */ -#define PCM990_IDE_IDEON 0x0002 /* RW Latch on Control Address */ -#define PCM990_IDE_IDEIN 0x0004 /* RW Latch on Interrupt usw. */ - -#define PCM990_IDE_PLD_REG4 0x1008 /* OFFSET IDE REGISTER 4 */ -#define PCM990_IDE_PWRENA 0x0001 /* RW IDE Power enable */ -#define PCM990_IDE_5V 0x0002 /* R IDE Power 5V */ -#define PCM990_IDE_PWG 0x0008 /* R IDE Power is on */ - -#define PCM990_IDE_PLD_P2V(x) ((x) - PCM990_IDE_PLD_PHYS + PCM990_IDE_PLD_BASE) -#define PCM990_IDE_PLD_V2P(x) ((x) - PCM990_IDE_PLD_BASE + PCM990_IDE_PLD_PHYS) - -/* - * Compact Flash - */ -#define PCM990_CF_IRQ_GPIO 11 -#define PCM990_CF_IRQ PXA_GPIO_TO_IRQ(PCM990_CF_IRQ_GPIO) -#define PCM990_CF_IRQ_EDGE IRQ_TYPE_EDGE_RISING - -#define PCM990_CF_CD_GPIO 12 -#define PCM990_CF_CD PXA_GPIO_TO_IRQ(PCM990_CF_CD_GPIO) -#define PCM990_CF_CD_EDGE IRQ_TYPE_EDGE_RISING - -#define PCM990_CF_PLD_PHYS 0x30000000 /* 16 bit wide */ - -/* visible CPLD (U6) registers */ -#define PCM990_CF_PLD_REG0 0x1000 /* OFFSET CF REGISTER 0 */ -#define PCM990_CF_REG0_LED 0x0001 /* RW LED on */ -#define PCM990_CF_REG0_BLK 0x0002 /* RW LED flash when access */ -#define PCM990_CF_REG0_PM5V 0x0004 /* R System VCC_5V enable */ -#define PCM990_CF_REG0_STBY 0x0008 /* R System StandBy */ - -#define PCM990_CF_PLD_REG1 0x1002 /* OFFSET CF REGISTER 1 */ -#define PCM990_CF_REG1_IDEMODE 0x0001 /* RW CF card run as TrueIDE */ -#define PCM990_CF_REG1_CF0 0x0002 /* RW CF card at ADDR 0x28000000 */ - -#define PCM990_CF_PLD_REG2 0x1004 /* OFFSET CF REGISTER 2 */ -#define PCM990_CF_REG2_RES 0x0002 /* RW CF RESET BIT */ -#define PCM990_CF_REG2_RDYENA 0x0004 /* RW Enable CF_RDY */ -#define PCM990_CF_REG2_RDY 0x0008 /* R CF_RDY auf PWAIT */ - -#define PCM990_CF_PLD_REG3 0x1006 /* OFFSET CF REGISTER 3 */ -#define PCM990_CF_REG3_CFOE 0x0001 /* RW Latch on Databus */ -#define PCM990_CF_REG3_CFON 0x0002 /* RW Latch on Control Address */ -#define PCM990_CF_REG3_CFIN 0x0004 /* RW Latch on Interrupt usw. */ -#define PCM990_CF_REG3_CFCD 0x0008 /* RW Latch on CD1/2 VS1/2 usw */ - -#define PCM990_CF_PLD_REG4 0x1008 /* OFFSET CF REGISTER 4 */ -#define PCM990_CF_REG4_PWRENA 0x0001 /* RW CF Power on (CD1/2 = "00") */ -#define PCM990_CF_REG4_5_3V 0x0002 /* RW 1 = 5V CF_VCC 0 = 3 V CF_VCC */ -#define PCM990_CF_REG4_3B 0x0004 /* RW 3.0V Backup from VCC (5_3V=0) */ -#define PCM990_CF_REG4_PWG 0x0008 /* R CF-Power is on */ - -#define PCM990_CF_PLD_REG5 0x100A /* OFFSET CF REGISTER 5 */ -#define PCM990_CF_REG5_BVD1 0x0001 /* R CF /BVD1 */ -#define PCM990_CF_REG5_BVD2 0x0002 /* R CF /BVD2 */ -#define PCM990_CF_REG5_VS1 0x0004 /* R CF /VS1 */ -#define PCM990_CF_REG5_VS2 0x0008 /* R CF /VS2 */ - -#define PCM990_CF_PLD_REG6 0x100C /* OFFSET CF REGISTER 6 */ -#define PCM990_CF_REG6_CD1 0x0001 /* R CF Card_Detect1 */ -#define PCM990_CF_REG6_CD2 0x0002 /* R CF Card_Detect2 */ - -/* - * Wolfson AC97 Touch - */ -#define PCM990_AC97_IRQ_GPIO 10 -#define PCM990_AC97_IRQ PXA_GPIO_TO_IRQ(PCM990_AC97_IRQ_GPIO) -#define PCM990_AC97_IRQ_EDGE IRQ_TYPE_EDGE_RISING - -/* - * MMC phyCORE - */ -#define PCM990_MMC0_IRQ_GPIO 9 -#define PCM990_MMC0_IRQ PXA_GPIO_TO_IRQ(PCM990_MMC0_IRQ_GPIO) -#define PCM990_MMC0_IRQ_EDGE IRQ_TYPE_EDGE_FALLING - -/* - * USB phyCore - */ -#define PCM990_USB_OVERCURRENT (88 | GPIO_ALT_FN_1_IN) -#define PCM990_USB_PWR_EN (89 | GPIO_ALT_FN_2_OUT) diff --git a/arch/arm/mach-pxa/include/mach/pm.h b/arch/arm/mach-pxa/include/mach/pm.h deleted file mode 100644 index 51558bcee999..000000000000 --- a/arch/arm/mach-pxa/include/mach/pm.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * Copyright (c) 2005 Richard Purdie - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - */ - -#include - -struct pxa_cpu_pm_fns { - int save_count; - void (*save)(unsigned long *); - void (*restore)(unsigned long *); - int (*valid)(suspend_state_t state); - void (*enter)(suspend_state_t state); - int (*prepare)(void); - void (*finish)(void); -}; - -extern struct pxa_cpu_pm_fns *pxa_cpu_pm_fns; - -/* sleep.S */ -extern int pxa25x_finish_suspend(unsigned long); -extern int pxa27x_finish_suspend(unsigned long); - -extern int pxa_pm_enter(suspend_state_t state); -extern int pxa_pm_prepare(void); -extern void pxa_pm_finish(void); - -/* NOTE: this is for PM debugging on Lubbock, it's really a big - * ugly, but let's keep the crap minimum here, instead of direct - * accessing the LUBBOCK CPLD registers in arch/arm/mach-pxa/pm.c - */ -#ifdef CONFIG_ARCH_LUBBOCK -extern void lubbock_set_hexled(uint32_t value); -#else -#define lubbock_set_hexled(x) -#endif diff --git a/arch/arm/mach-pxa/include/mach/pxa25x.h b/arch/arm/mach-pxa/include/mach/pxa25x.h deleted file mode 100644 index 5a341752e32c..000000000000 --- a/arch/arm/mach-pxa/include/mach/pxa25x.h +++ /dev/null @@ -1,9 +0,0 @@ -#ifndef __MACH_PXA25x_H -#define __MACH_PXA25x_H - -#include -#include -#include -#include - -#endif /* __MACH_PXA25x_H */ diff --git a/arch/arm/mach-pxa/include/mach/pxa27x-udc.h b/arch/arm/mach-pxa/include/mach/pxa27x-udc.h deleted file mode 100644 index 4cf28f670706..000000000000 --- a/arch/arm/mach-pxa/include/mach/pxa27x-udc.h +++ /dev/null @@ -1,257 +0,0 @@ -#ifndef _ASM_ARCH_PXA27X_UDC_H -#define _ASM_ARCH_PXA27X_UDC_H - -#ifdef _ASM_ARCH_PXA25X_UDC_H -#error You cannot include both PXA25x and PXA27x UDC support -#endif - -#define UDCCR __REG(0x40600000) /* UDC Control Register */ -#define UDCCR_OEN (1 << 31) /* On-the-Go Enable */ -#define UDCCR_AALTHNP (1 << 30) /* A-device Alternate Host Negotiation - Protocol Port Support */ -#define UDCCR_AHNP (1 << 29) /* A-device Host Negotiation Protocol - Support */ -#define UDCCR_BHNP (1 << 28) /* B-device Host Negotiation Protocol - Enable */ -#define UDCCR_DWRE (1 << 16) /* Device Remote Wake-up Enable */ -#define UDCCR_ACN (0x03 << 11) /* Active UDC configuration Number */ -#define UDCCR_ACN_S 11 -#define UDCCR_AIN (0x07 << 8) /* Active UDC interface Number */ -#define UDCCR_AIN_S 8 -#define UDCCR_AAISN (0x07 << 5) /* Active UDC Alternate Interface - Setting Number */ -#define UDCCR_AAISN_S 5 -#define UDCCR_SMAC (1 << 4) /* Switch Endpoint Memory to Active - Configuration */ -#define UDCCR_EMCE (1 << 3) /* Endpoint Memory Configuration - Error */ -#define UDCCR_UDR (1 << 2) /* UDC Resume */ -#define UDCCR_UDA (1 << 1) /* UDC Active */ -#define UDCCR_UDE (1 << 0) /* UDC Enable */ - -#define UDCICR0 __REG(0x40600004) /* UDC Interrupt Control Register0 */ -#define UDCICR1 __REG(0x40600008) /* UDC Interrupt Control Register1 */ -#define UDCICR_FIFOERR (1 << 1) /* FIFO Error interrupt for EP */ -#define UDCICR_PKTCOMPL (1 << 0) /* Packet Complete interrupt for EP */ - -#define UDC_INT_FIFOERROR (0x2) -#define UDC_INT_PACKETCMP (0x1) - -#define UDCICR_INT(n,intr) (((intr) & 0x03) << (((n) & 0x0F) * 2)) -#define UDCICR1_IECC (1 << 31) /* IntEn - Configuration Change */ -#define UDCICR1_IESOF (1 << 30) /* IntEn - Start of Frame */ -#define UDCICR1_IERU (1 << 29) /* IntEn - Resume */ -#define UDCICR1_IESU (1 << 28) /* IntEn - Suspend */ -#define UDCICR1_IERS (1 << 27) /* IntEn - Reset */ - -#define UDCISR0 __REG(0x4060000C) /* UDC Interrupt Status Register 0 */ -#define UDCISR1 __REG(0x40600010) /* UDC Interrupt Status Register 1 */ -#define UDCISR_INT(n,intr) (((intr) & 0x03) << (((n) & 0x0F) * 2)) -#define UDCISR1_IRCC (1 << 31) /* IntReq - Configuration Change */ -#define UDCISR1_IRSOF (1 << 30) /* IntReq - Start of Frame */ -#define UDCISR1_IRRU (1 << 29) /* IntReq - Resume */ -#define UDCISR1_IRSU (1 << 28) /* IntReq - Suspend */ -#define UDCISR1_IRRS (1 << 27) /* IntReq - Reset */ - -#define UDCFNR __REG(0x40600014) /* UDC Frame Number Register */ -#define UDCOTGICR __REG(0x40600018) /* UDC On-The-Go interrupt control */ -#define UDCOTGICR_IESF (1 << 24) /* OTG SET_FEATURE command recvd */ -#define UDCOTGICR_IEXR (1 << 17) /* Extra Transceiver Interrupt - Rising Edge Interrupt Enable */ -#define UDCOTGICR_IEXF (1 << 16) /* Extra Transceiver Interrupt - Falling Edge Interrupt Enable */ -#define UDCOTGICR_IEVV40R (1 << 9) /* OTG Vbus Valid 4.0V Rising Edge - Interrupt Enable */ -#define UDCOTGICR_IEVV40F (1 << 8) /* OTG Vbus Valid 4.0V Falling Edge - Interrupt Enable */ -#define UDCOTGICR_IEVV44R (1 << 7) /* OTG Vbus Valid 4.4V Rising Edge - Interrupt Enable */ -#define UDCOTGICR_IEVV44F (1 << 6) /* OTG Vbus Valid 4.4V Falling Edge - Interrupt Enable */ -#define UDCOTGICR_IESVR (1 << 5) /* OTG Session Valid Rising Edge - Interrupt Enable */ -#define UDCOTGICR_IESVF (1 << 4) /* OTG Session Valid Falling Edge - Interrupt Enable */ -#define UDCOTGICR_IESDR (1 << 3) /* OTG A-Device SRP Detect Rising - Edge Interrupt Enable */ -#define UDCOTGICR_IESDF (1 << 2) /* OTG A-Device SRP Detect Falling - Edge Interrupt Enable */ -#define UDCOTGICR_IEIDR (1 << 1) /* OTG ID Change Rising Edge - Interrupt Enable */ -#define UDCOTGICR_IEIDF (1 << 0) /* OTG ID Change Falling Edge - Interrupt Enable */ - -#define UP2OCR __REG(0x40600020) /* USB Port 2 Output Control register */ -#define UP3OCR __REG(0x40600024) /* USB Port 2 Output Control register */ - -#define UP2OCR_CPVEN (1 << 0) /* Charge Pump Vbus Enable */ -#define UP2OCR_CPVPE (1 << 1) /* Charge Pump Vbus Pulse Enable */ -#define UP2OCR_DPPDE (1 << 2) /* Host Port 2 Transceiver D+ Pull Down Enable */ -#define UP2OCR_DMPDE (1 << 3) /* Host Port 2 Transceiver D- Pull Down Enable */ -#define UP2OCR_DPPUE (1 << 4) /* Host Port 2 Transceiver D+ Pull Up Enable */ -#define UP2OCR_DMPUE (1 << 5) /* Host Port 2 Transceiver D- Pull Up Enable */ -#define UP2OCR_DPPUBE (1 << 6) /* Host Port 2 Transceiver D+ Pull Up Bypass Enable */ -#define UP2OCR_DMPUBE (1 << 7) /* Host Port 2 Transceiver D- Pull Up Bypass Enable */ -#define UP2OCR_EXSP (1 << 8) /* External Transceiver Speed Control */ -#define UP2OCR_EXSUS (1 << 9) /* External Transceiver Speed Enable */ -#define UP2OCR_IDON (1 << 10) /* OTG ID Read Enable */ -#define UP2OCR_HXS (1 << 16) /* Host Port 2 Transceiver Output Select */ -#define UP2OCR_HXOE (1 << 17) /* Host Port 2 Transceiver Output Enable */ -#define UP2OCR_SEOS(x) ((x & 7) << 24) /* Single-Ended Output Select */ - -#define UDCCSN(x) __REG2(0x40600100, (x) << 2) -#define UDCCSR0 __REG(0x40600100) /* UDC Control/Status register - Endpoint 0 */ -#define UDCCSR0_SA (1 << 7) /* Setup Active */ -#define UDCCSR0_RNE (1 << 6) /* Receive FIFO Not Empty */ -#define UDCCSR0_FST (1 << 5) /* Force Stall */ -#define UDCCSR0_SST (1 << 4) /* Sent Stall */ -#define UDCCSR0_DME (1 << 3) /* DMA Enable */ -#define UDCCSR0_FTF (1 << 2) /* Flush Transmit FIFO */ -#define UDCCSR0_IPR (1 << 1) /* IN Packet Ready */ -#define UDCCSR0_OPC (1 << 0) /* OUT Packet Complete */ - -#define UDCCSRA __REG(0x40600104) /* UDC Control/Status register - Endpoint A */ -#define UDCCSRB __REG(0x40600108) /* UDC Control/Status register - Endpoint B */ -#define UDCCSRC __REG(0x4060010C) /* UDC Control/Status register - Endpoint C */ -#define UDCCSRD __REG(0x40600110) /* UDC Control/Status register - Endpoint D */ -#define UDCCSRE __REG(0x40600114) /* UDC Control/Status register - Endpoint E */ -#define UDCCSRF __REG(0x40600118) /* UDC Control/Status register - Endpoint F */ -#define UDCCSRG __REG(0x4060011C) /* UDC Control/Status register - Endpoint G */ -#define UDCCSRH __REG(0x40600120) /* UDC Control/Status register - Endpoint H */ -#define UDCCSRI __REG(0x40600124) /* UDC Control/Status register - Endpoint I */ -#define UDCCSRJ __REG(0x40600128) /* UDC Control/Status register - Endpoint J */ -#define UDCCSRK __REG(0x4060012C) /* UDC Control/Status register - Endpoint K */ -#define UDCCSRL __REG(0x40600130) /* UDC Control/Status register - Endpoint L */ -#define UDCCSRM __REG(0x40600134) /* UDC Control/Status register - Endpoint M */ -#define UDCCSRN __REG(0x40600138) /* UDC Control/Status register - Endpoint N */ -#define UDCCSRP __REG(0x4060013C) /* UDC Control/Status register - Endpoint P */ -#define UDCCSRQ __REG(0x40600140) /* UDC Control/Status register - Endpoint Q */ -#define UDCCSRR __REG(0x40600144) /* UDC Control/Status register - Endpoint R */ -#define UDCCSRS __REG(0x40600148) /* UDC Control/Status register - Endpoint S */ -#define UDCCSRT __REG(0x4060014C) /* UDC Control/Status register - Endpoint T */ -#define UDCCSRU __REG(0x40600150) /* UDC Control/Status register - Endpoint U */ -#define UDCCSRV __REG(0x40600154) /* UDC Control/Status register - Endpoint V */ -#define UDCCSRW __REG(0x40600158) /* UDC Control/Status register - Endpoint W */ -#define UDCCSRX __REG(0x4060015C) /* UDC Control/Status register - Endpoint X */ - -#define UDCCSR_DPE (1 << 9) /* Data Packet Error */ -#define UDCCSR_FEF (1 << 8) /* Flush Endpoint FIFO */ -#define UDCCSR_SP (1 << 7) /* Short Packet Control/Status */ -#define UDCCSR_BNE (1 << 6) /* Buffer Not Empty (IN endpoints) */ -#define UDCCSR_BNF (1 << 6) /* Buffer Not Full (OUT endpoints) */ -#define UDCCSR_FST (1 << 5) /* Force STALL */ -#define UDCCSR_SST (1 << 4) /* Sent STALL */ -#define UDCCSR_DME (1 << 3) /* DMA Enable */ -#define UDCCSR_TRN (1 << 2) /* Tx/Rx NAK */ -#define UDCCSR_PC (1 << 1) /* Packet Complete */ -#define UDCCSR_FS (1 << 0) /* FIFO needs service */ - -#define UDCBCN(x) __REG2(0x40600200, (x)<<2) -#define UDCBCR0 __REG(0x40600200) /* Byte Count Register - EP0 */ -#define UDCBCRA __REG(0x40600204) /* Byte Count Register - EPA */ -#define UDCBCRB __REG(0x40600208) /* Byte Count Register - EPB */ -#define UDCBCRC __REG(0x4060020C) /* Byte Count Register - EPC */ -#define UDCBCRD __REG(0x40600210) /* Byte Count Register - EPD */ -#define UDCBCRE __REG(0x40600214) /* Byte Count Register - EPE */ -#define UDCBCRF __REG(0x40600218) /* Byte Count Register - EPF */ -#define UDCBCRG __REG(0x4060021C) /* Byte Count Register - EPG */ -#define UDCBCRH __REG(0x40600220) /* Byte Count Register - EPH */ -#define UDCBCRI __REG(0x40600224) /* Byte Count Register - EPI */ -#define UDCBCRJ __REG(0x40600228) /* Byte Count Register - EPJ */ -#define UDCBCRK __REG(0x4060022C) /* Byte Count Register - EPK */ -#define UDCBCRL __REG(0x40600230) /* Byte Count Register - EPL */ -#define UDCBCRM __REG(0x40600234) /* Byte Count Register - EPM */ -#define UDCBCRN __REG(0x40600238) /* Byte Count Register - EPN */ -#define UDCBCRP __REG(0x4060023C) /* Byte Count Register - EPP */ -#define UDCBCRQ __REG(0x40600240) /* Byte Count Register - EPQ */ -#define UDCBCRR __REG(0x40600244) /* Byte Count Register - EPR */ -#define UDCBCRS __REG(0x40600248) /* Byte Count Register - EPS */ -#define UDCBCRT __REG(0x4060024C) /* Byte Count Register - EPT */ -#define UDCBCRU __REG(0x40600250) /* Byte Count Register - EPU */ -#define UDCBCRV __REG(0x40600254) /* Byte Count Register - EPV */ -#define UDCBCRW __REG(0x40600258) /* Byte Count Register - EPW */ -#define UDCBCRX __REG(0x4060025C) /* Byte Count Register - EPX */ - -#define UDCDN(x) __REG2(0x40600300, (x)<<2) -#define PHYS_UDCDN(x) (0x40600300 + ((x)<<2)) -#define PUDCDN(x) (volatile u32 *)(io_p2v(PHYS_UDCDN((x)))) -#define UDCDR0 __REG(0x40600300) /* Data Register - EP0 */ -#define UDCDRA __REG(0x40600304) /* Data Register - EPA */ -#define UDCDRB __REG(0x40600308) /* Data Register - EPB */ -#define UDCDRC __REG(0x4060030C) /* Data Register - EPC */ -#define UDCDRD __REG(0x40600310) /* Data Register - EPD */ -#define UDCDRE __REG(0x40600314) /* Data Register - EPE */ -#define UDCDRF __REG(0x40600318) /* Data Register - EPF */ -#define UDCDRG __REG(0x4060031C) /* Data Register - EPG */ -#define UDCDRH __REG(0x40600320) /* Data Register - EPH */ -#define UDCDRI __REG(0x40600324) /* Data Register - EPI */ -#define UDCDRJ __REG(0x40600328) /* Data Register - EPJ */ -#define UDCDRK __REG(0x4060032C) /* Data Register - EPK */ -#define UDCDRL __REG(0x40600330) /* Data Register - EPL */ -#define UDCDRM __REG(0x40600334) /* Data Register - EPM */ -#define UDCDRN __REG(0x40600338) /* Data Register - EPN */ -#define UDCDRP __REG(0x4060033C) /* Data Register - EPP */ -#define UDCDRQ __REG(0x40600340) /* Data Register - EPQ */ -#define UDCDRR __REG(0x40600344) /* Data Register - EPR */ -#define UDCDRS __REG(0x40600348) /* Data Register - EPS */ -#define UDCDRT __REG(0x4060034C) /* Data Register - EPT */ -#define UDCDRU __REG(0x40600350) /* Data Register - EPU */ -#define UDCDRV __REG(0x40600354) /* Data Register - EPV */ -#define UDCDRW __REG(0x40600358) /* Data Register - EPW */ -#define UDCDRX __REG(0x4060035C) /* Data Register - EPX */ - -#define UDCCN(x) __REG2(0x40600400, (x)<<2) -#define UDCCRA __REG(0x40600404) /* Configuration register EPA */ -#define UDCCRB __REG(0x40600408) /* Configuration register EPB */ -#define UDCCRC __REG(0x4060040C) /* Configuration register EPC */ -#define UDCCRD __REG(0x40600410) /* Configuration register EPD */ -#define UDCCRE __REG(0x40600414) /* Configuration register EPE */ -#define UDCCRF __REG(0x40600418) /* Configuration register EPF */ -#define UDCCRG __REG(0x4060041C) /* Configuration register EPG */ -#define UDCCRH __REG(0x40600420) /* Configuration register EPH */ -#define UDCCRI __REG(0x40600424) /* Configuration register EPI */ -#define UDCCRJ __REG(0x40600428) /* Configuration register EPJ */ -#define UDCCRK __REG(0x4060042C) /* Configuration register EPK */ -#define UDCCRL __REG(0x40600430) /* Configuration register EPL */ -#define UDCCRM __REG(0x40600434) /* Configuration register EPM */ -#define UDCCRN __REG(0x40600438) /* Configuration register EPN */ -#define UDCCRP __REG(0x4060043C) /* Configuration register EPP */ -#define UDCCRQ __REG(0x40600440) /* Configuration register EPQ */ -#define UDCCRR __REG(0x40600444) /* Configuration register EPR */ -#define UDCCRS __REG(0x40600448) /* Configuration register EPS */ -#define UDCCRT __REG(0x4060044C) /* Configuration register EPT */ -#define UDCCRU __REG(0x40600450) /* Configuration register EPU */ -#define UDCCRV __REG(0x40600454) /* Configuration register EPV */ -#define UDCCRW __REG(0x40600458) /* Configuration register EPW */ -#define UDCCRX __REG(0x4060045C) /* Configuration register EPX */ - -#define UDCCONR_CN (0x03 << 25) /* Configuration Number */ -#define UDCCONR_CN_S (25) -#define UDCCONR_IN (0x07 << 22) /* Interface Number */ -#define UDCCONR_IN_S (22) -#define UDCCONR_AISN (0x07 << 19) /* Alternate Interface Number */ -#define UDCCONR_AISN_S (19) -#define UDCCONR_EN (0x0f << 15) /* Endpoint Number */ -#define UDCCONR_EN_S (15) -#define UDCCONR_ET (0x03 << 13) /* Endpoint Type: */ -#define UDCCONR_ET_S (13) -#define UDCCONR_ET_INT (0x03 << 13) /* Interrupt */ -#define UDCCONR_ET_BULK (0x02 << 13) /* Bulk */ -#define UDCCONR_ET_ISO (0x01 << 13) /* Isochronous */ -#define UDCCONR_ET_NU (0x00 << 13) /* Not used */ -#define UDCCONR_ED (1 << 12) /* Endpoint Direction */ -#define UDCCONR_MPS (0x3ff << 2) /* Maximum Packet Size */ -#define UDCCONR_MPS_S (2) -#define UDCCONR_DE (1 << 1) /* Double Buffering Enable */ -#define UDCCONR_EE (1 << 0) /* Endpoint Enable */ - - -#define UDC_INT_FIFOERROR (0x2) -#define UDC_INT_PACKETCMP (0x1) - -#define UDC_FNR_MASK (0x7ff) - -#define UDCCSR_WR_MASK (UDCCSR_DME|UDCCSR_FST) -#define UDC_BCR_MASK (0x3ff) - -#endif diff --git a/arch/arm/mach-pxa/include/mach/pxa27x.h b/arch/arm/mach-pxa/include/mach/pxa27x.h deleted file mode 100644 index 1a4291936c58..000000000000 --- a/arch/arm/mach-pxa/include/mach/pxa27x.h +++ /dev/null @@ -1,25 +0,0 @@ -#ifndef __MACH_PXA27x_H -#define __MACH_PXA27x_H - -#include -#include -#include -#include -#include - -#define ARB_CNTRL __REG(0x48000048) /* Arbiter Control Register */ - -#define ARB_DMA_SLV_PARK (1<<31) /* Be parked with DMA slave when idle */ -#define ARB_CI_PARK (1<<30) /* Be parked with Camera Interface when idle */ -#define ARB_EX_MEM_PARK (1<<29) /* Be parked with external MEMC when idle */ -#define ARB_INT_MEM_PARK (1<<28) /* Be parked with internal MEMC when idle */ -#define ARB_USB_PARK (1<<27) /* Be parked with USB when idle */ -#define ARB_LCD_PARK (1<<26) /* Be parked with LCD when idle */ -#define ARB_DMA_PARK (1<<25) /* Be parked with DMA when idle */ -#define ARB_CORE_PARK (1<<24) /* Be parked with core when idle */ -#define ARB_LOCK_FLAG (1<<23) /* Only Locking masters gain access to the bus */ - -extern int pxa27x_set_pwrmode(unsigned int mode); -extern void pxa27x_cpu_pm_enter(suspend_state_t state); - -#endif /* __MACH_PXA27x_H */ diff --git a/arch/arm/mach-pxa/include/mach/pxa300.h b/arch/arm/mach-pxa/include/mach/pxa300.h deleted file mode 100644 index 733b6412c3df..000000000000 --- a/arch/arm/mach-pxa/include/mach/pxa300.h +++ /dev/null @@ -1,7 +0,0 @@ -#ifndef __MACH_PXA300_H -#define __MACH_PXA300_H - -#include -#include - -#endif /* __MACH_PXA300_H */ diff --git a/arch/arm/mach-pxa/include/mach/pxa320.h b/arch/arm/mach-pxa/include/mach/pxa320.h deleted file mode 100644 index b6204e470d89..000000000000 --- a/arch/arm/mach-pxa/include/mach/pxa320.h +++ /dev/null @@ -1,8 +0,0 @@ -#ifndef __MACH_PXA320_H -#define __MACH_PXA320_H - -#include -#include - -#endif /* __MACH_PXA320_H */ - diff --git a/arch/arm/mach-pxa/include/mach/pxa3xx.h b/arch/arm/mach-pxa/include/mach/pxa3xx.h deleted file mode 100644 index b4143fb6631f..000000000000 --- a/arch/arm/mach-pxa/include/mach/pxa3xx.h +++ /dev/null @@ -1,8 +0,0 @@ -#ifndef __MACH_PXA3XX_H -#define __MACH_PXA3XX_H - -#include -#include -#include - -#endif /* __MACH_PXA3XX_H */ diff --git a/arch/arm/mach-pxa/include/mach/pxa930.h b/arch/arm/mach-pxa/include/mach/pxa930.h deleted file mode 100644 index 190363b98d01..000000000000 --- a/arch/arm/mach-pxa/include/mach/pxa930.h +++ /dev/null @@ -1,7 +0,0 @@ -#ifndef __MACH_PXA930_H -#define __MACH_PXA930_H - -#include -#include - -#endif /* __MACH_PXA930_H */ diff --git a/arch/arm/mach-pxa/include/mach/regs-rtc.h b/arch/arm/mach-pxa/include/mach/regs-rtc.h deleted file mode 100644 index f0e4a589bbe1..000000000000 --- a/arch/arm/mach-pxa/include/mach/regs-rtc.h +++ /dev/null @@ -1,23 +0,0 @@ -#ifndef __ASM_MACH_REGS_RTC_H -#define __ASM_MACH_REGS_RTC_H - -#include - -/* - * Real Time Clock - */ - -#define RCNR __REG(0x40900000) /* RTC Count Register */ -#define RTAR __REG(0x40900004) /* RTC Alarm Register */ -#define RTSR __REG(0x40900008) /* RTC Status Register */ -#define RTTR __REG(0x4090000C) /* RTC Timer Trim Register */ -#define PIAR __REG(0x40900038) /* Periodic Interrupt Alarm Register */ - -#define RTSR_PICE (1 << 15) /* Periodic interrupt count enable */ -#define RTSR_PIALE (1 << 14) /* Periodic interrupt Alarm enable */ -#define RTSR_HZE (1 << 3) /* HZ interrupt enable */ -#define RTSR_ALE (1 << 2) /* RTC alarm interrupt enable */ -#define RTSR_HZ (1 << 1) /* HZ rising-edge detected */ -#define RTSR_AL (1 << 0) /* RTC alarm detected */ - -#endif /* __ASM_MACH_REGS_RTC_H */ diff --git a/arch/arm/mach-pxa/include/mach/regs-u2d.h b/arch/arm/mach-pxa/include/mach/regs-u2d.h deleted file mode 100644 index c15c0c57de08..000000000000 --- a/arch/arm/mach-pxa/include/mach/regs-u2d.h +++ /dev/null @@ -1,200 +0,0 @@ -#ifndef __ASM_ARCH_PXA3xx_U2D_H -#define __ASM_ARCH_PXA3xx_U2D_H - -#include - -/* - * USB2 device controller registers and bits definitions - */ -#define U2DCR (0x0000) /* U2D Control Register */ -#define U2DCR_NDC (1 << 31) /* NAK During Config */ -#define U2DCR_HSTC (0x7 << 28) /* High Speed Timeout Calibration */ -#define U2DCR_SPEOREN (1 << 27) /* Short Packet EOR INTR generation Enable */ -#define U2DCR_FSTC (0x7 << 24) /* Full Speed Timeout Calibration */ -#define U2DCR_UCLKOVR (1 << 22) /* UTM Clock Override */ -#define U2DCR_ABP (1 << 21) /* Application Bus Power */ -#define U2DCR_ADD (1 << 20) /* Application Device Disconnect */ -#define U2DCR_CC (1 << 19) /* Configuration Change */ -#define U2DCR_HS (1 << 18) /* High Speed USB Detection */ -#define U2DCR_SMAC (1 << 17) /* Switch Endpoint Memory to Active Configuration */ -#define U2DCR_DWRE (1 << 16) /* Device Remote Wake-up Feature */ -#define U2DCR_ACN (0xf << 12) /* Active U2D Configuration Number */ -#define U2DCR_AIN (0xf << 8) /* Active U2D Interface Number */ -#define U2DCR_AAISN (0xf << 4) /* Active U2D Alternate Interface Setting Number */ -#define U2DCR_EMCE (1 << 3) /* Endpoint Memory Configuration Error */ -#define U2DCR_UDR (1 << 2) /* U2D Resume */ -#define U2DCR_UDA (1 << 1) /* U2D Active */ -#define U2DCR_UDE (1 << 0) /* U2D Enable */ - -#define U2DICR (0x0004) /* U2D Interrupt Control Register */ -#define U2DISR (0x000C) /* U2D Interrupt Status Register */ -#define U2DINT_CC (1 << 31) /* Interrupt - Configuration Change */ -#define U2DINT_SOF (1 << 30) /* Interrupt - SOF */ -#define U2DINT_USOF (1 << 29) /* Interrupt - micro SOF */ -#define U2DINT_RU (1 << 28) /* Interrupt - Resume */ -#define U2DINT_SU (1 << 27) /* Interrupt - Suspend */ -#define U2DINT_RS (1 << 26) /* Interrupt - Reset */ -#define U2DINT_DPE (1 << 25) /* Interrupt - Data Packet Error */ -#define U2DINT_FIFOERR (0x4) /* Interrupt - endpoint FIFO error */ -#define U2DINT_PACKETCMP (0x2) /* Interrupt - endpoint packet complete */ -#define U2DINT_SPACKETCMP (0x1) /* Interrupt - endpoint short packet complete */ - -#define U2DFNR (0x0014) /* U2D Frame Number Register */ - -#define U2DINT(n, intr) (((intr) & 0x07) << (((n) & 0x07) * 3)) -#define U2DICR2 (0x0008) /* U2D Interrupt Control Register 2 */ -#define U2DISR2 (0x0010) /* U2D Interrupt Status Register 2 */ - -#define U2DOTGCR (0x0020) /* U2D OTG Control Register */ -#define U2DOTGCR_OTGEN (1 << 31) /* On-The-Go Enable */ -#define U2DOTGCR_AALTHNP (1 << 30) /* A-device Alternate Host Negotiation Protocal Port Support */ -#define U2DOTGCR_AHNP (1 << 29) /* A-device Host Negotiation Protocal Support */ -#define U2DOTGCR_BHNP (1 << 28) /* B-device Host Negotiation Protocal Enable */ - -#ifdef CONFIG_CPU_PXA930 -#define U2DOTGCR_LPA (1 << 15) /* ULPI low power mode active */ -#define U2DOTGCR_IESI (1 << 13) /* OTG interrupt Enable */ -#define U2DOTGCR_ISSI (1 << 12) /* OTG interrupt status */ -#endif - -#define U2DOTGCR_CKAF (1 << 5) /* Carkit Mode Alternate Function Select */ -#define U2DOTGCR_UTMID (1 << 4) /* UTMI Interface Disable */ -#define U2DOTGCR_ULAF (1 << 3) /* ULPI Mode Alternate Function Select */ -#define U2DOTGCR_SMAF (1 << 2) /* Serial Mode Alternate Function Select */ -#define U2DOTGCR_RTSM (1 << 1) /* Return to Synchronous Mode (ULPI Mode) */ -#define U2DOTGCR_ULE (1 << 0) /* ULPI Wrapper Enable */ - -#define U2DOTGICR (0x0024) /* U2D OTG Interrupt Control Register */ -#define U2DOTGISR (0x0028) /* U2D OTG Interrupt Status Register */ - -#define U2DOTGINT_SF (1 << 17) /* OTG Set Feature Command Received */ -#define U2DOTGINT_SI (1 << 16) /* OTG Interrupt */ -#define U2DOTGINT_RLS1 (1 << 14) /* RXCMD Linestate[1] Change Interrupt Rise */ -#define U2DOTGINT_RLS0 (1 << 13) /* RXCMD Linestate[0] Change Interrupt Rise */ -#define U2DOTGINT_RID (1 << 12) /* RXCMD OTG ID Change Interrupt Rise */ -#define U2DOTGINT_RSE (1 << 11) /* RXCMD OTG Session End Interrupt Rise */ -#define U2DOTGINT_RSV (1 << 10) /* RXCMD OTG Session Valid Interrupt Rise */ -#define U2DOTGINT_RVV (1 << 9) /* RXCMD OTG Vbus Valid Interrupt Rise */ -#define U2DOTGINT_RCK (1 << 8) /* RXCMD Carkit Interrupt Rise */ -#define U2DOTGINT_FLS1 (1 << 6) /* RXCMD Linestate[1] Change Interrupt Fall */ -#define U2DOTGINT_FLS0 (1 << 5) /* RXCMD Linestate[0] Change Interrupt Fall */ -#define U2DOTGINT_FID (1 << 4) /* RXCMD OTG ID Change Interrupt Fall */ -#define U2DOTGINT_FSE (1 << 3) /* RXCMD OTG Session End Interrupt Fall */ -#define U2DOTGINT_FSV (1 << 2) /* RXCMD OTG Session Valid Interrupt Fall */ -#define U2DOTGINT_FVV (1 << 1) /* RXCMD OTG Vbus Valid Interrupt Fall */ -#define U2DOTGINT_FCK (1 << 0) /* RXCMD Carkit Interrupt Fall */ - -#define U2DOTGUSR (0x002C) /* U2D OTG ULPI Status Register */ -#define U2DOTGUSR_LPA (1 << 31) /* ULPI Low Power Mode Active */ -#define U2DOTGUSR_S6A (1 << 30) /* ULPI Serial Mode (6-pin) Active */ -#define U2DOTGUSR_S3A (1 << 29) /* ULPI Serial Mode (3-pin) Active */ -#define U2DOTGUSR_CKA (1 << 28) /* ULPI Car Kit Mode Active */ -#define U2DOTGUSR_LS1 (1 << 6) /* RXCMD Linestate 1 Status */ -#define U2DOTGUSR_LS0 (1 << 5) /* RXCMD Linestate 0 Status */ -#define U2DOTGUSR_ID (1 << 4) /* OTG IDGnd Status */ -#define U2DOTGUSR_SE (1 << 3) /* OTG Session End Status */ -#define U2DOTGUSR_SV (1 << 2) /* OTG Session Valid Status */ -#define U2DOTGUSR_VV (1 << 1) /* OTG Vbus Valid Status */ -#define U2DOTGUSR_CK (1 << 0) /* Carkit Interrupt Status */ - -#define U2DOTGUCR (0x0030) /* U2D OTG ULPI Control Register */ -#define U2DOTGUCR_RUN (1 << 25) /* RUN */ -#define U2DOTGUCR_RNW (1 << 24) /* Read or Write operation */ -#define U2DOTGUCR_ADDR (0x3f << 16) /* Address of the ULPI PHY register */ -#define U2DOTGUCR_WDATA (0xff << 8) /* The data for a WRITE command */ -#define U2DOTGUCR_RDATA (0xff << 0) /* The data for a READ command */ - -#define U2DP3CR (0x0034) /* U2D Port 3 Control Register */ -#define U2DP3CR_P2SS (0x3 << 8) /* Host Port 2 Serial Mode Select */ -#define U2DP3CR_P3SS (0x7 << 4) /* Host Port 3 Serial Mode Select */ -#define U2DP3CR_VPVMBEN (0x1 << 2) /* Host Port 3 Vp/Vm Block Enable */ -#define U2DP3CR_CFG (0x3 << 0) /* Host Port 3 Configuration */ - -#define U2DCSR0 (0x0100) /* U2D Control/Status Register - Endpoint 0 */ -#define U2DCSR0_IPA (1 << 8) /* IN Packet Adjusted */ -#define U2DCSR0_SA (1 << 7) /* SETUP Active */ -#define U2DCSR0_RNE (1 << 6) /* Receive FIFO Not Empty */ -#define U2DCSR0_FST (1 << 5) /* Force Stall */ -#define U2DCSR0_SST (1 << 4) /* Send Stall */ -#define U2DCSR0_DME (1 << 3) /* DMA Enable */ -#define U2DCSR0_FTF (1 << 2) /* Flush Transmit FIFO */ -#define U2DCSR0_IPR (1 << 1) /* IN Packet Ready */ -#define U2DCSR0_OPC (1 << 0) /* OUT Packet Complete */ - -#define U2DCSR(x) (0x0100 + ((x) << 2)) /* U2D Control/Status Register - Endpoint x */ -#define U2DCSR_BF (1 << 10) /* Buffer Full, for OUT eps */ -#define U2DCSR_BE (1 << 10) /* Buffer Empty, for IN eps */ -#define U2DCSR_DPE (1 << 9) /* Data Packet Error, for ISO eps only */ -#define U2DCSR_FEF (1 << 8) /* Flush Endpoint FIFO */ -#define U2DCSR_SP (1 << 7) /* Short Packet Control/Status, for OUT eps only, readonly */ -#define U2DCSR_BNE (1 << 6) /* Buffer Not Empty, for OUT eps */ -#define U2DCSR_BNF (1 << 6) /* Buffer Not Full, for IN eps */ -#define U2DCSR_FST (1 << 5) /* Force STALL, write 1 set */ -#define U2DCSR_SST (1 << 4) /* Sent STALL, write 1 clear */ -#define U2DCSR_DME (1 << 3) /* DMA Enable */ -#define U2DCSR_TRN (1 << 2) /* Tx/Rx NAK, write 1 clear */ -#define U2DCSR_PC (1 << 1) /* Packet Complete, write 1 clear */ -#define U2DCSR_FS (1 << 0) /* FIFO needs Service */ - -#define U2DBCR0 (0x0200) /* U2D Byte Count Register - Endpoint 0 */ -#define U2DBCR(x) (0x0200 + ((x) << 2)) /* U2D Byte Count Register - Endpoint x */ - -#define U2DDR0 (0x0300) /* U2D Data Register - Endpoint 0 */ - -#define U2DEPCR(x) (0x0400 + ((x) << 2)) /* U2D Configuration Register - Endpoint x */ -#define U2DEPCR_EE (1 << 0) /* Endpoint Enable */ -#define U2DEPCR_BS_MASK (0x3FE) /* Buffer Size, BS*8=FIFO size, max 8184B = 8KB */ - -#define U2DSCA (0x0500) /* U2D Setup Command Address */ -#define U2DSCA_VALUE (0x0120) - -#define U2DEN0 (0x0504) /* U2D Endpoint Information Register - Endpoint 0 */ -#define U2DEN(x) (0x0504 + ((x) << 2)) /* U2D Endpoint Information Register - Endpoint x */ - -/* U2DMA registers */ -#define U2DMACSR0 (0x1000) /* U2DMA Control/Status Register - Channel 0 */ -#define U2DMACSR(x) (0x1000 + ((x) << 2)) /* U2DMA Control/Status Register - Channel x */ -#define U2DMACSR_RUN (1 << 31) /* Run Bit (read / write) */ -#define U2DMACSR_STOPIRQEN (1 << 29) /* Stop Interrupt Enable (read / write) */ -#define U2DMACSR_EORIRQEN (1 << 28) /* End of Receive Interrupt Enable (R/W) */ -#define U2DMACSR_EORJMPEN (1 << 27) /* Jump to next descriptor on EOR */ -#define U2DMACSR_EORSTOPEN (1 << 26) /* STOP on an EOR */ -#define U2DMACSR_RASIRQEN (1 << 23) /* Request After Cnannel Stopped Interrupt Enable */ -#define U2DMACSR_MASKRUN (1 << 22) /* Mask Run */ -#define U2DMACSR_SCEMC (3 << 18) /* System Bus Split Completion Error Message Class */ -#define U2DMACSR_SCEMI (0x1f << 13) /* System Bus Split Completion Error Message Index */ -#define U2DMACSR_BUSERRTYPE (7 << 10) /* PX Bus Error Type */ -#define U2DMACSR_EORINTR (1 << 9) /* End Of Receive */ -#define U2DMACSR_REQPEND (1 << 8) /* Request Pending */ -#define U2DMACSR_RASINTR (1 << 4) /* Request After Channel Stopped (read / write 1 clear) */ -#define U2DMACSR_STOPINTR (1 << 3) /* Stop Interrupt (read only) */ -#define U2DMACSR_ENDINTR (1 << 2) /* End Interrupt (read / write 1 clear) */ -#define U2DMACSR_STARTINTR (1 << 1) /* Start Interrupt (read / write 1 clear) */ -#define U2DMACSR_BUSERRINTR (1 << 0) /* Bus Error Interrupt (read / write 1 clear) */ - -#define U2DMACR (0x1080) /* U2DMA Control Register */ -#define U2DMAINT (0x10F0) /* U2DMA Interrupt Register */ - -#define U2DMABR0 (0x1100) /* U2DMA Branch Register - Channel 0 */ -#define U2DMABR(x) (0x1100 + (x) << 2) /* U2DMA Branch Register - Channel x */ - -#define U2DMADADR0 (0x1200) /* U2DMA Descriptor Address Register - Channel 0 */ -#define U2DMADADR(x) (0x1200 + (x) * 0x10) /* U2DMA Descriptor Address Register - Channel x */ - -#define U2DMADADR_STOP (1U << 0) - -#define U2DMASADR0 (0x1204) /* U2DMA Source Address Register - Channel 0 */ -#define U2DMASADR(x) (0x1204 + (x) * 0x10) /* U2DMA Source Address Register - Channel x */ -#define U2DMATADR0 (0x1208) /* U2DMA Target Address Register - Channel 0 */ -#define U2DMATADR(x) (0x1208 + (x) * 0x10) /* U2DMA Target Address Register - Channel x */ - -#define U2DMACMDR0 (0x120C) /* U2DMA Command Address Register - Channel 0 */ -#define U2DMACMDR(x) (0x120C + (x) * 0x10) /* U2DMA Command Address Register - Channel x */ - -#define U2DMACMDR_XFRDIS (1 << 31) /* Transfer Direction */ -#define U2DMACMDR_STARTIRQEN (1 << 22) /* Start Interrupt Enable */ -#define U2DMACMDR_ENDIRQEN (1 << 21) /* End Interrupt Enable */ -#define U2DMACMDR_PACKCOMP (1 << 13) /* Packet Complete */ -#define U2DMACMDR_LEN (0x07ff) /* length mask (max = 2K - 1) */ - -#endif /* __ASM_ARCH_PXA3xx_U2D_H */ diff --git a/arch/arm/mach-pxa/include/mach/sharpsl_pm.h b/arch/arm/mach-pxa/include/mach/sharpsl_pm.h deleted file mode 100644 index 905be6755f04..000000000000 --- a/arch/arm/mach-pxa/include/mach/sharpsl_pm.h +++ /dev/null @@ -1,113 +0,0 @@ -/* - * SharpSL Battery/PM Driver - * - * Copyright (c) 2004-2005 Richard Purdie - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - */ -#ifndef _MACH_SHARPSL_PM -#define _MACH_SHARPSL_PM - -struct sharpsl_charger_machinfo { - void (*init)(void); - void (*exit)(void); - int gpio_acin; - int gpio_batfull; - int batfull_irq; - int gpio_batlock; - int gpio_fatal; - void (*discharge)(int); - void (*discharge1)(int); - void (*charge)(int); - void (*measure_temp)(int); - void (*presuspend)(void); - void (*postsuspend)(void); - void (*earlyresume)(void); - unsigned long (*read_devdata)(int); -#define SHARPSL_BATT_VOLT 1 -#define SHARPSL_BATT_TEMP 2 -#define SHARPSL_ACIN_VOLT 3 -#define SHARPSL_STATUS_ACIN 4 -#define SHARPSL_STATUS_LOCK 5 -#define SHARPSL_STATUS_CHRGFULL 6 -#define SHARPSL_STATUS_FATAL 7 - unsigned long (*charger_wakeup)(void); - int (*should_wakeup)(unsigned int resume_on_alarm); - void (*backlight_limit)(int); - int (*backlight_get_status) (void); - int charge_on_volt; - int charge_on_temp; - int charge_acin_high; - int charge_acin_low; - int fatal_acin_volt; - int fatal_noacin_volt; - int bat_levels; - struct battery_thresh *bat_levels_noac; - struct battery_thresh *bat_levels_acin; - struct battery_thresh *bat_levels_noac_bl; - struct battery_thresh *bat_levels_acin_bl; - int status_high_acin; - int status_low_acin; - int status_high_noac; - int status_low_noac; -}; - -struct battery_thresh { - int voltage; - int percentage; -}; - -struct battery_stat { - int ac_status; /* APM AC Present/Not Present */ - int mainbat_status; /* APM Main Battery Status */ - int mainbat_percent; /* Main Battery Percentage Charge */ - int mainbat_voltage; /* Main Battery Voltage */ -}; - -struct sharpsl_pm_status { - struct device *dev; - struct timer_list ac_timer; - struct timer_list chrg_full_timer; - - int charge_mode; -#define CHRG_ERROR (-1) -#define CHRG_OFF (0) -#define CHRG_ON (1) -#define CHRG_DONE (2) - - unsigned int flags; -#define SHARPSL_SUSPENDED (1 << 0) /* Device is Suspended */ -#define SHARPSL_ALARM_ACTIVE (1 << 1) /* Alarm is for charging event (not user) */ -#define SHARPSL_BL_LIMIT (1 << 2) /* Backlight Intensity Limited */ -#define SHARPSL_APM_QUEUED (1 << 3) /* APM Event Queued */ -#define SHARPSL_DO_OFFLINE_CHRG (1 << 4) /* Trigger the offline charger */ - - int full_count; - unsigned long charge_start_time; - struct sharpsl_charger_machinfo *machinfo; - struct battery_stat battstat; -}; - -extern struct sharpsl_pm_status sharpsl_pm; - -extern struct battery_thresh sharpsl_battery_levels_acin[]; -extern struct battery_thresh sharpsl_battery_levels_noac[]; - -#define SHARPSL_LED_ERROR 2 -#define SHARPSL_LED_ON 1 -#define SHARPSL_LED_OFF 0 - -void sharpsl_battery_kick(void); -void sharpsl_pm_led(int val); - -/* MAX1111 Channel Definitions */ -#define MAX1111_BATT_VOLT 4u -#define MAX1111_BATT_TEMP 2u -#define MAX1111_ACIN_VOLT 6u -int sharpsl_pm_pxa_read_max1111(int channel); - -void corgi_lcd_limit_intensity(int limit); -#endif diff --git a/arch/arm/mach-pxa/include/mach/tosa_bt.h b/arch/arm/mach-pxa/include/mach/tosa_bt.h deleted file mode 100644 index efc3c3d3b75d..000000000000 --- a/arch/arm/mach-pxa/include/mach/tosa_bt.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * Tosa bluetooth built-in chip control. - * - * Later it may be shared with some other platforms. - * - * Copyright (c) 2008 Dmitry Baryshkov - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - */ -#ifndef TOSA_BT_H -#define TOSA_BT_H - -struct tosa_bt_data { - int gpio_pwr; - int gpio_reset; -}; - -#endif - diff --git a/arch/arm/mach-pxa/include/mach/udc.h b/arch/arm/mach-pxa/include/mach/udc.h deleted file mode 100644 index 9a827e32db98..000000000000 --- a/arch/arm/mach-pxa/include/mach/udc.h +++ /dev/null @@ -1,8 +0,0 @@ -/* - * arch/arm/mach-pxa/include/mach/udc.h - * - */ -#include - -extern void pxa_set_udc_info(struct pxa2xx_udc_mach_info *info); - diff --git a/arch/arm/mach-pxa/include/mach/viper.h b/arch/arm/mach-pxa/include/mach/viper.h deleted file mode 100644 index 5f5fbf1f6489..000000000000 --- a/arch/arm/mach-pxa/include/mach/viper.h +++ /dev/null @@ -1,94 +0,0 @@ -/* - * arch/arm/mach-pxa/include/mach/viper.h - * - * Author: Ian Campbell - * Created: Feb 03, 2003 - * Copyright: Arcom Control Systems. - * - * Maintained by Marc Zyngier - * - * - * Created based on lubbock.h: - * Author: Nicolas Pitre - * Created: Jun 15, 2001 - * Copyright: MontaVista Software Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef ARCH_VIPER_H -#define ARCH_VIPER_H - -#define VIPER_BOOT_PHYS PXA_CS0_PHYS -#define VIPER_FLASH_PHYS PXA_CS1_PHYS -#define VIPER_ETH_PHYS PXA_CS2_PHYS -#define VIPER_USB_PHYS PXA_CS3_PHYS -#define VIPER_ETH_DATA_PHYS PXA_CS4_PHYS -#define VIPER_CPLD_PHYS PXA_CS5_PHYS - -#define VIPER_CPLD_BASE (0xf0000000) -#define VIPER_PC104IO_BASE (0xf1000000) -#define VIPER_USB_BASE (0xf1800000) - -#define VIPER_ETH_GPIO (0) -#define VIPER_CPLD_GPIO (1) -#define VIPER_USB_GPIO (2) -#define VIPER_UARTA_GPIO (4) -#define VIPER_UARTB_GPIO (3) -#define VIPER_CF_CD_GPIO (32) -#define VIPER_CF_RDY_GPIO (8) -#define VIPER_BCKLIGHT_EN_GPIO (9) -#define VIPER_LCD_EN_GPIO (10) -#define VIPER_PSU_DATA_GPIO (6) -#define VIPER_PSU_CLK_GPIO (11) -#define VIPER_UART_SHDN_GPIO (12) -#define VIPER_BRIGHTNESS_GPIO (16) -#define VIPER_PSU_nCS_LD_GPIO (19) -#define VIPER_UPS_GPIO (20) -#define VIPER_CF_POWER_GPIO (82) -#define VIPER_TPM_I2C_SDA_GPIO (26) -#define VIPER_TPM_I2C_SCL_GPIO (27) -#define VIPER_RTC_I2C_SDA_GPIO (83) -#define VIPER_RTC_I2C_SCL_GPIO (84) - -#define VIPER_CPLD_P2V(x) ((x) - VIPER_CPLD_PHYS + VIPER_CPLD_BASE) -#define VIPER_CPLD_V2P(x) ((x) - VIPER_CPLD_BASE + VIPER_CPLD_PHYS) - -#ifndef __ASSEMBLY__ -# define __VIPER_CPLD_REG(x) (*((volatile u16 *)VIPER_CPLD_P2V(x))) -#endif - -/* board level registers in the CPLD: (offsets from CPLD_BASE) ... */ - -/* ... Physical addresses */ -#define _VIPER_LO_IRQ_STATUS (VIPER_CPLD_PHYS + 0x100000) -#define _VIPER_ICR_PHYS (VIPER_CPLD_PHYS + 0x100002) -#define _VIPER_HI_IRQ_STATUS (VIPER_CPLD_PHYS + 0x100004) -#define _VIPER_VERSION_PHYS (VIPER_CPLD_PHYS + 0x100006) -#define VIPER_UARTA_PHYS (VIPER_CPLD_PHYS + 0x300010) -#define VIPER_UARTB_PHYS (VIPER_CPLD_PHYS + 0x300000) -#define _VIPER_SRAM_BASE (VIPER_CPLD_PHYS + 0x800000) - -/* ... Virtual addresses */ -#define VIPER_LO_IRQ_STATUS __VIPER_CPLD_REG(_VIPER_LO_IRQ_STATUS) -#define VIPER_HI_IRQ_STATUS __VIPER_CPLD_REG(_VIPER_HI_IRQ_STATUS) -#define VIPER_VERSION __VIPER_CPLD_REG(_VIPER_VERSION_PHYS) -#define VIPER_ICR __VIPER_CPLD_REG(_VIPER_ICR_PHYS) - -/* Decode VIPER_VERSION register */ -#define VIPER_CPLD_REVISION(x) (((x) >> 5) & 0x7) -#define VIPER_BOARD_VERSION(x) (((x) >> 3) & 0x3) -#define VIPER_BOARD_ISSUE(x) (((x) >> 0) & 0x7) - -/* Interrupt and Configuration Register (VIPER_ICR) */ -/* This is a write only register. Only CF_RST is used under Linux */ - -#define VIPER_ICR_RETRIG (1 << 0) -#define VIPER_ICR_AUTO_CLR (1 << 1) -#define VIPER_ICR_R_DIS (1 << 2) -#define VIPER_ICR_CF_RST (1 << 3) - -#endif - diff --git a/arch/arm/mach-pxa/include/mach/zeus.h b/arch/arm/mach-pxa/include/mach/zeus.h deleted file mode 100644 index 56024f81d57e..000000000000 --- a/arch/arm/mach-pxa/include/mach/zeus.h +++ /dev/null @@ -1,85 +0,0 @@ -/* - * arch/arm/mach-pxa/include/mach/zeus.h - * - * Author: David Vrabel - * Created: Sept 28, 2005 - * Copyright: Arcom Control Systems Ltd. - * - * Maintained by: Marc Zyngier - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef _MACH_ZEUS_H -#define _MACH_ZEUS_H - -#define ZEUS_NR_IRQS (IRQ_BOARD_START + 48) - -/* Physical addresses */ -#define ZEUS_FLASH_PHYS PXA_CS0_PHYS -#define ZEUS_ETH0_PHYS PXA_CS1_PHYS -#define ZEUS_ETH1_PHYS PXA_CS2_PHYS -#define ZEUS_CPLD_PHYS (PXA_CS4_PHYS+0x2000000) -#define ZEUS_SRAM_PHYS PXA_CS5_PHYS -#define ZEUS_PC104IO_PHYS (0x30000000) - -#define ZEUS_CPLD_VERSION_PHYS (ZEUS_CPLD_PHYS + 0x00000000) -#define ZEUS_CPLD_ISA_IRQ_PHYS (ZEUS_CPLD_PHYS + 0x00800000) -#define ZEUS_CPLD_CONTROL_PHYS (ZEUS_CPLD_PHYS + 0x01000000) -#define ZEUS_CPLD_EXTWDOG_PHYS (ZEUS_CPLD_PHYS + 0x01800000) - -/* GPIOs */ -#define ZEUS_AC97_GPIO 0 -#define ZEUS_WAKEUP_GPIO 1 -#define ZEUS_UARTA_GPIO 9 -#define ZEUS_UARTB_GPIO 10 -#define ZEUS_UARTC_GPIO 12 -#define ZEUS_UARTD_GPIO 11 -#define ZEUS_ETH0_GPIO 14 -#define ZEUS_ISA_GPIO 17 -#define ZEUS_BKLEN_GPIO 19 -#define ZEUS_USB2_PWREN_GPIO 22 -#define ZEUS_PTT_GPIO 27 -#define ZEUS_CF_CD_GPIO 35 -#define ZEUS_MMC_WP_GPIO 52 -#define ZEUS_MMC_CD_GPIO 53 -#define ZEUS_EXTGPIO_GPIO 91 -#define ZEUS_CF_PWEN_GPIO 97 -#define ZEUS_CF_RDY_GPIO 99 -#define ZEUS_LCD_EN_GPIO 101 -#define ZEUS_ETH1_GPIO 113 -#define ZEUS_CAN_GPIO 116 - -#define ZEUS_EXT0_GPIO_BASE 128 -#define ZEUS_EXT1_GPIO_BASE 160 -#define ZEUS_USER_GPIO_BASE 192 - -#define ZEUS_EXT0_GPIO(x) (ZEUS_EXT0_GPIO_BASE + (x)) -#define ZEUS_EXT1_GPIO(x) (ZEUS_EXT1_GPIO_BASE + (x)) -#define ZEUS_USER_GPIO(x) (ZEUS_USER_GPIO_BASE + (x)) - -#define ZEUS_CAN_SHDN_GPIO ZEUS_EXT1_GPIO(2) - -/* - * CPLD registers: - * Only 4 registers, but spread over a 32MB address space. - * Be gentle, and remap that over 32kB... - */ - -#define ZEUS_CPLD IOMEM(0xf0000000) -#define ZEUS_CPLD_VERSION (ZEUS_CPLD + 0x0000) -#define ZEUS_CPLD_ISA_IRQ (ZEUS_CPLD + 0x1000) -#define ZEUS_CPLD_CONTROL (ZEUS_CPLD + 0x2000) - -/* CPLD register bits */ -#define ZEUS_CPLD_CONTROL_CF_RST 0x01 - -#define ZEUS_PC104IO IOMEM(0xf1000000) - -#define ZEUS_SRAM_SIZE (256 * 1024) - -#endif - - diff --git a/arch/arm/mach-pxa/include/mach/zylonite.h b/arch/arm/mach-pxa/include/mach/zylonite.h deleted file mode 100644 index ecca976f03d2..000000000000 --- a/arch/arm/mach-pxa/include/mach/zylonite.h +++ /dev/null @@ -1,42 +0,0 @@ -#ifndef __ASM_ARCH_ZYLONITE_H -#define __ASM_ARCH_ZYLONITE_H - -#define ZYLONITE_ETH_PHYS 0x14000000 - -#define EXT_GPIO(x) (128 + (x)) - -#define ZYLONITE_NR_IRQS (IRQ_BOARD_START + 32) - -/* the following variables are processor specific and initialized - * by the corresponding zylonite_pxa3xx_init() - */ -extern int gpio_eth_irq; -extern int gpio_debug_led1; -extern int gpio_debug_led2; - -extern int wm9713_irq; - -extern int lcd_id; -extern int lcd_orientation; - -#ifdef CONFIG_MACH_ZYLONITE300 -extern void zylonite_pxa300_init(void); -#else -static inline void zylonite_pxa300_init(void) -{ - if (cpu_is_pxa300() || cpu_is_pxa310()) - panic("%s: PXA300/PXA310 not supported\n", __func__); -} -#endif - -#ifdef CONFIG_MACH_ZYLONITE320 -extern void zylonite_pxa320_init(void); -#else -static inline void zylonite_pxa320_init(void) -{ - if (cpu_is_pxa320()) - panic("%s: PXA320 not supported\n", __func__); -} -#endif - -#endif /* __ASM_ARCH_ZYLONITE_H */ diff --git a/arch/arm/mach-pxa/littleton.c b/arch/arm/mach-pxa/littleton.c index 5d665588c7eb..051c554776a6 100644 --- a/arch/arm/mach-pxa/littleton.c +++ b/arch/arm/mach-pxa/littleton.c @@ -41,11 +41,11 @@ #include #include -#include +#include "pxa300.h" #include #include #include -#include +#include "littleton.h" #include #include "generic.h" diff --git a/arch/arm/mach-pxa/littleton.h b/arch/arm/mach-pxa/littleton.h new file mode 100644 index 000000000000..8066be54e9f5 --- /dev/null +++ b/arch/arm/mach-pxa/littleton.h @@ -0,0 +1,13 @@ +#ifndef __ASM_ARCH_LITTLETON_H +#define __ASM_ARCH_LITTLETON_H + +#define LITTLETON_ETH_PHYS 0x30000000 + +#define LITTLETON_GPIO_LCD_CS (17) + +#define EXT0_GPIO_BASE (PXA_NR_BUILTIN_GPIO) +#define EXT0_GPIO(x) (EXT0_GPIO_BASE + (x)) + +#define LITTLETON_NR_IRQS (IRQ_BOARD_START + 8) + +#endif /* __ASM_ARCH_LITTLETON_H */ diff --git a/arch/arm/mach-pxa/lpd270.c b/arch/arm/mach-pxa/lpd270.c index 5fcd4f094900..e9f401b0a432 100644 --- a/arch/arm/mach-pxa/lpd270.c +++ b/arch/arm/mach-pxa/lpd270.c @@ -40,8 +40,8 @@ #include #include -#include -#include +#include "pxa27x.h" +#include "lpd270.h" #include #include #include diff --git a/arch/arm/mach-pxa/lpd270.h b/arch/arm/mach-pxa/lpd270.h new file mode 100644 index 000000000000..4edc712a2de8 --- /dev/null +++ b/arch/arm/mach-pxa/lpd270.h @@ -0,0 +1,43 @@ +/* + * arch/arm/mach-pxa/include/mach/lpd270.h + * + * Author: Lennert Buytenhek + * Created: Feb 10, 2006 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ASM_ARCH_LPD270_H +#define __ASM_ARCH_LPD270_H + +#define LPD270_CPLD_PHYS PXA_CS2_PHYS +#define LPD270_CPLD_VIRT IOMEM(0xf0000000) +#define LPD270_CPLD_SIZE 0x00100000 + +#define LPD270_ETH_PHYS (PXA_CS2_PHYS + 0x01000000) + +/* CPLD registers */ +#define LPD270_CPLD_REG(x) (LPD270_CPLD_VIRT + (x)) +#define LPD270_CONTROL LPD270_CPLD_REG(0x00) +#define LPD270_PERIPHERAL0 LPD270_CPLD_REG(0x04) +#define LPD270_PERIPHERAL1 LPD270_CPLD_REG(0x08) +#define LPD270_CPLD_REVISION LPD270_CPLD_REG(0x14) +#define LPD270_EEPROM_SPI_ITF LPD270_CPLD_REG(0x20) +#define LPD270_MODE_PINS LPD270_CPLD_REG(0x24) +#define LPD270_EGPIO LPD270_CPLD_REG(0x30) +#define LPD270_INT_MASK LPD270_CPLD_REG(0x40) +#define LPD270_INT_STATUS LPD270_CPLD_REG(0x50) + +#define LPD270_INT_AC97 (1 << 4) /* AC'97 CODEC IRQ */ +#define LPD270_INT_ETHERNET (1 << 3) /* Ethernet controller IRQ */ +#define LPD270_INT_USBC (1 << 2) /* USB client cable detection IRQ */ + +#define LPD270_IRQ(x) (IRQ_BOARD_START + (x)) +#define LPD270_USBC_IRQ LPD270_IRQ(2) +#define LPD270_ETHERNET_IRQ LPD270_IRQ(3) +#define LPD270_AC97_IRQ LPD270_IRQ(4) +#define LPD270_NR_IRQS (IRQ_BOARD_START + 5) + +#endif diff --git a/arch/arm/mach-pxa/lubbock.c b/arch/arm/mach-pxa/lubbock.c index 6de32fa0e251..7245f3359564 100644 --- a/arch/arm/mach-pxa/lubbock.c +++ b/arch/arm/mach-pxa/lubbock.c @@ -47,14 +47,14 @@ #include -#include +#include "pxa25x.h" #include #include -#include +#include "udc.h" #include #include #include -#include +#include "pm.h" #include #include "generic.h" diff --git a/arch/arm/mach-pxa/magician.c b/arch/arm/mach-pxa/magician.c index 896b268c3ab7..abc918169367 100644 --- a/arch/arm/mach-pxa/magician.c +++ b/arch/arm/mach-pxa/magician.c @@ -38,7 +38,7 @@ #include #include -#include +#include "pxa27x.h" #include #include #include @@ -48,9 +48,9 @@ #include #include -#include -#include +#include "udc.h" +#include "pxa27x-udc.h" #include "devices.h" #include "generic.h" diff --git a/arch/arm/mach-pxa/mainstone.c b/arch/arm/mach-pxa/mainstone.c index c3a87c176d72..40964069a17c 100644 --- a/arch/arm/mach-pxa/mainstone.c +++ b/arch/arm/mach-pxa/mainstone.c @@ -46,7 +46,7 @@ #include #include -#include +#include "pxa27x.h" #include #include #include diff --git a/arch/arm/mach-pxa/mfp-pxa25x.h b/arch/arm/mach-pxa/mfp-pxa25x.h new file mode 100644 index 000000000000..1c59d4b3b19b --- /dev/null +++ b/arch/arm/mach-pxa/mfp-pxa25x.h @@ -0,0 +1,225 @@ +#ifndef __ASM_ARCH_MFP_PXA25X_H +#define __ASM_ARCH_MFP_PXA25X_H + +#include "mfp-pxa2xx.h" + +/* GPIO */ +#define GPIO2_GPIO MFP_CFG_IN(GPIO2, AF0) +#define GPIO3_GPIO MFP_CFG_IN(GPIO3, AF0) +#define GPIO4_GPIO MFP_CFG_IN(GPIO4, AF0) +#define GPIO5_GPIO MFP_CFG_IN(GPIO5, AF0) +#define GPIO6_GPIO MFP_CFG_IN(GPIO6, AF0) +#define GPIO7_GPIO MFP_CFG_IN(GPIO7, AF0) +#define GPIO8_GPIO MFP_CFG_IN(GPIO8, AF0) + +#define GPIO1_RST MFP_CFG_IN(GPIO1, AF1) + +/* Crystal and Clock Signals */ +#define GPIO10_RTCCLK MFP_CFG_OUT(GPIO10, AF1, DRIVE_LOW) +#define GPIO70_RTCCLK MFP_CFG_OUT(GPIO70, AF1, DRIVE_LOW) +#define GPIO7_48MHz MFP_CFG_OUT(GPIO7, AF1, DRIVE_LOW) +#define GPIO11_3_6MHz MFP_CFG_OUT(GPIO11, AF1, DRIVE_LOW) +#define GPIO71_3_6MHz MFP_CFG_OUT(GPIO71, AF1, DRIVE_LOW) +#define GPIO12_32KHz MFP_CFG_OUT(GPIO12, AF1, DRIVE_LOW) +#define GPIO72_32kHz MFP_CFG_OUT(GPIO72, AF1, DRIVE_LOW) + +/* SDRAM and Static Memory I/O Signals */ +#define GPIO15_nCS_1 MFP_CFG_OUT(GPIO15, AF2, DRIVE_HIGH) +#define GPIO78_nCS_2 MFP_CFG_OUT(GPIO78, AF2, DRIVE_HIGH) +#define GPIO79_nCS_3 MFP_CFG_OUT(GPIO79, AF2, DRIVE_HIGH) +#define GPIO80_nCS_4 MFP_CFG_OUT(GPIO80, AF2, DRIVE_HIGH) +#define GPIO33_nCS_5 MFP_CFG_OUT(GPIO33, AF2, DRIVE_HIGH) + +/* Miscellaneous I/O and DMA Signals */ +#define GPIO18_RDY MFP_CFG_IN(GPIO18, AF1) +#define GPIO20_DREQ_0 MFP_CFG_IN(GPIO20, AF1) +#define GPIO19_DREQ_1 MFP_CFG_IN(GPIO19, AF1) + +/* Alternate Bus Master Mode I/O Signals */ +#define GPIO13_MBGNT MFP_CFG_OUT(GPIO13, AF2, DRIVE_LOW) +#define GPIO73_MBGNT MFP_CFG_OUT(GPIO73, AF1, DRIVE_LOW) +#define GPIO14_MBREQ MFP_CFG_IN(GPIO14, AF1) +#define GPIO66_MBREQ MFP_CFG_IN(GPIO66, AF1) + +/* PC CARD */ +#define GPIO52_nPCE_1 MFP_CFG_OUT(GPIO52, AF2, DRIVE_HIGH) +#define GPIO53_nPCE_2 MFP_CFG_OUT(GPIO53, AF2, DRIVE_HIGH) +#define GPIO55_nPREG MFP_CFG_OUT(GPIO55, AF2, DRIVE_HIGH) +#define GPIO50_nPIOR MFP_CFG_OUT(GPIO50, AF2, DRIVE_HIGH) +#define GPIO51_nPIOW MFP_CFG_OUT(GPIO51, AF2, DRIVE_HIGH) +#define GPIO49_nPWE MFP_CFG_OUT(GPIO49, AF2, DRIVE_HIGH) +#define GPIO48_nPOE MFP_CFG_OUT(GPIO48, AF2, DRIVE_HIGH) +#define GPIO57_nIOIS16 MFP_CFG_IN(GPIO57, AF1) +#define GPIO56_nPWAIT MFP_CFG_IN(GPIO56, AF1) +#define GPIO54_nPSKTSEL MFP_CFG_OUT(GPIO54, AF2, DRIVE_HIGH) + +/* FFUART */ +#define GPIO34_FFUART_RXD MFP_CFG_IN(GPIO34, AF1) +#define GPIO35_FFUART_CTS MFP_CFG_IN(GPIO35, AF1) +#define GPIO36_FFUART_DCD MFP_CFG_IN(GPIO36, AF1) +#define GPIO37_FFUART_DSR MFP_CFG_IN(GPIO37, AF1) +#define GPIO38_FFUART_RI MFP_CFG_IN(GPIO38, AF1) +#define GPIO39_FFUART_TXD MFP_CFG_OUT(GPIO39, AF2, DRIVE_HIGH) +#define GPIO40_FFUART_DTR MFP_CFG_OUT(GPIO40, AF2, DRIVE_HIGH) +#define GPIO41_FFUART_RTS MFP_CFG_OUT(GPIO41, AF2, DRIVE_HIGH) + +/* BTUART */ +#define GPIO42_BTUART_RXD MFP_CFG_IN(GPIO42, AF1) +#define GPIO43_BTUART_TXD MFP_CFG_OUT(GPIO43, AF2, DRIVE_HIGH) +#define GPIO44_BTUART_CTS MFP_CFG_IN(GPIO44, AF1) +#define GPIO45_BTUART_RTS MFP_CFG_OUT(GPIO45, AF2, DRIVE_HIGH) + +/* STUART */ +#define GPIO46_STUART_RXD MFP_CFG_IN(GPIO46, AF2) +#define GPIO47_STUART_TXD MFP_CFG_OUT(GPIO47, AF1, DRIVE_HIGH) + +/* HWUART */ +#define GPIO42_HWUART_RXD MFP_CFG_IN(GPIO42, AF3) +#define GPIO43_HWUART_TXD MFP_CFG_OUT(GPIO43, AF3, DRIVE_HIGH) +#define GPIO44_HWUART_CTS MFP_CFG_IN(GPIO44, AF3) +#define GPIO45_HWUART_RTS MFP_CFG_OUT(GPIO45, AF3, DRIVE_HIGH) +#define GPIO48_HWUART_TXD MFP_CFG_OUT(GPIO48, AF1, DRIVE_HIGH) +#define GPIO49_HWUART_RXD MFP_CFG_IN(GPIO49, AF1) +#define GPIO50_HWUART_CTS MFP_CFG_IN(GPIO50, AF1) +#define GPIO51_HWUART_RTS MFP_CFG_OUT(GPIO51, AF1, DRIVE_HIGH) + +/* FICP */ +#define GPIO46_FICP_RXD MFP_CFG_IN(GPIO46, AF1) +#define GPIO47_FICP_TXD MFP_CFG_OUT(GPIO47, AF2, DRIVE_HIGH) + +/* PWM 0/1 */ +#define GPIO16_PWM0_OUT MFP_CFG_OUT(GPIO16, AF2, DRIVE_LOW) +#define GPIO17_PWM1_OUT MFP_CFG_OUT(GPIO17, AF2, DRIVE_LOW) + +/* AC97 */ +#define GPIO28_AC97_BITCLK MFP_CFG_IN(GPIO28, AF1) +#define GPIO29_AC97_SDATA_IN_0 MFP_CFG_IN(GPIO29, AF1) +#define GPIO30_AC97_SDATA_OUT MFP_CFG_OUT(GPIO30, AF2, DRIVE_LOW) +#define GPIO31_AC97_SYNC MFP_CFG_OUT(GPIO31, AF2, DRIVE_LOW) +#define GPIO32_AC97_SDATA_IN_1 MFP_CFG_IN(GPIO32, AF1) + +/* I2S */ +#define GPIO28_I2S_BITCLK_IN MFP_CFG_IN(GPIO28, AF2) +#define GPIO28_I2S_BITCLK_OUT MFP_CFG_OUT(GPIO28, AF1, DRIVE_LOW) +#define GPIO29_I2S_SDATA_IN MFP_CFG_IN(GPIO29, AF2) +#define GPIO30_I2S_SDATA_OUT MFP_CFG_OUT(GPIO30, AF1, DRIVE_LOW) +#define GPIO31_I2S_SYNC MFP_CFG_OUT(GPIO31, AF1, DRIVE_LOW) +#define GPIO32_I2S_SYSCLK MFP_CFG_OUT(GPIO32, AF1, DRIVE_LOW) + +/* SSP 1 */ +#define GPIO23_SSP1_SCLK MFP_CFG_OUT(GPIO23, AF2, DRIVE_LOW) +#define GPIO24_SSP1_SFRM MFP_CFG_OUT(GPIO24, AF2, DRIVE_LOW) +#define GPIO25_SSP1_TXD MFP_CFG_OUT(GPIO25, AF2, DRIVE_LOW) +#define GPIO26_SSP1_RXD MFP_CFG_IN(GPIO26, AF1) +#define GPIO27_SSP1_EXTCLK MFP_CFG_IN(GPIO27, AF1) + +/* SSP 2 - NSSP */ +#define GPIO81_SSP2_CLK_OUT MFP_CFG_OUT(GPIO81, AF1, DRIVE_LOW) +#define GPIO81_SSP2_CLK_IN MFP_CFG_IN(GPIO81, AF1) +#define GPIO82_SSP2_FRM_OUT MFP_CFG_OUT(GPIO82, AF1, DRIVE_LOW) +#define GPIO82_SSP2_FRM_IN MFP_CFG_IN(GPIO82, AF1) +#define GPIO83_SSP2_TXD MFP_CFG_OUT(GPIO83, AF1, DRIVE_LOW) +#define GPIO83_SSP2_RXD MFP_CFG_IN(GPIO83, AF2) +#define GPIO84_SSP2_TXD MFP_CFG_OUT(GPIO84, AF1, DRIVE_LOW) +#define GPIO84_SSP2_RXD MFP_CFG_IN(GPIO84, AF2) + +/* MMC */ +#define GPIO6_MMC_CLK MFP_CFG_OUT(GPIO6, AF1, DRIVE_LOW) +#define GPIO8_MMC_CS0 MFP_CFG_OUT(GPIO8, AF1, DRIVE_LOW) +#define GPIO9_MMC_CS1 MFP_CFG_OUT(GPIO9, AF1, DRIVE_LOW) +#define GPIO34_MMC_CS0 MFP_CFG_OUT(GPIO34, AF2, DRIVE_LOW) +#define GPIO39_MMC_CS1 MFP_CFG_OUT(GPIO39, AF1, DRIVE_LOW) +#define GPIO53_MMC_CLK MFP_CFG_OUT(GPIO53, AF1, DRIVE_LOW) +#define GPIO54_MMC_CLK MFP_CFG_OUT(GPIO54, AF1, DRIVE_LOW) +#define GPIO69_MMC_CLK MFP_CFG_OUT(GPIO69, AF1, DRIVE_LOW) +#define GPIO67_MMC_CS0 MFP_CFG_OUT(GPIO67, AF1, DRIVE_LOW) +#define GPIO68_MMC_CS1 MFP_CFG_OUT(GPIO68, AF1, DRIVE_LOW) + +/* LCD */ +#define GPIO58_LCD_LDD_0 MFP_CFG_OUT(GPIO58, AF2, DRIVE_LOW) +#define GPIO59_LCD_LDD_1 MFP_CFG_OUT(GPIO59, AF2, DRIVE_LOW) +#define GPIO60_LCD_LDD_2 MFP_CFG_OUT(GPIO60, AF2, DRIVE_LOW) +#define GPIO61_LCD_LDD_3 MFP_CFG_OUT(GPIO61, AF2, DRIVE_LOW) +#define GPIO62_LCD_LDD_4 MFP_CFG_OUT(GPIO62, AF2, DRIVE_LOW) +#define GPIO63_LCD_LDD_5 MFP_CFG_OUT(GPIO63, AF2, DRIVE_LOW) +#define GPIO64_LCD_LDD_6 MFP_CFG_OUT(GPIO64, AF2, DRIVE_LOW) +#define GPIO65_LCD_LDD_7 MFP_CFG_OUT(GPIO65, AF2, DRIVE_LOW) +#define GPIO66_LCD_LDD_8 MFP_CFG_OUT(GPIO66, AF2, DRIVE_LOW) +#define GPIO67_LCD_LDD_9 MFP_CFG_OUT(GPIO67, AF2, DRIVE_LOW) +#define GPIO68_LCD_LDD_10 MFP_CFG_OUT(GPIO68, AF2, DRIVE_LOW) +#define GPIO69_LCD_LDD_11 MFP_CFG_OUT(GPIO69, AF2, DRIVE_LOW) +#define GPIO70_LCD_LDD_12 MFP_CFG_OUT(GPIO70, AF2, DRIVE_LOW) +#define GPIO71_LCD_LDD_13 MFP_CFG_OUT(GPIO71, AF2, DRIVE_LOW) +#define GPIO72_LCD_LDD_14 MFP_CFG_OUT(GPIO72, AF2, DRIVE_LOW) +#define GPIO73_LCD_LDD_15 MFP_CFG_OUT(GPIO73, AF2, DRIVE_LOW) +#define GPIO74_LCD_FCLK MFP_CFG_OUT(GPIO74, AF2, DRIVE_LOW) +#define GPIO75_LCD_LCLK MFP_CFG_OUT(GPIO75, AF2, DRIVE_LOW) +#define GPIO76_LCD_PCLK MFP_CFG_OUT(GPIO76, AF2, DRIVE_LOW) +#define GPIO77_LCD_BIAS MFP_CFG_OUT(GPIO77, AF2, DRIVE_LOW) + +#ifdef CONFIG_CPU_PXA26x +/* GPIO */ +#define GPIO85_GPIO MFP_CFG_IN(GPIO85, AF0) +#define GPIO86_GPIO MFP_CFG_IN(GPIO86, AF1) +#define GPIO87_GPIO MFP_CFG_IN(GPIO87, AF1) +#define GPIO88_GPIO MFP_CFG_IN(GPIO88, AF1) +#define GPIO89_GPIO MFP_CFG_IN(GPIO89, AF1) + +/* SDRAM */ +#define GPIO86_nSDCS2 MFP_CFG_OUT(GPIO86, AF0, DRIVE_HIGH) +#define GPIO87_nSDCS3 MFP_CFG_OUT(GPIO87, AF0, DRIVE_HIGH) +#define GPIO88_RDnWR MFP_CFG_OUT(GPIO88, AF0, DRIVE_HIGH) + +/* USB */ +#define GPIO9_USB_RCV MFP_CFG_IN(GPIO9, AF1) +#define GPIO32_USB_VP MFP_CFG_IN(GPIO32, AF2) +#define GPIO34_USB_VM MFP_CFG_IN(GPIO34, AF2) +#define GPIO39_USB_VPO MFP_CFG_OUT(GPIO39, AF3, DRIVE_LOW) +#define GPIO56_USB_VMO MFP_CFG_OUT(GPIO56, AF1, DRIVE_LOW) +#define GPIO57_USB_nOE MFP_CFG_OUT(GPIO57, AF1, DRIVE_HIGH) + +/* ASSP */ +#define GPIO28_ASSP_BITCLK_IN MFP_CFG_IN(GPIO28, AF3) +#define GPIO28_ASSP_BITCLK_OUT MFP_CFG_OUT(GPIO28, AF3, DRIVE_LOW) +#define GPIO29_ASSP_RXD MFP_CFG_IN(GPIO29, AF3) +#define GPIO30_ASSP_TXD MFP_CFG_OUT(GPIO30, AF3, DRIVE_LOW) +#define GPIO31_ASSP_SFRM_IN MFP_CFG_IN(GPIO31, AF1) +#define GPIO31_ASSP_SFRM_OUT MFP_CFG_OUT(GPIO31, AF3, DRIVE_LOW) + +/* AC97 */ +#define GPIO89_AC97_nRESET MFP_CFG_OUT(GPIO89, AF0, DRIVE_HIGH) +#endif /* CONFIG_CPU_PXA26x */ + +/* commonly used pin configurations */ +#define GPIOxx_LCD_16BPP \ + GPIO58_LCD_LDD_0, \ + GPIO59_LCD_LDD_1, \ + GPIO60_LCD_LDD_2, \ + GPIO61_LCD_LDD_3, \ + GPIO62_LCD_LDD_4, \ + GPIO63_LCD_LDD_5, \ + GPIO64_LCD_LDD_6, \ + GPIO65_LCD_LDD_7, \ + GPIO66_LCD_LDD_8, \ + GPIO67_LCD_LDD_9, \ + GPIO68_LCD_LDD_10, \ + GPIO69_LCD_LDD_11, \ + GPIO70_LCD_LDD_12, \ + GPIO71_LCD_LDD_13, \ + GPIO72_LCD_LDD_14, \ + GPIO73_LCD_LDD_15 + +#define GPIOxx_LCD_DSTN_16BPP \ + GPIOxx_LCD_16BPP, \ + GPIO74_LCD_FCLK, \ + GPIO75_LCD_LCLK, \ + GPIO76_LCD_PCLK + +#define GPIOxx_LCD_TFT_16BPP \ + GPIOxx_LCD_16BPP, \ + GPIO74_LCD_FCLK, \ + GPIO75_LCD_LCLK, \ + GPIO76_LCD_PCLK, \ + GPIO77_LCD_BIAS + +#endif /* __ASM_ARCH_MFP_PXA25X_H */ diff --git a/arch/arm/mach-pxa/mfp-pxa27x.h b/arch/arm/mach-pxa/mfp-pxa27x.h new file mode 100644 index 000000000000..9fe5601ce668 --- /dev/null +++ b/arch/arm/mach-pxa/mfp-pxa27x.h @@ -0,0 +1,471 @@ +#ifndef __ASM_ARCH_MFP_PXA27X_H +#define __ASM_ARCH_MFP_PXA27X_H + +/* + * NOTE: for those special-function bidirectional GPIOs, as described + * in the "PXA27x Developer's Manual" Section 24.4.2.1, only its input + * alternative is preserved, the direction is actually selected by the + * specific controller, and this should work in most cases. + */ + +#include "mfp-pxa2xx.h" + +/* Note: GPIO3/GPIO4 will be driven by Power I2C when PCFR/PI2C_EN + * bit is set, regardless of the GPIO configuration + */ +#define GPIO3_GPIO MFP_CFG_IN(GPIO3, AF0) +#define GPIO4_GPIO MFP_CFG_IN(GPIO4, AF0) + +/* GPIO */ +#define GPIO85_GPIO MFP_CFG_IN(GPIO85, AF0) +#define GPIO86_GPIO MFP_CFG_IN(GPIO86, AF0) +#define GPIO87_GPIO MFP_CFG_IN(GPIO87, AF0) +#define GPIO88_GPIO MFP_CFG_IN(GPIO88, AF0) +#define GPIO89_GPIO MFP_CFG_IN(GPIO89, AF0) +#define GPIO90_GPIO MFP_CFG_IN(GPIO90, AF0) +#define GPIO91_GPIO MFP_CFG_IN(GPIO91, AF0) +#define GPIO92_GPIO MFP_CFG_IN(GPIO92, AF0) +#define GPIO93_GPIO MFP_CFG_IN(GPIO93, AF0) +#define GPIO94_GPIO MFP_CFG_IN(GPIO94, AF0) +#define GPIO95_GPIO MFP_CFG_IN(GPIO95, AF0) +#define GPIO96_GPIO MFP_CFG_IN(GPIO96, AF0) +#define GPIO97_GPIO MFP_CFG_IN(GPIO97, AF0) +#define GPIO98_GPIO MFP_CFG_IN(GPIO98, AF0) +#define GPIO99_GPIO MFP_CFG_IN(GPIO99, AF0) +#define GPIO100_GPIO MFP_CFG_IN(GPIO100, AF0) +#define GPIO101_GPIO MFP_CFG_IN(GPIO101, AF0) +#define GPIO102_GPIO MFP_CFG_IN(GPIO102, AF0) +#define GPIO103_GPIO MFP_CFG_IN(GPIO103, AF0) +#define GPIO104_GPIO MFP_CFG_IN(GPIO104, AF0) +#define GPIO105_GPIO MFP_CFG_IN(GPIO105, AF0) +#define GPIO106_GPIO MFP_CFG_IN(GPIO106, AF0) +#define GPIO107_GPIO MFP_CFG_IN(GPIO107, AF0) +#define GPIO108_GPIO MFP_CFG_IN(GPIO108, AF0) +#define GPIO109_GPIO MFP_CFG_IN(GPIO109, AF0) +#define GPIO110_GPIO MFP_CFG_IN(GPIO110, AF0) +#define GPIO111_GPIO MFP_CFG_IN(GPIO111, AF0) +#define GPIO112_GPIO MFP_CFG_IN(GPIO112, AF0) +#define GPIO113_GPIO MFP_CFG_IN(GPIO113, AF0) +#define GPIO114_GPIO MFP_CFG_IN(GPIO114, AF0) +#define GPIO115_GPIO MFP_CFG_IN(GPIO115, AF0) +#define GPIO116_GPIO MFP_CFG_IN(GPIO116, AF0) +#define GPIO117_GPIO MFP_CFG_IN(GPIO117, AF0) +#define GPIO118_GPIO MFP_CFG_IN(GPIO118, AF0) +#define GPIO119_GPIO MFP_CFG_IN(GPIO119, AF0) +#define GPIO120_GPIO MFP_CFG_IN(GPIO120, AF0) + +/* Crystal and Clock Signals */ +#define GPIO9_HZ_CLK MFP_CFG_OUT(GPIO9, AF1, DRIVE_LOW) +#define GPIO10_HZ_CLK MFP_CFG_OUT(GPIO10, AF1, DRIVE_LOW) +#define GPIO11_48_MHz MFP_CFG_OUT(GPIO11, AF3, DRIVE_LOW) +#define GPIO12_48_MHz MFP_CFG_OUT(GPIO12, AF3, DRIVE_LOW) +#define GPIO13_CLK_EXT MFP_CFG_IN(GPIO13, AF1) + +/* OS Timer Signals */ +#define GPIO11_EXT_SYNC_0 MFP_CFG_IN(GPIO11, AF1) +#define GPIO12_EXT_SYNC_1 MFP_CFG_IN(GPIO12, AF1) +#define GPIO9_CHOUT_0 MFP_CFG_OUT(GPIO9, AF3, DRIVE_LOW) +#define GPIO10_CHOUT_1 MFP_CFG_OUT(GPIO10, AF3, DRIVE_LOW) +#define GPIO11_CHOUT_0 MFP_CFG_OUT(GPIO11, AF1, DRIVE_LOW) +#define GPIO12_CHOUT_1 MFP_CFG_OUT(GPIO12, AF1, DRIVE_LOW) + +/* SDRAM and Static Memory I/O Signals */ +#define GPIO20_nSDCS_2 MFP_CFG_OUT(GPIO20, AF1, DRIVE_HIGH) +#define GPIO21_nSDCS_3 MFP_CFG_OUT(GPIO21, AF1, DRIVE_HIGH) +#define GPIO15_nCS_1 MFP_CFG_OUT(GPIO15, AF2, DRIVE_HIGH) +#define GPIO78_nCS_2 MFP_CFG_OUT(GPIO78, AF2, DRIVE_HIGH) +#define GPIO79_nCS_3 MFP_CFG_OUT(GPIO79, AF2, DRIVE_HIGH) +#define GPIO80_nCS_4 MFP_CFG_OUT(GPIO80, AF2, DRIVE_HIGH) +#define GPIO33_nCS_5 MFP_CFG_OUT(GPIO33, AF2, DRIVE_HIGH) + +/* Miscellaneous I/O and DMA Signals */ +#define GPIO21_DVAL_0 MFP_CFG_OUT(GPIO21, AF2, DRIVE_HIGH) +#define GPIO116_DVAL_0 MFP_CFG_OUT(GPIO116, AF1, DRIVE_HIGH) +#define GPIO33_DVAL_1 MFP_CFG_OUT(GPIO33, AF1, DRIVE_HIGH) +#define GPIO96_DVAL_1 MFP_CFG_OUT(GPIO96, AF2, DRIVE_HIGH) +#define GPIO18_RDY MFP_CFG_IN(GPIO18, AF1) +#define GPIO20_DREQ_0 MFP_CFG_IN(GPIO20, AF1) +#define GPIO115_DREQ_0 MFP_CFG_IN(GPIO115, AF1) +#define GPIO80_DREQ_1 MFP_CFG_IN(GPIO80, AF1) +#define GPIO97_DREQ_1 MFP_CFG_IN(GPIO97, AF2) +#define GPIO85_DREQ_2 MFP_CFG_IN(GPIO85, AF2) +#define GPIO100_DREQ_2 MFP_CFG_IN(GPIO100, AF2) + +/* Alternate Bus Master Mode I/O Signals */ +#define GPIO20_MBREQ MFP_CFG_IN(GPIO20, AF2) +#define GPIO80_MBREQ MFP_CFG_IN(GPIO80, AF2) +#define GPIO96_MBREQ MFP_CFG_IN(GPIO96, AF2) +#define GPIO115_MBREQ MFP_CFG_IN(GPIO115, AF3) +#define GPIO21_MBGNT MFP_CFG_OUT(GPIO21, AF3, DRIVE_LOW) +#define GPIO33_MBGNT MFP_CFG_OUT(GPIO33, AF3, DRIVE_LOW) +#define GPIO97_MBGNT MFP_CFG_OUT(GPIO97, AF2, DRIVE_LOW) +#define GPIO116_MBGNT MFP_CFG_OUT(GPIO116, AF3, DRIVE_LOW) + +/* PC CARD */ +#define GPIO15_nPCE_1 MFP_CFG_OUT(GPIO15, AF1, DRIVE_HIGH) +#define GPIO85_nPCE_1 MFP_CFG_OUT(GPIO85, AF1, DRIVE_HIGH) +#define GPIO86_nPCE_1 MFP_CFG_OUT(GPIO86, AF1, DRIVE_HIGH) +#define GPIO102_nPCE_1 MFP_CFG_OUT(GPIO102, AF1, DRIVE_HIGH) +#define GPIO54_nPCE_2 MFP_CFG_OUT(GPIO54, AF2, DRIVE_HIGH) +#define GPIO78_nPCE_2 MFP_CFG_OUT(GPIO78, AF1, DRIVE_HIGH) +#define GPIO87_nPCE_2 MFP_CFG_IN(GPIO87, AF1) +#define GPIO55_nPREG MFP_CFG_OUT(GPIO55, AF2, DRIVE_HIGH) +#define GPIO50_nPIOR MFP_CFG_OUT(GPIO50, AF2, DRIVE_HIGH) +#define GPIO51_nPIOW MFP_CFG_OUT(GPIO51, AF2, DRIVE_HIGH) +#define GPIO49_nPWE MFP_CFG_OUT(GPIO49, AF2, DRIVE_HIGH) +#define GPIO48_nPOE MFP_CFG_OUT(GPIO48, AF2, DRIVE_HIGH) +#define GPIO57_nIOIS16 MFP_CFG_IN(GPIO57, AF1) +#define GPIO56_nPWAIT MFP_CFG_IN(GPIO56, AF1) +#define GPIO79_PSKTSEL MFP_CFG_OUT(GPIO79, AF1, DRIVE_HIGH) +#define GPIO104_PSKTSEL MFP_CFG_OUT(GPIO104, AF1, DRIVE_HIGH) + +/* I2C */ +#define GPIO117_I2C_SCL MFP_CFG_IN(GPIO117, AF1) +#define GPIO118_I2C_SDA MFP_CFG_IN(GPIO118, AF1) + +/* FFUART */ +#define GPIO9_FFUART_CTS MFP_CFG_IN(GPIO9, AF3) +#define GPIO26_FFUART_CTS MFP_CFG_IN(GPIO26, AF3) +#define GPIO35_FFUART_CTS MFP_CFG_IN(GPIO35, AF1) +#define GPIO100_FFUART_CTS MFP_CFG_IN(GPIO100, AF3) +#define GPIO10_FFUART_DCD MFP_CFG_IN(GPIO10, AF1) +#define GPIO36_FFUART_DCD MFP_CFG_IN(GPIO36, AF1) +#define GPIO33_FFUART_DSR MFP_CFG_IN(GPIO33, AF2) +#define GPIO37_FFUART_DSR MFP_CFG_IN(GPIO37, AF1) +#define GPIO38_FFUART_RI MFP_CFG_IN(GPIO38, AF1) +#define GPIO89_FFUART_RI MFP_CFG_IN(GPIO89, AF3) +#define GPIO19_FFUART_RXD MFP_CFG_IN(GPIO19, AF3) +#define GPIO33_FFUART_RXD MFP_CFG_IN(GPIO33, AF1) +#define GPIO34_FFUART_RXD MFP_CFG_IN(GPIO34, AF1) +#define GPIO41_FFUART_RXD MFP_CFG_IN(GPIO41, AF1) +#define GPIO53_FFUART_RXD MFP_CFG_IN(GPIO53, AF1) +#define GPIO85_FFUART_RXD MFP_CFG_IN(GPIO85, AF1) +#define GPIO96_FFUART_RXD MFP_CFG_IN(GPIO96, AF3) +#define GPIO102_FFUART_RXD MFP_CFG_IN(GPIO102, AF3) +#define GPIO16_FFUART_TXD MFP_CFG_OUT(GPIO16, AF3, DRIVE_HIGH) +#define GPIO37_FFUART_TXD MFP_CFG_OUT(GPIO37, AF3, DRIVE_HIGH) +#define GPIO39_FFUART_TXD MFP_CFG_OUT(GPIO39, AF2, DRIVE_HIGH) +#define GPIO83_FFUART_TXD MFP_CFG_OUT(GPIO83, AF2, DRIVE_HIGH) +#define GPIO99_FFUART_TXD MFP_CFG_OUT(GPIO99, AF3, DRIVE_HIGH) +#define GPIO27_FFUART_RTS MFP_CFG_OUT(GPIO27, AF3, DRIVE_HIGH) +#define GPIO41_FFUART_RTS MFP_CFG_OUT(GPIO41, AF2, DRIVE_HIGH) +#define GPIO83_FFUART_RTS MFP_CFG_OUT(GPIO83, AF3, DRIVE_HIGH) +#define GPIO98_FFUART_RTS MFP_CFG_OUT(GPIO98, AF3, DRIVE_HIGH) +#define GPIO40_FFUART_DTR MFP_CFG_OUT(GPIO40, AF2, DRIVE_HIGH) +#define GPIO82_FFUART_DTR MFP_CFG_OUT(GPIO82, AF3, DRIVE_HIGH) + +/* BTUART */ +#define GPIO44_BTUART_CTS MFP_CFG_IN(GPIO44, AF1) +#define GPIO42_BTUART_RXD MFP_CFG_IN(GPIO42, AF1) +#define GPIO45_BTUART_RTS MFP_CFG_OUT(GPIO45, AF2, DRIVE_HIGH) +#define GPIO45_BTUART_RTS_LPM_LOW MFP_CFG_OUT(GPIO45, AF2, DRIVE_LOW) +#define GPIO43_BTUART_TXD MFP_CFG_OUT(GPIO43, AF2, DRIVE_HIGH) +#define GPIO43_BTUART_TXD_LPM_LOW MFP_CFG_OUT(GPIO43, AF2, DRIVE_LOW) + +/* STUART */ +#define GPIO46_STUART_RXD MFP_CFG_IN(GPIO46, AF2) +#define GPIO47_STUART_TXD MFP_CFG_OUT(GPIO47, AF1, DRIVE_HIGH) + +/* FICP */ +#define GPIO42_FICP_RXD MFP_CFG_IN(GPIO42, AF2) +#define GPIO46_FICP_RXD MFP_CFG_IN(GPIO46, AF1) +#define GPIO43_FICP_TXD MFP_CFG_OUT(GPIO43, AF1, DRIVE_HIGH) +#define GPIO47_FICP_TXD MFP_CFG_OUT(GPIO47, AF2, DRIVE_HIGH) + +/* PWM 0/1/2/3 */ +#define GPIO11_PWM2_OUT MFP_CFG_OUT(GPIO11, AF2, DRIVE_LOW) +#define GPIO12_PWM3_OUT MFP_CFG_OUT(GPIO12, AF2, DRIVE_LOW) +#define GPIO16_PWM0_OUT MFP_CFG_OUT(GPIO16, AF2, DRIVE_LOW) +#define GPIO17_PWM1_OUT MFP_CFG_OUT(GPIO17, AF2, DRIVE_LOW) +#define GPIO38_PWM1_OUT MFP_CFG_OUT(GPIO38, AF3, DRIVE_LOW) +#define GPIO46_PWM2_OUT MFP_CFG_OUT(GPIO46, AF2, DRIVE_LOW) +#define GPIO47_PWM3_OUT MFP_CFG_OUT(GPIO47, AF3, DRIVE_LOW) +#define GPIO79_PWM2_OUT MFP_CFG_OUT(GPIO79, AF3, DRIVE_LOW) +#define GPIO80_PWM3_OUT MFP_CFG_OUT(GPIO80, AF3, DRIVE_LOW) +#define GPIO115_PWM1_OUT MFP_CFG_OUT(GPIO115, AF3, DRIVE_LOW) + +/* AC97 */ +#define GPIO31_AC97_SYNC MFP_CFG_OUT(GPIO31, AF2, DRIVE_LOW) +#define GPIO94_AC97_SYNC MFP_CFG_OUT(GPIO94, AF1, DRIVE_LOW) +#define GPIO30_AC97_SDATA_OUT MFP_CFG_OUT(GPIO30, AF2, DRIVE_LOW) +#define GPIO93_AC97_SDATA_OUT MFP_CFG_OUT(GPIO93, AF1, DRIVE_LOW) +#define GPIO45_AC97_SYSCLK MFP_CFG_OUT(GPIO45, AF1, DRIVE_LOW) +#define GPIO89_AC97_SYSCLK MFP_CFG_OUT(GPIO89, AF1, DRIVE_LOW) +#define GPIO98_AC97_SYSCLK MFP_CFG_OUT(GPIO98, AF1, DRIVE_LOW) +#define GPIO95_AC97_nRESET MFP_CFG_OUT(GPIO95, AF1, DRIVE_LOW) +#define GPIO113_AC97_nRESET MFP_CFG_OUT(GPIO113, AF2, DRIVE_LOW) +#define GPIO28_AC97_BITCLK MFP_CFG_IN(GPIO28, AF1) +#define GPIO29_AC97_SDATA_IN_0 MFP_CFG_IN(GPIO29, AF1) +#define GPIO116_AC97_SDATA_IN_0 MFP_CFG_IN(GPIO116, AF2) +#define GPIO99_AC97_SDATA_IN_1 MFP_CFG_IN(GPIO99, AF2) + +/* I2S */ +#define GPIO28_I2S_BITCLK_IN MFP_CFG_IN(GPIO28, AF2) +#define GPIO28_I2S_BITCLK_OUT MFP_CFG_OUT(GPIO28, AF1, DRIVE_LOW) +#define GPIO29_I2S_SDATA_IN MFP_CFG_IN(GPIO29, AF2) +#define GPIO30_I2S_SDATA_OUT MFP_CFG_OUT(GPIO30, AF1, DRIVE_LOW) +#define GPIO31_I2S_SYNC MFP_CFG_OUT(GPIO31, AF1, DRIVE_LOW) +#define GPIO113_I2S_SYSCLK MFP_CFG_OUT(GPIO113, AF1, DRIVE_LOW) + +/* SSP 1 */ +#define GPIO23_SSP1_SCLK_IN MFP_CFG_IN(GPIO23, AF2) +#define GPIO23_SSP1_SCLK MFP_CFG_OUT(GPIO23, AF2, DRIVE_LOW) +#define GPIO29_SSP1_SCLK MFP_CFG_IN(GPIO29, AF3) +#define GPIO27_SSP1_SYSCLK MFP_CFG_OUT(GPIO27, AF1, DRIVE_LOW) +#define GPIO53_SSP1_SYSCLK MFP_CFG_OUT(GPIO53, AF3, DRIVE_LOW) +#define GPIO24_SSP1_SFRM MFP_CFG_IN(GPIO24, AF2) +#define GPIO28_SSP1_SFRM MFP_CFG_IN(GPIO28, AF3) +#define GPIO25_SSP1_TXD MFP_CFG_OUT(GPIO25, AF2, DRIVE_LOW) +#define GPIO57_SSP1_TXD MFP_CFG_OUT(GPIO57, AF3, DRIVE_LOW) +#define GPIO26_SSP1_RXD MFP_CFG_IN(GPIO26, AF1) +#define GPIO27_SSP1_SCLKEN MFP_CFG_IN(GPIO27, AF2) + +/* SSP 2 */ +#define GPIO19_SSP2_SCLK MFP_CFG_IN(GPIO19, AF1) +#define GPIO22_SSP2_SCLK MFP_CFG_IN(GPIO22, AF3) +#define GPIO29_SSP2_SCLK MFP_CFG_OUT(GPIO29, AF3, DRIVE_LOW) +#define GPIO36_SSP2_SCLK MFP_CFG_IN(GPIO36, AF2) +#define GPIO50_SSP2_SCLK MFP_CFG_IN(GPIO50, AF3) +#define GPIO22_SSP2_SYSCLK MFP_CFG_OUT(GPIO22, AF2, DRIVE_LOW) +#define GPIO14_SSP2_SFRM MFP_CFG_IN(GPIO14, AF2) +#define GPIO37_SSP2_SFRM MFP_CFG_IN(GPIO37, AF2) +#define GPIO87_SSP2_SFRM MFP_CFG_OUT(GPIO87, AF3, DRIVE_LOW) +#define GPIO88_SSP2_SFRM MFP_CFG_IN(GPIO88, AF3) +#define GPIO13_SSP2_TXD MFP_CFG_OUT(GPIO13, AF1, DRIVE_LOW) +#define GPIO38_SSP2_TXD MFP_CFG_OUT(GPIO38, AF2, DRIVE_LOW) +#define GPIO87_SSP2_TXD MFP_CFG_OUT(GPIO87, AF1, DRIVE_LOW) +#define GPIO89_SSP2_TXD MFP_CFG_OUT(GPIO89, AF3, DRIVE_LOW) +#define GPIO11_SSP2_RXD MFP_CFG_IN(GPIO11, AF2) +#define GPIO29_SSP2_RXD MFP_CFG_OUT(GPIO29, AF1, DRIVE_LOW) +#define GPIO40_SSP2_RXD MFP_CFG_IN(GPIO40, AF1) +#define GPIO86_SSP2_RXD MFP_CFG_IN(GPIO86, AF1) +#define GPIO88_SSP2_RXD MFP_CFG_IN(GPIO88, AF2) +#define GPIO22_SSP2_EXTCLK MFP_CFG_IN(GPIO22, AF1) +#define GPIO27_SSP2_EXTCLK MFP_CFG_IN(GPIO27, AF1) +#define GPIO22_SSP2_SCLKEN MFP_CFG_IN(GPIO22, AF2) +#define GPIO23_SSP2_SCLKEN MFP_CFG_IN(GPIO23, AF2) + +/* SSP 3 */ +#define GPIO34_SSP3_SCLK MFP_CFG_IN(GPIO34, AF3) +#define GPIO40_SSP3_SCLK MFP_CFG_OUT(GPIO40, AF3, DRIVE_LOW) +#define GPIO52_SSP3_SCLK MFP_CFG_IN(GPIO52, AF2) +#define GPIO84_SSP3_SCLK MFP_CFG_IN(GPIO84, AF1) +#define GPIO45_SSP3_SYSCLK MFP_CFG_OUT(GPIO45, AF3, DRIVE_LOW) +#define GPIO35_SSP3_SFRM MFP_CFG_IN(GPIO35, AF3) +#define GPIO39_SSP3_SFRM MFP_CFG_IN(GPIO39, AF3) +#define GPIO83_SSP3_SFRM MFP_CFG_IN(GPIO83, AF1) +#define GPIO35_SSP3_TXD MFP_CFG_OUT(GPIO35, AF3, DRIVE_LOW) +#define GPIO38_SSP3_TXD MFP_CFG_OUT(GPIO38, AF1, DRIVE_LOW) +#define GPIO81_SSP3_TXD MFP_CFG_OUT(GPIO81, AF1, DRIVE_LOW) +#define GPIO41_SSP3_RXD MFP_CFG_IN(GPIO41, AF3) +#define GPIO82_SSP3_RXD MFP_CFG_IN(GPIO82, AF1) +#define GPIO89_SSP3_RXD MFP_CFG_IN(GPIO89, AF1) + +/* MMC */ +#define GPIO32_MMC_CLK MFP_CFG_OUT(GPIO32, AF2, DRIVE_LOW) +#define GPIO92_MMC_DAT_0 MFP_CFG_IN(GPIO92, AF1) +#define GPIO109_MMC_DAT_1 MFP_CFG_IN(GPIO109, AF1) +#define GPIO110_MMC_DAT_2 MFP_CFG_IN(GPIO110, AF1) +#define GPIO111_MMC_DAT_3 MFP_CFG_IN(GPIO111, AF1) +#define GPIO112_MMC_CMD MFP_CFG_IN(GPIO112, AF1) + +/* LCD */ +#define GPIO58_LCD_LDD_0 MFP_CFG_OUT(GPIO58, AF2, DRIVE_LOW) +#define GPIO59_LCD_LDD_1 MFP_CFG_OUT(GPIO59, AF2, DRIVE_LOW) +#define GPIO60_LCD_LDD_2 MFP_CFG_OUT(GPIO60, AF2, DRIVE_LOW) +#define GPIO61_LCD_LDD_3 MFP_CFG_OUT(GPIO61, AF2, DRIVE_LOW) +#define GPIO62_LCD_LDD_4 MFP_CFG_OUT(GPIO62, AF2, DRIVE_LOW) +#define GPIO63_LCD_LDD_5 MFP_CFG_OUT(GPIO63, AF2, DRIVE_LOW) +#define GPIO64_LCD_LDD_6 MFP_CFG_OUT(GPIO64, AF2, DRIVE_LOW) +#define GPIO65_LCD_LDD_7 MFP_CFG_OUT(GPIO65, AF2, DRIVE_LOW) +#define GPIO66_LCD_LDD_8 MFP_CFG_OUT(GPIO66, AF2, DRIVE_LOW) +#define GPIO67_LCD_LDD_9 MFP_CFG_OUT(GPIO67, AF2, DRIVE_LOW) +#define GPIO68_LCD_LDD_10 MFP_CFG_OUT(GPIO68, AF2, DRIVE_LOW) +#define GPIO69_LCD_LDD_11 MFP_CFG_OUT(GPIO69, AF2, DRIVE_LOW) +#define GPIO70_LCD_LDD_12 MFP_CFG_OUT(GPIO70, AF2, DRIVE_LOW) +#define GPIO71_LCD_LDD_13 MFP_CFG_OUT(GPIO71, AF2, DRIVE_LOW) +#define GPIO72_LCD_LDD_14 MFP_CFG_OUT(GPIO72, AF2, DRIVE_LOW) +#define GPIO73_LCD_LDD_15 MFP_CFG_OUT(GPIO73, AF2, DRIVE_LOW) +#define GPIO86_LCD_LDD_16 MFP_CFG_OUT(GPIO86, AF2, DRIVE_LOW) +#define GPIO87_LCD_LDD_17 MFP_CFG_OUT(GPIO87, AF2, DRIVE_LOW) +#define GPIO74_LCD_FCLK MFP_CFG_OUT(GPIO74, AF2, DRIVE_LOW) +#define GPIO75_LCD_LCLK MFP_CFG_OUT(GPIO75, AF2, DRIVE_LOW) +#define GPIO76_LCD_PCLK MFP_CFG_OUT(GPIO76, AF2, DRIVE_LOW) +#define GPIO77_LCD_BIAS MFP_CFG_OUT(GPIO77, AF2, DRIVE_LOW) +#define GPIO14_LCD_VSYNC MFP_CFG_IN(GPIO14, AF1) +#define GPIO19_LCD_CS MFP_CFG_OUT(GPIO19, AF2, DRIVE_LOW) + +/* Keypad */ +#define GPIO93_KP_DKIN_0 MFP_CFG_IN(GPIO93, AF1) +#define GPIO94_KP_DKIN_1 MFP_CFG_IN(GPIO94, AF1) +#define GPIO95_KP_DKIN_2 MFP_CFG_IN(GPIO95, AF1) +#define GPIO96_KP_DKIN_3 MFP_CFG_IN(GPIO96, AF1) +#define GPIO97_KP_DKIN_4 MFP_CFG_IN(GPIO97, AF1) +#define GPIO98_KP_DKIN_5 MFP_CFG_IN(GPIO98, AF1) +#define GPIO99_KP_DKIN_6 MFP_CFG_IN(GPIO99, AF1) +#define GPIO13_KP_KDIN_7 MFP_CFG_IN(GPIO13, AF2) +#define GPIO100_KP_MKIN_0 MFP_CFG_IN(GPIO100, AF1) +#define GPIO101_KP_MKIN_1 MFP_CFG_IN(GPIO101, AF1) +#define GPIO102_KP_MKIN_2 MFP_CFG_IN(GPIO102, AF1) +#define GPIO34_KP_MKIN_3 MFP_CFG_IN(GPIO34, AF2) +#define GPIO37_KP_MKIN_3 MFP_CFG_IN(GPIO37, AF3) +#define GPIO97_KP_MKIN_3 MFP_CFG_IN(GPIO97, AF3) +#define GPIO98_KP_MKIN_4 MFP_CFG_IN(GPIO98, AF3) +#define GPIO38_KP_MKIN_4 MFP_CFG_IN(GPIO38, AF2) +#define GPIO39_KP_MKIN_4 MFP_CFG_IN(GPIO39, AF1) +#define GPIO16_KP_MKIN_5 MFP_CFG_IN(GPIO16, AF1) +#define GPIO90_KP_MKIN_5 MFP_CFG_IN(GPIO90, AF1) +#define GPIO99_KP_MKIN_5 MFP_CFG_IN(GPIO99, AF3) +#define GPIO17_KP_MKIN_6 MFP_CFG_IN(GPIO17, AF1) +#define GPIO91_KP_MKIN_6 MFP_CFG_IN(GPIO91, AF1) +#define GPIO95_KP_MKIN_6 MFP_CFG_IN(GPIO95, AF3) +#define GPIO13_KP_MKIN_7 MFP_CFG_IN(GPIO13, AF3) +#define GPIO36_KP_MKIN_7 MFP_CFG_IN(GPIO36, AF3) +#define GPIO103_KP_MKOUT_0 MFP_CFG_OUT(GPIO103, AF2, DRIVE_HIGH) +#define GPIO104_KP_MKOUT_1 MFP_CFG_OUT(GPIO104, AF2, DRIVE_HIGH) +#define GPIO105_KP_MKOUT_2 MFP_CFG_OUT(GPIO105, AF2, DRIVE_HIGH) +#define GPIO106_KP_MKOUT_3 MFP_CFG_OUT(GPIO106, AF2, DRIVE_HIGH) +#define GPIO107_KP_MKOUT_4 MFP_CFG_OUT(GPIO107, AF2, DRIVE_HIGH) +#define GPIO108_KP_MKOUT_5 MFP_CFG_OUT(GPIO108, AF2, DRIVE_HIGH) +#define GPIO35_KP_MKOUT_6 MFP_CFG_OUT(GPIO35, AF2, DRIVE_HIGH) +#define GPIO22_KP_MKOUT_7 MFP_CFG_OUT(GPIO22, AF1, DRIVE_HIGH) +#define GPIO40_KP_MKOUT_6 MFP_CFG_OUT(GPIO40, AF1, DRIVE_HIGH) +#define GPIO41_KP_MKOUT_7 MFP_CFG_OUT(GPIO41, AF1, DRIVE_HIGH) +#define GPIO96_KP_MKOUT_6 MFP_CFG_OUT(GPIO96, AF3, DRIVE_HIGH) + +/* USB P3 */ +#define GPIO10_USB_P3_5 MFP_CFG_IN(GPIO10, AF3) +#define GPIO11_USB_P3_1 MFP_CFG_IN(GPIO11, AF3) +#define GPIO30_USB_P3_2 MFP_CFG_OUT(GPIO30, AF3, DRIVE_LOW) +#define GPIO31_USB_P3_6 MFP_CFG_OUT(GPIO31, AF3, DRIVE_LOW) +#define GPIO56_USB_P3_4 MFP_CFG_OUT(GPIO56, AF1, DRIVE_LOW) +#define GPIO86_USB_P3_5 MFP_CFG_IN(GPIO86, AF3) +#define GPIO87_USB_P3_1 MFP_CFG_IN(GPIO87, AF3) +#define GPIO90_USB_P3_5 MFP_CFG_IN(GPIO90, AF2) +#define GPIO91_USB_P3_1 MFP_CFG_IN(GPIO91, AF2) +#define GPIO113_USB_P3_3 MFP_CFG_IN(GPIO113, AF3) + +/* USB P2 */ +#define GPIO34_USB_P2_2 MFP_CFG_OUT(GPIO34, AF1, DRIVE_LOW) +#define GPIO35_USB_P2_1 MFP_CFG_IN(GPIO35, AF2) +#define GPIO36_USB_P2_4 MFP_CFG_OUT(GPIO36, AF1, DRIVE_LOW) +#define GPIO37_USB_P2_8 MFP_CFG_OUT(GPIO37, AF1, DRIVE_LOW) +#define GPIO38_USB_P2_3 MFP_CFG_IN(GPIO38, AF3) +#define GPIO39_USB_P2_6 MFP_CFG_OUT(GPIO39, AF1, DRIVE_LOW) +#define GPIO40_USB_P2_5 MFP_CFG_IN(GPIO40, AF3) +#define GPIO41_USB_P2_7 MFP_CFG_IN(GPIO41, AF2) +#define GPIO53_USB_P2_3 MFP_CFG_IN(GPIO53, AF2) + +/* USB Host Port 1/2 */ +#define GPIO88_USBH1_PWR MFP_CFG_IN(GPIO88, AF1) +#define GPIO89_USBH1_PEN MFP_CFG_OUT(GPIO89, AF2, DRIVE_LOW) +#define GPIO119_USBH2_PWR MFP_CFG_IN(GPIO119, AF1) +#define GPIO120_USBH2_PEN MFP_CFG_OUT(GPIO120, AF2, DRIVE_LOW) + +/* QCI - default to Master Mode: CIF_FV/CIF_LV Direction In */ +#define GPIO115_CIF_DD_3 MFP_CFG_IN(GPIO115, AF2) +#define GPIO116_CIF_DD_2 MFP_CFG_IN(GPIO116, AF1) +#define GPIO12_CIF_DD_7 MFP_CFG_IN(GPIO12, AF2) +#define GPIO17_CIF_DD_6 MFP_CFG_IN(GPIO17, AF2) +#define GPIO23_CIF_MCLK MFP_CFG_OUT(GPIO23, AF1, DRIVE_LOW) +#define GPIO24_CIF_FV MFP_CFG_IN(GPIO24, AF1) +#define GPIO25_CIF_LV MFP_CFG_IN(GPIO25, AF1) +#define GPIO26_CIF_PCLK MFP_CFG_IN(GPIO26, AF2) +#define GPIO27_CIF_DD_0 MFP_CFG_IN(GPIO27, AF3) +#define GPIO42_CIF_MCLK MFP_CFG_OUT(GPIO42, AF3, DRIVE_LOW) +#define GPIO43_CIF_FV MFP_CFG_IN(GPIO43, AF3) +#define GPIO44_CIF_LV MFP_CFG_IN(GPIO44, AF3) +#define GPIO45_CIF_PCLK MFP_CFG_IN(GPIO45, AF3) +#define GPIO47_CIF_DD_0 MFP_CFG_IN(GPIO47, AF1) +#define GPIO48_CIF_DD_5 MFP_CFG_IN(GPIO48, AF1) +#define GPIO50_CIF_DD_3 MFP_CFG_IN(GPIO50, AF1) +#define GPIO51_CIF_DD_2 MFP_CFG_IN(GPIO51, AF1) +#define GPIO52_CIF_DD_4 MFP_CFG_IN(GPIO52, AF1) +#define GPIO53_CIF_MCLK MFP_CFG_OUT(GPIO53, AF2, DRIVE_LOW) +#define GPIO54_CIF_PCLK MFP_CFG_IN(GPIO54, AF3) +#define GPIO55_CIF_DD_1 MFP_CFG_IN(GPIO55, AF1) +#define GPIO81_CIF_DD_0 MFP_CFG_IN(GPIO81, AF2) +#define GPIO82_CIF_DD_5 MFP_CFG_IN(GPIO82, AF3) +#define GPIO83_CIF_DD_4 MFP_CFG_IN(GPIO83, AF3) +#define GPIO84_CIF_FV MFP_CFG_IN(GPIO84, AF3) +#define GPIO85_CIF_LV MFP_CFG_IN(GPIO85, AF3) +#define GPIO90_CIF_DD_4 MFP_CFG_IN(GPIO90, AF3) +#define GPIO91_CIF_DD_5 MFP_CFG_IN(GPIO91, AF3) +#define GPIO93_CIF_DD_6 MFP_CFG_IN(GPIO93, AF2) +#define GPIO94_CIF_DD_5 MFP_CFG_IN(GPIO94, AF2) +#define GPIO95_CIF_DD_4 MFP_CFG_IN(GPIO95, AF2) +#define GPIO98_CIF_DD_0 MFP_CFG_IN(GPIO98, AF2) +#define GPIO103_CIF_DD_3 MFP_CFG_IN(GPIO103, AF1) +#define GPIO104_CIF_DD_2 MFP_CFG_IN(GPIO104, AF1) +#define GPIO105_CIF_DD_1 MFP_CFG_IN(GPIO105, AF1) +#define GPIO106_CIF_DD_9 MFP_CFG_IN(GPIO106, AF1) +#define GPIO107_CIF_DD_8 MFP_CFG_IN(GPIO107, AF1) +#define GPIO108_CIF_DD_7 MFP_CFG_IN(GPIO108, AF1) +#define GPIO114_CIF_DD_1 MFP_CFG_IN(GPIO114, AF1) + +/* Universal Subscriber ID Interface */ +#define GPIO114_UVS0 MFP_CFG_OUT(GPIO114, AF2, DRIVE_LOW) +#define GPIO115_nUVS1 MFP_CFG_OUT(GPIO115, AF2, DRIVE_LOW) +#define GPIO116_nUVS2 MFP_CFG_OUT(GPIO116, AF2, DRIVE_LOW) +#define GPIO14_UCLK MFP_CFG_OUT(GPIO14, AF3, DRIVE_LOW) +#define GPIO91_UCLK MFP_CFG_OUT(GPIO91, AF2, DRIVE_LOW) +#define GPIO19_nURST MFP_CFG_OUT(GPIO19, AF3, DRIVE_LOW) +#define GPIO90_nURST MFP_CFG_OUT(GPIO90, AF2, DRIVE_LOW) +#define GPIO116_UDET MFP_CFG_IN(GPIO116, AF3) +#define GPIO114_UEN MFP_CFG_OUT(GPIO114, AF1, DRIVE_LOW) +#define GPIO115_UEN MFP_CFG_OUT(GPIO115, AF1, DRIVE_LOW) + +/* Mobile Scalable Link (MSL) Interface */ +#define GPIO81_BB_OB_DAT_0 MFP_CFG_OUT(GPIO81, AF2, DRIVE_LOW) +#define GPIO48_BB_OB_DAT_1 MFP_CFG_OUT(GPIO48, AF1, DRIVE_LOW) +#define GPIO50_BB_OB_DAT_2 MFP_CFG_OUT(GPIO50, AF1, DRIVE_LOW) +#define GPIO51_BB_OB_DAT_3 MFP_CFG_OUT(GPIO51, AF1, DRIVE_LOW) +#define GPIO52_BB_OB_CLK MFP_CFG_OUT(GPIO52, AF1, DRIVE_LOW) +#define GPIO53_BB_OB_STB MFP_CFG_OUT(GPIO53, AF1, DRIVE_LOW) +#define GPIO54_BB_OB_WAIT MFP_CFG_IN(GPIO54, AF2) +#define GPIO82_BB_IB_DAT_0 MFP_CFG_IN(GPIO82, AF2) +#define GPIO55_BB_IB_DAT_1 MFP_CFG_IN(GPIO55, AF2) +#define GPIO56_BB_IB_DAT_2 MFP_CFG_IN(GPIO56, AF2) +#define GPIO57_BB_IB_DAT_3 MFP_CFG_IN(GPIO57, AF2) +#define GPIO83_BB_IB_CLK MFP_CFG_IN(GPIO83, AF2) +#define GPIO84_BB_IB_STB MFP_CFG_IN(GPIO84, AF2) +#define GPIO85_BB_IB_WAIT MFP_CFG_OUT(GPIO85, AF2, DRIVE_LOW) + +/* Memory Stick Host Controller */ +#define GPIO92_MSBS MFP_CFG_OUT(GPIO92, AF2, DRIVE_LOW) +#define GPIO109_MSSDIO MFP_CFG_IN(GPIO109, AF2) +#define GPIO112_nMSINS MFP_CFG_IN(GPIO112, AF2) +#define GPIO32_MSSCLK MFP_CFG_OUT(GPIO32, AF1, DRIVE_LOW) + +/* commonly used pin configurations */ +#define GPIOxx_LCD_16BPP \ + GPIO58_LCD_LDD_0, \ + GPIO59_LCD_LDD_1, \ + GPIO60_LCD_LDD_2, \ + GPIO61_LCD_LDD_3, \ + GPIO62_LCD_LDD_4, \ + GPIO63_LCD_LDD_5, \ + GPIO64_LCD_LDD_6, \ + GPIO65_LCD_LDD_7, \ + GPIO66_LCD_LDD_8, \ + GPIO67_LCD_LDD_9, \ + GPIO68_LCD_LDD_10, \ + GPIO69_LCD_LDD_11, \ + GPIO70_LCD_LDD_12, \ + GPIO71_LCD_LDD_13, \ + GPIO72_LCD_LDD_14, \ + GPIO73_LCD_LDD_15 + +#define GPIOxx_LCD_TFT_16BPP \ + GPIOxx_LCD_16BPP, \ + GPIO74_LCD_FCLK, \ + GPIO75_LCD_LCLK, \ + GPIO76_LCD_PCLK, \ + GPIO77_LCD_BIAS + +/* these enable a work-around for a hw bug in pxa27x during ac97 warm reset */ +#define GPIO113_AC97_nRESET_GPIO_HIGH MFP_CFG_OUT(GPIO113, AF0, DEFAULT) +#define GPIO95_AC97_nRESET_GPIO_HIGH MFP_CFG_OUT(GPIO95, AF0, DEFAULT) + +extern int keypad_set_wake(unsigned int on); +#endif /* __ASM_ARCH_MFP_PXA27X_H */ diff --git a/arch/arm/mach-pxa/mfp-pxa2xx.c b/arch/arm/mach-pxa/mfp-pxa2xx.c index 666b78972c40..3732aec76750 100644 --- a/arch/arm/mach-pxa/mfp-pxa2xx.c +++ b/arch/arm/mach-pxa/mfp-pxa2xx.c @@ -21,7 +21,7 @@ #include #include -#include +#include "mfp-pxa2xx.h" #include "generic.h" diff --git a/arch/arm/mach-pxa/mfp-pxa2xx.h b/arch/arm/mach-pxa/mfp-pxa2xx.h new file mode 100644 index 000000000000..cbf51ae81855 --- /dev/null +++ b/arch/arm/mach-pxa/mfp-pxa2xx.h @@ -0,0 +1,142 @@ +#ifndef __ASM_ARCH_MFP_PXA2XX_H +#define __ASM_ARCH_MFP_PXA2XX_H + +#include + +/* + * the following MFP_xxx bit definitions in mfp.h are re-used for pxa2xx: + * + * MFP_PIN(x) + * MFP_AFx + * MFP_LPM_DRIVE_{LOW, HIGH} + * MFP_LPM_EDGE_x + * + * other MFP_x bit definitions will be ignored + * + * and adds the below two bits specifically for pxa2xx: + * + * bit 23 - Input/Output (PXA2xx specific) + * bit 24 - Wakeup Enable(PXA2xx specific) + * bit 25 - Keep Output (PXA2xx specific) + */ + +#define MFP_DIR_IN (0x0 << 23) +#define MFP_DIR_OUT (0x1 << 23) +#define MFP_DIR_MASK (0x1 << 23) +#define MFP_DIR(x) (((x) >> 23) & 0x1) + +#define MFP_LPM_CAN_WAKEUP (0x1 << 24) + +/* + * MFP_LPM_KEEP_OUTPUT must be specified for pins that need to + * retain their last output level (low or high). + * Note: MFP_LPM_KEEP_OUTPUT has no effect on pins configured for input. + */ +#define MFP_LPM_KEEP_OUTPUT (0x1 << 25) + +#define WAKEUP_ON_EDGE_RISE (MFP_LPM_CAN_WAKEUP | MFP_LPM_EDGE_RISE) +#define WAKEUP_ON_EDGE_FALL (MFP_LPM_CAN_WAKEUP | MFP_LPM_EDGE_FALL) +#define WAKEUP_ON_EDGE_BOTH (MFP_LPM_CAN_WAKEUP | MFP_LPM_EDGE_BOTH) + +/* specifically for enabling wakeup on keypad GPIOs */ +#define WAKEUP_ON_LEVEL_HIGH (MFP_LPM_CAN_WAKEUP) + +#define MFP_CFG_IN(pin, af) \ + ((MFP_CFG_DEFAULT & ~(MFP_AF_MASK | MFP_DIR_MASK)) |\ + (MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_DIR_IN)) + +/* NOTE: pins configured as output _must_ provide a low power state, + * and this state should help to minimize the power dissipation. + */ +#define MFP_CFG_OUT(pin, af, state) \ + ((MFP_CFG_DEFAULT & ~(MFP_AF_MASK | MFP_DIR_MASK | MFP_LPM_STATE_MASK)) |\ + (MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_DIR_OUT | MFP_LPM_##state)) + +/* Common configurations for pxa25x and pxa27x + * + * Note: pins configured as GPIO are always initialized to input + * so not to cause any side effect + */ +#define GPIO0_GPIO MFP_CFG_IN(GPIO0, AF0) +#define GPIO1_GPIO MFP_CFG_IN(GPIO1, AF0) +#define GPIO9_GPIO MFP_CFG_IN(GPIO9, AF0) +#define GPIO10_GPIO MFP_CFG_IN(GPIO10, AF0) +#define GPIO11_GPIO MFP_CFG_IN(GPIO11, AF0) +#define GPIO12_GPIO MFP_CFG_IN(GPIO12, AF0) +#define GPIO13_GPIO MFP_CFG_IN(GPIO13, AF0) +#define GPIO14_GPIO MFP_CFG_IN(GPIO14, AF0) +#define GPIO15_GPIO MFP_CFG_IN(GPIO15, AF0) +#define GPIO16_GPIO MFP_CFG_IN(GPIO16, AF0) +#define GPIO17_GPIO MFP_CFG_IN(GPIO17, AF0) +#define GPIO18_GPIO MFP_CFG_IN(GPIO18, AF0) +#define GPIO19_GPIO MFP_CFG_IN(GPIO19, AF0) +#define GPIO20_GPIO MFP_CFG_IN(GPIO20, AF0) +#define GPIO21_GPIO MFP_CFG_IN(GPIO21, AF0) +#define GPIO22_GPIO MFP_CFG_IN(GPIO22, AF0) +#define GPIO23_GPIO MFP_CFG_IN(GPIO23, AF0) +#define GPIO24_GPIO MFP_CFG_IN(GPIO24, AF0) +#define GPIO25_GPIO MFP_CFG_IN(GPIO25, AF0) +#define GPIO26_GPIO MFP_CFG_IN(GPIO26, AF0) +#define GPIO27_GPIO MFP_CFG_IN(GPIO27, AF0) +#define GPIO28_GPIO MFP_CFG_IN(GPIO28, AF0) +#define GPIO29_GPIO MFP_CFG_IN(GPIO29, AF0) +#define GPIO30_GPIO MFP_CFG_IN(GPIO30, AF0) +#define GPIO31_GPIO MFP_CFG_IN(GPIO31, AF0) +#define GPIO32_GPIO MFP_CFG_IN(GPIO32, AF0) +#define GPIO33_GPIO MFP_CFG_IN(GPIO33, AF0) +#define GPIO34_GPIO MFP_CFG_IN(GPIO34, AF0) +#define GPIO35_GPIO MFP_CFG_IN(GPIO35, AF0) +#define GPIO36_GPIO MFP_CFG_IN(GPIO36, AF0) +#define GPIO37_GPIO MFP_CFG_IN(GPIO37, AF0) +#define GPIO38_GPIO MFP_CFG_IN(GPIO38, AF0) +#define GPIO39_GPIO MFP_CFG_IN(GPIO39, AF0) +#define GPIO40_GPIO MFP_CFG_IN(GPIO40, AF0) +#define GPIO41_GPIO MFP_CFG_IN(GPIO41, AF0) +#define GPIO42_GPIO MFP_CFG_IN(GPIO42, AF0) +#define GPIO43_GPIO MFP_CFG_IN(GPIO43, AF0) +#define GPIO44_GPIO MFP_CFG_IN(GPIO44, AF0) +#define GPIO45_GPIO MFP_CFG_IN(GPIO45, AF0) +#define GPIO46_GPIO MFP_CFG_IN(GPIO46, AF0) +#define GPIO47_GPIO MFP_CFG_IN(GPIO47, AF0) +#define GPIO48_GPIO MFP_CFG_IN(GPIO48, AF0) +#define GPIO49_GPIO MFP_CFG_IN(GPIO49, AF0) +#define GPIO50_GPIO MFP_CFG_IN(GPIO50, AF0) +#define GPIO51_GPIO MFP_CFG_IN(GPIO51, AF0) +#define GPIO52_GPIO MFP_CFG_IN(GPIO52, AF0) +#define GPIO53_GPIO MFP_CFG_IN(GPIO53, AF0) +#define GPIO54_GPIO MFP_CFG_IN(GPIO54, AF0) +#define GPIO55_GPIO MFP_CFG_IN(GPIO55, AF0) +#define GPIO56_GPIO MFP_CFG_IN(GPIO56, AF0) +#define GPIO57_GPIO MFP_CFG_IN(GPIO57, AF0) +#define GPIO58_GPIO MFP_CFG_IN(GPIO58, AF0) +#define GPIO59_GPIO MFP_CFG_IN(GPIO59, AF0) +#define GPIO60_GPIO MFP_CFG_IN(GPIO60, AF0) +#define GPIO61_GPIO MFP_CFG_IN(GPIO61, AF0) +#define GPIO62_GPIO MFP_CFG_IN(GPIO62, AF0) +#define GPIO63_GPIO MFP_CFG_IN(GPIO63, AF0) +#define GPIO64_GPIO MFP_CFG_IN(GPIO64, AF0) +#define GPIO65_GPIO MFP_CFG_IN(GPIO65, AF0) +#define GPIO66_GPIO MFP_CFG_IN(GPIO66, AF0) +#define GPIO67_GPIO MFP_CFG_IN(GPIO67, AF0) +#define GPIO68_GPIO MFP_CFG_IN(GPIO68, AF0) +#define GPIO69_GPIO MFP_CFG_IN(GPIO69, AF0) +#define GPIO70_GPIO MFP_CFG_IN(GPIO70, AF0) +#define GPIO71_GPIO MFP_CFG_IN(GPIO71, AF0) +#define GPIO72_GPIO MFP_CFG_IN(GPIO72, AF0) +#define GPIO73_GPIO MFP_CFG_IN(GPIO73, AF0) +#define GPIO74_GPIO MFP_CFG_IN(GPIO74, AF0) +#define GPIO75_GPIO MFP_CFG_IN(GPIO75, AF0) +#define GPIO76_GPIO MFP_CFG_IN(GPIO76, AF0) +#define GPIO77_GPIO MFP_CFG_IN(GPIO77, AF0) +#define GPIO78_GPIO MFP_CFG_IN(GPIO78, AF0) +#define GPIO79_GPIO MFP_CFG_IN(GPIO79, AF0) +#define GPIO80_GPIO MFP_CFG_IN(GPIO80, AF0) +#define GPIO81_GPIO MFP_CFG_IN(GPIO81, AF0) +#define GPIO82_GPIO MFP_CFG_IN(GPIO82, AF0) +#define GPIO83_GPIO MFP_CFG_IN(GPIO83, AF0) +#define GPIO84_GPIO MFP_CFG_IN(GPIO84, AF0) + +extern void pxa2xx_mfp_config(unsigned long *mfp_cfgs, int num); +extern void pxa2xx_mfp_set_lpm(int mfp, unsigned long lpm); +extern int gpio_set_wake(unsigned int gpio, unsigned int on); +#endif /* __ASM_ARCH_MFP_PXA2XX_H */ diff --git a/arch/arm/mach-pxa/mfp-pxa300.h b/arch/arm/mach-pxa/mfp-pxa300.h new file mode 100644 index 000000000000..5ee51e28304d --- /dev/null +++ b/arch/arm/mach-pxa/mfp-pxa300.h @@ -0,0 +1,575 @@ +/* + * arch/arm/mach-pxa/include/mach/mfp-pxa300.h + * + * PXA300/PXA310 specific MFP configuration definitions + * + * Copyright (C) 2007 Marvell International Ltd. + * 2007-08-21: eric miao + * initial version + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ASM_ARCH_MFP_PXA300_H +#define __ASM_ARCH_MFP_PXA300_H + +#include "mfp-pxa3xx.h" + +/* GPIO */ +#define GPIO46_GPIO MFP_CFG(GPIO46, AF1) +#define GPIO49_GPIO MFP_CFG(GPIO49, AF3) +#define GPIO50_GPIO MFP_CFG(GPIO50, AF2) +#define GPIO51_GPIO MFP_CFG(GPIO51, AF3) +#define GPIO52_GPIO MFP_CFG(GPIO52, AF3) +#define GPIO56_GPIO MFP_CFG(GPIO56, AF0) +#define GPIO58_GPIO MFP_CFG(GPIO58, AF0) +#define GPIO59_GPIO MFP_CFG(GPIO59, AF0) +#define GPIO60_GPIO MFP_CFG(GPIO60, AF0) +#define GPIO61_GPIO MFP_CFG(GPIO61, AF0) +#define GPIO62_GPIO MFP_CFG(GPIO62, AF0) + +#ifdef CONFIG_CPU_PXA310 +#define GPIO7_2_GPIO MFP_CFG(GPIO7_2, AF0) +#define GPIO8_2_GPIO MFP_CFG(GPIO8_2, AF0) +#define GPIO9_2_GPIO MFP_CFG(GPIO9_2, AF0) +#define GPIO10_2_GPIO MFP_CFG(GPIO10_2, AF0) +#define GPIO11_2_GPIO MFP_CFG(GPIO11_2, AF0) +#define GPIO12_2_GPIO MFP_CFG(GPIO12_2, AF0) +#endif + +/* Chip Select */ +#define GPIO1_nCS2 MFP_CFG(GPIO1, AF1) +#define GPIO2_nCS3 MFP_CFG(GPIO2, AF1) + +/* AC97 */ +#define GPIO23_AC97_nACRESET MFP_CFG(GPIO23, AF1) +#define GPIO24_AC97_SYSCLK MFP_CFG(GPIO24, AF1) +#define GPIO29_AC97_BITCLK MFP_CFG(GPIO29, AF1) +#define GPIO25_AC97_SDATA_IN_0 MFP_CFG(GPIO25, AF1) +#define GPIO26_AC97_SDATA_IN_1 MFP_CFG(GPIO26, AF1) +#define GPIO17_AC97_SDATA_IN_2 MFP_CFG(GPIO17, AF3) +#define GPIO21_AC97_SDATA_IN_2 MFP_CFG(GPIO21, AF2) +#define GPIO18_AC97_SDATA_IN_3 MFP_CFG(GPIO18, AF3) +#define GPIO22_AC97_SDATA_IN_3 MFP_CFG(GPIO22, AF2) +#define GPIO27_AC97_SDATA_OUT MFP_CFG(GPIO27, AF1) +#define GPIO28_AC97_SYNC MFP_CFG(GPIO28, AF1) + +/* I2C */ +#define GPIO21_I2C_SCL MFP_CFG_LPM(GPIO21, AF1, PULL_HIGH) +#define GPIO22_I2C_SDA MFP_CFG_LPM(GPIO22, AF1, PULL_HIGH) + +/* QCI */ +#define GPIO39_CI_DD_0 MFP_CFG_DRV(GPIO39, AF1, DS04X) +#define GPIO40_CI_DD_1 MFP_CFG_DRV(GPIO40, AF1, DS04X) +#define GPIO41_CI_DD_2 MFP_CFG_DRV(GPIO41, AF1, DS04X) +#define GPIO42_CI_DD_3 MFP_CFG_DRV(GPIO42, AF1, DS04X) +#define GPIO43_CI_DD_4 MFP_CFG_DRV(GPIO43, AF1, DS04X) +#define GPIO44_CI_DD_5 MFP_CFG_DRV(GPIO44, AF1, DS04X) +#define GPIO45_CI_DD_6 MFP_CFG_DRV(GPIO45, AF1, DS04X) +#define GPIO46_CI_DD_7 MFP_CFG_DRV(GPIO46, AF0, DS04X) +#define GPIO47_CI_DD_8 MFP_CFG_DRV(GPIO47, AF1, DS04X) +#define GPIO48_CI_DD_9 MFP_CFG_DRV(GPIO48, AF1, DS04X) +#define GPIO49_CI_MCLK MFP_CFG_DRV(GPIO49, AF0, DS04X) +#define GPIO50_CI_PCLK MFP_CFG_DRV(GPIO50, AF0, DS04X) +#define GPIO51_CI_HSYNC MFP_CFG_DRV(GPIO51, AF0, DS04X) +#define GPIO52_CI_VSYNC MFP_CFG_DRV(GPIO52, AF0, DS04X) + +/* KEYPAD */ +#define GPIO3_KP_DKIN_6 MFP_CFG_LPM(GPIO3, AF2, FLOAT) +#define GPIO4_KP_DKIN_7 MFP_CFG_LPM(GPIO4, AF2, FLOAT) +#define GPIO16_KP_DKIN_6 MFP_CFG_LPM(GPIO16, AF6, FLOAT) +#define GPIO83_KP_DKIN_2 MFP_CFG_LPM(GPIO83, AF5, FLOAT) +#define GPIO84_KP_DKIN_1 MFP_CFG_LPM(GPIO84, AF5, FLOAT) +#define GPIO85_KP_DKIN_0 MFP_CFG_LPM(GPIO85, AF3, FLOAT) +#define GPIO86_KP_DKIN_1 MFP_CFG_LPM(GPIO86, AF3, FLOAT) +#define GPIO87_KP_DKIN_2 MFP_CFG_LPM(GPIO87, AF3, FLOAT) +#define GPIO88_KP_DKIN_3 MFP_CFG_LPM(GPIO88, AF3, FLOAT) +#define GPIO89_KP_DKIN_3 MFP_CFG_LPM(GPIO89, AF3, FLOAT) +#define GPIO107_KP_DKIN_0 MFP_CFG_LPM(GPIO107, AF2, FLOAT) +#define GPIO108_KP_DKIN_1 MFP_CFG_LPM(GPIO108, AF2, FLOAT) +#define GPIO109_KP_DKIN_2 MFP_CFG_LPM(GPIO109, AF2, FLOAT) +#define GPIO110_KP_DKIN_3 MFP_CFG_LPM(GPIO110, AF2, FLOAT) +#define GPIO111_KP_DKIN_4 MFP_CFG_LPM(GPIO111, AF2, FLOAT) +#define GPIO112_KP_DKIN_5 MFP_CFG_LPM(GPIO112, AF2, FLOAT) +#define GPIO113_KP_DKIN_6 MFP_CFG_LPM(GPIO113, AF2, FLOAT) +#define GPIO114_KP_DKIN_7 MFP_CFG_LPM(GPIO114, AF2, FLOAT) +#define GPIO115_KP_DKIN_0 MFP_CFG_LPM(GPIO115, AF2, FLOAT) +#define GPIO116_KP_DKIN_1 MFP_CFG_LPM(GPIO116, AF2, FLOAT) +#define GPIO117_KP_DKIN_2 MFP_CFG_LPM(GPIO117, AF2, FLOAT) +#define GPIO118_KP_DKIN_3 MFP_CFG_LPM(GPIO118, AF2, FLOAT) +#define GPIO119_KP_DKIN_4 MFP_CFG_LPM(GPIO119, AF2, FLOAT) +#define GPIO120_KP_DKIN_5 MFP_CFG_LPM(GPIO120, AF2, FLOAT) +#define GPIO121_KP_DKIN_6 MFP_CFG_LPM(GPIO121, AF2, FLOAT) +#define GPIO122_KP_DKIN_5 MFP_CFG_LPM(GPIO122, AF2, FLOAT) +#define GPIO123_KP_DKIN_4 MFP_CFG_LPM(GPIO123, AF2, FLOAT) +#define GPIO124_KP_DKIN_3 MFP_CFG_LPM(GPIO124, AF2, FLOAT) +#define GPIO127_KP_DKIN_0 MFP_CFG_LPM(GPIO127, AF5, FLOAT) +#define GPIO0_2_KP_DKIN_0 MFP_CFG_LPM(GPIO0_2, AF2, FLOAT) +#define GPIO1_2_KP_DKIN_1 MFP_CFG_LPM(GPIO1_2, AF2, FLOAT) +#define GPIO2_2_KP_DKIN_6 MFP_CFG_LPM(GPIO2_2, AF2, FLOAT) +#define GPIO3_2_KP_DKIN_7 MFP_CFG_LPM(GPIO3_2, AF2, FLOAT) +#define GPIO4_2_KP_DKIN_1 MFP_CFG_LPM(GPIO4_2, AF2, FLOAT) +#define GPIO5_2_KP_DKIN_0 MFP_CFG_LPM(GPIO5_2, AF2, FLOAT) + +#define GPIO5_KP_MKIN_0 MFP_CFG_LPM(GPIO5, AF2, FLOAT) +#define GPIO6_KP_MKIN_1 MFP_CFG_LPM(GPIO6, AF2, FLOAT) +#define GPIO9_KP_MKIN_6 MFP_CFG_LPM(GPIO9, AF3, FLOAT) +#define GPIO10_KP_MKIN_7 MFP_CFG_LPM(GPIO10, AF3, FLOAT) +#define GPIO70_KP_MKIN_6 MFP_CFG_LPM(GPIO70, AF3, FLOAT) +#define GPIO71_KP_MKIN_7 MFP_CFG_LPM(GPIO71, AF3, FLOAT) +#define GPIO100_KP_MKIN_6 MFP_CFG_LPM(GPIO100, AF7, FLOAT) +#define GPIO101_KP_MKIN_7 MFP_CFG_LPM(GPIO101, AF7, FLOAT) +#define GPIO112_KP_MKIN_6 MFP_CFG_LPM(GPIO112, AF4, FLOAT) +#define GPIO113_KP_MKIN_7 MFP_CFG_LPM(GPIO113, AF4, FLOAT) +#define GPIO115_KP_MKIN_0 MFP_CFG_LPM(GPIO115, AF1, FLOAT) +#define GPIO116_KP_MKIN_1 MFP_CFG_LPM(GPIO116, AF1, FLOAT) +#define GPIO117_KP_MKIN_2 MFP_CFG_LPM(GPIO117, AF1, FLOAT) +#define GPIO118_KP_MKIN_3 MFP_CFG_LPM(GPIO118, AF1, FLOAT) +#define GPIO119_KP_MKIN_4 MFP_CFG_LPM(GPIO119, AF1, FLOAT) +#define GPIO120_KP_MKIN_5 MFP_CFG_LPM(GPIO120, AF1, FLOAT) +#define GPIO125_KP_MKIN_2 MFP_CFG_LPM(GPIO125, AF2, FLOAT) +#define GPIO2_2_KP_MKIN_6 MFP_CFG_LPM(GPIO2_2, AF1, FLOAT) +#define GPIO3_2_KP_MKIN_7 MFP_CFG_LPM(GPIO3_2, AF1, FLOAT) + +#define GPIO7_KP_MKOUT_5 MFP_CFG_LPM(GPIO7, AF1, DRIVE_HIGH) +#define GPIO11_KP_MKOUT_5 MFP_CFG_LPM(GPIO11, AF3, DRIVE_HIGH) +#define GPIO12_KP_MKOUT_6 MFP_CFG_LPM(GPIO12, AF3, DRIVE_HIGH) +#define GPIO13_KP_MKOUT_7 MFP_CFG_LPM(GPIO13, AF3, DRIVE_HIGH) +#define GPIO19_KP_MKOUT_4 MFP_CFG_LPM(GPIO19, AF3, DRIVE_HIGH) +#define GPIO20_KP_MKOUT_5 MFP_CFG_LPM(GPIO20, AF3, DRIVE_HIGH) +#define GPIO38_KP_MKOUT_5 MFP_CFG_LPM(GPIO38, AF5, DRIVE_HIGH) +#define GPIO53_KP_MKOUT_6 MFP_CFG_LPM(GPIO53, AF5, DRIVE_HIGH) +#define GPIO78_KP_MKOUT_7 MFP_CFG_LPM(GPIO78, AF5, DRIVE_HIGH) +#define GPIO85_KP_MKOUT_0 MFP_CFG_LPM(GPIO85, AF2, DRIVE_HIGH) +#define GPIO86_KP_MKOUT_1 MFP_CFG_LPM(GPIO86, AF2, DRIVE_HIGH) +#define GPIO87_KP_MKOUT_2 MFP_CFG_LPM(GPIO87, AF2, DRIVE_HIGH) +#define GPIO88_KP_MKOUT_3 MFP_CFG_LPM(GPIO88, AF2, DRIVE_HIGH) +#define GPIO104_KP_MKOUT_6 MFP_CFG_LPM(GPIO104, AF5, DRIVE_HIGH) +#define GPIO105_KP_MKOUT_7 MFP_CFG_LPM(GPIO105, AF5, DRIVE_HIGH) +#define GPIO121_KP_MKOUT_0 MFP_CFG_LPM(GPIO121, AF1, DRIVE_HIGH) +#define GPIO122_KP_MKOUT_1 MFP_CFG_LPM(GPIO122, AF1, DRIVE_HIGH) +#define GPIO123_KP_MKOUT_2 MFP_CFG_LPM(GPIO123, AF1, DRIVE_HIGH) +#define GPIO124_KP_MKOUT_3 MFP_CFG_LPM(GPIO124, AF1, DRIVE_HIGH) +#define GPIO125_KP_MKOUT_4 MFP_CFG_LPM(GPIO125, AF1, DRIVE_HIGH) +#define GPIO126_KP_MKOUT_7 MFP_CFG_LPM(GPIO126, AF4, DRIVE_HIGH) +#define GPIO5_2_KP_MKOUT_6 MFP_CFG_LPM(GPIO5_2, AF1, DRIVE_HIGH) +#define GPIO4_2_KP_MKOUT_5 MFP_CFG_LPM(GPIO4_2, AF1, DRIVE_HIGH) +#define GPIO6_2_KP_MKOUT_7 MFP_CFG_LPM(GPIO6_2, AF1, DRIVE_HIGH) + +/* LCD */ +#define GPIO54_LCD_LDD_0 MFP_CFG_DRV(GPIO54, AF1, DS01X) +#define GPIO55_LCD_LDD_1 MFP_CFG_DRV(GPIO55, AF1, DS01X) +#define GPIO56_LCD_LDD_2 MFP_CFG_DRV(GPIO56, AF1, DS01X) +#define GPIO57_LCD_LDD_3 MFP_CFG_DRV(GPIO57, AF1, DS01X) +#define GPIO58_LCD_LDD_4 MFP_CFG_DRV(GPIO58, AF1, DS01X) +#define GPIO59_LCD_LDD_5 MFP_CFG_DRV(GPIO59, AF1, DS01X) +#define GPIO60_LCD_LDD_6 MFP_CFG_DRV(GPIO60, AF1, DS01X) +#define GPIO61_LCD_LDD_7 MFP_CFG_DRV(GPIO61, AF1, DS01X) +#define GPIO62_LCD_LDD_8 MFP_CFG_DRV(GPIO62, AF1, DS01X) +#define GPIO63_LCD_LDD_9 MFP_CFG_DRV(GPIO63, AF1, DS01X) +#define GPIO64_LCD_LDD_10 MFP_CFG_DRV(GPIO64, AF1, DS01X) +#define GPIO65_LCD_LDD_11 MFP_CFG_DRV(GPIO65, AF1, DS01X) +#define GPIO66_LCD_LDD_12 MFP_CFG_DRV(GPIO66, AF1, DS01X) +#define GPIO67_LCD_LDD_13 MFP_CFG_DRV(GPIO67, AF1, DS01X) +#define GPIO68_LCD_LDD_14 MFP_CFG_DRV(GPIO68, AF1, DS01X) +#define GPIO69_LCD_LDD_15 MFP_CFG_DRV(GPIO69, AF1, DS01X) +#define GPIO70_LCD_LDD_16 MFP_CFG_DRV(GPIO70, AF1, DS01X) +#define GPIO71_LCD_LDD_17 MFP_CFG_DRV(GPIO71, AF1, DS01X) +#define GPIO62_LCD_CS_N MFP_CFG_DRV(GPIO62, AF2, DS01X) +#define GPIO72_LCD_FCLK MFP_CFG_DRV(GPIO72, AF1, DS01X) +#define GPIO73_LCD_LCLK MFP_CFG_DRV(GPIO73, AF1, DS01X) +#define GPIO74_LCD_PCLK MFP_CFG_DRV(GPIO74, AF1, DS02X) +#define GPIO75_LCD_BIAS MFP_CFG_DRV(GPIO75, AF1, DS01X) +#define GPIO76_LCD_VSYNC MFP_CFG_DRV(GPIO76, AF2, DS01X) + +#define GPIO15_LCD_CS_N MFP_CFG_DRV(GPIO15, AF2, DS01X) +#define GPIO127_LCD_CS_N MFP_CFG_DRV(GPIO127, AF1, DS01X) +#define GPIO63_LCD_VSYNC MFP_CFG_DRV(GPIO63, AF2, DS01X) + +/* Mini-LCD */ +#define GPIO72_MLCD_FCLK MFP_CFG_DRV(GPIO72, AF7, DS08X) +#define GPIO73_MLCD_LCLK MFP_CFG_DRV(GPIO73, AF7, DS08X) +#define GPIO54_MLCD_LDD_0 MFP_CFG_DRV(GPIO54, AF7, DS08X) +#define GPIO55_MLCD_LDD_1 MFP_CFG_DRV(GPIO55, AF7, DS08X) +#define GPIO56_MLCD_LDD_2 MFP_CFG_DRV(GPIO56, AF7, DS08X) +#define GPIO57_MLCD_LDD_3 MFP_CFG_DRV(GPIO57, AF7, DS08X) +#define GPIO58_MLCD_LDD_4 MFP_CFG_DRV(GPIO58, AF7, DS08X) +#define GPIO59_MLCD_LDD_5 MFP_CFG_DRV(GPIO59, AF7, DS08X) +#define GPIO60_MLCD_LDD_6 MFP_CFG_DRV(GPIO60, AF7, DS08X) +#define GPIO61_MLCD_LDD_7 MFP_CFG_DRV(GPIO61, AF7, DS08X) +#define GPIO62_MLCD_LDD_8 MFP_CFG_DRV(GPIO62, AF7, DS08X) +#define GPIO63_MLCD_LDD_9 MFP_CFG_DRV(GPIO63, AF7, DS08X) +#define GPIO64_MLCD_LDD_10 MFP_CFG_DRV(GPIO64, AF7, DS08X) +#define GPIO65_MLCD_LDD_11 MFP_CFG_DRV(GPIO65, AF7, DS08X) +#define GPIO66_MLCD_LDD_12 MFP_CFG_DRV(GPIO66, AF7, DS08X) +#define GPIO67_MLCD_LDD_13 MFP_CFG_DRV(GPIO67, AF7, DS08X) +#define GPIO68_MLCD_LDD_14 MFP_CFG_DRV(GPIO68, AF7, DS08X) +#define GPIO69_MLCD_LDD_15 MFP_CFG_DRV(GPIO69, AF7, DS08X) +#define GPIO74_MLCD_PCLK MFP_CFG_DRV(GPIO74, AF7, DS08X) +#define GPIO75_MLCD_BIAS MFP_CFG_DRV(GPIO75, AF2, DS08X) + +/* MMC1 */ +#define GPIO7_MMC1_CLK MFP_CFG_LPM(GPIO7, AF4, DRIVE_HIGH) +#define GPIO8_MMC1_CMD MFP_CFG_LPM(GPIO8, AF4, DRIVE_HIGH) +#define GPIO14_MMC1_CMD MFP_CFG_LPM(GPIO14, AF5, DRIVE_HIGH) +#define GPIO15_MMC1_CMD MFP_CFG_LPM(GPIO15, AF5, DRIVE_HIGH) +#define GPIO3_MMC1_DAT0 MFP_CFG_LPM(GPIO3, AF4, DRIVE_HIGH) +#define GPIO4_MMC1_DAT1 MFP_CFG_LPM(GPIO4, AF4, DRIVE_HIGH) +#define GPIO5_MMC1_DAT2 MFP_CFG_LPM(GPIO5, AF4, DRIVE_HIGH) +#define GPIO6_MMC1_DAT3 MFP_CFG_LPM(GPIO6, AF4, DRIVE_HIGH) + +/* MMC2 */ +#define GPIO9_MMC2_DAT0 MFP_CFG_LPM(GPIO9, AF4, PULL_HIGH) +#define GPIO10_MMC2_DAT1 MFP_CFG_LPM(GPIO10, AF4, PULL_HIGH) +#define GPIO11_MMC2_DAT2 MFP_CFG_LPM(GPIO11, AF4, PULL_HIGH) +#define GPIO12_MMC2_DAT3 MFP_CFG_LPM(GPIO12, AF4, PULL_HIGH) +#define GPIO13_MMC2_CLK MFP_CFG_LPM(GPIO13, AF4, PULL_HIGH) +#define GPIO14_MMC2_CMD MFP_CFG_LPM(GPIO14, AF4, PULL_HIGH) +#define GPIO77_MMC2_DAT0 MFP_CFG_LPM(GPIO77, AF4, PULL_HIGH) +#define GPIO78_MMC2_DAT1 MFP_CFG_LPM(GPIO78, AF4, PULL_HIGH) +#define GPIO79_MMC2_DAT2 MFP_CFG_LPM(GPIO79, AF4, PULL_HIGH) +#define GPIO80_MMC2_DAT3 MFP_CFG_LPM(GPIO80, AF4, PULL_HIGH) +#define GPIO81_MMC2_CLK MFP_CFG_LPM(GPIO81, AF4, PULL_HIGH) +#define GPIO82_MMC2_CMD MFP_CFG_LPM(GPIO82, AF4, PULL_HIGH) + +/* SSP1 */ +#define GPIO89_SSP1_EXTCLK MFP_CFG(GPIO89, AF1) +#define GPIO90_SSP1_SYSCLK MFP_CFG(GPIO90, AF1) +#define GPIO15_SSP1_SCLK MFP_CFG(GPIO15, AF6) +#define GPIO16_SSP1_FRM MFP_CFG(GPIO16, AF2) +#define GPIO33_SSP1_SCLK MFP_CFG(GPIO33, AF5) +#define GPIO34_SSP1_FRM MFP_CFG(GPIO34, AF5) +#define GPIO85_SSP1_SCLK MFP_CFG(GPIO85, AF1) +#define GPIO86_SSP1_FRM MFP_CFG(GPIO86, AF1) +#define GPIO18_SSP1_TXD MFP_CFG(GPIO18, AF7) +#define GPIO18_SSP1_RXD MFP_CFG(GPIO18, AF2) +#define GPIO20_SSP1_TXD MFP_CFG(GPIO20, AF2) +#define GPIO20_SSP1_RXD MFP_CFG(GPIO20, AF7) +#define GPIO35_SSP1_TXD MFP_CFG(GPIO35, AF5) +#define GPIO35_SSP1_RXD MFP_CFG(GPIO35, AF4) +#define GPIO36_SSP1_TXD MFP_CFG(GPIO36, AF5) +#define GPIO36_SSP1_RXD MFP_CFG(GPIO36, AF6) +#define GPIO87_SSP1_TXD MFP_CFG(GPIO87, AF1) +#define GPIO87_SSP1_RXD MFP_CFG(GPIO87, AF6) +#define GPIO88_SSP1_TXD MFP_CFG(GPIO88, AF6) +#define GPIO88_SSP1_RXD MFP_CFG(GPIO88, AF1) + +/* SSP2 */ +#define GPIO29_SSP2_EXTCLK MFP_CFG(GPIO29, AF2) +#define GPIO23_SSP2_SCLK MFP_CFG(GPIO23, AF2) +#define GPIO17_SSP2_FRM MFP_CFG(GPIO17, AF2) +#define GPIO25_SSP2_SCLK MFP_CFG(GPIO25, AF2) +#define GPIO26_SSP2_FRM MFP_CFG(GPIO26, AF2) +#define GPIO33_SSP2_SCLK MFP_CFG(GPIO33, AF6) +#define GPIO34_SSP2_FRM MFP_CFG(GPIO34, AF6) +#define GPIO64_SSP2_SCLK MFP_CFG(GPIO64, AF2) +#define GPIO65_SSP2_FRM MFP_CFG(GPIO65, AF2) +#define GPIO19_SSP2_TXD MFP_CFG(GPIO19, AF2) +#define GPIO19_SSP2_RXD MFP_CFG(GPIO19, AF7) +#define GPIO24_SSP2_TXD MFP_CFG(GPIO24, AF5) +#define GPIO24_SSP2_RXD MFP_CFG(GPIO24, AF4) +#define GPIO27_SSP2_TXD MFP_CFG(GPIO27, AF2) +#define GPIO27_SSP2_RXD MFP_CFG(GPIO27, AF5) +#define GPIO28_SSP2_TXD MFP_CFG(GPIO28, AF5) +#define GPIO28_SSP2_RXD MFP_CFG(GPIO28, AF2) +#define GPIO35_SSP2_TXD MFP_CFG(GPIO35, AF7) +#define GPIO35_SSP2_RXD MFP_CFG(GPIO35, AF6) +#define GPIO66_SSP2_TXD MFP_CFG(GPIO66, AF4) +#define GPIO66_SSP2_RXD MFP_CFG(GPIO66, AF2) +#define GPIO67_SSP2_TXD MFP_CFG(GPIO67, AF2) +#define GPIO67_SSP2_RXD MFP_CFG(GPIO67, AF4) +#define GPIO36_SSP2_TXD MFP_CFG(GPIO36, AF7) + +/* SSP3 */ +#define GPIO69_SSP3_FRM MFP_CFG_X(GPIO69, AF2, DS08X, DRIVE_LOW) +#define GPIO68_SSP3_SCLK MFP_CFG_X(GPIO68, AF2, DS08X, FLOAT) +#define GPIO92_SSP3_FRM MFP_CFG_X(GPIO92, AF1, DS08X, DRIVE_LOW) +#define GPIO91_SSP3_SCLK MFP_CFG_X(GPIO91, AF1, DS08X, FLOAT) +#define GPIO70_SSP3_TXD MFP_CFG_X(GPIO70, AF2, DS08X, DRIVE_LOW) +#define GPIO70_SSP3_RXD MFP_CFG_X(GPIO70, AF5, DS08X, FLOAT) +#define GPIO71_SSP3_TXD MFP_CFG_X(GPIO71, AF5, DS08X, DRIVE_LOW) +#define GPIO71_SSP3_RXD MFP_CFG_X(GPIO71, AF2, DS08X, FLOAT) +#define GPIO93_SSP3_TXD MFP_CFG_X(GPIO93, AF1, DS08X, DRIVE_LOW) +#define GPIO93_SSP3_RXD MFP_CFG_X(GPIO93, AF5, DS08X, FLOAT) +#define GPIO94_SSP3_TXD MFP_CFG_X(GPIO94, AF5, DS08X, DRIVE_LOW) +#define GPIO94_SSP3_RXD MFP_CFG_X(GPIO94, AF1, DS08X, FLOAT) + +/* SSP4 */ +#define GPIO95_SSP4_SCLK MFP_CFG_LPM(GPIO95, AF1, PULL_HIGH) +#define GPIO96_SSP4_FRM MFP_CFG_LPM(GPIO96, AF1, PULL_HIGH) +#define GPIO97_SSP4_TXD MFP_CFG_LPM(GPIO97, AF1, PULL_HIGH) +#define GPIO97_SSP4_RXD MFP_CFG_LPM(GPIO97, AF5, PULL_HIGH) +#define GPIO98_SSP4_TXD MFP_CFG_LPM(GPIO98, AF5, PULL_HIGH) +#define GPIO98_SSP4_RXD MFP_CFG_LPM(GPIO98, AF1, PULL_HIGH) + +/* UART1 */ +#define GPIO32_UART1_CTS MFP_CFG_LPM(GPIO32, AF2, FLOAT) +#define GPIO37_UART1_CTS MFP_CFG_LPM(GPIO37, AF4, FLOAT) +#define GPIO79_UART1_CTS MFP_CFG_LPM(GPIO79, AF1, FLOAT) +#define GPIO84_UART1_CTS MFP_CFG_LPM(GPIO84, AF3, FLOAT) +#define GPIO101_UART1_CTS MFP_CFG_LPM(GPIO101, AF1, FLOAT) +#define GPIO106_UART1_CTS MFP_CFG_LPM(GPIO106, AF6, FLOAT) + +#define GPIO32_UART1_RTS MFP_CFG_LPM(GPIO32, AF4, FLOAT) +#define GPIO37_UART1_RTS MFP_CFG_LPM(GPIO37, AF2, FLOAT) +#define GPIO79_UART1_RTS MFP_CFG_LPM(GPIO79, AF3, FLOAT) +#define GPIO84_UART1_RTS MFP_CFG_LPM(GPIO84, AF1, FLOAT) +#define GPIO101_UART1_RTS MFP_CFG_LPM(GPIO101, AF6, FLOAT) +#define GPIO106_UART1_RTS MFP_CFG_LPM(GPIO106, AF1, FLOAT) + +#define GPIO34_UART1_DSR MFP_CFG_LPM(GPIO34, AF2, FLOAT) +#define GPIO36_UART1_DSR MFP_CFG_LPM(GPIO36, AF4, FLOAT) +#define GPIO81_UART1_DSR MFP_CFG_LPM(GPIO81, AF1, FLOAT) +#define GPIO83_UART1_DSR MFP_CFG_LPM(GPIO83, AF3, FLOAT) +#define GPIO103_UART1_DSR MFP_CFG_LPM(GPIO103, AF1, FLOAT) +#define GPIO105_UART1_DSR MFP_CFG_LPM(GPIO105, AF6, FLOAT) + +#define GPIO34_UART1_DTR MFP_CFG_LPM(GPIO34, AF4, FLOAT) +#define GPIO36_UART1_DTR MFP_CFG_LPM(GPIO36, AF2, FLOAT) +#define GPIO81_UART1_DTR MFP_CFG_LPM(GPIO81, AF3, FLOAT) +#define GPIO83_UART1_DTR MFP_CFG_LPM(GPIO83, AF1, FLOAT) +#define GPIO103_UART1_DTR MFP_CFG_LPM(GPIO103, AF6, FLOAT) +#define GPIO105_UART1_DTR MFP_CFG_LPM(GPIO105, AF1, FLOAT) + +#define GPIO35_UART1_RI MFP_CFG_LPM(GPIO35, AF2, FLOAT) +#define GPIO82_UART1_RI MFP_CFG_LPM(GPIO82, AF1, FLOAT) +#define GPIO104_UART1_RI MFP_CFG_LPM(GPIO104, AF1, FLOAT) + +#define GPIO33_UART1_DCD MFP_CFG_LPM(GPIO33, AF2, FLOAT) +#define GPIO80_UART1_DCD MFP_CFG_LPM(GPIO80, AF1, FLOAT) +#define GPIO102_UART1_DCD MFP_CFG_LPM(GPIO102, AF1, FLOAT) + +#define GPIO30_UART1_RXD MFP_CFG_LPM(GPIO30, AF2, FLOAT) +#define GPIO31_UART1_RXD MFP_CFG_LPM(GPIO31, AF4, FLOAT) +#define GPIO77_UART1_RXD MFP_CFG_LPM(GPIO77, AF1, FLOAT) +#define GPIO78_UART1_RXD MFP_CFG_LPM(GPIO78, AF3, FLOAT) +#define GPIO99_UART1_RXD MFP_CFG_LPM(GPIO99, AF1, FLOAT) +#define GPIO100_UART1_RXD MFP_CFG_LPM(GPIO100, AF6, FLOAT) +#define GPIO102_UART1_RXD MFP_CFG_LPM(GPIO102, AF6, FLOAT) +#define GPIO104_UART1_RXD MFP_CFG_LPM(GPIO104, AF4, FLOAT) + +#define GPIO30_UART1_TXD MFP_CFG_LPM(GPIO30, AF4, FLOAT) +#define GPIO31_UART1_TXD MFP_CFG_LPM(GPIO31, AF2, FLOAT) +#define GPIO77_UART1_TXD MFP_CFG_LPM(GPIO77, AF3, FLOAT) +#define GPIO78_UART1_TXD MFP_CFG_LPM(GPIO78, AF1, FLOAT) +#define GPIO99_UART1_TXD MFP_CFG_LPM(GPIO99, AF6, FLOAT) +#define GPIO100_UART1_TXD MFP_CFG_LPM(GPIO100, AF1, FLOAT) +#define GPIO102_UART1_TXD MFP_CFG_LPM(GPIO102, AF4, FLOAT) + +/* UART2 */ +#define GPIO15_UART2_CTS MFP_CFG_LPM(GPIO15, AF3, FLOAT) +#define GPIO16_UART2_CTS MFP_CFG_LPM(GPIO16, AF5, FLOAT) +#define GPIO111_UART2_CTS MFP_CFG_LPM(GPIO111, AF3, FLOAT) +#define GPIO114_UART2_CTS MFP_CFG_LPM(GPIO114, AF1, FLOAT) + +#define GPIO15_UART2_RTS MFP_CFG_LPM(GPIO15, AF4, FLOAT) +#define GPIO16_UART2_RTS MFP_CFG_LPM(GPIO16, AF4, FLOAT) +#define GPIO114_UART2_RTS MFP_CFG_LPM(GPIO114, AF3, FLOAT) +#define GPIO111_UART2_RTS MFP_CFG_LPM(GPIO111, AF1, FLOAT) + +#define GPIO18_UART2_RXD MFP_CFG_LPM(GPIO18, AF5, FLOAT) +#define GPIO19_UART2_RXD MFP_CFG_LPM(GPIO19, AF4, FLOAT) +#define GPIO112_UART2_RXD MFP_CFG_LPM(GPIO112, AF1, FLOAT) +#define GPIO113_UART2_RXD MFP_CFG_LPM(GPIO113, AF3, FLOAT) + +#define GPIO18_UART2_TXD MFP_CFG_LPM(GPIO18, AF4, FLOAT) +#define GPIO19_UART2_TXD MFP_CFG_LPM(GPIO19, AF5, FLOAT) +#define GPIO112_UART2_TXD MFP_CFG_LPM(GPIO112, AF3, FLOAT) +#define GPIO113_UART2_TXD MFP_CFG_LPM(GPIO113, AF1, FLOAT) + +/* UART3 */ +#define GPIO91_UART3_CTS MFP_CFG_LPM(GPIO91, AF2, FLOAT) +#define GPIO92_UART3_CTS MFP_CFG_LPM(GPIO92, AF4, FLOAT) +#define GPIO107_UART3_CTS MFP_CFG_LPM(GPIO107, AF1, FLOAT) +#define GPIO108_UART3_CTS MFP_CFG_LPM(GPIO108, AF3, FLOAT) + +#define GPIO91_UART3_RTS MFP_CFG_LPM(GPIO91, AF4, FLOAT) +#define GPIO92_UART3_RTS MFP_CFG_LPM(GPIO92, AF2, FLOAT) +#define GPIO107_UART3_RTS MFP_CFG_LPM(GPIO107, AF3, FLOAT) +#define GPIO108_UART3_RTS MFP_CFG_LPM(GPIO108, AF1, FLOAT) + +#define GPIO7_UART3_RXD MFP_CFG_LPM(GPIO7, AF2, FLOAT) +#define GPIO8_UART3_RXD MFP_CFG_LPM(GPIO8, AF6, FLOAT) +#define GPIO93_UART3_RXD MFP_CFG_LPM(GPIO93, AF4, FLOAT) +#define GPIO94_UART3_RXD MFP_CFG_LPM(GPIO94, AF2, FLOAT) +#define GPIO109_UART3_RXD MFP_CFG_LPM(GPIO109, AF3, FLOAT) +#define GPIO110_UART3_RXD MFP_CFG_LPM(GPIO110, AF1, FLOAT) + +#define GPIO7_UART3_TXD MFP_CFG_LPM(GPIO7, AF6, FLOAT) +#define GPIO8_UART3_TXD MFP_CFG_LPM(GPIO8, AF2, FLOAT) +#define GPIO93_UART3_TXD MFP_CFG_LPM(GPIO93, AF2, FLOAT) +#define GPIO94_UART3_TXD MFP_CFG_LPM(GPIO94, AF4, FLOAT) +#define GPIO109_UART3_TXD MFP_CFG_LPM(GPIO109, AF1, FLOAT) +#define GPIO110_UART3_TXD MFP_CFG_LPM(GPIO110, AF3, FLOAT) + +/* USB Host */ +#define GPIO0_2_USBH_PEN MFP_CFG(GPIO0_2, AF1) +#define GPIO1_2_USBH_PWR MFP_CFG(GPIO1_2, AF1) + +/* USB P3 */ +#define GPIO77_USB_P3_1 MFP_CFG(GPIO77, AF2) +#define GPIO78_USB_P3_2 MFP_CFG(GPIO78, AF2) +#define GPIO79_USB_P3_3 MFP_CFG(GPIO79, AF2) +#define GPIO80_USB_P3_4 MFP_CFG(GPIO80, AF2) +#define GPIO81_USB_P3_5 MFP_CFG(GPIO81, AF2) +#define GPIO82_USB_P3_6 MFP_CFG(GPIO82, AF2) + +/* PWM */ +#define GPIO17_PWM0_OUT MFP_CFG(GPIO17, AF1) +#define GPIO18_PWM1_OUT MFP_CFG(GPIO18, AF1) +#define GPIO19_PWM2_OUT MFP_CFG(GPIO19, AF1) +#define GPIO20_PWM3_OUT MFP_CFG(GPIO20, AF1) + +/* CIR */ +#define GPIO8_CIR_OUT MFP_CFG(GPIO8, AF5) +#define GPIO16_CIR_OUT MFP_CFG(GPIO16, AF3) + +#define GPIO20_OW_DQ_IN MFP_CFG(GPIO20, AF5) +#define GPIO126_OW_DQ MFP_CFG(GPIO126, AF2) + +#define GPIO0_DF_RDY MFP_CFG(GPIO0, AF1) +#define GPIO7_CLK_BYPASS_XSC MFP_CFG(GPIO7, AF7) +#define GPIO17_EXT_SYNC_MVT_0 MFP_CFG(GPIO17, AF6) +#define GPIO18_EXT_SYNC_MVT_1 MFP_CFG(GPIO18, AF6) +#define GPIO19_OST_CHOUT_MVT_0 MFP_CFG(GPIO19, AF6) +#define GPIO20_OST_CHOUT_MVT_1 MFP_CFG(GPIO20, AF6) +#define GPIO49_48M_CLK MFP_CFG(GPIO49, AF2) +#define GPIO126_EXT_CLK MFP_CFG(GPIO126, AF3) +#define GPIO127_CLK_BYPASS_GB MFP_CFG(GPIO127, AF7) +#define GPIO71_EXT_MATCH_MVT MFP_CFG(GPIO71, AF6) + +#define GPIO3_uIO_IN MFP_CFG(GPIO3, AF1) + +#define GPIO4_uSIM_CARD_STATE MFP_CFG(GPIO4, AF1) +#define GPIO5_uSIM_uCLK MFP_CFG(GPIO5, AF1) +#define GPIO6_uSIM_uRST MFP_CFG(GPIO6, AF1) +#define GPIO16_uSIM_UVS_0 MFP_CFG(GPIO16, AF1) + +#define GPIO9_SCIO MFP_CFG(GPIO9, AF1) +#define GPIO20_RTC_MVT MFP_CFG(GPIO20, AF4) +#define GPIO126_RTC_MVT MFP_CFG(GPIO126, AF1) + +/* + * PXA300 specific MFP configurations + */ +#ifdef CONFIG_CPU_PXA300 +#define GPIO99_USB_P2_2 MFP_CFG(GPIO99, AF2) +#define GPIO99_USB_P2_5 MFP_CFG(GPIO99, AF3) +#define GPIO99_USB_P2_6 MFP_CFG(GPIO99, AF4) +#define GPIO100_USB_P2_2 MFP_CFG(GPIO100, AF4) +#define GPIO100_USB_P2_5 MFP_CFG(GPIO100, AF5) +#define GPIO101_USB_P2_1 MFP_CFG(GPIO101, AF2) +#define GPIO102_USB_P2_4 MFP_CFG(GPIO102, AF2) +#define GPIO104_USB_P2_3 MFP_CFG(GPIO104, AF2) +#define GPIO105_USB_P2_5 MFP_CFG(GPIO105, AF2) +#define GPIO100_USB_P2_6 MFP_CFG(GPIO100, AF2) +#define GPIO106_USB_P2_7 MFP_CFG(GPIO106, AF2) +#define GPIO103_USB_P2_8 MFP_CFG(GPIO103, AF2) + +/* U2D UTMI */ +#define GPIO38_UTM_CLK MFP_CFG(GPIO38, AF1) +#define GPIO26_U2D_RXERROR MFP_CFG(GPIO26, AF3) +#define GPIO50_U2D_RXERROR MFP_CFG(GPIO50, AF1) +#define GPIO89_U2D_RXERROR MFP_CFG(GPIO89, AF5) +#define GPIO24_UTM_RXVALID MFP_CFG(GPIO24, AF3) +#define GPIO48_UTM_RXVALID MFP_CFG(GPIO48, AF2) +#define GPIO87_UTM_RXVALID MFP_CFG(GPIO87, AF5) +#define GPIO25_UTM_RXACTIVE MFP_CFG(GPIO25, AF3) +#define GPIO47_UTM_RXACTIVE MFP_CFG(GPIO47, AF2) +#define GPIO49_UTM_RXACTIVE MFP_CFG(GPIO49, AF1) +#define GPIO88_UTM_RXACTIVE MFP_CFG(GPIO88, AF5) +#define GPIO53_UTM_TXREADY MFP_CFG(GPIO53, AF1) +#define GPIO67_UTM_LINESTATE_0 MFP_CFG(GPIO67, AF3) +#define GPIO92_UTM_LINESTATE_0 MFP_CFG(GPIO92, AF3) +#define GPIO104_UTM_LINESTATE_0 MFP_CFG(GPIO104, AF3) +#define GPIO109_UTM_LINESTATE_0 MFP_CFG(GPIO109, AF4) +#define GPIO68_UTM_LINESTATE_1 MFP_CFG(GPIO68, AF3) +#define GPIO93_UTM_LINESTATE_1 MFP_CFG(GPIO93, AF3) +#define GPIO105_UTM_LINESTATE_1 MFP_CFG(GPIO105, AF3) +#define GPIO27_U2D_OPMODE_0 MFP_CFG(GPIO27, AF4) +#define GPIO51_U2D_OPMODE_0 MFP_CFG(GPIO51, AF2) +#define GPIO90_U2D_OPMODE_0 MFP_CFG(GPIO90, AF7) +#define GPIO28_U2D_OPMODE_1 MFP_CFG(GPIO28, AF4) +#define GPIO52_U2D_OPMODE_1 MFP_CFG(GPIO52, AF2) +#define GPIO106_U2D_OPMODE_1 MFP_CFG(GPIO106, AF3) +#define GPIO110_U2D_OPMODE_1 MFP_CFG(GPIO110, AF5) +#define GPIO76_U2D_RESET MFP_CFG(GPIO76, AF1) +#define GPIO95_U2D_RESET MFP_CFG(GPIO95, AF2) +#define GPIO100_U2D_RESET MFP_CFG(GPIO100, AF3) +#define GPIO66_U2D_SUSPEND MFP_CFG(GPIO66, AF3) +#define GPIO98_U2D_SUSPEND MFP_CFG(GPIO98, AF2) +#define GPIO103_U2D_SUSPEND MFP_CFG(GPIO103, AF3) +#define GPIO65_U2D_TERM_SEL MFP_CFG(GPIO65, AF5) +#define GPIO97_U2D_TERM_SEL MFP_CFG(GPIO97, AF3) +#define GPIO102_U2D_TERM_SEL MFP_CFG(GPIO102, AF5) +#define GPIO29_U2D_TXVALID MFP_CFG(GPIO29, AF3) +#define GPIO52_U2D_TXVALID MFP_CFG(GPIO52, AF4) +#define GPIO69_U2D_TXVALID MFP_CFG(GPIO69, AF3) +#define GPIO85_U2D_TXVALID MFP_CFG(GPIO85, AF7) +#define GPIO64_U2D_XCVR_SEL MFP_CFG(GPIO64, AF5) +#define GPIO96_U2D_XCVR_SEL MFP_CFG(GPIO96, AF3) +#define GPIO101_U2D_XCVR_SEL MFP_CFG(GPIO101, AF5) +#define GPIO30_UTM_PHYDATA_0 MFP_CFG(GPIO30, AF3) +#define GPIO31_UTM_PHYDATA_1 MFP_CFG(GPIO31, AF3) +#define GPIO32_UTM_PHYDATA_2 MFP_CFG(GPIO32, AF3) +#define GPIO33_UTM_PHYDATA_3 MFP_CFG(GPIO33, AF3) +#define GPIO34_UTM_PHYDATA_4 MFP_CFG(GPIO34, AF3) +#define GPIO35_UTM_PHYDATA_5 MFP_CFG(GPIO35, AF3) +#define GPIO36_UTM_PHYDATA_6 MFP_CFG(GPIO36, AF3) +#define GPIO37_UTM_PHYDATA_7 MFP_CFG(GPIO37, AF3) +#define GPIO39_UTM_PHYDATA_0 MFP_CFG(GPIO39, AF3) +#define GPIO40_UTM_PHYDATA_1 MFP_CFG(GPIO40, AF3) +#define GPIO41_UTM_PHYDATA_2 MFP_CFG(GPIO41, AF3) +#define GPIO42_UTM_PHYDATA_3 MFP_CFG(GPIO42, AF3) +#define GPIO43_UTM_PHYDATA_4 MFP_CFG(GPIO43, AF3) +#define GPIO44_UTM_PHYDATA_5 MFP_CFG(GPIO44, AF3) +#define GPIO45_UTM_PHYDATA_6 MFP_CFG(GPIO45, AF3) +#define GPIO46_UTM_PHYDATA_7 MFP_CFG(GPIO46, AF3) +#endif /* CONFIG_CPU_PXA300 */ + +/* + * PXA310 specific MFP configurations + */ +#ifdef CONFIG_CPU_PXA310 +/* USB P2 */ +#define GPIO36_USB_P2_1 MFP_CFG(GPIO36, AF1) +#define GPIO30_USB_P2_2 MFP_CFG(GPIO30, AF1) +#define GPIO35_USB_P2_3 MFP_CFG(GPIO35, AF1) +#define GPIO32_USB_P2_4 MFP_CFG(GPIO32, AF1) +#define GPIO34_USB_P2_5 MFP_CFG(GPIO34, AF1) +#define GPIO31_USB_P2_6 MFP_CFG(GPIO31, AF1) + +/* MMC1 */ +#define GPIO24_MMC1_CMD MFP_CFG(GPIO24, AF3) +#define GPIO29_MMC1_DAT0 MFP_CFG(GPIO29, AF3) + +/* MMC3 */ +#define GPIO103_MMC3_CLK MFP_CFG(GPIO103, AF2) +#define GPIO105_MMC3_CMD MFP_CFG(GPIO105, AF2) +#define GPIO11_2_MMC3_CLK MFP_CFG(GPIO11_2, AF1) +#define GPIO12_2_MMC3_CMD MFP_CFG(GPIO12_2, AF1) +#define GPIO7_2_MMC3_DAT0 MFP_CFG(GPIO7_2, AF1) +#define GPIO8_2_MMC3_DAT1 MFP_CFG(GPIO8_2, AF1) +#define GPIO9_2_MMC3_DAT2 MFP_CFG(GPIO9_2, AF1) +#define GPIO10_2_MMC3_DAT3 MFP_CFG(GPIO10_2, AF1) + +/* ULPI */ +#define GPIO38_ULPI_CLK MFP_CFG(GPIO38, AF1) +#define GPIO30_ULPI_DATA_OUT_0 MFP_CFG(GPIO30, AF3) +#define GPIO31_ULPI_DATA_OUT_1 MFP_CFG(GPIO31, AF3) +#define GPIO32_ULPI_DATA_OUT_2 MFP_CFG(GPIO32, AF3) +#define GPIO33_ULPI_DATA_OUT_3 MFP_CFG(GPIO33, AF3) +#define GPIO34_ULPI_DATA_OUT_4 MFP_CFG(GPIO34, AF3) +#define GPIO35_ULPI_DATA_OUT_5 MFP_CFG(GPIO35, AF3) +#define GPIO36_ULPI_DATA_OUT_6 MFP_CFG(GPIO36, AF3) +#define GPIO37_ULPI_DATA_OUT_7 MFP_CFG(GPIO37, AF3) +#define GPIO33_ULPI_OTG_INTR MFP_CFG(GPIO33, AF1) + +#define ULPI_DIR MFP_CFG_DRV(ULPI_DIR, AF0, DS01X) +#define ULPI_NXT MFP_CFG_DRV(ULPI_NXT, AF0, DS01X) +#define ULPI_STP MFP_CFG_DRV(ULPI_STP, AF0, DS01X) +#endif /* CONFIG_CPU_PXA310 */ + +#endif /* __ASM_ARCH_MFP_PXA300_H */ diff --git a/arch/arm/mach-pxa/mfp-pxa320.h b/arch/arm/mach-pxa/mfp-pxa320.h new file mode 100644 index 000000000000..e8797cfc72e0 --- /dev/null +++ b/arch/arm/mach-pxa/mfp-pxa320.h @@ -0,0 +1,461 @@ +/* + * arch/arm/mach-pxa/include/mach/mfp-pxa320.h + * + * PXA320 specific MFP configuration definitions + * + * Copyright (C) 2007 Marvell International Ltd. + * 2007-08-21: eric miao + * initial version + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ASM_ARCH_MFP_PXA320_H +#define __ASM_ARCH_MFP_PXA320_H + +#include "mfp-pxa3xx.h" + +/* GPIO */ +#define GPIO46_GPIO MFP_CFG(GPIO46, AF0) +#define GPIO49_GPIO MFP_CFG(GPIO49, AF0) +#define GPIO50_GPIO MFP_CFG(GPIO50, AF0) +#define GPIO51_GPIO MFP_CFG(GPIO51, AF0) +#define GPIO52_GPIO MFP_CFG(GPIO52, AF0) + +#define GPIO7_2_GPIO MFP_CFG(GPIO7_2, AF0) +#define GPIO8_2_GPIO MFP_CFG(GPIO8_2, AF0) +#define GPIO9_2_GPIO MFP_CFG(GPIO9_2, AF0) +#define GPIO10_2_GPIO MFP_CFG(GPIO10_2, AF0) +#define GPIO11_2_GPIO MFP_CFG(GPIO11_2, AF0) +#define GPIO12_2_GPIO MFP_CFG(GPIO12_2, AF0) +#define GPIO13_2_GPIO MFP_CFG(GPIO13_2, AF0) +#define GPIO14_2_GPIO MFP_CFG(GPIO14_2, AF0) +#define GPIO15_2_GPIO MFP_CFG(GPIO15_2, AF0) +#define GPIO16_2_GPIO MFP_CFG(GPIO16_2, AF0) +#define GPIO17_2_GPIO MFP_CFG(GPIO17_2, AF0) + +/* Chip Select */ +#define GPIO3_nCS2 MFP_CFG(GPIO3, AF1) +#define GPIO4_nCS3 MFP_CFG(GPIO4, AF1) + +/* AC97 */ +#define GPIO34_AC97_SYSCLK MFP_CFG(GPIO34, AF1) +#define GPIO39_AC97_BITCLK MFP_CFG(GPIO39, AF1) +#define GPIO40_AC97_nACRESET MFP_CFG(GPIO40, AF1) +#define GPIO35_AC97_SDATA_IN_0 MFP_CFG(GPIO35, AF1) +#define GPIO36_AC97_SDATA_IN_1 MFP_CFG(GPIO36, AF1) +#define GPIO32_AC97_SDATA_IN_2 MFP_CFG(GPIO32, AF2) +#define GPIO33_AC97_SDATA_IN_3 MFP_CFG(GPIO33, AF2) +#define GPIO11_AC97_SDATA_IN_2 MFP_CFG(GPIO11, AF3) +#define GPIO12_AC97_SDATA_IN_3 MFP_CFG(GPIO12, AF3) +#define GPIO37_AC97_SDATA_OUT MFP_CFG(GPIO37, AF1) +#define GPIO38_AC97_SYNC MFP_CFG(GPIO38, AF1) + +/* I2C */ +#define GPIO32_I2C_SCL MFP_CFG_LPM(GPIO32, AF1, PULL_HIGH) +#define GPIO33_I2C_SDA MFP_CFG_LPM(GPIO33, AF1, PULL_HIGH) + +/* QCI */ +#define GPIO49_CI_DD_0 MFP_CFG_DRV(GPIO49, AF1, DS04X) +#define GPIO50_CI_DD_1 MFP_CFG_DRV(GPIO50, AF1, DS04X) +#define GPIO51_CI_DD_2 MFP_CFG_DRV(GPIO51, AF1, DS04X) +#define GPIO52_CI_DD_3 MFP_CFG_DRV(GPIO52, AF1, DS04X) +#define GPIO53_CI_DD_4 MFP_CFG_DRV(GPIO53, AF1, DS04X) +#define GPIO54_CI_DD_5 MFP_CFG_DRV(GPIO54, AF1, DS04X) +#define GPIO55_CI_DD_6 MFP_CFG_DRV(GPIO55, AF1, DS04X) +#define GPIO56_CI_DD_7 MFP_CFG_DRV(GPIO56, AF0, DS04X) +#define GPIO57_CI_DD_8 MFP_CFG_DRV(GPIO57, AF1, DS04X) +#define GPIO58_CI_DD_9 MFP_CFG_DRV(GPIO58, AF1, DS04X) +#define GPIO59_CI_MCLK MFP_CFG_DRV(GPIO59, AF0, DS04X) +#define GPIO60_CI_PCLK MFP_CFG_DRV(GPIO60, AF0, DS04X) +#define GPIO61_CI_HSYNC MFP_CFG_DRV(GPIO61, AF0, DS04X) +#define GPIO62_CI_VSYNC MFP_CFG_DRV(GPIO62, AF0, DS04X) + +#define GPIO31_CIR_OUT MFP_CFG(GPIO31, AF5) + +#define GPIO0_2_CLK_EXT MFP_CFG(GPIO0_2, AF3) +#define GPIO0_DRQ MFP_CFG(GPIO0, AF2) +#define GPIO11_EXT_SYNC0 MFP_CFG(GPIO11, AF5) +#define GPIO12_EXT_SYNC1 MFP_CFG(GPIO12, AF6) +#define GPIO0_2_HZ_CLK MFP_CFG(GPIO0_2, AF1) +#define GPIO14_HZ_CLK MFP_CFG(GPIO14, AF4) +#define GPIO30_ICP_RXD MFP_CFG(GPIO30, AF1) +#define GPIO31_ICP_TXD MFP_CFG(GPIO31, AF1) + +#define GPIO83_KP_DKIN_0 MFP_CFG_LPM(GPIO83, AF3, FLOAT) +#define GPIO84_KP_DKIN_1 MFP_CFG_LPM(GPIO84, AF3, FLOAT) +#define GPIO85_KP_DKIN_2 MFP_CFG_LPM(GPIO85, AF3, FLOAT) +#define GPIO86_KP_DKIN_3 MFP_CFG_LPM(GPIO86, AF3, FLOAT) + +#define GPIO105_KP_DKIN_0 MFP_CFG_LPM(GPIO105, AF2, FLOAT) +#define GPIO106_KP_DKIN_1 MFP_CFG_LPM(GPIO106, AF2, FLOAT) +#define GPIO107_KP_DKIN_2 MFP_CFG_LPM(GPIO107, AF2, FLOAT) +#define GPIO108_KP_DKIN_3 MFP_CFG_LPM(GPIO108, AF2, FLOAT) +#define GPIO109_KP_DKIN_4 MFP_CFG_LPM(GPIO109, AF2, FLOAT) +#define GPIO110_KP_DKIN_5 MFP_CFG_LPM(GPIO110, AF2, FLOAT) +#define GPIO111_KP_DKIN_6 MFP_CFG_LPM(GPIO111, AF2, FLOAT) +#define GPIO112_KP_DKIN_7 MFP_CFG_LPM(GPIO112, AF2, FLOAT) + +#define GPIO113_KP_DKIN_0 MFP_CFG_LPM(GPIO113, AF2, FLOAT) +#define GPIO114_KP_DKIN_1 MFP_CFG_LPM(GPIO114, AF2, FLOAT) +#define GPIO115_KP_DKIN_2 MFP_CFG_LPM(GPIO115, AF2, FLOAT) +#define GPIO116_KP_DKIN_3 MFP_CFG_LPM(GPIO116, AF2, FLOAT) +#define GPIO117_KP_DKIN_4 MFP_CFG_LPM(GPIO117, AF2, FLOAT) +#define GPIO118_KP_DKIN_5 MFP_CFG_LPM(GPIO118, AF2, FLOAT) +#define GPIO119_KP_DKIN_6 MFP_CFG_LPM(GPIO119, AF2, FLOAT) +#define GPIO120_KP_DKIN_7 MFP_CFG_LPM(GPIO120, AF2, FLOAT) + +#define GPIO127_KP_DKIN_0 MFP_CFG_LPM(GPIO127, AF2, FLOAT) +#define GPIO126_KP_DKIN_1 MFP_CFG_LPM(GPIO126, AF2, FLOAT) + +#define GPIO2_2_KP_DKIN_0 MFP_CFG_LPM(GPIO2_2, AF2, FLOAT) +#define GPIO3_2_KP_DKIN_1 MFP_CFG_LPM(GPIO3_2, AF2, FLOAT) +#define GPIO125_KP_DKIN_2 MFP_CFG_LPM(GPIO125, AF2, FLOAT) +#define GPIO124_KP_DKIN_3 MFP_CFG_LPM(GPIO124, AF2, FLOAT) +#define GPIO123_KP_DKIN_4 MFP_CFG_LPM(GPIO123, AF2, FLOAT) +#define GPIO122_KP_DKIN_5 MFP_CFG_LPM(GPIO122, AF2, FLOAT) +#define GPIO121_KP_DKIN_6 MFP_CFG_LPM(GPIO121, AF2, FLOAT) +#define GPIO4_2_KP_DKIN_7 MFP_CFG_LPM(GPIO4_2, AF2, FLOAT) + +#define GPIO113_KP_MKIN_0 MFP_CFG_LPM(GPIO113, AF1, FLOAT) +#define GPIO114_KP_MKIN_1 MFP_CFG_LPM(GPIO114, AF1, FLOAT) +#define GPIO115_KP_MKIN_2 MFP_CFG_LPM(GPIO115, AF1, FLOAT) +#define GPIO116_KP_MKIN_3 MFP_CFG_LPM(GPIO116, AF1, FLOAT) +#define GPIO117_KP_MKIN_4 MFP_CFG_LPM(GPIO117, AF1, FLOAT) +#define GPIO118_KP_MKIN_5 MFP_CFG_LPM(GPIO118, AF1, FLOAT) +#define GPIO119_KP_MKIN_6 MFP_CFG_LPM(GPIO119, AF1, FLOAT) +#define GPIO120_KP_MKIN_7 MFP_CFG_LPM(GPIO120, AF1, FLOAT) + +#define GPIO83_KP_MKOUT_0 MFP_CFG_LPM(GPIO83, AF2, DRIVE_HIGH) +#define GPIO84_KP_MKOUT_1 MFP_CFG_LPM(GPIO84, AF2, DRIVE_HIGH) +#define GPIO85_KP_MKOUT_2 MFP_CFG_LPM(GPIO85, AF2, DRIVE_HIGH) +#define GPIO86_KP_MKOUT_3 MFP_CFG_LPM(GPIO86, AF2, DRIVE_HIGH) +#define GPIO13_KP_MKOUT_4 MFP_CFG_LPM(GPIO13, AF3, DRIVE_HIGH) +#define GPIO14_KP_MKOUT_5 MFP_CFG_LPM(GPIO14, AF3, DRIVE_HIGH) + +#define GPIO121_KP_MKOUT_0 MFP_CFG_LPM(GPIO121, AF1, DRIVE_HIGH) +#define GPIO122_KP_MKOUT_1 MFP_CFG_LPM(GPIO122, AF1, DRIVE_HIGH) +#define GPIO123_KP_MKOUT_2 MFP_CFG_LPM(GPIO123, AF1, DRIVE_HIGH) +#define GPIO124_KP_MKOUT_3 MFP_CFG_LPM(GPIO124, AF1, DRIVE_HIGH) +#define GPIO125_KP_MKOUT_4 MFP_CFG_LPM(GPIO125, AF1, DRIVE_HIGH) +#define GPIO126_KP_MKOUT_5 MFP_CFG_LPM(GPIO126, AF1, DRIVE_HIGH) +#define GPIO127_KP_MKOUT_6 MFP_CFG_LPM(GPIO127, AF1, DRIVE_HIGH) +#define GPIO5_2_KP_MKOUT_7 MFP_CFG_LPM(GPIO5_2, AF1, DRIVE_HIGH) + +/* LCD */ +#define GPIO6_2_LCD_LDD_0 MFP_CFG_DRV(GPIO6_2, AF1, DS01X) +#define GPIO7_2_LCD_LDD_1 MFP_CFG_DRV(GPIO7_2, AF1, DS01X) +#define GPIO8_2_LCD_LDD_2 MFP_CFG_DRV(GPIO8_2, AF1, DS01X) +#define GPIO9_2_LCD_LDD_3 MFP_CFG_DRV(GPIO9_2, AF1, DS01X) +#define GPIO10_2_LCD_LDD_4 MFP_CFG_DRV(GPIO10_2, AF1, DS01X) +#define GPIO11_2_LCD_LDD_5 MFP_CFG_DRV(GPIO11_2, AF1, DS01X) +#define GPIO12_2_LCD_LDD_6 MFP_CFG_DRV(GPIO12_2, AF1, DS01X) +#define GPIO13_2_LCD_LDD_7 MFP_CFG_DRV(GPIO13_2, AF1, DS01X) +#define GPIO63_LCD_LDD_8 MFP_CFG_DRV(GPIO63, AF1, DS01X) +#define GPIO64_LCD_LDD_9 MFP_CFG_DRV(GPIO64, AF1, DS01X) +#define GPIO65_LCD_LDD_10 MFP_CFG_DRV(GPIO65, AF1, DS01X) +#define GPIO66_LCD_LDD_11 MFP_CFG_DRV(GPIO66, AF1, DS01X) +#define GPIO67_LCD_LDD_12 MFP_CFG_DRV(GPIO67, AF1, DS01X) +#define GPIO68_LCD_LDD_13 MFP_CFG_DRV(GPIO68, AF1, DS01X) +#define GPIO69_LCD_LDD_14 MFP_CFG_DRV(GPIO69, AF1, DS01X) +#define GPIO70_LCD_LDD_15 MFP_CFG_DRV(GPIO70, AF1, DS01X) +#define GPIO71_LCD_LDD_16 MFP_CFG_DRV(GPIO71, AF1, DS01X) +#define GPIO72_LCD_LDD_17 MFP_CFG_DRV(GPIO72, AF1, DS01X) +#define GPIO73_LCD_CS_N MFP_CFG_DRV(GPIO73, AF2, DS01X) +#define GPIO74_LCD_VSYNC MFP_CFG_DRV(GPIO74, AF2, DS01X) +#define GPIO14_2_LCD_FCLK MFP_CFG_DRV(GPIO14_2, AF1, DS01X) +#define GPIO15_2_LCD_LCLK MFP_CFG_DRV(GPIO15_2, AF1, DS01X) +#define GPIO16_2_LCD_PCLK MFP_CFG_DRV(GPIO16_2, AF1, DS01X) +#define GPIO17_2_LCD_BIAS MFP_CFG_DRV(GPIO17_2, AF1, DS01X) +#define GPIO64_LCD_VSYNC MFP_CFG_DRV(GPIO64, AF2, DS01X) +#define GPIO63_LCD_CS_N MFP_CFG_DRV(GPIO63, AF2, DS01X) + +#define GPIO6_2_MLCD_DD_0 MFP_CFG_DRV(GPIO6_2, AF7, DS08X) +#define GPIO7_2_MLCD_DD_1 MFP_CFG_DRV(GPIO7_2, AF7, DS08X) +#define GPIO8_2_MLCD_DD_2 MFP_CFG_DRV(GPIO8_2, AF7, DS08X) +#define GPIO9_2_MLCD_DD_3 MFP_CFG_DRV(GPIO9_2, AF7, DS08X) +#define GPIO10_2_MLCD_DD_4 MFP_CFG_DRV(GPIO10_2, AF7, DS08X) +#define GPIO11_2_MLCD_DD_5 MFP_CFG_DRV(GPIO11_2, AF7, DS08X) +#define GPIO12_2_MLCD_DD_6 MFP_CFG_DRV(GPIO12_2, AF7, DS08X) +#define GPIO13_2_MLCD_DD_7 MFP_CFG_DRV(GPIO13_2, AF7, DS08X) +#define GPIO63_MLCD_DD_8 MFP_CFG_DRV(GPIO63, AF7, DS08X) +#define GPIO64_MLCD_DD_9 MFP_CFG_DRV(GPIO64, AF7, DS08X) +#define GPIO65_MLCD_DD_10 MFP_CFG_DRV(GPIO65, AF7, DS08X) +#define GPIO66_MLCD_DD_11 MFP_CFG_DRV(GPIO66, AF7, DS08X) +#define GPIO67_MLCD_DD_12 MFP_CFG_DRV(GPIO67, AF7, DS08X) +#define GPIO68_MLCD_DD_13 MFP_CFG_DRV(GPIO68, AF7, DS08X) +#define GPIO69_MLCD_DD_14 MFP_CFG_DRV(GPIO69, AF7, DS08X) +#define GPIO70_MLCD_DD_15 MFP_CFG_DRV(GPIO70, AF7, DS08X) +#define GPIO71_MLCD_DD_16 MFP_CFG_DRV(GPIO71, AF7, DS08X) +#define GPIO72_MLCD_DD_17 MFP_CFG_DRV(GPIO72, AF7, DS08X) +#define GPIO73_MLCD_CS MFP_CFG_DRV(GPIO73, AF7, DS08X) +#define GPIO74_MLCD_VSYNC MFP_CFG_DRV(GPIO74, AF7, DS08X) +#define GPIO14_2_MLCD_FCLK MFP_CFG_DRV(GPIO14_2, AF7, DS08X) +#define GPIO15_2_MLCD_LCLK MFP_CFG_DRV(GPIO15_2, AF7, DS08X) +#define GPIO16_2_MLCD_PCLK MFP_CFG_DRV(GPIO16_2, AF7, DS08X) +#define GPIO17_2_MLCD_BIAS MFP_CFG_DRV(GPIO17_2, AF7, DS08X) + +/* MMC1 */ +#define GPIO9_MMC1_CMD MFP_CFG_LPM(GPIO9, AF4, DRIVE_HIGH) +#define GPIO22_MMC1_CLK MFP_CFG_LPM(GPIO22, AF4, DRIVE_HIGH) +#define GPIO23_MMC1_CMD MFP_CFG_LPM(GPIO23, AF4, DRIVE_HIGH) +#define GPIO30_MMC1_CLK MFP_CFG_LPM(GPIO30, AF4, DRIVE_HIGH) +#define GPIO31_MMC1_CMD MFP_CFG_LPM(GPIO31, AF4, DRIVE_HIGH) +#define GPIO5_MMC1_DAT0 MFP_CFG_LPM(GPIO5, AF4, DRIVE_HIGH) +#define GPIO6_MMC1_DAT1 MFP_CFG_LPM(GPIO6, AF4, DRIVE_HIGH) +#define GPIO7_MMC1_DAT2 MFP_CFG_LPM(GPIO7, AF4, DRIVE_HIGH) +#define GPIO8_MMC1_DAT3 MFP_CFG_LPM(GPIO8, AF4, DRIVE_HIGH) +#define GPIO18_MMC1_DAT0 MFP_CFG_LPM(GPIO18, AF4, DRIVE_HIGH) +#define GPIO19_MMC1_DAT1 MFP_CFG_LPM(GPIO19, AF4, DRIVE_HIGH) +#define GPIO20_MMC1_DAT2 MFP_CFG_LPM(GPIO20, AF4, DRIVE_HIGH) +#define GPIO21_MMC1_DAT3 MFP_CFG_LPM(GPIO21, AF4, DRIVE_HIGH) + +#define GPIO28_MMC2_CLK MFP_CFG_LPM(GPIO28, AF4, PULL_HIGH) +#define GPIO29_MMC2_CMD MFP_CFG_LPM(GPIO29, AF4, PULL_HIGH) +#define GPIO30_MMC2_CLK MFP_CFG_LPM(GPIO30, AF3, PULL_HIGH) +#define GPIO31_MMC2_CMD MFP_CFG_LPM(GPIO31, AF3, PULL_HIGH) +#define GPIO79_MMC2_CLK MFP_CFG_LPM(GPIO79, AF4, PULL_HIGH) +#define GPIO80_MMC2_CMD MFP_CFG_LPM(GPIO80, AF4, PULL_HIGH) + +#define GPIO5_MMC2_DAT0 MFP_CFG_LPM(GPIO5, AF2, PULL_HIGH) +#define GPIO6_MMC2_DAT1 MFP_CFG_LPM(GPIO6, AF2, PULL_HIGH) +#define GPIO7_MMC2_DAT2 MFP_CFG_LPM(GPIO7, AF2, PULL_HIGH) +#define GPIO8_MMC2_DAT3 MFP_CFG_LPM(GPIO8, AF2, PULL_HIGH) +#define GPIO24_MMC2_DAT0 MFP_CFG_LPM(GPIO24, AF4, PULL_HIGH) +#define GPIO75_MMC2_DAT0 MFP_CFG_LPM(GPIO75, AF4, PULL_HIGH) +#define GPIO25_MMC2_DAT1 MFP_CFG_LPM(GPIO25, AF4, PULL_HIGH) +#define GPIO76_MMC2_DAT1 MFP_CFG_LPM(GPIO76, AF4, PULL_HIGH) +#define GPIO26_MMC2_DAT2 MFP_CFG_LPM(GPIO26, AF4, PULL_HIGH) +#define GPIO77_MMC2_DAT2 MFP_CFG_LPM(GPIO77, AF4, PULL_HIGH) +#define GPIO27_MMC2_DAT3 MFP_CFG_LPM(GPIO27, AF4, PULL_HIGH) +#define GPIO78_MMC2_DAT3 MFP_CFG_LPM(GPIO78, AF4, PULL_HIGH) + +/* 1-Wire */ +#define GPIO14_ONE_WIRE MFP_CFG_LPM(GPIO14, AF5, FLOAT) +#define GPIO0_2_ONE_WIRE MFP_CFG_LPM(GPIO0_2, AF2, FLOAT) + +/* SSP1 */ +#define GPIO87_SSP1_EXTCLK MFP_CFG(GPIO87, AF1) +#define GPIO88_SSP1_SYSCLK MFP_CFG(GPIO88, AF1) +#define GPIO83_SSP1_SCLK MFP_CFG(GPIO83, AF1) +#define GPIO84_SSP1_SFRM MFP_CFG(GPIO84, AF1) +#define GPIO85_SSP1_RXD MFP_CFG(GPIO85, AF6) +#define GPIO85_SSP1_TXD MFP_CFG(GPIO85, AF1) +#define GPIO86_SSP1_RXD MFP_CFG(GPIO86, AF1) +#define GPIO86_SSP1_TXD MFP_CFG(GPIO86, AF6) + +/* SSP2 */ +#define GPIO39_SSP2_EXTCLK MFP_CFG(GPIO39, AF2) +#define GPIO40_SSP2_SYSCLK MFP_CFG(GPIO40, AF2) +#define GPIO12_SSP2_SCLK MFP_CFG(GPIO12, AF2) +#define GPIO35_SSP2_SCLK MFP_CFG(GPIO35, AF2) +#define GPIO36_SSP2_SFRM MFP_CFG(GPIO36, AF2) +#define GPIO37_SSP2_RXD MFP_CFG(GPIO37, AF5) +#define GPIO37_SSP2_TXD MFP_CFG(GPIO37, AF2) +#define GPIO38_SSP2_RXD MFP_CFG(GPIO38, AF2) +#define GPIO38_SSP2_TXD MFP_CFG(GPIO38, AF5) + +#define GPIO69_SSP3_SCLK MFP_CFG_X(GPIO69, AF2, DS08X, FLOAT) +#define GPIO70_SSP3_FRM MFP_CFG_X(GPIO70, AF2, DS08X, DRIVE_LOW) +#define GPIO89_SSP3_SCLK MFP_CFG_X(GPIO89, AF1, DS08X, FLOAT) +#define GPIO90_SSP3_FRM MFP_CFG_X(GPIO90, AF1, DS08X, DRIVE_LOW) +#define GPIO71_SSP3_RXD MFP_CFG_X(GPIO71, AF5, DS08X, FLOAT) +#define GPIO71_SSP3_TXD MFP_CFG_X(GPIO71, AF2, DS08X, DRIVE_LOW) +#define GPIO72_SSP3_RXD MFP_CFG_X(GPIO72, AF2, DS08X, FLOAT) +#define GPIO72_SSP3_TXD MFP_CFG_X(GPIO72, AF5, DS08X, DRIVE_LOW) +#define GPIO91_SSP3_RXD MFP_CFG_X(GPIO91, AF5, DS08X, FLOAT) +#define GPIO91_SSP3_TXD MFP_CFG_X(GPIO91, AF1, DS08X, DRIVE_LOW) +#define GPIO92_SSP3_RXD MFP_CFG_X(GPIO92, AF1, DS08X, FLOAT) +#define GPIO92_SSP3_TXD MFP_CFG_X(GPIO92, AF5, DS08X, DRIVE_LOW) + +#define GPIO93_SSP4_SCLK MFP_CFG_LPM(GPIO93, AF1, PULL_HIGH) +#define GPIO94_SSP4_FRM MFP_CFG_LPM(GPIO94, AF1, PULL_HIGH) +#define GPIO94_SSP4_RXD MFP_CFG_LPM(GPIO94, AF5, PULL_HIGH) +#define GPIO95_SSP4_RXD MFP_CFG_LPM(GPIO95, AF5, PULL_HIGH) +#define GPIO95_SSP4_TXD MFP_CFG_LPM(GPIO95, AF1, PULL_HIGH) +#define GPIO96_SSP4_RXD MFP_CFG_LPM(GPIO96, AF1, PULL_HIGH) +#define GPIO96_SSP4_TXD MFP_CFG_LPM(GPIO96, AF5, PULL_HIGH) + +/* UART1 */ +#define GPIO41_UART1_RXD MFP_CFG_LPM(GPIO41, AF2, FLOAT) +#define GPIO41_UART1_TXD MFP_CFG_LPM(GPIO41, AF4, FLOAT) +#define GPIO42_UART1_RXD MFP_CFG_LPM(GPIO42, AF4, FLOAT) +#define GPIO42_UART1_TXD MFP_CFG_LPM(GPIO42, AF2, FLOAT) +#define GPIO75_UART1_RXD MFP_CFG_LPM(GPIO75, AF1, FLOAT) +#define GPIO76_UART1_RXD MFP_CFG_LPM(GPIO76, AF3, FLOAT) +#define GPIO76_UART1_TXD MFP_CFG_LPM(GPIO76, AF1, FLOAT) +#define GPIO97_UART1_RXD MFP_CFG_LPM(GPIO97, AF1, FLOAT) +#define GPIO97_UART1_TXD MFP_CFG_LPM(GPIO97, AF6, FLOAT) +#define GPIO98_UART1_RXD MFP_CFG_LPM(GPIO98, AF6, FLOAT) +#define GPIO98_UART1_TXD MFP_CFG_LPM(GPIO98, AF1, FLOAT) +#define GPIO43_UART1_CTS MFP_CFG_LPM(GPIO43, AF2, FLOAT) +#define GPIO43_UART1_RTS MFP_CFG_LPM(GPIO43, AF4, FLOAT) +#define GPIO48_UART1_CTS MFP_CFG_LPM(GPIO48, AF4, FLOAT) +#define GPIO48_UART1_RTS MFP_CFG_LPM(GPIO48, AF2, FLOAT) +#define GPIO77_UART1_CTS MFP_CFG_LPM(GPIO77, AF1, FLOAT) +#define GPIO82_UART1_RTS MFP_CFG_LPM(GPIO82, AF1, FLOAT) +#define GPIO82_UART1_CTS MFP_CFG_LPM(GPIO82, AF3, FLOAT) +#define GPIO99_UART1_CTS MFP_CFG_LPM(GPIO99, AF1, FLOAT) +#define GPIO99_UART1_RTS MFP_CFG_LPM(GPIO99, AF6, FLOAT) +#define GPIO104_UART1_CTS MFP_CFG_LPM(GPIO104, AF6, FLOAT) +#define GPIO104_UART1_RTS MFP_CFG_LPM(GPIO104, AF1, FLOAT) +#define GPIO45_UART1_DTR MFP_CFG_LPM(GPIO45, AF4, FLOAT) +#define GPIO45_UART1_DSR MFP_CFG_LPM(GPIO45, AF2, FLOAT) +#define GPIO47_UART1_DTR MFP_CFG_LPM(GPIO47, AF2, FLOAT) +#define GPIO47_UART1_DSR MFP_CFG_LPM(GPIO47, AF4, FLOAT) +#define GPIO79_UART1_DSR MFP_CFG_LPM(GPIO79, AF1, FLOAT) +#define GPIO81_UART1_DTR MFP_CFG_LPM(GPIO81, AF1, FLOAT) +#define GPIO81_UART1_DSR MFP_CFG_LPM(GPIO81, AF3, FLOAT) +#define GPIO101_UART1_DTR MFP_CFG_LPM(GPIO101, AF6, FLOAT) +#define GPIO101_UART1_DSR MFP_CFG_LPM(GPIO101, AF1, FLOAT) +#define GPIO103_UART1_DTR MFP_CFG_LPM(GPIO103, AF1, FLOAT) +#define GPIO103_UART1_DSR MFP_CFG_LPM(GPIO103, AF6, FLOAT) +#define GPIO44_UART1_DCD MFP_CFG_LPM(GPIO44, AF2, FLOAT) +#define GPIO78_UART1_DCD MFP_CFG_LPM(GPIO78, AF1, FLOAT) +#define GPIO100_UART1_DCD MFP_CFG_LPM(GPIO100, AF1, FLOAT) +#define GPIO46_UART1_RI MFP_CFG_LPM(GPIO46, AF2, FLOAT) +#define GPIO80_UART1_RI MFP_CFG_LPM(GPIO80, AF1, FLOAT) +#define GPIO102_UART1_RI MFP_CFG_LPM(GPIO102, AF1, FLOAT) + +/* UART2 */ +#define GPIO109_UART2_CTS MFP_CFG_LPM(GPIO109, AF3, FLOAT) +#define GPIO109_UART2_RTS MFP_CFG_LPM(GPIO109, AF1, FLOAT) +#define GPIO112_UART2_CTS MFP_CFG_LPM(GPIO112, AF1, FLOAT) +#define GPIO112_UART2_RTS MFP_CFG_LPM(GPIO112, AF3, FLOAT) +#define GPIO110_UART2_RXD MFP_CFG_LPM(GPIO110, AF1, FLOAT) +#define GPIO110_UART2_TXD MFP_CFG_LPM(GPIO110, AF3, FLOAT) +#define GPIO111_UART2_RXD MFP_CFG_LPM(GPIO111, AF3, FLOAT) +#define GPIO111_UART2_TXD MFP_CFG_LPM(GPIO111, AF1, FLOAT) + +/* UART3 */ +#define GPIO89_UART3_CTS MFP_CFG_LPM(GPIO89, AF2, FLOAT) +#define GPIO89_UART3_RTS MFP_CFG_LPM(GPIO89, AF4, FLOAT) +#define GPIO90_UART3_CTS MFP_CFG_LPM(GPIO90, AF4, FLOAT) +#define GPIO90_UART3_RTS MFP_CFG_LPM(GPIO90, AF2, FLOAT) +#define GPIO105_UART3_CTS MFP_CFG_LPM(GPIO105, AF1, FLOAT) +#define GPIO105_UART3_RTS MFP_CFG_LPM(GPIO105, AF3, FLOAT) +#define GPIO106_UART3_CTS MFP_CFG_LPM(GPIO106, AF3, FLOAT) +#define GPIO106_UART3_RTS MFP_CFG_LPM(GPIO106, AF1, FLOAT) +#define GPIO30_UART3_RXD MFP_CFG_LPM(GPIO30, AF2, FLOAT) +#define GPIO30_UART3_TXD MFP_CFG_LPM(GPIO30, AF6, FLOAT) +#define GPIO31_UART3_RXD MFP_CFG_LPM(GPIO31, AF6, FLOAT) +#define GPIO31_UART3_TXD MFP_CFG_LPM(GPIO31, AF2, FLOAT) +#define GPIO91_UART3_RXD MFP_CFG_LPM(GPIO91, AF4, FLOAT) +#define GPIO91_UART3_TXD MFP_CFG_LPM(GPIO91, AF2, FLOAT) +#define GPIO92_UART3_RXD MFP_CFG_LPM(GPIO92, AF2, FLOAT) +#define GPIO92_UART3_TXD MFP_CFG_LPM(GPIO92, AF4, FLOAT) +#define GPIO107_UART3_RXD MFP_CFG_LPM(GPIO107, AF3, FLOAT) +#define GPIO107_UART3_TXD MFP_CFG_LPM(GPIO107, AF1, FLOAT) +#define GPIO108_UART3_RXD MFP_CFG_LPM(GPIO108, AF1, FLOAT) +#define GPIO108_UART3_TXD MFP_CFG_LPM(GPIO108, AF3, FLOAT) + + +/* USB 2.0 UTMI */ +#define GPIO10_UTM_CLK MFP_CFG(GPIO10, AF1) +#define GPIO36_U2D_RXERROR MFP_CFG(GPIO36, AF3) +#define GPIO60_U2D_RXERROR MFP_CFG(GPIO60, AF1) +#define GPIO87_U2D_RXERROR MFP_CFG(GPIO87, AF5) +#define GPIO34_UTM_RXVALID MFP_CFG(GPIO34, AF3) +#define GPIO58_UTM_RXVALID MFP_CFG(GPIO58, AF2) +#define GPIO85_UTM_RXVALID MFP_CFG(GPIO85, AF5) +#define GPIO35_UTM_RXACTIVE MFP_CFG(GPIO35, AF3) +#define GPIO59_UTM_RXACTIVE MFP_CFG(GPIO59, AF1) +#define GPIO86_UTM_RXACTIVE MFP_CFG(GPIO86, AF5) +#define GPIO73_UTM_TXREADY MFP_CFG(GPIO73, AF1) +#define GPIO68_UTM_LINESTATE_0 MFP_CFG(GPIO68, AF3) +#define GPIO90_UTM_LINESTATE_0 MFP_CFG(GPIO90, AF3) +#define GPIO102_UTM_LINESTATE_0 MFP_CFG(GPIO102, AF3) +#define GPIO107_UTM_LINESTATE_0 MFP_CFG(GPIO107, AF4) +#define GPIO69_UTM_LINESTATE_1 MFP_CFG(GPIO69, AF3) +#define GPIO91_UTM_LINESTATE_1 MFP_CFG(GPIO91, AF3) +#define GPIO103_UTM_LINESTATE_1 MFP_CFG(GPIO103, AF3) + +#define GPIO41_U2D_PHYDATA_0 MFP_CFG(GPIO41, AF3) +#define GPIO42_U2D_PHYDATA_1 MFP_CFG(GPIO42, AF3) +#define GPIO43_U2D_PHYDATA_2 MFP_CFG(GPIO43, AF3) +#define GPIO44_U2D_PHYDATA_3 MFP_CFG(GPIO44, AF3) +#define GPIO45_U2D_PHYDATA_4 MFP_CFG(GPIO45, AF3) +#define GPIO46_U2D_PHYDATA_5 MFP_CFG(GPIO46, AF3) +#define GPIO47_U2D_PHYDATA_6 MFP_CFG(GPIO47, AF3) +#define GPIO48_U2D_PHYDATA_7 MFP_CFG(GPIO48, AF3) + +#define GPIO49_U2D_PHYDATA_0 MFP_CFG(GPIO49, AF3) +#define GPIO50_U2D_PHYDATA_1 MFP_CFG(GPIO50, AF3) +#define GPIO51_U2D_PHYDATA_2 MFP_CFG(GPIO51, AF3) +#define GPIO52_U2D_PHYDATA_3 MFP_CFG(GPIO52, AF3) +#define GPIO53_U2D_PHYDATA_4 MFP_CFG(GPIO53, AF3) +#define GPIO54_U2D_PHYDATA_5 MFP_CFG(GPIO54, AF3) +#define GPIO55_U2D_PHYDATA_6 MFP_CFG(GPIO55, AF3) +#define GPIO56_U2D_PHYDATA_7 MFP_CFG(GPIO56, AF3) + +#define GPIO37_U2D_OPMODE0 MFP_CFG(GPIO37, AF4) +#define GPIO61_U2D_OPMODE0 MFP_CFG(GPIO61, AF2) +#define GPIO88_U2D_OPMODE0 MFP_CFG(GPIO88, AF7) + +#define GPIO38_U2D_OPMODE1 MFP_CFG(GPIO38, AF4) +#define GPIO62_U2D_OPMODE1 MFP_CFG(GPIO62, AF2) +#define GPIO104_U2D_OPMODE1 MFP_CFG(GPIO104, AF4) +#define GPIO108_U2D_OPMODE1 MFP_CFG(GPIO108, AF5) + +#define GPIO74_U2D_RESET MFP_CFG(GPIO74, AF1) +#define GPIO93_U2D_RESET MFP_CFG(GPIO93, AF2) +#define GPIO98_U2D_RESET MFP_CFG(GPIO98, AF3) + +#define GPIO67_U2D_SUSPEND MFP_CFG(GPIO67, AF3) +#define GPIO96_U2D_SUSPEND MFP_CFG(GPIO96, AF2) +#define GPIO101_U2D_SUSPEND MFP_CFG(GPIO101, AF3) + +#define GPIO66_U2D_TERM_SEL MFP_CFG(GPIO66, AF5) +#define GPIO95_U2D_TERM_SEL MFP_CFG(GPIO95, AF3) +#define GPIO97_U2D_TERM_SEL MFP_CFG(GPIO97, AF7) +#define GPIO100_U2D_TERM_SEL MFP_CFG(GPIO100, AF5) + +#define GPIO39_U2D_TXVALID MFP_CFG(GPIO39, AF4) +#define GPIO70_U2D_TXVALID MFP_CFG(GPIO70, AF5) +#define GPIO83_U2D_TXVALID MFP_CFG(GPIO83, AF7) + +#define GPIO65_U2D_XCVR_SEL MFP_CFG(GPIO65, AF5) +#define GPIO94_U2D_XCVR_SEL MFP_CFG(GPIO94, AF3) +#define GPIO99_U2D_XCVR_SEL MFP_CFG(GPIO99, AF5) + +/* USB Host 1.1 */ +#define GPIO2_2_USBH_PEN MFP_CFG(GPIO2_2, AF1) +#define GPIO3_2_USBH_PWR MFP_CFG(GPIO3_2, AF1) + +/* USB P2 */ +#define GPIO97_USB_P2_2 MFP_CFG(GPIO97, AF2) +#define GPIO97_USB_P2_6 MFP_CFG(GPIO97, AF4) +#define GPIO98_USB_P2_2 MFP_CFG(GPIO98, AF4) +#define GPIO98_USB_P2_6 MFP_CFG(GPIO98, AF2) +#define GPIO99_USB_P2_1 MFP_CFG(GPIO99, AF2) +#define GPIO100_USB_P2_4 MFP_CFG(GPIO100, AF2) +#define GPIO101_USB_P2_8 MFP_CFG(GPIO101, AF2) +#define GPIO102_USB_P2_3 MFP_CFG(GPIO102, AF2) +#define GPIO103_USB_P2_5 MFP_CFG(GPIO103, AF2) +#define GPIO104_USB_P2_7 MFP_CFG(GPIO104, AF2) + +/* USB P3 */ +#define GPIO75_USB_P3_1 MFP_CFG(GPIO75, AF2) +#define GPIO76_USB_P3_2 MFP_CFG(GPIO76, AF2) +#define GPIO77_USB_P3_3 MFP_CFG(GPIO77, AF2) +#define GPIO78_USB_P3_4 MFP_CFG(GPIO78, AF2) +#define GPIO79_USB_P3_5 MFP_CFG(GPIO79, AF2) +#define GPIO80_USB_P3_6 MFP_CFG(GPIO80, AF2) + +#define GPIO13_CHOUT0 MFP_CFG(GPIO13, AF6) +#define GPIO14_CHOUT1 MFP_CFG(GPIO14, AF6) + +#define GPIO2_RDY MFP_CFG(GPIO2, AF1) +#define GPIO5_NPIOR MFP_CFG(GPIO5, AF3) +#define GPIO6_NPIOW MFP_CFG(GPIO6, AF3) +#define GPIO7_NPIOS16 MFP_CFG(GPIO7, AF3) +#define GPIO8_NPWAIT MFP_CFG(GPIO8, AF3) + +#define GPIO11_PWM0_OUT MFP_CFG(GPIO11, AF1) +#define GPIO12_PWM1_OUT MFP_CFG(GPIO12, AF1) +#define GPIO13_PWM2_OUT MFP_CFG(GPIO13, AF1) +#define GPIO14_PWM3_OUT MFP_CFG(GPIO14, AF1) + +#endif /* __ASM_ARCH_MFP_PXA320_H */ diff --git a/arch/arm/mach-pxa/mfp-pxa3xx.c b/arch/arm/mach-pxa/mfp-pxa3xx.c index 89863a01ecd7..994edc0158d4 100644 --- a/arch/arm/mach-pxa/mfp-pxa3xx.c +++ b/arch/arm/mach-pxa/mfp-pxa3xx.c @@ -20,7 +20,7 @@ #include #include -#include +#include "mfp-pxa3xx.h" #include #ifdef CONFIG_PM diff --git a/arch/arm/mach-pxa/mfp-pxa3xx.h b/arch/arm/mach-pxa/mfp-pxa3xx.h new file mode 100644 index 000000000000..d375195d982b --- /dev/null +++ b/arch/arm/mach-pxa/mfp-pxa3xx.h @@ -0,0 +1,158 @@ +#ifndef __ASM_ARCH_MFP_PXA3XX_H +#define __ASM_ARCH_MFP_PXA3XX_H + +#include + +#define MFPR_BASE (0x40e10000) + +/* PXA3xx common MFP configurations - processor specific ones defined + * in mfp-pxa300.h and mfp-pxa320.h + */ +#define GPIO0_GPIO MFP_CFG(GPIO0, AF0) +#define GPIO1_GPIO MFP_CFG(GPIO1, AF0) +#define GPIO2_GPIO MFP_CFG(GPIO2, AF0) +#define GPIO3_GPIO MFP_CFG(GPIO3, AF0) +#define GPIO4_GPIO MFP_CFG(GPIO4, AF0) +#define GPIO5_GPIO MFP_CFG(GPIO5, AF0) +#define GPIO6_GPIO MFP_CFG(GPIO6, AF0) +#define GPIO7_GPIO MFP_CFG(GPIO7, AF0) +#define GPIO8_GPIO MFP_CFG(GPIO8, AF0) +#define GPIO9_GPIO MFP_CFG(GPIO9, AF0) +#define GPIO10_GPIO MFP_CFG(GPIO10, AF0) +#define GPIO11_GPIO MFP_CFG(GPIO11, AF0) +#define GPIO12_GPIO MFP_CFG(GPIO12, AF0) +#define GPIO13_GPIO MFP_CFG(GPIO13, AF0) +#define GPIO14_GPIO MFP_CFG(GPIO14, AF0) +#define GPIO15_GPIO MFP_CFG(GPIO15, AF0) +#define GPIO16_GPIO MFP_CFG(GPIO16, AF0) +#define GPIO17_GPIO MFP_CFG(GPIO17, AF0) +#define GPIO18_GPIO MFP_CFG(GPIO18, AF0) +#define GPIO19_GPIO MFP_CFG(GPIO19, AF0) +#define GPIO20_GPIO MFP_CFG(GPIO20, AF0) +#define GPIO21_GPIO MFP_CFG(GPIO21, AF0) +#define GPIO22_GPIO MFP_CFG(GPIO22, AF0) +#define GPIO23_GPIO MFP_CFG(GPIO23, AF0) +#define GPIO24_GPIO MFP_CFG(GPIO24, AF0) +#define GPIO25_GPIO MFP_CFG(GPIO25, AF0) +#define GPIO26_GPIO MFP_CFG(GPIO26, AF0) +#define GPIO27_GPIO MFP_CFG(GPIO27, AF0) +#define GPIO28_GPIO MFP_CFG(GPIO28, AF0) +#define GPIO29_GPIO MFP_CFG(GPIO29, AF0) +#define GPIO30_GPIO MFP_CFG(GPIO30, AF0) +#define GPIO31_GPIO MFP_CFG(GPIO31, AF0) +#define GPIO32_GPIO MFP_CFG(GPIO32, AF0) +#define GPIO33_GPIO MFP_CFG(GPIO33, AF0) +#define GPIO34_GPIO MFP_CFG(GPIO34, AF0) +#define GPIO35_GPIO MFP_CFG(GPIO35, AF0) +#define GPIO36_GPIO MFP_CFG(GPIO36, AF0) +#define GPIO37_GPIO MFP_CFG(GPIO37, AF0) +#define GPIO38_GPIO MFP_CFG(GPIO38, AF0) +#define GPIO39_GPIO MFP_CFG(GPIO39, AF0) +#define GPIO40_GPIO MFP_CFG(GPIO40, AF0) +#define GPIO41_GPIO MFP_CFG(GPIO41, AF0) +#define GPIO42_GPIO MFP_CFG(GPIO42, AF0) +#define GPIO43_GPIO MFP_CFG(GPIO43, AF0) +#define GPIO44_GPIO MFP_CFG(GPIO44, AF0) +#define GPIO45_GPIO MFP_CFG(GPIO45, AF0) + +#define GPIO47_GPIO MFP_CFG(GPIO47, AF0) +#define GPIO48_GPIO MFP_CFG(GPIO48, AF0) + +#define GPIO53_GPIO MFP_CFG(GPIO53, AF0) +#define GPIO54_GPIO MFP_CFG(GPIO54, AF0) +#define GPIO55_GPIO MFP_CFG(GPIO55, AF0) + +#define GPIO57_GPIO MFP_CFG(GPIO57, AF0) + +#define GPIO63_GPIO MFP_CFG(GPIO63, AF0) +#define GPIO64_GPIO MFP_CFG(GPIO64, AF0) +#define GPIO65_GPIO MFP_CFG(GPIO65, AF0) +#define GPIO66_GPIO MFP_CFG(GPIO66, AF0) +#define GPIO67_GPIO MFP_CFG(GPIO67, AF0) +#define GPIO68_GPIO MFP_CFG(GPIO68, AF0) +#define GPIO69_GPIO MFP_CFG(GPIO69, AF0) +#define GPIO70_GPIO MFP_CFG(GPIO70, AF0) +#define GPIO71_GPIO MFP_CFG(GPIO71, AF0) +#define GPIO72_GPIO MFP_CFG(GPIO72, AF0) +#define GPIO73_GPIO MFP_CFG(GPIO73, AF0) +#define GPIO74_GPIO MFP_CFG(GPIO74, AF0) +#define GPIO75_GPIO MFP_CFG(GPIO75, AF0) +#define GPIO76_GPIO MFP_CFG(GPIO76, AF0) +#define GPIO77_GPIO MFP_CFG(GPIO77, AF0) +#define GPIO78_GPIO MFP_CFG(GPIO78, AF0) +#define GPIO79_GPIO MFP_CFG(GPIO79, AF0) +#define GPIO80_GPIO MFP_CFG(GPIO80, AF0) +#define GPIO81_GPIO MFP_CFG(GPIO81, AF0) +#define GPIO82_GPIO MFP_CFG(GPIO82, AF0) +#define GPIO83_GPIO MFP_CFG(GPIO83, AF0) +#define GPIO84_GPIO MFP_CFG(GPIO84, AF0) +#define GPIO85_GPIO MFP_CFG(GPIO85, AF0) +#define GPIO86_GPIO MFP_CFG(GPIO86, AF0) +#define GPIO87_GPIO MFP_CFG(GPIO87, AF0) +#define GPIO88_GPIO MFP_CFG(GPIO88, AF0) +#define GPIO89_GPIO MFP_CFG(GPIO89, AF0) +#define GPIO90_GPIO MFP_CFG(GPIO90, AF0) +#define GPIO91_GPIO MFP_CFG(GPIO91, AF0) +#define GPIO92_GPIO MFP_CFG(GPIO92, AF0) +#define GPIO93_GPIO MFP_CFG(GPIO93, AF0) +#define GPIO94_GPIO MFP_CFG(GPIO94, AF0) +#define GPIO95_GPIO MFP_CFG(GPIO95, AF0) +#define GPIO96_GPIO MFP_CFG(GPIO96, AF0) +#define GPIO97_GPIO MFP_CFG(GPIO97, AF0) +#define GPIO98_GPIO MFP_CFG(GPIO98, AF0) +#define GPIO99_GPIO MFP_CFG(GPIO99, AF0) +#define GPIO100_GPIO MFP_CFG(GPIO100, AF0) +#define GPIO101_GPIO MFP_CFG(GPIO101, AF0) +#define GPIO102_GPIO MFP_CFG(GPIO102, AF0) +#define GPIO103_GPIO MFP_CFG(GPIO103, AF0) +#define GPIO104_GPIO MFP_CFG(GPIO104, AF0) +#define GPIO105_GPIO MFP_CFG(GPIO105, AF0) +#define GPIO106_GPIO MFP_CFG(GPIO106, AF0) +#define GPIO107_GPIO MFP_CFG(GPIO107, AF0) +#define GPIO108_GPIO MFP_CFG(GPIO108, AF0) +#define GPIO109_GPIO MFP_CFG(GPIO109, AF0) +#define GPIO110_GPIO MFP_CFG(GPIO110, AF0) +#define GPIO111_GPIO MFP_CFG(GPIO111, AF0) +#define GPIO112_GPIO MFP_CFG(GPIO112, AF0) +#define GPIO113_GPIO MFP_CFG(GPIO113, AF0) +#define GPIO114_GPIO MFP_CFG(GPIO114, AF0) +#define GPIO115_GPIO MFP_CFG(GPIO115, AF0) +#define GPIO116_GPIO MFP_CFG(GPIO116, AF0) +#define GPIO117_GPIO MFP_CFG(GPIO117, AF0) +#define GPIO118_GPIO MFP_CFG(GPIO118, AF0) +#define GPIO119_GPIO MFP_CFG(GPIO119, AF0) +#define GPIO120_GPIO MFP_CFG(GPIO120, AF0) +#define GPIO121_GPIO MFP_CFG(GPIO121, AF0) +#define GPIO122_GPIO MFP_CFG(GPIO122, AF0) +#define GPIO123_GPIO MFP_CFG(GPIO123, AF0) +#define GPIO124_GPIO MFP_CFG(GPIO124, AF0) +#define GPIO125_GPIO MFP_CFG(GPIO125, AF0) +#define GPIO126_GPIO MFP_CFG(GPIO126, AF0) +#define GPIO127_GPIO MFP_CFG(GPIO127, AF0) + +#define GPIO0_2_GPIO MFP_CFG(GPIO0_2, AF0) +#define GPIO1_2_GPIO MFP_CFG(GPIO1_2, AF0) +#define GPIO2_2_GPIO MFP_CFG(GPIO2_2, AF0) +#define GPIO3_2_GPIO MFP_CFG(GPIO3_2, AF0) +#define GPIO4_2_GPIO MFP_CFG(GPIO4_2, AF0) +#define GPIO5_2_GPIO MFP_CFG(GPIO5_2, AF0) +#define GPIO6_2_GPIO MFP_CFG(GPIO6_2, AF0) + +/* NOTE: usage of these two functions is not recommended, + * use pxa3xx_mfp_config() instead. + */ +static inline unsigned long pxa3xx_mfp_read(int mfp) +{ + return mfp_read(mfp); +} + +static inline void pxa3xx_mfp_write(int mfp, unsigned long val) +{ + mfp_write(mfp, val); +} + +static inline void pxa3xx_mfp_config(unsigned long *mfp_cfg, int num) +{ + mfp_config(mfp_cfg, num); +} +#endif /* __ASM_ARCH_MFP_PXA3XX_H */ diff --git a/arch/arm/mach-pxa/mfp-pxa930.h b/arch/arm/mach-pxa/mfp-pxa930.h new file mode 100644 index 000000000000..113967beeb67 --- /dev/null +++ b/arch/arm/mach-pxa/mfp-pxa930.h @@ -0,0 +1,498 @@ +/* + * arch/arm/mach-pxa/include/mach/mfp-pxa930.h + * + * PXA930 specific MFP configuration definitions + * + * Copyright (C) 2007-2008 Marvell International Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ASM_ARCH_MFP_PXA9xx_H +#define __ASM_ARCH_MFP_PXA9xx_H + +#include "mfp-pxa3xx.h" + +/* GPIO */ +#define GPIO46_GPIO MFP_CFG(GPIO46, AF0) +#define GPIO49_GPIO MFP_CFG(GPIO49, AF0) +#define GPIO50_GPIO MFP_CFG(GPIO50, AF0) +#define GPIO51_GPIO MFP_CFG(GPIO51, AF0) +#define GPIO52_GPIO MFP_CFG(GPIO52, AF0) +#define GPIO56_GPIO MFP_CFG(GPIO56, AF0) +#define GPIO58_GPIO MFP_CFG(GPIO58, AF0) +#define GPIO59_GPIO MFP_CFG(GPIO59, AF0) +#define GPIO60_GPIO MFP_CFG(GPIO60, AF0) +#define GPIO61_GPIO MFP_CFG(GPIO61, AF0) +#define GPIO62_GPIO MFP_CFG(GPIO62, AF0) + +#define GSIM_UCLK_GPIO_79 MFP_CFG(GSIM_UCLK, AF0) +#define GSIM_UIO_GPIO_80 MFP_CFG(GSIM_UIO, AF0) +#define GSIM_nURST_GPIO_81 MFP_CFG(GSIM_nURST, AF0) +#define GSIM_UDET_GPIO_82 MFP_CFG(GSIM_UDET, AF0) + +#define DF_IO15_GPIO_28 MFP_CFG(DF_IO15, AF0) +#define DF_IO14_GPIO_29 MFP_CFG(DF_IO14, AF0) +#define DF_IO13_GPIO_30 MFP_CFG(DF_IO13, AF0) +#define DF_IO12_GPIO_31 MFP_CFG(DF_IO12, AF0) +#define DF_IO11_GPIO_32 MFP_CFG(DF_IO11, AF0) +#define DF_IO10_GPIO_33 MFP_CFG(DF_IO10, AF0) +#define DF_IO9_GPIO_34 MFP_CFG(DF_IO9, AF0) +#define DF_IO8_GPIO_35 MFP_CFG(DF_IO8, AF0) +#define DF_IO7_GPIO_36 MFP_CFG(DF_IO7, AF0) +#define DF_IO6_GPIO_37 MFP_CFG(DF_IO6, AF0) +#define DF_IO5_GPIO_38 MFP_CFG(DF_IO5, AF0) +#define DF_IO4_GPIO_39 MFP_CFG(DF_IO4, AF0) +#define DF_IO3_GPIO_40 MFP_CFG(DF_IO3, AF0) +#define DF_IO2_GPIO_41 MFP_CFG(DF_IO2, AF0) +#define DF_IO1_GPIO_42 MFP_CFG(DF_IO1, AF0) +#define DF_IO0_GPIO_43 MFP_CFG(DF_IO0, AF0) +#define DF_nCS0_GPIO_44 MFP_CFG(DF_nCS0, AF0) +#define DF_nCS1_GPIO_45 MFP_CFG(DF_nCS1, AF0) +#define DF_nWE_GPIO_46 MFP_CFG(DF_nWE, AF0) +#define DF_nRE_nOE_GPIO_47 MFP_CFG(DF_nRE_nOE, AF0) +#define DF_CLE_nOE_GPIO_48 MFP_CFG(DF_CLE_nOE, AF0) +#define DF_nADV1_ALE_GPIO_49 MFP_CFG(DF_nADV1_ALE, AF0) +#define DF_nADV2_ALE_GPIO_50 MFP_CFG(DF_nADV2_ALE, AF0) +#define DF_INT_RnB_GPIO_51 MFP_CFG(DF_INT_RnB, AF0) +#define DF_SCLK_E_GPIO_52 MFP_CFG(DF_SCLK_E, AF0) + +#define DF_ADDR0_GPIO_53 MFP_CFG(DF_ADDR0, AF0) +#define DF_ADDR1_GPIO_54 MFP_CFG(DF_ADDR1, AF0) +#define DF_ADDR2_GPIO_55 MFP_CFG(DF_ADDR2, AF0) +#define DF_ADDR3_GPIO_56 MFP_CFG(DF_ADDR3, AF0) +#define nXCVREN_GPIO_57 MFP_CFG(nXCVREN, AF0) +#define nLUA_GPIO_58 MFP_CFG(nLUA, AF0) +#define nLLA_GPIO_59 MFP_CFG(nLLA, AF0) +#define nBE0_GPIO_60 MFP_CFG(nBE0, AF0) +#define nBE1_GPIO_61 MFP_CFG(nBE1, AF0) +#define RDY_GPIO_62 MFP_CFG(RDY, AF0) +#define PMIC_INT_GPIO83 MFP_CFG_LPM(PMIC_INT, AF0, PULL_HIGH) + +/* Chip Select */ +#define DF_nCS0_nCS2 MFP_CFG_LPM(DF_nCS0, AF3, PULL_HIGH) +#define DF_nCS1_nCS3 MFP_CFG_LPM(DF_nCS1, AF3, PULL_HIGH) + +/* AC97 */ +#define GPIO83_BAC97_SYSCLK MFP_CFG(GPIO83, AF3) +#define GPIO84_BAC97_SDATA_IN0 MFP_CFG(GPIO84, AF3) +#define GPIO85_BAC97_BITCLK MFP_CFG(GPIO85, AF3) +#define GPIO86_BAC97_nRESET MFP_CFG(GPIO86, AF3) +#define GPIO87_BAC97_SYNC MFP_CFG(GPIO87, AF3) +#define GPIO88_BAC97_SDATA_OUT MFP_CFG(GPIO88, AF3) + +/* I2C */ +#define GPIO39_CI2C_SCL MFP_CFG_LPM(GPIO39, AF3, PULL_HIGH) +#define GPIO40_CI2C_SDA MFP_CFG_LPM(GPIO40, AF3, PULL_HIGH) + +#define GPIO51_CI2C_SCL MFP_CFG_LPM(GPIO51, AF3, PULL_HIGH) +#define GPIO52_CI2C_SDA MFP_CFG_LPM(GPIO52, AF3, PULL_HIGH) + +#define GPIO63_CI2C_SCL MFP_CFG_LPM(GPIO63, AF4, PULL_HIGH) +#define GPIO64_CI2C_SDA MFP_CFG_LPM(GPIO64, AF4, PULL_HIGH) + +#define GPIO73_CI2C_SCL MFP_CFG_LPM(GPIO73, AF1, PULL_HIGH) +#define GPIO74_CI2C_SDA MFP_CFG_LPM(GPIO74, AF1, PULL_HIGH) + +#define GPIO77_CI2C_SCL MFP_CFG_LPM(GPIO77, AF2, PULL_HIGH) +#define GPIO78_CI2C_SDA MFP_CFG_LPM(GPIO78, AF2, PULL_HIGH) + +#define GPIO89_CI2C_SCL MFP_CFG_LPM(GPIO89, AF1, PULL_HIGH) +#define GPIO90_CI2C_SDA MFP_CFG_LPM(GPIO90, AF1, PULL_HIGH) + +#define GPIO95_CI2C_SCL MFP_CFG_LPM(GPIO95, AF1, PULL_HIGH) +#define GPIO96_CI2C_SDA MFP_CFG_LPM(GPIO96, AF1, PULL_HIGH) + +#define GPIO97_CI2C_SCL MFP_CFG_LPM(GPIO97, AF3, PULL_HIGH) +#define GPIO98_CI2C_SDA MFP_CFG_LPM(GPIO98, AF3, PULL_HIGH) + +/* QCI */ +#define GPIO63_CI_DD_9 MFP_CFG_LPM(GPIO63, AF1, PULL_LOW) +#define GPIO64_CI_DD_8 MFP_CFG_LPM(GPIO64, AF1, PULL_LOW) +#define GPIO65_CI_DD_7 MFP_CFG_LPM(GPIO65, AF1, PULL_LOW) +#define GPIO66_CI_DD_6 MFP_CFG_LPM(GPIO66, AF1, PULL_LOW) +#define GPIO67_CI_DD_5 MFP_CFG_LPM(GPIO67, AF1, PULL_LOW) +#define GPIO68_CI_DD_4 MFP_CFG_LPM(GPIO68, AF1, PULL_LOW) +#define GPIO69_CI_DD_3 MFP_CFG_LPM(GPIO69, AF1, PULL_LOW) +#define GPIO70_CI_DD_2 MFP_CFG_LPM(GPIO70, AF1, PULL_LOW) +#define GPIO71_CI_DD_1 MFP_CFG_LPM(GPIO71, AF1, PULL_LOW) +#define GPIO72_CI_DD_0 MFP_CFG_LPM(GPIO72, AF1, PULL_LOW) +#define GPIO73_CI_HSYNC MFP_CFG_LPM(GPIO73, AF1, PULL_LOW) +#define GPIO74_CI_VSYNC MFP_CFG_LPM(GPIO74, AF1, PULL_LOW) +#define GPIO75_CI_MCLK MFP_CFG_LPM(GPIO75, AF1, PULL_LOW) +#define GPIO76_CI_PCLK MFP_CFG_LPM(GPIO76, AF1, PULL_LOW) + +/* KEYPAD */ +#define GPIO4_KP_DKIN_4 MFP_CFG_LPM(GPIO4, AF3, FLOAT) +#define GPIO5_KP_DKIN_5 MFP_CFG_LPM(GPIO5, AF3, FLOAT) +#define GPIO6_KP_DKIN_6 MFP_CFG_LPM(GPIO6, AF3, FLOAT) +#define GPIO7_KP_DKIN_7 MFP_CFG_LPM(GPIO7, AF3, FLOAT) +#define GPIO8_KP_DKIN_4 MFP_CFG_LPM(GPIO8, AF3, FLOAT) +#define GPIO9_KP_DKIN_5 MFP_CFG_LPM(GPIO9, AF3, FLOAT) +#define GPIO10_KP_DKIN_6 MFP_CFG_LPM(GPIO10, AF3, FLOAT) +#define GPIO11_KP_DKIN_7 MFP_CFG_LPM(GPIO11, AF3, FLOAT) + +#define GPIO12_KP_DKIN_0 MFP_CFG_LPM(GPIO12, AF2, FLOAT) +#define GPIO13_KP_DKIN_1 MFP_CFG_LPM(GPIO13, AF2, FLOAT) +#define GPIO14_KP_DKIN_2 MFP_CFG_LPM(GPIO14, AF2, FLOAT) +#define GPIO15_KP_DKIN_3 MFP_CFG_LPM(GPIO15, AF2, FLOAT) + +#define GPIO41_KP_DKIN_0 MFP_CFG_LPM(GPIO41, AF2, FLOAT) +#define GPIO42_KP_DKIN_1 MFP_CFG_LPM(GPIO42, AF2, FLOAT) +#define GPIO43_KP_DKIN_2 MFP_CFG_LPM(GPIO43, AF2, FLOAT) +#define GPIO44_KP_DKIN_3 MFP_CFG_LPM(GPIO44, AF2, FLOAT) +#define GPIO41_KP_DKIN_4 MFP_CFG_LPM(GPIO41, AF4, FLOAT) +#define GPIO42_KP_DKIN_5 MFP_CFG_LPM(GPIO42, AF4, FLOAT) + +#define GPIO0_KP_MKIN_0 MFP_CFG_LPM(GPIO0, AF1, FLOAT) +#define GPIO2_KP_MKIN_1 MFP_CFG_LPM(GPIO2, AF1, FLOAT) +#define GPIO4_KP_MKIN_2 MFP_CFG_LPM(GPIO4, AF1, FLOAT) +#define GPIO6_KP_MKIN_3 MFP_CFG_LPM(GPIO6, AF1, FLOAT) +#define GPIO8_KP_MKIN_4 MFP_CFG_LPM(GPIO8, AF1, FLOAT) +#define GPIO10_KP_MKIN_5 MFP_CFG_LPM(GPIO10, AF1, FLOAT) +#define GPIO12_KP_MKIN_6 MFP_CFG_LPM(GPIO12, AF1, FLOAT) +#define GPIO14_KP_MKIN_7 MFP_CFG(GPIO14, AF1) +#define GPIO35_KP_MKIN_5 MFP_CFG(GPIO35, AF4) + +#define GPIO1_KP_MKOUT_0 MFP_CFG_LPM(GPIO1, AF1, DRIVE_HIGH) +#define GPIO3_KP_MKOUT_1 MFP_CFG_LPM(GPIO3, AF1, DRIVE_HIGH) +#define GPIO5_KP_MKOUT_2 MFP_CFG_LPM(GPIO5, AF1, DRIVE_HIGH) +#define GPIO7_KP_MKOUT_3 MFP_CFG_LPM(GPIO7, AF1, DRIVE_HIGH) +#define GPIO9_KP_MKOUT_4 MFP_CFG_LPM(GPIO9, AF1, DRIVE_HIGH) +#define GPIO11_KP_MKOUT_5 MFP_CFG_LPM(GPIO11, AF1, DRIVE_HIGH) +#define GPIO13_KP_MKOUT_6 MFP_CFG_LPM(GPIO13, AF1, DRIVE_HIGH) +#define GPIO15_KP_MKOUT_7 MFP_CFG_LPM(GPIO15, AF1, DRIVE_HIGH) +#define GPIO36_KP_MKOUT_5 MFP_CFG_LPM(GPIO36, AF4, DRIVE_HIGH) + +/* LCD */ +#define GPIO17_LCD_FCLK_RD MFP_CFG(GPIO17, AF1) +#define GPIO18_LCD_LCLK_A0 MFP_CFG(GPIO18, AF1) +#define GPIO19_LCD_PCLK_WR MFP_CFG(GPIO19, AF1) +#define GPIO20_LCD_BIAS MFP_CFG(GPIO20, AF1) +#define GPIO21_LCD_CS MFP_CFG(GPIO21, AF1) +#define GPIO22_LCD_CS2 MFP_CFG(GPIO22, AF2) +#define GPIO22_LCD_VSYNC MFP_CFG(GPIO22, AF1) +#define GPIO23_LCD_DD0 MFP_CFG(GPIO23, AF1) +#define GPIO24_LCD_DD1 MFP_CFG(GPIO24, AF1) +#define GPIO25_LCD_DD2 MFP_CFG(GPIO25, AF1) +#define GPIO26_LCD_DD3 MFP_CFG(GPIO26, AF1) +#define GPIO27_LCD_DD4 MFP_CFG(GPIO27, AF1) +#define GPIO28_LCD_DD5 MFP_CFG(GPIO28, AF1) +#define GPIO29_LCD_DD6 MFP_CFG(GPIO29, AF1) +#define GPIO30_LCD_DD7 MFP_CFG(GPIO30, AF1) +#define GPIO31_LCD_DD8 MFP_CFG(GPIO31, AF1) +#define GPIO32_LCD_DD9 MFP_CFG(GPIO32, AF1) +#define GPIO33_LCD_DD10 MFP_CFG(GPIO33, AF1) +#define GPIO34_LCD_DD11 MFP_CFG(GPIO34, AF1) +#define GPIO35_LCD_DD12 MFP_CFG(GPIO35, AF1) +#define GPIO36_LCD_DD13 MFP_CFG(GPIO36, AF1) +#define GPIO37_LCD_DD14 MFP_CFG(GPIO37, AF1) +#define GPIO38_LCD_DD15 MFP_CFG(GPIO38, AF1) +#define GPIO39_LCD_DD16 MFP_CFG(GPIO39, AF1) +#define GPIO40_LCD_DD17 MFP_CFG(GPIO40, AF1) +#define GPIO41_LCD_CS2 MFP_CFG(GPIO41, AF3) +#define GPIO42_LCD_VSYNC2 MFP_CFG(GPIO42, AF3) +#define GPIO44_LCD_DD7 MFP_CFG(GPIO44, AF1) + +/* Mini-LCD */ +#define GPIO17_MLCD_FCLK MFP_CFG(GPIO17, AF3) +#define GPIO18_MLCD_LCLK MFP_CFG(GPIO18, AF3) +#define GPIO19_MLCD_PCLK MFP_CFG(GPIO19, AF3) +#define GPIO20_MLCD_BIAS MFP_CFG(GPIO20, AF3) +#define GPIO23_MLCD_DD0 MFP_CFG(GPIO23, AF3) +#define GPIO24_MLCD_DD1 MFP_CFG(GPIO24, AF3) +#define GPIO25_MLCD_DD2 MFP_CFG(GPIO25, AF3) +#define GPIO26_MLCD_DD3 MFP_CFG(GPIO26, AF3) +#define GPIO27_MLCD_DD4 MFP_CFG(GPIO27, AF3) +#define GPIO28_MLCD_DD5 MFP_CFG(GPIO28, AF3) +#define GPIO29_MLCD_DD6 MFP_CFG(GPIO29, AF3) +#define GPIO30_MLCD_DD7 MFP_CFG(GPIO30, AF3) +#define GPIO31_MLCD_DD8 MFP_CFG(GPIO31, AF3) +#define GPIO32_MLCD_DD9 MFP_CFG(GPIO32, AF3) +#define GPIO33_MLCD_DD10 MFP_CFG(GPIO33, AF3) +#define GPIO34_MLCD_DD11 MFP_CFG(GPIO34, AF3) +#define GPIO35_MLCD_DD12 MFP_CFG(GPIO35, AF3) +#define GPIO36_MLCD_DD13 MFP_CFG(GPIO36, AF3) +#define GPIO37_MLCD_DD14 MFP_CFG(GPIO37, AF3) +#define GPIO38_MLCD_DD15 MFP_CFG(GPIO38, AF3) +#define GPIO44_MLCD_DD7 MFP_CFG(GPIO44, AF5) + +/* MMC1 */ +#define GPIO10_MMC1_DAT3 MFP_CFG(GPIO10, AF4) +#define GPIO11_MMC1_DAT2 MFP_CFG(GPIO11, AF4) +#define GPIO12_MMC1_DAT1 MFP_CFG(GPIO12, AF4) +#define GPIO13_MMC1_DAT0 MFP_CFG(GPIO13, AF4) +#define GPIO14_MMC1_CMD MFP_CFG(GPIO14, AF4) +#define GPIO15_MMC1_CLK MFP_CFG(GPIO15, AF4) +#define GPIO55_MMC1_CMD MFP_CFG(GPIO55, AF3) +#define GPIO56_MMC1_CLK MFP_CFG(GPIO56, AF3) +#define GPIO57_MMC1_DAT0 MFP_CFG(GPIO57, AF3) +#define GPIO58_MMC1_DAT1 MFP_CFG(GPIO58, AF3) +#define GPIO59_MMC1_DAT2 MFP_CFG(GPIO59, AF3) +#define GPIO60_MMC1_DAT3 MFP_CFG(GPIO60, AF3) + +#define DF_ADDR0_MMC1_CLK MFP_CFG(DF_ADDR0, AF2) +#define DF_ADDR1_MMC1_CMD MFP_CFG(DF_ADDR1, AF2) +#define DF_ADDR2_MMC1_DAT0 MFP_CFG(DF_ADDR2, AF2) +#define DF_ADDR3_MMC1_DAT1 MFP_CFG(DF_ADDR3, AF3) +#define nXCVREN_MMC1_DAT2 MFP_CFG(nXCVREN, AF2) + +/* MMC2 */ +#define GPIO31_MMC2_CMD MFP_CFG(GPIO31, AF7) +#define GPIO32_MMC2_CLK MFP_CFG(GPIO32, AF7) +#define GPIO33_MMC2_DAT0 MFP_CFG(GPIO33, AF7) +#define GPIO34_MMC2_DAT1 MFP_CFG(GPIO34, AF7) +#define GPIO35_MMC2_DAT2 MFP_CFG(GPIO35, AF7) +#define GPIO36_MMC2_DAT3 MFP_CFG(GPIO36, AF7) + +#define GPIO101_MMC2_DAT3 MFP_CFG(GPIO101, AF1) +#define GPIO102_MMC2_DAT2 MFP_CFG(GPIO102, AF1) +#define GPIO103_MMC2_DAT1 MFP_CFG(GPIO103, AF1) +#define GPIO104_MMC2_DAT0 MFP_CFG(GPIO104, AF1) +#define GPIO105_MMC2_CMD MFP_CFG(GPIO105, AF1) +#define GPIO106_MMC2_CLK MFP_CFG(GPIO106, AF1) + +#define DF_IO10_MMC2_DAT3 MFP_CFG(DF_IO10, AF3) +#define DF_IO11_MMC2_DAT2 MFP_CFG(DF_IO11, AF3) +#define DF_IO12_MMC2_DAT1 MFP_CFG(DF_IO12, AF3) +#define DF_IO13_MMC2_DAT0 MFP_CFG(DF_IO13, AF3) +#define DF_IO14_MMC2_CLK MFP_CFG(DF_IO14, AF3) +#define DF_IO15_MMC2_CMD MFP_CFG(DF_IO15, AF3) + +/* BSSP1 */ +#define GPIO12_BSSP1_CLK MFP_CFG(GPIO12, AF3) +#define GPIO13_BSSP1_FRM MFP_CFG(GPIO13, AF3) +#define GPIO14_BSSP1_RXD MFP_CFG(GPIO14, AF3) +#define GPIO15_BSSP1_TXD MFP_CFG(GPIO15, AF3) +#define GPIO97_BSSP1_CLK MFP_CFG(GPIO97, AF5) +#define GPIO98_BSSP1_FRM MFP_CFG(GPIO98, AF5) + +/* BSSP2 */ +#define GPIO84_BSSP2_SDATA_IN MFP_CFG(GPIO84, AF1) +#define GPIO85_BSSP2_BITCLK MFP_CFG(GPIO85, AF1) +#define GPIO86_BSSP2_SYSCLK MFP_CFG(GPIO86, AF1) +#define GPIO87_BSSP2_SYNC MFP_CFG(GPIO87, AF1) +#define GPIO88_BSSP2_DATA_OUT MFP_CFG(GPIO88, AF1) +#define GPIO86_BSSP2_SDATA_IN MFP_CFG(GPIO86, AF4) + +/* BSSP3 */ +#define GPIO79_BSSP3_CLK MFP_CFG(GPIO79, AF1) +#define GPIO80_BSSP3_FRM MFP_CFG(GPIO80, AF1) +#define GPIO81_BSSP3_TXD MFP_CFG(GPIO81, AF1) +#define GPIO82_BSSP3_RXD MFP_CFG(GPIO82, AF1) +#define GPIO83_BSSP3_SYSCLK MFP_CFG(GPIO83, AF1) + +/* BSSP4 */ +#define GPIO43_BSSP4_CLK MFP_CFG(GPIO43, AF4) +#define GPIO44_BSSP4_FRM MFP_CFG(GPIO44, AF4) +#define GPIO45_BSSP4_TXD MFP_CFG(GPIO45, AF4) +#define GPIO46_BSSP4_RXD MFP_CFG(GPIO46, AF4) + +#define GPIO51_BSSP4_CLK MFP_CFG(GPIO51, AF4) +#define GPIO52_BSSP4_FRM MFP_CFG(GPIO52, AF4) +#define GPIO53_BSSP4_TXD MFP_CFG(GPIO53, AF4) +#define GPIO54_BSSP4_RXD MFP_CFG(GPIO54, AF4) + +/* GSSP1 */ +#define GPIO79_GSSP1_CLK MFP_CFG(GPIO79, AF2) +#define GPIO80_GSSP1_FRM MFP_CFG(GPIO80, AF2) +#define GPIO81_GSSP1_TXD MFP_CFG(GPIO81, AF2) +#define GPIO82_GSSP1_RXD MFP_CFG(GPIO82, AF2) +#define GPIO83_GSSP1_SYSCLK MFP_CFG(GPIO83, AF2) + +#define GPIO93_GSSP1_CLK MFP_CFG(GPIO93, AF4) +#define GPIO94_GSSP1_FRM MFP_CFG(GPIO94, AF4) +#define GPIO95_GSSP1_TXD MFP_CFG(GPIO95, AF4) +#define GPIO96_GSSP1_RXD MFP_CFG(GPIO96, AF4) + +/* GSSP2 */ +#define GPIO47_GSSP2_CLK MFP_CFG(GPIO47, AF4) +#define GPIO48_GSSP2_FRM MFP_CFG(GPIO48, AF4) +#define GPIO49_GSSP2_RXD MFP_CFG(GPIO49, AF4) +#define GPIO50_GSSP2_TXD MFP_CFG(GPIO50, AF4) + +#define GPIO69_GSSP2_CLK MFP_CFG(GPIO69, AF4) +#define GPIO70_GSSP2_FRM MFP_CFG(GPIO70, AF4) +#define GPIO71_GSSP2_RXD MFP_CFG(GPIO71, AF4) +#define GPIO72_GSSP2_TXD MFP_CFG(GPIO72, AF4) + +#define GPIO84_GSSP2_RXD MFP_CFG(GPIO84, AF2) +#define GPIO85_GSSP2_CLK MFP_CFG(GPIO85, AF2) +#define GPIO86_GSSP2_SYSCLK MFP_CFG(GPIO86, AF2) +#define GPIO87_GSSP2_FRM MFP_CFG(GPIO87, AF2) +#define GPIO88_GSSP2_TXD MFP_CFG(GPIO88, AF2) +#define GPIO86_GSSP2_RXD MFP_CFG(GPIO86, AF5) + +#define GPIO103_GSSP2_CLK MFP_CFG(GPIO103, AF2) +#define GPIO104_GSSP2_FRM MFP_CFG(GPIO104, AF2) +#define GPIO105_GSSP2_RXD MFP_CFG(GPIO105, AF2) +#define GPIO106_GSSP2_TXD MFP_CFG(GPIO106, AF2) + +/* UART1 - FFUART */ +#define GPIO47_UART1_DSR_N MFP_CFG(GPIO47, AF1) +#define GPIO48_UART1_DTR_N MFP_CFG(GPIO48, AF1) +#define GPIO49_UART1_RI MFP_CFG(GPIO49, AF1) +#define GPIO50_UART1_DCD MFP_CFG(GPIO50, AF1) +#define GPIO51_UART1_CTS MFP_CFG(GPIO51, AF1) +#define GPIO52_UART1_RTS MFP_CFG(GPIO52, AF1) +#define GPIO53_UART1_RXD MFP_CFG(GPIO53, AF1) +#define GPIO54_UART1_TXD MFP_CFG(GPIO54, AF1) + +#define GPIO63_UART1_TXD MFP_CFG(GPIO63, AF2) +#define GPIO64_UART1_RXD MFP_CFG(GPIO64, AF2) +#define GPIO65_UART1_DSR MFP_CFG(GPIO65, AF2) +#define GPIO66_UART1_DTR MFP_CFG(GPIO66, AF2) +#define GPIO67_UART1_RI MFP_CFG(GPIO67, AF2) +#define GPIO68_UART1_DCD MFP_CFG(GPIO68, AF2) +#define GPIO69_UART1_CTS MFP_CFG(GPIO69, AF2) +#define GPIO70_UART1_RTS MFP_CFG(GPIO70, AF2) + +#define GPIO53_UART1_TXD MFP_CFG(GPIO53, AF2) +#define GPIO54_UART1_RXD MFP_CFG(GPIO54, AF2) + +/* UART2 - BTUART */ +#define GPIO91_UART2_RXD MFP_CFG(GPIO91, AF1) +#define GPIO92_UART2_TXD MFP_CFG(GPIO92, AF1) +#define GPIO93_UART2_CTS MFP_CFG(GPIO93, AF1) +#define GPIO94_UART2_RTS MFP_CFG(GPIO94, AF1) + +/* UART3 - STUART */ +#define GPIO43_UART3_RTS MFP_CFG(GPIO43, AF3) +#define GPIO44_UART3_CTS MFP_CFG(GPIO44, AF3) +#define GPIO45_UART3_RXD MFP_CFG(GPIO45, AF3) +#define GPIO46_UART3_TXD MFP_CFG(GPIO46, AF3) + +#define GPIO75_UART3_RTS MFP_CFG(GPIO75, AF5) +#define GPIO76_UART3_CTS MFP_CFG(GPIO76, AF5) +#define GPIO77_UART3_TXD MFP_CFG(GPIO77, AF5) +#define GPIO78_UART3_RXD MFP_CFG(GPIO78, AF5) + +/* DFI */ +#define DF_IO0_DF_IO0 MFP_CFG(DF_IO0, AF2) +#define DF_IO1_DF_IO1 MFP_CFG(DF_IO1, AF2) +#define DF_IO2_DF_IO2 MFP_CFG(DF_IO2, AF2) +#define DF_IO3_DF_IO3 MFP_CFG(DF_IO3, AF2) +#define DF_IO4_DF_IO4 MFP_CFG(DF_IO4, AF2) +#define DF_IO5_DF_IO5 MFP_CFG(DF_IO5, AF2) +#define DF_IO6_DF_IO6 MFP_CFG(DF_IO6, AF2) +#define DF_IO7_DF_IO7 MFP_CFG(DF_IO7, AF2) +#define DF_IO8_DF_IO8 MFP_CFG(DF_IO8, AF2) +#define DF_IO9_DF_IO9 MFP_CFG(DF_IO9, AF2) +#define DF_IO10_DF_IO10 MFP_CFG(DF_IO10, AF2) +#define DF_IO11_DF_IO11 MFP_CFG(DF_IO11, AF2) +#define DF_IO12_DF_IO12 MFP_CFG(DF_IO12, AF2) +#define DF_IO13_DF_IO13 MFP_CFG(DF_IO13, AF2) +#define DF_IO14_DF_IO14 MFP_CFG(DF_IO14, AF2) +#define DF_IO15_DF_IO15 MFP_CFG(DF_IO15, AF2) +#define DF_nADV1_ALE_DF_nADV1 MFP_CFG(DF_nADV1_ALE, AF2) +#define DF_nADV2_ALE_DF_nADV2 MFP_CFG(DF_nADV2_ALE, AF2) +#define DF_nCS0_DF_nCS0 MFP_CFG(DF_nCS0, AF2) +#define DF_nCS1_DF_nCS1 MFP_CFG(DF_nCS1, AF2) +#define DF_nRE_nOE_DF_nOE MFP_CFG(DF_nRE_nOE, AF2) +#define DF_nWE_DF_nWE MFP_CFG(DF_nWE, AF2) + +/* DFI - NAND */ +#define DF_CLE_nOE_ND_CLE MFP_CFG_LPM(DF_CLE_nOE, AF1, PULL_HIGH) +#define DF_INT_RnB_ND_INT_RnB MFP_CFG_LPM(DF_INT_RnB, AF1, PULL_LOW) +#define DF_IO0_ND_IO0 MFP_CFG_LPM(DF_IO0, AF1, PULL_LOW) +#define DF_IO1_ND_IO1 MFP_CFG_LPM(DF_IO1, AF1, PULL_LOW) +#define DF_IO2_ND_IO2 MFP_CFG_LPM(DF_IO2, AF1, PULL_LOW) +#define DF_IO3_ND_IO3 MFP_CFG_LPM(DF_IO3, AF1, PULL_LOW) +#define DF_IO4_ND_IO4 MFP_CFG_LPM(DF_IO4, AF1, PULL_LOW) +#define DF_IO5_ND_IO5 MFP_CFG_LPM(DF_IO5, AF1, PULL_LOW) +#define DF_IO6_ND_IO6 MFP_CFG_LPM(DF_IO6, AF1, PULL_LOW) +#define DF_IO7_ND_IO7 MFP_CFG_LPM(DF_IO7, AF1, PULL_LOW) +#define DF_IO8_ND_IO8 MFP_CFG_LPM(DF_IO8, AF1, PULL_LOW) +#define DF_IO9_ND_IO9 MFP_CFG_LPM(DF_IO9, AF1, PULL_LOW) +#define DF_IO10_ND_IO10 MFP_CFG_LPM(DF_IO10, AF1, PULL_LOW) +#define DF_IO11_ND_IO11 MFP_CFG_LPM(DF_IO11, AF1, PULL_LOW) +#define DF_IO12_ND_IO12 MFP_CFG_LPM(DF_IO12, AF1, PULL_LOW) +#define DF_IO13_ND_IO13 MFP_CFG_LPM(DF_IO13, AF1, PULL_LOW) +#define DF_IO14_ND_IO14 MFP_CFG_LPM(DF_IO14, AF1, PULL_LOW) +#define DF_IO15_ND_IO15 MFP_CFG_LPM(DF_IO15, AF1, PULL_LOW) +#define DF_nADV1_ALE_ND_ALE MFP_CFG_LPM(DF_nADV1_ALE, AF1, PULL_HIGH) +#define DF_nADV2_ALE_ND_ALE MFP_CFG_LPM(DF_nADV2_ALE, AF1, PULL_HIGH) +#define DF_nADV2_ALE_nCS3 MFP_CFG_LPM(DF_nADV2_ALE, AF3, PULL_HIGH) +#define DF_nCS0_ND_nCS0 MFP_CFG_LPM(DF_nCS0, AF1, PULL_HIGH) +#define DF_nCS1_ND_nCS1 MFP_CFG_LPM(DF_nCS1, AF1, PULL_HIGH) +#define DF_nRE_nOE_ND_nRE MFP_CFG_LPM(DF_nRE_nOE, AF1, PULL_HIGH) +#define DF_nWE_ND_nWE MFP_CFG_LPM(DF_nWE, AF1, PULL_HIGH) + +/* PWM */ +#define GPIO41_PWM0 MFP_CFG_LPM(GPIO41, AF1, PULL_LOW) +#define GPIO42_PWM1 MFP_CFG_LPM(GPIO42, AF1, PULL_LOW) +#define GPIO43_PWM3 MFP_CFG_LPM(GPIO43, AF1, PULL_LOW) +#define GPIO20_PWM0 MFP_CFG_LPM(GPIO20, AF2, PULL_LOW) +#define GPIO21_PWM2 MFP_CFG_LPM(GPIO21, AF3, PULL_LOW) +#define GPIO22_PWM3 MFP_CFG_LPM(GPIO22, AF3, PULL_LOW) +#define GPIO32_PWM0 MFP_CFG_LPM(GPIO32, AF4, PULL_LOW) + +/* CIR */ +#define GPIO46_CIR_OUT MFP_CFG(GPIO46, AF1) +#define GPIO77_CIR_OUT MFP_CFG(GPIO77, AF3) + +/* USB P2 */ +#define GPIO0_USB_P2_7 MFP_CFG(GPIO0, AF3) +#define GPIO15_USB_P2_7 MFP_CFG(GPIO15, AF5) +#define GPIO16_USB_P2_7 MFP_CFG(GPIO16, AF2) +#define GPIO48_USB_P2_7 MFP_CFG(GPIO48, AF7) +#define GPIO49_USB_P2_7 MFP_CFG(GPIO49, AF6) +#define DF_IO9_USB_P2_7 MFP_CFG(DF_IO9, AF3) + +#define GPIO48_USB_P2_8 MFP_CFG(GPIO48, AF2) +#define GPIO50_USB_P2_7 MFP_CFG_X(GPIO50, AF2, DS02X, FLOAT) +#define GPIO51_USB_P2_5 MFP_CFG(GPIO51, AF2) +#define GPIO47_USB_P2_4 MFP_CFG(GPIO47, AF2) +#define GPIO53_USB_P2_3 MFP_CFG(GPIO53, AF2) +#define GPIO54_USB_P2_6 MFP_CFG(GPIO54, AF2) +#define GPIO49_USB_P2_2 MFP_CFG(GPIO49, AF2) +#define GPIO52_USB_P2_1 MFP_CFG(GPIO52, AF2) + +#define GPIO63_USB_P2_8 MFP_CFG(GPIO63, AF3) +#define GPIO64_USB_P2_7 MFP_CFG(GPIO64, AF3) +#define GPIO65_USB_P2_6 MFP_CFG(GPIO65, AF3) +#define GPIO66_USG_P2_5 MFP_CFG(GPIO66, AF3) +#define GPIO67_USB_P2_4 MFP_CFG(GPIO67, AF3) +#define GPIO68_USB_P2_3 MFP_CFG(GPIO68, AF3) +#define GPIO69_USB_P2_2 MFP_CFG(GPIO69, AF3) +#define GPIO70_USB_P2_1 MFP_CFG(GPIO70, AF3) + +/* ULPI */ +#define GPIO31_USB_ULPI_D0 MFP_CFG(GPIO31, AF4) +#define GPIO30_USB_ULPI_D1 MFP_CFG(GPIO30, AF7) +#define GPIO33_USB_ULPI_D2 MFP_CFG(GPIO33, AF5) +#define GPIO34_USB_ULPI_D3 MFP_CFG(GPIO34, AF5) +#define GPIO35_USB_ULPI_D4 MFP_CFG(GPIO35, AF5) +#define GPIO36_USB_ULPI_D5 MFP_CFG(GPIO36, AF5) +#define GPIO41_USB_ULPI_D6 MFP_CFG(GPIO41, AF5) +#define GPIO42_USB_ULPI_D7 MFP_CFG(GPIO42, AF5) +#define GPIO37_USB_ULPI_DIR MFP_CFG(GPIO37, AF4) +#define GPIO38_USB_ULPI_CLK MFP_CFG(GPIO38, AF4) +#define GPIO39_USB_ULPI_STP MFP_CFG(GPIO39, AF4) +#define GPIO40_USB_ULPI_NXT MFP_CFG(GPIO40, AF4) + +#define GPIO3_CLK26MOUTDMD MFP_CFG(GPIO3, AF3) +#define GPIO40_CLK26MOUTDMD MFP_CFG(GPIO40, AF7) +#define GPIO94_CLK26MOUTDMD MFP_CFG(GPIO94, AF5) +#define GPIO104_CLK26MOUTDMD MFP_CFG(GPIO104, AF4) +#define DF_ADDR1_CLK26MOUTDMD MFP_CFG(DF_ADDR2, AF3) +#define DF_ADDR3_CLK26MOUTDMD MFP_CFG(DF_ADDR3, AF3) + +#define GPIO14_CLK26MOUT MFP_CFG(GPIO14, AF5) +#define GPIO38_CLK26MOUT MFP_CFG(GPIO38, AF7) +#define GPIO92_CLK26MOUT MFP_CFG(GPIO92, AF5) +#define GPIO105_CLK26MOUT MFP_CFG(GPIO105, AF4) + +#define GPIO2_CLK13MOUTDMD MFP_CFG(GPIO2, AF3) +#define GPIO39_CLK13MOUTDMD MFP_CFG(GPIO39, AF7) +#define GPIO50_CLK13MOUTDMD MFP_CFG(GPIO50, AF3) +#define GPIO93_CLK13MOUTDMD MFP_CFG(GPIO93, AF5) +#define GPIO103_CLK13MOUTDMD MFP_CFG(GPIO103, AF4) +#define DF_ADDR2_CLK13MOUTDMD MFP_CFG(DF_ADDR2, AF3) + +/* 1 wire */ +#define GPIO95_OW_DQ_IN MFP_CFG(GPIO95, AF5) + +#endif /* __ASM_ARCH_MFP_PXA9xx_H */ diff --git a/arch/arm/mach-pxa/mioa701.c b/arch/arm/mach-pxa/mioa701.c index 3b52b1aa0659..a315f6e3c4a6 100644 --- a/arch/arm/mach-pxa/mioa701.c +++ b/arch/arm/mach-pxa/mioa701.c @@ -47,19 +47,19 @@ #include #include -#include -#include +#include "pxa27x.h" +#include "regs-rtc.h" #include #include #include -#include -#include +#include "udc.h" +#include "pxa27x-udc.h" #include #include #include #include -#include +#include "mioa701.h" #include "generic.h" #include "devices.h" diff --git a/arch/arm/mach-pxa/mioa701.h b/arch/arm/mach-pxa/mioa701.h new file mode 100644 index 000000000000..e57f5c724e8a --- /dev/null +++ b/arch/arm/mach-pxa/mioa701.h @@ -0,0 +1,75 @@ +#ifndef _MIOA701_H_ +#define _MIOA701_H_ + +#define MIO_CFG_IN(pin, af) \ + ((MFP_CFG_DEFAULT & ~(MFP_AF_MASK | MFP_DIR_MASK)) |\ + (MFP_PIN(pin) | MFP_##af | MFP_DIR_IN)) + +#define MIO_CFG_OUT(pin, af, state) \ + ((MFP_CFG_DEFAULT & ~(MFP_AF_MASK | MFP_DIR_MASK | MFP_LPM_STATE_MASK)) |\ + (MFP_PIN(pin) | MFP_##af | MFP_DIR_OUT | MFP_LPM_##state)) + +/* Global GPIOs */ +#define GPIO9_CHARGE_EN 9 +#define GPIO18_POWEROFF 18 +#define GPIO87_LCD_POWER 87 +#define GPIO96_AC_DETECT 96 +#define GPIO80_MAYBE_CHARGE_VDROP 80 /* Drop of 88mV */ + +/* USB */ +#define GPIO13_nUSB_DETECT 13 +#define GPIO22_USB_ENABLE 22 + +/* SDIO bits */ +#define GPIO78_SDIO_RO 78 +#define GPIO15_SDIO_INSERT 15 +#define GPIO91_SDIO_EN 91 + +/* Bluetooth */ +#define GPIO14_BT_nACTIVITY 14 +#define GPIO83_BT_ON 83 +#define GPIO77_BT_UNKNOWN1 77 +#define GPIO86_BT_MAYBE_nRESET 86 + +/* GPS */ +#define GPIO23_GPS_UNKNOWN1 23 +#define GPIO26_GPS_ON 26 +#define GPIO27_GPS_RESET 27 +#define GPIO106_GPS_UNKNOWN2 106 +#define GPIO107_GPS_UNKNOWN3 107 + +/* GSM */ +#define GPIO24_GSM_MOD_RESET_CMD 24 +#define GPIO88_GSM_nMOD_ON_CMD 88 +#define GPIO90_GSM_nMOD_OFF_CMD 90 +#define GPIO114_GSM_nMOD_DTE_UART_STATE 114 +#define GPIO25_GSM_MOD_ON_STATE 25 +#define GPIO113_GSM_EVENT 113 + +/* SOUND */ +#define GPIO12_HPJACK_INSERT 12 + +/* LEDS */ +#define GPIO10_LED_nCharging 10 +#define GPIO97_LED_nBlue 97 +#define GPIO98_LED_nOrange 98 +#define GPIO82_LED_nVibra 82 +#define GPIO115_LED_nKeyboard 115 + +/* Keyboard */ +#define GPIO0_KEY_POWER 0 +#define GPIO93_KEY_VOLUME_UP 93 +#define GPIO94_KEY_VOLUME_DOWN 94 + +/* Camera */ +#define GPIO56_MT9M111_nOE 56 + +extern struct input_dev *mioa701_evdev; +extern void mioa701_gpio_lpm_set(unsigned long mfp_pin); + +/* Assembler externals mioa701_bootresume.S */ +extern u32 mioa701_bootstrap; +extern u32 mioa701_jumpaddr; +extern u32 mioa701_bootstrap_lg; + +#endif /* _MIOA701_H */ diff --git a/arch/arm/mach-pxa/mp900.c b/arch/arm/mach-pxa/mp900.c index 14f6aaf8fcc9..4d89029e5401 100644 --- a/arch/arm/mach-pxa/mp900.c +++ b/arch/arm/mach-pxa/mp900.c @@ -22,7 +22,7 @@ #include #include -#include +#include "pxa25x.h" #include "generic.h" static void isp116x_pfm_delay(struct device *dev, int delay) diff --git a/arch/arm/mach-pxa/mxm8x10.c b/arch/arm/mach-pxa/mxm8x10.c index d04ed4961e60..9a22ae0ad8c9 100644 --- a/arch/arm/mach-pxa/mxm8x10.c +++ b/arch/arm/mach-pxa/mxm8x10.c @@ -29,9 +29,9 @@ #include #include #include -#include +#include "pxa320.h" -#include +#include "mxm8x10.h" #include "devices.h" #include "generic.h" diff --git a/arch/arm/mach-pxa/mxm8x10.h b/arch/arm/mach-pxa/mxm8x10.h new file mode 100644 index 000000000000..ffa15665a418 --- /dev/null +++ b/arch/arm/mach-pxa/mxm8x10.h @@ -0,0 +1,21 @@ +#ifndef __MACH_MXM_8X10_H +#define __MACH_MXM_8X10_H + +#define MXM_8X10_ETH_PHYS 0x13000000 + +#if defined(CONFIG_MMC) + +#define MXM_8X10_SD_nCD (72) +#define MXM_8X10_SD_WP (84) + +extern void mxm_8x10_mmc_init(void); +#else +static inline void mxm_8x10_mmc_init(void) {} +#endif + +extern void mxm_8x10_usb_host_init(void); +extern void mxm_8x10_ac97_init(void); + +extern void mxm_8x10_barebones_init(void); + +#endif /* __MACH_MXM_8X10_H */ diff --git a/arch/arm/mach-pxa/palm27x.c b/arch/arm/mach-pxa/palm27x.c index 8fbfb10047ec..e5ae99db1de4 100644 --- a/arch/arm/mach-pxa/palm27x.c +++ b/arch/arm/mach-pxa/palm27x.c @@ -28,14 +28,14 @@ #include #include -#include +#include "pxa27x.h" #include #include #include #include -#include +#include "udc.h" #include -#include +#include "palm27x.h" #include "generic.h" #include "devices.h" diff --git a/arch/arm/mach-pxa/palm27x.h b/arch/arm/mach-pxa/palm27x.h new file mode 100644 index 000000000000..d4eac3d6ffb5 --- /dev/null +++ b/arch/arm/mach-pxa/palm27x.h @@ -0,0 +1,81 @@ +/* + * Common functions for Palm LD, T5, TX, Z72 + * + * Copyright (C) 2010 + * Marek Vasut + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ +#ifndef __INCLUDE_MACH_PALM27X__ +#define __INCLUDE_MACH_PALM27X__ + +#if defined(CONFIG_MMC_PXA) || defined(CONFIG_MMC_PXA_MODULE) +extern void __init palm27x_mmc_init(int detect, int ro, int power, + int power_inverted); +#else +static inline void palm27x_mmc_init(int detect, int ro, int power, + int power_inverted) +{} +#endif + +#if defined(CONFIG_SUSPEND) +extern void __init palm27x_pm_init(unsigned long str_base); +#else +static inline void palm27x_pm_init(unsigned long str_base) {} +#endif + +#if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULE) +extern struct pxafb_mode_info palm_320x480_lcd_mode; +extern struct pxafb_mode_info palm_320x320_lcd_mode; +extern struct pxafb_mode_info palm_320x320_new_lcd_mode; +extern void __init palm27x_lcd_init(int power, + struct pxafb_mode_info *mode); +#else +#define palm27x_lcd_init(power, mode) do {} while (0) +#endif + +#if defined(CONFIG_USB_PXA27X) || \ + defined(CONFIG_USB_PXA27X_MODULE) +extern void __init palm27x_udc_init(int vbus, int pullup, + int vbus_inverted); +#else +static inline void palm27x_udc_init(int vbus, int pullup, int vbus_inverted) {} +#endif + +#if defined(CONFIG_IRDA) || defined(CONFIG_IRDA_MODULE) +extern void __init palm27x_irda_init(int pwdn); +#else +static inline void palm27x_irda_init(int pwdn) {} +#endif + +#if defined(CONFIG_TOUCHSCREEN_WM97XX) || \ + defined(CONFIG_TOUCHSCREEN_WM97XX_MODULE) +extern void __init palm27x_ac97_init(int minv, int maxv, int jack, + int reset); +#else +static inline void palm27x_ac97_init(int minv, int maxv, int jack, int reset) {} +#endif + +#if defined(CONFIG_BACKLIGHT_PWM) || defined(CONFIG_BACKLIGHT_PWM_MODULE) +extern void __init palm27x_pwm_init(int bl, int lcd); +#else +static inline void palm27x_pwm_init(int bl, int lcd) {} +#endif + +#if defined(CONFIG_PDA_POWER) || defined(CONFIG_PDA_POWER_MODULE) +extern void __init palm27x_power_init(int ac, int usb); +#else +static inline void palm27x_power_init(int ac, int usb) {} +#endif + +#if defined(CONFIG_REGULATOR_MAX1586) || \ + defined(CONFIG_REGULATOR_MAX1586_MODULE) +extern void __init palm27x_pmic_init(void); +#else +static inline void palm27x_pmic_init(void) {} +#endif + +#endif /* __INCLUDE_MACH_PALM27X__ */ diff --git a/arch/arm/mach-pxa/palmld.c b/arch/arm/mach-pxa/palmld.c index cf210b11ffcc..980f2847f5b5 100644 --- a/arch/arm/mach-pxa/palmld.c +++ b/arch/arm/mach-pxa/palmld.c @@ -32,7 +32,7 @@ #include #include -#include +#include "pxa27x.h" #include #include #include @@ -40,7 +40,7 @@ #include #include #include -#include +#include "palm27x.h" #include "generic.h" #include "devices.h" diff --git a/arch/arm/mach-pxa/palmt5.c b/arch/arm/mach-pxa/palmt5.c index 3ed9b029428b..876144aa3564 100644 --- a/arch/arm/mach-pxa/palmt5.c +++ b/arch/arm/mach-pxa/palmt5.c @@ -33,16 +33,16 @@ #include #include -#include +#include "pxa27x.h" #include -#include +#include "palmt5.h" #include #include #include #include -#include +#include "udc.h" #include -#include +#include "palm27x.h" #include "generic.h" #include "devices.h" diff --git a/arch/arm/mach-pxa/palmt5.h b/arch/arm/mach-pxa/palmt5.h new file mode 100644 index 000000000000..f850cc9de1b4 --- /dev/null +++ b/arch/arm/mach-pxa/palmt5.h @@ -0,0 +1,86 @@ +/* + * GPIOs and interrupts for Palm Tungsten|T5 Handheld Computer + * + * Authors: Ales Snuparek + * Marek Vasut + * Justin Kendrick + * RichardT5 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#ifndef _INCLUDE_PALMT5_H_ +#define _INCLUDE_PALMT5_H_ + +#include /* PXA_GPIO_TO_IRQ */ + +/** HERE ARE GPIOs **/ + +/* GPIOs */ +#define GPIO_NR_PALMT5_GPIO_RESET 1 + +#define GPIO_NR_PALMT5_POWER_DETECT 90 +#define GPIO_NR_PALMT5_HOTSYNC_BUTTON_N 10 +#define GPIO_NR_PALMT5_EARPHONE_DETECT 107 + +/* SD/MMC */ +#define GPIO_NR_PALMT5_SD_DETECT_N 14 +#define GPIO_NR_PALMT5_SD_POWER 114 +#define GPIO_NR_PALMT5_SD_READONLY 115 + +/* TOUCHSCREEN */ +#define GPIO_NR_PALMT5_WM9712_IRQ 27 + +/* IRDA - disable GPIO connected to SD pin of tranceiver (TFBS4710?) ? */ +#define GPIO_NR_PALMT5_IR_DISABLE 40 + +/* USB */ +#define GPIO_NR_PALMT5_USB_DETECT_N 15 +#define GPIO_NR_PALMT5_USB_PULLUP 93 + +/* LCD/BACKLIGHT */ +#define GPIO_NR_PALMT5_BL_POWER 84 +#define GPIO_NR_PALMT5_LCD_POWER 96 + +/* BLUETOOTH */ +#define GPIO_NR_PALMT5_BT_POWER 17 +#define GPIO_NR_PALMT5_BT_RESET 83 + +/* INTERRUPTS */ +#define IRQ_GPIO_PALMT5_SD_DETECT_N PXA_GPIO_TO_IRQ(GPIO_NR_PALMT5_SD_DETECT_N) +#define IRQ_GPIO_PALMT5_WM9712_IRQ PXA_GPIO_TO_IRQ(GPIO_NR_PALMT5_WM9712_IRQ) +#define IRQ_GPIO_PALMT5_USB_DETECT PXA_GPIO_TO_IRQ(GPIO_NR_PALMT5_USB_DETECT) +#define IRQ_GPIO_PALMT5_GPIO_RESET PXA_GPIO_TO_IRQ(GPIO_NR_PALMT5_GPIO_RESET) + +/** HERE ARE INIT VALUES **/ + +/* Various addresses */ +#define PALMT5_PHYS_RAM_START 0xa0000000 +#define PALMT5_PHYS_IO_START 0x40000000 +#define PALMT5_STR_BASE 0xa0200000 + +/* TOUCHSCREEN */ +#define AC97_LINK_FRAME 21 + +/* BATTERY */ +#define PALMT5_BAT_MAX_VOLTAGE 4000 /* 4.00v current voltage */ +#define PALMT5_BAT_MIN_VOLTAGE 3550 /* 3.55v critical voltage */ +#define PALMT5_BAT_MAX_CURRENT 0 /* unknown */ +#define PALMT5_BAT_MIN_CURRENT 0 /* unknown */ +#define PALMT5_BAT_MAX_CHARGE 1 /* unknown */ +#define PALMT5_BAT_MIN_CHARGE 1 /* unknown */ +#define PALMT5_MAX_LIFE_MINS 360 /* on-life in minutes */ + +#define PALMT5_BAT_MEASURE_DELAY (HZ * 1) + +/* BACKLIGHT */ +#define PALMT5_MAX_INTENSITY 0xFE +#define PALMT5_DEFAULT_INTENSITY 0x7E +#define PALMT5_LIMIT_MASK 0x7F +#define PALMT5_PRESCALER 0x3F +#define PALMT5_PERIOD_NS 3500 + +#endif diff --git a/arch/arm/mach-pxa/palmtc.c b/arch/arm/mach-pxa/palmtc.c index 0b5c3876720c..18946594a7c8 100644 --- a/arch/arm/mach-pxa/palmtc.c +++ b/arch/arm/mach-pxa/palmtc.c @@ -32,13 +32,13 @@ #include #include -#include +#include "pxa25x.h" #include #include #include #include #include -#include +#include "udc.h" #include "generic.h" #include "devices.h" diff --git a/arch/arm/mach-pxa/palmte2.c b/arch/arm/mach-pxa/palmte2.c index e64bb4326e69..36b46141a28b 100644 --- a/arch/arm/mach-pxa/palmte2.c +++ b/arch/arm/mach-pxa/palmte2.c @@ -32,13 +32,13 @@ #include #include -#include +#include "pxa25x.h" #include -#include +#include "palmte2.h" #include #include #include -#include +#include "udc.h" #include #include "generic.h" diff --git a/arch/arm/mach-pxa/palmte2.h b/arch/arm/mach-pxa/palmte2.h new file mode 100644 index 000000000000..f89e989a7637 --- /dev/null +++ b/arch/arm/mach-pxa/palmte2.h @@ -0,0 +1,68 @@ +/* + * GPIOs and interrupts for Palm Tungsten|E2 Handheld Computer + * + * Author: + * Carlos Eduardo Medaglia Dyonisio + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#ifndef _INCLUDE_PALMTE2_H_ +#define _INCLUDE_PALMTE2_H_ + +/** HERE ARE GPIOs **/ + +/* GPIOs */ +#define GPIO_NR_PALMTE2_POWER_DETECT 9 +#define GPIO_NR_PALMTE2_HOTSYNC_BUTTON_N 4 +#define GPIO_NR_PALMTE2_EARPHONE_DETECT 15 + +/* SD/MMC */ +#define GPIO_NR_PALMTE2_SD_DETECT_N 10 +#define GPIO_NR_PALMTE2_SD_POWER 55 +#define GPIO_NR_PALMTE2_SD_READONLY 51 + +/* IRDA - disable GPIO connected to SD pin of tranceiver (TFBS4710?) ? */ +#define GPIO_NR_PALMTE2_IR_DISABLE 48 + +/* USB */ +#define GPIO_NR_PALMTE2_USB_DETECT_N 35 +#define GPIO_NR_PALMTE2_USB_PULLUP 53 + +/* LCD/BACKLIGHT */ +#define GPIO_NR_PALMTE2_BL_POWER 56 +#define GPIO_NR_PALMTE2_LCD_POWER 37 + +/* KEYS */ +#define GPIO_NR_PALMTE2_KEY_NOTES 5 +#define GPIO_NR_PALMTE2_KEY_TASKS 7 +#define GPIO_NR_PALMTE2_KEY_CALENDAR 11 +#define GPIO_NR_PALMTE2_KEY_CONTACTS 13 +#define GPIO_NR_PALMTE2_KEY_CENTER 14 +#define GPIO_NR_PALMTE2_KEY_LEFT 19 +#define GPIO_NR_PALMTE2_KEY_RIGHT 20 +#define GPIO_NR_PALMTE2_KEY_DOWN 21 +#define GPIO_NR_PALMTE2_KEY_UP 22 + +/** HERE ARE INIT VALUES **/ + +/* BACKLIGHT */ +#define PALMTE2_MAX_INTENSITY 0xFE +#define PALMTE2_DEFAULT_INTENSITY 0x7E +#define PALMTE2_LIMIT_MASK 0x7F +#define PALMTE2_PRESCALER 0x3F +#define PALMTE2_PERIOD_NS 3500 + +/* BATTERY */ +#define PALMTE2_BAT_MAX_VOLTAGE 4000 /* 4.00v current voltage */ +#define PALMTE2_BAT_MIN_VOLTAGE 3550 /* 3.55v critical voltage */ +#define PALMTE2_BAT_MAX_CURRENT 0 /* unknown */ +#define PALMTE2_BAT_MIN_CURRENT 0 /* unknown */ +#define PALMTE2_BAT_MAX_CHARGE 1 /* unknown */ +#define PALMTE2_BAT_MIN_CHARGE 1 /* unknown */ +#define PALMTE2_MAX_LIFE_MINS 360 /* on-life in minutes */ + +#endif diff --git a/arch/arm/mach-pxa/palmtreo.c b/arch/arm/mach-pxa/palmtreo.c index d8b937c870de..b2aae54bed42 100644 --- a/arch/arm/mach-pxa/palmtreo.c +++ b/arch/arm/mach-pxa/palmtreo.c @@ -31,20 +31,20 @@ #include #include -#include -#include +#include "pxa27x.h" +#include "pxa27x-udc.h" #include -#include +#include "palmtreo.h" #include #include #include #include -#include +#include "udc.h" #include #include #include #include -#include +#include "palm27x.h" #include diff --git a/arch/arm/mach-pxa/palmtreo.h b/arch/arm/mach-pxa/palmtreo.h new file mode 100644 index 000000000000..714b6574393e --- /dev/null +++ b/arch/arm/mach-pxa/palmtreo.h @@ -0,0 +1,68 @@ +/* + * GPIOs and interrupts for Palm Treo smartphones + * + * currently supported: + * Palm Treo 680 (GSM) + * Palm Centro 685 (GSM) + * + * Author: Tomas Cech + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * find more info at www.hackndev.com + * + */ + +#ifndef _INCLUDE_TREO_H_ +#define _INCLUDE_TREO_H_ + +/* GPIOs */ +#define GPIO_NR_TREO_POWER_DETECT 0 +#define GPIO_NR_TREO_AMP_EN 27 +#define GPIO_NR_TREO_GREEN_LED 20 +#define GPIO_NR_TREO_RED_LED 79 +#define GPIO_NR_TREO_SD_DETECT_N 113 +#define GPIO_NR_TREO_EP_DETECT_N 116 +#define GPIO_NR_TREO_USB_DETECT 1 +#define GPIO_NR_TREO_USB_PULLUP 114 +#define GPIO_NR_TREO_GSM_POWER 40 +#define GPIO_NR_TREO_GSM_RESET 87 +#define GPIO_NR_TREO_GSM_WAKE 57 +#define GPIO_NR_TREO_GSM_HOST_WAKE 14 +#define GPIO_NR_TREO_GSM_TRIGGER 10 +#define GPIO_NR_TREO_IR_EN 115 +#define GPIO_NR_TREO_IR_TXD 47 +#define GPIO_NR_TREO_BL_POWER 38 +#define GPIO_NR_TREO_LCD_POWER 25 + +/* Treo680 specific GPIOs */ +#define GPIO_NR_TREO680_SD_READONLY 33 +#define GPIO_NR_TREO680_SD_POWER 42 +#define GPIO_NR_TREO680_VIBRATE_EN 44 +#define GPIO_NR_TREO680_KEYB_BL 24 +#define GPIO_NR_TREO680_BT_EN 43 +#define GPIO_NR_TREO680_LCD_POWER 77 +#define GPIO_NR_TREO680_LCD_EN 86 +#define GPIO_NR_TREO680_LCD_EN_N 25 + +/* Centro685 specific GPIOs */ +#define GPIO_NR_CENTRO_SD_POWER 21 +#define GPIO_NR_CENTRO_VIBRATE_EN 22 +#define GPIO_NR_CENTRO_KEYB_BL 33 +#define GPIO_NR_CENTRO_BT_EN 80 + +/* Various addresses */ +#define TREO_PHYS_RAM_START 0xa0000000 +#define TREO_PHYS_IO_START 0x40000000 +#define TREO_STR_BASE 0xa2000000 + +/* BACKLIGHT */ +#define TREO_MAX_INTENSITY 254 +#define TREO_DEFAULT_INTENSITY 160 +#define TREO_LIMIT_MASK 0x7F +#define TREO_PRESCALER 63 +#define TREO_PERIOD_NS 3500 + +#endif diff --git a/arch/arm/mach-pxa/palmtx.c b/arch/arm/mach-pxa/palmtx.c index 83f830dd8ad8..b84b2eb24ccd 100644 --- a/arch/arm/mach-pxa/palmtx.c +++ b/arch/arm/mach-pxa/palmtx.c @@ -37,16 +37,16 @@ #include #include -#include +#include "pxa27x.h" #include #include #include #include #include #include -#include +#include "udc.h" #include -#include +#include "palm27x.h" #include "generic.h" #include "devices.h" diff --git a/arch/arm/mach-pxa/palmz72.c b/arch/arm/mach-pxa/palmz72.c index 1a35ddf218da..abba86f3e254 100644 --- a/arch/arm/mach-pxa/palmz72.c +++ b/arch/arm/mach-pxa/palmz72.c @@ -37,18 +37,18 @@ #include #include -#include +#include "pxa27x.h" #include -#include +#include "palmz72.h" #include #include #include #include -#include +#include "udc.h" #include -#include +#include "palm27x.h" -#include +#include "pm.h" #include #include diff --git a/arch/arm/mach-pxa/palmz72.h b/arch/arm/mach-pxa/palmz72.h new file mode 100644 index 000000000000..0d4700a79612 --- /dev/null +++ b/arch/arm/mach-pxa/palmz72.h @@ -0,0 +1,84 @@ +/* + * GPIOs and interrupts for Palm Zire72 Handheld Computer + * + * Authors: Alex Osborne + * Jan Herman <2hp@seznam.cz> + * Sergey Lapin + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#ifndef _INCLUDE_PALMZ72_H_ +#define _INCLUDE_PALMZ72_H_ + +/* Power and control */ +#define GPIO_NR_PALMZ72_GPIO_RESET 1 +#define GPIO_NR_PALMZ72_POWER_DETECT 0 + +/* SD/MMC */ +#define GPIO_NR_PALMZ72_SD_DETECT_N 14 +#define GPIO_NR_PALMZ72_SD_POWER_N 98 +#define GPIO_NR_PALMZ72_SD_RO 115 + +/* Touchscreen */ +#define GPIO_NR_PALMZ72_WM9712_IRQ 27 + +/* IRDA - disable GPIO connected to SD pin of tranceiver (TFBS4710?) ? */ +#define GPIO_NR_PALMZ72_IR_DISABLE 49 + +/* USB */ +#define GPIO_NR_PALMZ72_USB_DETECT_N 15 +#define GPIO_NR_PALMZ72_USB_PULLUP 95 + +/* LCD/Backlight */ +#define GPIO_NR_PALMZ72_BL_POWER 20 +#define GPIO_NR_PALMZ72_LCD_POWER 96 + +/* LED */ +#define GPIO_NR_PALMZ72_LED_GREEN 88 + +/* Bluetooth */ +#define GPIO_NR_PALMZ72_BT_POWER 17 +#define GPIO_NR_PALMZ72_BT_RESET 83 + +/* Camera */ +#define GPIO_NR_PALMZ72_CAM_PWDN 56 +#define GPIO_NR_PALMZ72_CAM_RESET 57 +#define GPIO_NR_PALMZ72_CAM_POWER 91 + +/** Initial values **/ + +/* Battery */ +#define PALMZ72_BAT_MAX_VOLTAGE 4000 /* 4.00v current voltage */ +#define PALMZ72_BAT_MIN_VOLTAGE 3550 /* 3.55v critical voltage */ +#define PALMZ72_BAT_MAX_CURRENT 0 /* unknown */ +#define PALMZ72_BAT_MIN_CURRENT 0 /* unknown */ +#define PALMZ72_BAT_MAX_CHARGE 1 /* unknown */ +#define PALMZ72_BAT_MIN_CHARGE 1 /* unknown */ +#define PALMZ72_MAX_LIFE_MINS 360 /* on-life in minutes */ + +/* Backlight */ +#define PALMZ72_MAX_INTENSITY 0xFE +#define PALMZ72_DEFAULT_INTENSITY 0x7E +#define PALMZ72_LIMIT_MASK 0x7F +#define PALMZ72_PRESCALER 0x3F +#define PALMZ72_PERIOD_NS 3500 + +#ifdef CONFIG_PM +struct palmz72_resume_info { + u32 magic0; /* 0x0 */ + u32 magic1; /* 0x4 */ + u32 resume_addr; /* 0x8 */ + u32 pad[11]; /* 0xc..0x37 */ + u32 arm_control; /* 0x38 */ + u32 aux_control; /* 0x3c */ + u32 ttb; /* 0x40 */ + u32 domain_access; /* 0x44 */ + u32 process_id; /* 0x48 */ +}; +#endif +#endif + diff --git a/arch/arm/mach-pxa/pcm027.c b/arch/arm/mach-pxa/pcm027.c index 69918c7e3f1f..ccca9f7575c3 100644 --- a/arch/arm/mach-pxa/pcm027.c +++ b/arch/arm/mach-pxa/pcm027.c @@ -30,8 +30,8 @@ #include #include -#include -#include +#include "pxa27x.h" +#include "pcm027.h" #include "generic.h" /* diff --git a/arch/arm/mach-pxa/pcm027.h b/arch/arm/mach-pxa/pcm027.h new file mode 100644 index 000000000000..047cdf234f25 --- /dev/null +++ b/arch/arm/mach-pxa/pcm027.h @@ -0,0 +1,86 @@ +/* + * arch/arm/mach-pxa/include/mach/pcm027.h + * + * (c) 2003 Phytec Messtechnik GmbH + * (c) 2007 Juergen Beisert + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +/* + * Definitions of CPU card resources only + */ + +#include /* PXA_GPIO_TO_IRQ */ + +/* phyCORE-PXA270 (PCM027) Interrupts */ +#define PCM027_IRQ(x) (IRQ_BOARD_START + (x)) +#define PCM027_BTDET_IRQ PCM027_IRQ(0) +#define PCM027_FF_RI_IRQ PCM027_IRQ(1) +#define PCM027_MMCDET_IRQ PCM027_IRQ(2) +#define PCM027_PM_5V_IRQ PCM027_IRQ(3) + +#define PCM027_NR_IRQS (IRQ_BOARD_START + 32) + +/* I2C RTC */ +#define PCM027_RTC_IRQ_GPIO 0 +#define PCM027_RTC_IRQ PXA_GPIO_TO_IRQ(PCM027_RTC_IRQ_GPIO) +#define PCM027_RTC_IRQ_EDGE IRQ_TYPE_EDGE_FALLING +#define ADR_PCM027_RTC 0x51 /* I2C address */ + +/* I2C EEPROM */ +#define ADR_PCM027_EEPROM 0x54 /* I2C address */ + +/* Ethernet chip (SMSC91C111) */ +#define PCM027_ETH_IRQ_GPIO 52 +#define PCM027_ETH_IRQ PXA_GPIO_TO_IRQ(PCM027_ETH_IRQ_GPIO) +#define PCM027_ETH_IRQ_EDGE IRQ_TYPE_EDGE_RISING +#define PCM027_ETH_PHYS PXA_CS5_PHYS +#define PCM027_ETH_SIZE (1*1024*1024) + +/* CAN controller SJA1000 (unsupported yet) */ +#define PCM027_CAN_IRQ_GPIO 114 +#define PCM027_CAN_IRQ PXA_GPIO_TO_IRQ(PCM027_CAN_IRQ_GPIO) +#define PCM027_CAN_IRQ_EDGE IRQ_TYPE_EDGE_FALLING +#define PCM027_CAN_PHYS 0x22000000 +#define PCM027_CAN_SIZE 0x100 + +/* SPI GPIO expander (unsupported yet) */ +#define PCM027_EGPIO_IRQ_GPIO 27 +#define PCM027_EGPIO_IRQ PXA_GPIO_TO_IRQ(PCM027_EGPIO_IRQ_GPIO) +#define PCM027_EGPIO_IRQ_EDGE IRQ_TYPE_EDGE_FALLING +#define PCM027_EGPIO_CS 24 +/* + * TODO: Switch this pin from dedicated usage to GPIO if + * more than the MAX7301 device is connected to this SPI bus + */ +#define PCM027_EGPIO_CS_MODE GPIO24_SFRM_MD + +/* Flash memory */ +#define PCM027_FLASH_PHYS 0x00000000 +#define PCM027_FLASH_SIZE 0x02000000 + +/* onboard LEDs connected to GPIO */ +#define PCM027_LED_CPU 90 +#define PCM027_LED_HEARD_BEAT 91 + +/* + * This CPU module needs a baseboard to work. After basic initializing + * its own devices, it calls baseboard's init function. + * TODO: Add your own basebaord init function and call it from + * inside pcm027_init(). This example here is for the developmen board. + * Refer pcm990-baseboard.c + */ +extern void pcm990_baseboard_init(void); diff --git a/arch/arm/mach-pxa/pcm990-baseboard.c b/arch/arm/mach-pxa/pcm990-baseboard.c index b71c96f614f9..e802b112a255 100644 --- a/arch/arm/mach-pxa/pcm990-baseboard.c +++ b/arch/arm/mach-pxa/pcm990-baseboard.c @@ -32,11 +32,11 @@ #include #include -#include +#include "pxa27x.h" #include #include #include -#include +#include "pcm990_baseboard.h" #include #include "devices.h" diff --git a/arch/arm/mach-pxa/pcm990_baseboard.h b/arch/arm/mach-pxa/pcm990_baseboard.h new file mode 100644 index 000000000000..79d35adfa786 --- /dev/null +++ b/arch/arm/mach-pxa/pcm990_baseboard.h @@ -0,0 +1,212 @@ +/* + * arch/arm/mach-pxa/include/mach/pcm990_baseboard.h + * + * (c) 2003 Phytec Messtechnik GmbH + * (c) 2007 Juergen Beisert + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include "pcm027.h" +#include /* PXA_GPIO_TO_IRQ */ + +/* + * definitions relevant only when the PCM-990 + * development base board is in use + */ + +/* CPLD's interrupt controller is connected to PCM-027 GPIO 9 */ +#define PCM990_CTRL_INT_IRQ_GPIO 9 +#define PCM990_CTRL_INT_IRQ PXA_GPIO_TO_IRQ(PCM990_CTRL_INT_IRQ_GPIO) +#define PCM990_CTRL_INT_IRQ_EDGE IRQ_TYPE_EDGE_RISING +#define PCM990_CTRL_PHYS PXA_CS1_PHYS /* 16-Bit */ +#define PCM990_CTRL_SIZE (1*1024*1024) + +#define PCM990_CTRL_PWR_IRQ_GPIO 14 +#define PCM990_CTRL_PWR_IRQ PXA_GPIO_TO_IRQ(PCM990_CTRL_PWR_IRQ_GPIO) +#define PCM990_CTRL_PWR_IRQ_EDGE IRQ_TYPE_EDGE_RISING + +/* visible CPLD (U7) registers */ +#define PCM990_CTRL_REG0 0x0000 /* RESET REGISTER */ +#define PCM990_CTRL_SYSRES 0x0001 /* System RESET REGISTER */ +#define PCM990_CTRL_RESOUT 0x0002 /* RESETOUT Enable REGISTER */ +#define PCM990_CTRL_RESGPIO 0x0004 /* RESETGPIO Enable REGISTER */ + +#define PCM990_CTRL_REG1 0x0002 /* Power REGISTER */ +#define PCM990_CTRL_5VOFF 0x0001 /* Disable 5V Regulators */ +#define PCM990_CTRL_CANPWR 0x0004 /* Enable CANPWR ADUM */ +#define PCM990_CTRL_PM_5V 0x0008 /* Read 5V OK */ + +#define PCM990_CTRL_REG2 0x0004 /* LED REGISTER */ +#define PCM990_CTRL_LEDPWR 0x0001 /* POWER LED enable */ +#define PCM990_CTRL_LEDBAS 0x0002 /* BASIS LED enable */ +#define PCM990_CTRL_LEDUSR 0x0004 /* USER LED enable */ + +#define PCM990_CTRL_REG3 0x0006 /* LCD CTRL REGISTER 3 */ +#define PCM990_CTRL_LCDPWR 0x0001 /* RW LCD Power on */ +#define PCM990_CTRL_LCDON 0x0002 /* RW LCD Latch on */ +#define PCM990_CTRL_LCDPOS1 0x0004 /* RW POS 1 */ +#define PCM990_CTRL_LCDPOS2 0x0008 /* RW POS 2 */ + +#define PCM990_CTRL_REG4 0x0008 /* MMC1 CTRL REGISTER 4 */ +#define PCM990_CTRL_MMC1PWR 0x0001 /* RW MMC1 Power on */ + +#define PCM990_CTRL_REG5 0x000A /* MMC2 CTRL REGISTER 5 */ +#define PCM990_CTRL_MMC2PWR 0x0001 /* RW MMC2 Power on */ +#define PCM990_CTRL_MMC2LED 0x0002 /* RW MMC2 LED */ +#define PCM990_CTRL_MMC2DE 0x0004 /* R MMC2 Card detect */ +#define PCM990_CTRL_MMC2WP 0x0008 /* R MMC2 Card write protect */ + +#define PCM990_CTRL_INTSETCLR 0x000C /* Interrupt Clear REGISTER */ +#define PCM990_CTRL_INTC0 0x0001 /* Clear Reg BT Detect */ +#define PCM990_CTRL_INTC1 0x0002 /* Clear Reg FR RI */ +#define PCM990_CTRL_INTC2 0x0004 /* Clear Reg MMC1 Detect */ +#define PCM990_CTRL_INTC3 0x0008 /* Clear Reg PM_5V off */ + +#define PCM990_CTRL_INTMSKENA 0x000E /* Interrupt Enable REGISTER */ +#define PCM990_CTRL_ENAINT0 0x0001 /* Enable Int BT Detect */ +#define PCM990_CTRL_ENAINT1 0x0002 /* Enable Int FR RI */ +#define PCM990_CTRL_ENAINT2 0x0004 /* Enable Int MMC1 Detect */ +#define PCM990_CTRL_ENAINT3 0x0008 /* Enable Int PM_5V off */ + +#define PCM990_CTRL_REG8 0x0014 /* Uart REGISTER */ +#define PCM990_CTRL_FFSD 0x0001 /* BT Uart Enable */ +#define PCM990_CTRL_BTSD 0x0002 /* FF Uart Enable */ +#define PCM990_CTRL_FFRI 0x0004 /* FF Uart RI detect */ +#define PCM990_CTRL_BTRX 0x0008 /* BT Uart Rx detect */ + +#define PCM990_CTRL_REG9 0x0010 /* AC97 Flash REGISTER */ +#define PCM990_CTRL_FLWP 0x0001 /* pC Flash Write Protect */ +#define PCM990_CTRL_FLDIS 0x0002 /* pC Flash Disable */ +#define PCM990_CTRL_AC97ENA 0x0004 /* Enable AC97 Expansion */ + +#define PCM990_CTRL_REG10 0x0012 /* GPS-REGISTER */ +#define PCM990_CTRL_GPSPWR 0x0004 /* GPS-Modul Power on */ +#define PCM990_CTRL_GPSENA 0x0008 /* GPS-Modul Enable */ + +#define PCM990_CTRL_REG11 0x0014 /* Accu REGISTER */ +#define PCM990_CTRL_ACENA 0x0001 /* Charge Enable */ +#define PCM990_CTRL_ACSEL 0x0002 /* Charge Akku -> DC Enable */ +#define PCM990_CTRL_ACPRES 0x0004 /* DC Present */ +#define PCM990_CTRL_ACALARM 0x0008 /* Error Akku */ + +/* + * IDE + */ +#define PCM990_IDE_IRQ_GPIO 13 +#define PCM990_IDE_IRQ PXA_GPIO_TO_IRQ(PCM990_IDE_IRQ_GPIO) +#define PCM990_IDE_IRQ_EDGE IRQ_TYPE_EDGE_RISING +#define PCM990_IDE_PLD_PHYS 0x20000000 /* 16 bit wide */ +#define PCM990_IDE_PLD_BASE 0xee000000 +#define PCM990_IDE_PLD_SIZE (1*1024*1024) + +/* visible CPLD (U6) registers */ +#define PCM990_IDE_PLD_REG0 0x1000 /* OFFSET IDE REGISTER 0 */ +#define PCM990_IDE_PM5V 0x0004 /* R System VCC_5V */ +#define PCM990_IDE_STBY 0x0008 /* R System StandBy */ + +#define PCM990_IDE_PLD_REG1 0x1002 /* OFFSET IDE REGISTER 1 */ +#define PCM990_IDE_IDEMODE 0x0001 /* R TrueIDE Mode */ +#define PCM990_IDE_DMAENA 0x0004 /* RW DMA Enable */ +#define PCM990_IDE_DMA1_0 0x0008 /* RW 1=DREQ1 0=DREQ0 */ + +#define PCM990_IDE_PLD_REG2 0x1004 /* OFFSET IDE REGISTER 2 */ +#define PCM990_IDE_RESENA 0x0001 /* RW IDE Reset Bit enable */ +#define PCM990_IDE_RES 0x0002 /* RW IDE Reset Bit */ +#define PCM990_IDE_RDY 0x0008 /* RDY */ + +#define PCM990_IDE_PLD_REG3 0x1006 /* OFFSET IDE REGISTER 3 */ +#define PCM990_IDE_IDEOE 0x0001 /* RW Latch on Databus */ +#define PCM990_IDE_IDEON 0x0002 /* RW Latch on Control Address */ +#define PCM990_IDE_IDEIN 0x0004 /* RW Latch on Interrupt usw. */ + +#define PCM990_IDE_PLD_REG4 0x1008 /* OFFSET IDE REGISTER 4 */ +#define PCM990_IDE_PWRENA 0x0001 /* RW IDE Power enable */ +#define PCM990_IDE_5V 0x0002 /* R IDE Power 5V */ +#define PCM990_IDE_PWG 0x0008 /* R IDE Power is on */ + +#define PCM990_IDE_PLD_P2V(x) ((x) - PCM990_IDE_PLD_PHYS + PCM990_IDE_PLD_BASE) +#define PCM990_IDE_PLD_V2P(x) ((x) - PCM990_IDE_PLD_BASE + PCM990_IDE_PLD_PHYS) + +/* + * Compact Flash + */ +#define PCM990_CF_IRQ_GPIO 11 +#define PCM990_CF_IRQ PXA_GPIO_TO_IRQ(PCM990_CF_IRQ_GPIO) +#define PCM990_CF_IRQ_EDGE IRQ_TYPE_EDGE_RISING + +#define PCM990_CF_CD_GPIO 12 +#define PCM990_CF_CD PXA_GPIO_TO_IRQ(PCM990_CF_CD_GPIO) +#define PCM990_CF_CD_EDGE IRQ_TYPE_EDGE_RISING + +#define PCM990_CF_PLD_PHYS 0x30000000 /* 16 bit wide */ + +/* visible CPLD (U6) registers */ +#define PCM990_CF_PLD_REG0 0x1000 /* OFFSET CF REGISTER 0 */ +#define PCM990_CF_REG0_LED 0x0001 /* RW LED on */ +#define PCM990_CF_REG0_BLK 0x0002 /* RW LED flash when access */ +#define PCM990_CF_REG0_PM5V 0x0004 /* R System VCC_5V enable */ +#define PCM990_CF_REG0_STBY 0x0008 /* R System StandBy */ + +#define PCM990_CF_PLD_REG1 0x1002 /* OFFSET CF REGISTER 1 */ +#define PCM990_CF_REG1_IDEMODE 0x0001 /* RW CF card run as TrueIDE */ +#define PCM990_CF_REG1_CF0 0x0002 /* RW CF card at ADDR 0x28000000 */ + +#define PCM990_CF_PLD_REG2 0x1004 /* OFFSET CF REGISTER 2 */ +#define PCM990_CF_REG2_RES 0x0002 /* RW CF RESET BIT */ +#define PCM990_CF_REG2_RDYENA 0x0004 /* RW Enable CF_RDY */ +#define PCM990_CF_REG2_RDY 0x0008 /* R CF_RDY auf PWAIT */ + +#define PCM990_CF_PLD_REG3 0x1006 /* OFFSET CF REGISTER 3 */ +#define PCM990_CF_REG3_CFOE 0x0001 /* RW Latch on Databus */ +#define PCM990_CF_REG3_CFON 0x0002 /* RW Latch on Control Address */ +#define PCM990_CF_REG3_CFIN 0x0004 /* RW Latch on Interrupt usw. */ +#define PCM990_CF_REG3_CFCD 0x0008 /* RW Latch on CD1/2 VS1/2 usw */ + +#define PCM990_CF_PLD_REG4 0x1008 /* OFFSET CF REGISTER 4 */ +#define PCM990_CF_REG4_PWRENA 0x0001 /* RW CF Power on (CD1/2 = "00") */ +#define PCM990_CF_REG4_5_3V 0x0002 /* RW 1 = 5V CF_VCC 0 = 3 V CF_VCC */ +#define PCM990_CF_REG4_3B 0x0004 /* RW 3.0V Backup from VCC (5_3V=0) */ +#define PCM990_CF_REG4_PWG 0x0008 /* R CF-Power is on */ + +#define PCM990_CF_PLD_REG5 0x100A /* OFFSET CF REGISTER 5 */ +#define PCM990_CF_REG5_BVD1 0x0001 /* R CF /BVD1 */ +#define PCM990_CF_REG5_BVD2 0x0002 /* R CF /BVD2 */ +#define PCM990_CF_REG5_VS1 0x0004 /* R CF /VS1 */ +#define PCM990_CF_REG5_VS2 0x0008 /* R CF /VS2 */ + +#define PCM990_CF_PLD_REG6 0x100C /* OFFSET CF REGISTER 6 */ +#define PCM990_CF_REG6_CD1 0x0001 /* R CF Card_Detect1 */ +#define PCM990_CF_REG6_CD2 0x0002 /* R CF Card_Detect2 */ + +/* + * Wolfson AC97 Touch + */ +#define PCM990_AC97_IRQ_GPIO 10 +#define PCM990_AC97_IRQ PXA_GPIO_TO_IRQ(PCM990_AC97_IRQ_GPIO) +#define PCM990_AC97_IRQ_EDGE IRQ_TYPE_EDGE_RISING + +/* + * MMC phyCORE + */ +#define PCM990_MMC0_IRQ_GPIO 9 +#define PCM990_MMC0_IRQ PXA_GPIO_TO_IRQ(PCM990_MMC0_IRQ_GPIO) +#define PCM990_MMC0_IRQ_EDGE IRQ_TYPE_EDGE_FALLING + +/* + * USB phyCore + */ +#define PCM990_USB_OVERCURRENT (88 | GPIO_ALT_FN_1_IN) +#define PCM990_USB_PWR_EN (89 | GPIO_ALT_FN_2_OUT) diff --git a/arch/arm/mach-pxa/pm.c b/arch/arm/mach-pxa/pm.c index 37178a8559b1..388463b99090 100644 --- a/arch/arm/mach-pxa/pm.c +++ b/arch/arm/mach-pxa/pm.c @@ -16,7 +16,7 @@ #include #include -#include +#include "pm.h" struct pxa_cpu_pm_fns *pxa_cpu_pm_fns; static unsigned long *sleep_save; diff --git a/arch/arm/mach-pxa/pm.h b/arch/arm/mach-pxa/pm.h new file mode 100644 index 000000000000..51558bcee999 --- /dev/null +++ b/arch/arm/mach-pxa/pm.h @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2005 Richard Purdie + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#include + +struct pxa_cpu_pm_fns { + int save_count; + void (*save)(unsigned long *); + void (*restore)(unsigned long *); + int (*valid)(suspend_state_t state); + void (*enter)(suspend_state_t state); + int (*prepare)(void); + void (*finish)(void); +}; + +extern struct pxa_cpu_pm_fns *pxa_cpu_pm_fns; + +/* sleep.S */ +extern int pxa25x_finish_suspend(unsigned long); +extern int pxa27x_finish_suspend(unsigned long); + +extern int pxa_pm_enter(suspend_state_t state); +extern int pxa_pm_prepare(void); +extern void pxa_pm_finish(void); + +/* NOTE: this is for PM debugging on Lubbock, it's really a big + * ugly, but let's keep the crap minimum here, instead of direct + * accessing the LUBBOCK CPLD registers in arch/arm/mach-pxa/pm.c + */ +#ifdef CONFIG_ARCH_LUBBOCK +extern void lubbock_set_hexled(uint32_t value); +#else +#define lubbock_set_hexled(x) +#endif diff --git a/arch/arm/mach-pxa/poodle.c b/arch/arm/mach-pxa/poodle.c index 195b1121c8f1..62a119137be7 100644 --- a/arch/arm/mach-pxa/poodle.c +++ b/arch/arm/mach-pxa/poodle.c @@ -41,9 +41,9 @@ #include #include -#include +#include "pxa25x.h" #include -#include +#include "udc.h" #include #include #include diff --git a/arch/arm/mach-pxa/pxa25x.c b/arch/arm/mach-pxa/pxa25x.c index 1dc85ffc3e20..a177bf45feef 100644 --- a/arch/arm/mach-pxa/pxa25x.c +++ b/arch/arm/mach-pxa/pxa25x.c @@ -30,9 +30,9 @@ #include #include #include -#include +#include "pxa25x.h" #include -#include +#include "pm.h" #include #include diff --git a/arch/arm/mach-pxa/pxa25x.h b/arch/arm/mach-pxa/pxa25x.h new file mode 100644 index 000000000000..2011e8da0592 --- /dev/null +++ b/arch/arm/mach-pxa/pxa25x.h @@ -0,0 +1,9 @@ +#ifndef __MACH_PXA25x_H +#define __MACH_PXA25x_H + +#include +#include +#include "mfp-pxa25x.h" +#include + +#endif /* __MACH_PXA25x_H */ diff --git a/arch/arm/mach-pxa/pxa27x-udc.h b/arch/arm/mach-pxa/pxa27x-udc.h new file mode 100644 index 000000000000..4cf28f670706 --- /dev/null +++ b/arch/arm/mach-pxa/pxa27x-udc.h @@ -0,0 +1,257 @@ +#ifndef _ASM_ARCH_PXA27X_UDC_H +#define _ASM_ARCH_PXA27X_UDC_H + +#ifdef _ASM_ARCH_PXA25X_UDC_H +#error You cannot include both PXA25x and PXA27x UDC support +#endif + +#define UDCCR __REG(0x40600000) /* UDC Control Register */ +#define UDCCR_OEN (1 << 31) /* On-the-Go Enable */ +#define UDCCR_AALTHNP (1 << 30) /* A-device Alternate Host Negotiation + Protocol Port Support */ +#define UDCCR_AHNP (1 << 29) /* A-device Host Negotiation Protocol + Support */ +#define UDCCR_BHNP (1 << 28) /* B-device Host Negotiation Protocol + Enable */ +#define UDCCR_DWRE (1 << 16) /* Device Remote Wake-up Enable */ +#define UDCCR_ACN (0x03 << 11) /* Active UDC configuration Number */ +#define UDCCR_ACN_S 11 +#define UDCCR_AIN (0x07 << 8) /* Active UDC interface Number */ +#define UDCCR_AIN_S 8 +#define UDCCR_AAISN (0x07 << 5) /* Active UDC Alternate Interface + Setting Number */ +#define UDCCR_AAISN_S 5 +#define UDCCR_SMAC (1 << 4) /* Switch Endpoint Memory to Active + Configuration */ +#define UDCCR_EMCE (1 << 3) /* Endpoint Memory Configuration + Error */ +#define UDCCR_UDR (1 << 2) /* UDC Resume */ +#define UDCCR_UDA (1 << 1) /* UDC Active */ +#define UDCCR_UDE (1 << 0) /* UDC Enable */ + +#define UDCICR0 __REG(0x40600004) /* UDC Interrupt Control Register0 */ +#define UDCICR1 __REG(0x40600008) /* UDC Interrupt Control Register1 */ +#define UDCICR_FIFOERR (1 << 1) /* FIFO Error interrupt for EP */ +#define UDCICR_PKTCOMPL (1 << 0) /* Packet Complete interrupt for EP */ + +#define UDC_INT_FIFOERROR (0x2) +#define UDC_INT_PACKETCMP (0x1) + +#define UDCICR_INT(n,intr) (((intr) & 0x03) << (((n) & 0x0F) * 2)) +#define UDCICR1_IECC (1 << 31) /* IntEn - Configuration Change */ +#define UDCICR1_IESOF (1 << 30) /* IntEn - Start of Frame */ +#define UDCICR1_IERU (1 << 29) /* IntEn - Resume */ +#define UDCICR1_IESU (1 << 28) /* IntEn - Suspend */ +#define UDCICR1_IERS (1 << 27) /* IntEn - Reset */ + +#define UDCISR0 __REG(0x4060000C) /* UDC Interrupt Status Register 0 */ +#define UDCISR1 __REG(0x40600010) /* UDC Interrupt Status Register 1 */ +#define UDCISR_INT(n,intr) (((intr) & 0x03) << (((n) & 0x0F) * 2)) +#define UDCISR1_IRCC (1 << 31) /* IntReq - Configuration Change */ +#define UDCISR1_IRSOF (1 << 30) /* IntReq - Start of Frame */ +#define UDCISR1_IRRU (1 << 29) /* IntReq - Resume */ +#define UDCISR1_IRSU (1 << 28) /* IntReq - Suspend */ +#define UDCISR1_IRRS (1 << 27) /* IntReq - Reset */ + +#define UDCFNR __REG(0x40600014) /* UDC Frame Number Register */ +#define UDCOTGICR __REG(0x40600018) /* UDC On-The-Go interrupt control */ +#define UDCOTGICR_IESF (1 << 24) /* OTG SET_FEATURE command recvd */ +#define UDCOTGICR_IEXR (1 << 17) /* Extra Transceiver Interrupt + Rising Edge Interrupt Enable */ +#define UDCOTGICR_IEXF (1 << 16) /* Extra Transceiver Interrupt + Falling Edge Interrupt Enable */ +#define UDCOTGICR_IEVV40R (1 << 9) /* OTG Vbus Valid 4.0V Rising Edge + Interrupt Enable */ +#define UDCOTGICR_IEVV40F (1 << 8) /* OTG Vbus Valid 4.0V Falling Edge + Interrupt Enable */ +#define UDCOTGICR_IEVV44R (1 << 7) /* OTG Vbus Valid 4.4V Rising Edge + Interrupt Enable */ +#define UDCOTGICR_IEVV44F (1 << 6) /* OTG Vbus Valid 4.4V Falling Edge + Interrupt Enable */ +#define UDCOTGICR_IESVR (1 << 5) /* OTG Session Valid Rising Edge + Interrupt Enable */ +#define UDCOTGICR_IESVF (1 << 4) /* OTG Session Valid Falling Edge + Interrupt Enable */ +#define UDCOTGICR_IESDR (1 << 3) /* OTG A-Device SRP Detect Rising + Edge Interrupt Enable */ +#define UDCOTGICR_IESDF (1 << 2) /* OTG A-Device SRP Detect Falling + Edge Interrupt Enable */ +#define UDCOTGICR_IEIDR (1 << 1) /* OTG ID Change Rising Edge + Interrupt Enable */ +#define UDCOTGICR_IEIDF (1 << 0) /* OTG ID Change Falling Edge + Interrupt Enable */ + +#define UP2OCR __REG(0x40600020) /* USB Port 2 Output Control register */ +#define UP3OCR __REG(0x40600024) /* USB Port 2 Output Control register */ + +#define UP2OCR_CPVEN (1 << 0) /* Charge Pump Vbus Enable */ +#define UP2OCR_CPVPE (1 << 1) /* Charge Pump Vbus Pulse Enable */ +#define UP2OCR_DPPDE (1 << 2) /* Host Port 2 Transceiver D+ Pull Down Enable */ +#define UP2OCR_DMPDE (1 << 3) /* Host Port 2 Transceiver D- Pull Down Enable */ +#define UP2OCR_DPPUE (1 << 4) /* Host Port 2 Transceiver D+ Pull Up Enable */ +#define UP2OCR_DMPUE (1 << 5) /* Host Port 2 Transceiver D- Pull Up Enable */ +#define UP2OCR_DPPUBE (1 << 6) /* Host Port 2 Transceiver D+ Pull Up Bypass Enable */ +#define UP2OCR_DMPUBE (1 << 7) /* Host Port 2 Transceiver D- Pull Up Bypass Enable */ +#define UP2OCR_EXSP (1 << 8) /* External Transceiver Speed Control */ +#define UP2OCR_EXSUS (1 << 9) /* External Transceiver Speed Enable */ +#define UP2OCR_IDON (1 << 10) /* OTG ID Read Enable */ +#define UP2OCR_HXS (1 << 16) /* Host Port 2 Transceiver Output Select */ +#define UP2OCR_HXOE (1 << 17) /* Host Port 2 Transceiver Output Enable */ +#define UP2OCR_SEOS(x) ((x & 7) << 24) /* Single-Ended Output Select */ + +#define UDCCSN(x) __REG2(0x40600100, (x) << 2) +#define UDCCSR0 __REG(0x40600100) /* UDC Control/Status register - Endpoint 0 */ +#define UDCCSR0_SA (1 << 7) /* Setup Active */ +#define UDCCSR0_RNE (1 << 6) /* Receive FIFO Not Empty */ +#define UDCCSR0_FST (1 << 5) /* Force Stall */ +#define UDCCSR0_SST (1 << 4) /* Sent Stall */ +#define UDCCSR0_DME (1 << 3) /* DMA Enable */ +#define UDCCSR0_FTF (1 << 2) /* Flush Transmit FIFO */ +#define UDCCSR0_IPR (1 << 1) /* IN Packet Ready */ +#define UDCCSR0_OPC (1 << 0) /* OUT Packet Complete */ + +#define UDCCSRA __REG(0x40600104) /* UDC Control/Status register - Endpoint A */ +#define UDCCSRB __REG(0x40600108) /* UDC Control/Status register - Endpoint B */ +#define UDCCSRC __REG(0x4060010C) /* UDC Control/Status register - Endpoint C */ +#define UDCCSRD __REG(0x40600110) /* UDC Control/Status register - Endpoint D */ +#define UDCCSRE __REG(0x40600114) /* UDC Control/Status register - Endpoint E */ +#define UDCCSRF __REG(0x40600118) /* UDC Control/Status register - Endpoint F */ +#define UDCCSRG __REG(0x4060011C) /* UDC Control/Status register - Endpoint G */ +#define UDCCSRH __REG(0x40600120) /* UDC Control/Status register - Endpoint H */ +#define UDCCSRI __REG(0x40600124) /* UDC Control/Status register - Endpoint I */ +#define UDCCSRJ __REG(0x40600128) /* UDC Control/Status register - Endpoint J */ +#define UDCCSRK __REG(0x4060012C) /* UDC Control/Status register - Endpoint K */ +#define UDCCSRL __REG(0x40600130) /* UDC Control/Status register - Endpoint L */ +#define UDCCSRM __REG(0x40600134) /* UDC Control/Status register - Endpoint M */ +#define UDCCSRN __REG(0x40600138) /* UDC Control/Status register - Endpoint N */ +#define UDCCSRP __REG(0x4060013C) /* UDC Control/Status register - Endpoint P */ +#define UDCCSRQ __REG(0x40600140) /* UDC Control/Status register - Endpoint Q */ +#define UDCCSRR __REG(0x40600144) /* UDC Control/Status register - Endpoint R */ +#define UDCCSRS __REG(0x40600148) /* UDC Control/Status register - Endpoint S */ +#define UDCCSRT __REG(0x4060014C) /* UDC Control/Status register - Endpoint T */ +#define UDCCSRU __REG(0x40600150) /* UDC Control/Status register - Endpoint U */ +#define UDCCSRV __REG(0x40600154) /* UDC Control/Status register - Endpoint V */ +#define UDCCSRW __REG(0x40600158) /* UDC Control/Status register - Endpoint W */ +#define UDCCSRX __REG(0x4060015C) /* UDC Control/Status register - Endpoint X */ + +#define UDCCSR_DPE (1 << 9) /* Data Packet Error */ +#define UDCCSR_FEF (1 << 8) /* Flush Endpoint FIFO */ +#define UDCCSR_SP (1 << 7) /* Short Packet Control/Status */ +#define UDCCSR_BNE (1 << 6) /* Buffer Not Empty (IN endpoints) */ +#define UDCCSR_BNF (1 << 6) /* Buffer Not Full (OUT endpoints) */ +#define UDCCSR_FST (1 << 5) /* Force STALL */ +#define UDCCSR_SST (1 << 4) /* Sent STALL */ +#define UDCCSR_DME (1 << 3) /* DMA Enable */ +#define UDCCSR_TRN (1 << 2) /* Tx/Rx NAK */ +#define UDCCSR_PC (1 << 1) /* Packet Complete */ +#define UDCCSR_FS (1 << 0) /* FIFO needs service */ + +#define UDCBCN(x) __REG2(0x40600200, (x)<<2) +#define UDCBCR0 __REG(0x40600200) /* Byte Count Register - EP0 */ +#define UDCBCRA __REG(0x40600204) /* Byte Count Register - EPA */ +#define UDCBCRB __REG(0x40600208) /* Byte Count Register - EPB */ +#define UDCBCRC __REG(0x4060020C) /* Byte Count Register - EPC */ +#define UDCBCRD __REG(0x40600210) /* Byte Count Register - EPD */ +#define UDCBCRE __REG(0x40600214) /* Byte Count Register - EPE */ +#define UDCBCRF __REG(0x40600218) /* Byte Count Register - EPF */ +#define UDCBCRG __REG(0x4060021C) /* Byte Count Register - EPG */ +#define UDCBCRH __REG(0x40600220) /* Byte Count Register - EPH */ +#define UDCBCRI __REG(0x40600224) /* Byte Count Register - EPI */ +#define UDCBCRJ __REG(0x40600228) /* Byte Count Register - EPJ */ +#define UDCBCRK __REG(0x4060022C) /* Byte Count Register - EPK */ +#define UDCBCRL __REG(0x40600230) /* Byte Count Register - EPL */ +#define UDCBCRM __REG(0x40600234) /* Byte Count Register - EPM */ +#define UDCBCRN __REG(0x40600238) /* Byte Count Register - EPN */ +#define UDCBCRP __REG(0x4060023C) /* Byte Count Register - EPP */ +#define UDCBCRQ __REG(0x40600240) /* Byte Count Register - EPQ */ +#define UDCBCRR __REG(0x40600244) /* Byte Count Register - EPR */ +#define UDCBCRS __REG(0x40600248) /* Byte Count Register - EPS */ +#define UDCBCRT __REG(0x4060024C) /* Byte Count Register - EPT */ +#define UDCBCRU __REG(0x40600250) /* Byte Count Register - EPU */ +#define UDCBCRV __REG(0x40600254) /* Byte Count Register - EPV */ +#define UDCBCRW __REG(0x40600258) /* Byte Count Register - EPW */ +#define UDCBCRX __REG(0x4060025C) /* Byte Count Register - EPX */ + +#define UDCDN(x) __REG2(0x40600300, (x)<<2) +#define PHYS_UDCDN(x) (0x40600300 + ((x)<<2)) +#define PUDCDN(x) (volatile u32 *)(io_p2v(PHYS_UDCDN((x)))) +#define UDCDR0 __REG(0x40600300) /* Data Register - EP0 */ +#define UDCDRA __REG(0x40600304) /* Data Register - EPA */ +#define UDCDRB __REG(0x40600308) /* Data Register - EPB */ +#define UDCDRC __REG(0x4060030C) /* Data Register - EPC */ +#define UDCDRD __REG(0x40600310) /* Data Register - EPD */ +#define UDCDRE __REG(0x40600314) /* Data Register - EPE */ +#define UDCDRF __REG(0x40600318) /* Data Register - EPF */ +#define UDCDRG __REG(0x4060031C) /* Data Register - EPG */ +#define UDCDRH __REG(0x40600320) /* Data Register - EPH */ +#define UDCDRI __REG(0x40600324) /* Data Register - EPI */ +#define UDCDRJ __REG(0x40600328) /* Data Register - EPJ */ +#define UDCDRK __REG(0x4060032C) /* Data Register - EPK */ +#define UDCDRL __REG(0x40600330) /* Data Register - EPL */ +#define UDCDRM __REG(0x40600334) /* Data Register - EPM */ +#define UDCDRN __REG(0x40600338) /* Data Register - EPN */ +#define UDCDRP __REG(0x4060033C) /* Data Register - EPP */ +#define UDCDRQ __REG(0x40600340) /* Data Register - EPQ */ +#define UDCDRR __REG(0x40600344) /* Data Register - EPR */ +#define UDCDRS __REG(0x40600348) /* Data Register - EPS */ +#define UDCDRT __REG(0x4060034C) /* Data Register - EPT */ +#define UDCDRU __REG(0x40600350) /* Data Register - EPU */ +#define UDCDRV __REG(0x40600354) /* Data Register - EPV */ +#define UDCDRW __REG(0x40600358) /* Data Register - EPW */ +#define UDCDRX __REG(0x4060035C) /* Data Register - EPX */ + +#define UDCCN(x) __REG2(0x40600400, (x)<<2) +#define UDCCRA __REG(0x40600404) /* Configuration register EPA */ +#define UDCCRB __REG(0x40600408) /* Configuration register EPB */ +#define UDCCRC __REG(0x4060040C) /* Configuration register EPC */ +#define UDCCRD __REG(0x40600410) /* Configuration register EPD */ +#define UDCCRE __REG(0x40600414) /* Configuration register EPE */ +#define UDCCRF __REG(0x40600418) /* Configuration register EPF */ +#define UDCCRG __REG(0x4060041C) /* Configuration register EPG */ +#define UDCCRH __REG(0x40600420) /* Configuration register EPH */ +#define UDCCRI __REG(0x40600424) /* Configuration register EPI */ +#define UDCCRJ __REG(0x40600428) /* Configuration register EPJ */ +#define UDCCRK __REG(0x4060042C) /* Configuration register EPK */ +#define UDCCRL __REG(0x40600430) /* Configuration register EPL */ +#define UDCCRM __REG(0x40600434) /* Configuration register EPM */ +#define UDCCRN __REG(0x40600438) /* Configuration register EPN */ +#define UDCCRP __REG(0x4060043C) /* Configuration register EPP */ +#define UDCCRQ __REG(0x40600440) /* Configuration register EPQ */ +#define UDCCRR __REG(0x40600444) /* Configuration register EPR */ +#define UDCCRS __REG(0x40600448) /* Configuration register EPS */ +#define UDCCRT __REG(0x4060044C) /* Configuration register EPT */ +#define UDCCRU __REG(0x40600450) /* Configuration register EPU */ +#define UDCCRV __REG(0x40600454) /* Configuration register EPV */ +#define UDCCRW __REG(0x40600458) /* Configuration register EPW */ +#define UDCCRX __REG(0x4060045C) /* Configuration register EPX */ + +#define UDCCONR_CN (0x03 << 25) /* Configuration Number */ +#define UDCCONR_CN_S (25) +#define UDCCONR_IN (0x07 << 22) /* Interface Number */ +#define UDCCONR_IN_S (22) +#define UDCCONR_AISN (0x07 << 19) /* Alternate Interface Number */ +#define UDCCONR_AISN_S (19) +#define UDCCONR_EN (0x0f << 15) /* Endpoint Number */ +#define UDCCONR_EN_S (15) +#define UDCCONR_ET (0x03 << 13) /* Endpoint Type: */ +#define UDCCONR_ET_S (13) +#define UDCCONR_ET_INT (0x03 << 13) /* Interrupt */ +#define UDCCONR_ET_BULK (0x02 << 13) /* Bulk */ +#define UDCCONR_ET_ISO (0x01 << 13) /* Isochronous */ +#define UDCCONR_ET_NU (0x00 << 13) /* Not used */ +#define UDCCONR_ED (1 << 12) /* Endpoint Direction */ +#define UDCCONR_MPS (0x3ff << 2) /* Maximum Packet Size */ +#define UDCCONR_MPS_S (2) +#define UDCCONR_DE (1 << 1) /* Double Buffering Enable */ +#define UDCCONR_EE (1 << 0) /* Endpoint Enable */ + + +#define UDC_INT_FIFOERROR (0x2) +#define UDC_INT_PACKETCMP (0x1) + +#define UDC_FNR_MASK (0x7ff) + +#define UDCCSR_WR_MASK (UDCCSR_DME|UDCCSR_FST) +#define UDC_BCR_MASK (0x3ff) + +#endif diff --git a/arch/arm/mach-pxa/pxa27x.c b/arch/arm/mach-pxa/pxa27x.c index ffc424028557..8dfd1755c659 100644 --- a/arch/arm/mach-pxa/pxa27x.c +++ b/arch/arm/mach-pxa/pxa27x.c @@ -28,10 +28,10 @@ #include #include #include -#include +#include "pxa27x.h" #include #include -#include +#include "pm.h" #include #include diff --git a/arch/arm/mach-pxa/pxa27x.h b/arch/arm/mach-pxa/pxa27x.h new file mode 100644 index 000000000000..075131d83eab --- /dev/null +++ b/arch/arm/mach-pxa/pxa27x.h @@ -0,0 +1,25 @@ +#ifndef __MACH_PXA27x_H +#define __MACH_PXA27x_H + +#include +#include +#include +#include "mfp-pxa27x.h" +#include + +#define ARB_CNTRL __REG(0x48000048) /* Arbiter Control Register */ + +#define ARB_DMA_SLV_PARK (1<<31) /* Be parked with DMA slave when idle */ +#define ARB_CI_PARK (1<<30) /* Be parked with Camera Interface when idle */ +#define ARB_EX_MEM_PARK (1<<29) /* Be parked with external MEMC when idle */ +#define ARB_INT_MEM_PARK (1<<28) /* Be parked with internal MEMC when idle */ +#define ARB_USB_PARK (1<<27) /* Be parked with USB when idle */ +#define ARB_LCD_PARK (1<<26) /* Be parked with LCD when idle */ +#define ARB_DMA_PARK (1<<25) /* Be parked with DMA when idle */ +#define ARB_CORE_PARK (1<<24) /* Be parked with core when idle */ +#define ARB_LOCK_FLAG (1<<23) /* Only Locking masters gain access to the bus */ + +extern int pxa27x_set_pwrmode(unsigned int mode); +extern void pxa27x_cpu_pm_enter(suspend_state_t state); + +#endif /* __MACH_PXA27x_H */ diff --git a/arch/arm/mach-pxa/pxa2xx.c b/arch/arm/mach-pxa/pxa2xx.c index 447dcbb22f6f..6b5e566f52c8 100644 --- a/arch/arm/mach-pxa/pxa2xx.c +++ b/arch/arm/mach-pxa/pxa2xx.c @@ -17,7 +17,7 @@ #include #include -#include +#include "mfp-pxa25x.h" #include #include diff --git a/arch/arm/mach-pxa/pxa300.c b/arch/arm/mach-pxa/pxa300.c index 28c5b5686638..df83b1bddf34 100644 --- a/arch/arm/mach-pxa/pxa300.c +++ b/arch/arm/mach-pxa/pxa300.c @@ -18,7 +18,7 @@ #include #include -#include +#include "pxa300.h" #include "generic.h" #include "devices.h" diff --git a/arch/arm/mach-pxa/pxa300.h b/arch/arm/mach-pxa/pxa300.h new file mode 100644 index 000000000000..59fa41025c80 --- /dev/null +++ b/arch/arm/mach-pxa/pxa300.h @@ -0,0 +1,7 @@ +#ifndef __MACH_PXA300_H +#define __MACH_PXA300_H + +#include "pxa3xx.h" +#include "mfp-pxa300.h" + +#endif /* __MACH_PXA300_H */ diff --git a/arch/arm/mach-pxa/pxa320.c b/arch/arm/mach-pxa/pxa320.c index 2f55bb4b9087..a26eec57eec6 100644 --- a/arch/arm/mach-pxa/pxa320.c +++ b/arch/arm/mach-pxa/pxa320.c @@ -18,7 +18,7 @@ #include #include -#include +#include "pxa320.h" #include "generic.h" #include "devices.h" diff --git a/arch/arm/mach-pxa/pxa320.h b/arch/arm/mach-pxa/pxa320.h new file mode 100644 index 000000000000..b9e5115a1c30 --- /dev/null +++ b/arch/arm/mach-pxa/pxa320.h @@ -0,0 +1,8 @@ +#ifndef __MACH_PXA320_H +#define __MACH_PXA320_H + +#include "pxa3xx.h" +#include "mfp-pxa320.h" + +#endif /* __MACH_PXA320_H */ + diff --git a/arch/arm/mach-pxa/pxa3xx-ulpi.c b/arch/arm/mach-pxa/pxa3xx-ulpi.c index 1c85275cb768..eba595fac8ca 100644 --- a/arch/arm/mach-pxa/pxa3xx-ulpi.c +++ b/arch/arm/mach-pxa/pxa3xx-ulpi.c @@ -26,7 +26,7 @@ #include #include -#include +#include "regs-u2d.h" #include struct pxa3xx_u2d_ulpi { diff --git a/arch/arm/mach-pxa/pxa3xx.c b/arch/arm/mach-pxa/pxa3xx.c index 20ce2d386f17..a1c4c888f246 100644 --- a/arch/arm/mach-pxa/pxa3xx.c +++ b/arch/arm/mach-pxa/pxa3xx.c @@ -30,7 +30,7 @@ #include #include #include -#include +#include "pm.h" #include #include #include diff --git a/arch/arm/mach-pxa/pxa3xx.h b/arch/arm/mach-pxa/pxa3xx.h new file mode 100644 index 000000000000..b4143fb6631f --- /dev/null +++ b/arch/arm/mach-pxa/pxa3xx.h @@ -0,0 +1,8 @@ +#ifndef __MACH_PXA3XX_H +#define __MACH_PXA3XX_H + +#include +#include +#include + +#endif /* __MACH_PXA3XX_H */ diff --git a/arch/arm/mach-pxa/pxa930.c b/arch/arm/mach-pxa/pxa930.c index ab624487cf39..da912be6eae7 100644 --- a/arch/arm/mach-pxa/pxa930.c +++ b/arch/arm/mach-pxa/pxa930.c @@ -17,7 +17,7 @@ #include #include -#include +#include "pxa930.h" #include "devices.h" diff --git a/arch/arm/mach-pxa/pxa930.h b/arch/arm/mach-pxa/pxa930.h new file mode 100644 index 000000000000..4eceb02978e8 --- /dev/null +++ b/arch/arm/mach-pxa/pxa930.h @@ -0,0 +1,7 @@ +#ifndef __MACH_PXA930_H +#define __MACH_PXA930_H + +#include "pxa3xx.h" +#include "mfp-pxa930.h" + +#endif /* __MACH_PXA930_H */ diff --git a/arch/arm/mach-pxa/raumfeld.c b/arch/arm/mach-pxa/raumfeld.c index 36571a9a44fe..0f67d94be297 100644 --- a/arch/arm/mach-pxa/raumfeld.c +++ b/arch/arm/mach-pxa/raumfeld.c @@ -49,7 +49,7 @@ #include #include -#include +#include "pxa300.h" #include #include #include diff --git a/arch/arm/mach-pxa/regs-rtc.h b/arch/arm/mach-pxa/regs-rtc.h new file mode 100644 index 000000000000..f0e4a589bbe1 --- /dev/null +++ b/arch/arm/mach-pxa/regs-rtc.h @@ -0,0 +1,23 @@ +#ifndef __ASM_MACH_REGS_RTC_H +#define __ASM_MACH_REGS_RTC_H + +#include + +/* + * Real Time Clock + */ + +#define RCNR __REG(0x40900000) /* RTC Count Register */ +#define RTAR __REG(0x40900004) /* RTC Alarm Register */ +#define RTSR __REG(0x40900008) /* RTC Status Register */ +#define RTTR __REG(0x4090000C) /* RTC Timer Trim Register */ +#define PIAR __REG(0x40900038) /* Periodic Interrupt Alarm Register */ + +#define RTSR_PICE (1 << 15) /* Periodic interrupt count enable */ +#define RTSR_PIALE (1 << 14) /* Periodic interrupt Alarm enable */ +#define RTSR_HZE (1 << 3) /* HZ interrupt enable */ +#define RTSR_ALE (1 << 2) /* RTC alarm interrupt enable */ +#define RTSR_HZ (1 << 1) /* HZ rising-edge detected */ +#define RTSR_AL (1 << 0) /* RTC alarm detected */ + +#endif /* __ASM_MACH_REGS_RTC_H */ diff --git a/arch/arm/mach-pxa/regs-u2d.h b/arch/arm/mach-pxa/regs-u2d.h new file mode 100644 index 000000000000..c15c0c57de08 --- /dev/null +++ b/arch/arm/mach-pxa/regs-u2d.h @@ -0,0 +1,200 @@ +#ifndef __ASM_ARCH_PXA3xx_U2D_H +#define __ASM_ARCH_PXA3xx_U2D_H + +#include + +/* + * USB2 device controller registers and bits definitions + */ +#define U2DCR (0x0000) /* U2D Control Register */ +#define U2DCR_NDC (1 << 31) /* NAK During Config */ +#define U2DCR_HSTC (0x7 << 28) /* High Speed Timeout Calibration */ +#define U2DCR_SPEOREN (1 << 27) /* Short Packet EOR INTR generation Enable */ +#define U2DCR_FSTC (0x7 << 24) /* Full Speed Timeout Calibration */ +#define U2DCR_UCLKOVR (1 << 22) /* UTM Clock Override */ +#define U2DCR_ABP (1 << 21) /* Application Bus Power */ +#define U2DCR_ADD (1 << 20) /* Application Device Disconnect */ +#define U2DCR_CC (1 << 19) /* Configuration Change */ +#define U2DCR_HS (1 << 18) /* High Speed USB Detection */ +#define U2DCR_SMAC (1 << 17) /* Switch Endpoint Memory to Active Configuration */ +#define U2DCR_DWRE (1 << 16) /* Device Remote Wake-up Feature */ +#define U2DCR_ACN (0xf << 12) /* Active U2D Configuration Number */ +#define U2DCR_AIN (0xf << 8) /* Active U2D Interface Number */ +#define U2DCR_AAISN (0xf << 4) /* Active U2D Alternate Interface Setting Number */ +#define U2DCR_EMCE (1 << 3) /* Endpoint Memory Configuration Error */ +#define U2DCR_UDR (1 << 2) /* U2D Resume */ +#define U2DCR_UDA (1 << 1) /* U2D Active */ +#define U2DCR_UDE (1 << 0) /* U2D Enable */ + +#define U2DICR (0x0004) /* U2D Interrupt Control Register */ +#define U2DISR (0x000C) /* U2D Interrupt Status Register */ +#define U2DINT_CC (1 << 31) /* Interrupt - Configuration Change */ +#define U2DINT_SOF (1 << 30) /* Interrupt - SOF */ +#define U2DINT_USOF (1 << 29) /* Interrupt - micro SOF */ +#define U2DINT_RU (1 << 28) /* Interrupt - Resume */ +#define U2DINT_SU (1 << 27) /* Interrupt - Suspend */ +#define U2DINT_RS (1 << 26) /* Interrupt - Reset */ +#define U2DINT_DPE (1 << 25) /* Interrupt - Data Packet Error */ +#define U2DINT_FIFOERR (0x4) /* Interrupt - endpoint FIFO error */ +#define U2DINT_PACKETCMP (0x2) /* Interrupt - endpoint packet complete */ +#define U2DINT_SPACKETCMP (0x1) /* Interrupt - endpoint short packet complete */ + +#define U2DFNR (0x0014) /* U2D Frame Number Register */ + +#define U2DINT(n, intr) (((intr) & 0x07) << (((n) & 0x07) * 3)) +#define U2DICR2 (0x0008) /* U2D Interrupt Control Register 2 */ +#define U2DISR2 (0x0010) /* U2D Interrupt Status Register 2 */ + +#define U2DOTGCR (0x0020) /* U2D OTG Control Register */ +#define U2DOTGCR_OTGEN (1 << 31) /* On-The-Go Enable */ +#define U2DOTGCR_AALTHNP (1 << 30) /* A-device Alternate Host Negotiation Protocal Port Support */ +#define U2DOTGCR_AHNP (1 << 29) /* A-device Host Negotiation Protocal Support */ +#define U2DOTGCR_BHNP (1 << 28) /* B-device Host Negotiation Protocal Enable */ + +#ifdef CONFIG_CPU_PXA930 +#define U2DOTGCR_LPA (1 << 15) /* ULPI low power mode active */ +#define U2DOTGCR_IESI (1 << 13) /* OTG interrupt Enable */ +#define U2DOTGCR_ISSI (1 << 12) /* OTG interrupt status */ +#endif + +#define U2DOTGCR_CKAF (1 << 5) /* Carkit Mode Alternate Function Select */ +#define U2DOTGCR_UTMID (1 << 4) /* UTMI Interface Disable */ +#define U2DOTGCR_ULAF (1 << 3) /* ULPI Mode Alternate Function Select */ +#define U2DOTGCR_SMAF (1 << 2) /* Serial Mode Alternate Function Select */ +#define U2DOTGCR_RTSM (1 << 1) /* Return to Synchronous Mode (ULPI Mode) */ +#define U2DOTGCR_ULE (1 << 0) /* ULPI Wrapper Enable */ + +#define U2DOTGICR (0x0024) /* U2D OTG Interrupt Control Register */ +#define U2DOTGISR (0x0028) /* U2D OTG Interrupt Status Register */ + +#define U2DOTGINT_SF (1 << 17) /* OTG Set Feature Command Received */ +#define U2DOTGINT_SI (1 << 16) /* OTG Interrupt */ +#define U2DOTGINT_RLS1 (1 << 14) /* RXCMD Linestate[1] Change Interrupt Rise */ +#define U2DOTGINT_RLS0 (1 << 13) /* RXCMD Linestate[0] Change Interrupt Rise */ +#define U2DOTGINT_RID (1 << 12) /* RXCMD OTG ID Change Interrupt Rise */ +#define U2DOTGINT_RSE (1 << 11) /* RXCMD OTG Session End Interrupt Rise */ +#define U2DOTGINT_RSV (1 << 10) /* RXCMD OTG Session Valid Interrupt Rise */ +#define U2DOTGINT_RVV (1 << 9) /* RXCMD OTG Vbus Valid Interrupt Rise */ +#define U2DOTGINT_RCK (1 << 8) /* RXCMD Carkit Interrupt Rise */ +#define U2DOTGINT_FLS1 (1 << 6) /* RXCMD Linestate[1] Change Interrupt Fall */ +#define U2DOTGINT_FLS0 (1 << 5) /* RXCMD Linestate[0] Change Interrupt Fall */ +#define U2DOTGINT_FID (1 << 4) /* RXCMD OTG ID Change Interrupt Fall */ +#define U2DOTGINT_FSE (1 << 3) /* RXCMD OTG Session End Interrupt Fall */ +#define U2DOTGINT_FSV (1 << 2) /* RXCMD OTG Session Valid Interrupt Fall */ +#define U2DOTGINT_FVV (1 << 1) /* RXCMD OTG Vbus Valid Interrupt Fall */ +#define U2DOTGINT_FCK (1 << 0) /* RXCMD Carkit Interrupt Fall */ + +#define U2DOTGUSR (0x002C) /* U2D OTG ULPI Status Register */ +#define U2DOTGUSR_LPA (1 << 31) /* ULPI Low Power Mode Active */ +#define U2DOTGUSR_S6A (1 << 30) /* ULPI Serial Mode (6-pin) Active */ +#define U2DOTGUSR_S3A (1 << 29) /* ULPI Serial Mode (3-pin) Active */ +#define U2DOTGUSR_CKA (1 << 28) /* ULPI Car Kit Mode Active */ +#define U2DOTGUSR_LS1 (1 << 6) /* RXCMD Linestate 1 Status */ +#define U2DOTGUSR_LS0 (1 << 5) /* RXCMD Linestate 0 Status */ +#define U2DOTGUSR_ID (1 << 4) /* OTG IDGnd Status */ +#define U2DOTGUSR_SE (1 << 3) /* OTG Session End Status */ +#define U2DOTGUSR_SV (1 << 2) /* OTG Session Valid Status */ +#define U2DOTGUSR_VV (1 << 1) /* OTG Vbus Valid Status */ +#define U2DOTGUSR_CK (1 << 0) /* Carkit Interrupt Status */ + +#define U2DOTGUCR (0x0030) /* U2D OTG ULPI Control Register */ +#define U2DOTGUCR_RUN (1 << 25) /* RUN */ +#define U2DOTGUCR_RNW (1 << 24) /* Read or Write operation */ +#define U2DOTGUCR_ADDR (0x3f << 16) /* Address of the ULPI PHY register */ +#define U2DOTGUCR_WDATA (0xff << 8) /* The data for a WRITE command */ +#define U2DOTGUCR_RDATA (0xff << 0) /* The data for a READ command */ + +#define U2DP3CR (0x0034) /* U2D Port 3 Control Register */ +#define U2DP3CR_P2SS (0x3 << 8) /* Host Port 2 Serial Mode Select */ +#define U2DP3CR_P3SS (0x7 << 4) /* Host Port 3 Serial Mode Select */ +#define U2DP3CR_VPVMBEN (0x1 << 2) /* Host Port 3 Vp/Vm Block Enable */ +#define U2DP3CR_CFG (0x3 << 0) /* Host Port 3 Configuration */ + +#define U2DCSR0 (0x0100) /* U2D Control/Status Register - Endpoint 0 */ +#define U2DCSR0_IPA (1 << 8) /* IN Packet Adjusted */ +#define U2DCSR0_SA (1 << 7) /* SETUP Active */ +#define U2DCSR0_RNE (1 << 6) /* Receive FIFO Not Empty */ +#define U2DCSR0_FST (1 << 5) /* Force Stall */ +#define U2DCSR0_SST (1 << 4) /* Send Stall */ +#define U2DCSR0_DME (1 << 3) /* DMA Enable */ +#define U2DCSR0_FTF (1 << 2) /* Flush Transmit FIFO */ +#define U2DCSR0_IPR (1 << 1) /* IN Packet Ready */ +#define U2DCSR0_OPC (1 << 0) /* OUT Packet Complete */ + +#define U2DCSR(x) (0x0100 + ((x) << 2)) /* U2D Control/Status Register - Endpoint x */ +#define U2DCSR_BF (1 << 10) /* Buffer Full, for OUT eps */ +#define U2DCSR_BE (1 << 10) /* Buffer Empty, for IN eps */ +#define U2DCSR_DPE (1 << 9) /* Data Packet Error, for ISO eps only */ +#define U2DCSR_FEF (1 << 8) /* Flush Endpoint FIFO */ +#define U2DCSR_SP (1 << 7) /* Short Packet Control/Status, for OUT eps only, readonly */ +#define U2DCSR_BNE (1 << 6) /* Buffer Not Empty, for OUT eps */ +#define U2DCSR_BNF (1 << 6) /* Buffer Not Full, for IN eps */ +#define U2DCSR_FST (1 << 5) /* Force STALL, write 1 set */ +#define U2DCSR_SST (1 << 4) /* Sent STALL, write 1 clear */ +#define U2DCSR_DME (1 << 3) /* DMA Enable */ +#define U2DCSR_TRN (1 << 2) /* Tx/Rx NAK, write 1 clear */ +#define U2DCSR_PC (1 << 1) /* Packet Complete, write 1 clear */ +#define U2DCSR_FS (1 << 0) /* FIFO needs Service */ + +#define U2DBCR0 (0x0200) /* U2D Byte Count Register - Endpoint 0 */ +#define U2DBCR(x) (0x0200 + ((x) << 2)) /* U2D Byte Count Register - Endpoint x */ + +#define U2DDR0 (0x0300) /* U2D Data Register - Endpoint 0 */ + +#define U2DEPCR(x) (0x0400 + ((x) << 2)) /* U2D Configuration Register - Endpoint x */ +#define U2DEPCR_EE (1 << 0) /* Endpoint Enable */ +#define U2DEPCR_BS_MASK (0x3FE) /* Buffer Size, BS*8=FIFO size, max 8184B = 8KB */ + +#define U2DSCA (0x0500) /* U2D Setup Command Address */ +#define U2DSCA_VALUE (0x0120) + +#define U2DEN0 (0x0504) /* U2D Endpoint Information Register - Endpoint 0 */ +#define U2DEN(x) (0x0504 + ((x) << 2)) /* U2D Endpoint Information Register - Endpoint x */ + +/* U2DMA registers */ +#define U2DMACSR0 (0x1000) /* U2DMA Control/Status Register - Channel 0 */ +#define U2DMACSR(x) (0x1000 + ((x) << 2)) /* U2DMA Control/Status Register - Channel x */ +#define U2DMACSR_RUN (1 << 31) /* Run Bit (read / write) */ +#define U2DMACSR_STOPIRQEN (1 << 29) /* Stop Interrupt Enable (read / write) */ +#define U2DMACSR_EORIRQEN (1 << 28) /* End of Receive Interrupt Enable (R/W) */ +#define U2DMACSR_EORJMPEN (1 << 27) /* Jump to next descriptor on EOR */ +#define U2DMACSR_EORSTOPEN (1 << 26) /* STOP on an EOR */ +#define U2DMACSR_RASIRQEN (1 << 23) /* Request After Cnannel Stopped Interrupt Enable */ +#define U2DMACSR_MASKRUN (1 << 22) /* Mask Run */ +#define U2DMACSR_SCEMC (3 << 18) /* System Bus Split Completion Error Message Class */ +#define U2DMACSR_SCEMI (0x1f << 13) /* System Bus Split Completion Error Message Index */ +#define U2DMACSR_BUSERRTYPE (7 << 10) /* PX Bus Error Type */ +#define U2DMACSR_EORINTR (1 << 9) /* End Of Receive */ +#define U2DMACSR_REQPEND (1 << 8) /* Request Pending */ +#define U2DMACSR_RASINTR (1 << 4) /* Request After Channel Stopped (read / write 1 clear) */ +#define U2DMACSR_STOPINTR (1 << 3) /* Stop Interrupt (read only) */ +#define U2DMACSR_ENDINTR (1 << 2) /* End Interrupt (read / write 1 clear) */ +#define U2DMACSR_STARTINTR (1 << 1) /* Start Interrupt (read / write 1 clear) */ +#define U2DMACSR_BUSERRINTR (1 << 0) /* Bus Error Interrupt (read / write 1 clear) */ + +#define U2DMACR (0x1080) /* U2DMA Control Register */ +#define U2DMAINT (0x10F0) /* U2DMA Interrupt Register */ + +#define U2DMABR0 (0x1100) /* U2DMA Branch Register - Channel 0 */ +#define U2DMABR(x) (0x1100 + (x) << 2) /* U2DMA Branch Register - Channel x */ + +#define U2DMADADR0 (0x1200) /* U2DMA Descriptor Address Register - Channel 0 */ +#define U2DMADADR(x) (0x1200 + (x) * 0x10) /* U2DMA Descriptor Address Register - Channel x */ + +#define U2DMADADR_STOP (1U << 0) + +#define U2DMASADR0 (0x1204) /* U2DMA Source Address Register - Channel 0 */ +#define U2DMASADR(x) (0x1204 + (x) * 0x10) /* U2DMA Source Address Register - Channel x */ +#define U2DMATADR0 (0x1208) /* U2DMA Target Address Register - Channel 0 */ +#define U2DMATADR(x) (0x1208 + (x) * 0x10) /* U2DMA Target Address Register - Channel x */ + +#define U2DMACMDR0 (0x120C) /* U2DMA Command Address Register - Channel 0 */ +#define U2DMACMDR(x) (0x120C + (x) * 0x10) /* U2DMA Command Address Register - Channel x */ + +#define U2DMACMDR_XFRDIS (1 << 31) /* Transfer Direction */ +#define U2DMACMDR_STARTIRQEN (1 << 22) /* Start Interrupt Enable */ +#define U2DMACMDR_ENDIRQEN (1 << 21) /* End Interrupt Enable */ +#define U2DMACMDR_PACKCOMP (1 << 13) /* Packet Complete */ +#define U2DMACMDR_LEN (0x07ff) /* length mask (max = 2K - 1) */ + +#endif /* __ASM_ARCH_PXA3xx_U2D_H */ diff --git a/arch/arm/mach-pxa/saar.c b/arch/arm/mach-pxa/saar.c index 710c493eac89..1414b5f29114 100644 --- a/arch/arm/mach-pxa/saar.c +++ b/arch/arm/mach-pxa/saar.c @@ -31,7 +31,7 @@ #include #include -#include +#include "pxa930.h" #include #include "devices.h" diff --git a/arch/arm/mach-pxa/sharpsl_pm.c b/arch/arm/mach-pxa/sharpsl_pm.c index bdc0c41bc4fd..b80eab9993c5 100644 --- a/arch/arm/mach-pxa/sharpsl_pm.c +++ b/arch/arm/mach-pxa/sharpsl_pm.c @@ -27,10 +27,10 @@ #include #include -#include +#include "pm.h" #include -#include -#include +#include "regs-rtc.h" +#include "sharpsl_pm.h" /* * Constants diff --git a/arch/arm/mach-pxa/sharpsl_pm.h b/arch/arm/mach-pxa/sharpsl_pm.h new file mode 100644 index 000000000000..905be6755f04 --- /dev/null +++ b/arch/arm/mach-pxa/sharpsl_pm.h @@ -0,0 +1,113 @@ +/* + * SharpSL Battery/PM Driver + * + * Copyright (c) 2004-2005 Richard Purdie + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ +#ifndef _MACH_SHARPSL_PM +#define _MACH_SHARPSL_PM + +struct sharpsl_charger_machinfo { + void (*init)(void); + void (*exit)(void); + int gpio_acin; + int gpio_batfull; + int batfull_irq; + int gpio_batlock; + int gpio_fatal; + void (*discharge)(int); + void (*discharge1)(int); + void (*charge)(int); + void (*measure_temp)(int); + void (*presuspend)(void); + void (*postsuspend)(void); + void (*earlyresume)(void); + unsigned long (*read_devdata)(int); +#define SHARPSL_BATT_VOLT 1 +#define SHARPSL_BATT_TEMP 2 +#define SHARPSL_ACIN_VOLT 3 +#define SHARPSL_STATUS_ACIN 4 +#define SHARPSL_STATUS_LOCK 5 +#define SHARPSL_STATUS_CHRGFULL 6 +#define SHARPSL_STATUS_FATAL 7 + unsigned long (*charger_wakeup)(void); + int (*should_wakeup)(unsigned int resume_on_alarm); + void (*backlight_limit)(int); + int (*backlight_get_status) (void); + int charge_on_volt; + int charge_on_temp; + int charge_acin_high; + int charge_acin_low; + int fatal_acin_volt; + int fatal_noacin_volt; + int bat_levels; + struct battery_thresh *bat_levels_noac; + struct battery_thresh *bat_levels_acin; + struct battery_thresh *bat_levels_noac_bl; + struct battery_thresh *bat_levels_acin_bl; + int status_high_acin; + int status_low_acin; + int status_high_noac; + int status_low_noac; +}; + +struct battery_thresh { + int voltage; + int percentage; +}; + +struct battery_stat { + int ac_status; /* APM AC Present/Not Present */ + int mainbat_status; /* APM Main Battery Status */ + int mainbat_percent; /* Main Battery Percentage Charge */ + int mainbat_voltage; /* Main Battery Voltage */ +}; + +struct sharpsl_pm_status { + struct device *dev; + struct timer_list ac_timer; + struct timer_list chrg_full_timer; + + int charge_mode; +#define CHRG_ERROR (-1) +#define CHRG_OFF (0) +#define CHRG_ON (1) +#define CHRG_DONE (2) + + unsigned int flags; +#define SHARPSL_SUSPENDED (1 << 0) /* Device is Suspended */ +#define SHARPSL_ALARM_ACTIVE (1 << 1) /* Alarm is for charging event (not user) */ +#define SHARPSL_BL_LIMIT (1 << 2) /* Backlight Intensity Limited */ +#define SHARPSL_APM_QUEUED (1 << 3) /* APM Event Queued */ +#define SHARPSL_DO_OFFLINE_CHRG (1 << 4) /* Trigger the offline charger */ + + int full_count; + unsigned long charge_start_time; + struct sharpsl_charger_machinfo *machinfo; + struct battery_stat battstat; +}; + +extern struct sharpsl_pm_status sharpsl_pm; + +extern struct battery_thresh sharpsl_battery_levels_acin[]; +extern struct battery_thresh sharpsl_battery_levels_noac[]; + +#define SHARPSL_LED_ERROR 2 +#define SHARPSL_LED_ON 1 +#define SHARPSL_LED_OFF 0 + +void sharpsl_battery_kick(void); +void sharpsl_pm_led(int val); + +/* MAX1111 Channel Definitions */ +#define MAX1111_BATT_VOLT 4u +#define MAX1111_BATT_TEMP 2u +#define MAX1111_ACIN_VOLT 6u +int sharpsl_pm_pxa_read_max1111(int channel); + +void corgi_lcd_limit_intensity(int limit); +#endif diff --git a/arch/arm/mach-pxa/spitz.c b/arch/arm/mach-pxa/spitz.c index f4e2e2719580..825f903ab77e 100644 --- a/arch/arm/mach-pxa/spitz.c +++ b/arch/arm/mach-pxa/spitz.c @@ -40,15 +40,15 @@ #include #include -#include -#include +#include "pxa27x.h" +#include "pxa27x-udc.h" #include #include #include #include #include #include -#include +#include "sharpsl_pm.h" #include #include "generic.h" diff --git a/arch/arm/mach-pxa/spitz_pm.c b/arch/arm/mach-pxa/spitz_pm.c index e191f9996b26..ea9f9034cb54 100644 --- a/arch/arm/mach-pxa/spitz_pm.c +++ b/arch/arm/mach-pxa/spitz_pm.c @@ -25,8 +25,8 @@ #include #include -#include -#include +#include "pxa27x.h" +#include "sharpsl_pm.h" #include "generic.h" diff --git a/arch/arm/mach-pxa/stargate2.c b/arch/arm/mach-pxa/stargate2.c index 01de542432a6..702f4f14b708 100644 --- a/arch/arm/mach-pxa/stargate2.c +++ b/arch/arm/mach-pxa/stargate2.c @@ -43,10 +43,10 @@ #include #include -#include +#include "pxa27x.h" #include -#include -#include +#include "udc.h" +#include "pxa27x-udc.h" #include #include diff --git a/arch/arm/mach-pxa/tavorevb.c b/arch/arm/mach-pxa/tavorevb.c index 349a13a76215..4b38e821ac9c 100644 --- a/arch/arm/mach-pxa/tavorevb.c +++ b/arch/arm/mach-pxa/tavorevb.c @@ -24,7 +24,7 @@ #include #include -#include +#include "pxa930.h" #include #include diff --git a/arch/arm/mach-pxa/tosa-bt.c b/arch/arm/mach-pxa/tosa-bt.c index e0a53208880a..107f37210fb9 100644 --- a/arch/arm/mach-pxa/tosa-bt.c +++ b/arch/arm/mach-pxa/tosa-bt.c @@ -16,7 +16,7 @@ #include #include -#include +#include "tosa_bt.h" static void tosa_bt_on(struct tosa_bt_data *data) { diff --git a/arch/arm/mach-pxa/tosa.c b/arch/arm/mach-pxa/tosa.c index e6e27c0468e4..13de6602966f 100644 --- a/arch/arm/mach-pxa/tosa.c +++ b/arch/arm/mach-pxa/tosa.c @@ -43,12 +43,12 @@ #include #include -#include +#include "pxa25x.h" #include #include #include -#include -#include +#include "udc.h" +#include "tosa_bt.h" #include #include diff --git a/arch/arm/mach-pxa/tosa_bt.h b/arch/arm/mach-pxa/tosa_bt.h new file mode 100644 index 000000000000..efc3c3d3b75d --- /dev/null +++ b/arch/arm/mach-pxa/tosa_bt.h @@ -0,0 +1,22 @@ +/* + * Tosa bluetooth built-in chip control. + * + * Later it may be shared with some other platforms. + * + * Copyright (c) 2008 Dmitry Baryshkov + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ +#ifndef TOSA_BT_H +#define TOSA_BT_H + +struct tosa_bt_data { + int gpio_pwr; + int gpio_reset; +}; + +#endif + diff --git a/arch/arm/mach-pxa/trizeps4.c b/arch/arm/mach-pxa/trizeps4.c index 066e3a250ee0..ea78bc5c4198 100644 --- a/arch/arm/mach-pxa/trizeps4.c +++ b/arch/arm/mach-pxa/trizeps4.c @@ -41,7 +41,7 @@ #include #include -#include +#include "pxa27x.h" #include #include #include diff --git a/arch/arm/mach-pxa/udc.h b/arch/arm/mach-pxa/udc.h new file mode 100644 index 000000000000..9a827e32db98 --- /dev/null +++ b/arch/arm/mach-pxa/udc.h @@ -0,0 +1,8 @@ +/* + * arch/arm/mach-pxa/include/mach/udc.h + * + */ +#include + +extern void pxa_set_udc_info(struct pxa2xx_udc_mach_info *info); + diff --git a/arch/arm/mach-pxa/viper.c b/arch/arm/mach-pxa/viper.c index 7ecc61ad2bed..8e89d91b206b 100644 --- a/arch/arm/mach-pxa/viper.c +++ b/arch/arm/mach-pxa/viper.c @@ -47,12 +47,12 @@ #include #include -#include +#include "pxa25x.h" #include #include #include #include -#include +#include "viper.h" #include #include diff --git a/arch/arm/mach-pxa/viper.h b/arch/arm/mach-pxa/viper.h new file mode 100644 index 000000000000..5f5fbf1f6489 --- /dev/null +++ b/arch/arm/mach-pxa/viper.h @@ -0,0 +1,94 @@ +/* + * arch/arm/mach-pxa/include/mach/viper.h + * + * Author: Ian Campbell + * Created: Feb 03, 2003 + * Copyright: Arcom Control Systems. + * + * Maintained by Marc Zyngier + * + * + * Created based on lubbock.h: + * Author: Nicolas Pitre + * Created: Jun 15, 2001 + * Copyright: MontaVista Software Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef ARCH_VIPER_H +#define ARCH_VIPER_H + +#define VIPER_BOOT_PHYS PXA_CS0_PHYS +#define VIPER_FLASH_PHYS PXA_CS1_PHYS +#define VIPER_ETH_PHYS PXA_CS2_PHYS +#define VIPER_USB_PHYS PXA_CS3_PHYS +#define VIPER_ETH_DATA_PHYS PXA_CS4_PHYS +#define VIPER_CPLD_PHYS PXA_CS5_PHYS + +#define VIPER_CPLD_BASE (0xf0000000) +#define VIPER_PC104IO_BASE (0xf1000000) +#define VIPER_USB_BASE (0xf1800000) + +#define VIPER_ETH_GPIO (0) +#define VIPER_CPLD_GPIO (1) +#define VIPER_USB_GPIO (2) +#define VIPER_UARTA_GPIO (4) +#define VIPER_UARTB_GPIO (3) +#define VIPER_CF_CD_GPIO (32) +#define VIPER_CF_RDY_GPIO (8) +#define VIPER_BCKLIGHT_EN_GPIO (9) +#define VIPER_LCD_EN_GPIO (10) +#define VIPER_PSU_DATA_GPIO (6) +#define VIPER_PSU_CLK_GPIO (11) +#define VIPER_UART_SHDN_GPIO (12) +#define VIPER_BRIGHTNESS_GPIO (16) +#define VIPER_PSU_nCS_LD_GPIO (19) +#define VIPER_UPS_GPIO (20) +#define VIPER_CF_POWER_GPIO (82) +#define VIPER_TPM_I2C_SDA_GPIO (26) +#define VIPER_TPM_I2C_SCL_GPIO (27) +#define VIPER_RTC_I2C_SDA_GPIO (83) +#define VIPER_RTC_I2C_SCL_GPIO (84) + +#define VIPER_CPLD_P2V(x) ((x) - VIPER_CPLD_PHYS + VIPER_CPLD_BASE) +#define VIPER_CPLD_V2P(x) ((x) - VIPER_CPLD_BASE + VIPER_CPLD_PHYS) + +#ifndef __ASSEMBLY__ +# define __VIPER_CPLD_REG(x) (*((volatile u16 *)VIPER_CPLD_P2V(x))) +#endif + +/* board level registers in the CPLD: (offsets from CPLD_BASE) ... */ + +/* ... Physical addresses */ +#define _VIPER_LO_IRQ_STATUS (VIPER_CPLD_PHYS + 0x100000) +#define _VIPER_ICR_PHYS (VIPER_CPLD_PHYS + 0x100002) +#define _VIPER_HI_IRQ_STATUS (VIPER_CPLD_PHYS + 0x100004) +#define _VIPER_VERSION_PHYS (VIPER_CPLD_PHYS + 0x100006) +#define VIPER_UARTA_PHYS (VIPER_CPLD_PHYS + 0x300010) +#define VIPER_UARTB_PHYS (VIPER_CPLD_PHYS + 0x300000) +#define _VIPER_SRAM_BASE (VIPER_CPLD_PHYS + 0x800000) + +/* ... Virtual addresses */ +#define VIPER_LO_IRQ_STATUS __VIPER_CPLD_REG(_VIPER_LO_IRQ_STATUS) +#define VIPER_HI_IRQ_STATUS __VIPER_CPLD_REG(_VIPER_HI_IRQ_STATUS) +#define VIPER_VERSION __VIPER_CPLD_REG(_VIPER_VERSION_PHYS) +#define VIPER_ICR __VIPER_CPLD_REG(_VIPER_ICR_PHYS) + +/* Decode VIPER_VERSION register */ +#define VIPER_CPLD_REVISION(x) (((x) >> 5) & 0x7) +#define VIPER_BOARD_VERSION(x) (((x) >> 3) & 0x3) +#define VIPER_BOARD_ISSUE(x) (((x) >> 0) & 0x7) + +/* Interrupt and Configuration Register (VIPER_ICR) */ +/* This is a write only register. Only CF_RST is used under Linux */ + +#define VIPER_ICR_RETRIG (1 << 0) +#define VIPER_ICR_AUTO_CLR (1 << 1) +#define VIPER_ICR_R_DIS (1 << 2) +#define VIPER_ICR_CF_RST (1 << 3) + +#endif + diff --git a/arch/arm/mach-pxa/vpac270.c b/arch/arm/mach-pxa/vpac270.c index 54122a983ae3..c006ee902a8f 100644 --- a/arch/arm/mach-pxa/vpac270.c +++ b/arch/arm/mach-pxa/vpac270.c @@ -31,14 +31,14 @@ #include #include -#include +#include "pxa27x.h" #include #include #include #include #include -#include -#include +#include "pxa27x-udc.h" +#include "udc.h" #include #include "generic.h" diff --git a/arch/arm/mach-pxa/xcep.c b/arch/arm/mach-pxa/xcep.c index 13b1d4586d7d..3f06cd90567a 100644 --- a/arch/arm/mach-pxa/xcep.c +++ b/arch/arm/mach-pxa/xcep.c @@ -28,7 +28,7 @@ #include #include -#include +#include "pxa25x.h" #include #include "generic.h" diff --git a/arch/arm/mach-pxa/z2.c b/arch/arm/mach-pxa/z2.c index d9899d73e46b..510e533871f3 100644 --- a/arch/arm/mach-pxa/z2.c +++ b/arch/arm/mach-pxa/z2.c @@ -35,13 +35,13 @@ #include #include -#include -#include +#include "pxa27x.h" +#include "mfp-pxa27x.h" #include #include #include #include -#include +#include "pm.h" #include "generic.h" #include "devices.h" diff --git a/arch/arm/mach-pxa/zeus.c b/arch/arm/mach-pxa/zeus.c index 30e62a3f0701..515b7ddda8aa 100644 --- a/arch/arm/mach-pxa/zeus.c +++ b/arch/arm/mach-pxa/zeus.c @@ -38,17 +38,17 @@ #include #include -#include +#include "pxa27x.h" #include #include #include -#include -#include +#include "pxa27x-udc.h" +#include "udc.h" #include -#include +#include "pm.h" #include #include -#include +#include "zeus.h" #include #include "generic.h" diff --git a/arch/arm/mach-pxa/zeus.h b/arch/arm/mach-pxa/zeus.h new file mode 100644 index 000000000000..56024f81d57e --- /dev/null +++ b/arch/arm/mach-pxa/zeus.h @@ -0,0 +1,85 @@ +/* + * arch/arm/mach-pxa/include/mach/zeus.h + * + * Author: David Vrabel + * Created: Sept 28, 2005 + * Copyright: Arcom Control Systems Ltd. + * + * Maintained by: Marc Zyngier + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef _MACH_ZEUS_H +#define _MACH_ZEUS_H + +#define ZEUS_NR_IRQS (IRQ_BOARD_START + 48) + +/* Physical addresses */ +#define ZEUS_FLASH_PHYS PXA_CS0_PHYS +#define ZEUS_ETH0_PHYS PXA_CS1_PHYS +#define ZEUS_ETH1_PHYS PXA_CS2_PHYS +#define ZEUS_CPLD_PHYS (PXA_CS4_PHYS+0x2000000) +#define ZEUS_SRAM_PHYS PXA_CS5_PHYS +#define ZEUS_PC104IO_PHYS (0x30000000) + +#define ZEUS_CPLD_VERSION_PHYS (ZEUS_CPLD_PHYS + 0x00000000) +#define ZEUS_CPLD_ISA_IRQ_PHYS (ZEUS_CPLD_PHYS + 0x00800000) +#define ZEUS_CPLD_CONTROL_PHYS (ZEUS_CPLD_PHYS + 0x01000000) +#define ZEUS_CPLD_EXTWDOG_PHYS (ZEUS_CPLD_PHYS + 0x01800000) + +/* GPIOs */ +#define ZEUS_AC97_GPIO 0 +#define ZEUS_WAKEUP_GPIO 1 +#define ZEUS_UARTA_GPIO 9 +#define ZEUS_UARTB_GPIO 10 +#define ZEUS_UARTC_GPIO 12 +#define ZEUS_UARTD_GPIO 11 +#define ZEUS_ETH0_GPIO 14 +#define ZEUS_ISA_GPIO 17 +#define ZEUS_BKLEN_GPIO 19 +#define ZEUS_USB2_PWREN_GPIO 22 +#define ZEUS_PTT_GPIO 27 +#define ZEUS_CF_CD_GPIO 35 +#define ZEUS_MMC_WP_GPIO 52 +#define ZEUS_MMC_CD_GPIO 53 +#define ZEUS_EXTGPIO_GPIO 91 +#define ZEUS_CF_PWEN_GPIO 97 +#define ZEUS_CF_RDY_GPIO 99 +#define ZEUS_LCD_EN_GPIO 101 +#define ZEUS_ETH1_GPIO 113 +#define ZEUS_CAN_GPIO 116 + +#define ZEUS_EXT0_GPIO_BASE 128 +#define ZEUS_EXT1_GPIO_BASE 160 +#define ZEUS_USER_GPIO_BASE 192 + +#define ZEUS_EXT0_GPIO(x) (ZEUS_EXT0_GPIO_BASE + (x)) +#define ZEUS_EXT1_GPIO(x) (ZEUS_EXT1_GPIO_BASE + (x)) +#define ZEUS_USER_GPIO(x) (ZEUS_USER_GPIO_BASE + (x)) + +#define ZEUS_CAN_SHDN_GPIO ZEUS_EXT1_GPIO(2) + +/* + * CPLD registers: + * Only 4 registers, but spread over a 32MB address space. + * Be gentle, and remap that over 32kB... + */ + +#define ZEUS_CPLD IOMEM(0xf0000000) +#define ZEUS_CPLD_VERSION (ZEUS_CPLD + 0x0000) +#define ZEUS_CPLD_ISA_IRQ (ZEUS_CPLD + 0x1000) +#define ZEUS_CPLD_CONTROL (ZEUS_CPLD + 0x2000) + +/* CPLD register bits */ +#define ZEUS_CPLD_CONTROL_CF_RST 0x01 + +#define ZEUS_PC104IO IOMEM(0xf1000000) + +#define ZEUS_SRAM_SIZE (256 * 1024) + +#endif + + diff --git a/arch/arm/mach-pxa/zylonite.c b/arch/arm/mach-pxa/zylonite.c index e20359a7433c..3642389b301a 100644 --- a/arch/arm/mach-pxa/zylonite.c +++ b/arch/arm/mach-pxa/zylonite.c @@ -25,10 +25,10 @@ #include #include -#include +#include "pxa3xx.h" #include #include -#include +#include "zylonite.h" #include #include #include diff --git a/arch/arm/mach-pxa/zylonite.h b/arch/arm/mach-pxa/zylonite.h new file mode 100644 index 000000000000..ecca976f03d2 --- /dev/null +++ b/arch/arm/mach-pxa/zylonite.h @@ -0,0 +1,42 @@ +#ifndef __ASM_ARCH_ZYLONITE_H +#define __ASM_ARCH_ZYLONITE_H + +#define ZYLONITE_ETH_PHYS 0x14000000 + +#define EXT_GPIO(x) (128 + (x)) + +#define ZYLONITE_NR_IRQS (IRQ_BOARD_START + 32) + +/* the following variables are processor specific and initialized + * by the corresponding zylonite_pxa3xx_init() + */ +extern int gpio_eth_irq; +extern int gpio_debug_led1; +extern int gpio_debug_led2; + +extern int wm9713_irq; + +extern int lcd_id; +extern int lcd_orientation; + +#ifdef CONFIG_MACH_ZYLONITE300 +extern void zylonite_pxa300_init(void); +#else +static inline void zylonite_pxa300_init(void) +{ + if (cpu_is_pxa300() || cpu_is_pxa310()) + panic("%s: PXA300/PXA310 not supported\n", __func__); +} +#endif + +#ifdef CONFIG_MACH_ZYLONITE320 +extern void zylonite_pxa320_init(void); +#else +static inline void zylonite_pxa320_init(void) +{ + if (cpu_is_pxa320()) + panic("%s: PXA320 not supported\n", __func__); +} +#endif + +#endif /* __ASM_ARCH_ZYLONITE_H */ diff --git a/arch/arm/mach-pxa/zylonite_pxa300.c b/arch/arm/mach-pxa/zylonite_pxa300.c index 869bce7c3f24..e247acf1400a 100644 --- a/arch/arm/mach-pxa/zylonite_pxa300.c +++ b/arch/arm/mach-pxa/zylonite_pxa300.c @@ -21,8 +21,8 @@ #include #include -#include -#include +#include "pxa300.h" +#include "zylonite.h" #include "generic.h" diff --git a/arch/arm/mach-pxa/zylonite_pxa320.c b/arch/arm/mach-pxa/zylonite_pxa320.c index 9942bac4cf7d..47961ae0c448 100644 --- a/arch/arm/mach-pxa/zylonite_pxa320.c +++ b/arch/arm/mach-pxa/zylonite_pxa320.c @@ -18,8 +18,8 @@ #include #include -#include -#include +#include "pxa320.h" +#include "zylonite.h" #include "generic.h" diff --git a/drivers/clk/pxa/clk-pxa25x.c b/drivers/clk/pxa/clk-pxa25x.c index 542e45ef5087..b7747229db9a 100644 --- a/drivers/clk/pxa/clk-pxa25x.c +++ b/drivers/clk/pxa/clk-pxa25x.c @@ -17,7 +17,6 @@ #include #include #include -#include #include #include -- cgit v1.2.3-59-g8ed1b From 5420b4b156179ec634d9e42279b6898b85852960 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Fri, 9 Oct 2015 13:38:57 +0200 Subject: ARM: realview: add an DT SMP boot method This adds an SMP boot method for the ARM RealView reference designs. We also select HAVE_SMP by default and make it use SMP_ON_UP so we only need to support one single kernel across the RealView reference designs when using DT. The RealViews need to have the SCU (Snoop Control Unit) activated on boot, and this is now done by looking up its address from the device tree and initializing it and counting the available cores. The RealViews boot by using a magic address register in the system controller (SYS_FLAGS) to store the boot address, the ROM will then read this register to the PC when the CPUs are taken out of WFI. This code uses a handle to the syscon regmap to access this register. Signed-off-by: Linus Walleij --- Documentation/devicetree/bindings/arm/cpus.txt | 1 + arch/arm/mach-realview/Kconfig | 2 + arch/arm/mach-realview/Makefile | 2 +- arch/arm/mach-realview/platsmp-dt.c | 91 ++++++++++++++++++++++++++ 4 files changed, 95 insertions(+), 1 deletion(-) create mode 100644 arch/arm/mach-realview/platsmp-dt.c (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt index 3a07a87fef20..19af9157f094 100644 --- a/Documentation/devicetree/bindings/arm/cpus.txt +++ b/Documentation/devicetree/bindings/arm/cpus.txt @@ -190,6 +190,7 @@ nodes to be present and contain the properties described below. "allwinner,sun6i-a31" "allwinner,sun8i-a23" "arm,psci" + "arm,realview-smp" "brcm,brahma-b15" "marvell,armada-375-smp" "marvell,armada-380-smp" diff --git a/arch/arm/mach-realview/Kconfig b/arch/arm/mach-realview/Kconfig index edbc925e42c2..7316fff0f3ba 100644 --- a/arch/arm/mach-realview/Kconfig +++ b/arch/arm/mach-realview/Kconfig @@ -5,11 +5,13 @@ config REALVIEW_DT bool "Support RealView(R) Device Tree based boot" select ARM_GIC select CLK_SP810 + select HAVE_SMP select ICST select MFD_SYSCON select POWER_RESET select POWER_RESET_VERSATILE select POWER_SUPPLY + select SMP_ON_UP select SOC_REALVIEW select USE_OF help diff --git a/arch/arm/mach-realview/Makefile b/arch/arm/mach-realview/Makefile index e07fdf7ae8a7..a46fa694cf07 100644 --- a/arch/arm/mach-realview/Makefile +++ b/arch/arm/mach-realview/Makefile @@ -3,7 +3,7 @@ # obj-y := core.o -obj-$(CONFIG_REALVIEW_DT) += realview-dt.o +obj-$(CONFIG_REALVIEW_DT) += realview-dt.o platsmp-dt.o obj-$(CONFIG_MACH_REALVIEW_EB) += realview_eb.o obj-$(CONFIG_MACH_REALVIEW_PB11MP) += realview_pb11mp.o obj-$(CONFIG_MACH_REALVIEW_PB1176) += realview_pb1176.o diff --git a/arch/arm/mach-realview/platsmp-dt.c b/arch/arm/mach-realview/platsmp-dt.c new file mode 100644 index 000000000000..65585392655b --- /dev/null +++ b/arch/arm/mach-realview/platsmp-dt.c @@ -0,0 +1,91 @@ +/* + * Copyright (C) 2015 Linus Walleij + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include + +#include "core.h" + +#define REALVIEW_SYS_FLAGSSET_OFFSET 0x30 + +static const struct of_device_id realview_scu_match[] = { + { .compatible = "arm,arm11mp-scu", }, + { .compatible = "arm,cortex-a9-scu", }, + { .compatible = "arm,cortex-a5-scu", }, + { } +}; + +static const struct of_device_id realview_syscon_match[] = { + { .compatible = "arm,core-module-integrator", }, + { .compatible = "arm,realview-eb-syscon", }, + { .compatible = "arm,realview-pb11mp-syscon", }, + { .compatible = "arm,realview-pbx-syscon", }, + { }, +}; + +static void __init realview_smp_prepare_cpus(unsigned int max_cpus) +{ + struct device_node *np; + void __iomem *scu_base; + struct regmap *map; + unsigned int ncores; + int i; + + np = of_find_matching_node(NULL, realview_scu_match); + if (!np) { + pr_err("PLATSMP: No SCU base address\n"); + return; + } + scu_base = of_iomap(np, 0); + of_node_put(np); + if (!scu_base) { + pr_err("PLATSMP: No SCU remap\n"); + return; + } + + scu_enable(scu_base); + ncores = scu_get_core_count(scu_base); + pr_info("SCU: %d cores detected\n", ncores); + for (i = 0; i < ncores; i++) + set_cpu_possible(i, true); + iounmap(scu_base); + + /* The syscon contains the magic SMP start address registers */ + np = of_find_matching_node(NULL, realview_syscon_match); + if (!np) { + pr_err("PLATSMP: No syscon match\n"); + return; + } + map = syscon_node_to_regmap(np); + if (IS_ERR(map)) { + pr_err("PLATSMP: No syscon regmap\n"); + return; + } + /* Put the boot address in this magic register */ + regmap_write(map, REALVIEW_SYS_FLAGSSET_OFFSET, + virt_to_phys(versatile_secondary_startup)); +} + +struct smp_operations realview_dt_smp_ops __initdata = { + .smp_prepare_cpus = realview_smp_prepare_cpus, + .smp_secondary_init = versatile_secondary_init, + .smp_boot_secondary = versatile_boot_secondary, +#ifdef CONFIG_HOTPLUG_CPU + .cpu_die = realview_cpu_die, +#endif +}; +CPU_METHOD_OF_DECLARE(realview_smp, "arm,realview-smp", &realview_dt_smp_ops); -- cgit v1.2.3-59-g8ed1b