From af9422a85721f7afa8d5ad3442b5de5549a23e84 Mon Sep 17 00:00:00 2001 From: Gareth Williams Date: Tue, 28 May 2019 12:54:26 +0100 Subject: dt-bindings: clock: renesas: r9a06g032-sysctrl: Document power Domains The driver is gaining power domain support, so add the new property to the DT binding and update the examples. Signed-off-by: Gareth Williams Signed-off-by: Geert Uytterhoeven --- .../devicetree/bindings/clock/renesas,r9a06g032-sysctrl.txt | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/clock/renesas,r9a06g032-sysctrl.txt b/Documentation/devicetree/bindings/clock/renesas,r9a06g032-sysctrl.txt index d60b99756bb9..aed713cf0831 100644 --- a/Documentation/devicetree/bindings/clock/renesas,r9a06g032-sysctrl.txt +++ b/Documentation/devicetree/bindings/clock/renesas,r9a06g032-sysctrl.txt @@ -13,6 +13,7 @@ Required Properties: - external (optional) RGMII_REFCLK - clock-names: Must be: clock-names = "mclk", "rtc", "jtag", "rgmii_ref_ext"; + - #power-domain-cells: Must be 0 Examples -------- @@ -27,6 +28,7 @@ Examples clocks = <&ext_mclk>, <&ext_rtc_clk>, <&ext_jtag_clk>, <&ext_rgmii_ref>; clock-names = "mclk", "rtc", "jtag", "rgmii_ref_ext"; + #power-domain-cells = <0>; }; - Other nodes can use the clocks provided by SYSCTRL as in: @@ -38,6 +40,7 @@ Examples interrupts = ; reg-shift = <2>; reg-io-width = <4>; - clocks = <&sysctrl R9A06G032_CLK_UART0>; - clock-names = "baudclk"; + clocks = <&sysctrl R9A06G032_CLK_UART0>, <&sysctrl R9A06G032_HCLK_UART0>; + clock-names = "baudclk", "apb_pclk"; + power-domains = <&sysctrl>; }; -- cgit v1.2.3-59-g8ed1b From b467ec063ec56900e1ebba4d5aeb50b0a7cb0ef8 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Mon, 27 May 2019 12:02:19 +0200 Subject: dt-bindings: clk: Convert Allwinner CCU to a schema The Allwinner SoCs have a clocks controller supported in Linux, with a matching Device Tree binding. Now that we have the DT validation in place, let's convert the device tree bindings for that controller over to a YAML schemas. Signed-off-by: Maxime Ripard --- .../bindings/clock/allwinner,sun4i-a10-ccu.yaml | 141 +++++++++++++++++++++ .../devicetree/bindings/clock/sunxi-ccu.txt | 62 --------- 2 files changed, 141 insertions(+), 62 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-ccu.yaml delete mode 100644 Documentation/devicetree/bindings/clock/sunxi-ccu.txt (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-ccu.yaml b/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-ccu.yaml new file mode 100644 index 000000000000..c935405458fe --- /dev/null +++ b/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-ccu.yaml @@ -0,0 +1,141 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/allwinner,sun4i-a10-ccu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner Clock Control Unit Device Tree Bindings + +maintainers: + - Chen-Yu Tsai + - Maxime Ripard + +properties: + "#clock-cells": + const: 1 + + "#reset-cells": + const: 1 + + compatible: + enum: + - allwinner,sun4i-a10-ccu + - allwinner,sun5i-a10s-ccu + - allwinner,sun5i-a13-ccu + - allwinner,sun6i-a31-ccu + - allwinner,sun7i-a20-ccu + - allwinner,sun8i-a23-ccu + - allwinner,sun8i-a33-ccu + - allwinner,sun8i-a83t-ccu + - allwinner,sun8i-a83t-r-ccu + - allwinner,sun8i-h3-ccu + - allwinner,sun8i-h3-r-ccu + - allwinner,sun8i-r40-ccu + - allwinner,sun8i-v3s-ccu + - allwinner,sun9i-a80-ccu + - allwinner,sun50i-a64-ccu + - allwinner,sun50i-a64-r-ccu + - allwinner,sun50i-h5-ccu + - allwinner,sun50i-h6-ccu + - allwinner,sun50i-h6-r-ccu + - allwinner,suniv-f1c100s-ccu + - nextthing,gr8-ccu + + reg: + maxItems: 1 + + clocks: + minItems: 2 + maxItems: 4 + items: + - description: High Frequency Oscillator (usually at 24MHz) + - description: Low Frequency Oscillator (usually at 32kHz) + - description: Internal Oscillator + - description: Peripherals PLL + + clock-names: + minItems: 2 + maxItems: 4 + items: + - const: hosc + - const: losc + - const: iosc + - const: pll-periph + +required: + - "#clock-cells" + - "#reset-cells" + - compatible + - reg + - clocks + - clock-names + +if: + properties: + compatible: + enum: + - allwinner,sun8i-a83t-r-ccu + - allwinner,sun8i-h3-r-ccu + - allwinner,sun50i-a64-r-ccu + - allwinner,sun50i-h6-r-ccu + +then: + properties: + clocks: + minItems: 4 + maxItems: 4 + + clock-names: + minItems: 4 + maxItems: 4 + +else: + if: + properties: + compatible: + const: allwinner,sun50i-h6-ccu + + then: + properties: + clocks: + minItems: 3 + maxItems: 3 + + clock-names: + minItems: 3 + maxItems: 3 + + else: + properties: + clocks: + minItems: 2 + maxItems: 2 + + clock-names: + minItems: 2 + maxItems: 2 + +additionalProperties: false + +examples: + - | + ccu: clock@1c20000 { + compatible = "allwinner,sun8i-h3-ccu"; + reg = <0x01c20000 0x400>; + clocks = <&osc24M>, <&osc32k>; + clock-names = "hosc", "losc"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + - | + r_ccu: clock@1f01400 { + compatible = "allwinner,sun50i-a64-r-ccu"; + reg = <0x01f01400 0x100>; + clocks = <&osc24M>, <&osc32k>, <&iosc>, <&ccu 11>; + clock-names = "hosc", "losc", "iosc", "pll-periph"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + +... diff --git a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt deleted file mode 100644 index e3bd88ae456b..000000000000 --- a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt +++ /dev/null @@ -1,62 +0,0 @@ -Allwinner Clock Control Unit Binding ------------------------------------- - -Required properties : -- compatible: must contain one of the following compatibles: - - "allwinner,sun4i-a10-ccu" - - "allwinner,sun5i-a10s-ccu" - - "allwinner,sun5i-a13-ccu" - - "allwinner,sun6i-a31-ccu" - - "allwinner,sun7i-a20-ccu" - - "allwinner,sun8i-a23-ccu" - - "allwinner,sun8i-a33-ccu" - - "allwinner,sun8i-a83t-ccu" - - "allwinner,sun8i-a83t-r-ccu" - - "allwinner,sun8i-h3-ccu" - - "allwinner,sun8i-h3-r-ccu" -+ - "allwinner,sun8i-r40-ccu" - - "allwinner,sun8i-v3s-ccu" - - "allwinner,sun9i-a80-ccu" - - "allwinner,sun50i-a64-ccu" - - "allwinner,sun50i-a64-r-ccu" - - "allwinner,sun50i-h5-ccu" - - "allwinner,sun50i-h6-ccu" - - "allwinner,sun50i-h6-r-ccu" - - "allwinner,suniv-f1c100s-ccu" - - "nextthing,gr8-ccu" - -- reg: Must contain the registers base address and length -- clocks: phandle to the oscillators feeding the CCU. Two are needed: - - "hosc": the high frequency oscillator (usually at 24MHz) - - "losc": the low frequency oscillator (usually at 32kHz) - On the A83T, this is the internal 16MHz oscillator divided by 512 -- clock-names: Must contain the clock names described just above -- #clock-cells : must contain 1 -- #reset-cells : must contain 1 - -For the main CCU on H6, one more clock is needed: -- "iosc": the SoC's internal frequency oscillator - -For the PRCM CCUs on A83T/H3/A64/H6, two more clocks are needed: -- "pll-periph": the SoC's peripheral PLL from the main CCU -- "iosc": the SoC's internal frequency oscillator - -Example for generic CCU: -ccu: clock@1c20000 { - compatible = "allwinner,sun8i-h3-ccu"; - reg = <0x01c20000 0x400>; - clocks = <&osc24M>, <&osc32k>; - clock-names = "hosc", "losc"; - #clock-cells = <1>; - #reset-cells = <1>; -}; - -Example for PRCM CCU: -r_ccu: clock@1f01400 { - compatible = "allwinner,sun50i-a64-r-ccu"; - reg = <0x01f01400 0x100>; - clocks = <&osc24M>, <&osc32k>, <&iosc>, <&ccu CLK_PLL_PERIPH0>; - clock-names = "hosc", "losc", "iosc", "pll-periph"; - #clock-cells = <1>; - #reset-cells = <1>; -}; -- cgit v1.2.3-59-g8ed1b From 3d8b6e9c774ff57ad2860f79abd9cdb8f29ecaf8 Mon Sep 17 00:00:00 2001 From: Fabien Parent Date: Thu, 2 May 2019 14:18:42 +0200 Subject: dt-bindings: mediatek: audsys: add support for MT8516 Add AUDSYS device tree bindings documentation for MediaTek MT8516 SoC. Signed-off-by: Fabien Parent Reviewed-by: Rob Herring Signed-off-by: Stephen Boyd --- .../bindings/arm/mediatek/mediatek,audsys.txt | 1 + include/dt-bindings/clock/mt8516-clk.h | 17 +++++++++++++++++ 2 files changed, 18 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt index f3cef1a6d95c..07c9d813465c 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt @@ -10,6 +10,7 @@ Required Properties: - "mediatek,mt7622-audsys", "syscon" - "mediatek,mt7623-audsys", "mediatek,mt2701-audsys", "syscon" - "mediatek,mt8183-audiosys", "syscon" + - "mediatek,mt8516-audsys", "syscon" - #clock-cells: Must be 1 The AUDSYS controller uses the common clk binding from diff --git a/include/dt-bindings/clock/mt8516-clk.h b/include/dt-bindings/clock/mt8516-clk.h index 9cfca53cd78d..816447b98edd 100644 --- a/include/dt-bindings/clock/mt8516-clk.h +++ b/include/dt-bindings/clock/mt8516-clk.h @@ -208,4 +208,21 @@ #define CLK_TOP_MSDC2_INFRA 176 #define CLK_TOP_NR_CLK 177 +/* AUDSYS */ + +#define CLK_AUD_AFE 0 +#define CLK_AUD_I2S 1 +#define CLK_AUD_22M 2 +#define CLK_AUD_24M 3 +#define CLK_AUD_INTDIR 4 +#define CLK_AUD_APLL2_TUNER 5 +#define CLK_AUD_APLL_TUNER 6 +#define CLK_AUD_HDMI 7 +#define CLK_AUD_SPDF 8 +#define CLK_AUD_ADC 9 +#define CLK_AUD_DAC 10 +#define CLK_AUD_DAC_PREDIS 11 +#define CLK_AUD_TML 12 +#define CLK_AUD_NR_CLK 13 + #endif /* _DT_BINDINGS_CLK_MT8516_H */ -- cgit v1.2.3-59-g8ed1b From 072a551fd5cff2329ad151c7c25b7958afc0f149 Mon Sep 17 00:00:00 2001 From: Jeffrey Hugo Date: Tue, 28 May 2019 09:47:40 -0700 Subject: dt-bindings: clock: Document gpucc for msm8998 The GPU for msm8998 has its own clock controller. Document it. Signed-off-by: Jeffrey Hugo Signed-off-by: Stephen Boyd --- .../devicetree/bindings/clock/qcom,gpucc.txt | 4 ++- include/dt-bindings/clock/qcom,gpucc-msm8998.h | 29 ++++++++++++++++++++++ 2 files changed, 32 insertions(+), 1 deletion(-) create mode 100644 include/dt-bindings/clock/qcom,gpucc-msm8998.h (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/clock/qcom,gpucc.txt b/Documentation/devicetree/bindings/clock/qcom,gpucc.txt index 4e5215ef1acd..269afe8a757e 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gpucc.txt +++ b/Documentation/devicetree/bindings/clock/qcom,gpucc.txt @@ -2,13 +2,15 @@ Qualcomm Graphics Clock & Reset Controller Binding -------------------------------------------------- Required properties : -- compatible : shall contain "qcom,sdm845-gpucc" +- compatible : shall contain "qcom,sdm845-gpucc" or "qcom,msm8998-gpucc" - reg : shall contain base register location and length - #clock-cells : from common clock binding, shall contain 1 - #reset-cells : from common reset binding, shall contain 1 - #power-domain-cells : from generic power domain binding, shall contain 1 - clocks : shall contain the XO clock + shall contain the gpll0 out main clock (msm8998) - clock-names : shall be "xo" + shall be "gpll0" (msm8998) Example: gpucc: clock-controller@5090000 { diff --git a/include/dt-bindings/clock/qcom,gpucc-msm8998.h b/include/dt-bindings/clock/qcom,gpucc-msm8998.h new file mode 100644 index 000000000000..2623570ee974 --- /dev/null +++ b/include/dt-bindings/clock/qcom,gpucc-msm8998.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2019, Jeffrey Hugo + */ + +#ifndef _DT_BINDINGS_CLK_MSM_GPUCC_8998_H +#define _DT_BINDINGS_CLK_MSM_GPUCC_8998_H + +#define GPUPLL0 0 +#define GPUPLL0_OUT_EVEN 1 +#define RBCPR_CLK_SRC 2 +#define GFX3D_CLK_SRC 3 +#define RBBMTIMER_CLK_SRC 4 +#define GFX3D_ISENSE_CLK_SRC 5 +#define RBCPR_CLK 6 +#define GFX3D_CLK 7 +#define RBBMTIMER_CLK 8 +#define GFX3D_ISENSE_CLK 9 +#define GPUCC_CXO_CLK 10 + +#define GPU_CX_BCR 0 +#define RBCPR_BCR 1 +#define GPU_GX_BCR 2 +#define GPU_ISENSE_BCR 3 + +#define GPU_CX_GDSC 1 +#define GPU_GX_GDSC 2 + +#endif -- cgit v1.2.3-59-g8ed1b From 7391d7f4b0690a98c5bf6a113c33400e2d29d9f8 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Tue, 28 May 2019 10:07:56 +0200 Subject: dt-bindings: clk: meson: add g12b periph clock controller bindings Update the documentation to support clock driver for the Amlogic G12B SoC. G12B clock driver is very close, the main differences are : - the clock tree is duplicated for the both clusters, and the SYS_PLL are swapped between the clusters - G12B has additional clocks like for CSI an other components Reviewed-by: Rob Herring Reviewed-by: Martin Blumenstingl Signed-off-by: Neil Armstrong Signed-off-by: Jerome Brunet --- Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt b/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt index 5c8b105be4d6..6eaa52092313 100644 --- a/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt +++ b/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt @@ -10,6 +10,7 @@ Required Properties: "amlogic,gxl-clkc" for GXL and GXM SoC, "amlogic,axg-clkc" for AXG SoC. "amlogic,g12a-clkc" for G12A SoC. + "amlogic,g12b-clkc" for G12B SoC. - clocks : list of clock phandle, one for each entry clock-names. - clock-names : should contain the following: * "xtal": the platform xtal -- cgit v1.2.3-59-g8ed1b From 179175d389c7aad4c7b7276f772d04cfc92864b1 Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Tue, 25 Jun 2019 14:20:56 -0700 Subject: clk: Document some devm_clk_bulk*() APIs Add some new clk devm APIs that we've added over time to the devres documentation. Signed-off-by: Stephen Boyd --- Documentation/driver-model/devres.txt | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'Documentation') diff --git a/Documentation/driver-model/devres.txt b/Documentation/driver-model/devres.txt index 69c7fa7f616c..38205662d417 100644 --- a/Documentation/driver-model/devres.txt +++ b/Documentation/driver-model/devres.txt @@ -244,6 +244,10 @@ CLOCK devm_clk_get() devm_clk_get_optional() devm_clk_put() + devm_clk_bulk_get() + devm_clk_bulk_get_all() + devm_clk_bulk_get_optional() + devm_get_clk_from_childl() devm_clk_hw_register() devm_of_clk_add_hw_provider() devm_clk_hw_register_clkdev() -- cgit v1.2.3-59-g8ed1b From 9a042e718fc0faf77db35a8106c8ded948971219 Mon Sep 17 00:00:00 2001 From: Chris Packham Date: Tue, 18 Jun 2019 09:54:56 +1200 Subject: dt-bindings: clock: mvebu: Add compatible string for 98dx1135 core clock Add compatible string for the core clock on the 98dx1135 switch with integrated CPU. Signed-off-by: Chris Packham Reviewed-by: Andrew Lunn Signed-off-by: Stephen Boyd --- Documentation/devicetree/bindings/clock/mvebu-core-clock.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/clock/mvebu-core-clock.txt b/Documentation/devicetree/bindings/clock/mvebu-core-clock.txt index 796c260c183d..d8f5c490f893 100644 --- a/Documentation/devicetree/bindings/clock/mvebu-core-clock.txt +++ b/Documentation/devicetree/bindings/clock/mvebu-core-clock.txt @@ -59,6 +59,7 @@ Required properties: "marvell,dove-core-clock" - for Dove SoC core clocks "marvell,kirkwood-core-clock" - for Kirkwood SoC (except mv88f6180) "marvell,mv88f6180-core-clock" - for Kirkwood MV88f6180 SoC + "marvell,mv98dx1135-core-clock" - for Kirkwood 98dx1135 SoC "marvell,mv88f5181-core-clock" - for Orion MV88F5181 SoC "marvell,mv88f5182-core-clock" - for Orion MV88F5182 SoC "marvell,mv88f5281-core-clock" - for Orion MV88F5281 SoC -- cgit v1.2.3-59-g8ed1b From b36d5cf75342e27bd1272971b69a3bbb42eae03b Mon Sep 17 00:00:00 2001 From: Claudiu Beznea Date: Tue, 21 May 2019 10:11:29 +0000 Subject: dt-bindings: clk: at91: add bindings for SAM9X60's slow clock controller Add bindings for SAM9X60's slow clock controller. Signed-off-by: Claudiu Beznea Reviewed-by: Alexandre Belloni Reviewed-by: Rob Herring Signed-off-by: Stephen Boyd --- Documentation/devicetree/bindings/clock/at91-clock.txt | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/clock/at91-clock.txt b/Documentation/devicetree/bindings/clock/at91-clock.txt index b520280e33ff..13f45db3b66d 100644 --- a/Documentation/devicetree/bindings/clock/at91-clock.txt +++ b/Documentation/devicetree/bindings/clock/at91-clock.txt @@ -9,10 +9,11 @@ Slow Clock controller: Required properties: - compatible : shall be one of the following: "atmel,at91sam9x5-sckc", - "atmel,sama5d3-sckc" or - "atmel,sama5d4-sckc": + "atmel,sama5d3-sckc", + "atmel,sama5d4-sckc" or + "microchip,sam9x60-sckc": at91 SCKC (Slow Clock Controller) -- #clock-cells : shall be 0. +- #clock-cells : shall be 1 for "microchip,sam9x60-sckc" otherwise shall be 0. - clocks : shall be the input parent clock phandle for the clock. Optional properties: -- cgit v1.2.3-59-g8ed1b From dc1d9dac5ca2f3c3cf024f1e17857033ba1e080e Mon Sep 17 00:00:00 2001 From: Jonas Gorski Date: Thu, 2 May 2019 14:26:55 +0200 Subject: devicetree: document the BCM63XX gated clock bindings MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add binding documentation for the gated clock controller found on MIPS based BCM63XX SoCs. Signed-off-by: Jonas Gorski Reviewed-by: Florian Fainelli Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Rob Herring Signed-off-by: Stephen Boyd --- .../bindings/clock/brcm,bcm63xx-clocks.txt | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/brcm,bcm63xx-clocks.txt (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/clock/brcm,bcm63xx-clocks.txt b/Documentation/devicetree/bindings/clock/brcm,bcm63xx-clocks.txt new file mode 100644 index 000000000000..3041657e2f96 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/brcm,bcm63xx-clocks.txt @@ -0,0 +1,22 @@ +Gated Clock Controller Bindings for MIPS based BCM63XX SoCs + +Required properties: +- compatible: must be one of: + "brcm,bcm3368-clocks" + "brcm,bcm6328-clocks" + "brcm,bcm6358-clocks" + "brcm,bcm6362-clocks" + "brcm,bcm6368-clocks" + "brcm,bcm63268-clocks" + +- reg: Address and length of the register set +- #clock-cells: must be <1> + + +Example: + +clkctl: clock-controller@10000004 { + compatible = "brcm,bcm6328-clocks"; + reg = <0x10000004 0x4>; + #clock-cells = <1>; +}; -- cgit v1.2.3-59-g8ed1b From d743ea67cb98f9cd727e7ff07a0da647b9544444 Mon Sep 17 00:00:00 2001 From: Mike Looijmans Date: Fri, 17 May 2019 15:20:20 +0200 Subject: dt-bindings: clock: Add silabs,si5341 Adds the devicetree bindings for the Si5341 and Si5340 chips from Silicon Labs. These are multiple-input multiple-output clock synthesizers. Signed-off-by: Mike Looijmans Reviewed-by: Rob Herring Signed-off-by: Stephen Boyd --- .../devicetree/bindings/clock/silabs,si5341.txt | 162 +++++++++++++++++++++ 1 file changed, 162 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/silabs,si5341.txt (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/clock/silabs,si5341.txt b/Documentation/devicetree/bindings/clock/silabs,si5341.txt new file mode 100644 index 000000000000..a70c333e4cd4 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/silabs,si5341.txt @@ -0,0 +1,162 @@ +Binding for Silicon Labs Si5341 and Si5340 programmable i2c clock generator. + +Reference +[1] Si5341 Data Sheet + https://www.silabs.com/documents/public/data-sheets/Si5341-40-D-DataSheet.pdf +[2] Si5341 Reference Manual + https://www.silabs.com/documents/public/reference-manuals/Si5341-40-D-RM.pdf + +The Si5341 and Si5340 are programmable i2c clock generators with up to 10 output +clocks. The chip contains a PLL that sources 5 (or 4) multisynth clocks, which +in turn can be directed to any of the 10 (or 4) outputs through a divider. +The internal structure of the clock generators can be found in [2]. + +The driver can be used in "as is" mode, reading the current settings from the +chip at boot, in case you have a (pre-)programmed device. If the PLL is not +configured when the driver probes, it assumes the driver must fully initialize +it. + +The device type, speed grade and revision are determined runtime by probing. + +The driver currently only supports XTAL input mode, and does not support any +fancy input configurations. They can still be programmed into the chip and +the driver will leave them "as is". + +==I2C device node== + +Required properties: +- compatible: shall be one of the following: + "silabs,si5340" - Si5340 A/B/C/D + "silabs,si5341" - Si5341 A/B/C/D +- reg: i2c device address, usually 0x74 +- #clock-cells: from common clock binding; shall be set to 2. + The first value is "0" for outputs, "1" for synthesizers. + The second value is the output or synthesizer index. +- clocks: from common clock binding; list of parent clock handles, + corresponding to inputs. Use a fixed clock for the "xtal" input. + At least one must be present. +- clock-names: One of: "xtal", "in0", "in1", "in2" +- vdd-supply: Regulator node for VDD + +Optional properties: +- vdda-supply: Regulator node for VDDA +- vdds-supply: Regulator node for VDDS +- silabs,pll-m-num, silabs,pll-m-den: Numerator and denominator for PLL + feedback divider. Must be such that the PLL output is in the valid range. For + example, to create 14GHz from a 48MHz xtal, use m-num=14000 and m-den=48. Only + the fraction matters, using 3500 and 12 will deliver the exact same result. + If these are not specified, and the PLL is not yet programmed when the driver + probes, the PLL will be set to 14GHz. +- silabs,reprogram: When present, the driver will always assume the device must + be initialized, and always performs the soft-reset routine. Since this will + temporarily stop all output clocks, don't do this if the chip is generating + the CPU clock for example. +- interrupts: Interrupt for INTRb pin. +- #address-cells: shall be set to 1. +- #size-cells: shall be set to 0. + + +== Child nodes: Outputs == + +The child nodes list the output clocks. + +Each of the clock outputs can be overwritten individually by using a child node. +If a child node for a clock output is not set, the configuration remains +unchanged. + +Required child node properties: +- reg: number of clock output. + +Optional child node properties: +- vdd-supply: Regulator node for VDD for this output. The driver selects default + values for common-mode and amplitude based on the voltage. +- silabs,format: Output format, one of: + 1 = differential (defaults to LVDS levels) + 2 = low-power (defaults to HCSL levels) + 4 = LVCMOS +- silabs,common-mode: Manually override output common mode, see [2] for values +- silabs,amplitude: Manually override output amplitude, see [2] for values +- silabs,synth-master: boolean. If present, this output is allowed to change the + multisynth frequency dynamically. +- silabs,silabs,disable-high: boolean. If set, the clock output is driven HIGH + when disabled, otherwise it's driven LOW. + +==Example== + +/* 48MHz reference crystal */ +ref48: ref48M { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <48000000>; +}; + +i2c-master-node { + /* Programmable clock (for logic) */ + si5341: clock-generator@74 { + reg = <0x74>; + compatible = "silabs,si5341"; + #clock-cells = <2>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&ref48>; + clock-names = "xtal"; + + silabs,pll-m-num = <14000>; /* PLL at 14.0 GHz */ + silabs,pll-m-den = <48>; + silabs,reprogram; /* Chips are not programmed, always reset */ + + out@0 { + reg = <0>; + silabs,format = <1>; /* LVDS 3v3 */ + silabs,common-mode = <3>; + silabs,amplitude = <3>; + silabs,synth-master; + }; + + /* + * Output 6 configuration: + * LVDS 1v8 + */ + out@6 { + reg = <6>; + silabs,format = <1>; /* LVDS 1v8 */ + silabs,common-mode = <13>; + silabs,amplitude = <3>; + }; + + /* + * Output 8 configuration: + * HCSL 3v3 + */ + out@8 { + reg = <8>; + silabs,format = <2>; + silabs,common-mode = <11>; + silabs,amplitude = <3>; + }; + }; +}; + +some-video-node { + /* Standard clock bindings */ + clock-names = "pixel"; + clocks = <&si5341 0 7>; /* Output 7 */ + + /* Set output 7 to use syntesizer 3 as its parent */ + assigned-clocks = <&si5341 0 7>, <&si5341 1 3>; + assigned-clock-parents = <&si5341 1 3>; + /* Set output 7 to 148.5 MHz using a synth frequency of 594 MHz */ + assigned-clock-rates = <148500000>, <594000000>; +}; + +some-audio-node { + clock-names = "i2s-clk"; + clocks = <&si5341 0 0>; + /* + * since output 0 is a synth-master, the synth will be automatically set + * to an appropriate frequency when the audio driver requests another + * frequency. We give control over synth 2 to this output here. + */ + assigned-clocks = <&si5341 0 0>; + assigned-clock-parents = <&si5341 1 2>; +}; -- cgit v1.2.3-59-g8ed1b From f9d3fb22ab27aaee8748480fe3fa8cc17875ee30 Mon Sep 17 00:00:00 2001 From: Charles Keepax Date: Thu, 27 Jun 2019 09:55:17 +0100 Subject: clk: lochnagar: Update DT binding doc to include the primary SPDIF MCLK This clock was missed when the binding was initially merged but is supported by the driver, so add it to the binding document. Signed-off-by: Charles Keepax Signed-off-by: Stephen Boyd --- Documentation/devicetree/bindings/clock/cirrus,lochnagar.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/clock/cirrus,lochnagar.txt b/Documentation/devicetree/bindings/clock/cirrus,lochnagar.txt index b8d8ef3bdc5f..52a064c789ee 100644 --- a/Documentation/devicetree/bindings/clock/cirrus,lochnagar.txt +++ b/Documentation/devicetree/bindings/clock/cirrus,lochnagar.txt @@ -40,6 +40,7 @@ Optional properties: input audio clocks from host system. - ln-psia1-mclk, ln-psia2-mclk : Optional input audio clocks from external connector. + - ln-spdif-mclk : Optional input audio clock from SPDIF. - ln-spdif-clkout : Optional input audio clock from SPDIF. - ln-adat-mclk : Optional input audio clock from ADAT. - ln-pmic-32k : On board fixed clock. -- cgit v1.2.3-59-g8ed1b