From ab407df736c1d8263fc92a35589fb54854f627b3 Mon Sep 17 00:00:00 2001 From: Eddie Huang Date: Wed, 22 Oct 2014 15:12:00 +0200 Subject: DTS: serial: Add bindings document for the Mediatek UARTs This patch add s devicetree document for Mediatek UART. Signed-off-by: Eddie Huang Signed-off-by: Matthias Brugger --- Documentation/devicetree/bindings/serial/mtk-uart.txt | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/serial/mtk-uart.txt b/Documentation/devicetree/bindings/serial/mtk-uart.txt index 48358a33ea7d..0eebbfea91a4 100644 --- a/Documentation/devicetree/bindings/serial/mtk-uart.txt +++ b/Documentation/devicetree/bindings/serial/mtk-uart.txt @@ -2,6 +2,8 @@ Required properties: - compatible should contain: + * "mediatek,mt8135-uart" for MT8135 compatible UARTS + * "mediatek,mt8127-uart" for MT8127 compatible UARTS * "mediatek,mt6589-uart" for MT6589 compatible UARTS * "mediatek,mt6582-uart" for MT6582 compatible UARTS * "mediatek,mt6577-uart" for all compatible UARTS (MT6589, MT6582, MT6577) -- cgit v1.2.3-59-g8ed1b From 931ca3c5cda2fa926e29da8e77544f04a946f51a Mon Sep 17 00:00:00 2001 From: Howard Chen Date: Thu, 8 Jan 2015 14:23:11 +0800 Subject: dt-bindings: add mt6592 compatible string for mediatek sysirq This patch adds a compatible string for mt6592 SoC to the dts documentation of mediateks sysirq. Signed-off-by: Howard Chen Signed-off-by: Matthias Brugger --- Documentation/devicetree/bindings/arm/mediatek/mediatek,sysirq.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,sysirq.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,sysirq.txt index d680b07ec6e8..4cd6f7ba45c6 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,sysirq.txt +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,sysirq.txt @@ -7,6 +7,7 @@ Required properties: - compatible: should be one of: "mediatek,mt8135-sysirq" "mediatek,mt8127-sysirq" + "mediatek,mt6592-sysirq" "mediatek,mt6589-sysirq" "mediatek,mt6582-sysirq" "mediatek,mt6577-sysirq" -- cgit v1.2.3-59-g8ed1b From 912cdb4eb08d23704d629d8191a1ee9bcf53e71c Mon Sep 17 00:00:00 2001 From: Gregory CLEMENT Date: Thu, 8 Jan 2015 18:38:12 +0100 Subject: ARM: mvebu: Document the Device Tree binding for the Armada 388 SoC Update the binding documentation of the Armada 38x Soc family with the Armada 388. Signed-off-by: Gregory CLEMENT Signed-off-by: Andrew Lunn --- Documentation/devicetree/bindings/arm/armada-38x.txt | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/armada-38x.txt b/Documentation/devicetree/bindings/arm/armada-38x.txt index ad9f8ed4d9bd..202953f1887e 100644 --- a/Documentation/devicetree/bindings/arm/armada-38x.txt +++ b/Documentation/devicetree/bindings/arm/armada-38x.txt @@ -15,6 +15,13 @@ Required root node property: compatible: must contain "marvell,armada385" +In addition, boards using the Marvell Armada 388 SoC shall have the +following property before the previous one: + +Required root node property: + +compatible: must contain "marvell,armada388" + Example: compatible = "marvell,a385-rd", "marvell,armada385", "marvell,armada380"; -- cgit v1.2.3-59-g8ed1b From ddefbdb4c0df6bcb751971e2395e65daf26abb10 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 30 Dec 2014 13:43:42 +0100 Subject: dt: bindings: update mvebu-mbus DT binding with new compatible properties Contrary to what was originally thought, the Armada 375 and Armada 38x MBus windows hardware block is *not* compatible with the Armada 370, due to a difference in how window 13 is handled. It was rather compatible with the Armada XP MBus hardware block. However, the DTs for Armada 375 and Armada 38x encode the following compatible string for MBus: compatible = "marvell,armada375-mbus", "marvell,armada370-mbus", "simple-bus"; compatible = "marvell,armada380-mbus", "marvell,armada370-mbus", "simple-bus"; So, by extending the mvebu-mbus DT binding to also cover the marvell,armada375-mbus and marvell,armada380-mbus compatible strings, we can define a new behavior for those SoCs without changing the DT. Therefore, this commit adds those two new compatible strings to the DT binding documentation of mvebu-mbus. Note that it re-uses two existing duplicated lines for the armada370-mbus and armadaxp-mbus compatible strings. Signed-off-by: Thomas Petazzoni Signed-off-by: Andrew Lunn --- Documentation/devicetree/bindings/bus/mvebu-mbus.txt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/bus/mvebu-mbus.txt b/Documentation/devicetree/bindings/bus/mvebu-mbus.txt index 5e16c3ccb061..fa6cde41b460 100644 --- a/Documentation/devicetree/bindings/bus/mvebu-mbus.txt +++ b/Documentation/devicetree/bindings/bus/mvebu-mbus.txt @@ -6,8 +6,8 @@ Required properties: - compatible: Should be set to one of the following: marvell,armada370-mbus marvell,armadaxp-mbus - marvell,armada370-mbus - marvell,armadaxp-mbus + marvell,armada375-mbus + marvell,armada380-mbus marvell,kirkwood-mbus marvell,dove-mbus marvell,orion5x-88f5281-mbus -- cgit v1.2.3-59-g8ed1b From d19b4fa012f45efccef1d57fb4491df1bd559291 Mon Sep 17 00:00:00 2001 From: Barry Song Date: Sun, 4 Jan 2015 14:37:27 +0800 Subject: ARM: dts: drop MARCO platform DT stuff MARCO will not be supported any more. it has been replaced by CSR atlas7. Signed-off-by: Barry Song Acked-by: Arnd Bergmann --- Documentation/devicetree/bindings/arm/sirf.txt | 2 - arch/arm/boot/dts/Makefile | 1 - arch/arm/boot/dts/marco-evb.dts | 54 -- arch/arm/boot/dts/marco.dtsi | 757 ------------------------- 4 files changed, 814 deletions(-) delete mode 100644 arch/arm/boot/dts/marco-evb.dts delete mode 100644 arch/arm/boot/dts/marco.dtsi (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/sirf.txt b/Documentation/devicetree/bindings/arm/sirf.txt index c6ba6d3c747f..9daa1c1490a3 100644 --- a/Documentation/devicetree/bindings/arm/sirf.txt +++ b/Documentation/devicetree/bindings/arm/sirf.txt @@ -4,6 +4,4 @@ CSR SiRFprimaII and SiRFmarco device tree bindings. Required root node properties: - compatible: - "sirf,prima2-cb" : prima2 "cb" evaluation board - - "sirf,marco-cb" : marco "cb" evaluation board - "sirf,prima2" : prima2 device based board - - "sirf,marco" : marco device based board diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 91bd5bd62857..68feb8f8b5bc 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -175,7 +175,6 @@ dtb-$(CONFIG_MACH_KIRKWOOD) += kirkwood-b3.dtb \ kirkwood-ts419-6281.dtb \ kirkwood-ts419-6282.dtb dtb-$(CONFIG_ARCH_LPC32XX) += ea3250.dtb phy3250.dtb -dtb-$(CONFIG_ARCH_MARCO) += marco-evb.dtb dtb-$(CONFIG_MACH_MESON6) += meson6-atv1200.dtb dtb-$(CONFIG_ARCH_MMP) += pxa168-aspenite.dtb \ pxa910-dkb.dtb \ diff --git a/arch/arm/boot/dts/marco-evb.dts b/arch/arm/boot/dts/marco-evb.dts deleted file mode 100644 index 5130aeacfca5..000000000000 --- a/arch/arm/boot/dts/marco-evb.dts +++ /dev/null @@ -1,54 +0,0 @@ -/* - * DTS file for CSR SiRFmarco Evaluation Board - * - * Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company. - * - * Licensed under GPLv2 or later. - */ - -/dts-v1/; - -/include/ "marco.dtsi" - -/ { - model = "CSR SiRFmarco Evaluation Board"; - compatible = "sirf,marco-cb", "sirf,marco"; - - memory { - reg = <0x40000000 0x60000000>; - }; - - axi { - peri-iobg { - uart1: uart@cc060000 { - status = "okay"; - }; - uart2: uart@cc070000 { - status = "okay"; - }; - i2c0: i2c@cc0e0000 { - status = "okay"; - fpga-cpld@4d { - compatible = "sirf,fpga-cpld"; - reg = <0x4d>; - }; - }; - spi1: spi@cc170000 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&spi1_pins_a>; - spi@0 { - compatible = "spidev"; - reg = <0>; - spi-max-frequency = <1000000>; - }; - }; - pci-iobg { - sd0: sdhci@cd000000 { - bus-width = <8>; - status = "okay"; - }; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/marco.dtsi b/arch/arm/boot/dts/marco.dtsi deleted file mode 100644 index fb354225740a..000000000000 --- a/arch/arm/boot/dts/marco.dtsi +++ /dev/null @@ -1,757 +0,0 @@ -/* - * DTS file for CSR SiRFmarco SoC - * - * Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company. - * - * Licensed under GPLv2 or later. - */ - -/include/ "skeleton.dtsi" -/ { - compatible = "sirf,marco"; - #address-cells = <1>; - #size-cells = <1>; - interrupt-parent = <&gic>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0>; - }; - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <1>; - }; - }; - - axi { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x40000000 0x40000000 0xa0000000>; - - l2-cache-controller@c0030000 { - compatible = "arm,pl310-cache"; - reg = <0xc0030000 0x1000>; - interrupts = <0 59 0>; - arm,tag-latency = <1 1 1>; - arm,data-latency = <1 1 1>; - arm,filter-ranges = <0x40000000 0x80000000>; - }; - - gic: interrupt-controller@c0011000 { - compatible = "arm,cortex-a9-gic"; - interrupt-controller; - #interrupt-cells = <3>; - reg = <0xc0011000 0x1000>, - <0xc0010100 0x0100>; - }; - - rstc-iobg { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0xc2000000 0xc2000000 0x1000000>; - - rstc: reset-controller@c2000000 { - compatible = "sirf,marco-rstc"; - reg = <0xc2000000 0x10000>; - #reset-cells = <1>; - }; - }; - - sys-iobg { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0xc3000000 0xc3000000 0x1000000>; - - clock-controller@c3000000 { - compatible = "sirf,marco-clkc"; - reg = <0xc3000000 0x1000>; - interrupts = <0 3 0>; - }; - - rsc-controller@c3010000 { - compatible = "sirf,marco-rsc"; - reg = <0xc3010000 0x1000>; - }; - }; - - mem-iobg { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0xc4000000 0xc4000000 0x1000000>; - - memory-controller@c4000000 { - compatible = "sirf,marco-memc"; - reg = <0xc4000000 0x10000>; - interrupts = <0 27 0>; - }; - }; - - disp-iobg0 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0xc5000000 0xc5000000 0x1000000>; - - display0@c5000000 { - compatible = "sirf,marco-lcd"; - reg = <0xc5000000 0x10000>; - interrupts = <0 30 0>; - }; - - vpp0@c5010000 { - compatible = "sirf,marco-vpp"; - reg = <0xc5010000 0x10000>; - interrupts = <0 31 0>; - }; - }; - - disp-iobg1 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0xc6000000 0xc6000000 0x1000000>; - - display1@c6000000 { - compatible = "sirf,marco-lcd"; - reg = <0xc6000000 0x10000>; - interrupts = <0 62 0>; - }; - - vpp1@c6010000 { - compatible = "sirf,marco-vpp"; - reg = <0xc6010000 0x10000>; - interrupts = <0 63 0>; - }; - }; - - graphics-iobg { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0xc8000000 0xc8000000 0x1000000>; - - graphics@c8000000 { - compatible = "powervr,sgx540"; - reg = <0xc8000000 0x1000000>; - interrupts = <0 6 0>; - }; - }; - - multimedia-iobg { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0xc9000000 0xc9000000 0x1000000>; - - multimedia@a0000000 { - compatible = "sirf,marco-video-codec"; - reg = <0xc9000000 0x1000000>; - interrupts = <0 5 0>; - }; - }; - - dsp-iobg { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0xca000000 0xca000000 0x2000000>; - - dspif@ca000000 { - compatible = "sirf,marco-dspif"; - reg = <0xca000000 0x10000>; - interrupts = <0 9 0>; - }; - - gps@ca010000 { - compatible = "sirf,marco-gps"; - reg = <0xca010000 0x10000>; - interrupts = <0 7 0>; - }; - - dsp@cb000000 { - compatible = "sirf,marco-dsp"; - reg = <0xcb000000 0x1000000>; - interrupts = <0 8 0>; - }; - }; - - peri-iobg { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0xcc000000 0xcc000000 0x2000000>; - - timer@cc020000 { - compatible = "sirf,marco-tick"; - reg = <0xcc020000 0x1000>; - interrupts = <0 0 0>, - <0 1 0>, - <0 2 0>, - <0 49 0>, - <0 50 0>, - <0 51 0>; - }; - - nand@cc030000 { - compatible = "sirf,marco-nand"; - reg = <0xcc030000 0x10000>; - interrupts = <0 41 0>; - }; - - audio@cc040000 { - compatible = "sirf,marco-audio"; - reg = <0xcc040000 0x10000>; - interrupts = <0 35 0>; - }; - - uart0: uart@cc050000 { - cell-index = <0>; - compatible = "sirf,marco-uart"; - reg = <0xcc050000 0x1000>; - interrupts = <0 17 0>; - fifosize = <128>; - status = "disabled"; - }; - - uart1: uart@cc060000 { - cell-index = <1>; - compatible = "sirf,marco-uart"; - reg = <0xcc060000 0x1000>; - interrupts = <0 18 0>; - fifosize = <32>; - status = "disabled"; - }; - - uart2: uart@cc070000 { - cell-index = <2>; - compatible = "sirf,marco-uart"; - reg = <0xcc070000 0x1000>; - interrupts = <0 19 0>; - fifosize = <128>; - status = "disabled"; - }; - - uart3: uart@cc190000 { - cell-index = <3>; - compatible = "sirf,marco-uart"; - reg = <0xcc190000 0x1000>; - interrupts = <0 66 0>; - fifosize = <128>; - status = "disabled"; - }; - - uart4: uart@cc1a0000 { - cell-index = <4>; - compatible = "sirf,marco-uart"; - reg = <0xcc1a0000 0x1000>; - interrupts = <0 69 0>; - fifosize = <128>; - status = "disabled"; - }; - - usp0: usp@cc080000 { - cell-index = <0>; - compatible = "sirf,marco-usp"; - reg = <0xcc080000 0x10000>; - interrupts = <0 20 0>; - status = "disabled"; - }; - - usp1: usp@cc090000 { - cell-index = <1>; - compatible = "sirf,marco-usp"; - reg = <0xcc090000 0x10000>; - interrupts = <0 21 0>; - status = "disabled"; - }; - - usp2: usp@cc0a0000 { - cell-index = <2>; - compatible = "sirf,marco-usp"; - reg = <0xcc0a0000 0x10000>; - interrupts = <0 22 0>; - status = "disabled"; - }; - - dmac0: dma-controller@cc0b0000 { - cell-index = <0>; - compatible = "sirf,marco-dmac"; - reg = <0xcc0b0000 0x10000>; - interrupts = <0 12 0>; - }; - - dmac1: dma-controller@cc160000 { - cell-index = <1>; - compatible = "sirf,marco-dmac"; - reg = <0xcc160000 0x10000>; - interrupts = <0 13 0>; - }; - - vip@cc0c0000 { - compatible = "sirf,marco-vip"; - reg = <0xcc0c0000 0x10000>; - }; - - spi0: spi@cc0d0000 { - cell-index = <0>; - compatible = "sirf,marco-spi"; - reg = <0xcc0d0000 0x10000>; - interrupts = <0 15 0>; - sirf,spi-num-chipselects = <1>; - cs-gpios = <&gpio 0 0>; - sirf,spi-dma-rx-channel = <25>; - sirf,spi-dma-tx-channel = <20>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi1: spi@cc170000 { - cell-index = <1>; - compatible = "sirf,marco-spi"; - reg = <0xcc170000 0x10000>; - interrupts = <0 16 0>; - sirf,spi-num-chipselects = <1>; - cs-gpios = <&gpio 0 0>; - sirf,spi-dma-rx-channel = <12>; - sirf,spi-dma-tx-channel = <13>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c0: i2c@cc0e0000 { - cell-index = <0>; - compatible = "sirf,marco-i2c"; - reg = <0xcc0e0000 0x10000>; - interrupts = <0 24 0>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c1: i2c@cc0f0000 { - cell-index = <1>; - compatible = "sirf,marco-i2c"; - reg = <0xcc0f0000 0x10000>; - interrupts = <0 25 0>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - tsc@cc110000 { - compatible = "sirf,marco-tsc"; - reg = <0xcc110000 0x10000>; - interrupts = <0 33 0>; - }; - - gpio: pinctrl@cc120000 { - #gpio-cells = <2>; - #interrupt-cells = <2>; - compatible = "sirf,marco-pinctrl"; - reg = <0xcc120000 0x10000>; - interrupts = <0 43 0>, - <0 44 0>, - <0 45 0>, - <0 46 0>, - <0 47 0>; - gpio-controller; - interrupt-controller; - - lcd_16pins_a: lcd0_0 { - lcd { - sirf,pins = "lcd_16bitsgrp"; - sirf,function = "lcd_16bits"; - }; - }; - lcd_18pins_a: lcd0_1 { - lcd { - sirf,pins = "lcd_18bitsgrp"; - sirf,function = "lcd_18bits"; - }; - }; - lcd_24pins_a: lcd0_2 { - lcd { - sirf,pins = "lcd_24bitsgrp"; - sirf,function = "lcd_24bits"; - }; - }; - lcdrom_pins_a: lcdrom0_0 { - lcd { - sirf,pins = "lcdromgrp"; - sirf,function = "lcdrom"; - }; - }; - uart0_pins_a: uart0_0 { - uart { - sirf,pins = "uart0grp"; - sirf,function = "uart0"; - }; - }; - uart1_pins_a: uart1_0 { - uart { - sirf,pins = "uart1grp"; - sirf,function = "uart1"; - }; - }; - uart2_pins_a: uart2_0 { - uart { - sirf,pins = "uart2grp"; - sirf,function = "uart2"; - }; - }; - uart2_noflow_pins_a: uart2_1 { - uart { - sirf,pins = "uart2_nostreamctrlgrp"; - sirf,function = "uart2_nostreamctrl"; - }; - }; - spi0_pins_a: spi0_0 { - spi { - sirf,pins = "spi0grp"; - sirf,function = "spi0"; - }; - }; - spi1_pins_a: spi1_0 { - spi { - sirf,pins = "spi1grp"; - sirf,function = "spi1"; - }; - }; - i2c0_pins_a: i2c0_0 { - i2c { - sirf,pins = "i2c0grp"; - sirf,function = "i2c0"; - }; - }; - i2c1_pins_a: i2c1_0 { - i2c { - sirf,pins = "i2c1grp"; - sirf,function = "i2c1"; - }; - }; - pwm0_pins_a: pwm0_0 { - pwm { - sirf,pins = "pwm0grp"; - sirf,function = "pwm0"; - }; - }; - pwm1_pins_a: pwm1_0 { - pwm { - sirf,pins = "pwm1grp"; - sirf,function = "pwm1"; - }; - }; - pwm2_pins_a: pwm2_0 { - pwm { - sirf,pins = "pwm2grp"; - sirf,function = "pwm2"; - }; - }; - pwm3_pins_a: pwm3_0 { - pwm { - sirf,pins = "pwm3grp"; - sirf,function = "pwm3"; - }; - }; - gps_pins_a: gps_0 { - gps { - sirf,pins = "gpsgrp"; - sirf,function = "gps"; - }; - }; - vip_pins_a: vip_0 { - vip { - sirf,pins = "vipgrp"; - sirf,function = "vip"; - }; - }; - sdmmc0_pins_a: sdmmc0_0 { - sdmmc0 { - sirf,pins = "sdmmc0grp"; - sirf,function = "sdmmc0"; - }; - }; - sdmmc1_pins_a: sdmmc1_0 { - sdmmc1 { - sirf,pins = "sdmmc1grp"; - sirf,function = "sdmmc1"; - }; - }; - sdmmc2_pins_a: sdmmc2_0 { - sdmmc2 { - sirf,pins = "sdmmc2grp"; - sirf,function = "sdmmc2"; - }; - }; - sdmmc3_pins_a: sdmmc3_0 { - sdmmc3 { - sirf,pins = "sdmmc3grp"; - sirf,function = "sdmmc3"; - }; - }; - sdmmc4_pins_a: sdmmc4_0 { - sdmmc4 { - sirf,pins = "sdmmc4grp"; - sirf,function = "sdmmc4"; - }; - }; - sdmmc5_pins_a: sdmmc5_0 { - sdmmc5 { - sirf,pins = "sdmmc5grp"; - sirf,function = "sdmmc5"; - }; - }; - i2s_pins_a: i2s_0 { - i2s { - sirf,pins = "i2sgrp"; - sirf,function = "i2s"; - }; - }; - ac97_pins_a: ac97_0 { - ac97 { - sirf,pins = "ac97grp"; - sirf,function = "ac97"; - }; - }; - nand_pins_a: nand_0 { - nand { - sirf,pins = "nandgrp"; - sirf,function = "nand"; - }; - }; - usp0_pins_a: usp0_0 { - usp0 { - sirf,pins = "usp0grp"; - sirf,function = "usp0"; - }; - }; - usp1_pins_a: usp1_0 { - usp1 { - sirf,pins = "usp1grp"; - sirf,function = "usp1"; - }; - }; - usp2_pins_a: usp2_0 { - usp2 { - sirf,pins = "usp2grp"; - sirf,function = "usp2"; - }; - }; - usb0_utmi_drvbus_pins_a: usb0_utmi_drvbus_0 { - usb0_utmi_drvbus { - sirf,pins = "usb0_utmi_drvbusgrp"; - sirf,function = "usb0_utmi_drvbus"; - }; - }; - usb1_utmi_drvbus_pins_a: usb1_utmi_drvbus_0 { - usb1_utmi_drvbus { - sirf,pins = "usb1_utmi_drvbusgrp"; - sirf,function = "usb1_utmi_drvbus"; - }; - }; - warm_rst_pins_a: warm_rst_0 { - warm_rst { - sirf,pins = "warm_rstgrp"; - sirf,function = "warm_rst"; - }; - }; - pulse_count_pins_a: pulse_count_0 { - pulse_count { - sirf,pins = "pulse_countgrp"; - sirf,function = "pulse_count"; - }; - }; - cko0_rst_pins_a: cko0_rst_0 { - cko0_rst { - sirf,pins = "cko0_rstgrp"; - sirf,function = "cko0_rst"; - }; - }; - cko1_rst_pins_a: cko1_rst_0 { - cko1_rst { - sirf,pins = "cko1_rstgrp"; - sirf,function = "cko1_rst"; - }; - }; - }; - - pwm@cc130000 { - compatible = "sirf,marco-pwm"; - reg = <0xcc130000 0x10000>; - }; - - efusesys@cc140000 { - compatible = "sirf,marco-efuse"; - reg = <0xcc140000 0x10000>; - }; - - pulsec@cc150000 { - compatible = "sirf,marco-pulsec"; - reg = <0xcc150000 0x10000>; - interrupts = <0 48 0>; - }; - - pci-iobg { - compatible = "sirf,marco-pciiobg", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0xcd000000 0xcd000000 0x1000000>; - - sd0: sdhci@cd000000 { - cell-index = <0>; - compatible = "sirf,marco-sdhc"; - reg = <0xcd000000 0x100000>; - interrupts = <0 38 0>; - status = "disabled"; - }; - - sd1: sdhci@cd100000 { - cell-index = <1>; - compatible = "sirf,marco-sdhc"; - reg = <0xcd100000 0x100000>; - interrupts = <0 38 0>; - status = "disabled"; - }; - - sd2: sdhci@cd200000 { - cell-index = <2>; - compatible = "sirf,marco-sdhc"; - reg = <0xcd200000 0x100000>; - interrupts = <0 23 0>; - status = "disabled"; - }; - - sd3: sdhci@cd300000 { - cell-index = <3>; - compatible = "sirf,marco-sdhc"; - reg = <0xcd300000 0x100000>; - interrupts = <0 23 0>; - status = "disabled"; - }; - - sd4: sdhci@cd400000 { - cell-index = <4>; - compatible = "sirf,marco-sdhc"; - reg = <0xcd400000 0x100000>; - interrupts = <0 39 0>; - status = "disabled"; - }; - - sd5: sdhci@cd500000 { - cell-index = <5>; - compatible = "sirf,marco-sdhc"; - reg = <0xcd500000 0x100000>; - interrupts = <0 39 0>; - status = "disabled"; - }; - - pci-copy@cd900000 { - compatible = "sirf,marco-pcicp"; - reg = <0xcd900000 0x100000>; - interrupts = <0 40 0>; - }; - - rom-interface@cda00000 { - compatible = "sirf,marco-romif"; - reg = <0xcda00000 0x100000>; - }; - }; - }; - - rtc-iobg { - compatible = "sirf,marco-rtciobg", "sirf-marco-rtciobg-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0xc1000000 0x10000>; - - gpsrtc@1000 { - compatible = "sirf,marco-gpsrtc"; - reg = <0x1000 0x1000>; - interrupts = <0 55 0>, - <0 56 0>, - <0 57 0>; - }; - - sysrtc@2000 { - compatible = "sirf,marco-sysrtc"; - reg = <0x2000 0x1000>; - interrupts = <0 52 0>, - <0 53 0>, - <0 54 0>; - }; - - pwrc@3000 { - compatible = "sirf,marco-pwrc"; - reg = <0x3000 0x1000>; - interrupts = <0 32 0>; - }; - }; - - uus-iobg { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0xce000000 0xce000000 0x1000000>; - - usb0: usb@ce000000 { - compatible = "chipidea,ci13611a-marco"; - reg = <0xce000000 0x10000>; - interrupts = <0 10 0>; - }; - - usb1: usb@ce010000 { - compatible = "chipidea,ci13611a-marco"; - reg = <0xce010000 0x10000>; - interrupts = <0 11 0>; - }; - - security@ce020000 { - compatible = "sirf,marco-security"; - reg = <0xce020000 0x10000>; - interrupts = <0 42 0>; - }; - }; - - can-iobg { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0xd0000000 0xd0000000 0x1000000>; - - can0: can@d0000000 { - compatible = "sirf,marco-can"; - reg = <0xd0000000 0x10000>; - }; - - can1: can@d0010000 { - compatible = "sirf,marco-can"; - reg = <0xd0010000 0x10000>; - }; - }; - - lvds-iobg { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0xd1000000 0xd1000000 0x1000000>; - - lvds@d1000000 { - compatible = "sirf,marco-lvds"; - reg = <0xd1000000 0x10000>; - interrupts = <0 64 0>; - }; - }; - }; -}; -- cgit v1.2.3-59-g8ed1b From 4e46e7d4f7567ac5ced0d6d5b6770c1af4adf286 Mon Sep 17 00:00:00 2001 From: Pankaj Dubey Date: Mon, 12 Jan 2015 18:16:46 +0900 Subject: Documentation: dt-bindings: add exynos-chipid binding information Exynos SoC's DT files are using Chipid device nodes, but it's binding information is missing. This patch adds exynos-chipid binding information. Signed-off-by: Pankaj Dubey Signed-off-by: Kukjin Kim --- .../devicetree/bindings/arm/samsung/exynos-chipid.txt | 12 ++++++++++++ 1 file changed, 12 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/samsung/exynos-chipid.txt (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/samsung/exynos-chipid.txt b/Documentation/devicetree/bindings/arm/samsung/exynos-chipid.txt new file mode 100644 index 000000000000..85c5dfd4a720 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/samsung/exynos-chipid.txt @@ -0,0 +1,12 @@ +SAMSUNG Exynos SoCs Chipid driver. + +Required properties: +- compatible : Should at least contain "samsung,exynos4210-chipid". + +- reg: offset and length of the register set + +Example: + chipid@10000000 { + compatible = "samsung,exynos4210-chipid"; + reg = <0x10000000 0x100>; + }; -- cgit v1.2.3-59-g8ed1b From 3b8df3903465803f47902fe0510628efdd6ab5a3 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 3 Dec 2014 14:41:41 +0100 Subject: PM / Domains: Add DT bindings for the R-Mobile System Controller The Renesas R-Mobile System Controller provides a.o. power management support, following the generic PM domain bindings in Documentation/devicetree/bindings/power/power_domain.txt. For now this supports the R-Mobile A1 (r8a7740) only, but it should be sufficiently generic to handle other members of the SH-Mobile/R-Mobile family in the future. Signed-off-by: Geert Uytterhoeven Reviewed-by: Ulf Hansson Signed-off-by: Simon Horman --- .../bindings/power/renesas,sysc-rmobile.txt | 98 ++++++++++++++++++++++ 1 file changed, 98 insertions(+) create mode 100644 Documentation/devicetree/bindings/power/renesas,sysc-rmobile.txt (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/power/renesas,sysc-rmobile.txt b/Documentation/devicetree/bindings/power/renesas,sysc-rmobile.txt new file mode 100644 index 000000000000..2460476808e9 --- /dev/null +++ b/Documentation/devicetree/bindings/power/renesas,sysc-rmobile.txt @@ -0,0 +1,98 @@ +DT bindings for the Renesas R-Mobile System Controller + +== System Controller Node == + +The R-Mobile System Controller provides the following functions: + - Boot mode management, + - Reset generation, + - Power management. + +Required properties: +- compatible: Should be "renesas,sysc-", "renesas,sysc-rmobile" as + fallback. + Examples with soctypes are: + - "renesas,sysc-r8a7740" (R-Mobile A1) +- reg: Two address start and address range blocks for the device: + - The first block refers to the normally accessible registers, + - the second block refers to the registers protected by the HPB + semaphore. + +Optional nodes: +- pm-domains: This node contains a hierarchy of PM domain nodes, which should + match the Power Area Hierarchy in the Power Domain Specifications section of + the device's datasheet. + + +== PM Domain Nodes == + +Each of the PM domain nodes represents a PM domain, as documented by the +generic PM domain bindings in +Documentation/devicetree/bindings/power/power_domain.txt. + +The nodes should be named by the real power area names, and thus their names +should be unique. + +Required properties: + - #power-domain-cells: Must be 0. + +Optional properties: +- reg: If the PM domain is not always-on, this property must contain the bit + index number for the corresponding power area in the various Power + Control and Status Registers. The parent's node must contain the + following two properties: + - #address-cells: Must be 1, + - #size-cells: Must be 0. + If the PM domain is always-on, this property must be omitted. + + +Example: + +This shows a subset of the r8a7740 PM domain hierarchy, containing the +C5 "always-on" domain, 2 of its subdomains (A4S and A4SU), and the A3SP domain, +which is a subdomain of A4S. + + sysc: system-controller@e6180000 { + compatible = "renesas,sysc-r8a7740", "renesas,sysc-rmobile"; + reg = <0xe6180000 0x8000>, <0xe6188000 0x8000>; + + pm-domains { + pd_c5: c5 { + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <0>; + + pd_a4s: a4s@10 { + reg = <10>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <0>; + + pd_a3sp: a3sp@11 { + reg = <11>; + #power-domain-cells = <0>; + }; + }; + + pd_a4su: a4su@20 { + reg = <20>; + #power-domain-cells = <0>; + }; + }; + }; + }; + + +== PM Domain Consumers == + +Hardware blocks belonging to a PM domain should contain a "power-domains" +property that is a phandle pointing to the corresponding PM domain node. + +Example: + + tpu: pwm@e6600000 { + compatible = "renesas,tpu-r8a7740", "renesas,tpu"; + reg = <0xe6600000 0x100>; + clocks = <&mstp3_clks R8A7740_CLK_TPU0>; + power-domains = <&pd_a3sp>; + #pwm-cells = <3>; + }; -- cgit v1.2.3-59-g8ed1b From 7d76d03b9be8ea8977df45176336cc4fec6ac603 Mon Sep 17 00:00:00 2001 From: Zhiwu Song Date: Thu, 25 Dec 2014 16:34:19 +0800 Subject: ARM: dts: add init dts file for CSR atlas7 SoC CSR atlas7 uses Network on Chip(NoC) bus architecture, there are dozens of MARCOs, in each MARCO, there are dozens of hardware modules. Signed-off-by: Zhiwu Song Signed-off-by: Hao Liu Signed-off-by: Barry Song Acked-by: Arnd Bergmann --- Documentation/devicetree/bindings/arm/sirf.txt | 4 + arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/atlas7-evb.dts | 110 ++++ arch/arm/boot/dts/atlas7.dtsi | 813 +++++++++++++++++++++++++ 4 files changed, 928 insertions(+) create mode 100644 arch/arm/boot/dts/atlas7-evb.dts create mode 100644 arch/arm/boot/dts/atlas7.dtsi (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/sirf.txt b/Documentation/devicetree/bindings/arm/sirf.txt index 9daa1c1490a3..7b28ee6fee91 100644 --- a/Documentation/devicetree/bindings/arm/sirf.txt +++ b/Documentation/devicetree/bindings/arm/sirf.txt @@ -3,5 +3,9 @@ CSR SiRFprimaII and SiRFmarco device tree bindings. Required root node properties: - compatible: + - "sirf,atlas6-cb" : atlas6 "cb" evaluation board + - "sirf,atlas6" : atlas6 device based board + - "sirf,atlas7-cb" : atlas7 "cb" evaluation board + - "sirf,atlas7" : atlas7 device based board - "sirf,prima2-cb" : prima2 "cb" evaluation board - "sirf,prima2" : prima2 device based board diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 68feb8f8b5bc..0048cb16370f 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -52,6 +52,7 @@ dtb-$(CONFIG_ARCH_AT91) += sama5d36ek.dtb dtb-$(CONFIG_ARCH_AT91) += at91-sama5d4ek.dtb dtb-$(CONFIG_ARCH_ATLAS6) += atlas6-evb.dtb +dtb-$(CONFIG_ARCH_ATLAS7) += atlas7-evb.dtb dtb-$(CONFIG_ARCH_AXXIA) += axm5516-amarillo.dtb dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b-plus.dtb diff --git a/arch/arm/boot/dts/atlas7-evb.dts b/arch/arm/boot/dts/atlas7-evb.dts new file mode 100644 index 000000000000..49cf59a95572 --- /dev/null +++ b/arch/arm/boot/dts/atlas7-evb.dts @@ -0,0 +1,110 @@ +/* + * DTS file for CSR SiRFatlas7 Evaluation Board + * + * Copyright (c) 2014 Cambridge Silicon Radio Limited, a CSR plc group company. + * + * Licensed under GPLv2 or later. + */ + +/dts-v1/; + +/include/ "atlas7.dtsi" + +/ { + model = "CSR SiRFatlas7 Evaluation Board"; + compatible = "sirf,atlas7-cb", "sirf,atlas7"; + + chosen { + bootargs = "console=ttySiRF1,115200 earlyprintk"; + }; + + memory { + device_type = "memory"; + reg = <0x40000000 0x20000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + vpp_reserved: vpp_mem@5e800000 { + compatible = "sirf,reserved-memory"; + reg = <0x5e800000 0x800000>; + }; + + nanddisk_reserved: nanddisk@46000000 { + reg = <0x46000000 0x200000>; + no-map; + }; + }; + + + noc { + mediam { + nand@17050000 { + memory-region = <&nanddisk_reserved>; + }; + }; + + gnssm { + spi1: spi@18200000 { + status = "okay"; + spiflash: macronix@0{ + status = "okay"; + compatible = "macronix,mx25l6405d"; + reg = <0>; + spi-max-frequency = <37500000>; + spi-cpha; + spi-cpol; + #address-cells = <1>; + #size-cells = <1>; + partitions@0 { + label = "myspiboot"; + reg = <0x0 0x800000>; + }; + }; + }; + }; + + btm { + uart6: uart@11000000 { + status = "okay"; + sirf,uart-has-rtscts; + }; + }; + + disp-iobg { + vpp@13110000 { + memory-region = <&vpp_reserved>; + }; + }; + + display0: display@0 { + compatible = "lvds-panel"; + source = "lvds.0"; + + bl-gpios = <&gpio_1 63 0>; + data-lines = <24>; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <60000000>; + hactive = <1024>; + vactive = <600>; + hfront-porch = <220>; + hback-porch = <100>; + hsync-len = <1>; + vback-porch = <10>; + vfront-porch = <25>; + vsync-len = <1>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <1>; + }; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/atlas7.dtsi b/arch/arm/boot/dts/atlas7.dtsi new file mode 100644 index 000000000000..a753178abc85 --- /dev/null +++ b/arch/arm/boot/dts/atlas7.dtsi @@ -0,0 +1,813 @@ +/* + * DTS file for CSR SiRFatlas7 SoC + * + * Copyright (c) 2014 Cambridge Silicon Radio Limited, a CSR plc group company. + * + * Licensed under GPLv2 or later. + */ + +/include/ "skeleton.dtsi" +/ { + compatible = "sirf,atlas7"; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&gic>; + aliases { + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + serial4 = &uart4; + serial5 = &uart5; + serial6 = &uart6; + serial9 = &usp2; + }; + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0>; + }; + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <1>; + }; + }; + + noc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x10000000 0x10000000 0xc0000000>; + + gic: interrupt-controller@10301000 { + compatible = "arm,cortex-a9-gic"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0x10301000 0x1000>, + <0x10302000 0x0100>; + }; + + pmu_regulator: pmu_regulator@10E30020 { + compatible = "sirf,atlas7-pmu-ldo"; + reg = <0x10E30020 0x4>; + ldo: ldo { + regulator-name = "ldo"; + }; + }; + + atlas7_codec: atlas7_codec@10E30000 { + #sound-dai-cells = <0>; + compatible = "sirf,atlas7-codec"; + reg = <0x10E30000 0x400>; + clocks = <&car 62>; + ldo-supply = <&ldo>; + }; + + atlas7_iacc: atlas7_iacc@10D01000 { + #sound-dai-cells = <0>; + compatible = "sirf,atlas7-iacc"; + reg = <0x10D01000 0x100>; + dmas = <&dmac3 0>, <&dmac3 7>, <&dmac3 8>, + <&dmac3 3>, <&dmac3 9>; + dma-names = "rx", "tx0", "tx1", "tx2", "tx3"; + clocks = <&car 62>; + }; + + ipc@13240000 { + compatible = "sirf,atlas7-ipc"; + ranges = <0x13240000 0x13240000 0x00010000>; + #address-cells = <1>; + #size-cells = <1>; + + hwspinlock { + compatible = "sirf,hwspinlock"; + reg = <0x13240000 0x00010000>; + + num-spinlocks = <30>; + }; + + ns_m3_rproc@0 { + compatible = "sirf,ns2m30-rproc"; + reg = <0x13240000 0x00010000>; + interrupts = <0 123 0>; + }; + + ns_m3_rproc@1 { + compatible = "sirf,ns2m31-rproc"; + reg = <0x13240000 0x00010000>; + interrupts = <0 126 0>; + }; + + ns_kal_rproc@0 { + compatible = "sirf,ns2kal0-rproc"; + reg = <0x13240000 0x00010000>; + interrupts = <0 124 0>; + }; + + ns_kal_rproc@1 { + compatible = "sirf,ns2kal1-rproc"; + reg = <0x13240000 0x00010000>; + interrupts = <0 127 0>; + }; + }; + + pinctrl: ioc@18880000 { + compatible = "sirf,atlas7-ioc"; + reg = <0x18880000 0x1000>, + <0x10E40000 0x1000>; + }; + + pmipc { + compatible = "arteris, flexnoc", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x13240000 0x13240000 0x00010000>; + pmipc@0x13240000 { + compatible = "sirf,atlas7-pmipc"; + reg = <0x13240000 0x00010000>; + }; + }; + + dramfw { + compatible = "arteris, flexnoc", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x10830000 0x10830000 0x18000>; + dramfw@10820000 { + compatible = "sirf,nocfw-dramfw"; + reg = <0x10830000 0x18000>; + }; + }; + + spramfw { + compatible = "arteris, flexnoc", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x10250000 0x10250000 0x3000>; + spramfw@10820000 { + compatible = "sirf,nocfw-spramfw"; + reg = <0x10250000 0x3000>; + }; + }; + + cpum { + compatible = "arteris, flexnoc", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x10200000 0x10200000 0x3000>; + cpum@10200000 { + compatible = "sirf,nocfw-cpum"; + reg = <0x10200000 0x3000>; + }; + }; + + cgum { + compatible = "arteris, flexnoc", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x18641000 0x18641000 0x3000>, + <0x18620000 0x18620000 0x1000>; + + cgum@18641000 { + compatible = "sirf,nocfw-cgum"; + reg = <0x18641000 0x3000>; + }; + + car: clock-controller@18620000 { + compatible = "sirf,atlas7-car"; + reg = <0x18620000 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + }; + + gnssm { + compatible = "arteris, flexnoc", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x18000000 0x18000000 0x0000ffff>, + <0x18010000 0x18010000 0x1000>, + <0x18020000 0x18020000 0x1000>, + <0x18030000 0x18030000 0x1000>, + <0x18040000 0x18040000 0x1000>, + <0x18050000 0x18050000 0x1000>, + <0x18060000 0x18060000 0x1000>, + <0x18100000 0x18100000 0x3000>, + <0x18250000 0x18250000 0x10000>, + <0x18200000 0x18200000 0x1000>; + + dmac0: dma-controller@18000000 { + cell-index = <0>; + compatible = "sirf,atlas7-dmac"; + reg = <0x18000000 0x1000>; + interrupts = <0 12 0>; + clocks = <&car 89>; + dma-channels = <16>; + #dma-cells = <1>; + }; + + gnssmfw@0x18100000 { + compatible = "sirf,nocfw-gnssm"; + reg = <0x18100000 0x3000>; + }; + + uart0: uart@18010000 { + cell-index = <0>; + compatible = "sirf,atlas7-uart"; + reg = <0x18010000 0x1000>; + interrupts = <0 17 0>; + clocks = <&car 90>; + fifosize = <128>; + dmas = <&dmac0 3>, <&dmac0 2>; + dma-names = "rx", "tx"; + }; + + uart1: uart@18020000 { + cell-index = <1>; + compatible = "sirf,atlas7-uart"; + reg = <0x18020000 0x1000>; + interrupts = <0 18 0>; + clocks = <&car 88>; + fifosize = <32>; + }; + + uart2: uart@18030000 { + cell-index = <2>; + compatible = "sirf,atlas7-uart"; + reg = <0x18030000 0x1000>; + interrupts = <0 19 0>; + clocks = <&car 91>; + fifosize = <128>; + dmas = <&dmac0 6>, <&dmac0 7>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + uart3: uart@18040000 { + cell-index = <3>; + compatible = "sirf,atlas7-uart"; + reg = <0x18040000 0x1000>; + interrupts = <0 66 0>; + clocks = <&car 92>; + fifosize = <128>; + dmas = <&dmac0 4>, <&dmac0 5>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + uart4: uart@18050000 { + cell-index = <4>; + compatible = "sirf,atlas7-uart"; + reg = <0x18050000 0x1000>; + interrupts = <0 69 0>; + clocks = <&car 93>; + fifosize = <128>; + dmas = <&dmac0 0>, <&dmac0 1>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + uart5: uart@18060000 { + cell-index = <5>; + compatible = "sirf,atlas7-uart"; + reg = <0x18060000 0x1000>; + interrupts = <0 71 0>; + clocks = <&car 94>; + fifosize = <128>; + dmas = <&dmac0 8>, <&dmac0 9>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + dspub@18250000 { + compatible = "dx,cc44p"; + reg = <0x18250000 0x10000>; + interrupts = <0 27 0>; + }; + + spi1: spi@18200000 { + compatible = "sirf,prima2-spi"; + reg = <0x18200000 0x1000>; + interrupts = <0 16 0>; + clocks = <&car 95>; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&dmac0 12>, <&dmac0 13>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + }; + + + gpum { + compatible = "arteris, flexnoc", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x13000000 0x13000000 0x3000>; + gpum@0x13000000 { + compatible = "sirf,nocfw-gpum"; + reg = <0x13000000 0x3000>; + }; + }; + + mediam { + compatible = "arteris, flexnoc", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x16000000 0x16000000 0x00200000>, + <0x17020000 0x17020000 0x1000>, + <0x17030000 0x17030000 0x1000>, + <0x17040000 0x17040000 0x1000>, + <0x17050000 0x17050000 0x10000>, + <0x17060000 0x17060000 0x200>, + <0x17060200 0x17060200 0x100>, + <0x17070000 0x17070000 0x200>, + <0x17070200 0x17070200 0x100>, + <0x170A0000 0x170A0000 0x3000>; + + mediam@170A0000 { + compatible = "sirf,nocfw-mediam"; + reg = <0x170A0000 0x3000>; + }; + + gpio_0: gpio_mediam@17040000 { + #gpio-cells = <2>; + #interrupt-cells = <2>; + compatible = "sirf,atlas7-gpio"; + reg = <0x17040000 0x1000>; + interrupts = <0 13 0>, <0 14 0>; + clocks = <&car 107>; + clock-names = "gpio0_io"; + gpio-controller; + interrupt-controller; + }; + + nand@17050000 { + compatible = "sirf,atlas7-nand"; + reg = <0x17050000 0x10000>; + interrupts = <0 41 0>; + clocks = <&car 108>, <&car 112>; + clock-names = "nand_io", "nand_nand"; + }; + + sd0: sdhci@16000000 { + cell-index = <0>; + compatible = "sirf,atlas7-sdhc"; + reg = <0x16000000 0x100000>; + interrupts = <0 38 0>; + clocks = <&car 109>, <&car 111>; + clock-names = "core", "iface"; + wp-inverted; + non-removable; + status = "disabled"; + bus-width = <8>; + }; + + sd1: sdhci@16100000 { + cell-index = <1>; + compatible = "sirf,atlas7-sdhc"; + reg = <0x16100000 0x100000>; + interrupts = <0 38 0>; + clocks = <&car 109>, <&car 111>; + clock-names = "core", "iface"; + non-removable; + status = "disabled"; + bus-width = <8>; + }; + + usb0: usb@17060000 { + cell-index = <0>; + compatible = "sirf,atlas7-usb"; + reg = <0x17060000 0x200>; + interrupts = <0 10 0>; + clocks = <&car 113>; + sirf,usbphy = <&usbphy0>; + phy_type = "utmi"; + dr_mode = "otg"; + maximum-speed = "high-speed"; + status = "okay"; + }; + + usb1: usb@17070000 { + cell-index = <1>; + compatible = "sirf,atlas7-usb"; + reg = <0x17070000 0x200>; + interrupts = <0 11 0>; + clocks = <&car 114>; + sirf,usbphy = <&usbphy1>; + phy_type = "utmi"; + dr_mode = "host"; + maximum-speed = "high-speed"; + status = "okay"; + }; + + usbphy0: usbphy@0 { + compatible = "sirf,atlas7-usbphy"; + reg = <0x17060200 0x100>; + clocks = <&car 115>; + status = "okay"; + }; + + usbphy1: usbphy@1 { + compatible = "sirf,atlas7-usbphy"; + reg = <0x17070200 0x100>; + clocks = <&car 116>; + status = "okay"; + }; + + i2c0: i2c@17020000 { + cell-index = <0>; + compatible = "sirf,prima2-i2c"; + reg = <0x17020000 0x1000>; + interrupts = <0 24 0>; + clocks = <&car 105>; + #address-cells = <1>; + #size-cells = <0>; + }; + + }; + + vdifm { + compatible = "arteris, flexnoc", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x13290000 0x13290000 0x3000>, + <0x13300000 0x13300000 0x1000>, + <0x14200000 0x14200000 0x600000>; + + vdifm@13290000 { + compatible = "sirf,nocfw-vdifm"; + reg = <0x13290000 0x3000>; + }; + + gpio_1: gpio_vdifm@13300000 { + #gpio-cells = <2>; + #interrupt-cells = <2>; + compatible = "sirf,atlas7-gpio"; + reg = <0x13300000 0x1000>; + interrupts = <0 43 0>, <0 44 0>, <0 45 0>; + clocks = <&car 84>; + clock-names = "gpio1_io"; + gpio-controller; + interrupt-controller; + }; + + sd2: sdhci@14200000 { + cell-index = <2>; + compatible = "sirf,atlas7-sdhc"; + reg = <0x14200000 0x100000>; + interrupts = <0 23 0>; + clocks = <&car 70>, <&car 75>; + clock-names = "core", "iface"; + status = "disabled"; + bus-width = <4>; + sd-uhs-sdr50; + vqmmc-supply = <&vqmmc>; + vqmmc: vqmmc@2 { + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <1950000>; + regulator-name = "vqmmc-ldo"; + regulator-type = "voltage"; + regulator-boot-on; + regulator-allow-bypass; + }; + }; + + sd3: sdhci@14300000 { + cell-index = <3>; + compatible = "sirf,atlas7-sdhc"; + reg = <0x14300000 0x100000>; + interrupts = <0 23 0>; + clocks = <&car 76>, <&car 81>; + clock-names = "core", "iface"; + status = "disabled"; + bus-width = <4>; + }; + + sd5: sdhci@14500000 { + cell-index = <5>; + compatible = "sirf,atlas7-sdhc"; + reg = <0x14500000 0x100000>; + interrupts = <0 39 0>; + clocks = <&car 71>, <&car 76>; + clock-names = "core", "iface"; + status = "disabled"; + bus-width = <4>; + loop-dma; + }; + + sd6: sdhci@14600000 { + cell-index = <6>; + compatible = "sirf,atlas7-sdhc"; + reg = <0x14600000 0x100000>; + interrupts = <0 98 0>; + clocks = <&car 72>, <&car 77>; + clock-names = "core", "iface"; + status = "disabled"; + bus-width = <4>; + }; + + sd7: sdhci@14700000 { + cell-index = <7>; + compatible = "sirf,atlas7-sdhc"; + reg = <0x14700000 0x100000>; + interrupts = <0 98 0>; + clocks = <&car 72>, <&car 77>; + clock-names = "core", "iface"; + status = "disabled"; + bus-width = <4>; + }; + }; + + audiom { + compatible = "arteris, flexnoc", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x10d50000 0x10d50000 0x0000ffff>, + <0x10d60000 0x10d60000 0x0000ffff>, + <0x10d80000 0x10d80000 0x0000ffff>, + <0x10d90000 0x10d90000 0x0000ffff>, + <0x10ED0000 0x10ED0000 0x3000>, + <0x10dc8000 0x10dc8000 0x1000>, + <0x10dc0000 0x10dc0000 0x1000>, + <0x10db0000 0x10db0000 0x4000>, + <0x10d40000 0x10d40000 0x1000>, + <0x10d30000 0x10d30000 0x1000>; + + timer@10dc0000 { + compatible = "sirf,atlas7-tick"; + reg = <0x10dc0000 0x1000>; + interrupts = <0 0 0>, + <0 1 0>, + <0 2 0>, + <0 49 0>, + <0 50 0>, + <0 51 0>; + clocks = <&car 47>; + }; + + timerb@10dc8000 { + compatible = "sirf,atlas7-tick"; + reg = <0x10dc8000 0x1000>; + interrupts = <0 74 0>, + <0 75 0>, + <0 76 0>, + <0 77 0>, + <0 78 0>, + <0 79 0>; + clocks = <&car 47>; + }; + + vip0@10db0000 { + compatible = "sirf,atlas7-vip0"; + reg = <0x10db0000 0x2000>; + interrupts = <0 85 0>; + sirf,vip_cma_size = <0xC00000>; + }; + + cvd@10db2000 { + compatible = "sirf,cvd"; + reg = <0x10db2000 0x2000>; + clocks = <&car 46>; + }; + + dmac2: dma-controller@10d50000 { + cell-index = <2>; + compatible = "sirf,atlas7-dmac"; + reg = <0x10d50000 0xffff>; + interrupts = <0 55 0>; + clocks = <&car 60>; + dma-channels = <16>; + #dma-cells = <1>; + }; + + dmac3: dma-controller@10d60000 { + cell-index = <3>; + compatible = "sirf,atlas7-dmac"; + reg = <0x10d60000 0xffff>; + interrupts = <0 56 0>; + clocks = <&car 61>; + dma-channels = <16>; + #dma-cells = <1>; + }; + + adc: adc@10d80000 { + compatible = "sirf,atlas7-adc"; + reg = <0x10d80000 0xffff>; + interrupts = <0 34 0>; + clocks = <&car 49>; + #io-channel-cells = <1>; + }; + + pulsec@10d90000 { + compatible = "sirf,prima2-pulsec"; + reg = <0x10d90000 0xffff>; + interrupts = <0 42 0>; + clocks = <&car 54>; + }; + + audiom@10ED0000 { + compatible = "sirf,nocfw-audiom"; + reg = <0x10ED0000 0x3000>; + interrupts = <0 102 0>; + }; + + usp1: usp@10d30000 { + cell-index = <1>; + reg = <0x10d30000 0x1000>; + fifosize = <512>; + clocks = <&car 58>; + dmas = <&dmac2 6>, <&dmac2 7>; + dma-names = "rx", "tx"; + }; + + usp2: usp@10d40000 { + cell-index = <2>; + reg = <0x10d40000 0x1000>; + interrupts = <0 22 0>; + clocks = <&car 59>; + dmas = <&dmac2 12>, <&dmac2 13>; + dma-names = "rx", "tx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + ddrm { + compatible = "arteris, flexnoc", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x10820000 0x10820000 0x3000>, + <0x10800000 0x10800000 0x2000>; + ddrm@10820000 { + compatible = "sirf,nocfw-ddrm"; + reg = <0x10820000 0x3000>; + interrupts = <0 105 0>; + }; + + memory-controller@0x10800000 { + compatible = "sirf,atlas7-memc"; + reg = <0x10800000 0x2000>; + }; + + }; + + btm { + compatible = "arteris, flexnoc", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x11002000 0x11002000 0x0000ffff>, + <0x11010000 0x11010000 0x3000>, + <0x11000000 0x11000000 0x1000>, + <0x11001000 0x11001000 0x1000>; + + dmac4: dma-controller@11002000 { + cell-index = <4>; + compatible = "sirf,atlas7-dmac"; + reg = <0x11002000 0x1000>; + interrupts = <0 99 0>; + clocks = <&car 130>; + dma-channels = <16>; + #dma-cells = <1>; + }; + uart6: uart@11000000 { + cell-index = <6>; + compatible = "sirf,atlas7-bt-uart", + "sirf,atlas7-uart"; + reg = <0x11000000 0x1000>; + interrupts = <0 100 0>; + clocks = <&car 131>, <&car 133>, <&car 134>; + clock-names = "uart", "general", "noc"; + fifosize = <128>; + dmas = <&dmac4 12>, <&dmac4 13>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + usp3: usp@11001000 { + compatible = "sirf,atlas7-bt-usp", + "sirf,prima2-usp-pcm"; + cell-index = <3>; + reg = <0x11001000 0x1000>; + fifosize = <512>; + clocks = <&car 132>, <&car 129>, <&car 133>, + <&car 134>, <&car 135>; + clock-names = "usp3_io", "a7ca_btss", "a7ca_io", + "noc_btm_io", "thbtm_io"; + dmas = <&dmac4 0>, <&dmac4 1>; + dma-names = "rx", "tx"; + }; + + btm@11010000 { + compatible = "sirf,nocfw-btm"; + reg = <0x11010000 0x3000>; + }; + }; + + rtcm { + compatible = "arteris, flexnoc", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x18810000 0x18810000 0x3000>, + <0x18840000 0x18840000 0x1000>, + <0x18890000 0x18890000 0x1000>, + <0x188B0000 0x188B0000 0x10000>, + <0x188D0000 0x188D0000 0x1000>; + rtcm@18810000 { + compatible = "sirf,nocfw-rtcm"; + reg = <0x18810000 0x3000>; + interrupts = <0 109 0>; + }; + + gpio_2: gpio_rtcm@18890000 { + #gpio-cells = <2>; + #interrupt-cells = <2>; + compatible = "sirf,atlas7-gpio"; + reg = <0x18890000 0x1000>; + interrupts = <0 47 0>; + gpio-controller; + interrupt-controller; + }; + + rtc-iobg@18840000 { + compatible = "sirf,prima2-rtciobg", + "sirf-prima2-rtciobg-bus", + "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x18840000 0x1000>; + + sysrtc@2000 { + compatible = "sirf,prima2-sysrtc"; + reg = <0x2000 0x100>; + interrupts = <0 52 0>; + }; + pwrc@3000 { + compatible = "sirf,atlas7-pwrc"; + reg = <0x3000 0x100>; + }; + }; + + qspi: flash@188B0000 { + cell-index = <0>; + compatible = "sirf,atlas7-qspi-nor"; + reg = <0x188B0000 0x10000>; + interrupts = <0 15 0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + retain@0x188D0000 { + compatible = "sirf,atlas7-retain"; + reg = <0x188D0000 0x1000>; + }; + + }; + disp-iobg { + /* lcdc0 */ + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x13100000 0x13100000 0x20000>, + <0x10e10000 0x10e10000 0x10000>; + + lcd@13100000 { + compatible = "sirf,atlas7-lcdc"; + reg = <0x13100000 0x10000>; + interrupts = <0 30 0>; + clocks = <&car 79>; + }; + vpp@13110000 { + compatible = "sirf,atlas7-vpp"; + reg = <0x13110000 0x10000>; + interrupts = <0 31 0>; + clocks = <&car 78>; + resets = <&car 29>; + }; + lvds@10e10000 { + compatible = "sirf,atlas7-lvdsc"; + reg = <0x10e10000 0x10000>; + interrupts = <0 64 0>; + clocks = <&car 54>; + resets = <&car 29>; + }; + + }; + + graphics-iobg { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x12000000 0x12000000 0x1000000>; + + graphics@12000000 { + compatible = "powervr,sgx531"; + reg = <0x12000000 0x1000000>; + interrupts = <0 6 0>; + clocks = <&car 126>; + }; + }; + }; +}; -- cgit v1.2.3-59-g8ed1b From 753b9c9cfdfeae57f956c55e1ccdfcf2d90e6196 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 14 Jan 2015 12:12:59 +0100 Subject: ARM: shmobile: Add DT bindings for Renesas memory controllers Add DT bindings for Renesas R-Mobile and SH-Mobile memory controllers. Currently memory controller device nodes are used only to reference PM domains, and prevent these PM domains from being powered down, which would crash the system. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- .../renesas-memory-controllers.txt | 44 ++++++++++++++++++++++ 1 file changed, 44 insertions(+) create mode 100644 Documentation/devicetree/bindings/memory-controllers/renesas-memory-controllers.txt (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/memory-controllers/renesas-memory-controllers.txt b/Documentation/devicetree/bindings/memory-controllers/renesas-memory-controllers.txt new file mode 100644 index 000000000000..c64b7925cd09 --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/renesas-memory-controllers.txt @@ -0,0 +1,44 @@ +DT bindings for Renesas R-Mobile and SH-Mobile memory controllers +================================================================= + +Renesas R-Mobile and SH-Mobile SoCs contain one or more memory controllers. +These memory controllers differ from one SoC variant to another, and are called +by different names ("DDR Bus Controller (DBSC)", "DDR3 Bus State Controller +(DBSC3)", "SDRAM Bus State Controller (SBSC)"). + +Currently memory controller device nodes are used only to reference PM +domains, and prevent these PM domains from being powered down, which would +crash the system. + +As there exist no actual drivers for these controllers yet, these bindings +should be considered EXPERIMENTAL for now. + +Required properties: + - compatible: Must be one of the following SoC-specific values: + - "renesas,dbsc-r8a73a4" (R-Mobile APE6) + - "renesas,dbsc3-r8a7740" (R-Mobile A1) + - "renesas,sbsc-sh73a0" (SH-Mobile AG5) + - reg: Must contain the base address and length of the memory controller's + registers. + +Optional properties: + - interrupts: Must contain a list of interrupt specifiers for memory + controller interrupts, if available. + - interrupts-names: Must contain a list of interrupt names corresponding to + the interrupts in the interrupts property, if available. + Valid interrupt names are: + - "sec" (secure interrupt) + - "temp" (normal (temperature) interrupt) + - power-domains: Must contain a reference to the PM domain that the memory + controller belongs to, if available. + +Example: + + sbsc1: memory-controller@fe400000 { + compatible = "renesas,sbsc-sh73a0"; + reg = <0xfe400000 0x400>; + interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>, + <0 36 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "sec", "temp"; + power-domains = <&pd_a4bc0>; + }; -- cgit v1.2.3-59-g8ed1b From fbaa5e694a1240c5f6b829b1e17652e4e228ee12 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 14 Jan 2015 13:11:19 +0100 Subject: PM / Domains: R-Mobile SYSC: Document SH-Mobile AG5 (sh73a0) binding SH-Mobile AG5 (sh73a0) can be handled by the existing bindings. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- Documentation/devicetree/bindings/power/renesas,sysc-rmobile.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/power/renesas,sysc-rmobile.txt b/Documentation/devicetree/bindings/power/renesas,sysc-rmobile.txt index 2460476808e9..cc3b1f0a9b1a 100644 --- a/Documentation/devicetree/bindings/power/renesas,sysc-rmobile.txt +++ b/Documentation/devicetree/bindings/power/renesas,sysc-rmobile.txt @@ -12,6 +12,7 @@ Required properties: fallback. Examples with soctypes are: - "renesas,sysc-r8a7740" (R-Mobile A1) + - "renesas,sysc-sh73a0" (SH-Mobile AG5) - reg: Two address start and address range blocks for the device: - The first block refers to the normally accessible registers, - the second block refers to the registers protected by the HPB -- cgit v1.2.3-59-g8ed1b From 76b4701a03472330d1f62144c55eeaba1fed70cf Mon Sep 17 00:00:00 2001 From: Oleksij Rempel Date: Thu, 8 Jan 2015 10:16:46 +0100 Subject: ARM: add alphascale,acc.txt bindings documentation ACC is for AlphaScale Clock Controller. Signed-off-by: Oleksij Rempel Signed-off-by: Olof Johansson --- .../devicetree/bindings/clock/alphascale,acc.txt | 115 +++++++++++++++++++++ 1 file changed, 115 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/alphascale,acc.txt (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/clock/alphascale,acc.txt b/Documentation/devicetree/bindings/clock/alphascale,acc.txt new file mode 100644 index 000000000000..62e67e883e76 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/alphascale,acc.txt @@ -0,0 +1,115 @@ +Alphascale Clock Controller + +The ACC (Alphascale Clock Controller) is responsible of choising proper +clock source, setting deviders and clock gates. + +Required properties for the ACC node: + - compatible: must be "alphascale,asm9260-clock-controller" + - reg: must contain the ACC register base and size + - #clock-cells : shall be set to 1. + +Simple one-cell clock specifier format is used, where the only cell is used +as an index of the clock inside the provider. +It is encouraged to use dt-binding for clock index definitions. SoC specific +dt-binding should be included to the device tree descriptor. For example +Alphascale ASM9260: +#include + +This binding contains two types of clock providers: + _AHB_ - AHB gate; + _SYS_ - adjustable clock source. Not all peripheral have _SYS_ clock provider. +All clock specific details can be found in the SoC documentation. +CLKID_AHB_ROM 0 +CLKID_AHB_RAM 1 +CLKID_AHB_GPIO 2 +CLKID_AHB_MAC 3 +CLKID_AHB_EMI 4 +CLKID_AHB_USB0 5 +CLKID_AHB_USB1 6 +CLKID_AHB_DMA0 7 +CLKID_AHB_DMA1 8 +CLKID_AHB_UART0 9 +CLKID_AHB_UART1 10 +CLKID_AHB_UART2 11 +CLKID_AHB_UART3 12 +CLKID_AHB_UART4 13 +CLKID_AHB_UART5 14 +CLKID_AHB_UART6 15 +CLKID_AHB_UART7 16 +CLKID_AHB_UART8 17 +CLKID_AHB_UART9 18 +CLKID_AHB_I2S0 19 +CLKID_AHB_I2C0 20 +CLKID_AHB_I2C1 21 +CLKID_AHB_SSP0 22 +CLKID_AHB_IOCONFIG 23 +CLKID_AHB_WDT 24 +CLKID_AHB_CAN0 25 +CLKID_AHB_CAN1 26 +CLKID_AHB_MPWM 27 +CLKID_AHB_SPI0 28 +CLKID_AHB_SPI1 29 +CLKID_AHB_QEI 30 +CLKID_AHB_QUADSPI0 31 +CLKID_AHB_CAMIF 32 +CLKID_AHB_LCDIF 33 +CLKID_AHB_TIMER0 34 +CLKID_AHB_TIMER1 35 +CLKID_AHB_TIMER2 36 +CLKID_AHB_TIMER3 37 +CLKID_AHB_IRQ 38 +CLKID_AHB_RTC 39 +CLKID_AHB_NAND 40 +CLKID_AHB_ADC0 41 +CLKID_AHB_LED 42 +CLKID_AHB_DAC0 43 +CLKID_AHB_LCD 44 +CLKID_AHB_I2S1 45 +CLKID_AHB_MAC1 46 + +CLKID_SYS_CPU 47 +CLKID_SYS_AHB 48 +CLKID_SYS_I2S0M 49 +CLKID_SYS_I2S0S 50 +CLKID_SYS_I2S1M 51 +CLKID_SYS_I2S1S 52 +CLKID_SYS_UART0 53 +CLKID_SYS_UART1 54 +CLKID_SYS_UART2 55 +CLKID_SYS_UART3 56 +CLKID_SYS_UART4 56 +CLKID_SYS_UART5 57 +CLKID_SYS_UART6 58 +CLKID_SYS_UART7 59 +CLKID_SYS_UART8 60 +CLKID_SYS_UART9 61 +CLKID_SYS_SPI0 62 +CLKID_SYS_SPI1 63 +CLKID_SYS_QUADSPI 64 +CLKID_SYS_SSP0 65 +CLKID_SYS_NAND 66 +CLKID_SYS_TRACE 67 +CLKID_SYS_CAMM 68 +CLKID_SYS_WDT 69 +CLKID_SYS_CLKOUT 70 +CLKID_SYS_MAC 71 +CLKID_SYS_LCD 72 +CLKID_SYS_ADCANA 73 + +Example of clock consumer with _SYS_ and _AHB_ sinks. +uart4: serial@80010000 { + compatible = "alphascale,asm9260-uart"; + reg = <0x80010000 0x4000>; + clocks = <&acc CLKID_SYS_UART4>, <&acc CLKID_AHB_UART4>; + interrupts = <19>; + status = "disabled"; +}; + +Clock consumer with only one, _AHB_ sink. +timer0: timer@80088000 { + compatible = "alphascale,asm9260-timer"; + reg = <0x80088000 0x4000>; + clocks = <&acc CLKID_AHB_TIMER0>; + interrupts = <29>; +}; + -- cgit v1.2.3-59-g8ed1b From 03ed8470575bad95e8360108183cff5ca0c8e44e Mon Sep 17 00:00:00 2001 From: Oleksij Rempel Date: Thu, 8 Jan 2015 10:16:47 +0100 Subject: add Alphascale to vendor-prefixes.txt this company already provided some products, so it make sense to add them to vendor-prefixes.txt list Signed-off-by: Oleksij Rempel Acked-by: Rob Herring Signed-off-by: Olof Johansson --- Documentation/devicetree/bindings/vendor-prefixes.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index b1df0ad1306c..76a4b3b43e59 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -11,6 +11,7 @@ adi Analog Devices, Inc. aeroflexgaisler Aeroflex Gaisler AB ak Asahi Kasei Corp. allwinner Allwinner Technology Co., Ltd. +alphascale AlphaScale Integrated Circuits Systems, Inc. altr Altera Corp. amcc Applied Micro Circuits Corporation (APM, formally AMCC) amd Advanced Micro Devices (AMD), Inc. -- cgit v1.2.3-59-g8ed1b From 56a9c909d88ab3f66e14c5d21727b8e388a8ec90 Mon Sep 17 00:00:00 2001 From: Wang Long Date: Wed, 24 Dec 2014 03:09:58 +0000 Subject: ARM: dts: Add hip01-ca9x2 dts file Add dts file for Hisilicon hip01 ca9x2 board Signed-off-by: Wang Long Signed-off-by: Wei Xu [olof: Folded in smp enable-method from a different patch] Signed-off-by: Olof Johansson --- .../bindings/arm/hisilicon/hisilicon.txt | 25 +++++ arch/arm/boot/dts/Makefile | 2 + arch/arm/boot/dts/hip01-ca9x2.dts | 51 ++++++++++ arch/arm/boot/dts/hip01.dtsi | 110 +++++++++++++++++++++ 4 files changed, 188 insertions(+) create mode 100644 arch/arm/boot/dts/hip01-ca9x2.dts create mode 100644 arch/arm/boot/dts/hip01.dtsi (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt index f717c7b48603..35b1bd49cfa1 100644 --- a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt +++ b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt @@ -9,6 +9,10 @@ HiP04 D01 Board Required root node properties: - compatible = "hisilicon,hip04-d01"; +HiP01 ca9x2 Board +Required root node properties: + - compatible = "hisilicon,hip01-ca9x2"; + Hisilicon system controller @@ -36,6 +40,27 @@ Example: reboot-offset = <0x4>; }; +----------------------------------------------------------------------- +Hisilicon HiP01 system controller + +Required properties: +- compatible : "hisilicon,hip01-sysctrl" +- reg : Register address and size + +The HiP01 system controller is mostly compatible with hisilicon +system controller,but it has some specific control registers for +HIP01 SoC family, such as slave core boot, and also some same +registers located at different offset. + +Example: + + /* for hip01-ca9x2 */ + sysctrl: system-controller@10000000 { + compatible = "hisilicon,hip01-sysctrl", "hisilicon,sysctrl"; + reg = <0x10000000 0x1000>; + reboot-offset = <0x4>; + }; + ----------------------------------------------------------------------- Hisilicon CPU controller diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 31065cc01df3..293b80e196b7 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -123,6 +123,8 @@ dtb-$(CONFIG_ARCH_HIX5HD2) += \ dtb-$(CONFIG_ARCH_HIGHBANK) += \ highbank.dtb \ ecx-2000.dtb +dtb-$(CONFIG_ARCH_HIP01) += \ + hip01-ca9x2.dtb dtb-$(CONFIG_ARCH_HIP04) += \ hip04-d01.dtb dtb-$(CONFIG_ARCH_INTEGRATOR) += \ diff --git a/arch/arm/boot/dts/hip01-ca9x2.dts b/arch/arm/boot/dts/hip01-ca9x2.dts new file mode 100644 index 000000000000..eca5e42770fe --- /dev/null +++ b/arch/arm/boot/dts/hip01-ca9x2.dts @@ -0,0 +1,51 @@ +/* + * Hisilicon Ltd. HiP01 SoC + * + * Copyright (C) 2014 Hisilicon Ltd. + * Copyright (C) 2014 Huawei Ltd. + * + * Author: Wang Long + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/dts-v1/; + +/* First 8KB reserved for secondary core boot */ +/memreserve/ 0x80000000 0x00002000; + +#include "hip01.dtsi" + +/ { + model = "Hisilicon HIP01 Development Board"; + compatible = "hisilicon,hip01-ca9x2", "hisilicon,hip01"; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + enable-method = "hisilicon,hip01-smp"; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <1>; + }; + }; + + memory { + device_type = "memory"; + reg = <0x80000000 0x80000000>; + }; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/hip01.dtsi b/arch/arm/boot/dts/hip01.dtsi new file mode 100644 index 000000000000..33130f8461c3 --- /dev/null +++ b/arch/arm/boot/dts/hip01.dtsi @@ -0,0 +1,110 @@ +/* + * Hisilicon Ltd. HiP01 SoC + * + * Copyright (c) 2014 Hisilicon Ltd. + * Copyright (c) 2014 Huawei Ltd. + * + * Author: Wang Long + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "skeleton.dtsi" + +/ { + interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; + + gic: interrupt-controller@1e001000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x1a001000 0x1000>, <0x1a000100 0x1000>; + }; + + hisi_refclk144mhz: refclk144mkhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <144000000>; + clock-output-names = "hisi:refclk144khz"; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + interrupt-parent = <&gic>; + ranges = <0 0x10000000 0x20000000>; + + amba { + #address-cells = <1>; + #size-cells = <1>; + compatible = "arm,amba-bus"; + ranges; + + uart0: uart@10001000 { + compatible = "snps,dw-apb-uart"; + reg = <0x10001000 0x1000>; + clocks = <&hisi_refclk144mhz>; + clock-names = "apb_pclk"; + reg-shift = <2>; + interrupts = <0 32 4>; + status = "disabled"; + }; + + uart1: uart@10002000 { + compatible = "snps,dw-apb-uart"; + reg = <0x10002000 0x1000>; + clocks = <&hisi_refclk144mhz>; + clock-names = "apb_pclk"; + reg-shift = <2>; + interrupts = <0 33 4>; + status = "disabled"; + }; + + uart2: uart@10003000 { + compatible = "snps,dw-apb-uart"; + reg = <0x10003000 0x1000>; + clocks = <&hisi_refclk144mhz>; + clock-names = "apb_pclk"; + reg-shift = <2>; + interrupts = <0 34 4>; + status = "disabled"; + }; + + uart3: uart@10006000 { + compatible = "snps,dw-apb-uart"; + reg = <0x10006000 0x1000>; + clocks = <&hisi_refclk144mhz>; + clock-names = "apb_pclk"; + reg-shift = <2>; + interrupts = <0 4 4>; + status = "disabled"; + }; + }; + + system-controller@10000000 { + compatible = "hisilicon,hip01-sysctrl", "hisilicon,sysctrl"; + reg = <0x10000000 0x1000>; + reboot-offset = <0x4>; + }; + + global_timer@0a000200 { + compatible = "arm,cortex-a9-global-timer"; + reg = <0x0a000200 0x100>; + interrupts = <1 11 0xf04>; + clocks = <&hisi_refclk144mhz>; + }; + + local_timer@0a000600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0x0a000600 0x100>; + interrupts = <1 13 0xf04>; + clocks = <&hisi_refclk144mhz>; + }; + }; +}; -- cgit v1.2.3-59-g8ed1b From 7636bda61aacbef955c7f0088f7c3cb0875dc4a9 Mon Sep 17 00:00:00 2001 From: Christoph Junghans Date: Tue, 13 Jan 2015 21:49:29 -0700 Subject: ARM: Kirkwood: Added support for pogoplug e02 (pink/gray) The pogoplug differs from the SheevaPlug only by a few details, but especially in the led assignments. This patch was tested under Gentoo Linux and is based on dts files from Arch Linux ARM and OpenWrt. Suggested-by: Felix Kaechele Suggested-by: Oleg Rakhmanov Signed-off-by: Christoph Junghans [Andrew Lunn : Fixed subject line] Signed-off-by: Andrew Lunn --- .../devicetree/bindings/vendor-prefixes.txt | 1 + arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/kirkwood-pogo_e02.dts | 134 +++++++++++++++++++++ 3 files changed, 136 insertions(+) create mode 100644 arch/arm/boot/dts/kirkwood-pogo_e02.dts (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index b1df0ad1306c..61888db9ee72 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -34,6 +34,7 @@ chipidea Chipidea, Inc chrp Common Hardware Reference Platform chunghwa Chunghwa Picture Tubes Ltd. cirrus Cirrus Logic, Inc. +cloudengines Cloud Engines, Inc. cnm Chips&Media, Inc. cortina Cortina Systems, Inc. crystalfontz Crystalfontz America, Inc. diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 17ee1d6a0ac0..968bc7a9a43b 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -161,6 +161,7 @@ dtb-$(CONFIG_MACH_KIRKWOOD) += kirkwood-b3.dtb \ kirkwood-openrd-base.dtb \ kirkwood-openrd-client.dtb \ kirkwood-openrd-ultimate.dtb \ + kirkwood-pogo_e02.dtb \ kirkwood-rd88f6192.dtb \ kirkwood-rd88f6281-z0.dtb \ kirkwood-rd88f6281-a.dtb \ diff --git a/arch/arm/boot/dts/kirkwood-pogo_e02.dts b/arch/arm/boot/dts/kirkwood-pogo_e02.dts new file mode 100644 index 000000000000..a190080c9c4f --- /dev/null +++ b/arch/arm/boot/dts/kirkwood-pogo_e02.dts @@ -0,0 +1,134 @@ +/* + * kirkwood-pogo_e02.dts - Device tree file for Pogoplug E02 + * + * Copyright (C) 2015 Christoph Junghans + * + * based on information of dts files from + * Arch Linux ARM by Oleg Rakhmanov + * OpenWrt by Felix Kaechele + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +/dts-v1/; + +#include "kirkwood.dtsi" +#include "kirkwood-6281.dtsi" + +/ { + model = "Cloud Engines Pogoplug E02"; + compatible = "cloudengines,pogoe02", "marvell,kirkwood-88f6281", + "marvell,kirkwood"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x10000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200n8"; + stdout-path = &uart0; + }; + + gpio-leds { + compatible = "gpio-leds"; + + health { + label = "pogo_e02:green:health"; + gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; + default-state = "keep"; + }; + fault { + label = "pogo_e02:orange:fault"; + gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; + }; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&pmx_usb_power_enable>; + pinctrl-names = "default"; + + usb_power: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "USB Power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio0 29 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&pinctrl { + pinctrl-0 = < &pmx_usb_power_enable &pmx_led_orange + &pmx_led_green >; + pinctrl-names = "default"; + + pmx_usb_power_enable: pmx-usb-power-enable { + marvell,pins = "mpp29"; + marvell,function = "gpio"; + }; + + pmx_led_green: pmx-led-green { + marvell,pins = "mpp48"; + marvell,function = "gpio"; + }; + + pmx_led_orange: pmx-led-orange { + marvell,pins = "mpp49"; + marvell,function = "gpio"; + }; +}; + +&uart0 { + status = "okay"; +}; + +&nand { + chip-delay = <40>; + status = "okay"; + + partition@0 { + label = "u-boot"; + reg = <0x0000000 0x100000>; + read-only; + }; + + partition@100000 { + label = "uImage"; + reg = <0x0100000 0x400000>; + }; + + partition@500000 { + label = "pogoplug"; + reg = <0x0500000 0x2000000>; + }; + + partition@2500000 { + label = "root"; + reg = <0x02500000 0x5b00000>; + }; +}; + +&mdio { + status = "okay"; + + ethphy0: ethernet-phy@0 { + reg = <0>; + }; +}; + +ð0 { + status = "okay"; + ethernet0-port@0 { + phy-handle = <ðphy0>; + }; +}; -- cgit v1.2.3-59-g8ed1b From 0da65870413630339399eb691162eef5c27272de Mon Sep 17 00:00:00 2001 From: Marek Szyprowski Date: Sat, 24 Jan 2015 13:16:15 +0900 Subject: ARM: dts: convert to generic power domain bindings for exynos DT This patch replaces all custom samsung,power-domain dt properties with generic power domain bindings and updates documentation Samsung's devices referring to old binding. Suggested-by: Kevin Hilman Signed-off-by: Marek Szyprowski Reviewed-by: Javier Martinez Canillas [javier.martinez@collabora.co.uk: tested on the Exynos5800 Peach Pi Chromebook] Tested-by: Javier Martinez Canillas Signed-off-by: Kukjin Kim --- .../bindings/arm/exynos/power_domain.txt | 2 +- .../devicetree/bindings/iommu/samsung,sysmmu.txt | 6 +++--- .../devicetree/bindings/media/s5p-mfc.txt | 4 ++-- .../devicetree/bindings/video/exynos_dsim.txt | 4 ++-- .../devicetree/bindings/video/samsung-fimd.txt | 4 ++-- arch/arm/boot/dts/exynos3250.dtsi | 11 +++++++--- arch/arm/boot/dts/exynos4.dtsi | 25 ++++++++++++++-------- arch/arm/boot/dts/exynos4210.dtsi | 1 + arch/arm/boot/dts/exynos4415.dtsi | 7 ++++++ arch/arm/boot/dts/exynos4x12.dtsi | 7 +++--- arch/arm/boot/dts/exynos5250.dtsi | 12 ++++++----- arch/arm/boot/dts/exynos5420.dtsi | 10 ++++++--- 12 files changed, 60 insertions(+), 33 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/exynos/power_domain.txt b/Documentation/devicetree/bindings/arm/exynos/power_domain.txt index abde1ea8a119..f4445e5a2bbb 100644 --- a/Documentation/devicetree/bindings/arm/exynos/power_domain.txt +++ b/Documentation/devicetree/bindings/arm/exynos/power_domain.txt @@ -23,7 +23,7 @@ Optional Properties: devices in this power domain. Maximum of 4 pairs (N = 0 to 3) are supported currently. -Node of a device using power domains must have a samsung,power-domain property +Node of a device using power domains must have a power-domains property defined with a phandle to respective power domain. Example: diff --git a/Documentation/devicetree/bindings/iommu/samsung,sysmmu.txt b/Documentation/devicetree/bindings/iommu/samsung,sysmmu.txt index 6fa4c737af23..729543c47046 100644 --- a/Documentation/devicetree/bindings/iommu/samsung,sysmmu.txt +++ b/Documentation/devicetree/bindings/iommu/samsung,sysmmu.txt @@ -45,7 +45,7 @@ Required properties: Exynos4 SoCs, there needs no "master" clock. Exynos5 SoCs, some System MMUs must have "master" clocks. - clocks: Required if the System MMU is needed to gate its clock. -- samsung,power-domain: Required if the System MMU is needed to gate its power. +- power-domains: Required if the System MMU is needed to gate its power. Please refer to the following document: Documentation/devicetree/bindings/arm/exynos/power_domain.txt @@ -54,7 +54,7 @@ Examples: compatible = "samsung,exynos5-gsc"; reg = <0x13e00000 0x1000>; interrupts = <0 85 0>; - samsung,power-domain = <&pd_gsc>; + power-domains = <&pd_gsc>; clocks = <&clock CLK_GSCL0>; clock-names = "gscl"; }; @@ -66,5 +66,5 @@ Examples: interrupts = <2 0>; clock-names = "sysmmu", "master"; clocks = <&clock CLK_SMMU_GSCL0>, <&clock CLK_GSCL0>; - samsung,power-domain = <&pd_gsc>; + power-domains = <&pd_gsc>; }; diff --git a/Documentation/devicetree/bindings/media/s5p-mfc.txt b/Documentation/devicetree/bindings/media/s5p-mfc.txt index 3e3c5f349570..2d5787eac91a 100644 --- a/Documentation/devicetree/bindings/media/s5p-mfc.txt +++ b/Documentation/devicetree/bindings/media/s5p-mfc.txt @@ -28,7 +28,7 @@ Required properties: for DMA contiguous memory allocation and its size. Optional properties: - - samsung,power-domain : power-domain property defined with a phandle + - power-domains : power-domain property defined with a phandle to respective power domain. Example: @@ -38,7 +38,7 @@ mfc: codec@13400000 { compatible = "samsung,mfc-v5"; reg = <0x13400000 0x10000>; interrupts = <0 94 0>; - samsung,power-domain = <&pd_mfc>; + power-domains = <&pd_mfc>; clocks = <&clock 273>; clock-names = "mfc"; }; diff --git a/Documentation/devicetree/bindings/video/exynos_dsim.txt b/Documentation/devicetree/bindings/video/exynos_dsim.txt index ca2b4aacd9af..802aa7ef64e5 100644 --- a/Documentation/devicetree/bindings/video/exynos_dsim.txt +++ b/Documentation/devicetree/bindings/video/exynos_dsim.txt @@ -21,7 +21,7 @@ Required properties: according to DSI host bindings (see MIPI DSI bindings [1]) Optional properties: - - samsung,power-domain: a phandle to DSIM power domain node + - power-domains: a phandle to DSIM power domain node Child nodes: Should contain DSI peripheral nodes (see MIPI DSI bindings [1]). @@ -53,7 +53,7 @@ Example: phy-names = "dsim"; vddcore-supply = <&vusb_reg>; vddio-supply = <&vmipi_reg>; - samsung,power-domain = <&pd_lcd0>; + power-domains = <&pd_lcd0>; #address-cells = <1>; #size-cells = <0>; samsung,pll-clock-frequency = <24000000>; diff --git a/Documentation/devicetree/bindings/video/samsung-fimd.txt b/Documentation/devicetree/bindings/video/samsung-fimd.txt index cf1af6371021..a8bbbde03e79 100644 --- a/Documentation/devicetree/bindings/video/samsung-fimd.txt +++ b/Documentation/devicetree/bindings/video/samsung-fimd.txt @@ -38,7 +38,7 @@ Required properties: property. Must contain "sclk_fimd" and "fimd". Optional Properties: -- samsung,power-domain: a phandle to FIMD power domain node. +- power-domains: a phandle to FIMD power domain node. - samsung,invert-vden: video enable signal is inverted - samsung,invert-vclk: video clock signal is inverted - display-timings: timing settings for FIMD, as described in document [1]. @@ -97,7 +97,7 @@ SoC specific DT entry: interrupts = <11 0>, <11 1>, <11 2>; clocks = <&clock 140>, <&clock 283>; clock-names = "sclk_fimd", "fimd"; - samsung,power-domain = <&pd_lcd0>; + power-domains = <&pd_lcd0>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi index 204a84be5b87..acdf34401015 100644 --- a/arch/arm/boot/dts/exynos3250.dtsi +++ b/arch/arm/boot/dts/exynos3250.dtsi @@ -141,26 +141,31 @@ pd_cam: cam-power-domain@10023C00 { compatible = "samsung,exynos4210-pd"; reg = <0x10023C00 0x20>; + #power-domain-cells = <0>; }; pd_mfc: mfc-power-domain@10023C40 { compatible = "samsung,exynos4210-pd"; reg = <0x10023C40 0x20>; + #power-domain-cells = <0>; }; pd_g3d: g3d-power-domain@10023C60 { compatible = "samsung,exynos4210-pd"; reg = <0x10023C60 0x20>; + #power-domain-cells = <0>; }; pd_lcd0: lcd0-power-domain@10023C80 { compatible = "samsung,exynos4210-pd"; reg = <0x10023C80 0x20>; + #power-domain-cells = <0>; }; pd_isp: isp-power-domain@10023CA0 { compatible = "samsung,exynos4210-pd"; reg = <0x10023CA0 0x20>; + #power-domain-cells = <0>; }; cmu: clock-controller@10030000 { @@ -235,7 +240,7 @@ interrupts = <0 84 0>, <0 85 0>, <0 86 0>; clocks = <&cmu CLK_SCLK_FIMD0>, <&cmu CLK_FIMD0>; clock-names = "sclk_fimd", "fimd"; - samsung,power-domain = <&pd_lcd0>; + power-domains = <&pd_lcd0>; samsung,sysreg = <&sys_reg>; status = "disabled"; }; @@ -245,7 +250,7 @@ reg = <0x11C80000 0x10000>; interrupts = <0 83 0>; samsung,phy-type = <0>; - samsung,power-domain = <&pd_lcd0>; + power-domains = <&pd_lcd0>; phys = <&mipi_phy 1>; phy-names = "dsim"; clocks = <&cmu CLK_DSIM0>, <&cmu CLK_SCLK_MIPI0>; @@ -348,7 +353,7 @@ interrupts = <0 102 0>; clock-names = "mfc", "sclk_mfc"; clocks = <&cmu CLK_MFC>, <&cmu CLK_SCLK_MFC>; - samsung,power-domain = <&pd_mfc>; + power-domains = <&pd_mfc>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi index b8168f1f8139..c5dc2efb99ed 100644 --- a/arch/arm/boot/dts/exynos4.dtsi +++ b/arch/arm/boot/dts/exynos4.dtsi @@ -81,36 +81,43 @@ pd_mfc: mfc-power-domain@10023C40 { compatible = "samsung,exynos4210-pd"; reg = <0x10023C40 0x20>; + #power-domain-cells = <0>; }; pd_g3d: g3d-power-domain@10023C60 { compatible = "samsung,exynos4210-pd"; reg = <0x10023C60 0x20>; + #power-domain-cells = <0>; }; pd_lcd0: lcd0-power-domain@10023C80 { compatible = "samsung,exynos4210-pd"; reg = <0x10023C80 0x20>; + #power-domain-cells = <0>; }; pd_tv: tv-power-domain@10023C20 { compatible = "samsung,exynos4210-pd"; reg = <0x10023C20 0x20>; + #power-domain-cells = <0>; }; pd_cam: cam-power-domain@10023C00 { compatible = "samsung,exynos4210-pd"; reg = <0x10023C00 0x20>; + #power-domain-cells = <0>; }; pd_gps: gps-power-domain@10023CE0 { compatible = "samsung,exynos4210-pd"; reg = <0x10023CE0 0x20>; + #power-domain-cells = <0>; }; pd_gps_alive: gps-alive-power-domain@10023D00 { compatible = "samsung,exynos4210-pd"; reg = <0x10023D00 0x20>; + #power-domain-cells = <0>; }; gic: interrupt-controller@10490000 { @@ -147,7 +154,7 @@ compatible = "samsung,exynos4210-mipi-dsi"; reg = <0x11C80000 0x10000>; interrupts = <0 79 0>; - samsung,power-domain = <&pd_lcd0>; + power-domains = <&pd_lcd0>; phys = <&mipi_phy 1>; phy-names = "dsim"; clocks = <&clock CLK_DSIM0>, <&clock CLK_SCLK_MIPI0>; @@ -172,7 +179,7 @@ interrupts = <0 84 0>; clocks = <&clock CLK_FIMC0>, <&clock CLK_SCLK_FIMC0>; clock-names = "fimc", "sclk_fimc"; - samsung,power-domain = <&pd_cam>; + power-domains = <&pd_cam>; samsung,sysreg = <&sys_reg>; status = "disabled"; }; @@ -183,7 +190,7 @@ interrupts = <0 85 0>; clocks = <&clock CLK_FIMC1>, <&clock CLK_SCLK_FIMC1>; clock-names = "fimc", "sclk_fimc"; - samsung,power-domain = <&pd_cam>; + power-domains = <&pd_cam>; samsung,sysreg = <&sys_reg>; status = "disabled"; }; @@ -194,7 +201,7 @@ interrupts = <0 86 0>; clocks = <&clock CLK_FIMC2>, <&clock CLK_SCLK_FIMC2>; clock-names = "fimc", "sclk_fimc"; - samsung,power-domain = <&pd_cam>; + power-domains = <&pd_cam>; samsung,sysreg = <&sys_reg>; status = "disabled"; }; @@ -205,7 +212,7 @@ interrupts = <0 87 0>; clocks = <&clock CLK_FIMC3>, <&clock CLK_SCLK_FIMC3>; clock-names = "fimc", "sclk_fimc"; - samsung,power-domain = <&pd_cam>; + power-domains = <&pd_cam>; samsung,sysreg = <&sys_reg>; status = "disabled"; }; @@ -217,7 +224,7 @@ clocks = <&clock CLK_CSIS0>, <&clock CLK_SCLK_CSIS0>; clock-names = "csis", "sclk_csis"; bus-width = <4>; - samsung,power-domain = <&pd_cam>; + power-domains = <&pd_cam>; phys = <&mipi_phy 0>; phy-names = "csis"; status = "disabled"; @@ -232,7 +239,7 @@ clocks = <&clock CLK_CSIS1>, <&clock CLK_SCLK_CSIS1>; clock-names = "csis", "sclk_csis"; bus-width = <2>; - samsung,power-domain = <&pd_cam>; + power-domains = <&pd_cam>; phys = <&mipi_phy 2>; phy-names = "csis"; status = "disabled"; @@ -391,7 +398,7 @@ compatible = "samsung,mfc-v5"; reg = <0x13400000 0x10000>; interrupts = <0 94 0>; - samsung,power-domain = <&pd_mfc>; + power-domains = <&pd_mfc>; clocks = <&clock CLK_MFC>, <&clock CLK_SCLK_MFC>; clock-names = "mfc", "sclk_mfc"; status = "disabled"; @@ -641,7 +648,7 @@ interrupts = <11 0>, <11 1>, <11 2>; clocks = <&clock CLK_SCLK_FIMD0>, <&clock CLK_FIMD0>; clock-names = "sclk_fimd", "fimd"; - samsung,power-domain = <&pd_lcd0>; + power-domains = <&pd_lcd0>; samsung,sysreg = <&sys_reg>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi index bcc9e63c8070..6728aaa2af9d 100644 --- a/arch/arm/boot/dts/exynos4210.dtsi +++ b/arch/arm/boot/dts/exynos4210.dtsi @@ -79,6 +79,7 @@ pd_lcd1: lcd1-power-domain@10023CA0 { compatible = "samsung,exynos4210-pd"; reg = <0x10023CA0 0x20>; + #power-domain-cells = <0>; }; gic: interrupt-controller@10490000 { diff --git a/arch/arm/boot/dts/exynos4415.dtsi b/arch/arm/boot/dts/exynos4415.dtsi index c1c9b37340d9..2007def1ab43 100644 --- a/arch/arm/boot/dts/exynos4415.dtsi +++ b/arch/arm/boot/dts/exynos4415.dtsi @@ -131,36 +131,43 @@ pd_cam: cam-power-domain@10024000 { compatible = "samsung,exynos4210-pd"; reg = <0x10024000 0x20>; + #power-domain-cells = <0>; }; pd_tv: tv-power-domain@10024020 { compatible = "samsung,exynos4210-pd"; reg = <0x10024020 0x20>; + #power-domain-cells = <0>; }; pd_mfc: mfc-power-domain@10024040 { compatible = "samsung,exynos4210-pd"; reg = <0x10024040 0x20>; + #power-domain-cells = <0>; }; pd_g3d: g3d-power-domain@10024060 { compatible = "samsung,exynos4210-pd"; reg = <0x10024060 0x20>; + #power-domain-cells = <0>; }; pd_lcd0: lcd0-power-domain@10024080 { compatible = "samsung,exynos4210-pd"; reg = <0x10024080 0x20>; + #power-domain-cells = <0>; }; pd_isp0: isp0-power-domain@100240A0 { compatible = "samsung,exynos4210-pd"; reg = <0x100240A0 0x20>; + #power-domain-cells = <0>; }; pd_isp1: isp1-power-domain@100240E0 { compatible = "samsung,exynos4210-pd"; reg = <0x100240E0 0x20>; + #power-domain-cells = <0>; }; cmu: clock-controller@10030000 { diff --git a/arch/arm/boot/dts/exynos4x12.dtsi b/arch/arm/boot/dts/exynos4x12.dtsi index 93b70402e943..da8734e25f50 100644 --- a/arch/arm/boot/dts/exynos4x12.dtsi +++ b/arch/arm/boot/dts/exynos4x12.dtsi @@ -52,6 +52,7 @@ pd_isp: isp-power-domain@10023CA0 { compatible = "samsung,exynos4210-pd"; reg = <0x10023CA0 0x20>; + #power-domain-cells = <0>; }; clock: clock-controller@10030000 { @@ -195,7 +196,7 @@ compatible = "samsung,exynos4212-fimc-lite"; reg = <0x12390000 0x1000>; interrupts = <0 105 0>; - samsung,power-domain = <&pd_isp>; + power-domains = <&pd_isp>; clocks = <&clock CLK_FIMC_LITE0>; clock-names = "flite"; status = "disabled"; @@ -205,7 +206,7 @@ compatible = "samsung,exynos4212-fimc-lite"; reg = <0x123A0000 0x1000>; interrupts = <0 106 0>; - samsung,power-domain = <&pd_isp>; + power-domains = <&pd_isp>; clocks = <&clock CLK_FIMC_LITE1>; clock-names = "flite"; status = "disabled"; @@ -215,7 +216,7 @@ compatible = "samsung,exynos4212-fimc-is", "simple-bus"; reg = <0x12000000 0x260000>; interrupts = <0 90 0>, <0 95 0>; - samsung,power-domain = <&pd_isp>; + power-domains = <&pd_isp>; clocks = <&clock CLK_FIMC_LITE0>, <&clock CLK_FIMC_LITE1>, <&clock CLK_PPMUISPX>, <&clock CLK_PPMUISPMX>, diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi index 0a229fcd7acf..2b5a62c91d26 100644 --- a/arch/arm/boot/dts/exynos5250.dtsi +++ b/arch/arm/boot/dts/exynos5250.dtsi @@ -93,11 +93,13 @@ pd_gsc: gsc-power-domain@10044000 { compatible = "samsung,exynos4210-pd"; reg = <0x10044000 0x20>; + #power-domain-cells = <0>; }; pd_mfc: mfc-power-domain@10044040 { compatible = "samsung,exynos4210-pd"; reg = <0x10044040 0x20>; + #power-domain-cells = <0>; }; clock: clock-controller@10010000 { @@ -222,7 +224,7 @@ compatible = "samsung,mfc-v6"; reg = <0x11000000 0x10000>; interrupts = <0 96 0>; - samsung,power-domain = <&pd_mfc>; + power-domains = <&pd_mfc>; clocks = <&clock CLK_MFC>; clock-names = "mfc"; }; @@ -682,7 +684,7 @@ compatible = "samsung,exynos5-gsc"; reg = <0x13e00000 0x1000>; interrupts = <0 85 0>; - samsung,power-domain = <&pd_gsc>; + power-domains = <&pd_gsc>; clocks = <&clock CLK_GSCL0>; clock-names = "gscl"; }; @@ -691,7 +693,7 @@ compatible = "samsung,exynos5-gsc"; reg = <0x13e10000 0x1000>; interrupts = <0 86 0>; - samsung,power-domain = <&pd_gsc>; + power-domains = <&pd_gsc>; clocks = <&clock CLK_GSCL1>; clock-names = "gscl"; }; @@ -700,7 +702,7 @@ compatible = "samsung,exynos5-gsc"; reg = <0x13e20000 0x1000>; interrupts = <0 87 0>; - samsung,power-domain = <&pd_gsc>; + power-domains = <&pd_gsc>; clocks = <&clock CLK_GSCL2>; clock-names = "gscl"; }; @@ -709,7 +711,7 @@ compatible = "samsung,exynos5-gsc"; reg = <0x13e30000 0x1000>; interrupts = <0 88 0>; - samsung,power-domain = <&pd_gsc>; + power-domains = <&pd_gsc>; clocks = <&clock CLK_GSCL3>; clock-names = "gscl"; }; diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index 517e50f6760b..03ef2481c640 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -178,7 +178,7 @@ interrupts = <0 96 0>; clocks = <&clock CLK_MFC>; clock-names = "mfc"; - samsung,power-domain = <&mfc_pd>; + power-domains = <&mfc_pd>; }; mmc_0: mmc@12200000 { @@ -250,11 +250,13 @@ gsc_pd: power-domain@10044000 { compatible = "samsung,exynos4210-pd"; reg = <0x10044000 0x20>; + #power-domain-cells = <0>; }; isp_pd: power-domain@10044020 { compatible = "samsung,exynos4210-pd"; reg = <0x10044020 0x20>; + #power-domain-cells = <0>; }; mfc_pd: power-domain@10044060 { @@ -263,11 +265,13 @@ clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MOUT_SW_ACLK333>, <&clock CLK_MOUT_USER_ACLK333>; clock-names = "oscclk", "pclk0", "clk0"; + #power-domain-cells = <0>; }; msc_pd: power-domain@10044120 { compatible = "samsung,exynos4210-pd"; reg = <0x10044120 0x20>; + #power-domain-cells = <0>; }; pinctrl_0: pinctrl@13400000 { @@ -730,7 +734,7 @@ interrupts = <0 85 0>; clocks = <&clock CLK_GSCL0>; clock-names = "gscl"; - samsung,power-domain = <&gsc_pd>; + power-domains = <&gsc_pd>; }; gsc_1: video-scaler@13e10000 { @@ -739,7 +743,7 @@ interrupts = <0 86 0>; clocks = <&clock CLK_GSCL1>; clock-names = "gscl"; - samsung,power-domain = <&gsc_pd>; + power-domains = <&gsc_pd>; }; pmu_system_controller: system-controller@10040000 { -- cgit v1.2.3-59-g8ed1b From 37e73ac467fb92180b9784bf6e74d1ff1d03ef69 Mon Sep 17 00:00:00 2001 From: FUKAUMI Naoki Date: Sun, 25 Jan 2015 21:39:34 +0900 Subject: dt-bindings: add vendor prefix and root compatible property for Rockchip boards This adds vendor prefix and root compatible property for following boards - Firefly, Firefly-RK3288 boards (both beta and mass production version) - ChipSPARK, Rayeager PX2 board PX2 SoC is fully compatible with RK3066. Signed-off-by: FUKAUMI Naoki Signed-off-by: Heiko Stuebner --- Documentation/devicetree/bindings/arm/rockchip.txt | 10 ++++++++++ Documentation/devicetree/bindings/vendor-prefixes.txt | 2 ++ 2 files changed, 12 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/rockchip.txt b/Documentation/devicetree/bindings/arm/rockchip.txt index eaa3d1a0eb05..6809e4e51ed2 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.txt +++ b/Documentation/devicetree/bindings/arm/rockchip.txt @@ -9,6 +9,16 @@ Rockchip platforms device tree bindings Required root node properties: - compatible = "mundoreader,bq-curie2", "rockchip,rk3066a"; +- ChipSPARK Rayeager PX2 board: + Required root node properties: + - compatible = "chipspark,rayeager-px2", "rockchip,rk3066a"; + - Radxa Rock board: Required root node properties: - compatible = "radxa,rock", "rockchip,rk3188"; + +- Firefly Firefly-RK3288 board: + Required root node properties: + - compatible = "firefly,firefly-rk3288", "rockchip,rk3288"; + or + - compatible = "firefly,firefly-rk3288-beta", "rockchip,rk3288"; diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index b1df0ad1306c..ad6aade2ee33 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -31,6 +31,7 @@ capella Capella Microsystems, Inc cavium Cavium, Inc. cdns Cadence Design Systems Inc. chipidea Chipidea, Inc +chipspark ChipSPARK chrp Common Hardware Reference Platform chunghwa Chunghwa Picture Tubes Ltd. cirrus Cirrus Logic, Inc. @@ -58,6 +59,7 @@ eukrea EukrĂ©a Electromatique everest Everest Semiconductor Co. Ltd. excito Excito fcs Fairchild Semiconductor +firefly Firefly fsl Freescale Semiconductor GEFanuc GE Fanuc Intelligent Platforms Embedded Systems, Inc. gef GE Fanuc Intelligent Platforms Embedded Systems, Inc. -- cgit v1.2.3-59-g8ed1b From f32063c517b4e2773ba2df53934172dab60485a8 Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Mon, 29 Dec 2014 13:08:40 +0100 Subject: dt: atmel_ac97c: Add device tree documentation This adds the bindings for AC97 controller device tree support. Signed-off-by: Alexander Stein Acked-By Alexandre Belloni Signed-off-by: Nicolas Ferre --- .../devicetree/bindings/sound/atmel_ac97c.txt | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) create mode 100644 Documentation/devicetree/bindings/sound/atmel_ac97c.txt (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/sound/atmel_ac97c.txt b/Documentation/devicetree/bindings/sound/atmel_ac97c.txt new file mode 100644 index 000000000000..b151bd902ce3 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/atmel_ac97c.txt @@ -0,0 +1,20 @@ +* Atmel AC97 controller + +Required properties: + - compatible: "atmel,at91sam9263-ac97c" + - reg: Address and length of the register set for the device + - interrupts: Should contain AC97 interrupt + - ac97-gpios: Please refer to soc-ac97link.txt, only ac97-reset is used +Optional properties: + - pinctrl-names, pinctrl-0: Please refer to pinctrl-bindings.txt + +Example: +sound@fffa0000 { + compatible = "atmel,at91sam9263-ac97c"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ac97>; + reg = <0xfffa0000 0x4000>; + interrupts = <18 IRQ_TYPE_LEVEL_HIGH 5>; + + ac97-gpios = <&pioB 0 0 &pioB 2 0 &pioC 29 GPIO_ACTIVE_LOW>; +}; -- cgit v1.2.3-59-g8ed1b From 58f1fdea0b059c9cc8a3cb76109e6e0bf313e304 Mon Sep 17 00:00:00 2001 From: Baruch Siach Date: Wed, 14 Jan 2015 10:40:33 +0200 Subject: ARM: devicetree: document supported Conexant Digicolor SoC Of the Digicolor SoCs series only CX92755 is currently supported. Acked-by: Arnd Bergmann Signed-off-by: Baruch Siach Signed-off-by: Olof Johansson --- Documentation/devicetree/bindings/arm/digicolor.txt | 6 ++++++ 1 file changed, 6 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/digicolor.txt (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/digicolor.txt b/Documentation/devicetree/bindings/arm/digicolor.txt new file mode 100644 index 000000000000..658553f40b23 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/digicolor.txt @@ -0,0 +1,6 @@ +Conexant Digicolor Platforms Device Tree Bindings + +Each device tree must specify which Conexant Digicolor SoC it uses. +Must be the following compatible string: + + cnxt,cx92755 -- cgit v1.2.3-59-g8ed1b From ce4ee5806f15d171be4ba7f54d01fedb49baea66 Mon Sep 17 00:00:00 2001 From: Bhupesh Sharma Date: Sun, 25 Jan 2015 02:42:49 +0530 Subject: Documentation: DT: Add bindings for FSL NS16550A UART This patch addss the device-tree documentation for Freescale's NS16550 UART (also called DUART). There is a specific errata fix required in FSL NS16550 UART which ensures that an random interrupt storm is not observed when a break is provided as an input to the UART. Signed-off-by: Bhupesh Sharma Acked-by: Mark Rutland Signed-off-by: Olof Johansson --- Documentation/devicetree/bindings/serial/of-serial.txt | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/serial/of-serial.txt b/Documentation/devicetree/bindings/serial/of-serial.txt index b52b98234b9b..93e249c78060 100644 --- a/Documentation/devicetree/bindings/serial/of-serial.txt +++ b/Documentation/devicetree/bindings/serial/of-serial.txt @@ -16,6 +16,7 @@ Required properties: - "altr,16550-FIFO64" - "altr,16550-FIFO128" - "fsl,16550-FIFO64" + - "fsl,ns16550" - "serial" if the port type is unknown. - reg : offset and length of the register set for the device. - interrupts : should contain uart interrupt. @@ -40,6 +41,17 @@ Optional properties: driver is allowed to detect support for the capability even without this property. +Note: +* fsl,ns16550: + ------------ + Freescale DUART is very similar to the PC16552D (and to a + pair of NS16550A), albeit with some nonstandard behavior such as + erratum A-004737 (relating to incorrect BRK handling). + + Represents a single port that is compatible with the DUART found + on many Freescale chips (examples include mpc8349, mpc8548, + mpc8641d, p4080 and ls2085a). + Example: uart@80230000 { -- cgit v1.2.3-59-g8ed1b From b4b3c85573079159d819fffab83316a286de5f45 Mon Sep 17 00:00:00 2001 From: Bhupesh Sharma Date: Sun, 25 Jan 2015 02:42:50 +0530 Subject: Documentation: DT: Add entry for FSL LS2085A SoC and Simulator model This patch adds a devicetree binding documentation for FSL's LS2085A SoC and Simulator model. Signed-off-by: Bhupesh Sharma Signed-off-by: Olof Johansson --- Documentation/devicetree/bindings/arm/fsl.txt | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/fsl.txt b/Documentation/devicetree/bindings/arm/fsl.txt index c830b5b65882..a5462b6b3c30 100644 --- a/Documentation/devicetree/bindings/arm/fsl.txt +++ b/Documentation/devicetree/bindings/arm/fsl.txt @@ -124,3 +124,11 @@ Example: compatible = "fsl,ls1021a-dcfg"; reg = <0x0 0x1ee0000 0x0 0x10000>; }; + +Freescale LS2085A SoC Device Tree Bindings +------------------------------------------ + +LS2085A ARMv8 based Simulator model +Required root node properties: + - compatible = "fsl,ls2085a-simu", "fsl,ls2085a"; + -- cgit v1.2.3-59-g8ed1b From a5565a217520d12ef8d6349456a63592875999b3 Mon Sep 17 00:00:00 2001 From: Bhupesh Sharma Date: Sun, 25 Jan 2015 02:42:51 +0530 Subject: Documentation: DT: Add entry for FSL Management Complex This patch adds a devicetree binding documentation for FSL's Management Complex. Management Complex is a hardware resource manager that manages specialized hardware objects used in network-oriented packet processing applications Signed-off-by: Bhupesh Sharma Signed-off-by: Stuart Yoder Signed-off-by: J. German Rivera Signed-off-by: Olof Johansson --- .../devicetree/bindings/misc/fsl,qoriq-mc.txt | 40 ++++++++++++++++++++++ 1 file changed, 40 insertions(+) create mode 100644 Documentation/devicetree/bindings/misc/fsl,qoriq-mc.txt (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/misc/fsl,qoriq-mc.txt b/Documentation/devicetree/bindings/misc/fsl,qoriq-mc.txt new file mode 100644 index 000000000000..c7a26ca8da12 --- /dev/null +++ b/Documentation/devicetree/bindings/misc/fsl,qoriq-mc.txt @@ -0,0 +1,40 @@ +* Freescale Management Complex + +The Freescale Management Complex (fsl-mc) is a hardware resource +manager that manages specialized hardware objects used in +network-oriented packet processing applications. After the fsl-mc +block is enabled, pools of hardware resources are available, such as +queues, buffer pools, I/O interfaces. These resources are building +blocks that can be used to create functional hardware objects/devices +such as network interfaces, crypto accelerator instances, L2 switches, +etc. + +Required properties: + + - compatible + Value type: + Definition: Must be "fsl,qoriq-mc". A Freescale Management Complex + compatible with this binding must have Block Revision + Registers BRR1 and BRR2 at offset 0x0BF8 and 0x0BFC in + the MC control register region. + + - reg + Value type: + Definition: A standard property. Specifies one or two regions + defining the MC's registers: + + -the first region is the command portal for the + this machine and must always be present + + -the second region is the MC control registers. This + region may not be present in some scenarios, such + as in the device tree presented to a virtual machine. + +Example: + + fsl_mc: fsl-mc@80c000000 { + compatible = "fsl,qoriq-mc"; + reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */ + <0x00000000 0x08340000 0 0x40000>; /* MC control reg */ + }; + -- cgit v1.2.3-59-g8ed1b