From fd6beeb37e04a274a807d4d00601202ea90e5e73 Mon Sep 17 00:00:00 2001 From: Gwenhael Goavec-Merou Date: Mon, 11 Nov 2013 18:56:49 +0100 Subject: ARM: imx27-apf27dev: Add sdhci support Signed-off-by: Gwenhael Goavec-Merou Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx27-apf27dev.dts | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch/arm/boot/dts/imx27-apf27dev.dts') diff --git a/arch/arm/boot/dts/imx27-apf27dev.dts b/arch/arm/boot/dts/imx27-apf27dev.dts index 47c8c26012e4..7d908777ca5b 100644 --- a/arch/arm/boot/dts/imx27-apf27dev.dts +++ b/arch/arm/boot/dts/imx27-apf27dev.dts @@ -89,3 +89,9 @@ &i2c2 { status = "okay"; }; + +&sdhci2 { + bus-width = <4>; + cd-gpios = <&gpio3 14 0>; + status = "okay"; +}; -- cgit v1.2.3-59-g8ed1b From d1572f1f174d6ed12d5fec8ce1dbce4de2fefe2a Mon Sep 17 00:00:00 2001 From: Gwenhael Goavec-Merou Date: Mon, 25 Nov 2013 08:45:44 +0100 Subject: ARM: dts: imx27-apf27dev: fix display size Signed-off-by: Gwenhael Goavec-Merou Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx27-apf27dev.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm/boot/dts/imx27-apf27dev.dts') diff --git a/arch/arm/boot/dts/imx27-apf27dev.dts b/arch/arm/boot/dts/imx27-apf27dev.dts index 7d908777ca5b..9197329a2c93 100644 --- a/arch/arm/boot/dts/imx27-apf27dev.dts +++ b/arch/arm/boot/dts/imx27-apf27dev.dts @@ -22,10 +22,10 @@ bits-per-pixel = <16>; /* non-standard but required */ fsl,pcr = <0xfae80083>; /* non-standard but required */ display-timings { - timing0: 640x480 { + timing0: 800x480 { clock-frequency = <33000033>; hactive = <800>; - vactive = <640>; + vactive = <480>; hback-porch = <96>; hfront-porch = <96>; vback-porch = <20>; -- cgit v1.2.3-59-g8ed1b From 392aa4bf688a2d54f14e53a759b8b4e51c6c9f5c Mon Sep 17 00:00:00 2001 From: Gwenhael Goavec-Merou Date: Thu, 28 Nov 2013 08:19:32 +0100 Subject: ARM: dts: imx27: imx27-apf27dev: add pinctrl for cspi, i2c, sdhc and framebuffer Signed-off-by: Gwenhael Goavec-Merou Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx27-apf27dev.dts | 89 ++++++++++++++++++++++++++++++++++++ 1 file changed, 89 insertions(+) (limited to 'arch/arm/boot/dts/imx27-apf27dev.dts') diff --git a/arch/arm/boot/dts/imx27-apf27dev.dts b/arch/arm/boot/dts/imx27-apf27dev.dts index 9197329a2c93..9e5a61ef34b6 100644 --- a/arch/arm/boot/dts/imx27-apf27dev.dts +++ b/arch/arm/boot/dts/imx27-apf27dev.dts @@ -60,6 +60,8 @@ &cspi1 { fsl,spi-num-chipselects = <1>; cs-gpios = <&gpio4 28 1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_cspi1>; status = "okay"; }; @@ -67,17 +69,23 @@ fsl,spi-num-chipselects = <3>; cs-gpios = <&gpio4 21 1>, <&gpio4 27 1>, <&gpio2 17 1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_cspi2>; status = "okay"; }; &fb { display = <&display>; fsl,dmacr = <0x00020010>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_imxfb1>; status = "okay"; }; &i2c1 { clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; status = "okay"; rtc@68 { @@ -87,11 +95,92 @@ }; &i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; status = "okay"; }; +&iomuxc { + imx27-apf27dev { + pinctrl_cspi1: cspi1grp { + fsl,pins = < + MX27_PAD_CSPI1_MISO__CSPI1_MISO 0x0 + MX27_PAD_CSPI1_MOSI__CSPI1_MOSI 0x0 + MX27_PAD_CSPI1_SCLK__CSPI1_SCLK 0x0 + >; + }; + + pinctrl_cspi2: cspi2grp { + fsl,pins = < + MX27_PAD_CSPI2_MISO__CSPI2_MISO 0x0 + MX27_PAD_CSPI2_MOSI__CSPI2_MOSI 0x0 + MX27_PAD_CSPI2_SCLK__CSPI2_SCLK 0x0 + >; + }; + + pinctrl_imxfb1: imxfbgrp { + fsl,pins = < + MX27_PAD_CLS__CLS 0x0 + MX27_PAD_CONTRAST__CONTRAST 0x0 + MX27_PAD_LD0__LD0 0x0 + MX27_PAD_LD1__LD1 0x0 + MX27_PAD_LD2__LD2 0x0 + MX27_PAD_LD3__LD3 0x0 + MX27_PAD_LD4__LD4 0x0 + MX27_PAD_LD5__LD5 0x0 + MX27_PAD_LD6__LD6 0x0 + MX27_PAD_LD7__LD7 0x0 + MX27_PAD_LD8__LD8 0x0 + MX27_PAD_LD9__LD9 0x0 + MX27_PAD_LD10__LD10 0x0 + MX27_PAD_LD11__LD11 0x0 + MX27_PAD_LD12__LD12 0x0 + MX27_PAD_LD13__LD13 0x0 + MX27_PAD_LD14__LD14 0x0 + MX27_PAD_LD15__LD15 0x0 + MX27_PAD_LD16__LD16 0x0 + MX27_PAD_LD17__LD17 0x0 + MX27_PAD_LSCLK__LSCLK 0x0 + MX27_PAD_OE_ACD__OE_ACD 0x0 + MX27_PAD_PS__PS 0x0 + MX27_PAD_REV__REV 0x0 + MX27_PAD_SPL_SPR__SPL_SPR 0x0 + MX27_PAD_HSYNC__HSYNC 0x0 + MX27_PAD_VSYNC__VSYNC 0x0 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX27_PAD_I2C_DATA__I2C_DATA 0x0 + MX27_PAD_I2C_CLK__I2C_CLK 0x0 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX27_PAD_I2C2_SDA__I2C2_SDA 0x0 + MX27_PAD_I2C2_SCL__I2C2_SCL 0x0 + >; + }; + + pinctrl_sdhc2: sdhc2grp { + fsl,pins = < + MX27_PAD_SD2_CLK__SD2_CLK 0x0 + MX27_PAD_SD2_CMD__SD2_CMD 0x0 + MX27_PAD_SD2_D0__SD2_D0 0x0 + MX27_PAD_SD2_D1__SD2_D1 0x0 + MX27_PAD_SD2_D2__SD2_D2 0x0 + MX27_PAD_SD2_D3__SD2_D3 0x0 + >; + }; + }; +}; + &sdhci2 { bus-width = <4>; cd-gpios = <&gpio3 14 0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sdhc2>; status = "okay"; }; -- cgit v1.2.3-59-g8ed1b From 6ece55b39218d35d44e050d6e47b28a6489edd2b Mon Sep 17 00:00:00 2001 From: Alexander Shiyan Date: Sat, 30 Nov 2013 10:18:04 +0400 Subject: ARM: dts: i.MX27 boards: Switch to use standard GPIO and IRQ flags definitions Signed-off-by: Alexander Shiyan Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx27-apf27dev.dts | 13 +++++++------ arch/arm/boot/dts/imx27-phytec-phycard-s-rdk.dts | 2 +- arch/arm/boot/dts/imx27-phytec-phycard-s-som.dts | 4 ++-- arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts | 9 +++++---- arch/arm/boot/dts/imx27-phytec-phycore-som.dts | 6 +++--- arch/arm/boot/dts/imx27.dtsi | 2 ++ 6 files changed, 20 insertions(+), 16 deletions(-) (limited to 'arch/arm/boot/dts/imx27-apf27dev.dts') diff --git a/arch/arm/boot/dts/imx27-apf27dev.dts b/arch/arm/boot/dts/imx27-apf27dev.dts index 9e5a61ef34b6..3d3ce2c8ae28 100644 --- a/arch/arm/boot/dts/imx27-apf27dev.dts +++ b/arch/arm/boot/dts/imx27-apf27dev.dts @@ -41,7 +41,7 @@ user-key { label = "user"; - gpios = <&gpio6 13 0>; + gpios = <&gpio6 13 GPIO_ACTIVE_HIGH>; linux,code = <276>; /* BTN_EXTRA */ }; }; @@ -51,7 +51,7 @@ user { label = "Heartbeat"; - gpios = <&gpio6 14 0>; + gpios = <&gpio6 14 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; }; @@ -59,7 +59,7 @@ &cspi1 { fsl,spi-num-chipselects = <1>; - cs-gpios = <&gpio4 28 1>; + cs-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_cspi1>; status = "okay"; @@ -67,8 +67,9 @@ &cspi2 { fsl,spi-num-chipselects = <3>; - cs-gpios = <&gpio4 21 1>, <&gpio4 27 1>, - <&gpio2 17 1>; + cs-gpios = <&gpio4 21 GPIO_ACTIVE_LOW>, + <&gpio4 27 GPIO_ACTIVE_LOW>, + <&gpio2 17 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_cspi2>; status = "okay"; @@ -179,7 +180,7 @@ &sdhci2 { bus-width = <4>; - cd-gpios = <&gpio3 14 0>; + cd-gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhc2>; status = "okay"; diff --git a/arch/arm/boot/dts/imx27-phytec-phycard-s-rdk.dts b/arch/arm/boot/dts/imx27-phytec-phycard-s-rdk.dts index c37c74a12e05..04cadfcb32f1 100644 --- a/arch/arm/boot/dts/imx27-phytec-phycard-s-rdk.dts +++ b/arch/arm/boot/dts/imx27-phytec-phycard-s-rdk.dts @@ -124,7 +124,7 @@ }; &sdhci2 { - cd-gpios = <&gpio3 29 0>; + cd-gpios = <&gpio3 29 GPIO_ACTIVE_HIGH>; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx27-phytec-phycard-s-som.dts b/arch/arm/boot/dts/imx27-phytec-phycard-s-som.dts index 0d01d32ba6a1..e51e55077aa0 100644 --- a/arch/arm/boot/dts/imx27-phytec-phycard-s-som.dts +++ b/arch/arm/boot/dts/imx27-phytec-phycard-s-som.dts @@ -24,8 +24,8 @@ &cspi1 { fsl,spi-num-chipselects = <2>; - cs-gpios = <&gpio4 28 0>, - <&gpio4 27 0>; + cs-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>, + <&gpio4 27 GPIO_ACTIVE_HIGH>; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts b/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts index be7667e73a2e..834fde84186e 100644 --- a/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts +++ b/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts @@ -16,7 +16,8 @@ &cspi1 { fsl,spi-num-chipselects = <2>; - cs-gpios = <&gpio4 28 0>, <&gpio4 27 0>; + cs-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>, + <&gpio4 27 GPIO_ACTIVE_LOW>; }; &i2c1 { @@ -65,8 +66,8 @@ &sdhci2 { bus-width = <4>; - cd-gpios = <&gpio3 29 0>; - wp-gpios = <&gpio3 28 0>; + cd-gpios = <&gpio3 29 GPIO_ACTIVE_HIGH>; + wp-gpios = <&gpio3 28 GPIO_ACTIVE_HIGH>; vmmc-supply = <&vmmc1_reg>; status = "okay"; }; @@ -90,7 +91,7 @@ compatible = "nxp,sja1000"; reg = <4 0x00000000 0x00000100>; interrupt-parent = <&gpio5>; - interrupts = <19 0x2>; + interrupts = <19 IRQ_TYPE_EDGE_FALLING>; nxp,external-clock-frequency = <16000000>; nxp,tx-output-config = <0x16>; nxp,no-comparator-bypass; diff --git a/arch/arm/boot/dts/imx27-phytec-phycore-som.dts b/arch/arm/boot/dts/imx27-phytec-phycore-som.dts index 07fd4be8cd36..dd26e1588a58 100644 --- a/arch/arm/boot/dts/imx27-phytec-phycore-som.dts +++ b/arch/arm/boot/dts/imx27-phytec-phycore-som.dts @@ -52,7 +52,7 @@ &cspi1 { fsl,spi-num-chipselects = <1>; - cs-gpios = <&gpio4 28 0>; + cs-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>; status = "okay"; pmic: mc13783@0 { @@ -62,7 +62,7 @@ spi-max-frequency = <20000000>; reg = <0>; interrupt-parent = <&gpio2>; - interrupts = <23 0x4>; + interrupts = <23 IRQ_TYPE_LEVEL_HIGH>; fsl,mc13xxx-uses-adc; fsl,mc13xxx-uses-rtc; @@ -149,7 +149,7 @@ &fec { phy-mode = "mii"; - phy-reset-gpios = <&gpio3 30 0>; + phy-reset-gpios = <&gpio3 30 GPIO_ACTIVE_HIGH>; phy-supply = <®_3v3>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_fec1>; diff --git a/arch/arm/boot/dts/imx27.dtsi b/arch/arm/boot/dts/imx27.dtsi index 672bb8eaa7e6..1af8fcfe552e 100644 --- a/arch/arm/boot/dts/imx27.dtsi +++ b/arch/arm/boot/dts/imx27.dtsi @@ -11,6 +11,8 @@ #include "skeleton.dtsi" #include "imx27-pinfunc.h" +#include +#include / { aliases { -- cgit v1.2.3-59-g8ed1b From 398f460d8b4c4ca8de79fb78fa21937096bbc891 Mon Sep 17 00:00:00 2001 From: Gwenhael Goavec-Merou Date: Tue, 3 Dec 2013 12:10:14 +0100 Subject: ARM: dts: apf27dev: Add pwm support Signed-off-by: Gwenhael Goavec-Merou Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx27-apf27dev.dts | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'arch/arm/boot/dts/imx27-apf27dev.dts') diff --git a/arch/arm/boot/dts/imx27-apf27dev.dts b/arch/arm/boot/dts/imx27-apf27dev.dts index 3d3ce2c8ae28..7c5478e8f36f 100644 --- a/arch/arm/boot/dts/imx27-apf27dev.dts +++ b/arch/arm/boot/dts/imx27-apf27dev.dts @@ -165,6 +165,12 @@ >; }; + pinctrl_pwm: pwmgrp { + fsl,pins = < + MX27_PAD_PWMO__PWMO 0x0 + >; + }; + pinctrl_sdhc2: sdhc2grp { fsl,pins = < MX27_PAD_SD2_CLK__SD2_CLK 0x0 @@ -185,3 +191,8 @@ pinctrl-0 = <&pinctrl_sdhc2>; status = "okay"; }; + +&pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm>; +}; -- cgit v1.2.3-59-g8ed1b From 932693f7099e4448f7ab266aea83b26444dfeb5d Mon Sep 17 00:00:00 2001 From: Gwenhael Goavec-Merou Date: Tue, 3 Dec 2013 12:10:15 +0100 Subject: ARM: dts: imx27-apf27dev: Add pinctrl for cspi, sdhci, leds and keys - add chip-select pinctrl for cspi - add card-detect for sdhci2 - add pinctrl for gpio-leds and gpio-keys Signed-off-by: Gwenhael Goavec-Merou Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx27-apf27dev.dts | 34 +++++++++++++++++++++++++++++++--- 1 file changed, 31 insertions(+), 3 deletions(-) (limited to 'arch/arm/boot/dts/imx27-apf27dev.dts') diff --git a/arch/arm/boot/dts/imx27-apf27dev.dts b/arch/arm/boot/dts/imx27-apf27dev.dts index 7c5478e8f36f..2b6d489dae69 100644 --- a/arch/arm/boot/dts/imx27-apf27dev.dts +++ b/arch/arm/boot/dts/imx27-apf27dev.dts @@ -38,6 +38,8 @@ gpio-keys { compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; user-key { label = "user"; @@ -48,6 +50,8 @@ leds { compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; user { label = "Heartbeat"; @@ -61,7 +65,7 @@ fsl,spi-num-chipselects = <1>; cs-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_cspi1>; + pinctrl-0 = <&pinctrl_cspi1 &pinctrl_cspi1_cs>; status = "okay"; }; @@ -71,7 +75,7 @@ <&gpio4 27 GPIO_ACTIVE_LOW>, <&gpio2 17 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_cspi2>; + pinctrl-0 = <&pinctrl_cspi2 &pinctrl_cspi2_cs>; status = "okay"; }; @@ -111,6 +115,10 @@ >; }; + pinctrl_cspi1_cs: cspi1csgrp { + fsl,pins = ; + }; + pinctrl_cspi2: cspi2grp { fsl,pins = < MX27_PAD_CSPI2_MISO__CSPI2_MISO 0x0 @@ -119,6 +127,22 @@ >; }; + pinctrl_cspi2_cs: cspi2csgrp { + fsl,pins = < + MX27_PAD_CSI_D5__GPIO2_17 0x0 + MX27_PAD_CSPI2_SS0__GPIO4_21 0x0 + MX27_PAD_CSPI1_SS1__GPIO4_27 0x0 + >; + }; + + pinctrl_gpio_leds: gpioledsgrp { + fsl,pins = ; + }; + + pinctrl_gpio_keys: gpiokeysgrp { + fsl,pins = ; + }; + pinctrl_imxfb1: imxfbgrp { fsl,pins = < MX27_PAD_CLS__CLS 0x0 @@ -181,6 +205,10 @@ MX27_PAD_SD2_D3__SD2_D3 0x0 >; }; + + pinctrl_sdhc2_cd: sdhc2cdgrp { + fsl,pins = ; + }; }; }; @@ -188,7 +216,7 @@ bus-width = <4>; cd-gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sdhc2>; + pinctrl-0 = <&pinctrl_sdhc2 &pinctrl_sdhc2_cd>; status = "okay"; }; -- cgit v1.2.3-59-g8ed1b