From d4ea5c61e15adb3995a9944b96e842ce7faaa450 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 4 May 2021 16:41:24 +0200 Subject: ARM: dts: rcar-gen1: Correct internal delay for i2c[123] According to the R-Car M1A and H1 Hardware User's Manuals Rev. 1.00, the LSI internal delay for I2C instances 1 to 3 is 5 ns (typ.), which differs from the default 50 ns as specified for instance 0. Signed-off-by: Geert Uytterhoeven Reviewed-by: Wolfram Sang Link: https://lore.kernel.org/r/1eac63f15a776e492ff8a2d8447c5e1019982dd1.1620138979.git.geert+renesas@glider.be Link: https://lore.kernel.org/r/73c96fd455df82ef04fd1db6d7dd79b4679f6c56.1620138979.git.geert+renesas@glider.be --- arch/arm/boot/dts/r8a7778.dtsi | 3 +++ 1 file changed, 3 insertions(+) (limited to 'arch/arm/boot/dts/r8a7778.dtsi') diff --git a/arch/arm/boot/dts/r8a7778.dtsi b/arch/arm/boot/dts/r8a7778.dtsi index c9f8735860bf..95efbafb0b70 100644 --- a/arch/arm/boot/dts/r8a7778.dtsi +++ b/arch/arm/boot/dts/r8a7778.dtsi @@ -166,6 +166,7 @@ interrupts = ; clocks = <&mstp0_clks R8A7778_CLK_I2C1>; power-domains = <&cpg_clocks>; + i2c-scl-internal-delay-ns = <5>; status = "disabled"; }; @@ -177,6 +178,7 @@ interrupts = ; clocks = <&mstp0_clks R8A7778_CLK_I2C2>; power-domains = <&cpg_clocks>; + i2c-scl-internal-delay-ns = <5>; status = "disabled"; }; @@ -188,6 +190,7 @@ interrupts = ; clocks = <&mstp0_clks R8A7778_CLK_I2C3>; power-domains = <&cpg_clocks>; + i2c-scl-internal-delay-ns = <5>; status = "disabled"; }; -- cgit v1.2.3-59-g8ed1b