From fde56f62a103c16cab41a138e29316b303e81c80 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Thu, 8 Apr 2021 22:39:25 +0530 Subject: ARM: configs: qcom_defconfig: Enable SDX55 A7 PLL and APCS clock driver Enable A7 PLL driver and APCS clock driver on SDX55 platform. Signed-off-by: Manivannan Sadhasivam Link: https://lore.kernel.org/r/20210408170930.91834-3-manivannan.sadhasivam@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm/configs/qcom_defconfig | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm/configs/qcom_defconfig') diff --git a/arch/arm/configs/qcom_defconfig b/arch/arm/configs/qcom_defconfig index 0b9da27f923a..02f6185f31a6 100644 --- a/arch/arm/configs/qcom_defconfig +++ b/arch/arm/configs/qcom_defconfig @@ -215,6 +215,8 @@ CONFIG_DMADEVICES=y CONFIG_QCOM_BAM_DMA=y CONFIG_STAGING=y CONFIG_COMMON_CLK_QCOM=y +CONFIG_QCOM_A7PLL=y +CONFIG_QCOM_CLK_APCS_SDX55=y CONFIG_QCOM_CLK_RPM=y CONFIG_QCOM_CLK_RPMH=y CONFIG_QCOM_CLK_SMD_RPM=y -- cgit v1.2.3-59-g8ed1b