From 65ae65c9058eb41e9566ffd12699607c68b23e5f Mon Sep 17 00:00:00 2001 From: Janusz Krzysztofik Date: Tue, 21 Dec 2010 21:08:15 -0700 Subject: OMAP1: clock_data: use runtime cpu / machine checks Otherwise multi-omap1 configurations may set wrong clock speed. Created and tested against l-o master on Amstrad Delta. Signed-off-by: Janusz Krzysztofik Signed-off-by: Paul Walmsley --- arch/arm/mach-omap1/clock_data.c | 17 ++++++++--------- 1 file changed, 8 insertions(+), 9 deletions(-) (limited to 'arch/arm/mach-omap1') diff --git a/arch/arm/mach-omap1/clock_data.c b/arch/arm/mach-omap1/clock_data.c index 12fee24181b2..92400b9eb69f 100644 --- a/arch/arm/mach-omap1/clock_data.c +++ b/arch/arm/mach-omap1/clock_data.c @@ -823,12 +823,10 @@ int __init omap1_clk_init(void) crystal_type = info->system_clock_type; } -#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) - ck_ref.rate = 13000000; -#elif defined(CONFIG_ARCH_OMAP16XX) - if (crystal_type == 2) + if (cpu_is_omap7xx()) + ck_ref.rate = 13000000; + if (cpu_is_omap16xx() && crystal_type == 2) ck_ref.rate = 19200000; -#endif pr_info("Clocks: ARM_SYSST: 0x%04x DPLL_CTL: 0x%04x ARM_CKCTL: " "0x%04x\n", omap_readw(ARM_SYSST), omap_readw(DPLL_CTL), @@ -883,10 +881,11 @@ int __init omap1_clk_init(void) ck_dpll1.rate / 1000000, (ck_dpll1.rate / 100000) % 10, arm_ck.rate / 1000000, (arm_ck.rate / 100000) % 10); -#if defined(CONFIG_MACH_OMAP_PERSEUS2) || defined(CONFIG_MACH_OMAP_FSAMPLE) - /* Select slicer output as OMAP input clock */ - omap_writew(omap_readw(OMAP7XX_PCC_UPLD_CTRL) & ~0x1, OMAP7XX_PCC_UPLD_CTRL); -#endif + if (machine_is_omap_perseus2() || machine_is_omap_fsample()) { + /* Select slicer output as OMAP input clock */ + omap_writew(omap_readw(OMAP7XX_PCC_UPLD_CTRL) & ~0x1, + OMAP7XX_PCC_UPLD_CTRL); + } /* Amstrad Delta wants BCLK high when inactive */ if (machine_is_ams_delta()) -- cgit v1.2.3-59-g8ed1b