From cca851d7b4d87f3a644d3381930dc737890bd9ac Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Mon, 28 Jan 2008 13:01:30 +0100 Subject: [ARM] 4790/1: S3C2412: Fix parent selection for msysclk. The msysclk clock was checking for the wrong PLL for the parent in s3c2412_setparent_msysclk(), trying the UPLL instead of the MPLL output. Also ensure the mpll and fclks are at the same rate at init time. Signed-off-by: Ben Dooks Signed-off-by: Russell King --- arch/arm/mach-s3c2412/s3c2412.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm/mach-s3c2412/s3c2412.c') diff --git a/arch/arm/mach-s3c2412/s3c2412.c b/arch/arm/mach-s3c2412/s3c2412.c index 265cd3f567a3..abf1599c9f97 100644 --- a/arch/arm/mach-s3c2412/s3c2412.c +++ b/arch/arm/mach-s3c2412/s3c2412.c @@ -168,6 +168,8 @@ void __init s3c2412_init_clocks(int xtal) fclk = s3c2410_get_pll(__raw_readl(S3C2410_MPLLCON), xtal*2); + clk_mpll.rate = fclk; + tmp = __raw_readl(S3C2410_CLKDIVN); /* work out clock scalings */ -- cgit v1.2.3-59-g8ed1b