From c04c77540a4f996ee94d0240bbae3a7512febd37 Mon Sep 17 00:00:00 2001 From: Joseph Lo Date: Wed, 3 Jul 2013 17:50:37 +0800 Subject: ARM: tegra: do v7_invalidate_l1 only when CPU is Cortex-A9 The v7_invalidate_l1 was used for the L1 cache that come out from reset in a undefined state. This is no need for Cortex-A15. We do it for A9 only. Signed-off-by: Joseph Lo Signed-off-by: Stephen Warren --- arch/arm/mach-tegra/headsmp.S | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'arch/arm/mach-tegra/headsmp.S') diff --git a/arch/arm/mach-tegra/headsmp.S b/arch/arm/mach-tegra/headsmp.S index 045c16f2dd51..2072e7322c39 100644 --- a/arch/arm/mach-tegra/headsmp.S +++ b/arch/arm/mach-tegra/headsmp.S @@ -6,6 +6,7 @@ .section ".text.head", "ax" ENTRY(tegra_secondary_startup) - bl v7_invalidate_l1 + check_cpu_part_num 0xc09, r8, r9 + bleq v7_invalidate_l1 b secondary_startup ENDPROC(tegra_secondary_startup) -- cgit v1.2.3-59-g8ed1b