From cd587096c0e2b85a67e77721a753679bac89b394 Mon Sep 17 00:00:00 2001 From: "Hebbar, Gururaja" Date: Mon, 19 Nov 2012 21:59:58 +0530 Subject: mmc: omap_hsmmc: Enable HSPE bit for high speed cards HSMMC IP on AM33xx need a special setting to handle High-speed cards. Other platforms like TI81xx, OMAP4 may need this as-well. This depends on the HSMMC IP timing closure done for the high speed cards. From AM335x TRM (SPRUH73F - 18.3.12 Output Signals Generation): The MMC/SD/SDIO output signals can be driven on either falling edge or rising edge depending on the SD_HCTL[2] HSPE bit. This feature allows to reach better timing performance, and thus to increase data transfer frequency. There are few pre-requisites for enabling the HSPE bit - Controller should support High-Speed-Enable Bit and - Controller should not be using DDR Mode and - Controller should advertise that it supports High Speed in capabilities register and - MMC/SD clock coming out of controller > 25MHz Signed-off-by: Hebbar, Gururaja Signed-off-by: Venkatraman S Signed-off-by: Chris Ball --- arch/arm/plat-omap/include/plat/mmc.h | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm/plat-omap') diff --git a/arch/arm/plat-omap/include/plat/mmc.h b/arch/arm/plat-omap/include/plat/mmc.h index 8b4e4f2da2f5..346af5b490be 100644 --- a/arch/arm/plat-omap/include/plat/mmc.h +++ b/arch/arm/plat-omap/include/plat/mmc.h @@ -126,6 +126,7 @@ struct omap_mmc_platform_data { /* we can put the features above into this variable */ #define HSMMC_HAS_PBIAS (1 << 0) #define HSMMC_HAS_UPDATED_RESET (1 << 1) +#define HSMMC_HAS_HSPE_SUPPORT (1 << 2) unsigned features; int switch_pin; /* gpio (card detect) */ -- cgit v1.2.3-59-g8ed1b