From c197cec5fae7968a7154ee999f0a1b07938d1528 Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Sat, 18 Jul 2009 10:12:25 +0100 Subject: ARM: S3C: Update hwmon device definition and name Change the hwmon device name to something more generic as this should be functional for both the s3c24xx and s3c64xx archs. Since it has yet to have a driver, it is pretty safe to change as there are no extant users. Also add the necessary entry in devs.h which seems to have been missed out at somepoint. Signed-off-by: Ben Dooks Signed-off-by: Ben Dooks --- arch/arm/plat-s3c/include/plat/devs.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm/plat-s3c/include') diff --git a/arch/arm/plat-s3c/include/plat/devs.h b/arch/arm/plat-s3c/include/plat/devs.h index 2e170827e0b0..1989ca1bb2b1 100644 --- a/arch/arm/plat-s3c/include/plat/devs.h +++ b/arch/arm/plat-s3c/include/plat/devs.h @@ -46,6 +46,8 @@ extern struct platform_device s3c_device_hsmmc2; extern struct platform_device s3c_device_spi0; extern struct platform_device s3c_device_spi1; +extern struct platform_device s3c_device_hwmon; + extern struct platform_device s3c_device_nand; extern struct platform_device s3c_device_usbgadget; -- cgit v1.2.3-59-g8ed1b From e170adcb406504b8acd35554c69830c11916be1f Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Sat, 18 Jul 2009 10:12:27 +0100 Subject: ARM: S3C: Add ADC synchronous read call. To add HWMON support, we need a synchronous read() call that blocks until completion. Add the client that is being service to the select and convert callbacks to make the code easier. Signed-off-by: Ben Dooks Signed-off-by: Ben Dooks --- arch/arm/plat-s3c/include/plat/adc.h | 8 +++-- arch/arm/plat-s3c24xx/adc.c | 64 +++++++++++++++++++++++++++++------- 2 files changed, 59 insertions(+), 13 deletions(-) (limited to 'arch/arm/plat-s3c/include') diff --git a/arch/arm/plat-s3c/include/plat/adc.h b/arch/arm/plat-s3c/include/plat/adc.h index d847bd476b6c..5f3b1cd53b90 100644 --- a/arch/arm/plat-s3c/include/plat/adc.h +++ b/arch/arm/plat-s3c/include/plat/adc.h @@ -19,10 +19,14 @@ struct s3c_adc_client; extern int s3c_adc_start(struct s3c_adc_client *client, unsigned int channel, unsigned int nr_samples); +extern int s3c_adc_read(struct s3c_adc_client *client, unsigned int ch); + extern struct s3c_adc_client * s3c_adc_register(struct platform_device *pdev, - void (*select)(unsigned selected), - void (*conv)(unsigned d0, unsigned d1, + void (*select)(struct s3c_adc_client *client, + unsigned selected), + void (*conv)(struct s3c_adc_client *client, + unsigned d0, unsigned d1, unsigned *samples_left), unsigned int is_ts); diff --git a/arch/arm/plat-s3c24xx/adc.c b/arch/arm/plat-s3c24xx/adc.c index ee1baf11ad9e..11117a7ba911 100644 --- a/arch/arm/plat-s3c24xx/adc.c +++ b/arch/arm/plat-s3c24xx/adc.c @@ -39,13 +39,16 @@ struct s3c_adc_client { struct platform_device *pdev; struct list_head pend; + wait_queue_head_t *wait; unsigned int nr_samples; + int result; unsigned char is_ts; unsigned char channel; - void (*select_cb)(unsigned selected); - void (*convert_cb)(unsigned val1, unsigned val2, + void (*select_cb)(struct s3c_adc_client *c, unsigned selected); + void (*convert_cb)(struct s3c_adc_client *c, + unsigned val1, unsigned val2, unsigned *samples_left); }; @@ -81,7 +84,7 @@ static inline void s3c_adc_select(struct adc_device *adc, { unsigned con = readl(adc->regs + S3C2410_ADCCON); - client->select_cb(1); + client->select_cb(client, 1); con &= ~S3C2410_ADCCON_MUXMASK; con &= ~S3C2410_ADCCON_STDBM; @@ -153,25 +156,61 @@ int s3c_adc_start(struct s3c_adc_client *client, } EXPORT_SYMBOL_GPL(s3c_adc_start); -static void s3c_adc_default_select(unsigned select) +static void s3c_convert_done(struct s3c_adc_client *client, + unsigned v, unsigned u, unsigned *left) +{ + client->result = v; + wake_up(client->wait); +} + +int s3c_adc_read(struct s3c_adc_client *client, unsigned int ch) +{ + DECLARE_WAIT_QUEUE_HEAD_ONSTACK(wake); + int ret; + + client->convert_cb = s3c_convert_done; + client->wait = &wake; + client->result = -1; + + ret = s3c_adc_start(client, ch, 1); + if (ret < 0) + goto err; + + ret = wait_event_timeout(wake, client->result >= 0, HZ / 2); + if (client->result < 0) { + ret = -ETIMEDOUT; + goto err; + } + + client->convert_cb = NULL; + return client->result; + +err: + return ret; +} +EXPORT_SYMBOL_GPL(s3c_adc_convert); + +static void s3c_adc_default_select(struct s3c_adc_client *client, + unsigned select) { } struct s3c_adc_client *s3c_adc_register(struct platform_device *pdev, - void (*select)(unsigned int selected), - void (*conv)(unsigned d0, unsigned d1, + void (*select)(struct s3c_adc_client *client, + unsigned int selected), + void (*conv)(struct s3c_adc_client *client, + unsigned d0, unsigned d1, unsigned *samples_left), unsigned int is_ts) { struct s3c_adc_client *client; WARN_ON(!pdev); - WARN_ON(!conv); if (!select) select = s3c_adc_default_select; - if (!conv || !pdev) + if (!pdev) return ERR_PTR(-EINVAL); client = kzalloc(sizeof(struct s3c_adc_client), GFP_KERNEL); @@ -230,16 +269,19 @@ static irqreturn_t s3c_adc_irq(int irq, void *pw) adc_dbg(adc, "read %d: 0x%04x, 0x%04x\n", client->nr_samples, data0, data1); client->nr_samples--; - (client->convert_cb)(data0 & 0x3ff, data1 & 0x3ff, &client->nr_samples); + + if (client->convert_cb) + (client->convert_cb)(client, data0 & 0x3ff, data1 & 0x3ff, + &client->nr_samples); if (client->nr_samples > 0) { /* fire another conversion for this */ - client->select_cb(1); + client->select_cb(client, 1); s3c_adc_convert(adc); } else { local_irq_save(flags); - (client->select_cb)(0); + (client->select_cb)(client, 0); adc->cur = NULL; s3c_adc_try(adc); -- cgit v1.2.3-59-g8ed1b From bff78650a2b0ed42b8fb134b6a9b387e00027d67 Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Sat, 18 Jul 2009 10:12:28 +0100 Subject: ARM: HWMON: S3C24XX series ADC driver Add support for the ADC controller on the S3C series of processors to drivers/hwmon for use with hardware monitoring systems. Signed-off-by: Ben Dooks Acked-by: Jean Delvare Signed-off-by: Ben Dooks --- arch/arm/plat-s3c/include/plat/hwmon.h | 41 ++++ drivers/hwmon/Kconfig | 17 ++ drivers/hwmon/Makefile | 1 + drivers/hwmon/s3c-hwmon.c | 405 +++++++++++++++++++++++++++++++++ 4 files changed, 464 insertions(+) create mode 100644 arch/arm/plat-s3c/include/plat/hwmon.h create mode 100644 drivers/hwmon/s3c-hwmon.c (limited to 'arch/arm/plat-s3c/include') diff --git a/arch/arm/plat-s3c/include/plat/hwmon.h b/arch/arm/plat-s3c/include/plat/hwmon.h new file mode 100644 index 000000000000..1ba88ea0aa31 --- /dev/null +++ b/arch/arm/plat-s3c/include/plat/hwmon.h @@ -0,0 +1,41 @@ +/* linux/arch/arm/plat-s3c/include/plat/hwmon.h + * + * Copyright 2005 Simtec Electronics + * Ben Dooks + * http://armlinux.simtec.co.uk/ + * + * S3C - HWMon interface for ADC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_ARCH_ADC_HWMON_H +#define __ASM_ARCH_ADC_HWMON_H __FILE__ + +/** + * s3c_hwmon_chcfg - channel configuration + * @name: The name to give this channel. + * @mult: Multiply the ADC value read by this. + * @div: Divide the value from the ADC by this. + * + * The value read from the ADC is converted to a value that + * hwmon expects (mV) by result = (value_read * @mult) / @div. + */ +struct s3c_hwmon_chcfg { + const char *name; + unsigned int mult; + unsigned int div; +}; + +/** + * s3c_hwmon_pdata - HWMON platform data + * @in: One configuration for each possible channel used. + */ +struct s3c_hwmon_pdata { + struct s3c_hwmon_chcfg *in[8]; +}; + +#endif /* __ASM_ARCH_ADC_HWMON_H */ + diff --git a/drivers/hwmon/Kconfig b/drivers/hwmon/Kconfig index 2d5016691d40..2e25b7a827d3 100644 --- a/drivers/hwmon/Kconfig +++ b/drivers/hwmon/Kconfig @@ -702,6 +702,23 @@ config SENSORS_SHT15 This driver can also be built as a module. If so, the module will be called sht15. +config SENSORS_S3C + tristate "S3C24XX/S3C64XX Inbuilt ADC" + depends on ARCH_S3C2410 || ARCH_S3C64XX + help + If you say yes here you get support for the on-board ADCs of + the Samsung S3C24XX or S3C64XX series of SoC + + This driver can also be built as a module. If so, the module + will be called s3c-hwmo. + +config SENSORS_S3C_RAW + bool "Include raw channel attributes in sysfs" + depends on SENSORS_S3C + help + Say Y here if you want to include raw copies of all the ADC + channels in sysfs. + config SENSORS_SIS5595 tristate "Silicon Integrated Systems Corp. SiS5595" depends on PCI diff --git a/drivers/hwmon/Makefile b/drivers/hwmon/Makefile index b793dce6bed5..7f239a247c33 100644 --- a/drivers/hwmon/Makefile +++ b/drivers/hwmon/Makefile @@ -76,6 +76,7 @@ obj-$(CONFIG_SENSORS_MAX6650) += max6650.o obj-$(CONFIG_SENSORS_PC87360) += pc87360.o obj-$(CONFIG_SENSORS_PC87427) += pc87427.o obj-$(CONFIG_SENSORS_PCF8591) += pcf8591.o +obj-$(CONFIG_SENSORS_S3C) += s3c-hwmon.o obj-$(CONFIG_SENSORS_SHT15) += sht15.o obj-$(CONFIG_SENSORS_SIS5595) += sis5595.o obj-$(CONFIG_SENSORS_SMSC47B397)+= smsc47b397.o diff --git a/drivers/hwmon/s3c-hwmon.c b/drivers/hwmon/s3c-hwmon.c new file mode 100644 index 000000000000..3a524f2fe493 --- /dev/null +++ b/drivers/hwmon/s3c-hwmon.c @@ -0,0 +1,405 @@ +/* linux/drivers/hwmon/s3c-hwmon.c + * + * Copyright (C) 2005, 2008, 2009 Simtec Electronics + * http://armlinux.simtec.co.uk/ + * Ben Dooks + * + * S3C24XX/S3C64XX ADC hwmon support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +*/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include + +struct s3c_hwmon_attr { + struct sensor_device_attribute in; + struct sensor_device_attribute label; + char in_name[12]; + char label_name[12]; +}; + +/** + * struct s3c_hwmon - ADC hwmon client information + * @lock: Access lock to serialise the conversions. + * @client: The client we registered with the S3C ADC core. + * @hwmon_dev: The hwmon device we created. + * @attr: The holders for the channel attributes. +*/ +struct s3c_hwmon { + struct semaphore lock; + struct s3c_adc_client *client; + struct device *hwmon_dev; + + struct s3c_hwmon_attr attrs[8]; +}; + +/** + * s3c_hwmon_read_ch - read a value from a given adc channel. + * @dev: The device. + * @hwmon: Our state. + * @channel: The channel we're reading from. + * + * Read a value from the @channel with the proper locking and sleep until + * either the read completes or we timeout awaiting the ADC core to get + * back to us. + */ +static int s3c_hwmon_read_ch(struct device *dev, + struct s3c_hwmon *hwmon, int channel) +{ + int ret; + + ret = down_interruptible(&hwmon->lock); + if (ret < 0) + return ret; + + dev_dbg(dev, "reading channel %d\n", channel); + + ret = s3c_adc_read(hwmon->client, channel); + up(&hwmon->lock); + + return ret; +} + +#ifdef CONFIG_SENSORS_S3C_RAW +/** + * s3c_hwmon_show_raw - show a conversion from the raw channel number. + * @dev: The device that the attribute belongs to. + * @attr: The attribute being read. + * @buf: The result buffer. + * + * This show deals with the raw attribute, registered for each possible + * ADC channel. This does a conversion and returns the raw (un-scaled) + * value returned from the hardware. + */ +static ssize_t s3c_hwmon_show_raw(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct s3c_hwmon *adc = platform_get_drvdata(to_platform_device(dev)); + struct sensor_device_attribute *sa = to_sensor_dev_attr(attr); + int ret; + + ret = s3c_hwmon_read_ch(dev, adc, sa->index); + + return (ret < 0) ? ret : snprintf(buf, PAGE_SIZE, "%d\n", ret); +} + +#define DEF_ADC_ATTR(x) \ + static SENSOR_DEVICE_ATTR(adc##x##_raw, S_IRUGO, s3c_hwmon_show_raw, NULL, x) + +DEF_ADC_ATTR(0); +DEF_ADC_ATTR(1); +DEF_ADC_ATTR(2); +DEF_ADC_ATTR(3); +DEF_ADC_ATTR(4); +DEF_ADC_ATTR(5); +DEF_ADC_ATTR(6); +DEF_ADC_ATTR(7); + +static struct attribute *s3c_hwmon_attrs[9] = { + &sensor_dev_attr_adc0_raw.dev_attr.attr, + &sensor_dev_attr_adc1_raw.dev_attr.attr, + &sensor_dev_attr_adc2_raw.dev_attr.attr, + &sensor_dev_attr_adc3_raw.dev_attr.attr, + &sensor_dev_attr_adc4_raw.dev_attr.attr, + &sensor_dev_attr_adc5_raw.dev_attr.attr, + &sensor_dev_attr_adc6_raw.dev_attr.attr, + &sensor_dev_attr_adc7_raw.dev_attr.attr, + NULL, +}; + +static struct attribute_group s3c_hwmon_attrgroup = { + .attrs = s3c_hwmon_attrs, +}; + +static inline int s3c_hwmon_add_raw(struct device *dev) +{ + return sysfs_create_group(&dev->kobj, &s3c_hwmon_attrgroup); +} + +static inline void s3c_hwmon_remove_raw(struct device *dev) +{ + sysfs_remove_group(&dev->kobj, &s3c_hwmon_attrgroup); +} + +#else + +static inline int s3c_hwmon_add_raw(struct device *dev) { return 0; } +static inline void s3c_hwmon_remove_raw(struct device *dev) { } + +#endif /* CONFIG_SENSORS_S3C_RAW */ + +/** + * s3c_hwmon_ch_show - show value of a given channel + * @dev: The device that the attribute belongs to. + * @attr: The attribute being read. + * @buf: The result buffer. + * + * Read a value from the ADC and scale it before returning it to the + * caller. The scale factor is gained from the channel configuration + * passed via the platform data when the device was registered. + */ +static ssize_t s3c_hwmon_ch_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct sensor_device_attribute *sen_attr = to_sensor_dev_attr(attr); + struct s3c_hwmon *hwmon = platform_get_drvdata(to_platform_device(dev)); + struct s3c_hwmon_pdata *pdata = dev->platform_data; + struct s3c_hwmon_chcfg *cfg; + int ret; + + cfg = pdata->in[sen_attr->index]; + + ret = s3c_hwmon_read_ch(dev, hwmon, sen_attr->index); + if (ret < 0) + return ret; + + ret *= cfg->mult; + ret = DIV_ROUND_CLOSEST(ret, cfg->div); + + return snprintf(buf, PAGE_SIZE, "%d\n", ret); +} + +/** + * s3c_hwmon_label_show - show label name of the given channel. + * @dev: The device that the attribute belongs to. + * @attr: The attribute being read. + * @buf: The result buffer. + * + * Return the label name of a given channel + */ +static ssize_t s3c_hwmon_label_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct sensor_device_attribute *sen_attr = to_sensor_dev_attr(attr); + struct s3c_hwmon_pdata *pdata = dev->platform_data; + struct s3c_hwmon_chcfg *cfg; + + cfg = pdata->in[sen_attr->index]; + + return snprintf(buf, PAGE_SIZE, "%s\n", cfg->name); +} + +/** + * s3c_hwmon_create_attr - create hwmon attribute for given channel. + * @dev: The device to create the attribute on. + * @cfg: The channel configuration passed from the platform data. + * @channel: The ADC channel number to process. + * + * Create the scaled attribute for use with hwmon from the specified + * platform data in @pdata. The sysfs entry is handled by the routine + * s3c_hwmon_ch_show(). + * + * The attribute name is taken from the configuration data if present + * otherwise the name is taken by concatenating in_ with the channel + * number. + */ +static int s3c_hwmon_create_attr(struct device *dev, + struct s3c_hwmon_chcfg *cfg, + struct s3c_hwmon_attr *attrs, + int channel) +{ + struct sensor_device_attribute *attr; + int ret; + + snprintf(attrs->in_name, sizeof(attrs->in_name), "in%d_input", channel); + + attr = &attrs->in; + attr->index = channel; + attr->dev_attr.attr.name = attrs->in_name; + attr->dev_attr.attr.mode = S_IRUGO; + attr->dev_attr.attr.owner = THIS_MODULE; + attr->dev_attr.show = s3c_hwmon_ch_show; + + ret = device_create_file(dev, &attr->dev_attr); + if (ret < 0) { + dev_err(dev, "failed to create input attribute\n"); + return ret; + } + + /* if this has a name, add a label */ + if (cfg->name) { + snprintf(attrs->label_name, sizeof(attrs->label_name), + "in%d_label", channel); + + attr = &attrs->label; + attr->index = channel; + attr->dev_attr.attr.name = attrs->label_name; + attr->dev_attr.attr.mode = S_IRUGO; + attr->dev_attr.attr.owner = THIS_MODULE; + attr->dev_attr.show = s3c_hwmon_label_show; + + ret = device_create_file(dev, &attr->dev_attr); + if (ret < 0) { + device_remove_file(dev, &attrs->in.dev_attr); + dev_err(dev, "failed to create label attribute\n"); + } + } + + return ret; +} + +static void s3c_hwmon_remove_attr(struct device *dev, + struct s3c_hwmon_attr *attrs) +{ + device_remove_file(dev, &attrs->in.dev_attr); + device_remove_file(dev, &attrs->label.dev_attr); +} + +/** + * s3c_hwmon_probe - device probe entry. + * @dev: The device being probed. +*/ +static int __devinit s3c_hwmon_probe(struct platform_device *dev) +{ + struct s3c_hwmon_pdata *pdata = dev->dev.platform_data; + struct s3c_hwmon *hwmon; + int ret = 0; + int i; + + if (!pdata) { + dev_err(&dev->dev, "no platform data supplied\n"); + return -EINVAL; + } + + hwmon = kzalloc(sizeof(struct s3c_hwmon), GFP_KERNEL); + if (hwmon == NULL) { + dev_err(&dev->dev, "no memory\n"); + return -ENOMEM; + } + + platform_set_drvdata(dev, hwmon); + + init_MUTEX(&hwmon->lock); + + /* Register with the core ADC driver. */ + + hwmon->client = s3c_adc_register(dev, NULL, NULL, 0); + if (IS_ERR(hwmon->client)) { + dev_err(&dev->dev, "cannot register adc\n"); + ret = PTR_ERR(hwmon->client); + goto err_mem; + } + + /* add attributes for our adc devices. */ + + ret = s3c_hwmon_add_raw(&dev->dev); + if (ret) + goto err_registered; + + /* register with the hwmon core */ + + hwmon->hwmon_dev = hwmon_device_register(&dev->dev); + if (IS_ERR(hwmon->hwmon_dev)) { + dev_err(&dev->dev, "error registering with hwmon\n"); + ret = PTR_ERR(hwmon->hwmon_dev); + goto err_raw_attribute; + } + + for (i = 0; i < ARRAY_SIZE(pdata->in); i++) { + if (!pdata->in[i]) + continue; + + if (pdata->in[i]->mult >= 0x10000) + dev_warn(&dev->dev, + "channel %d multiplier too large\n", + i); + + ret = s3c_hwmon_create_attr(&dev->dev, pdata->in[i], + &hwmon->attrs[i], i); + if (ret) { + dev_err(&dev->dev, + "error creating channel %d\n", i); + + for (i--; i >= 0; i--) + s3c_hwmon_remove_attr(&dev->dev, + &hwmon->attrs[i]); + + goto err_hwmon_register; + } + } + + return 0; + + err_hwmon_register: + hwmon_device_unregister(hwmon->hwmon_dev); + + err_raw_attribute: + s3c_hwmon_remove_raw(&dev->dev); + + err_registered: + s3c_adc_release(hwmon->client); + + err_mem: + kfree(hwmon); + return ret; +} + +static int __devexit s3c_hwmon_remove(struct platform_device *dev) +{ + struct s3c_hwmon *hwmon = platform_get_drvdata(dev); + int i; + + s3c_hwmon_remove_raw(&dev->dev); + + for (i = 0; i < ARRAY_SIZE(hwmon->attrs); i++) + s3c_hwmon_remove_attr(&dev->dev, &hwmon->attrs[i]); + + hwmon_device_unregister(hwmon->hwmon_dev); + s3c_adc_release(hwmon->client); + + return 0; +} + +static struct platform_driver s3c_hwmon_driver = { + .driver = { + .name = "s3c-hwmon", + .owner = THIS_MODULE, + }, + .probe = s3c_hwmon_probe, + .remove = __devexit_p(s3c_hwmon_remove), +}; + +static int __init s3c_hwmon_init(void) +{ + return platform_driver_register(&s3c_hwmon_driver); +} + +static void __exit s3c_hwmon_exit(void) +{ + platform_driver_unregister(&s3c_hwmon_driver); +} + +module_init(s3c_hwmon_init); +module_exit(s3c_hwmon_exit); + +MODULE_AUTHOR("Ben Dooks "); +MODULE_DESCRIPTION("S3C ADC HWMon driver"); +MODULE_LICENSE("GPL v2"); +MODULE_ALIAS("platform:s3c-hwmon"); -- cgit v1.2.3-59-g8ed1b From ea5fe9aedf512d20b75b7dcfd54ab99ae5c0934b Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Thu, 30 Jul 2009 23:23:22 +0100 Subject: ARM: S3C: CPUFREQ: Documentation for cpufreq header Update arch/arm/plat-s3c/include/plat/cpu-freq.h to include kerneldoc style documentation. Signed-off-by: Ben Dooks Signed-off-by: Ben Dooks --- arch/arm/plat-s3c/include/plat/cpu-freq.h | 91 +++++++++++++++++++++++++++---- 1 file changed, 81 insertions(+), 10 deletions(-) (limited to 'arch/arm/plat-s3c/include') diff --git a/arch/arm/plat-s3c/include/plat/cpu-freq.h b/arch/arm/plat-s3c/include/plat/cpu-freq.h index c86a13307e90..0ba7670fd075 100644 --- a/arch/arm/plat-s3c/include/plat/cpu-freq.h +++ b/arch/arm/plat-s3c/include/plat/cpu-freq.h @@ -17,6 +17,21 @@ struct s3c_cpufreq_info; struct s3c_cpufreq_board; struct s3c_iotimings; +/** + * struct s3c_freq - frequency information (mainly for core drivers) + * @fclk: The FCLK frequency in Hz. + * @armclk: The ARMCLK frequency in Hz. + * @hclk_tns: HCLK cycle time in 10ths of nano-seconds. + * @hclk: The HCLK frequency in Hz. + * @pclk: The PCLK frequency in Hz. + * + * This contains the frequency information about the current configuration + * mainly for the core drivers to ensure we do not end up passing about + * a large number of parameters. + * + * The @hclk_tns field is a useful cache for the parts of the drivers that + * need to calculate IO timings and suchlike. + */ struct s3c_freq { unsigned long fclk; unsigned long armclk; @@ -25,33 +40,75 @@ struct s3c_freq { unsigned long pclk; }; -/* wrapper 'struct cpufreq_freqs' so that any drivers receiving the +/** + * struct s3c_cpufreq_freqs - s3c cpufreq notification information. + * @freqs: The cpufreq setting information. + * @old: The old clock settings. + * @new: The new clock settings. + * @pll_changing: Set if the PLL is changing. + * + * Wrapper 'struct cpufreq_freqs' so that any drivers receiving the * notification can use this information that is not provided by just * having the core frequency alone. + * + * The pll_changing flag is used to indicate if the PLL itself is + * being set during this change. This is important as the clocks + * will temporarily be set to the XTAL clock during this time, so + * drivers may want to close down their output during this time. + * + * Note, this is not being used by any current drivers and therefore + * may be removed in the future. */ - struct s3c_cpufreq_freqs { struct cpufreq_freqs freqs; struct s3c_freq old; struct s3c_freq new; + + unsigned int pll_changing:1; }; #define to_s3c_cpufreq(_cf) container_of(_cf, struct s3c_cpufreq_freqs, freqs) +/** + * struct s3c_clkdivs - clock divisor information + * @p_divisor: Divisor from FCLK to PCLK. + * @h_divisor: Divisor from FCLK to HCLK. + * @arm_divisor: Divisor from FCLK to ARMCLK (not all CPUs). + * @dvs: Non-zero if using DVS mode for ARMCLK. + * + * Divisor settings for the core clocks. + */ struct s3c_clkdivs { - int p_divisor; /* fclk / pclk */ - int h_divisor; /* fclk / hclk */ - int arm_divisor; /* not all cpus have this. */ - unsigned char dvs; /* using dvs mode to arm. */ + int p_divisor; + int h_divisor; + int arm_divisor; + unsigned char dvs; }; #define PLLVAL(_m, _p, _s) (((_m) << 12) | ((_p) << 4) | (_s)) +/** + * struct s3c_pllval - PLL value entry. + * @freq: The frequency for this entry in Hz. + * @pll_reg: The PLL register setting for this PLL value. + */ struct s3c_pllval { unsigned long freq; unsigned long pll_reg; }; +/** + * struct s3c_cpufreq_config - current cpu frequency configuration + * @freq: The current settings for the core clocks. + * @pll: The PLL table entry for the current PLL settings. + * @divs: The divisor settings for the core clocks. + * @info: The current core driver information. + * @board: The information for the board we are running on. + * + * This is for the core drivers that need to know information about + * the current settings and values. It should not be needed by any + * device drivers. +*/ struct s3c_cpufreq_config { struct s3c_freq freq; struct s3c_pllval pll; @@ -60,13 +117,27 @@ struct s3c_cpufreq_config { struct s3c_cpufreq_board *board; }; -/* s3c_cpufreq_board +/** + * struct s3c_cpufreq_board - per-board cpu frequency informatin + * @refresh: The SDRAM refresh period in nanoseconds. + * @auto_io: Set if the IO timing settings should be generated from the + * initialisation time hardware registers. + * @need_io: Set if the board has external IO on any of the chipselect + * lines that will require the hardware timing registers to be + * updated on a clock change. + * @max: The maxium frequency limits for the system. Any field that + * is left at zero will use the CPU's settings. + * + * This contains the board specific settings that affect how the CPU + * drivers chose settings. These include the memory refresh and IO + * timing information. * - * per-board configuraton information, such as memory refresh and - * how to initialise IO timings. + * Registration depends on the driver being used, the ARMCLK only + * implementation does not currently need this but the older style + * driver requires this to be available. */ struct s3c_cpufreq_board { - unsigned int refresh; /* refresh period in ns */ + unsigned int refresh; unsigned int auto_io:1; /* automatically init io timings. */ unsigned int need_io:1; /* set if needs io timing support. */ -- cgit v1.2.3-59-g8ed1b From d6fc87d3f7d236892e4d0003a07cd2b5171e5e27 Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Thu, 30 Jul 2009 23:23:23 +0100 Subject: ARM: S3C: CPUFREQ: Move struct s3c_cpufreq_config to cpu-freq-core.h Move the structure s3c_cpufreq_config from cpu-freq.h to the less advertised cpu-freq-core.h as it is not needed by anything outside the core drivers. Signed-off-by: Ben Dooks Signed-off-by: Ben Dooks --- arch/arm/plat-s3c/include/plat/cpu-freq.h | 20 ----------------- arch/arm/plat-s3c24xx/include/plat/cpu-freq-core.h | 25 ++++++++++++++++++++++ 2 files changed, 25 insertions(+), 20 deletions(-) (limited to 'arch/arm/plat-s3c/include') diff --git a/arch/arm/plat-s3c/include/plat/cpu-freq.h b/arch/arm/plat-s3c/include/plat/cpu-freq.h index 0ba7670fd075..7b982b7f28cd 100644 --- a/arch/arm/plat-s3c/include/plat/cpu-freq.h +++ b/arch/arm/plat-s3c/include/plat/cpu-freq.h @@ -97,26 +97,6 @@ struct s3c_pllval { unsigned long pll_reg; }; -/** - * struct s3c_cpufreq_config - current cpu frequency configuration - * @freq: The current settings for the core clocks. - * @pll: The PLL table entry for the current PLL settings. - * @divs: The divisor settings for the core clocks. - * @info: The current core driver information. - * @board: The information for the board we are running on. - * - * This is for the core drivers that need to know information about - * the current settings and values. It should not be needed by any - * device drivers. -*/ -struct s3c_cpufreq_config { - struct s3c_freq freq; - struct s3c_pllval pll; - struct s3c_clkdivs divs; - struct s3c_cpufreq_info *info; /* for core, not drivers */ - struct s3c_cpufreq_board *board; -}; - /** * struct s3c_cpufreq_board - per-board cpu frequency informatin * @refresh: The SDRAM refresh period in nanoseconds. diff --git a/arch/arm/plat-s3c24xx/include/plat/cpu-freq-core.h b/arch/arm/plat-s3c24xx/include/plat/cpu-freq-core.h index e078821b3605..7938fb0bc387 100644 --- a/arch/arm/plat-s3c24xx/include/plat/cpu-freq-core.h +++ b/arch/arm/plat-s3c24xx/include/plat/cpu-freq-core.h @@ -64,6 +64,31 @@ struct s3c_plltab { int size; }; +/** + * struct s3c_cpufreq_config - current cpu frequency configuration + * @freq: The current settings for the core clocks. + * @max: Maxium settings, derived from core, board and user settings. + * @pll: The PLL table entry for the current PLL settings. + * @divs: The divisor settings for the core clocks. + * @info: The current core driver information. + * @board: The information for the board we are running on. + * @lock_pll: Set if the PLL settings cannot be changed. + * + * This is for the core drivers that need to know information about + * the current settings and values. It should not be needed by any + * device drivers. +*/ +struct s3c_cpufreq_config { + struct s3c_freq freq; + struct s3c_freq max; + struct cpufreq_frequency_table pll; + struct s3c_clkdivs divs; + struct s3c_cpufreq_info *info; /* for core, not drivers */ + struct s3c_cpufreq_board *board; + + unsigned int lock_pll:1; +}; + /** * struct s3c_cpufreq_info - Information for the CPU frequency driver. * @name: The name of this implementation. -- cgit v1.2.3-59-g8ed1b From e13cf03eaae3792442c401860910d40f33c89a33 Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Thu, 30 Jul 2009 23:23:35 +0100 Subject: ARM: S3C: Update CPU register mapping practices. Currently map-base.h defines the main virtual address mappings made for all the support S3C SoC series, but does not then define any base for per-cpu mappings to be made from. Add S3C_ADDR_CPU() macro to define an virtual address as an offset from the last of the core mappings. Signed-off-by: Ben Dooks Signed-off-by: Ben Dooks --- arch/arm/mach-s3c6400/include/mach/map.h | 4 ++-- arch/arm/plat-s3c/include/plat/map-base.h | 8 +++++++- 2 files changed, 9 insertions(+), 3 deletions(-) (limited to 'arch/arm/plat-s3c/include') diff --git a/arch/arm/mach-s3c6400/include/mach/map.h b/arch/arm/mach-s3c6400/include/mach/map.h index 5057d9948d35..e02e6c38a396 100644 --- a/arch/arm/mach-s3c6400/include/mach/map.h +++ b/arch/arm/mach-s3c6400/include/mach/map.h @@ -49,7 +49,7 @@ #define S3C64XX_PA_IIC1 (0x7F00F000) #define S3C64XX_PA_GPIO (0x7F008000) -#define S3C64XX_VA_GPIO S3C_ADDR(0x00500000) +#define S3C64XX_VA_GPIO S3C_ADDR_CPU(0x00000000) #define S3C64XX_SZ_GPIO SZ_4K #define S3C64XX_PA_SDRAM (0x50000000) @@ -57,7 +57,7 @@ #define S3C64XX_PA_VIC1 (0x71300000) #define S3C64XX_PA_MODEM (0x74108000) -#define S3C64XX_VA_MODEM S3C_ADDR(0x00600000) +#define S3C64XX_VA_MODEM S3C_ADDR_CPU(0x00100000) #define S3C64XX_PA_USBHOST (0x74300000) diff --git a/arch/arm/plat-s3c/include/plat/map-base.h b/arch/arm/plat-s3c/include/plat/map-base.h index b84289d32a54..250be311c85b 100644 --- a/arch/arm/plat-s3c/include/plat/map-base.h +++ b/arch/arm/plat-s3c/include/plat/map-base.h @@ -32,9 +32,15 @@ #define S3C_VA_IRQ S3C_ADDR(0x00000000) /* irq controller(s) */ #define S3C_VA_SYS S3C_ADDR(0x00100000) /* system control */ -#define S3C_VA_MEM S3C_ADDR(0x00200000) /* system control */ +#define S3C_VA_MEM S3C_ADDR(0x00200000) /* memory control */ #define S3C_VA_TIMER S3C_ADDR(0x00300000) /* timer block */ #define S3C_VA_WATCHDOG S3C_ADDR(0x00400000) /* watchdog */ #define S3C_VA_UART S3C_ADDR(0x01000000) /* UART */ +/* This is used for the CPU specific mappings that may be needed, so that + * they do not need to directly used S3C_ADDR() and thus make it easier to + * modify the space for mapping. + */ +#define S3C_ADDR_CPU(x) S3C_ADDR(0x00500000 + (x)) + #endif /* __ASM_PLAT_MAP_H */ -- cgit v1.2.3-59-g8ed1b From f0176794b6abc2e5239c07a58cf11b6f43d0f185 Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Thu, 30 Jul 2009 23:23:38 +0100 Subject: ARM: S3C2410: Add S3C2410A sysdev. Add a sysdev S3C2410A sysdev to allow the differentiation of the S3C2410A from the S3C2410. This is needed for the CPUFREQ code to enable the extra features and update cpu specific information. Signed-off-by: Ben Dooks Signed-off-by: Ben Dooks --- arch/arm/mach-s3c2410/dma.c | 11 +++++++++++ arch/arm/mach-s3c2410/irq.c | 15 ++++++++++++++- arch/arm/mach-s3c2410/pm.c | 12 ++++++++++++ arch/arm/mach-s3c2410/s3c2410.c | 20 ++++++++++++++++++++ arch/arm/plat-s3c/include/plat/cpu.h | 1 + arch/arm/plat-s3c24xx/cpu.c | 2 +- arch/arm/plat-s3c24xx/include/plat/s3c2410.h | 1 + 7 files changed, 60 insertions(+), 2 deletions(-) (limited to 'arch/arm/plat-s3c/include') diff --git a/arch/arm/mach-s3c2410/dma.c b/arch/arm/mach-s3c2410/dma.c index dbf96e60d992..63b753f56c64 100644 --- a/arch/arm/mach-s3c2410/dma.c +++ b/arch/arm/mach-s3c2410/dma.c @@ -164,6 +164,17 @@ static int __init s3c2410_dma_drvinit(void) } arch_initcall(s3c2410_dma_drvinit); + +static struct sysdev_driver s3c2410a_dma_driver = { + .add = s3c2410_dma_add, +}; + +static int __init s3c2410a_dma_drvinit(void) +{ + return sysdev_driver_register(&s3c2410a_sysclass, &s3c2410a_dma_driver); +} + +arch_initcall(s3c2410a_dma_drvinit); #endif #if defined(CONFIG_CPU_S3C2442) diff --git a/arch/arm/mach-s3c2410/irq.c b/arch/arm/mach-s3c2410/irq.c index 92150399563b..5e2f35332056 100644 --- a/arch/arm/mach-s3c2410/irq.c +++ b/arch/arm/mach-s3c2410/irq.c @@ -39,9 +39,22 @@ static struct sysdev_driver s3c2410_irq_driver = { .resume = s3c24xx_irq_resume, }; -static int s3c2410_irq_init(void) +static int __init s3c2410_irq_init(void) { return sysdev_driver_register(&s3c2410_sysclass, &s3c2410_irq_driver); } arch_initcall(s3c2410_irq_init); + +static struct sysdev_driver s3c2410a_irq_driver = { + .add = s3c2410_irq_add, + .suspend = s3c24xx_irq_suspend, + .resume = s3c24xx_irq_resume, +}; + +static int __init s3c2410a_irq_init(void) +{ + return sysdev_driver_register(&s3c2410a_sysclass, &s3c2410a_irq_driver); +} + +arch_initcall(s3c2410a_irq_init); diff --git a/arch/arm/mach-s3c2410/pm.c b/arch/arm/mach-s3c2410/pm.c index 143e08a599d4..966119c8efee 100644 --- a/arch/arm/mach-s3c2410/pm.c +++ b/arch/arm/mach-s3c2410/pm.c @@ -119,6 +119,18 @@ static int __init s3c2410_pm_drvinit(void) } arch_initcall(s3c2410_pm_drvinit); + +static struct sysdev_driver s3c2410a_pm_driver = { + .add = s3c2410_pm_add, + .resume = s3c2410_pm_resume, +}; + +static int __init s3c2410a_pm_drvinit(void) +{ + return sysdev_driver_register(&s3c2410a_sysclass, &s3c2410a_pm_driver); +} + +arch_initcall(s3c2410a_pm_drvinit); #endif #if defined(CONFIG_CPU_S3C2440) diff --git a/arch/arm/mach-s3c2410/s3c2410.c b/arch/arm/mach-s3c2410/s3c2410.c index feb141b1f915..e5724a22c358 100644 --- a/arch/arm/mach-s3c2410/s3c2410.c +++ b/arch/arm/mach-s3c2410/s3c2410.c @@ -116,6 +116,13 @@ struct sysdev_class s3c2410_sysclass = { .name = "s3c2410-core", }; +/* Note, we would have liked to name this s3c2410-core, but we cannot + * register two sysdev_class with the same name. + */ +struct sysdev_class s3c2410a_sysclass = { + .name = "s3c2410a-core", +}; + static struct sys_device s3c2410_sysdev = { .cls = &s3c2410_sysclass, }; @@ -133,9 +140,22 @@ static int __init s3c2410_core_init(void) core_initcall(s3c2410_core_init); +static int __init s3c2410a_core_init(void) +{ + return sysdev_class_register(&s3c2410a_sysclass); +} + +core_initcall(s3c2410a_core_init); + int __init s3c2410_init(void) { printk("S3C2410: Initialising architecture\n"); return sysdev_register(&s3c2410_sysdev); } + +int __init s3c2410a_init(void) +{ + s3c2410_sysdev.cls = &s3c2410a_sysclass; + return s3c2410_init(); +} diff --git a/arch/arm/plat-s3c/include/plat/cpu.h b/arch/arm/plat-s3c/include/plat/cpu.h index be541cbba070..fbc3d498e02e 100644 --- a/arch/arm/plat-s3c/include/plat/cpu.h +++ b/arch/arm/plat-s3c/include/plat/cpu.h @@ -65,6 +65,7 @@ extern struct sys_timer s3c24xx_timer; /* system device classes */ extern struct sysdev_class s3c2410_sysclass; +extern struct sysdev_class s3c2410a_sysclass; extern struct sysdev_class s3c2412_sysclass; extern struct sysdev_class s3c2440_sysclass; extern struct sysdev_class s3c2442_sysclass; diff --git a/arch/arm/plat-s3c24xx/cpu.c b/arch/arm/plat-s3c24xx/cpu.c index 1932b7e0da15..5447e60f3936 100644 --- a/arch/arm/plat-s3c24xx/cpu.c +++ b/arch/arm/plat-s3c24xx/cpu.c @@ -81,7 +81,7 @@ static struct cpu_table cpu_ids[] __initdata = { .map_io = s3c2410_map_io, .init_clocks = s3c2410_init_clocks, .init_uarts = s3c2410_init_uarts, - .init = s3c2410_init, + .init = s3c2410a_init, .name = name_s3c2410a }, { diff --git a/arch/arm/plat-s3c24xx/include/plat/s3c2410.h b/arch/arm/plat-s3c24xx/include/plat/s3c2410.h index a9ac9e29759e..b6deeef8f663 100644 --- a/arch/arm/plat-s3c24xx/include/plat/s3c2410.h +++ b/arch/arm/plat-s3c24xx/include/plat/s3c2410.h @@ -14,6 +14,7 @@ #ifdef CONFIG_CPU_S3C2410 extern int s3c2410_init(void); +extern int s3c2410a_init(void); extern void s3c2410_map_io(void); -- cgit v1.2.3-59-g8ed1b From d91e9a7ab93e09e5a0fbed73f3a6a330f14620a4 Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Wed, 5 Aug 2009 18:29:57 +0100 Subject: ARM: S3C24XX: Add platform device for AC97 controller Move the definition of the "generic" IRQ in the process. Signed-off-by: Mark Brown Signed-off-by: Ben Dooks --- arch/arm/mach-s3c2410/include/mach/irqs.h | 6 ++++ arch/arm/plat-s3c/include/plat/devs.h | 1 + arch/arm/plat-s3c24xx/devs.c | 50 +++++++++++++++++++++++++++++++ sound/soc/s3c24xx/s3c24xx-ac97.h | 6 ---- 4 files changed, 57 insertions(+), 6 deletions(-) (limited to 'arch/arm/plat-s3c/include') diff --git a/arch/arm/mach-s3c2410/include/mach/irqs.h b/arch/arm/mach-s3c2410/include/mach/irqs.h index 2a2384ffa7b1..6c12c6312ad8 100644 --- a/arch/arm/mach-s3c2410/include/mach/irqs.h +++ b/arch/arm/mach-s3c2410/include/mach/irqs.h @@ -164,6 +164,12 @@ #define IRQ_S3CUART_TX3 IRQ_S3C2443_TX3 #define IRQ_S3CUART_ERR3 IRQ_S3C2443_ERR3 +#ifdef CONFIG_CPU_S3C2440 +#define IRQ_S3C244x_AC97 IRQ_S3C2440_AC97 +#else +#define IRQ_S3C244x_AC97 IRQ_S3C2443_AC97 +#endif + /* Our FIQs are routable from IRQ_EINT0 to IRQ_ADCPARENT */ #define FIQ_START IRQ_EINT0 diff --git a/arch/arm/plat-s3c/include/plat/devs.h b/arch/arm/plat-s3c/include/plat/devs.h index 2e170827e0b0..2e6599411c28 100644 --- a/arch/arm/plat-s3c/include/plat/devs.h +++ b/arch/arm/plat-s3c/include/plat/devs.h @@ -56,5 +56,6 @@ extern struct platform_device s3c_device_usb_hsotg; #ifdef CONFIG_CPU_S3C2440 extern struct platform_device s3c_device_camif; +extern struct platform_device s3c_device_ac97; #endif diff --git a/arch/arm/plat-s3c24xx/devs.c b/arch/arm/plat-s3c24xx/devs.c index 4eb378c89a39..4553ad6c7adc 100644 --- a/arch/arm/plat-s3c24xx/devs.c +++ b/arch/arm/plat-s3c24xx/devs.c @@ -26,6 +26,8 @@ #include #include #include +#include +#include #include #include @@ -473,4 +475,52 @@ struct platform_device s3c_device_camif = { EXPORT_SYMBOL(s3c_device_camif); +/* AC97 */ + +static struct resource s3c_ac97_resource[] = { + [0] = { + .start = S3C2440_PA_AC97, + .end = S3C2440_PA_AC97 + S3C2440_SZ_AC97 -1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_S3C244x_AC97, + .end = IRQ_S3C244x_AC97, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .name = "PCM out", + .start = DMACH_PCM_OUT, + .end = DMACH_PCM_OUT, + .flags = IORESOURCE_DMA, + }, + [3] = { + .name = "PCM in", + .start = DMACH_PCM_IN, + .end = DMACH_PCM_IN, + .flags = IORESOURCE_DMA, + }, + [4] = { + .name = "Mic in", + .start = DMACH_MIC_IN, + .end = DMACH_MIC_IN, + .flags = IORESOURCE_DMA, + }, +}; + +static u64 s3c_device_ac97_dmamask = 0xffffffffUL; + +struct platform_device s3c_device_ac97 = { + .name = "s3c-ac97", + .id = -1, + .num_resources = ARRAY_SIZE(s3c_ac97_resource), + .resource = s3c_ac97_resource, + .dev = { + .dma_mask = &s3c_device_ac97_dmamask, + .coherent_dma_mask = 0xffffffffUL + } +}; + +EXPORT_SYMBOL(s3c_device_ac97); + #endif // CONFIG_CPU_S32440 diff --git a/sound/soc/s3c24xx/s3c24xx-ac97.h b/sound/soc/s3c24xx/s3c24xx-ac97.h index a96dcadf28b4..e96f941a810b 100644 --- a/sound/soc/s3c24xx/s3c24xx-ac97.h +++ b/sound/soc/s3c24xx/s3c24xx-ac97.h @@ -20,12 +20,6 @@ #define AC_CMD_ADDR(x) (x << 16) #define AC_CMD_DATA(x) (x & 0xffff) -#ifdef CONFIG_CPU_S3C2440 -#define IRQ_S3C244x_AC97 IRQ_S3C2440_AC97 -#else -#define IRQ_S3C244x_AC97 IRQ_S3C2443_AC97 -#endif - extern struct snd_soc_dai s3c2443_ac97_dai[]; #endif /*S3C24XXAC97_H_*/ -- cgit v1.2.3-59-g8ed1b