From 7596723ecd54456da4b8bc5afc4a961aa09bd34b Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Mon, 23 Nov 2015 16:21:43 +0100 Subject: arm64: tegra: Add DSI panel on Jetson TX1 Some variants of the Jetson TX1 ship with a 8.0" WUXGA TFT LCD panel connected via four DSI lanes. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi | 50 ++++++++++++++++++++++++++ 1 file changed, 50 insertions(+) (limited to 'arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi') diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi index b28aff5e104d..78a16a57fec7 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi @@ -1261,6 +1261,23 @@ }; }; + pwm@7000a000 { + status = "okay"; + }; + + i2c@7000c400 { + status = "okay"; + clock-frequency = <100000>; + + exp1: gpio@74 { + compatible = "ti,tca9539"; + reg = <0x74>; + + #gpio-cells = <2>; + gpio-controller; + }; + }; + /* MMC/SD */ sdhci@700b0000 { status = "okay"; @@ -1340,6 +1357,39 @@ regulator-enable-ramp-delay = <472>; regulator-disable-ramp-delay = <4880>; }; + + vdd_dsi_csi: regulator@5 { + compatible = "regulator-fixed"; + reg = <5>; + regulator-name = "AVDD_DSI_CSI_1V2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + vin-supply = <&vdd_sys_1v2>; + }; + + vdd_3v3_dis: regulator@6 { + compatible = "regulator-fixed"; + reg = <6>; + regulator-name = "VDD_DIS_3V3_LCD"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + gpio = <&exp1 3 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_3v3_sys>; + }; + + vdd_1v8_dis: regulator@7 { + compatible = "regulator-fixed"; + reg = <7>; + regulator-name = "VDD_LCD_1V8_DIS"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + gpio = <&exp1 14 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_1v8>; + }; }; gpio-keys { -- cgit v1.2.3-59-g8ed1b