From 77643815b019d3e78b2ca028d701f95df58e7cf3 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 9 Sep 2022 11:53:53 +0200 Subject: arm64: dts: renesas: white-hawk: Add I2C0 and EEPROMs Enable the I2C0 bus on the White Hawk CPU board, and describe the I2C EEPROMs present on the White Hawk CPU and BreakOut boards. Based on a larger patch in the BSP by Takeshi Kihara. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/d01cada6f2d3e44dd6cb26cfa8e4ce6382f1fbff.1662715538.git.geert+renesas@glider.be --- .../boot/dts/renesas/r8a779g0-white-hawk-cpu.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) (limited to 'arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-cpu.dtsi') diff --git a/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-cpu.dtsi b/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-cpu.dtsi index ba8cc162076c..27daba944a33 100644 --- a/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-cpu.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-cpu.dtsi @@ -40,6 +40,21 @@ status = "okay"; }; +&i2c0 { + pinctrl-0 = <&i2c0_pins>; + pinctrl-names = "default"; + + status = "okay"; + clock-frequency = <400000>; + + eeprom@50 { + compatible = "rohm,br24g01", "atmel,24c01"; + label = "cpu-board"; + reg = <0x50>; + pagesize = <8>; + }; +}; + &pfc { pinctrl-0 = <&scif_clk_pins>; pinctrl-names = "default"; @@ -49,6 +64,11 @@ function = "hscif0"; }; + i2c0_pins: i2c0 { + groups = "i2c0"; + function = "i2c0"; + }; + scif_clk_pins: scif_clk { groups = "scif_clk"; function = "scif_clk"; -- cgit v1.2.3-59-g8ed1b