From 2a8d28b8af7906259efe1c3c39de0b660f9eb35b Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Fri, 15 Jul 2022 09:02:47 +0200 Subject: arm64: dts: qcom: sc7280: reorder USB interrupts Only one of the USB controllers supports SuperSpeed and have an SS PHY wakeup interrupt. Reorder the interrupts so that they match the updated binding which specifically has the optional interrupt last. Acked-by: Krzysztof Kozlowski Signed-off-by: Johan Hovold Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220715070248.19078-4-johan+linaro@kernel.org --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index f5e8619c26b1..13d7f267b289 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -3174,10 +3174,11 @@ assigned-clock-rates = <19200000>, <200000000>; interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, - <&pdc 13 IRQ_TYPE_EDGE_RISING>, - <&pdc 12 IRQ_TYPE_EDGE_RISING>; + <&pdc 12 IRQ_TYPE_EDGE_RISING>, + <&pdc 13 IRQ_TYPE_EDGE_RISING>; interrupt-names = "hs_phy_irq", - "dm_hs_phy_irq", "dp_hs_phy_irq"; + "dp_hs_phy_irq", + "dm_hs_phy_irq"; power-domains = <&gcc GCC_USB30_SEC_GDSC>; @@ -3357,13 +3358,13 @@ assigned-clock-rates = <19200000>, <200000000>; interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, - <&pdc 17 IRQ_TYPE_EDGE_BOTH>, + <&pdc 14 IRQ_TYPE_LEVEL_HIGH>, <&pdc 15 IRQ_TYPE_EDGE_BOTH>, - <&pdc 14 IRQ_TYPE_LEVEL_HIGH>; + <&pdc 17 IRQ_TYPE_EDGE_BOTH>; interrupt-names = "hs_phy_irq", - "ss_phy_irq", + "dp_hs_phy_irq", "dm_hs_phy_irq", - "dp_hs_phy_irq"; + "ss_phy_irq"; power-domains = <&gcc GCC_USB30_PRIM_GDSC>; -- cgit v1.2.3-59-g8ed1b