From 60a2fb8d202a4d98a87a6ff1aef87c9a07b4d2f4 Mon Sep 17 00:00:00 2001 From: Moudy Ho Date: Tue, 23 Aug 2022 10:38:02 +0800 Subject: arm64: dts: mt8183: add MediaTek MDP3 nodes Add device nodes for Media Data Path 3 (MDP3) modules. Signed-off-by: Moudy Ho Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20220823023803.27850-4-moudy.ho@mediatek.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8183.dtsi | 63 ++++++++++++++++++++++++++++++++ 1 file changed, 63 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi index 9d32871973a2..1543876b1e3c 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -1691,6 +1691,60 @@ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>; }; + mdp3-rdma0@14001000 { + compatible = "mediatek,mt8183-mdp3-rdma"; + reg = <0 0x14001000 0 0x1000>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x1000 0x1000>; + mediatek,gce-events = , + ; + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_MDP_RDMA0>, + <&mmsys CLK_MM_MDP_RSZ1>; + iommus = <&iommu M4U_PORT_MDP_RDMA0>; + mboxes = <&gce 20 CMDQ_THR_PRIO_LOWEST 0>, + <&gce 21 CMDQ_THR_PRIO_LOWEST 0>; + }; + + mdp3-rsz0@14003000 { + compatible = "mediatek,mt8183-mdp3-rsz"; + reg = <0 0x14003000 0 0x1000>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x3000 0x1000>; + mediatek,gce-events = , + ; + clocks = <&mmsys CLK_MM_MDP_RSZ0>; + }; + + mdp3-rsz1@14004000 { + compatible = "mediatek,mt8183-mdp3-rsz"; + reg = <0 0x14004000 0 0x1000>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x4000 0x1000>; + mediatek,gce-events = , + ; + clocks = <&mmsys CLK_MM_MDP_RSZ1>; + }; + + mdp3-wrot0@14005000 { + compatible = "mediatek,mt8183-mdp3-wrot"; + reg = <0 0x14005000 0 0x1000>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>; + mediatek,gce-events = , + ; + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_MDP_WROT0>; + iommus = <&iommu M4U_PORT_MDP_WROT0>; + }; + + mdp3-wdma@14006000 { + compatible = "mediatek,mt8183-mdp3-wdma"; + reg = <0 0x14006000 0 0x1000>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 0x1000>; + mediatek,gce-events = , + ; + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_MDP_WDMA0>; + iommus = <&iommu M4U_PORT_MDP_WDMA0>; + }; + ovl0: ovl@14008000 { compatible = "mediatek,mt8183-disp-ovl"; reg = <0 0x14008000 0 0x1000>; @@ -1834,6 +1888,15 @@ power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; }; + mdp3-ccorr@1401c000 { + compatible = "mediatek,mt8183-mdp3-ccorr"; + reg = <0 0x1401c000 0 0x1000>; + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0xc000 0x1000>; + mediatek,gce-events = , + ; + clocks = <&mmsys CLK_MM_MDP_CCORR>; + }; + imgsys: syscon@15020000 { compatible = "mediatek,mt8183-imgsys", "syscon"; reg = <0 0x15020000 0 0x1000>; -- cgit v1.2.3-59-g8ed1b From a8013418d35cc760d0af3bec6deba885af97fc87 Mon Sep 17 00:00:00 2001 From: Fabien Parent Date: Tue, 26 Jul 2022 14:56:11 +0200 Subject: arm64: dts: mediatek: mt8183: add keyboard node MT8183 has an on-SoC keyboard controller commonly used for volume up/down buttons. List it in the SoC dts so that boards can enable/use it. Signed-off-by: Fabien Parent Signed-off-by: Mattijs Korpershoek Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20220720-mt8183-keypad-v2-6-6d42c357cb76@baylibre.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8183.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi index 1543876b1e3c..71589489b306 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -943,6 +943,15 @@ clock-names = "spi", "wrap"; }; + keyboard: keyboard@10010000 { + compatible = "mediatek,mt6779-keypad"; + reg = <0 0x10010000 0 0x1000>; + interrupts = ; + clocks = <&clk26m>; + clock-names = "kpd"; + status = "disabled"; + }; + scp: scp@10500000 { compatible = "mediatek,mt8183-scp"; reg = <0 0x10500000 0 0x80000>, -- cgit v1.2.3-59-g8ed1b From 09c332027d87cfda9ff58bb84952f6ffefbd309e Mon Sep 17 00:00:00 2001 From: Fabien Parent Date: Tue, 26 Jul 2022 14:56:12 +0200 Subject: arm64: dts: mediatek: mt8183-pumpkin: add keypad support Add device-tree bindings for the keypad driver on the MT8183 Pumpkin board. The MT8183 Pumpkin board has 2 buttons connected using: KPROW0, KPROW1 and KPCOL0. Signed-off-by: Fabien Parent Signed-off-by: Mattijs Korpershoek Link: https://lore.kernel.org/r/20220720-mt8183-keypad-v2-7-6d42c357cb76@baylibre.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts b/arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts index 530e0c9ce0c9..a1d01639df30 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts +++ b/arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts @@ -7,6 +7,7 @@ /dts-v1/; #include +#include #include "mt8183.dtsi" #include "mt6358.dtsi" @@ -122,6 +123,18 @@ clock-frequency = <100000>; }; +&keyboard { + pinctrl-names = "default"; + pinctrl-0 = <&keyboard_pins>; + status = "okay"; + linux,keymap = ; + keypad,num-rows = <2>; + keypad,num-columns = <1>; + debounce-delay-ms = <32>; + mediatek,keys-per-group = <2>; +}; + &mmc0 { status = "okay"; pinctrl-names = "default", "state_uhs"; @@ -226,6 +239,14 @@ }; }; + keyboard_pins: keyboard { + pins_keyboard { + pinmux = , + , + ; + }; + }; + mmc0_pins_default: mmc0-pins-default { pins_cmd_dat { pinmux = , -- cgit v1.2.3-59-g8ed1b From d3dfd468857479a13285929f96132ae394f76f0a Mon Sep 17 00:00:00 2001 From: Tinghan Shen Date: Thu, 11 Aug 2022 10:58:00 +0800 Subject: arm64: dts: mediatek: Update mt81xx scpsys node to align with dt-bindings Update scpsys nodes using simple-mfd in mt81xx SoC devicetree to align with the bindings. Add specific compatibles for syscon node, even it's a dummy compatible, because syscon node must come with a specific compatible. Remove the '#power-domain-cells" propertry since the simple-mfd node is not the power domain provider; the provider is the child node. Signed-off-by: Tinghan Shen Link: https://lore.kernel.org/r/20220811025813.21492-8-tinghan.shen@mediatek.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8167.dtsi | 3 +-- arch/arm64/boot/dts/mediatek/mt8173.dtsi | 3 +-- arch/arm64/boot/dts/mediatek/mt8183.dtsi | 3 +-- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 3 +-- 4 files changed, 4 insertions(+), 8 deletions(-) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/mediatek/mt8167.dtsi b/arch/arm64/boot/dts/mediatek/mt8167.dtsi index 54655f2feb04..fbe1a1128cc6 100644 --- a/arch/arm64/boot/dts/mediatek/mt8167.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8167.dtsi @@ -36,9 +36,8 @@ }; scpsys: syscon@10006000 { - compatible = "syscon", "simple-mfd"; + compatible = "mediatek,mt8167-scpsys", "syscon", "simple-mfd"; reg = <0 0x10006000 0 0x1000>; - #power-domain-cells = <1>; spm: power-controller { compatible = "mediatek,mt8167-power-controller"; diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi index 6d9513c1f5bf..b4d48f8b7eeb 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi @@ -444,9 +444,8 @@ }; scpsys: syscon@10006000 { - compatible = "syscon", "simple-mfd"; + compatible = "mediatek,mt8173-scpsys", "syscon", "simple-mfd"; reg = <0 0x10006000 0 0x1000>; - #power-domain-cells = <1>; /* System Power Manager */ spm: power-controller { diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi index 71589489b306..a70b669c49ba 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -761,9 +761,8 @@ }; scpsys: syscon@10006000 { - compatible = "syscon", "simple-mfd"; + compatible = "mediatek,mt8183-scpsys", "syscon", "simple-mfd"; reg = <0 0x10006000 0 0x1000>; - #power-domain-cells = <1>; /* System Power Manager */ spm: power-controller { diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index cbae5a5ee4a0..8cd5906fe3a8 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -306,9 +306,8 @@ }; scpsys: syscon@10006000 { - compatible = "syscon", "simple-mfd"; + compatible = "mediatek,mt8192-scpsys", "syscon", "simple-mfd"; reg = <0 0x10006000 0 0x1000>; - #power-domain-cells = <1>; /* System Power Manager */ spm: power-controller { -- cgit v1.2.3-59-g8ed1b From a376a9a6491431587992e3d4319466d9adba1b58 Mon Sep 17 00:00:00 2001 From: Tinghan Shen Date: Thu, 11 Aug 2022 10:58:01 +0800 Subject: arm64: dts: mt8195: Disable watchdog external reset signal Disable the external output reset signal of watchdog reset to avoid losing the reset reason stored in the watchdog registers. Signed-off-by: Fengquan Chen Signed-off-by: Tinghan Shen Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20220811025813.21492-9-tinghan.shen@mediatek.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index 066c14989708..436687ba826f 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -327,6 +327,7 @@ watchdog: watchdog@10007000 { compatible = "mediatek,mt8195-wdt", "mediatek,mt6589-wdt"; + mediatek,disable-extrst; reg = <0 0x10007000 0 0x100>; }; -- cgit v1.2.3-59-g8ed1b From a93f071a753a2f3fb7ff0acff588ade7679c92aa Mon Sep 17 00:00:00 2001 From: Tzung-Bi Shih Date: Thu, 11 Aug 2022 10:58:02 +0800 Subject: arm64: dts: mt8195: Disable I2C0 node The I2C0 node should not be enabled globally, as usage is board dependent; disable it in dtsi. Signed-off-by: Tzung-Bi Shih Signed-off-by: Tinghan Shen Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20220811025813.21492-10-tinghan.shen@mediatek.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index 436687ba826f..8032b839dfe8 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -829,7 +829,7 @@ clock-names = "main", "dma"; #address-cells = <1>; #size-cells = <0>; - status = "okay"; + status = "disabled"; }; i2c1: i2c@11e01000 { -- cgit v1.2.3-59-g8ed1b From e39e72cffea3288d3b1f27e0e05ce6c2d18b8735 Mon Sep 17 00:00:00 2001 From: YT Lee Date: Thu, 11 Aug 2022 10:58:03 +0800 Subject: arm64: dts: mt8195: Add cpufreq node Add cpufreq node for mt8195. Signed-off-by: YT Lee Signed-off-by: Tinghan Shen Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20220811025813.21492-11-tinghan.shen@mediatek.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index 8032b839dfe8..900aaa16f862 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -26,6 +26,7 @@ compatible = "arm,cortex-a55"; reg = <0x000>; enable-method = "psci"; + performance-domains = <&performance 0>; clock-frequency = <1701000000>; capacity-dmips-mhz = <578>; cpu-idle-states = <&cpu_off_l &cluster_off_l>; @@ -38,6 +39,7 @@ compatible = "arm,cortex-a55"; reg = <0x100>; enable-method = "psci"; + performance-domains = <&performance 0>; clock-frequency = <1701000000>; capacity-dmips-mhz = <578>; cpu-idle-states = <&cpu_off_l &cluster_off_l>; @@ -50,6 +52,7 @@ compatible = "arm,cortex-a55"; reg = <0x200>; enable-method = "psci"; + performance-domains = <&performance 0>; clock-frequency = <1701000000>; capacity-dmips-mhz = <578>; cpu-idle-states = <&cpu_off_l &cluster_off_l>; @@ -62,6 +65,7 @@ compatible = "arm,cortex-a55"; reg = <0x300>; enable-method = "psci"; + performance-domains = <&performance 0>; clock-frequency = <1701000000>; capacity-dmips-mhz = <578>; cpu-idle-states = <&cpu_off_l &cluster_off_l>; @@ -74,6 +78,7 @@ compatible = "arm,cortex-a78"; reg = <0x400>; enable-method = "psci"; + performance-domains = <&performance 1>; clock-frequency = <2171000000>; capacity-dmips-mhz = <1024>; cpu-idle-states = <&cpu_off_b &cluster_off_b>; @@ -86,6 +91,7 @@ compatible = "arm,cortex-a78"; reg = <0x500>; enable-method = "psci"; + performance-domains = <&performance 1>; clock-frequency = <2171000000>; capacity-dmips-mhz = <1024>; cpu-idle-states = <&cpu_off_b &cluster_off_b>; @@ -98,6 +104,7 @@ compatible = "arm,cortex-a78"; reg = <0x600>; enable-method = "psci"; + performance-domains = <&performance 1>; clock-frequency = <2171000000>; capacity-dmips-mhz = <1024>; cpu-idle-states = <&cpu_off_b &cluster_off_b>; @@ -110,6 +117,7 @@ compatible = "arm,cortex-a78"; reg = <0x700>; enable-method = "psci"; + performance-domains = <&performance 1>; clock-frequency = <2171000000>; capacity-dmips-mhz = <1024>; cpu-idle-states = <&cpu_off_b &cluster_off_b>; @@ -231,6 +239,12 @@ clock-output-names = "clk32k"; }; + performance: performance-controller@11bc10 { + compatible = "mediatek,cpufreq-hw"; + reg = <0 0x0011bc10 0 0x120>, <0 0x0011bd30 0 0x120>; + #performance-domain-cells = <1>; + }; + pmu-a55 { compatible = "arm,cortex-a55-pmu"; interrupt-parent = <&gic>; -- cgit v1.2.3-59-g8ed1b From 6aa5b46d1755a2e3db86fa6bd3f3d15d3c012594 Mon Sep 17 00:00:00 2001 From: Tinghan Shen Date: Thu, 11 Aug 2022 10:58:04 +0800 Subject: arm64: dts: mt8195: Add vdosys and vppsys clock nodes Add display clock nodes. Signed-off-by: Tinghan Shen Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20220811025813.21492-12-tinghan.shen@mediatek.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index 900aaa16f862..8d59a7da3271 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -983,6 +983,12 @@ #clock-cells = <1>; }; + vppsys0: clock-controller@14000000 { + compatible = "mediatek,mt8195-vppsys0"; + reg = <0 0x14000000 0 0x1000>; + #clock-cells = <1>; + }; + wpesys: clock-controller@14e00000 { compatible = "mediatek,mt8195-wpesys"; reg = <0 0x14e00000 0 0x1000>; @@ -1001,6 +1007,12 @@ #clock-cells = <1>; }; + vppsys1: clock-controller@14f00000 { + compatible = "mediatek,mt8195-vppsys1"; + reg = <0 0x14f00000 0 0x1000>; + #clock-cells = <1>; + }; + imgsys: clock-controller@15000000 { compatible = "mediatek,mt8195-imgsys"; reg = <0 0x15000000 0 0x1000>; @@ -1108,5 +1120,17 @@ reg = <0 0x1b000000 0 0x1000>; #clock-cells = <1>; }; + + vdosys0: syscon@1c01a000 { + compatible = "mediatek,mt8195-mmsys", "syscon"; + reg = <0 0x1c01a000 0 0x1000>; + #clock-cells = <1>; + }; + + vdosys1: syscon@1c100000 { + compatible = "mediatek,mt8195-mmsys", "syscon"; + reg = <0 0x1c100000 0 0x1000>; + #clock-cells = <1>; + }; }; }; -- cgit v1.2.3-59-g8ed1b From 2b515194bf0cb8f380586e96d2530a51b1878e6a Mon Sep 17 00:00:00 2001 From: Tinghan Shen Date: Thu, 11 Aug 2022 10:58:05 +0800 Subject: arm64: dts: mt8195: Add power domains controller Add power domains controller node for mt8195. Signed-off-by: Weiyi Lu Signed-off-by: Tinghan Shen Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20220811025813.21492-13-tinghan.shen@mediatek.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 326 +++++++++++++++++++++++++++++++ 1 file changed, 326 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index 8d59a7da3271..7e77aecb1296 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -10,6 +10,7 @@ #include #include #include +#include / { compatible = "mediatek,mt8195"; @@ -338,6 +339,331 @@ #interrupt-cells = <2>; }; + scpsys: syscon@10006000 { + compatible = "mediatek,mt8195-scpsys", "syscon", "simple-mfd"; + reg = <0 0x10006000 0 0x1000>; + + /* System Power Manager */ + spm: power-controller { + compatible = "mediatek,mt8195-power-controller"; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + /* power domain of the SoC */ + mfg0: power-domain@MT8195_POWER_DOMAIN_MFG0 { + reg = ; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + power-domain@MT8195_POWER_DOMAIN_MFG1 { + reg = ; + clocks = <&apmixedsys CLK_APMIXED_MFGPLL>; + clock-names = "mfg"; + mediatek,infracfg = <&infracfg_ao>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + power-domain@MT8195_POWER_DOMAIN_MFG2 { + reg = ; + #power-domain-cells = <0>; + }; + + power-domain@MT8195_POWER_DOMAIN_MFG3 { + reg = ; + #power-domain-cells = <0>; + }; + + power-domain@MT8195_POWER_DOMAIN_MFG4 { + reg = ; + #power-domain-cells = <0>; + }; + + power-domain@MT8195_POWER_DOMAIN_MFG5 { + reg = ; + #power-domain-cells = <0>; + }; + + power-domain@MT8195_POWER_DOMAIN_MFG6 { + reg = ; + #power-domain-cells = <0>; + }; + }; + }; + + power-domain@MT8195_POWER_DOMAIN_VPPSYS0 { + reg = ; + clocks = <&topckgen CLK_TOP_VPP>, + <&topckgen CLK_TOP_CAM>, + <&topckgen CLK_TOP_CCU>, + <&topckgen CLK_TOP_IMG>, + <&topckgen CLK_TOP_VENC>, + <&topckgen CLK_TOP_VDEC>, + <&topckgen CLK_TOP_WPE_VPP>, + <&topckgen CLK_TOP_CFG_VPP0>, + <&vppsys0 CLK_VPP0_SMI_COMMON>, + <&vppsys0 CLK_VPP0_GALS_VDO0_LARB0>, + <&vppsys0 CLK_VPP0_GALS_VDO0_LARB1>, + <&vppsys0 CLK_VPP0_GALS_VENCSYS>, + <&vppsys0 CLK_VPP0_GALS_VENCSYS_CORE1>, + <&vppsys0 CLK_VPP0_GALS_INFRA>, + <&vppsys0 CLK_VPP0_GALS_CAMSYS>, + <&vppsys0 CLK_VPP0_GALS_VPP1_LARB5>, + <&vppsys0 CLK_VPP0_GALS_VPP1_LARB6>, + <&vppsys0 CLK_VPP0_SMI_REORDER>, + <&vppsys0 CLK_VPP0_SMI_IOMMU>, + <&vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS>, + <&vppsys0 CLK_VPP0_GALS_EMI0_EMI1>, + <&vppsys0 CLK_VPP0_SMI_SUB_COMMON_REORDER>, + <&vppsys0 CLK_VPP0_SMI_RSI>, + <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>, + <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>, + <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>, + <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>; + clock-names = "vppsys", "vppsys1", "vppsys2", "vppsys3", + "vppsys4", "vppsys5", "vppsys6", "vppsys7", + "vppsys0-0", "vppsys0-1", "vppsys0-2", "vppsys0-3", + "vppsys0-4", "vppsys0-5", "vppsys0-6", "vppsys0-7", + "vppsys0-8", "vppsys0-9", "vppsys0-10", "vppsys0-11", + "vppsys0-12", "vppsys0-13", "vppsys0-14", + "vppsys0-15", "vppsys0-16", "vppsys0-17", + "vppsys0-18"; + mediatek,infracfg = <&infracfg_ao>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + power-domain@MT8195_POWER_DOMAIN_VDEC1 { + reg = ; + clocks = <&vdecsys CLK_VDEC_LARB1>; + clock-names = "vdec1-0"; + mediatek,infracfg = <&infracfg_ao>; + #power-domain-cells = <0>; + }; + + power-domain@MT8195_POWER_DOMAIN_VENC_CORE1 { + reg = ; + mediatek,infracfg = <&infracfg_ao>; + #power-domain-cells = <0>; + }; + + power-domain@MT8195_POWER_DOMAIN_VDOSYS0 { + reg = ; + clocks = <&topckgen CLK_TOP_CFG_VDO0>, + <&vdosys0 CLK_VDO0_SMI_GALS>, + <&vdosys0 CLK_VDO0_SMI_COMMON>, + <&vdosys0 CLK_VDO0_SMI_EMI>, + <&vdosys0 CLK_VDO0_SMI_IOMMU>, + <&vdosys0 CLK_VDO0_SMI_LARB>, + <&vdosys0 CLK_VDO0_SMI_RSI>; + clock-names = "vdosys0", "vdosys0-0", "vdosys0-1", + "vdosys0-2", "vdosys0-3", + "vdosys0-4", "vdosys0-5"; + mediatek,infracfg = <&infracfg_ao>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + power-domain@MT8195_POWER_DOMAIN_VPPSYS1 { + reg = ; + clocks = <&topckgen CLK_TOP_CFG_VPP1>, + <&vppsys1 CLK_VPP1_VPPSYS1_GALS>, + <&vppsys1 CLK_VPP1_VPPSYS1_LARB>; + clock-names = "vppsys1", "vppsys1-0", + "vppsys1-1"; + mediatek,infracfg = <&infracfg_ao>; + #power-domain-cells = <0>; + }; + + power-domain@MT8195_POWER_DOMAIN_WPESYS { + reg = ; + clocks = <&wpesys CLK_WPE_SMI_LARB7>, + <&wpesys CLK_WPE_SMI_LARB8>, + <&wpesys CLK_WPE_SMI_LARB7_P>, + <&wpesys CLK_WPE_SMI_LARB8_P>; + clock-names = "wepsys-0", "wepsys-1", "wepsys-2", + "wepsys-3"; + mediatek,infracfg = <&infracfg_ao>; + #power-domain-cells = <0>; + }; + + power-domain@MT8195_POWER_DOMAIN_VDEC0 { + reg = ; + clocks = <&vdecsys_soc CLK_VDEC_SOC_LARB1>; + clock-names = "vdec0-0"; + mediatek,infracfg = <&infracfg_ao>; + #power-domain-cells = <0>; + }; + + power-domain@MT8195_POWER_DOMAIN_VDEC2 { + reg = ; + clocks = <&vdecsys_core1 CLK_VDEC_CORE1_LARB1>; + clock-names = "vdec2-0"; + mediatek,infracfg = <&infracfg_ao>; + #power-domain-cells = <0>; + }; + + power-domain@MT8195_POWER_DOMAIN_VENC { + reg = ; + mediatek,infracfg = <&infracfg_ao>; + #power-domain-cells = <0>; + }; + + power-domain@MT8195_POWER_DOMAIN_VDOSYS1 { + reg = ; + clocks = <&topckgen CLK_TOP_CFG_VDO1>, + <&vdosys1 CLK_VDO1_SMI_LARB2>, + <&vdosys1 CLK_VDO1_SMI_LARB3>, + <&vdosys1 CLK_VDO1_GALS>; + clock-names = "vdosys1", "vdosys1-0", + "vdosys1-1", "vdosys1-2"; + mediatek,infracfg = <&infracfg_ao>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + power-domain@MT8195_POWER_DOMAIN_DP_TX { + reg = ; + mediatek,infracfg = <&infracfg_ao>; + #power-domain-cells = <0>; + }; + + power-domain@MT8195_POWER_DOMAIN_EPD_TX { + reg = ; + mediatek,infracfg = <&infracfg_ao>; + #power-domain-cells = <0>; + }; + + power-domain@MT8195_POWER_DOMAIN_HDMI_TX { + reg = ; + clocks = <&topckgen CLK_TOP_HDMI_APB>; + clock-names = "hdmi_tx"; + #power-domain-cells = <0>; + }; + }; + + power-domain@MT8195_POWER_DOMAIN_IMG { + reg = ; + clocks = <&imgsys CLK_IMG_LARB9>, + <&imgsys CLK_IMG_GALS>; + clock-names = "img-0", "img-1"; + mediatek,infracfg = <&infracfg_ao>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + power-domain@MT8195_POWER_DOMAIN_DIP { + reg = ; + #power-domain-cells = <0>; + }; + + power-domain@MT8195_POWER_DOMAIN_IPE { + reg = ; + clocks = <&topckgen CLK_TOP_IPE>, + <&imgsys CLK_IMG_IPE>, + <&ipesys CLK_IPE_SMI_LARB12>; + clock-names = "ipe", "ipe-0", "ipe-1"; + mediatek,infracfg = <&infracfg_ao>; + #power-domain-cells = <0>; + }; + }; + + power-domain@MT8195_POWER_DOMAIN_CAM { + reg = ; + clocks = <&camsys CLK_CAM_LARB13>, + <&camsys CLK_CAM_LARB14>, + <&camsys CLK_CAM_CAM2MM0_GALS>, + <&camsys CLK_CAM_CAM2MM1_GALS>, + <&camsys CLK_CAM_CAM2SYS_GALS>; + clock-names = "cam-0", "cam-1", "cam-2", "cam-3", + "cam-4"; + mediatek,infracfg = <&infracfg_ao>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + power-domain@MT8195_POWER_DOMAIN_CAM_RAWA { + reg = ; + #power-domain-cells = <0>; + }; + + power-domain@MT8195_POWER_DOMAIN_CAM_RAWB { + reg = ; + #power-domain-cells = <0>; + }; + + power-domain@MT8195_POWER_DOMAIN_CAM_MRAW { + reg = ; + #power-domain-cells = <0>; + }; + }; + }; + }; + + power-domain@MT8195_POWER_DOMAIN_PCIE_MAC_P0 { + reg = ; + mediatek,infracfg = <&infracfg_ao>; + #power-domain-cells = <0>; + }; + + power-domain@MT8195_POWER_DOMAIN_PCIE_MAC_P1 { + reg = ; + mediatek,infracfg = <&infracfg_ao>; + #power-domain-cells = <0>; + }; + + power-domain@MT8195_POWER_DOMAIN_PCIE_PHY { + reg = ; + #power-domain-cells = <0>; + }; + + power-domain@MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY { + reg = ; + #power-domain-cells = <0>; + }; + + power-domain@MT8195_POWER_DOMAIN_CSI_RX_TOP { + reg = ; + clocks = <&topckgen CLK_TOP_SENINF>, + <&topckgen CLK_TOP_SENINF2>; + clock-names = "csi_rx_top", "csi_rx_top1"; + #power-domain-cells = <0>; + }; + + power-domain@MT8195_POWER_DOMAIN_ETHER { + reg = ; + clocks = <&pericfg_ao CLK_PERI_AO_ETHERNET_MAC>; + clock-names = "ether"; + #power-domain-cells = <0>; + }; + + power-domain@MT8195_POWER_DOMAIN_ADSP { + reg = ; + clocks = <&topckgen CLK_TOP_ADSP>, + <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>; + clock-names = "adsp", "adsp1"; + #address-cells = <1>; + #size-cells = <0>; + mediatek,infracfg = <&infracfg_ao>; + #power-domain-cells = <1>; + + power-domain@MT8195_POWER_DOMAIN_AUDIO { + reg = ; + clocks = <&topckgen CLK_TOP_A1SYS_HP>, + <&topckgen CLK_TOP_AUD_INTBUS>, + <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>, + <&infracfg_ao CLK_INFRA_AO_AUDIO_26M_B>; + clock-names = "audio", "audio1", "audio2", + "audio3"; + mediatek,infracfg = <&infracfg_ao>; + #power-domain-cells = <0>; + }; + }; + }; + }; + watchdog: watchdog@10007000 { compatible = "mediatek,mt8195-wdt", "mediatek,mt6589-wdt"; -- cgit v1.2.3-59-g8ed1b From 385e0eedb7ab8069894c59455892dd916acb4456 Mon Sep 17 00:00:00 2001 From: Tinghan Shen Date: Thu, 11 Aug 2022 10:58:06 +0800 Subject: arm64: dts: mt8195: Add spmi node Add spmi node to mt8195. Signed-off-by: Henry Chen Signed-off-by: Tinghan Shen Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20220811025813.21492-14-tinghan.shen@mediatek.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index 7e77aecb1296..da2d976ff844 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -697,6 +697,21 @@ assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>; }; + spmi: spmi@10027000 { + compatible = "mediatek,mt8195-spmi"; + reg = <0 0x10027000 0 0x000e00>, + <0 0x10029000 0 0x000100>; + reg-names = "pmif", "spmimst"; + clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>, + <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>, + <&topckgen CLK_TOP_SPMI_M_MST>; + clock-names = "pmif_sys_ck", + "pmif_tmr_ck", + "spmimst_clk_mux"; + assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC>; + assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>; + }; + scp_adsp: clock-controller@10720000 { compatible = "mediatek,mt8195-scp_adsp"; reg = <0 0x10720000 0 0x1000>; -- cgit v1.2.3-59-g8ed1b From 867477a5d39fc614151f77bf036c50a29d5ead7f Mon Sep 17 00:00:00 2001 From: Tinghan Shen Date: Thu, 11 Aug 2022 10:58:07 +0800 Subject: arm64: dts: mt8195: Add scp node Add scp node for mt8195. Signed-off-by: Tinghan Shen Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20220811025813.21492-15-tinghan.shen@mediatek.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index da2d976ff844..d10db01a360a 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -712,6 +712,16 @@ assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>; }; + scp: scp@10500000 { + compatible = "mediatek,mt8195-scp"; + reg = <0 0x10500000 0 0x100000>, + <0 0x10720000 0 0xe0000>, + <0 0x10700000 0 0x8000>; + reg-names = "sram", "cfg", "l1tcm"; + interrupts = ; + status = "disabled"; + }; + scp_adsp: clock-controller@10720000 { compatible = "mediatek,mt8195-scp_adsp"; reg = <0 0x10720000 0 0x1000>; -- cgit v1.2.3-59-g8ed1b From 8903821c8ef9fe89ef20401f2261d2cfcdb0c386 Mon Sep 17 00:00:00 2001 From: Tinghan Shen Date: Thu, 11 Aug 2022 10:58:08 +0800 Subject: arm64: dts: mt8195: Add audio related nodes Add audio related nodes for mt8195. Signed-off-by: Trevor Wu Signed-off-by: Tinghan Shen Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20220811025813.21492-16-tinghan.shen@mediatek.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 58 ++++++++++++++++++++++++++++++++ 1 file changed, 58 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index d10db01a360a..bbea0acff3d2 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -226,6 +226,17 @@ <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>; }; + dmic_codec: dmic-codec { + compatible = "dmic-codec"; + num-channels = <2>; + wakeup-delay-ms = <50>; + }; + + sound: mt8195-sound { + mediatek,platform = <&afe>; + status = "disabled"; + }; + clk26m: oscillator-26m { compatible = "fixed-clock"; #clock-cells = <0>; @@ -728,6 +739,53 @@ #clock-cells = <1>; }; + afe: mt8195-afe-pcm@10890000 { + compatible = "mediatek,mt8195-audio"; + reg = <0 0x10890000 0 0x10000>; + mediatek,topckgen = <&topckgen>; + power-domains = <&spm MT8195_POWER_DOMAIN_AUDIO>; + interrupts = ; + clocks = <&clk26m>, + <&apmixedsys CLK_APMIXED_APLL1>, + <&apmixedsys CLK_APMIXED_APLL2>, + <&topckgen CLK_TOP_APLL12_DIV0>, + <&topckgen CLK_TOP_APLL12_DIV1>, + <&topckgen CLK_TOP_APLL12_DIV2>, + <&topckgen CLK_TOP_APLL12_DIV3>, + <&topckgen CLK_TOP_APLL12_DIV9>, + <&topckgen CLK_TOP_A1SYS_HP>, + <&topckgen CLK_TOP_AUD_INTBUS>, + <&topckgen CLK_TOP_AUDIO_H>, + <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>, + <&topckgen CLK_TOP_DPTX_MCK>, + <&topckgen CLK_TOP_I2SO1_MCK>, + <&topckgen CLK_TOP_I2SO2_MCK>, + <&topckgen CLK_TOP_I2SI1_MCK>, + <&topckgen CLK_TOP_I2SI2_MCK>, + <&infracfg_ao CLK_INFRA_AO_AUDIO_26M_B>, + <&scp_adsp CLK_SCP_ADSP_AUDIODSP>; + clock-names = "clk26m", + "apll1_ck", + "apll2_ck", + "apll12_div0", + "apll12_div1", + "apll12_div2", + "apll12_div3", + "apll12_div9", + "a1sys_hp_sel", + "aud_intbus_sel", + "audio_h_sel", + "audio_local_bus_sel", + "dptx_m_sel", + "i2so1_m_sel", + "i2so2_m_sel", + "i2si1_m_sel", + "i2si2_m_sel", + "infra_ao_audio_26m_b", + "scp_adsp_audiodsp"; + status = "disabled"; + }; + uart0: serial@11001100 { compatible = "mediatek,mt8195-uart", "mediatek,mt6577-uart"; -- cgit v1.2.3-59-g8ed1b From 7dd5bc578974a96025cb120012706bb4bf4e41fc Mon Sep 17 00:00:00 2001 From: YC Hung Date: Thu, 11 Aug 2022 10:58:09 +0800 Subject: arm64: dts: mt8195: Add adsp node and adsp mailbox nodes Add adsp node and adsp mailbox nodes for mt8195. Signed-off-by: YC Hung Signed-off-by: Allen-KH Cheng Signed-off-by: Tinghan Shen Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20220811025813.21492-17-tinghan.shen@mediatek.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 37 ++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index bbea0acff3d2..f42d33414125 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -739,6 +739,43 @@ #clock-cells = <1>; }; + adsp: dsp@10803000 { + compatible = "mediatek,mt8195-dsp"; + reg = <0 0x10803000 0 0x1000>, + <0 0x10840000 0 0x40000>; + reg-names = "cfg", "sram"; + clocks = <&topckgen CLK_TOP_ADSP>, + <&clk26m>, + <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>, + <&topckgen CLK_TOP_MAINPLL_D7_D2>, + <&scp_adsp CLK_SCP_ADSP_AUDIODSP>, + <&topckgen CLK_TOP_AUDIO_H>; + clock-names = "adsp_sel", + "clk26m_ck", + "audio_local_bus", + "mainpll_d7_d2", + "scp_adsp_audiodsp", + "audio_h"; + power-domains = <&spm MT8195_POWER_DOMAIN_ADSP>; + mbox-names = "rx", "tx"; + mboxes = <&adsp_mailbox0>, <&adsp_mailbox1>; + status = "disabled"; + }; + + adsp_mailbox0: mailbox@10816000 { + compatible = "mediatek,mt8195-adsp-mbox"; + #mbox-cells = <0>; + reg = <0 0x10816000 0 0x1000>; + interrupts = ; + }; + + adsp_mailbox1: mailbox@10817000 { + compatible = "mediatek,mt8195-adsp-mbox"; + #mbox-cells = <0>; + reg = <0 0x10817000 0 0x1000>; + interrupts = ; + }; + afe: mt8195-afe-pcm@10890000 { compatible = "mediatek,mt8195-audio"; reg = <0 0x10890000 0 0x10000>; -- cgit v1.2.3-59-g8ed1b From 04cd978316c992711f341b0c91fdb44f2c21836b Mon Sep 17 00:00:00 2001 From: Trevor Wu Date: Thu, 11 Aug 2022 10:58:10 +0800 Subject: arm64: dts: mt8195: Specify audio reset controller Specify audio reset controller for audio hardware resetting. Signed-off-by: Trevor Wu Signed-off-by: Tinghan Shen Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20220811025813.21492-18-tinghan.shen@mediatek.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 3 +++ 1 file changed, 3 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index f42d33414125..9c14c42f0713 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -680,6 +680,7 @@ "mediatek,mt6589-wdt"; mediatek,disable-extrst; reg = <0 0x10007000 0 0x100>; + #reset-cells = <1>; }; apmixedsys: syscon@1000c000 { @@ -782,6 +783,8 @@ mediatek,topckgen = <&topckgen>; power-domains = <&spm MT8195_POWER_DOMAIN_AUDIO>; interrupts = ; + resets = <&watchdog 14>; + reset-names = "audiosys"; clocks = <&clk26m>, <&apmixedsys CLK_APMIXED_APLL1>, <&apmixedsys CLK_APMIXED_APLL2>, -- cgit v1.2.3-59-g8ed1b From 3b5838d1d82e381e31bc3d13398f08d69b98be5d Mon Sep 17 00:00:00 2001 From: Tinghan Shen Date: Thu, 11 Aug 2022 10:58:11 +0800 Subject: arm64: dts: mt8195: Add iommu and smi nodes Add iommu nodes and smi nodes for mt8195. Signed-off-by: Yong Wu Signed-off-by: Tinghan Shen Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20220811025813.21492-19-tinghan.shen@mediatek.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 449 +++++++++++++++++++++++++++++++ 1 file changed, 449 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index 9c14c42f0713..f1f52af3823a 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -724,6 +725,17 @@ assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>; }; + iommu_infra: infra-iommu@10315000 { + compatible = "mediatek,mt8195-iommu-infra"; + reg = <0 0x10315000 0 0x5000>; + interrupts = , + , + , + , + ; + #iommu-cells = <1>; + }; + scp: scp@10500000 { compatible = "mediatek,mt8195-scp"; reg = <0 0x10500000 0 0x100000>, @@ -1438,6 +1450,64 @@ #clock-cells = <1>; }; + smi_sub_common_vpp0_vpp1_2x1: smi@14010000 { + compatible = "mediatek,mt8195-smi-sub-common"; + reg = <0 0x14010000 0 0x1000>; + clocks = <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>, + <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>, + <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>; + clock-names = "apb", "smi", "gals0"; + mediatek,smi = <&smi_common_vpp>; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; + }; + + smi_sub_common_vdec_vpp0_2x1: smi@14011000 { + compatible = "mediatek,mt8195-smi-sub-common"; + reg = <0 0x14011000 0 0x1000>; + clocks = <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>, + <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>, + <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>; + clock-names = "apb", "smi", "gals0"; + mediatek,smi = <&smi_common_vpp>; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; + }; + + smi_common_vpp: smi@14012000 { + compatible = "mediatek,mt8195-smi-common-vpp"; + reg = <0 0x14012000 0 0x1000>; + clocks = <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>, + <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>, + <&vppsys0 CLK_VPP0_SMI_RSI>, + <&vppsys0 CLK_VPP0_SMI_RSI>; + clock-names = "apb", "smi", "gals0", "gals1"; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; + }; + + larb4: larb@14013000 { + compatible = "mediatek,mt8195-smi-larb"; + reg = <0 0x14013000 0 0x1000>; + mediatek,larb-id = <4>; + mediatek,smi = <&smi_sub_common_vpp0_vpp1_2x1>; + clocks = <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>, + <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; + }; + + iommu_vpp: iommu@14018000 { + compatible = "mediatek,mt8195-iommu-vpp"; + reg = <0 0x14018000 0 0x1000>; + mediatek,larbs = <&larb1 &larb3 &larb4 &larb6 &larb8 + &larb12 &larb14 &larb16 &larb18 + &larb20 &larb22 &larb23 &larb26 + &larb27>; + interrupts = ; + clocks = <&vppsys0 CLK_VPP0_SMI_IOMMU>; + clock-names = "bclk"; + #iommu-cells = <1>; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; + }; + wpesys: clock-controller@14e00000 { compatible = "mediatek,mt8195-wpesys"; reg = <0 0x14e00000 0 0x1000>; @@ -1456,24 +1526,116 @@ #clock-cells = <1>; }; + larb7: larb@14e04000 { + compatible = "mediatek,mt8195-smi-larb"; + reg = <0 0x14e04000 0 0x1000>; + mediatek,larb-id = <7>; + mediatek,smi = <&smi_common_vdo>; + clocks = <&wpesys CLK_WPE_SMI_LARB7>, + <&wpesys CLK_WPE_SMI_LARB7>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8195_POWER_DOMAIN_WPESYS>; + }; + + larb8: larb@14e05000 { + compatible = "mediatek,mt8195-smi-larb"; + reg = <0 0x14e05000 0 0x1000>; + mediatek,larb-id = <8>; + mediatek,smi = <&smi_common_vpp>; + clocks = <&wpesys CLK_WPE_SMI_LARB8>, + <&wpesys CLK_WPE_SMI_LARB8>, + <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>; + clock-names = "apb", "smi", "gals"; + power-domains = <&spm MT8195_POWER_DOMAIN_WPESYS>; + }; + vppsys1: clock-controller@14f00000 { compatible = "mediatek,mt8195-vppsys1"; reg = <0 0x14f00000 0 0x1000>; #clock-cells = <1>; }; + larb5: larb@14f02000 { + compatible = "mediatek,mt8195-smi-larb"; + reg = <0 0x14f02000 0 0x1000>; + mediatek,larb-id = <5>; + mediatek,smi = <&smi_common_vdo>; + clocks = <&vppsys1 CLK_VPP1_VPPSYS1_LARB>, + <&vppsys1 CLK_VPP1_VPPSYS1_GALS>, + <&vppsys0 CLK_VPP0_GALS_VPP1_LARB5>; + clock-names = "apb", "smi", "gals"; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + }; + + larb6: larb@14f03000 { + compatible = "mediatek,mt8195-smi-larb"; + reg = <0 0x14f03000 0 0x1000>; + mediatek,larb-id = <6>; + mediatek,smi = <&smi_sub_common_vpp0_vpp1_2x1>; + clocks = <&vppsys1 CLK_VPP1_VPPSYS1_LARB>, + <&vppsys1 CLK_VPP1_VPPSYS1_GALS>, + <&vppsys0 CLK_VPP0_GALS_VPP1_LARB6>; + clock-names = "apb", "smi", "gals"; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + }; + imgsys: clock-controller@15000000 { compatible = "mediatek,mt8195-imgsys"; reg = <0 0x15000000 0 0x1000>; #clock-cells = <1>; }; + larb9: larb@15001000 { + compatible = "mediatek,mt8195-smi-larb"; + reg = <0 0x15001000 0 0x1000>; + mediatek,larb-id = <9>; + mediatek,smi = <&smi_sub_common_img1_3x1>; + clocks = <&imgsys CLK_IMG_LARB9>, + <&imgsys CLK_IMG_LARB9>, + <&imgsys CLK_IMG_GALS>; + clock-names = "apb", "smi", "gals"; + power-domains = <&spm MT8195_POWER_DOMAIN_IMG>; + }; + + smi_sub_common_img0_3x1: smi@15002000 { + compatible = "mediatek,mt8195-smi-sub-common"; + reg = <0 0x15002000 0 0x1000>; + clocks = <&imgsys CLK_IMG_IPE>, + <&imgsys CLK_IMG_IPE>, + <&vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS>; + clock-names = "apb", "smi", "gals0"; + mediatek,smi = <&smi_common_vpp>; + power-domains = <&spm MT8195_POWER_DOMAIN_IMG>; + }; + + smi_sub_common_img1_3x1: smi@15003000 { + compatible = "mediatek,mt8195-smi-sub-common"; + reg = <0 0x15003000 0 0x1000>; + clocks = <&imgsys CLK_IMG_LARB9>, + <&imgsys CLK_IMG_LARB9>, + <&imgsys CLK_IMG_GALS>; + clock-names = "apb", "smi", "gals0"; + mediatek,smi = <&smi_common_vdo>; + power-domains = <&spm MT8195_POWER_DOMAIN_IMG>; + }; + imgsys1_dip_top: clock-controller@15110000 { compatible = "mediatek,mt8195-imgsys1_dip_top"; reg = <0 0x15110000 0 0x1000>; #clock-cells = <1>; }; + larb10: larb@15120000 { + compatible = "mediatek,mt8195-smi-larb"; + reg = <0 0x15120000 0 0x1000>; + mediatek,larb-id = <10>; + mediatek,smi = <&smi_sub_common_img1_3x1>; + clocks = <&imgsys CLK_IMG_DIP0>, + <&imgsys1_dip_top CLK_IMG1_DIP_TOP_LARB10>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8195_POWER_DOMAIN_DIP>; + }; + imgsys1_dip_nr: clock-controller@15130000 { compatible = "mediatek,mt8195-imgsys1_dip_nr"; reg = <0 0x15130000 0 0x1000>; @@ -1486,18 +1648,129 @@ #clock-cells = <1>; }; + larb11: larb@15230000 { + compatible = "mediatek,mt8195-smi-larb"; + reg = <0 0x15230000 0 0x1000>; + mediatek,larb-id = <11>; + mediatek,smi = <&smi_sub_common_img1_3x1>; + clocks = <&imgsys CLK_IMG_WPE0>, + <&imgsys1_wpe CLK_IMG1_WPE_LARB11>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8195_POWER_DOMAIN_DIP>; + }; + ipesys: clock-controller@15330000 { compatible = "mediatek,mt8195-ipesys"; reg = <0 0x15330000 0 0x1000>; #clock-cells = <1>; }; + larb12: larb@15340000 { + compatible = "mediatek,mt8195-smi-larb"; + reg = <0 0x15340000 0 0x1000>; + mediatek,larb-id = <12>; + mediatek,smi = <&smi_sub_common_img0_3x1>; + clocks = <&ipesys CLK_IPE_SMI_LARB12>, + <&ipesys CLK_IPE_SMI_LARB12>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8195_POWER_DOMAIN_IPE>; + }; + camsys: clock-controller@16000000 { compatible = "mediatek,mt8195-camsys"; reg = <0 0x16000000 0 0x1000>; #clock-cells = <1>; }; + larb13: larb@16001000 { + compatible = "mediatek,mt8195-smi-larb"; + reg = <0 0x16001000 0 0x1000>; + mediatek,larb-id = <13>; + mediatek,smi = <&smi_sub_common_cam_4x1>; + clocks = <&camsys CLK_CAM_LARB13>, + <&camsys CLK_CAM_LARB13>, + <&camsys CLK_CAM_CAM2MM0_GALS>; + clock-names = "apb", "smi", "gals"; + power-domains = <&spm MT8195_POWER_DOMAIN_CAM>; + }; + + larb14: larb@16002000 { + compatible = "mediatek,mt8195-smi-larb"; + reg = <0 0x16002000 0 0x1000>; + mediatek,larb-id = <14>; + mediatek,smi = <&smi_sub_common_cam_7x1>; + clocks = <&camsys CLK_CAM_LARB14>, + <&camsys CLK_CAM_LARB14>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8195_POWER_DOMAIN_CAM>; + }; + + smi_sub_common_cam_4x1: smi@16004000 { + compatible = "mediatek,mt8195-smi-sub-common"; + reg = <0 0x16004000 0 0x1000>; + clocks = <&camsys CLK_CAM_LARB13>, + <&camsys CLK_CAM_LARB13>, + <&camsys CLK_CAM_CAM2MM0_GALS>; + clock-names = "apb", "smi", "gals0"; + mediatek,smi = <&smi_common_vdo>; + power-domains = <&spm MT8195_POWER_DOMAIN_CAM>; + }; + + smi_sub_common_cam_7x1: smi@16005000 { + compatible = "mediatek,mt8195-smi-sub-common"; + reg = <0 0x16005000 0 0x1000>; + clocks = <&camsys CLK_CAM_LARB14>, + <&camsys CLK_CAM_CAM2MM1_GALS>, + <&vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS>; + clock-names = "apb", "smi", "gals0"; + mediatek,smi = <&smi_common_vpp>; + power-domains = <&spm MT8195_POWER_DOMAIN_CAM>; + }; + + larb16: larb@16012000 { + compatible = "mediatek,mt8195-smi-larb"; + reg = <0 0x16012000 0 0x1000>; + mediatek,larb-id = <16>; + mediatek,smi = <&smi_sub_common_cam_7x1>; + clocks = <&camsys_rawa CLK_CAM_RAWA_LARBX>, + <&camsys_rawa CLK_CAM_RAWA_LARBX>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWA>; + }; + + larb17: larb@16013000 { + compatible = "mediatek,mt8195-smi-larb"; + reg = <0 0x16013000 0 0x1000>; + mediatek,larb-id = <17>; + mediatek,smi = <&smi_sub_common_cam_4x1>; + clocks = <&camsys_yuva CLK_CAM_YUVA_LARBX>, + <&camsys_yuva CLK_CAM_YUVA_LARBX>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWA>; + }; + + larb27: larb@16014000 { + compatible = "mediatek,mt8195-smi-larb"; + reg = <0 0x16014000 0 0x1000>; + mediatek,larb-id = <27>; + mediatek,smi = <&smi_sub_common_cam_7x1>; + clocks = <&camsys_rawb CLK_CAM_RAWB_LARBX>, + <&camsys_rawb CLK_CAM_RAWB_LARBX>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWB>; + }; + + larb28: larb@16015000 { + compatible = "mediatek,mt8195-smi-larb"; + reg = <0 0x16015000 0 0x1000>; + mediatek,larb-id = <28>; + mediatek,smi = <&smi_sub_common_cam_4x1>; + clocks = <&camsys_yuvb CLK_CAM_YUVB_LARBX>, + <&camsys_yuvb CLK_CAM_YUVB_LARBX>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWB>; + }; + camsys_rawa: clock-controller@1604f000 { compatible = "mediatek,mt8195-camsys_rawa"; reg = <0 0x1604f000 0 0x1000>; @@ -1528,24 +1801,103 @@ #clock-cells = <1>; }; + larb25: larb@16141000 { + compatible = "mediatek,mt8195-smi-larb"; + reg = <0 0x16141000 0 0x1000>; + mediatek,larb-id = <25>; + mediatek,smi = <&smi_sub_common_cam_4x1>; + clocks = <&camsys CLK_CAM_LARB13>, + <&camsys_mraw CLK_CAM_MRAW_LARBX>, + <&camsys CLK_CAM_CAM2MM0_GALS>; + clock-names = "apb", "smi", "gals"; + power-domains = <&spm MT8195_POWER_DOMAIN_CAM_MRAW>; + }; + + larb26: larb@16142000 { + compatible = "mediatek,mt8195-smi-larb"; + reg = <0 0x16142000 0 0x1000>; + mediatek,larb-id = <26>; + mediatek,smi = <&smi_sub_common_cam_7x1>; + clocks = <&camsys_mraw CLK_CAM_MRAW_LARBX>, + <&camsys_mraw CLK_CAM_MRAW_LARBX>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8195_POWER_DOMAIN_CAM_MRAW>; + + }; + ccusys: clock-controller@17200000 { compatible = "mediatek,mt8195-ccusys"; reg = <0 0x17200000 0 0x1000>; #clock-cells = <1>; }; + larb18: larb@17201000 { + compatible = "mediatek,mt8195-smi-larb"; + reg = <0 0x17201000 0 0x1000>; + mediatek,larb-id = <18>; + mediatek,smi = <&smi_sub_common_cam_7x1>; + clocks = <&ccusys CLK_CCU_LARB18>, + <&ccusys CLK_CCU_LARB18>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8195_POWER_DOMAIN_CAM>; + }; + + larb24: larb@1800d000 { + compatible = "mediatek,mt8195-smi-larb"; + reg = <0 0x1800d000 0 0x1000>; + mediatek,larb-id = <24>; + mediatek,smi = <&smi_common_vdo>; + clocks = <&vdecsys_soc CLK_VDEC_SOC_LARB1>, + <&vdecsys_soc CLK_VDEC_SOC_LARB1>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>; + }; + + larb23: larb@1800e000 { + compatible = "mediatek,mt8195-smi-larb"; + reg = <0 0x1800e000 0 0x1000>; + mediatek,larb-id = <23>; + mediatek,smi = <&smi_sub_common_vdec_vpp0_2x1>; + clocks = <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>, + <&vdecsys_soc CLK_VDEC_SOC_LARB1>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>; + }; + vdecsys_soc: clock-controller@1800f000 { compatible = "mediatek,mt8195-vdecsys_soc"; reg = <0 0x1800f000 0 0x1000>; #clock-cells = <1>; }; + larb21: larb@1802e000 { + compatible = "mediatek,mt8195-smi-larb"; + reg = <0 0x1802e000 0 0x1000>; + mediatek,larb-id = <21>; + mediatek,smi = <&smi_common_vdo>; + clocks = <&vdecsys CLK_VDEC_LARB1>, + <&vdecsys CLK_VDEC_LARB1>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>; + }; + vdecsys: clock-controller@1802f000 { compatible = "mediatek,mt8195-vdecsys"; reg = <0 0x1802f000 0 0x1000>; #clock-cells = <1>; }; + larb22: larb@1803e000 { + compatible = "mediatek,mt8195-smi-larb"; + reg = <0 0x1803e000 0 0x1000>; + mediatek,larb-id = <22>; + mediatek,smi = <&smi_sub_common_vdec_vpp0_2x1>; + clocks = <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>, + <&vdecsys_core1 CLK_VDEC_CORE1_LARB1>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8195_POWER_DOMAIN_VDEC2>; + }; + vdecsys_core1: clock-controller@1803f000 { compatible = "mediatek,mt8195-vdecsys_core1"; reg = <0 0x1803f000 0 0x1000>; @@ -1564,6 +1916,17 @@ #clock-cells = <1>; }; + larb19: larb@1a010000 { + compatible = "mediatek,mt8195-smi-larb"; + reg = <0 0x1a010000 0 0x1000>; + mediatek,larb-id = <19>; + mediatek,smi = <&smi_common_vdo>; + clocks = <&vencsys CLK_VENC_VENC>, + <&vencsys CLK_VENC_GALS>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8195_POWER_DOMAIN_VENC>; + }; + vencsys_core1: clock-controller@1b000000 { compatible = "mediatek,mt8195-vencsys_core1"; reg = <0 0x1b000000 0 0x1000>; @@ -1576,10 +1939,96 @@ #clock-cells = <1>; }; + larb20: larb@1b010000 { + compatible = "mediatek,mt8195-smi-larb"; + reg = <0 0x1b010000 0 0x1000>; + mediatek,larb-id = <20>; + mediatek,smi = <&smi_common_vpp>; + clocks = <&vencsys_core1 CLK_VENC_CORE1_LARB>, + <&vencsys_core1 CLK_VENC_CORE1_GALS>, + <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>; + clock-names = "apb", "smi", "gals"; + power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>; + }; + + larb0: larb@1c018000 { + compatible = "mediatek,mt8195-smi-larb"; + reg = <0 0x1c018000 0 0x1000>; + mediatek,larb-id = <0>; + mediatek,smi = <&smi_common_vdo>; + clocks = <&vdosys0 CLK_VDO0_SMI_LARB>, + <&vdosys0 CLK_VDO0_SMI_LARB>, + <&vppsys0 CLK_VPP0_GALS_VDO0_LARB0>; + clock-names = "apb", "smi", "gals"; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; + }; + + larb1: larb@1c019000 { + compatible = "mediatek,mt8195-smi-larb"; + reg = <0 0x1c019000 0 0x1000>; + mediatek,larb-id = <1>; + mediatek,smi = <&smi_common_vpp>; + clocks = <&vdosys0 CLK_VDO0_SMI_LARB>, + <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>, + <&vppsys0 CLK_VPP0_GALS_VDO0_LARB1>; + clock-names = "apb", "smi", "gals"; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; + }; + vdosys1: syscon@1c100000 { compatible = "mediatek,mt8195-mmsys", "syscon"; reg = <0 0x1c100000 0 0x1000>; #clock-cells = <1>; }; + + smi_common_vdo: smi@1c01b000 { + compatible = "mediatek,mt8195-smi-common-vdo"; + reg = <0 0x1c01b000 0 0x1000>; + clocks = <&vdosys0 CLK_VDO0_SMI_COMMON>, + <&vdosys0 CLK_VDO0_SMI_EMI>, + <&vdosys0 CLK_VDO0_SMI_RSI>, + <&vdosys0 CLK_VDO0_SMI_GALS>; + clock-names = "apb", "smi", "gals0", "gals1"; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; + + }; + + iommu_vdo: iommu@1c01f000 { + compatible = "mediatek,mt8195-iommu-vdo"; + reg = <0 0x1c01f000 0 0x1000>; + mediatek,larbs = <&larb0 &larb2 &larb5 &larb7 &larb9 + &larb10 &larb11 &larb13 &larb17 + &larb19 &larb21 &larb24 &larb25 + &larb28>; + interrupts = ; + #iommu-cells = <1>; + clocks = <&vdosys0 CLK_VDO0_SMI_IOMMU>; + clock-names = "bclk"; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; + }; + + larb2: larb@1c102000 { + compatible = "mediatek,mt8195-smi-larb"; + reg = <0 0x1c102000 0 0x1000>; + mediatek,larb-id = <2>; + mediatek,smi = <&smi_common_vdo>; + clocks = <&vdosys1 CLK_VDO1_SMI_LARB2>, + <&vdosys1 CLK_VDO1_SMI_LARB2>, + <&vdosys1 CLK_VDO1_GALS>; + clock-names = "apb", "smi", "gals"; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; + }; + + larb3: larb@1c103000 { + compatible = "mediatek,mt8195-smi-larb"; + reg = <0 0x1c103000 0 0x1000>; + mediatek,larb-id = <3>; + mediatek,smi = <&smi_common_vpp>; + clocks = <&vdosys1 CLK_VDO1_SMI_LARB3>, + <&vdosys1 CLK_VDO1_GALS>, + <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>; + clock-names = "apb", "smi", "gals"; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; + }; }; }; -- cgit v1.2.3-59-g8ed1b From 329239a154bc735a74c33e33c5139b30949efc57 Mon Sep 17 00:00:00 2001 From: "Jason-JH.Lin" Date: Thu, 11 Aug 2022 10:58:12 +0800 Subject: arm64: dts: mt8195: Add gce node Add gce node and gce alias to mt8195 device tree. Signed-off-by: Jason-JH.Lin Signed-off-by: Tinghan Shen Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20220811025813.21492-20-tinghan.shen@mediatek.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index f1f52af3823a..5ad7c4200178 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -6,6 +6,7 @@ /dts-v1/; #include +#include #include #include #include @@ -19,6 +20,11 @@ #address-cells = <2>; #size-cells = <2>; + aliases { + gce0 = &gce0; + gce1 = &gce1; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -736,6 +742,22 @@ #iommu-cells = <1>; }; + gce0: mailbox@10320000 { + compatible = "mediatek,mt8195-gce"; + reg = <0 0x10320000 0 0x4000>; + interrupts = ; + #mbox-cells = <2>; + clocks = <&infracfg_ao CLK_INFRA_AO_GCE>; + }; + + gce1: mailbox@10330000 { + compatible = "mediatek,mt8195-gce"; + reg = <0 0x10330000 0 0x4000>; + interrupts = ; + #mbox-cells = <2>; + clocks = <&infracfg_ao CLK_INFRA_AO_GCE2>; + }; + scp: scp@10500000 { compatible = "mediatek,mt8195-scp"; reg = <0 0x10500000 0 0x100000>, -- cgit v1.2.3-59-g8ed1b From b852ee68fd722294145d86bb4d383d4ad4ae270f Mon Sep 17 00:00:00 2001 From: "Jason-JH.Lin" Date: Thu, 11 Aug 2022 10:58:13 +0800 Subject: arm64: dts: mt8195: Add display node for vdosys0 Add display node for vdosys0 of mt8195. Signed-off-by: Jason-JH.Lin Signed-off-by: Tinghan Shen Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20220811025813.21492-21-tinghan.shen@mediatek.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 93 ++++++++++++++++++++++++++++++++ 1 file changed, 93 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index 5ad7c4200178..a50ebb5d145f 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -1958,6 +1958,7 @@ vdosys0: syscon@1c01a000 { compatible = "mediatek,mt8195-mmsys", "syscon"; reg = <0 0x1c01a000 0 0x1000>; + mboxes = <&gce0 0 CMDQ_THR_PRIO_4>; #clock-cells = <1>; }; @@ -1973,6 +1974,98 @@ power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>; }; + ovl0: ovl@1c000000 { + compatible = "mediatek,mt8195-disp-ovl", "mediatek,mt8183-disp-ovl"; + reg = <0 0x1c000000 0 0x1000>; + interrupts = ; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; + clocks = <&vdosys0 CLK_VDO0_DISP_OVL0>; + iommus = <&iommu_vdo M4U_PORT_L0_DISP_OVL0_RDMA0>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x0000 0x1000>; + }; + + rdma0: rdma@1c002000 { + compatible = "mediatek,mt8195-disp-rdma"; + reg = <0 0x1c002000 0 0x1000>; + interrupts = ; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; + clocks = <&vdosys0 CLK_VDO0_DISP_RDMA0>; + iommus = <&iommu_vdo M4U_PORT_L0_DISP_RDMA0>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x2000 0x1000>; + }; + + color0: color@1c003000 { + compatible = "mediatek,mt8195-disp-color", "mediatek,mt8173-disp-color"; + reg = <0 0x1c003000 0 0x1000>; + interrupts = ; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; + clocks = <&vdosys0 CLK_VDO0_DISP_COLOR0>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x3000 0x1000>; + }; + + ccorr0: ccorr@1c004000 { + compatible = "mediatek,mt8195-disp-ccorr", "mediatek,mt8192-disp-ccorr"; + reg = <0 0x1c004000 0 0x1000>; + interrupts = ; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; + clocks = <&vdosys0 CLK_VDO0_DISP_CCORR0>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x4000 0x1000>; + }; + + aal0: aal@1c005000 { + compatible = "mediatek,mt8195-disp-aal", "mediatek,mt8183-disp-aal"; + reg = <0 0x1c005000 0 0x1000>; + interrupts = ; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; + clocks = <&vdosys0 CLK_VDO0_DISP_AAL0>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x5000 0x1000>; + }; + + gamma0: gamma@1c006000 { + compatible = "mediatek,mt8195-disp-gamma", "mediatek,mt8183-disp-gamma"; + reg = <0 0x1c006000 0 0x1000>; + interrupts = ; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; + clocks = <&vdosys0 CLK_VDO0_DISP_GAMMA0>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x6000 0x1000>; + }; + + dither0: dither@1c007000 { + compatible = "mediatek,mt8195-disp-dither", "mediatek,mt8183-disp-dither"; + reg = <0 0x1c007000 0 0x1000>; + interrupts = ; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; + clocks = <&vdosys0 CLK_VDO0_DISP_DITHER0>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x7000 0x1000>; + }; + + dsc0: dsc@1c009000 { + compatible = "mediatek,mt8195-disp-dsc"; + reg = <0 0x1c009000 0 0x1000>; + interrupts = ; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; + clocks = <&vdosys0 CLK_VDO0_DSC_WRAP0>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x9000 0x1000>; + }; + + merge0: merge@1c014000 { + compatible = "mediatek,mt8195-disp-merge"; + reg = <0 0x1c014000 0 0x1000>; + interrupts = ; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; + clocks = <&vdosys0 CLK_VDO0_VPP_MERGE0>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0x4000 0x1000>; + }; + + mutex: mutex@1c016000 { + compatible = "mediatek,mt8195-disp-mutex"; + reg = <0 0x1c016000 0 0x1000>; + interrupts = ; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; + clocks = <&vdosys0 CLK_VDO0_DISP_MUTEX0>; + mediatek,gce-events = ; + }; + larb0: larb@1c018000 { compatible = "mediatek,mt8195-smi-larb"; reg = <0 0x1c018000 0 0x1000>; -- cgit v1.2.3-59-g8ed1b From 2e78620b13509787a239c847b1ba576265a38bc4 Mon Sep 17 00:00:00 2001 From: Allen-KH Cheng Date: Fri, 26 Aug 2022 01:04:48 +0800 Subject: arm64: dts: Add MediaTek MT8186 dts and evaluation board and Makefile MT8186 is a SoC based on 64bit ARMv8 architecture. It contains 6 CA55 and 2 CA76 cores. MT8186 share many HW IP with MT65xx series. We add basic chip support for MediaTek MT8186 on evaluation board. Signed-off-by: Allen-KH Cheng Link: https://lore.kernel.org/r/20220825170448.17024-1-allen-kh.cheng@mediatek.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/Makefile | 1 + arch/arm64/boot/dts/mediatek/mt8186-evb.dts | 220 ++++++++ arch/arm64/boot/dts/mediatek/mt8186.dtsi | 819 ++++++++++++++++++++++++++++ 3 files changed, 1040 insertions(+) create mode 100644 arch/arm64/boot/dts/mediatek/mt8186-evb.dts create mode 100644 arch/arm64/boot/dts/mediatek/mt8186.dtsi (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile index af362a085a02..0ec90cb3ef28 100644 --- a/arch/arm64/boot/dts/mediatek/Makefile +++ b/arch/arm64/boot/dts/mediatek/Makefile @@ -37,6 +37,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-kodama-sku32.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-krane-sku0.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-krane-sku176.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-pumpkin.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-evb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-asurada-hayato-r1.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-asurada-spherion-r0.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-evb.dtb diff --git a/arch/arm64/boot/dts/mediatek/mt8186-evb.dts b/arch/arm64/boot/dts/mediatek/mt8186-evb.dts new file mode 100644 index 000000000000..ed74a3617c13 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8186-evb.dts @@ -0,0 +1,220 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Copyright (C) 2022 MediaTek Inc. + */ +/dts-v1/; +#include "mt8186.dtsi" + +/ { + model = "MediaTek MT8186 evaluation board"; + compatible = "mediatek,mt8186-evb", "mediatek,mt8186"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:921600n8"; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0 0x40000000 0 0x80000000>; + }; +}; + +&i2c0 { + status = "okay"; + + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; +}; + +&i2c1 { + status = "okay"; + + clock-frequency = <400000>; + i2c-scl-internal-delay-ns = <8000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; +}; + +&i2c2 { + status = "okay"; + + clock-frequency = <400000>; + i2c-scl-internal-delay-ns = <10000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins>; +}; + +&i2c3 { + status = "okay"; + + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_pins>; +}; + +&i2c4 { + status = "okay"; + + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c4_pins>; +}; + +&i2c5 { + status = "okay"; + + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c5_pins>; +}; + +&i2c6 { + status = "okay"; + + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c6_pins>; +}; + +&i2c7 { + status = "okay"; + + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c7_pins>; +}; + +&i2c8 { + status = "okay"; + + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c8_pins>; +}; + +&i2c9 { + status = "okay"; + + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c9_pins>; +}; + +&pio { + i2c0_pins: i2c0-default-pins { + pins-bus { + pinmux = , + ; + bias-disable; + drive-strength-microamp = <1000>; + input-enable; + }; + }; + + i2c1_pins: i2c1-default-pins { + pins-bus { + pinmux = , + ; + bias-disable; + drive-strength-microamp = <1000>; + input-enable; + }; + }; + + i2c2_pins: i2c2-default-pins { + pins-bus { + pinmux = , + ; + bias-disable; + drive-strength-microamp = <1000>; + input-enable; + }; + }; + + i2c3_pins: i2c3-default-pins { + pins-bus { + pinmux = , + ; + bias-disable; + drive-strength-microamp = <1000>; + input-enable; + }; + }; + + i2c4_pins: i2c4-default-pins { + pins-bus { + pinmux = , + ; + bias-disable; + drive-strength-microamp = <1000>; + input-enable; + }; + }; + + i2c5_pins: i2c5-default-pins { + pins-bus { + pinmux = , + ; + bias-disable; + drive-strength-microamp = <1000>; + input-enable; + }; + }; + + i2c6_pins: i2c6-default-pins { + pins-bus { + pinmux = , + ; + bias-pull-up = ; + drive-strength-microamp = <1000>; + input-enable; + }; + }; + + i2c7_pins: i2c7-default-pins { + pins-bus { + pinmux = , + ; + bias-disable; + drive-strength-microamp = <1000>; + input-enable; + }; + }; + + i2c8_pins: i2c8-default-pins { + pins-bus { + pinmux = , + ; + bias-disable; + drive-strength-microamp = <1000>; + input-enable; + }; + }; + + i2c9_pins: i2c9-default-pins { + pins-bus { + pinmux = , + ; + bias-pull-up = ; + drive-strength-microamp = <1000>; + input-enable; + }; + }; +}; + +&u3phy0 { + status = "okay"; +}; + +&u3phy1 { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi new file mode 100644 index 000000000000..64693c17af9e --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi @@ -0,0 +1,819 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Copyright (C) 2022 MediaTek Inc. + * Author: Allen-KH Cheng + */ +/dts-v1/; +#include +#include +#include +#include +#include +#include +#include + +/ { + compatible = "mediatek,mt8186"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + + core1 { + cpu = <&cpu1>; + }; + + core2 { + cpu = <&cpu2>; + }; + + core3 { + cpu = <&cpu3>; + }; + + core4 { + cpu = <&cpu4>; + }; + + core5 { + cpu = <&cpu5>; + }; + }; + + cluster1 { + core0 { + cpu = <&cpu6>; + }; + + core1 { + cpu = <&cpu7>; + }; + }; + }; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x000>; + enable-method = "psci"; + clock-frequency = <2000000000>; + capacity-dmips-mhz = <382>; + cpu-idle-states = <&cpu_off_l &cluster_off_l>; + next-level-cache = <&l2_0>; + #cooling-cells = <2>; + }; + + cpu1: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x100>; + enable-method = "psci"; + clock-frequency = <2000000000>; + capacity-dmips-mhz = <382>; + cpu-idle-states = <&cpu_off_l &cluster_off_l>; + next-level-cache = <&l2_0>; + #cooling-cells = <2>; + }; + + cpu2: cpu@200 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x200>; + enable-method = "psci"; + clock-frequency = <2000000000>; + capacity-dmips-mhz = <382>; + cpu-idle-states = <&cpu_off_l &cluster_off_l>; + next-level-cache = <&l2_0>; + #cooling-cells = <2>; + }; + + cpu3: cpu@300 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x300>; + enable-method = "psci"; + clock-frequency = <2000000000>; + capacity-dmips-mhz = <382>; + cpu-idle-states = <&cpu_off_l &cluster_off_l>; + next-level-cache = <&l2_0>; + #cooling-cells = <2>; + }; + + cpu4: cpu@400 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x400>; + enable-method = "psci"; + clock-frequency = <2000000000>; + capacity-dmips-mhz = <382>; + cpu-idle-states = <&cpu_off_l &cluster_off_l>; + next-level-cache = <&l2_0>; + #cooling-cells = <2>; + }; + + cpu5: cpu@500 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x500>; + enable-method = "psci"; + clock-frequency = <2000000000>; + capacity-dmips-mhz = <382>; + cpu-idle-states = <&cpu_off_l &cluster_off_l>; + next-level-cache = <&l2_0>; + #cooling-cells = <2>; + }; + + cpu6: cpu@600 { + device_type = "cpu"; + compatible = "arm,cortex-a76"; + reg = <0x600>; + enable-method = "psci"; + clock-frequency = <2050000000>; + capacity-dmips-mhz = <1024>; + cpu-idle-states = <&cpu_off_b &cluster_off_b>; + next-level-cache = <&l2_1>; + #cooling-cells = <2>; + }; + + cpu7: cpu@700 { + device_type = "cpu"; + compatible = "arm,cortex-a76"; + reg = <0x700>; + enable-method = "psci"; + clock-frequency = <2050000000>; + capacity-dmips-mhz = <1024>; + cpu-idle-states = <&cpu_off_b &cluster_off_b>; + next-level-cache = <&l2_1>; + #cooling-cells = <2>; + }; + + idle-states { + entry-method = "psci"; + + cpu_off_l: cpu-off-l { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x00010001>; + local-timer-stop; + entry-latency-us = <50>; + exit-latency-us = <100>; + min-residency-us = <1600>; + }; + + cpu_off_b: cpu-off-b { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x00010001>; + local-timer-stop; + entry-latency-us = <50>; + exit-latency-us = <100>; + min-residency-us = <1400>; + }; + + cluster_off_l: cluster-off-l { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x01010001>; + local-timer-stop; + entry-latency-us = <100>; + exit-latency-us = <250>; + min-residency-us = <2100>; + }; + + cluster_off_b: cluster-off-b { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x01010001>; + local-timer-stop; + entry-latency-us = <100>; + exit-latency-us = <250>; + min-residency-us = <1900>; + }; + }; + + l2_0: l2-cache0 { + compatible = "cache"; + next-level-cache = <&l3_0>; + }; + + l2_1: l2-cache1 { + compatible = "cache"; + next-level-cache = <&l3_0>; + }; + + l3_0: l3-cache { + compatible = "cache"; + }; + }; + + clk13m: oscillator-13m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <13000000>; + clock-output-names = "clk13m"; + }; + + clk26m: oscillator-26m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + clock-output-names = "clk26m"; + }; + + clk32k: oscillator-32k { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "clk32k"; + }; + + pmu-a55 { + compatible = "arm,cortex-a55-pmu"; + interrupt-parent = <&gic>; + interrupts = ; + }; + + pmu-a76 { + compatible = "arm,cortex-a76-pmu"; + interrupt-parent = <&gic>; + interrupts = ; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&gic>; + interrupts = , + , + , + ; + }; + + soc { + #address-cells = <2>; + #size-cells = <2>; + compatible = "simple-bus"; + ranges; + + gic: interrupt-controller@c000000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <4>; + #redistributor-regions = <1>; + interrupt-parent = <&gic>; + interrupt-controller; + reg = <0 0x0c000000 0 0x40000>, + <0 0x0c040000 0 0x200000>; + interrupts = ; + + ppi-partitions { + ppi_cluster0: interrupt-partition-0 { + affinity = <&cpu0 &cpu1 &cpu2 &cpu3 &cpu4 &cpu5>; + }; + + ppi_cluster1: interrupt-partition-1 { + affinity = <&cpu6 &cpu7>; + }; + }; + }; + + mcusys: syscon@c53a000 { + compatible = "mediatek,mt8186-mcusys", "syscon"; + reg = <0 0xc53a000 0 0x1000>; + #clock-cells = <1>; + }; + + topckgen: syscon@10000000 { + compatible = "mediatek,mt8186-topckgen", "syscon"; + reg = <0 0x10000000 0 0x1000>; + #clock-cells = <1>; + }; + + infracfg_ao: syscon@10001000 { + compatible = "mediatek,mt8186-infracfg_ao", "syscon"; + reg = <0 0x10001000 0 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + pericfg: syscon@10003000 { + compatible = "mediatek,mt8186-pericfg", "syscon"; + reg = <0 0x10003000 0 0x1000>; + }; + + pio: pinctrl@10005000 { + compatible = "mediatek,mt8186-pinctrl"; + reg = <0 0x10005000 0 0x1000>, + <0 0x10002000 0 0x0200>, + <0 0x10002200 0 0x0200>, + <0 0x10002400 0 0x0200>, + <0 0x10002600 0 0x0200>, + <0 0x10002a00 0 0x0200>, + <0 0x10002c00 0 0x0200>, + <0 0x1000b000 0 0x1000>; + reg-names = "iocfg0", "iocfg_lt", "iocfg_lm", "iocfg_lb", + "iocfg_bl", "iocfg_rb", "iocfg_rt", "eint"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pio 0 0 185>; + interrupt-controller; + interrupts = ; + #interrupt-cells = <2>; + }; + + watchdog: watchdog@10007000 { + compatible = "mediatek,mt8186-wdt", + "mediatek,mt6589-wdt"; + mediatek,disable-extrst; + reg = <0 0x10007000 0 0x1000>; + #reset-cells = <1>; + }; + + apmixedsys: syscon@1000c000 { + compatible = "mediatek,mt8186-apmixedsys", "syscon"; + reg = <0 0x1000c000 0 0x1000>; + #clock-cells = <1>; + }; + + pwrap: pwrap@1000d000 { + compatible = "mediatek,mt8186-pwrap", "syscon"; + reg = <0 0x1000d000 0 0x1000>; + reg-names = "pwrap"; + interrupts = ; + clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>, + <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>; + clock-names = "spi", "wrap"; + }; + + systimer: timer@10017000 { + compatible = "mediatek,mt8186-timer", + "mediatek,mt6765-timer"; + reg = <0 0x10017000 0 0x1000>; + interrupts = ; + clocks = <&clk13m>; + }; + + scp: scp@10500000 { + compatible = "mediatek,mt8186-scp"; + reg = <0 0x10500000 0 0x40000>, + <0 0x105c0000 0 0x19080>; + reg-names = "sram", "cfg"; + interrupts = ; + }; + + nor_flash: spi@11000000 { + compatible = "mediatek,mt8186-nor"; + reg = <0 0x11000000 0 0x1000>; + clocks = <&topckgen CLK_TOP_SPINOR>, + <&infracfg_ao CLK_INFRA_AO_SPINOR>, + <&infracfg_ao CLK_INFRA_AO_FLASHIF_133M>, + <&infracfg_ao CLK_INFRA_AO_FLASHIF_66M>; + clock-names = "spi", "sf", "axi", "axi_s"; + assigned-clocks = <&topckgen CLK_TOP_SPINOR>; + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D3_D8>; + interrupts = ; + status = "disabled"; + }; + + auxadc: adc@11001000 { + compatible = "mediatek,mt8186-auxadc", "mediatek,mt8173-auxadc"; + reg = <0 0x11001000 0 0x1000>; + #io-channel-cells = <1>; + clocks = <&infracfg_ao CLK_INFRA_AO_AUXADC>; + clock-names = "main"; + }; + + uart0: serial@11002000 { + compatible = "mediatek,mt8186-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11002000 0 0x1000>; + interrupts = ; + clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART0>; + clock-names = "baud", "bus"; + status = "disabled"; + }; + + uart1: serial@11003000 { + compatible = "mediatek,mt8186-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11003000 0 0x1000>; + interrupts = ; + clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART1>; + clock-names = "baud", "bus"; + status = "disabled"; + }; + + i2c0: i2c@11007000 { + compatible = "mediatek,mt8186-i2c"; + reg = <0 0x11007000 0 0x1000>, + <0 0x10200100 0 0x100>; + interrupts = ; + clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C0>, + <&infracfg_ao CLK_INFRA_AO_AP_DMA>; + clock-names = "main", "dma"; + clock-div = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@11008000 { + compatible = "mediatek,mt8186-i2c"; + reg = <0 0x11008000 0 0x1000>, + <0 0x10200200 0 0x100>; + interrupts = ; + clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C1>, + <&infracfg_ao CLK_INFRA_AO_AP_DMA>; + clock-names = "main", "dma"; + clock-div = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@11009000 { + compatible = "mediatek,mt8186-i2c"; + reg = <0 0x11009000 0 0x1000>, + <0 0x10200300 0 0x180>; + interrupts = ; + clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C2>, + <&infracfg_ao CLK_INFRA_AO_AP_DMA>; + clock-names = "main", "dma"; + clock-div = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c3: i2c@1100f000 { + compatible = "mediatek,mt8186-i2c"; + reg = <0 0x1100f000 0 0x1000>, + <0 0x10200480 0 0x100>; + interrupts = ; + clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C3>, + <&infracfg_ao CLK_INFRA_AO_AP_DMA>; + clock-names = "main", "dma"; + clock-div = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c4: i2c@11011000 { + compatible = "mediatek,mt8186-i2c"; + reg = <0 0x11011000 0 0x1000>, + <0 0x10200580 0 0x180>; + interrupts = ; + clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C4>, + <&infracfg_ao CLK_INFRA_AO_AP_DMA>; + clock-names = "main", "dma"; + clock-div = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c5: i2c@11016000 { + compatible = "mediatek,mt8186-i2c"; + reg = <0 0x11016000 0 0x1000>, + <0 0x10200700 0 0x100>; + interrupts = ; + clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C5>, + <&infracfg_ao CLK_INFRA_AO_AP_DMA>; + clock-names = "main", "dma"; + clock-div = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c6: i2c@1100d000 { + compatible = "mediatek,mt8186-i2c"; + reg = <0 0x1100d000 0 0x1000>, + <0 0x10200800 0 0x100>; + interrupts = ; + clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C6>, + <&infracfg_ao CLK_INFRA_AO_AP_DMA>; + clock-names = "main", "dma"; + clock-div = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c7: i2c@11004000 { + compatible = "mediatek,mt8186-i2c"; + reg = <0 0x11004000 0 0x1000>, + <0 0x10200900 0 0x180>; + interrupts = ; + clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C7>, + <&infracfg_ao CLK_INFRA_AO_AP_DMA>; + clock-names = "main", "dma"; + clock-div = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c8: i2c@11005000 { + compatible = "mediatek,mt8186-i2c"; + reg = <0 0x11005000 0 0x1000>, + <0 0x10200A80 0 0x180>; + interrupts = ; + clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C8>, + <&infracfg_ao CLK_INFRA_AO_AP_DMA>; + clock-names = "main", "dma"; + clock-div = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi0: spi@1100a000 { + compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x1100a000 0 0x1000>; + interrupts = ; + clocks = <&topckgen CLK_TOP_MAINPLL_D5>, + <&topckgen CLK_TOP_SPI>, + <&infracfg_ao CLK_INFRA_AO_SPI0>; + clock-names = "parent-clk", "sel-clk", "spi-clk"; + status = "disabled"; + }; + + pwm0: pwm@1100e000 { + compatible = "mediatek,mt8186-disp-pwm", "mediatek,mt8183-disp-pwm"; + reg = <0 0x1100e000 0 0x1000>; + interrupts = ; + #pwm-cells = <2>; + clocks = <&topckgen CLK_TOP_DISP_PWM>, + <&infracfg_ao CLK_INFRA_AO_DISP_PWM>; + clock-names = "main", "mm"; + status = "disabled"; + }; + + spi1: spi@11010000 { + compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x11010000 0 0x1000>; + interrupts = ; + clocks = <&topckgen CLK_TOP_MAINPLL_D5>, + <&topckgen CLK_TOP_SPI>, + <&infracfg_ao CLK_INFRA_AO_SPI1>; + clock-names = "parent-clk", "sel-clk", "spi-clk"; + status = "disabled"; + }; + + spi2: spi@11012000 { + compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x11012000 0 0x1000>; + interrupts = ; + clocks = <&topckgen CLK_TOP_MAINPLL_D5>, + <&topckgen CLK_TOP_SPI>, + <&infracfg_ao CLK_INFRA_AO_SPI2>; + clock-names = "parent-clk", "sel-clk", "spi-clk"; + status = "disabled"; + }; + + spi3: spi@11013000 { + compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x11013000 0 0x1000>; + interrupts = ; + clocks = <&topckgen CLK_TOP_MAINPLL_D5>, + <&topckgen CLK_TOP_SPI>, + <&infracfg_ao CLK_INFRA_AO_SPI3>; + clock-names = "parent-clk", "sel-clk", "spi-clk"; + status = "disabled"; + }; + + spi4: spi@11014000 { + compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x11014000 0 0x1000>; + interrupts = ; + clocks = <&topckgen CLK_TOP_MAINPLL_D5>, + <&topckgen CLK_TOP_SPI>, + <&infracfg_ao CLK_INFRA_AO_SPI4>; + clock-names = "parent-clk", "sel-clk", "spi-clk"; + status = "disabled"; + }; + + spi5: spi@11015000 { + compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x11015000 0 0x1000>; + interrupts = ; + clocks = <&topckgen CLK_TOP_MAINPLL_D5>, + <&topckgen CLK_TOP_SPI>, + <&infracfg_ao CLK_INFRA_AO_SPI5>; + clock-names = "parent-clk", "sel-clk", "spi-clk"; + status = "disabled"; + }; + + imp_iic_wrap: clock-controller@11017000 { + compatible = "mediatek,mt8186-imp_iic_wrap"; + reg = <0 0x11017000 0 0x1000>; + #clock-cells = <1>; + }; + + uart2: serial@11018000 { + compatible = "mediatek,mt8186-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11018000 0 0x1000>; + interrupts = ; + clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART2>; + clock-names = "baud", "bus"; + status = "disabled"; + }; + + i2c9: i2c@11019000 { + compatible = "mediatek,mt8186-i2c"; + reg = <0 0x11019000 0 0x1000>, + <0 0x10200c00 0 0x180>; + interrupts = ; + clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C9>, + <&infracfg_ao CLK_INFRA_AO_AP_DMA>; + clock-names = "main", "dma"; + clock-div = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + mmc0: mmc@11230000 { + compatible = "mediatek,mt8186-mmc", + "mediatek,mt8183-mmc"; + reg = <0 0x11230000 0 0x1000>, + <0 0x11cd0000 0 0x1000>; + clocks = <&topckgen CLK_TOP_MSDC50_0>, + <&infracfg_ao CLK_INFRA_AO_MSDC0>, + <&infracfg_ao CLK_INFRA_AO_MSDC0_SRC>; + clock-names = "source", "hclk", "source_cg"; + interrupts = ; + assigned-clocks = <&topckgen CLK_TOP_MSDC50_0>; + assigned-clock-parents = <&apmixedsys CLK_APMIXED_MSDCPLL>; + status = "disabled"; + }; + + mmc1: mmc@11240000 { + compatible = "mediatek,mt8186-mmc", + "mediatek,mt8183-mmc"; + reg = <0 0x11240000 0 0x1000>, + <0 0x11c90000 0 0x1000>; + clocks = <&topckgen CLK_TOP_MSDC30_1>, + <&infracfg_ao CLK_INFRA_AO_MSDC1>, + <&infracfg_ao CLK_INFRA_AO_MSDC1_SRC>; + clock-names = "source", "hclk", "source_cg"; + interrupts = ; + assigned-clocks = <&topckgen CLK_TOP_MSDC30_1>; + assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>; + status = "disabled"; + }; + + u3phy0: t-phy@11c80000 { + compatible = "mediatek,mt8186-tphy", + "mediatek,generic-tphy-v2"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x11c80000 0x1000>; + status = "disabled"; + + u2port1: usb-phy@0 { + reg = <0x0 0x700>; + clocks = <&clk26m>; + clock-names = "ref"; + #phy-cells = <1>; + }; + + u3port1: usb-phy@700 { + reg = <0x700 0x900>; + clocks = <&clk26m>; + clock-names = "ref"; + #phy-cells = <1>; + }; + }; + + u3phy1: t-phy@11ca0000 { + compatible = "mediatek,mt8186-tphy", + "mediatek,generic-tphy-v2"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x11ca0000 0x1000>; + status = "disabled"; + + u2port0: usb-phy@0 { + reg = <0x0 0x700>; + clocks = <&clk26m>; + clock-names = "ref"; + #phy-cells = <1>; + mediatek,discth = <0x8>; + }; + }; + + efuse: efuse@11cb0000 { + compatible = "mediatek,mt8186-efuse", "mediatek,efuse"; + reg = <0 0x11cb0000 0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + }; + + mipi_tx0: dsi-phy@11cc0000 { + compatible = "mediatek,mt8183-mipi-tx"; + reg = <0 0x11cc0000 0 0x1000>; + clocks = <&clk26m>; + #clock-cells = <0>; + #phy-cells = <0>; + clock-output-names = "mipi_tx0_pll"; + status = "disabled"; + }; + + mfgsys: clock-controller@13000000 { + compatible = "mediatek,mt8186-mfgsys"; + reg = <0 0x13000000 0 0x1000>; + #clock-cells = <1>; + }; + + mmsys: syscon@14000000 { + compatible = "mediatek,mt8186-mmsys", "syscon"; + reg = <0 0x14000000 0 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + wpesys: clock-controller@14020000 { + compatible = "mediatek,mt8186-wpesys"; + reg = <0 0x14020000 0 0x1000>; + #clock-cells = <1>; + }; + + imgsys1: clock-controller@15020000 { + compatible = "mediatek,mt8186-imgsys1"; + reg = <0 0x15020000 0 0x1000>; + #clock-cells = <1>; + }; + + imgsys2: clock-controller@15820000 { + compatible = "mediatek,mt8186-imgsys2"; + reg = <0 0x15820000 0 0x1000>; + #clock-cells = <1>; + }; + + vdecsys: clock-controller@1602f000 { + compatible = "mediatek,mt8186-vdecsys"; + reg = <0 0x1602f000 0 0x1000>; + #clock-cells = <1>; + }; + + vencsys: clock-controller@17000000 { + compatible = "mediatek,mt8186-vencsys"; + reg = <0 0x17000000 0 0x1000>; + #clock-cells = <1>; + }; + + camsys: clock-controller@1a000000 { + compatible = "mediatek,mt8186-camsys"; + reg = <0 0x1a000000 0 0x1000>; + #clock-cells = <1>; + }; + + camsys_rawa: clock-controller@1a04f000 { + compatible = "mediatek,mt8186-camsys_rawa"; + reg = <0 0x1a04f000 0 0x1000>; + #clock-cells = <1>; + }; + + camsys_rawb: clock-controller@1a06f000 { + compatible = "mediatek,mt8186-camsys_rawb"; + reg = <0 0x1a06f000 0 0x1000>; + #clock-cells = <1>; + }; + + mdpsys: clock-controller@1b000000 { + compatible = "mediatek,mt8186-mdpsys"; + reg = <0 0x1b000000 0 0x1000>; + #clock-cells = <1>; + }; + + ipesys: clock-controller@1c000000 { + compatible = "mediatek,mt8186-ipesys"; + reg = <0 0x1c000000 0 0x1000>; + #clock-cells = <1>; + }; + }; +}; -- cgit v1.2.3-59-g8ed1b From 18222e059850f64637221de7f82fae38740b16aa Mon Sep 17 00:00:00 2001 From: Allen-KH Cheng Date: Tue, 12 Jul 2022 19:40:42 +0800 Subject: arm64: dts: mt8192: Add pwm node MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add pwm node for mt8192 SoC. Signed-off-by: Allen-KH Cheng Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Nícolas F. R. A. Prado Tested-by: Nícolas F. R. A. Prado Tested-by: Chen-Yu Tsai Link: https://lore.kernel.org/r/20220712114046.15574-2-allen-kh.cheng@mediatek.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index 8cd5906fe3a8..b29486057580 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -598,6 +598,17 @@ status = "disabled"; }; + pwm0: pwm@1100e000 { + compatible = "mediatek,mt8183-disp-pwm"; + reg = <0 0x1100e000 0 0x1000>; + interrupts = ; + #pwm-cells = <2>; + clocks = <&topckgen CLK_TOP_DISP_PWM_SEL>, + <&infracfg CLK_INFRA_DISP_PWM>; + clock-names = "main", "mm"; + status = "disabled"; + }; + spi1: spi@11010000 { compatible = "mediatek,mt8192-spi", "mediatek,mt6765-spi"; -- cgit v1.2.3-59-g8ed1b From 85c4ec6f7cf5d1ad1939617efad9f805a326f884 Mon Sep 17 00:00:00 2001 From: Allen-KH Cheng Date: Tue, 12 Jul 2022 19:40:43 +0800 Subject: arm64: dts: mt8192: Add mipi_tx node MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add mipi_tx node for mt8192 SoC. Signed-off-by: Allen-KH Cheng Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Nícolas F. R. A. Prado Tested-by: Nícolas F. R. A. Prado Tested-by: Chen-Yu Tsai Link: https://lore.kernel.org/r/20220712114046.15574-3-allen-kh.cheng@mediatek.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index b29486057580..8dce6609c726 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -1094,6 +1094,16 @@ }; }; + mipi_tx0: dsi-phy@11e50000 { + compatible = "mediatek,mt8183-mipi-tx"; + reg = <0 0x11e50000 0 0x1000>; + clocks = <&apmixedsys CLK_APMIXED_MIPID26M>; + #clock-cells = <0>; + #phy-cells = <0>; + clock-output-names = "mipi_tx0_pll"; + status = "disabled"; + }; + i2c0: i2c@11f00000 { compatible = "mediatek,mt8192-i2c"; reg = <0 0x11f00000 0 0x1000>, -- cgit v1.2.3-59-g8ed1b From 7d3553788dd9cd51643e8071d28885e1ca13d669 Mon Sep 17 00:00:00 2001 From: Allen-KH Cheng Date: Tue, 12 Jul 2022 19:40:44 +0800 Subject: arm64: dts: mediatek: Add mmsys #reset-cells property for mt8192 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit To support reset of mmsys, we include mt8192-resets.h and add property of #reset-cells in mmsys. Signed-off-by: Allen-KH Cheng Reviewed-by: Nícolas F. R. A. Prado Reviewed-by: AngeloGioacchino Del Regno Tested-by: Nícolas F. R. A. Prado Tested-by: Chen-Yu Tsai Link: https://lore.kernel.org/r/20220712114046.15574-4-allen-kh.cheng@mediatek.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index 8dce6609c726..89d16de09132 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -12,6 +12,7 @@ #include #include #include +#include / { compatible = "mediatek,mt8192"; @@ -1186,6 +1187,7 @@ compatible = "mediatek,mt8192-mmsys", "syscon"; reg = <0 0x14000000 0 0x1000>; #clock-cells = <1>; + #reset-cells = <1>; }; smi_common: smi@14002000 { -- cgit v1.2.3-59-g8ed1b From b4b75bac952bd5393cae4b58ad1986b569fd7231 Mon Sep 17 00:00:00 2001 From: Allen-KH Cheng Date: Tue, 12 Jul 2022 19:40:45 +0800 Subject: arm64: dts: mt8192: Add display nodes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add display nodes and gce info for mt8192 SoC. GCE (Global Command Engine) properties to the display nodes in order to enable the usage of the CMDQ (Command Queue), which is required for operating the display. Signed-off-by: Allen-KH Cheng Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Nícolas F. R. A. Prado Tested-by: Nícolas F. R. A. Prado Tested-by: Chen-Yu Tsai Link: https://lore.kernel.org/r/20220712114046.15574-5-allen-kh.cheng@mediatek.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 146 +++++++++++++++++++++++++++++++ 1 file changed, 146 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index 89d16de09132..c8ae0285bb53 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -6,6 +6,7 @@ /dts-v1/; #include +#include #include #include #include @@ -20,6 +21,14 @@ #address-cells = <2>; #size-cells = <2>; + aliases { + ovl0 = &ovl0; + ovl-2l0 = &ovl_2l0; + ovl-2l2 = &ovl_2l2; + rdma0 = &rdma0; + rdma4 = &rdma4; + }; + clk26m: oscillator0 { compatible = "fixed-clock"; #clock-cells = <0>; @@ -553,6 +562,15 @@ assigned-clock-parents = <&topckgen CLK_TOP_OSC_D10>; }; + gce: mailbox@10228000 { + compatible = "mediatek,mt8192-gce"; + reg = <0 0x10228000 0 0x4000>; + interrupts = ; + #mbox-cells = <2>; + clocks = <&infracfg CLK_INFRA_GCE>; + clock-names = "gce"; + }; + scp_adsp: clock-controller@10720000 { compatible = "mediatek,mt8192-scp_adsp"; reg = <0 0x10720000 0 0x1000>; @@ -1188,6 +1206,19 @@ reg = <0 0x14000000 0 0x1000>; #clock-cells = <1>; #reset-cells = <1>; + mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>, + <&gce 1 CMDQ_THR_PRIO_HIGHEST>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>; + }; + + mutex: mutex@14001000 { + compatible = "mediatek,mt8192-disp-mutex"; + reg = <0 0x14001000 0 0x1000>; + interrupts = ; + clocks = <&mmsys CLK_MM_DISP_MUTEX0>; + mediatek,gce-events = , + ; + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; }; smi_common: smi@14002000 { @@ -1221,6 +1252,121 @@ power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; }; + ovl0: ovl@14005000 { + compatible = "mediatek,mt8192-disp-ovl"; + reg = <0 0x14005000 0 0x1000>; + interrupts = ; + clocks = <&mmsys CLK_MM_DISP_OVL0>; + iommus = <&iommu0 M4U_PORT_L0_OVL_RDMA0>, + <&iommu0 M4U_PORT_L0_OVL_RDMA0_HDR>; + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>; + }; + + ovl_2l0: ovl@14006000 { + compatible = "mediatek,mt8192-disp-ovl-2l"; + reg = <0 0x14006000 0 0x1000>; + interrupts = ; + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_DISP_OVL0_2L>; + iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0>, + <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0_HDR>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 0x1000>; + }; + + rdma0: rdma@14007000 { + compatible = "mediatek,mt8192-disp-rdma", + "mediatek,mt8183-disp-rdma"; + reg = <0 0x14007000 0 0x1000>; + interrupts = ; + clocks = <&mmsys CLK_MM_DISP_RDMA0>; + iommus = <&iommu0 M4U_PORT_L0_DISP_RDMA0>; + mediatek,rdma-fifo-size = <5120>; + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x7000 0x1000>; + }; + + color0: color@14009000 { + compatible = "mediatek,mt8192-disp-color", + "mediatek,mt8173-disp-color"; + reg = <0 0x14009000 0 0x1000>; + interrupts = ; + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_DISP_COLOR0>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>; + }; + + ccorr0: ccorr@1400a000 { + compatible = "mediatek,mt8192-disp-ccorr"; + reg = <0 0x1400a000 0 0x1000>; + interrupts = ; + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_DISP_CCORR0>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xa000 0x1000>; + }; + + aal0: aal@1400b000 { + compatible = "mediatek,mt8192-disp-aal", + "mediatek,mt8183-disp-aal"; + reg = <0 0x1400b000 0 0x1000>; + interrupts = ; + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_DISP_AAL0>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>; + }; + + gamma0: gamma@1400c000 { + compatible = "mediatek,mt8192-disp-gamma", + "mediatek,mt8183-disp-gamma"; + reg = <0 0x1400c000 0 0x1000>; + interrupts = ; + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_DISP_GAMMA0>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>; + }; + + postmask0: postmask@1400d000 { + compatible = "mediatek,mt8192-disp-postmask"; + reg = <0 0x1400d000 0 0x1000>; + interrupts = ; + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_DISP_POSTMASK0>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>; + }; + + dither0: dither@1400e000 { + compatible = "mediatek,mt8192-disp-dither", + "mediatek,mt8183-disp-dither"; + reg = <0 0x1400e000 0 0x1000>; + interrupts = ; + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_DISP_DITHER0>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>; + }; + + ovl_2l2: ovl@14014000 { + compatible = "mediatek,mt8192-disp-ovl-2l"; + reg = <0 0x14014000 0 0x1000>; + interrupts = ; + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_DISP_OVL2_2L>; + iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2>, + <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2_HDR>; + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x4000 0x1000>; + }; + + rdma4: rdma@14015000 { + compatible = "mediatek,mt8192-disp-rdma", + "mediatek,mt8183-disp-rdma"; + reg = <0 0x14015000 0 0x1000>; + interrupts = ; + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_DISP_RDMA4>; + iommus = <&iommu0 M4U_PORT_L1_DISP_RDMA4>; + mediatek,rdma-fifo-size = <2048>; + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>; + }; + dpi0: dpi@14016000 { compatible = "mediatek,mt8192-dpi"; reg = <0 0x14016000 0 0x1000>; -- cgit v1.2.3-59-g8ed1b From 0708ed7c2c63a60ee59dd50cdb50689571a234b3 Mon Sep 17 00:00:00 2001 From: Allen-KH Cheng Date: Tue, 12 Jul 2022 19:40:46 +0800 Subject: arm64: dts: mt8192: Add dsi node MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add dsi node for mt8192 SoC. Signed-off-by: Allen-KH Cheng Reviewed-by: Nícolas F. R. A. Prado Reviewed-by: AngeloGioacchino Del Regno Tested-by: Nícolas F. R. A. Prado Tested-by: Chen-Yu Tsai Link: https://lore.kernel.org/r/20220712114046.15574-6-allen-kh.cheng@mediatek.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index c8ae0285bb53..64bf65b1b184 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -1344,6 +1344,25 @@ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>; }; + dsi0: dsi@14010000 { + compatible = "mediatek,mt8183-dsi"; + reg = <0 0x14010000 0 0x1000>; + interrupts = ; + clocks = <&mmsys CLK_MM_DSI0>, + <&mmsys CLK_MM_DSI_DSI0>, + <&mipi_tx0>; + clock-names = "engine", "digital", "hs"; + phys = <&mipi_tx0>; + phy-names = "dphy"; + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; + resets = <&mmsys MT8192_MMSYS_SW0_RST_B_DISP_DSI0>; + status = "disabled"; + + port { + dsi_out: endpoint { }; + }; + }; + ovl_2l2: ovl@14014000 { compatible = "mediatek,mt8192-disp-ovl-2l"; reg = <0 0x14014000 0 0x1000>; -- cgit v1.2.3-59-g8ed1b From 6210fc2e4ca2551cb09fd122ee49ebcf64487f3e Mon Sep 17 00:00:00 2001 From: "Nícolas F. R. A. Prado" Date: Fri, 8 Jul 2022 15:43:14 -0400 Subject: arm64: dts: mediatek: Add missing xHCI clocks for mt8192 and mt8195 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The MediaTek xHCI dt-binding expects a specific order for the clocks, but the mt8192 and mt8195 devicetrees were skipping some of the middle clocks. These clocks are wired to the controller hardware but aren't controllable. Add the missing clocks as handles to fixed clocks, so that the clock order is respected and the dtbs_check warnings are gone. Signed-off-by: Nícolas F. R. A. Prado Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20220708194314.56922-1-nfraprado@collabora.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 9 ++++++--- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 18 ++++++++++++++---- 2 files changed, 20 insertions(+), 7 deletions(-) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index 64bf65b1b184..6b20376191a7 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -753,9 +753,12 @@ assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, <&topckgen CLK_TOP_UNIVPLL_D5_D4>; clocks = <&infracfg CLK_INFRA_SSUSB>, - <&infracfg CLK_INFRA_SSUSB_XHCI>, - <&apmixedsys CLK_APMIXED_USBPLL>; - clock-names = "sys_ck", "xhci_ck", "ref_ck"; + <&apmixedsys CLK_APMIXED_USBPLL>, + <&clk26m>, + <&clk26m>, + <&infracfg CLK_INFRA_SSUSB_XHCI>; + clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", + "xhci_ck"; wakeup-source; mediatek,syscon-wakeup = <&pericfg 0x420 102>; status = "disabled"; diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index a50ebb5d145f..905d1a90b406 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -1058,8 +1058,10 @@ clocks = <&infracfg_ao CLK_INFRA_AO_SSUSB>, <&topckgen CLK_TOP_SSUSB_REF>, <&apmixedsys CLK_APMIXED_USB1PLL>, + <&clk26m>, <&infracfg_ao CLK_INFRA_AO_SSUSB_XHCI>; - clock-names = "sys_ck", "ref_ck", "mcu_ck", "xhci_ck"; + clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", + "xhci_ck"; mediatek,syscon-wakeup = <&pericfg 0x400 103>; wakeup-source; status = "disabled"; @@ -1123,8 +1125,10 @@ clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_1P_BUS>, <&topckgen CLK_TOP_SSUSB_P1_REF>, <&apmixedsys CLK_APMIXED_USB1PLL>, + <&clk26m>, <&pericfg_ao CLK_PERI_AO_SSUSB_1P_XHCI>; - clock-names = "sys_ck", "ref_ck", "mcu_ck","xhci_ck"; + clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", + "xhci_ck"; mediatek,syscon-wakeup = <&pericfg 0x400 104>; wakeup-source; status = "disabled"; @@ -1144,8 +1148,11 @@ <&topckgen CLK_TOP_UNIVPLL_D5_D4>; clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_2P_BUS>, <&topckgen CLK_TOP_SSUSB_P2_REF>, + <&clk26m>, + <&clk26m>, <&pericfg_ao CLK_PERI_AO_SSUSB_2P_XHCI>; - clock-names = "sys_ck", "ref_ck", "xhci_ck"; + clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", + "xhci_ck"; mediatek,syscon-wakeup = <&pericfg 0x400 105>; wakeup-source; status = "disabled"; @@ -1165,8 +1172,11 @@ <&topckgen CLK_TOP_UNIVPLL_D5_D4>; clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_3P_BUS>, <&topckgen CLK_TOP_SSUSB_P3_REF>, + <&clk26m>, + <&clk26m>, <&pericfg_ao CLK_PERI_AO_SSUSB_3P_XHCI>; - clock-names = "sys_ck", "ref_ck", "xhci_ck"; + clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", + "xhci_ck"; mediatek,syscon-wakeup = <&pericfg 0x400 106>; wakeup-source; status = "disabled"; -- cgit v1.2.3-59-g8ed1b From 5334bed7b2344115928cca4c1a63b32ccde1814d Mon Sep 17 00:00:00 2001 From: Tinghan Shen Date: Wed, 31 Aug 2022 14:51:00 +0800 Subject: arm64: dts: mediatek: Fix build warnings of mt8173 vcodec nodes Correct the phandle of power domain node referenced by vcodec nodes. arch/arm64/boot/dts/mediatek/mt8173.dtsi:1450.35-1471.5: Warning (power_domains_property): /soc/vcodec@18002000: Missing property '#power-domain-cells' in node /soc/syscon@10006000 or bad phandle (referred from power-domains[0]) arch/arm64/boot/dts/mediatek/mt8173.dtsi:1502.35-1522.5: Warning (power_domains_property): /soc/vcodec@19002000: Missing property '#power-domain-cells' in node /soc/syscon@10006000 or bad phandle (referred from power-domains[0]) Fixes: d3dfd4688574 ("arm64: dts: mediatek: Update mt81xx scpsys node to align with dt-bindings") Signed-off-by: Tinghan Shen Link: https://lore.kernel.org/r/20220831065100.27722-1-tinghan.shen@mediatek.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8173.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi index b4d48f8b7eeb..7640b5158ff9 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi @@ -1467,7 +1467,7 @@ clock-names = "venc_sel"; assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>; assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL>; - power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC>; + power-domains = <&spm MT8173_POWER_DOMAIN_VENC>; }; jpegdec: jpegdec@18004000 { @@ -1518,7 +1518,7 @@ assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>; assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL_370P5>; - power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC_LT>; + power-domains = <&spm MT8173_POWER_DOMAIN_VENC_LT>; }; }; }; -- cgit v1.2.3-59-g8ed1b From d86a1c69bd9a4d6859293cd0ecebfa692f6a3150 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Fri, 2 Sep 2022 10:11:50 +0200 Subject: arm64: dts: mediatek: cherry: Enable the System Companion Processor MT8195 features a SCP like some other older SoCs, and Cherry uses it for various tasks. Add the required pin configuration and DMA pool and enable the node. Signed-off-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20220902081156.38526-2-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi | 29 +++++++++++++++++++++++++ 1 file changed, 29 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi index fcc600674339..e83d58d99757 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi @@ -104,6 +104,18 @@ enable-active-high; regulator-always-on; }; + + reserved_memory: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + scp_mem: memory@50000000 { + compatible = "shared-dma-pool"; + reg = <0 0x50000000 0 0x2900000>; + no-map; + }; + }; }; &i2c0 { @@ -600,6 +612,14 @@ }; }; + scp_pins: scp-default-pins { + pins-vreq { + pinmux = ; + bias-disable; + input-enable; + }; + }; + spi0_pins: spi0-default-pins { pins-cs-mosi-clk { pinmux = , @@ -643,6 +663,15 @@ interrupts-extended = <&pio 222 IRQ_TYPE_LEVEL_HIGH>; }; +&scp { + status = "okay"; + + firmware-name = "mediatek/mt8195/scp.img"; + memory-region = <&scp_mem>; + pinctrl-names = "default"; + pinctrl-0 = <&scp_pins>; +}; + &spi0 { status = "okay"; -- cgit v1.2.3-59-g8ed1b From e775cc1a9b4fb9b7b62edc480642ebd21e3b81e1 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Fri, 2 Sep 2022 10:11:51 +0200 Subject: arm64: dts: mediatek: cherry: Wire up the ChromeOS Embedded Controller Wire up the ChromeOS Embedded Controller on SPI0 and its communication channel via SCP RPMSG along with all of the offered functionality, including Keyboard, Smart Battery Metrics (SBS), keyboard backlight, I2C tunnel, regulators and Type-C connector management. Signed-off-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20220902081156.38526-3-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi | 77 +++++++++++++++++++++++++ 1 file changed, 77 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi index e83d58d99757..73f531f84fa2 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi @@ -426,6 +426,14 @@ "AP_SPI_FLASH_MOSI", "AP_SPI_FLASH_MISO"; + cros_ec_int: cros-ec-irq-default-pins { + pins-ec-ap-int-odl { + pinmux = ; + bias-pull-up = ; + input-enable; + }; + }; + i2c0_pins: i2c0-default-pins { pins-bus { pinmux = , @@ -670,6 +678,11 @@ memory-region = <&scp_mem>; pinctrl-names = "default"; pinctrl-0 = <&scp_pins>; + + cros-ec-rpmsg { + compatible = "google,cros-ec-rpmsg"; + mediatek,rpmsg-name = "cros-ec-rpmsg"; + }; }; &spi0 { @@ -678,6 +691,67 @@ pinctrl-names = "default"; pinctrl-0 = <&spi0_pins>; mediatek,pad-select = <0>; + + cros_ec: ec@0 { + #address-cells = <1>; + #size-cells = <0>; + + compatible = "google,cros-ec-spi"; + reg = <0>; + interrupts-extended = <&pio 4 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&cros_ec_int>; + spi-max-frequency = <3000000>; + + keyboard-backlight { + compatible = "google,cros-kbd-led-backlight"; + }; + + i2c_tunnel: i2c-tunnel { + compatible = "google,cros-ec-i2c-tunnel"; + google,remote-bus = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + mt_pmic_vmc_ldo_reg: regulator@0 { + compatible = "google,cros-ec-regulator"; + reg = <0>; + regulator-name = "mt_pmic_vmc_ldo"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3600000>; + }; + + mt_pmic_vmch_ldo_reg: regulator@1 { + compatible = "google,cros-ec-regulator"; + reg = <1>; + regulator-name = "mt_pmic_vmch_ldo"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3600000>; + }; + + typec { + compatible = "google,cros-ec-typec"; + #address-cells = <1>; + #size-cells = <0>; + + usb_c0: connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + power-role = "dual"; + data-role = "host"; + try-power-role = "source"; + }; + + usb_c1: connector@1 { + compatible = "usb-c-connector"; + reg = <1>; + power-role = "dual"; + data-role = "host"; + try-power-role = "source"; + }; + }; + }; }; &u3phy0 { @@ -729,3 +803,6 @@ vusb33-supply = <&mt6359_vusb_ldo_reg>; vbus-supply = <&usb_vbus>; }; + +#include +#include -- cgit v1.2.3-59-g8ed1b From 63ce81b224dd8033fd5f629fb4581a26eedd5797 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Fri, 2 Sep 2022 10:11:52 +0200 Subject: arm64: dts: mediatek: cherry: Add Google Security Chip (GSC) TPM Add support for the Cr50 Google Security Chip (GSC) found on this platform on I2C3 to support TPM and to also use it as an entropy source for the kernel. Signed-off-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20220902081156.38526-4-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi index 73f531f84fa2..a07e7fe66315 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi @@ -149,6 +149,14 @@ clock-frequency = <400000>; pinctrl-names = "default"; pinctrl-0 = <&i2c3_pins>; + + tpm@50 { + compatible = "google,cr50"; + reg = <0x50>; + interrupts-extended = <&pio 88 IRQ_TYPE_EDGE_FALLING>; + pinctrl-names = "default"; + pinctrl-0 = <&cr50_int>; + }; }; &i2c4 { @@ -426,6 +434,13 @@ "AP_SPI_FLASH_MOSI", "AP_SPI_FLASH_MISO"; + cr50_int: cr50-irq-default-pins { + pins-gsc-ap-int-odl { + pinmux = ; + input-enable; + }; + }; + cros_ec_int: cros-ec-irq-default-pins { pins-ec-ap-int-odl { pinmux = ; -- cgit v1.2.3-59-g8ed1b From 824fae69f53b914b30fb279ae73d04dd35df432a Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Fri, 2 Sep 2022 10:11:53 +0200 Subject: arm64: dts: mediatek: cherry: Add keyboard mapping for the top row Chromebooks' embedded keyboards differ from standard layouts for the top row, as this one doesn't have the standard function keys but shortcuts instead: map these keys to achieve the functionality that is pictured on the printouts. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Chen-Yu Tsai Tested-by: Chen-Yu Tsai Link: https://lore.kernel.org/r/20220902081156.38526-5-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi | 30 +++++++++++++++++++++++++ 1 file changed, 30 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi index a07e7fe66315..1174ab344e47 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi @@ -821,3 +821,33 @@ #include #include + +&keyboard_controller { + function-row-physmap = < + MATRIX_KEY(0x00, 0x02, 0) /* T1 */ + MATRIX_KEY(0x03, 0x02, 0) /* T2 */ + MATRIX_KEY(0x02, 0x02, 0) /* T3 */ + MATRIX_KEY(0x01, 0x02, 0) /* T4 */ + MATRIX_KEY(0x03, 0x04, 0) /* T5 */ + MATRIX_KEY(0x02, 0x04, 0) /* T6 */ + MATRIX_KEY(0x01, 0x04, 0) /* T7 */ + MATRIX_KEY(0x02, 0x09, 0) /* T8 */ + MATRIX_KEY(0x01, 0x09, 0) /* T9 */ + MATRIX_KEY(0x00, 0x04, 0) /* T10 */ + >; + + linux,keymap = < + MATRIX_KEY(0x00, 0x02, KEY_BACK) + MATRIX_KEY(0x03, 0x02, KEY_REFRESH) + MATRIX_KEY(0x02, 0x02, KEY_ZOOM) + MATRIX_KEY(0x01, 0x02, KEY_SCALE) + MATRIX_KEY(0x03, 0x04, KEY_SYSRQ) + MATRIX_KEY(0x02, 0x04, KEY_BRIGHTNESSDOWN) + MATRIX_KEY(0x01, 0x04, KEY_BRIGHTNESSUP) + MATRIX_KEY(0x02, 0x09, KEY_MUTE) + MATRIX_KEY(0x01, 0x09, KEY_VOLUMEDOWN) + MATRIX_KEY(0x00, 0x04, KEY_VOLUMEUP) + + CROS_STD_MAIN_KEYMAP + >; +}; -- cgit v1.2.3-59-g8ed1b From 07984e82ae3b8cf09a8d3d78b6a691f275d38036 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Fri, 2 Sep 2022 10:11:54 +0200 Subject: arm64: dts: mediatek: cherry: Enable secondary SD/MMC controller As of now, all of the boards based on the cherry platform have a usable secondary SD/MMC controller, usually for SD cards: enable it to allow both booting from it and generally accessing external storage. Signed-off-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20220902081156.38526-6-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi | 45 +++++++++++++++++++++++++ 1 file changed, 45 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi index 1174ab344e47..0654a28e6782 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi @@ -17,6 +17,7 @@ i2c5 = &i2c5; i2c7 = &i2c7; mmc0 = &mmc0; + mmc1 = &mmc1; serial0 = &uart0; }; @@ -227,6 +228,24 @@ vqmmc-supply = <&mt6359_vufs_ldo_reg>; }; +&mmc1 { + status = "okay"; + + bus-width = <4>; + cap-sd-highspeed; + cd-gpios = <&pio 54 GPIO_ACTIVE_LOW>; + max-frequency = <200000000>; + no-mmc; + no-sdio; + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&mmc1_pins_default>, <&mmc1_pins_detect>; + pinctrl-1 = <&mmc1_pins_default>; + sd-uhs-sdr50; + sd-uhs-sdr104; + vmmc-supply = <&mt_pmic_vmch_ldo_reg>; + vqmmc-supply = <&mt_pmic_vmc_ldo_reg>; +}; + /* for CPU-L */ &mt6359_vcore_buck_reg { regulator-always-on; @@ -575,6 +594,32 @@ }; }; + mmc1_pins_detect: mmc1-detect-pins { + pins-insert { + pinmux = ; + bias-pull-up; + }; + }; + + mmc1_pins_default: mmc1-default-pins { + pins-cmd-dat { + pinmux = , + , + , + , + ; + input-enable; + drive-strength = <8>; + bias-pull-up = ; + }; + + pins-clk { + pinmux = ; + drive-strength = <8>; + bias-pull-down = ; + }; + }; + nor_pins_default: nor-default-pins { pins-ck-io { pinmux = , -- cgit v1.2.3-59-g8ed1b From b53f37249cfa4e2e0caacdc72f4a8dfdb8574419 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Fri, 2 Sep 2022 10:11:55 +0200 Subject: arm64: dts: mediatek: cherry: Enable Elantech eKTH3000 i2c trackpad The Cherry platform uses an Elantech touchpad/trackpad: enable probing it at address 0x15 on I2C1. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Chen-Yu Tsai Tested-by: Chen-Yu Tsai Link: https://lore.kernel.org/r/20220902081156.38526-7-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi index 0654a28e6782..ee59619068d9 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi @@ -134,6 +134,16 @@ i2c-scl-internal-delay-ns = <12500>; pinctrl-names = "default"; pinctrl-0 = <&i2c1_pins>; + + trackpad@15 { + compatible = "elan,ekth3000"; + reg = <0x15>; + interrupts-extended = <&pio 6 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&trackpad_pins>; + vcc-supply = <&pp3300_s3>; + wakeup-source; + }; }; &i2c2 { @@ -710,6 +720,14 @@ }; }; + trackpad_pins: trackpad-default-pins { + pins-int-n { + pinmux = ; + input-enable; + bias-pull-up; + }; + }; + touchscreen_pins: touchscreen-default-pins { pins-int-n { pinmux = ; -- cgit v1.2.3-59-g8ed1b From 260c04d425eb8424626b64e164faebeb63c67625 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Fri, 2 Sep 2022 10:11:56 +0200 Subject: arm64: dts: mediatek: cherry: Enable MT6315 regulators on SPMI bus All machines in the Cherry platform use MT6315 over SPMI: add the two instances, providing Vbcpu and Vgpu regulators. Signed-off-by: AngeloGioacchino Del Regno Tested-by: Chen-Yu Tsai Link: https://lore.kernel.org/r/20220902081156.38526-8-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi | 42 +++++++++++++++++++++++++ 1 file changed, 42 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi index ee59619068d9..9b62e161db26 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi @@ -4,6 +4,7 @@ */ #include +#include #include "mt8195.dtsi" #include "mt6359.dtsi" @@ -832,6 +833,47 @@ }; }; +&spmi { + #address-cells = <2>; + #size-cells = <0>; + + mt6315@6 { + compatible = "mediatek,mt6315-regulator"; + reg = <0x6 SPMI_USID>; + + regulators { + mt6315_6_vbuck1: vbuck1 { + regulator-compatible = "vbuck1"; + regulator-name = "Vbcpu"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1193750>; + regulator-enable-ramp-delay = <256>; + regulator-ramp-delay = <6250>; + regulator-allowed-modes = <0 1 2>; + regulator-always-on; + }; + }; + }; + + mt6315@7 { + compatible = "mediatek,mt6315-regulator"; + reg = <0x7 SPMI_USID>; + + regulators { + mt6315_7_vbuck1: vbuck1 { + regulator-compatible = "vbuck1"; + regulator-name = "Vgpu"; + regulator-min-microvolt = <625000>; + regulator-max-microvolt = <1193750>; + regulator-enable-ramp-delay = <256>; + regulator-ramp-delay = <6250>; + regulator-allowed-modes = <0 1 2>; + regulator-always-on; + }; + }; + }; +}; + &u3phy0 { status = "okay"; }; -- cgit v1.2.3-59-g8ed1b From 300218b0503d40f3efc69363ca70b7f75c3ba81f Mon Sep 17 00:00:00 2001 From: Peter Chiu Date: Thu, 1 Sep 2022 21:05:52 +0800 Subject: arm64: dts: mt7986: add built-in Wi-Fi device nodes This enables built-in 802.11ax Wi-Fi support. Reviewed-by: Sam Shih Reviewed-by: Ryder Lee Signed-off-by: Peter Chiu Link: https://lore.kernel.org/r/20220901130552.26234-1-chui-hao.chiu@mediatek.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts | 38 ++++++++++++++++++++++++++ arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 23 ++++++++++++++++ arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts | 40 ++++++++++++++++++++++++++++ 3 files changed, 101 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts b/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts index 882277a52b69..afe37b702eef 100644 --- a/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts +++ b/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts @@ -115,6 +115,13 @@ status = "okay"; }; +&wifi { + status = "okay"; + pinctrl-names = "default", "dbdc"; + pinctrl-0 = <&wf_2g_5g_pins>; + pinctrl-1 = <&wf_dbdc_pins>; +}; + &pio { uart1_pins: uart1-pins { mux { @@ -129,4 +136,35 @@ groups = "uart2"; }; }; + + wf_2g_5g_pins: wf-2g-5g-pins { + mux { + function = "wifi"; + groups = "wf_2g", "wf_5g"; + }; + conf { + pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4", + "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6", + "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10", + "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1", + "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0", + "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8", + "WF1_TOP_CLK", "WF1_TOP_DATA"; + drive-strength = <4>; + }; + }; + + wf_dbdc_pins: wf-dbdc-pins { + mux { + function = "wifi"; + groups = "wf_dbdc"; + }; + conf { + pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4", + "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6", + "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10", + "WF0_TOP_CLK", "WF0_TOP_DATA"; + drive-strength = <4>; + }; + }; }; diff --git a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi index e3a407d03551..890ded0efc51 100644 --- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi @@ -7,6 +7,7 @@ #include #include #include +#include / { interrupt-parent = <&gic>; @@ -70,6 +71,11 @@ reg = <0 0x43000000 0 0x30000>; no-map; }; + + wmcpu_emi: wmcpu-reserved@4fc00000 { + no-map; + reg = <0 0x4fc00000 0 0x00100000>; + }; }; timer { @@ -261,6 +267,23 @@ #size-cells = <0>; status = "disabled"; }; + + wifi: wifi@18000000 { + compatible = "mediatek,mt7986-wmac"; + resets = <&watchdog MT7986_TOPRGU_CONSYS_SW_RST>; + reset-names = "consys"; + clocks = <&topckgen CLK_TOP_CONN_MCUSYS_SEL>, + <&topckgen CLK_TOP_AP2CNN_HOST_SEL>; + clock-names = "mcu", "ap2conn"; + reg = <0 0x18000000 0 0x1000000>, + <0 0x10003000 0 0x1000>, + <0 0x11d10000 0 0x1000>; + interrupts = , + , + , + ; + memory-region = <&wmcpu_emi>; + }; }; }; diff --git a/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts b/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts index 0f49d5764ff3..3443013b5971 100644 --- a/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts +++ b/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts @@ -98,3 +98,43 @@ }; }; }; + +&wifi { + status = "okay"; + pinctrl-names = "default", "dbdc"; + pinctrl-0 = <&wf_2g_5g_pins>; + pinctrl-1 = <&wf_dbdc_pins>; +}; + +&pio { + wf_2g_5g_pins: wf-2g-5g-pins { + mux { + function = "wifi"; + groups = "wf_2g", "wf_5g"; + }; + conf { + pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4", + "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6", + "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10", + "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1", + "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0", + "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8", + "WF1_TOP_CLK", "WF1_TOP_DATA"; + drive-strength = <4>; + }; + }; + + wf_dbdc_pins: wf-dbdc-pins { + mux { + function = "wifi"; + groups = "wf_dbdc"; + }; + conf { + pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4", + "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6", + "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10", + "WF0_TOP_CLK", "WF0_TOP_DATA"; + drive-strength = <4>; + }; + }; +}; -- cgit v1.2.3-59-g8ed1b From 5ebb14aa5a193b3a6a5c359bdd4d3573cb14bdf1 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Fri, 29 Jul 2022 11:35:36 +0200 Subject: arm64: dts: mediatek: mt6795: Add CPUX system timer node Add a node for mt6795-systimer: this is necessary to start the System Timer(s) for all cores, finally making CNTVCT_EL0 usable. Signed-off-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20220729093536.27623-1-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt6795.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/mediatek/mt6795.dtsi b/arch/arm64/boot/dts/mediatek/mt6795.dtsi index d4842b4a4eb7..46f0e54be766 100644 --- a/arch/arm64/boot/dts/mediatek/mt6795.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt6795.dtsi @@ -230,6 +230,14 @@ reg = <0 0x10200620 0 0x20>; }; + systimer: timer@10200670 { + compatible = "mediatek,mt6795-systimer"; + reg = <0 0x10200670 0 0x10>; + interrupts = ; + clocks = <&system_clk>; + clock-names = "clk13m"; + }; + gic: interrupt-controller@10221000 { compatible = "arm,gic-400"; #interrupt-cells = <3>; -- cgit v1.2.3-59-g8ed1b