From 26a7e06dfee97b3fb1a4491d55831de7ef4723fd Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Tue, 17 Nov 2015 02:42:32 +0900 Subject: arm64: renesas: r8a7795: Add Renesas R8A7795 SoC support Initial version of Renesas R-Car H3 support (V10) Signed-off-by: Gaku Inami Signed-off-by: Kuninori Morimoto Signed-off-by: Magnus Damm Signed-off-by: Simon Horman Acked-by: Geert Uytterhoeven --- arch/arm64/boot/dts/Makefile | 1 + arch/arm64/boot/dts/renesas/Makefile | 2 + arch/arm64/boot/dts/renesas/r8a7795.dtsi | 83 ++++++++++++++++++++++++++++++++ 3 files changed, 86 insertions(+) create mode 100644 arch/arm64/boot/dts/renesas/Makefile create mode 100644 arch/arm64/boot/dts/renesas/r8a7795.dtsi (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile index eb3c42d97175..0e775e4d6a00 100644 --- a/arch/arm64/boot/dts/Makefile +++ b/arch/arm64/boot/dts/Makefile @@ -10,6 +10,7 @@ dts-dirs += hisilicon dts-dirs += marvell dts-dirs += mediatek dts-dirs += qcom +dts-dirs += renesas dts-dirs += rockchip dts-dirs += sprd dts-dirs += xilinx diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile new file mode 100644 index 000000000000..fec69f46d65b --- /dev/null +++ b/arch/arm64/boot/dts/renesas/Makefile @@ -0,0 +1,2 @@ +always := $(dtb-y) +clean-files := *.dtb diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi new file mode 100644 index 000000000000..8d7552020daf --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi @@ -0,0 +1,83 @@ +/* + * Device Tree Source for the r8a7795 SoC + * + * Copyright (C) 2015 Renesas Electronics Corp. + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +#include + +/ { + compatible = "renesas,r8a7795"; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + /* 1 core only at this point */ + a57_0: cpu@0 { + compatible = "arm,cortex-a57", "arm,armv8"; + reg = <0x0>; + device_type = "cpu"; + }; + }; + + extal_clk: extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + + extalr_clk: extalr { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + + soc { + compatible = "simple-bus"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gic: interrupt-controller@0xf1010000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x0 0xf1010000 0 0x1000>, + <0x0 0xf1020000 0 0x2000>; + interrupts = ; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; + + cpg: clock-controller@e6150000 { + compatible = "renesas,r8a7795-cpg-mssr"; + reg = <0 0xe6150000 0 0x1000>; + clocks = <&extal_clk>, <&extalr_clk>; + clock-names = "extal", "extalr"; + #clock-cells = <2>; + #power-domain-cells = <0>; + }; + }; +}; -- cgit v1.2.3-59-g8ed1b From d920212667ecdceea144fae267f81cb119f5d8e7 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 2 Oct 2015 11:55:40 +0900 Subject: arm64: renesas: r8a7795: Add dummy dma-controller nodes Add dummy nodes for the 3 DMA controllers. This allows to start describing DMA channels for DMA slaves now. Signed-off-by: Geert Uytterhoeven Signed-off-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a7795.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi index 8d7552020daf..9e1de4d6615c 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi @@ -79,5 +79,17 @@ #clock-cells = <2>; #power-domain-cells = <0>; }; + + dmac0: dma-controller@e6700000 { + /* Empty node for now */ + }; + + dmac1: dma-controller@e7300000 { + /* Empty node for now */ + }; + + dmac2: dma-controller@e7310000 { + /* Empty node for now */ + }; }; }; -- cgit v1.2.3-59-g8ed1b From 49af46b4095672344641438c7035cc6c826d1809 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 2 Oct 2015 11:55:51 +0900 Subject: arm64: renesas: r8a7795: Add all SCIF nodes Add the device nodes for all R-Car H3 SCIF serial ports, incl. clocks, clock domain, and dma properties. Signed-off-by: Geert Uytterhoeven Signed-off-by: Kuninori Morimoto Signed-off-by: Gaku Inami Acked-by: Laurent Pinchart Signed-off-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a7795.dtsi | 73 ++++++++++++++++++++++++++++++++ 1 file changed, 73 insertions(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi index 9e1de4d6615c..002b828e8230 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi @@ -8,6 +8,7 @@ * kind, whether express or implied. */ +#include #include / { @@ -91,5 +92,77 @@ dmac2: dma-controller@e7310000 { /* Empty node for now */ }; + + scif0: serial@e6e60000 { + compatible = "renesas,scif-r8a7795", "renesas,scif"; + reg = <0 0xe6e60000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 207>; + clock-names = "sci_ick"; + dmas = <&dmac1 0x51>, <&dmac1 0x50>; + dma-names = "tx", "rx"; + power-domains = <&cpg>; + status = "disabled"; + }; + + scif1: serial@e6e68000 { + compatible = "renesas,scif-r8a7795", "renesas,scif"; + reg = <0 0xe6e68000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 206>; + clock-names = "sci_ick"; + dmas = <&dmac1 0x53>, <&dmac1 0x52>; + dma-names = "tx", "rx"; + power-domains = <&cpg>; + status = "disabled"; + }; + + scif2: serial@e6e88000 { + compatible = "renesas,scif-r8a7795", "renesas,scif"; + reg = <0 0xe6e88000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 310>; + clock-names = "sci_ick"; + dmas = <&dmac1 0x13>, <&dmac1 0x12>; + dma-names = "tx", "rx"; + power-domains = <&cpg>; + status = "disabled"; + }; + + scif3: serial@e6c50000 { + compatible = "renesas,scif-r8a7795", "renesas,scif"; + reg = <0 0xe6c50000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 204>; + clock-names = "sci_ick"; + dmas = <&dmac0 0x57>, <&dmac0 0x56>; + dma-names = "tx", "rx"; + power-domains = <&cpg>; + status = "disabled"; + }; + + scif4: serial@e6c40000 { + compatible = "renesas,scif-r8a7795", "renesas,scif"; + reg = <0 0xe6c40000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 203>; + clock-names = "sci_ick"; + dmas = <&dmac0 0x59>, <&dmac0 0x58>; + dma-names = "tx", "rx"; + power-domains = <&cpg>; + status = "disabled"; + }; + + scif5: serial@e6f30000 { + compatible = "renesas,scif-r8a7795", "renesas,scif"; + reg = <0 0xe6f30000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 202>; + clock-names = "sci_ick"; + dmas = <&dmac1 0x5b>, <&dmac1 0x5a>; + dma-names = "tx", "rx"; + power-domains = <&cpg>; + status = "disabled"; + }; }; }; -- cgit v1.2.3-59-g8ed1b From 9241844a2d3312f3984aacd16ad25fda6e83fc13 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Fri, 2 Oct 2015 11:56:01 +0900 Subject: arm64: renesas: r8a7795: enable PFC Add a PFC node for the on-chip r8a7795 pin controller. Signed-off-by: Kuninori Morimoto Acked-by: Geert Uytterhoeven Acked-by: Laurent Pinchart Signed-off-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a7795.dtsi | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi index 002b828e8230..e26eecf1230f 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi @@ -81,6 +81,11 @@ #power-domain-cells = <0>; }; + pfc: pfc@e6060000 { + compatible = "renesas,pfc-r8a7795"; + reg = <0 0xe6060000 0 0x50c>; + }; + dmac0: dma-controller@e6700000 { /* Empty node for now */ }; -- cgit v1.2.3-59-g8ed1b From 1950fab0789111de4ba3406c6e93dc57e345d32c Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Fri, 2 Oct 2015 11:56:12 +0900 Subject: arm64: renesas: add Salvator-X board support Add initial board support for r8a7795 Salvator-X. At this point only DEBUG0 and DEBUG1 serial ports are supported. Signed-off-by: Kuninori Morimoto Signed-off-by: Gaku Inami Signed-off-by: Takeshi Kihara Signed-off-by: Geert Uytterhoeven Signed-off-by: Magnus Damm Signed-off-by: Simon Horman --- Documentation/devicetree/bindings/arm/shmobile.txt | 2 + arch/arm64/boot/dts/renesas/Makefile | 2 + arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts | 62 ++++++++++++++++++++++ 3 files changed, 66 insertions(+) create mode 100644 arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts (limited to 'arch/arm64/boot') diff --git a/Documentation/devicetree/bindings/arm/shmobile.txt b/Documentation/devicetree/bindings/arm/shmobile.txt index 6712ebbe5f49..678a8184da24 100644 --- a/Documentation/devicetree/bindings/arm/shmobile.txt +++ b/Documentation/devicetree/bindings/arm/shmobile.txt @@ -59,5 +59,7 @@ Boards: compatible = "renesas,marzen", "renesas,r8a7779" - Porter (M2-LCDP) compatible = "renesas,porter", "renesas,r8a7791" + - Salvator-X + compatible = "renesas,salvator-x", "renesas,r8a7795"; - SILK (RTP0RC7794LCB00011S) compatible = "renesas,silk", "renesas,r8a7794" diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile index fec69f46d65b..9ce1890a650e 100644 --- a/arch/arm64/boot/dts/renesas/Makefile +++ b/arch/arm64/boot/dts/renesas/Makefile @@ -1,2 +1,4 @@ +dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-salvator-x.dtb + always := $(dtb-y) clean-files := *.dtb diff --git a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts new file mode 100644 index 000000000000..a3db98384e53 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts @@ -0,0 +1,62 @@ +/* + * Device Tree Source for the Salvator-X board + * + * Copyright (C) 2015 Renesas Electronics Corp. + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +/dts-v1/; +#include "r8a7795.dtsi" + +/ { + model = "Renesas Salvator-X board based on r8a7795"; + compatible = "renesas,salvator-x", "renesas,r8a7795"; + + aliases { + serial0 = &scif2; + serial1 = &scif1; + }; + + chosen { + bootargs = "ignore_loglevel"; + stdout-path = "serial0:115200n8"; + }; + + memory@48000000 { + device_type = "memory"; + /* first 128MB is reserved for secure area. */ + reg = <0x0 0x48000000 0x0 0x38000000>; + }; +}; + +&extal_clk { + clock-frequency = <16666666>; +}; + +&pfc { + scif1_pins: scif1 { + renesas,groups = "scif1_data_a", "scif1_ctrl"; + renesas,function = "scif1"; + }; + scif2_pins: scif2 { + renesas,groups = "scif2_data_a"; + renesas,function = "scif2"; + }; +}; + +&scif1 { + pinctrl-0 = <&scif1_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&scif2 { + pinctrl-0 = <&scif2_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; -- cgit v1.2.3-59-g8ed1b From 33a93aa490ae256d0b982e2d66cf570cf61f95de Mon Sep 17 00:00:00 2001 From: Anup Patel Date: Fri, 2 Oct 2015 23:24:18 +0530 Subject: arm64: dts: Add L2-cache DT node for NS2 Recent kernels requires cache hierrachy to be defined via DT hence this patch updates NS2 DT accordingly. Signed-off-by: Anup Patel Reviewed-by: Sandeep Tripathy Reviewed-by: Ray Jui Reviewed-by: Scott Branden Signed-off-by: Florian Fainelli --- arch/arm64/boot/dts/broadcom/ns2.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/broadcom/ns2.dtsi b/arch/arm64/boot/dts/broadcom/ns2.dtsi index 3c92d92278e5..f7591755c37a 100644 --- a/arch/arm64/boot/dts/broadcom/ns2.dtsi +++ b/arch/arm64/boot/dts/broadcom/ns2.dtsi @@ -50,6 +50,7 @@ reg = <0 0>; enable-method = "spin-table"; cpu-release-addr = <0 0x84b00000>; + next-level-cache = <&CLUSTER0_L2>; }; cpu@1 { @@ -58,6 +59,7 @@ reg = <0 1>; enable-method = "spin-table"; cpu-release-addr = <0 0x84b00000>; + next-level-cache = <&CLUSTER0_L2>; }; cpu@2 { @@ -66,6 +68,7 @@ reg = <0 2>; enable-method = "spin-table"; cpu-release-addr = <0 0x84b00000>; + next-level-cache = <&CLUSTER0_L2>; }; cpu@3 { @@ -74,6 +77,11 @@ reg = <0 3>; enable-method = "spin-table"; cpu-release-addr = <0 0x84b00000>; + next-level-cache = <&CLUSTER0_L2>; + }; + + CLUSTER0_L2: l2-cache@000 { + compatible = "cache"; }; }; -- cgit v1.2.3-59-g8ed1b From 6ec5f3c5264795290f3d7ed67286cca2c1486bfe Mon Sep 17 00:00:00 2001 From: Anup Patel Date: Fri, 2 Oct 2015 23:24:19 +0530 Subject: arm64: dts: Add SMMU DT node for NS2 The SMMU-500 driver is already available in Linux kernel. Let's enable it for NS2 in DT. This patch keeps mmu-masters attribute empty so that driver patches can later extend this attribute when adding device DT nodes. Signed-off-by: Anup Patel Reviewed-by: Ray Jui Reviewed-by: Scott Branden Signed-off-by: Florian Fainelli --- arch/arm64/boot/dts/broadcom/ns2.dtsi | 41 +++++++++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/broadcom/ns2.dtsi b/arch/arm64/boot/dts/broadcom/ns2.dtsi index f7591755c37a..c5d90e4d76fa 100644 --- a/arch/arm64/boot/dts/broadcom/ns2.dtsi +++ b/arch/arm64/boot/dts/broadcom/ns2.dtsi @@ -103,6 +103,47 @@ #size-cells = <1>; ranges = <0 0 0 0xffffffff>; + smmu: mmu@64000000 { + compatible = "arm,mmu-500"; + reg = <0x64000000 0x40000>; + #global-interrupts = <2>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + mmu-masters; + }; + gic: interrupt-controller@65210000 { compatible = "arm,gic-400"; #interrupt-cells = <3>; -- cgit v1.2.3-59-g8ed1b From 5b467c3b2d36b6ed8a6d17923c12f3091d83ce77 Mon Sep 17 00:00:00 2001 From: Anup Patel Date: Fri, 2 Oct 2015 23:24:20 +0530 Subject: arm64: dts: Add syscon based reboot in DT for NS2 To reset NS2, we simply have to write '0' to BIT[1] at offset 0x90 of CRMU space. The above can be easily achieved by writing 0xfffffffd at offset 0x90 using syscon-reboot driver. We don't need to have separate driver for rebooting NS2. This patch enables syscon-reboot driver for NS2 using DT. Signed-off-by: Anup Patel Reviewed-by: Ray Jui Reviewed-by: Scott Branden Signed-off-by: Florian Fainelli --- arch/arm64/boot/dts/broadcom/ns2.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/broadcom/ns2.dtsi b/arch/arm64/boot/dts/broadcom/ns2.dtsi index c5d90e4d76fa..5d2ac6b548b1 100644 --- a/arch/arm64/boot/dts/broadcom/ns2.dtsi +++ b/arch/arm64/boot/dts/broadcom/ns2.dtsi @@ -144,6 +144,18 @@ mmu-masters; }; + crmu: crmu@65024000 { + compatible = "syscon"; + reg = <0x65024000 0x100>; + }; + + reboot@65024000 { + compatible ="syscon-reboot"; + regmap = <&crmu>; + offset = <0x90>; + mask = <0xfffffffd>; + }; + gic: interrupt-controller@65210000 { compatible = "arm,gic-400"; #interrupt-cells = <3>; -- cgit v1.2.3-59-g8ed1b From 5b31d8759bcc36ad994e38970b7cca5195d8bc19 Mon Sep 17 00:00:00 2001 From: Anup Patel Date: Fri, 2 Oct 2015 23:24:21 +0530 Subject: arm64: dts: Add ARM PMUv3 DT node in NS2 DT The NS2 SoC has Cortex-A57 CPUs which support ARM PMUv3 so, lets enable ARM PMUv3 in NS2 DT. Signed-off-by: Anup Patel Reviewed-by: Vikram Prakash Reviewed-by: Ray Jui Reviewed-by: Scott Branden Signed-off-by: Florian Fainelli --- arch/arm64/boot/dts/broadcom/ns2.dtsi | 20 ++++++++++++++++---- 1 file changed, 16 insertions(+), 4 deletions(-) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/broadcom/ns2.dtsi b/arch/arm64/boot/dts/broadcom/ns2.dtsi index 5d2ac6b548b1..bc31c0e6eec4 100644 --- a/arch/arm64/boot/dts/broadcom/ns2.dtsi +++ b/arch/arm64/boot/dts/broadcom/ns2.dtsi @@ -44,7 +44,7 @@ #address-cells = <2>; #size-cells = <0>; - cpu@0 { + A57_0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a57", "arm,armv8"; reg = <0 0>; @@ -53,7 +53,7 @@ next-level-cache = <&CLUSTER0_L2>; }; - cpu@1 { + A57_1: cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a57", "arm,armv8"; reg = <0 1>; @@ -62,7 +62,7 @@ next-level-cache = <&CLUSTER0_L2>; }; - cpu@2 { + A57_2: cpu@2 { device_type = "cpu"; compatible = "arm,cortex-a57", "arm,armv8"; reg = <0 2>; @@ -71,7 +71,7 @@ next-level-cache = <&CLUSTER0_L2>; }; - cpu@3 { + A57_3: cpu@3 { device_type = "cpu"; compatible = "arm,cortex-a57", "arm,armv8"; reg = <0 3>; @@ -97,6 +97,18 @@ IRQ_TYPE_EDGE_RISING)>; }; + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = , + , + , + ; + interrupt-affinity = <&A57_0>, + <&A57_1>, + <&A57_2>, + <&A57_3>; + }; + soc: soc { compatible = "simple-bus"; #address-cells = <1>; -- cgit v1.2.3-59-g8ed1b From e8a6e265f595e93ac54bc8238d6afd350df4b793 Mon Sep 17 00:00:00 2001 From: Anup Patel Date: Fri, 2 Oct 2015 23:24:22 +0530 Subject: arm64: dts: Add IPROC RNG200 DT node for NS2 We have IPROC RNG200 hardware random number generation in NS2 SoC, lets enable it for NS2 in NS2 DT. Signed-off-by: Anup Patel Reviewed-by: Ray Jui Reviewed-by: Pramod KUMAR Reviewed-by: Vikram Prakash Reviewed-by: Scott Branden Signed-off-by: Florian Fainelli --- arch/arm64/boot/dts/broadcom/ns2.dtsi | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/broadcom/ns2.dtsi b/arch/arm64/boot/dts/broadcom/ns2.dtsi index bc31c0e6eec4..92ecf1c921e5 100644 --- a/arch/arm64/boot/dts/broadcom/ns2.dtsi +++ b/arch/arm64/boot/dts/broadcom/ns2.dtsi @@ -187,5 +187,10 @@ clock-frequency = <23961600>; status = "disabled"; }; + + hwrng: hwrng@66220000 { + compatible = "brcm,iproc-rng200"; + reg = <0x66220000 0x28>; + }; }; }; -- cgit v1.2.3-59-g8ed1b From 7ac674e8df7aae461b92652026952d5b788c699b Mon Sep 17 00:00:00 2001 From: Ray Jui Date: Fri, 2 Oct 2015 23:24:23 +0530 Subject: arm64: dts: Add I2C nodes for NS2 This patch adds iProc I2C DT nodes for NS2 and enable them for the NS2 SVK board Signed-off-by: Ray Jui Reviewed-by: Vikram Prakash Reviewed-by: Scott Branden Signed-off-by: Florian Fainelli --- arch/arm64/boot/dts/broadcom/ns2-svk.dts | 8 ++++++++ arch/arm64/boot/dts/broadcom/ns2.dtsi | 20 ++++++++++++++++++++ 2 files changed, 28 insertions(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/broadcom/ns2-svk.dts b/arch/arm64/boot/dts/broadcom/ns2-svk.dts index 244baf879dc9..e5950d5c34e9 100644 --- a/arch/arm64/boot/dts/broadcom/ns2-svk.dts +++ b/arch/arm64/boot/dts/broadcom/ns2-svk.dts @@ -52,6 +52,14 @@ }; soc: soc { + i2c0: i2c@66080000 { + status = "ok"; + }; + + i2c1: i2c@660b0000 { + status = "ok"; + }; + uart3: serial@66130000 { status = "ok"; }; diff --git a/arch/arm64/boot/dts/broadcom/ns2.dtsi b/arch/arm64/boot/dts/broadcom/ns2.dtsi index 92ecf1c921e5..f60327780d18 100644 --- a/arch/arm64/boot/dts/broadcom/ns2.dtsi +++ b/arch/arm64/boot/dts/broadcom/ns2.dtsi @@ -178,6 +178,26 @@ <0x65260000 0x1000>; }; + i2c0: i2c@66080000 { + compatible = "brcm,iproc-i2c"; + reg = <0x66080000 0x100>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-frequency = <100000>; + status = "disabled"; + }; + + i2c1: i2c@660b0000 { + compatible = "brcm,iproc-i2c"; + reg = <0x660b0000 0x100>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-frequency = <100000>; + status = "disabled"; + }; + uart3: serial@66130000 { compatible = "snps,dw-apb-uart"; reg = <0x66130000 0x100>; -- cgit v1.2.3-59-g8ed1b From c6fe9a2edf4debba5697a01b5c134b9d515fad84 Mon Sep 17 00:00:00 2001 From: Anup Patel Date: Fri, 30 Oct 2015 12:29:21 +0530 Subject: arm64: dts: Add BRCM IPROC NAND DT node for NS2 The NAND controller on NS2 SoC is compatible with existing BRCM IPROC NAND driver so let's enable it in NS2 DT and NS2 SVK DT. This patch also fixes use of node labels in ns2-svk.dts. Signed-off-by: Anup Patel Reviewed-by: Ray Jui Reviewed-by: Scott Branden Reviewed-by: Brian Norris Signed-off-by: Florian Fainelli --- arch/arm64/boot/dts/broadcom/ns2-svk.dts | 30 ++++++++++++++++++++---------- arch/arm64/boot/dts/broadcom/ns2.dtsi | 14 ++++++++++++++ 2 files changed, 34 insertions(+), 10 deletions(-) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/broadcom/ns2-svk.dts b/arch/arm64/boot/dts/broadcom/ns2-svk.dts index e5950d5c34e9..6bb3d4d9efa9 100644 --- a/arch/arm64/boot/dts/broadcom/ns2-svk.dts +++ b/arch/arm64/boot/dts/broadcom/ns2-svk.dts @@ -50,18 +50,28 @@ device_type = "memory"; reg = <0x000000000 0x80000000 0x00000000 0x40000000>; }; +}; - soc: soc { - i2c0: i2c@66080000 { - status = "ok"; - }; +&i2c0 { + status = "ok"; +}; - i2c1: i2c@660b0000 { - status = "ok"; - }; +&i2c1 { + status = "ok"; +}; + +&uart3 { + status = "ok"; +}; - uart3: serial@66130000 { - status = "ok"; - }; +&nand { + nandcs@0 { + compatible = "brcm,nandcs"; + reg = <0>; + nand-ecc-mode = "hw"; + nand-ecc-strength = <8>; + nand-ecc-step-size = <512>; + #address-cells = <1>; + #size-cells = <1>; }; }; diff --git a/arch/arm64/boot/dts/broadcom/ns2.dtsi b/arch/arm64/boot/dts/broadcom/ns2.dtsi index f60327780d18..96108228410c 100644 --- a/arch/arm64/boot/dts/broadcom/ns2.dtsi +++ b/arch/arm64/boot/dts/broadcom/ns2.dtsi @@ -212,5 +212,19 @@ compatible = "brcm,iproc-rng200"; reg = <0x66220000 0x28>; }; + + nand: nand@66460000 { + compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1"; + reg = <0x66460000 0x600>, + <0x67015408 0x600>, + <0x66460f00 0x20>; + reg-names = "nand", "iproc-idm", "iproc-ext"; + interrupts = ; + + #address-cells = <1>; + #size-cells = <0>; + + brcm,nand-has-wp; + }; }; }; -- cgit v1.2.3-59-g8ed1b From 8f74e861862e17b3f03f095f6b3e8dc3bddc5f0c Mon Sep 17 00:00:00 2001 From: Suman Tripathi Date: Fri, 19 Jun 2015 17:30:26 +0530 Subject: arm64: dts: Add the arasan mmc DTS entries for APM X-Gene v1 SoC This patch adds the arasan mmc nodes to reuse the of-arasan driver for APM X-Gene v1 SoC platforms. [dhdang: changelog] Signed-off-by: Suman Tripathi Signed-off-by: Duc Dang --- arch/arm64/boot/dts/apm/apm-mustang.dts | 4 +++ arch/arm64/boot/dts/apm/apm-storm.dtsi | 44 +++++++++++++++++++++++++++++++++ 2 files changed, 48 insertions(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/apm/apm-mustang.dts b/arch/arm64/boot/dts/apm/apm-mustang.dts index 01cdeda93c3a..178aef2cdd09 100644 --- a/arch/arm64/boot/dts/apm/apm-mustang.dts +++ b/arch/arm64/boot/dts/apm/apm-mustang.dts @@ -74,3 +74,7 @@ &xgenet { status = "ok"; }; + +&mmc0 { + status = "ok"; +}; diff --git a/arch/arm64/boot/dts/apm/apm-storm.dtsi b/arch/arm64/boot/dts/apm/apm-storm.dtsi index 6c5ed119934f..445f68d83051 100644 --- a/arch/arm64/boot/dts/apm/apm-storm.dtsi +++ b/arch/arm64/boot/dts/apm/apm-storm.dtsi @@ -150,6 +150,40 @@ clock-output-names = "socplldiv2"; }; + ahbclk: ahbclk@1f2ac000 { + compatible = "apm,xgene-device-clock"; + #clock-cells = <1>; + clocks = <&socplldiv2 0>; + reg = <0x0 0x1f2ac000 0x0 0x1000 + 0x0 0x17000000 0x0 0x2000>; + reg-names = "csr-reg", "div-reg"; + csr-offset = <0x0>; + csr-mask = <0x1>; + enable-offset = <0x8>; + enable-mask = <0x1>; + divider-offset = <0x164>; + divider-width = <0x5>; + divider-shift = <0x0>; + clock-output-names = "ahbclk"; + }; + + sdioclk: sdioclk@1f2ac000 { + compatible = "apm,xgene-device-clock"; + #clock-cells = <1>; + clocks = <&socplldiv2 0>; + reg = <0x0 0x1f2ac000 0x0 0x1000 + 0x0 0x17000000 0x0 0x2000>; + reg-names = "csr-reg", "div-reg"; + csr-offset = <0x0>; + csr-mask = <0x2>; + enable-offset = <0x8>; + enable-mask = <0x2>; + divider-offset = <0x178>; + divider-width = <0x8>; + divider-shift = <0x0>; + clock-output-names = "sdioclk"; + }; + qmlclk: qmlclk { compatible = "apm,xgene-device-clock"; #clock-cells = <1>; @@ -686,6 +720,16 @@ interrupts = <0x0 0x4f 0x4>; }; + mmc0: mmc@1c000000 { + compatible = "arasan,sdhci-4.9a"; + reg = <0x0 0x1c000000 0x0 0x100>; + interrupts = <0x0 0x49 0x4>; + dma-coherent; + no-1-8-v; + clock-names = "clk_xin", "clk_ahb"; + clocks = <&sdioclk 0>, <&ahbclk 0>; + }; + phy1: phy@1f21a000 { compatible = "apm,xgene-phy"; reg = <0x0 0x1f21a000 0x0 0x100>; -- cgit v1.2.3-59-g8ed1b From 0ae8c000210ffe1a4ac93ad1bc4a8cce11841553 Mon Sep 17 00:00:00 2001 From: Duc Dang Date: Wed, 16 Sep 2015 17:12:57 +0530 Subject: arm64: dts: Add the arasan mmc DTS entries for APm X-Gene v2 SoC This patch adds the arasan mmc nodes to reuse the of-arasan driver for APM X-Gene v2 SoC platforms. Signed-off-by: Duc Dang --- arch/arm64/boot/dts/apm/apm-merlin.dts | 4 +++ arch/arm64/boot/dts/apm/apm-shadowcat.dtsi | 44 ++++++++++++++++++++++++++++++ 2 files changed, 48 insertions(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/apm/apm-merlin.dts b/arch/arm64/boot/dts/apm/apm-merlin.dts index 119a469bd189..a0092f977591 100644 --- a/arch/arm64/boot/dts/apm/apm-merlin.dts +++ b/arch/arm64/boot/dts/apm/apm-merlin.dts @@ -70,3 +70,7 @@ &xgenet1 { status = "ok"; }; + +&mmc0 { + status = "ok"; +}; diff --git a/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi b/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi index c804f8f1f38c..718ffc431b19 100644 --- a/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi +++ b/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi @@ -140,6 +140,40 @@ clock-output-names = "socplldiv2"; }; + ahbclk: ahbclk@1f2ac000 { + compatible = "apm,xgene-device-clock"; + #clock-cells = <1>; + clocks = <&socplldiv2 0>; + reg = <0x0 0x1f2ac000 0x0 0x1000 + 0x0 0x17000000 0x0 0x2000>; + reg-names = "csr-reg", "div-reg"; + csr-offset = <0x0>; + csr-mask = <0x1>; + enable-offset = <0x8>; + enable-mask = <0x1>; + divider-offset = <0x164>; + divider-width = <0x5>; + divider-shift = <0x0>; + clock-output-names = "ahbclk"; + }; + + sdioclk: sdioclk@1f2ac000 { + compatible = "apm,xgene-device-clock"; + #clock-cells = <1>; + clocks = <&socplldiv2 0>; + reg = <0x0 0x1f2ac000 0x0 0x1000 + 0x0 0x17000000 0x0 0x2000>; + reg-names = "csr-reg", "div-reg"; + csr-offset = <0x0>; + csr-mask = <0x2>; + enable-offset = <0x8>; + enable-mask = <0x2>; + divider-offset = <0x178>; + divider-width = <0x8>; + divider-shift = <0x0>; + clock-output-names = "sdioclk"; + }; + pcie0clk: pcie0clk@1f2bc000 { compatible = "apm,xgene-device-clock"; #clock-cells = <1>; @@ -224,6 +258,16 @@ dma-coherent; }; + mmc0: mmc@1c000000 { + compatible = "arasan,sdhci-4.9a"; + reg = <0x0 0x1c000000 0x0 0x100>; + interrupts = <0x0 0x49 0x4>; + dma-coherent; + no-1-8-v; + clock-names = "clk_xin", "clk_ahb"; + clocks = <&sdioclk 0>, <&ahbclk 0>; + }; + sbgpio: sbgpio@17001000{ compatible = "apm,xgene-gpio-sb"; reg = <0x0 0x17001000 0x0 0x400>; -- cgit v1.2.3-59-g8ed1b From b0e7a85a97413fb47f6ba40ac5497cfa40758664 Mon Sep 17 00:00:00 2001 From: Duc Dang Date: Thu, 22 Oct 2015 18:54:57 -0700 Subject: arm64: dts: X-Gene: Do not reset or enable/disable clock for AHB block Remove register information used to reset and enable/disable clock for AHB block as reseting AHB or disabling its clock will make other peripherals attached to it stop working. Signed-off-by: Duc Dang --- arch/arm64/boot/dts/apm/apm-shadowcat.dtsi | 11 +++-------- arch/arm64/boot/dts/apm/apm-storm.dtsi | 11 +++-------- 2 files changed, 6 insertions(+), 16 deletions(-) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi b/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi index 718ffc431b19..ddf1e86fa67e 100644 --- a/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi +++ b/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi @@ -140,17 +140,12 @@ clock-output-names = "socplldiv2"; }; - ahbclk: ahbclk@1f2ac000 { + ahbclk: ahbclk@17000000 { compatible = "apm,xgene-device-clock"; #clock-cells = <1>; clocks = <&socplldiv2 0>; - reg = <0x0 0x1f2ac000 0x0 0x1000 - 0x0 0x17000000 0x0 0x2000>; - reg-names = "csr-reg", "div-reg"; - csr-offset = <0x0>; - csr-mask = <0x1>; - enable-offset = <0x8>; - enable-mask = <0x1>; + reg = <0x0 0x17000000 0x0 0x2000>; + reg-names = "div-reg"; divider-offset = <0x164>; divider-width = <0x5>; divider-shift = <0x0>; diff --git a/arch/arm64/boot/dts/apm/apm-storm.dtsi b/arch/arm64/boot/dts/apm/apm-storm.dtsi index 445f68d83051..32f9ba9b6962 100644 --- a/arch/arm64/boot/dts/apm/apm-storm.dtsi +++ b/arch/arm64/boot/dts/apm/apm-storm.dtsi @@ -150,17 +150,12 @@ clock-output-names = "socplldiv2"; }; - ahbclk: ahbclk@1f2ac000 { + ahbclk: ahbclk@17000000 { compatible = "apm,xgene-device-clock"; #clock-cells = <1>; clocks = <&socplldiv2 0>; - reg = <0x0 0x1f2ac000 0x0 0x1000 - 0x0 0x17000000 0x0 0x2000>; - reg-names = "csr-reg", "div-reg"; - csr-offset = <0x0>; - csr-mask = <0x1>; - enable-offset = <0x8>; - enable-mask = <0x1>; + reg = <0x0 0x17000000 0x0 0x2000>; + reg-names = "div-reg"; divider-offset = <0x164>; divider-width = <0x5>; divider-shift = <0x0>; -- cgit v1.2.3-59-g8ed1b From e6ae03c4ba43a0623e333e2e8627c5647a71ae58 Mon Sep 17 00:00:00 2001 From: Duc Dang Date: Mon, 5 Oct 2015 16:36:10 -0700 Subject: arm64: dts: Add RNG device tree nodes for APM X-Gene v2 platform This patch adds device tree nodes to enable driver for True Random Number Generator (TRNG) on APM X-Gene v2 platforms. Signed-off-by: Duc Dang --- arch/arm64/boot/dts/apm/apm-shadowcat.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi b/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi index ddf1e86fa67e..630ed4a4ef1b 100644 --- a/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi +++ b/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi @@ -199,6 +199,19 @@ csr-mask = <0x3>; clock-output-names = "xge1clk"; }; + + rngpkaclk: rngpkaclk@17000000 { + compatible = "apm,xgene-device-clock"; + #clock-cells = <1>; + clocks = <&socplldiv2 0>; + reg = <0x0 0x17000000 0x0 0x2000>; + reg-names = "csr-reg"; + csr-offset = <0xc>; + csr-mask = <0x10>; + enable-offset = <0x10>; + enable-mask = <0x10>; + clock-output-names = "rngpkaclk"; + }; }; scu: system-clk-controller@17000000 { @@ -306,5 +319,12 @@ local-mac-address = [00 01 73 00 00 02]; phy-connection-type = "xgmii"; }; + + rng: rng@10520000 { + compatible = "apm,xgene-rng"; + reg = <0x0 0x10520000 0x0 0x100>; + interrupts = <0x0 0x41 0x4>; + clocks = <&rngpkaclk 0>; + }; }; }; -- cgit v1.2.3-59-g8ed1b From 726e92fdba7d6866ffb3f884af4a20f42e480095 Mon Sep 17 00:00:00 2001 From: Duc Dang Date: Mon, 12 Oct 2015 15:31:56 -0700 Subject: arm64: dts: Add v2m MSI frame nodes for APM X-Gene v2 platforms This patch adds all 16 v2m MSI frames that APM X-Gene v2 SoC supports into APM X-Gene v2 device tree. Signed-off-by: Duc Dang --- arch/arm64/boot/dts/apm/apm-shadowcat.dtsi | 80 ++++++++++++++++++++++++++++++ 1 file changed, 80 insertions(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi b/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi index 630ed4a4ef1b..b4e51925dfd2 100644 --- a/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi +++ b/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi @@ -89,6 +89,86 @@ <0x0 0x780A0000 0x0 0x20000>, /* GIC CPU */ <0x0 0x780C0000 0x0 0x10000>, /* GIC VCPU Control */ <0x0 0x780E0000 0x0 0x20000>; /* GIC VCPU */ + v2m0: v2m@0x00000 { + compatible = "arm,gic-v2m-frame"; + msi-controller; + reg = <0x0 0x0 0x0 0x1000>; + }; + v2m1: v2m@0x10000 { + compatible = "arm,gic-v2m-frame"; + msi-controller; + reg = <0x0 0x10000 0x0 0x1000>; + }; + v2m2: v2m@0x20000 { + compatible = "arm,gic-v2m-frame"; + msi-controller; + reg = <0x0 0x20000 0x0 0x1000>; + }; + v2m3: v2m@0x30000 { + compatible = "arm,gic-v2m-frame"; + msi-controller; + reg = <0x0 0x30000 0x0 0x1000>; + }; + v2m4: v2m@0x40000 { + compatible = "arm,gic-v2m-frame"; + msi-controller; + reg = <0x0 0x40000 0x0 0x1000>; + }; + v2m5: v2m@0x50000 { + compatible = "arm,gic-v2m-frame"; + msi-controller; + reg = <0x0 0x50000 0x0 0x1000>; + }; + v2m6: v2m@0x60000 { + compatible = "arm,gic-v2m-frame"; + msi-controller; + reg = <0x0 0x60000 0x0 0x1000>; + }; + v2m7: v2m@0x70000 { + compatible = "arm,gic-v2m-frame"; + msi-controller; + reg = <0x0 0x70000 0x0 0x1000>; + }; + v2m8: v2m@0x80000 { + compatible = "arm,gic-v2m-frame"; + msi-controller; + reg = <0x0 0x80000 0x0 0x1000>; + }; + v2m9: v2m@0x90000 { + compatible = "arm,gic-v2m-frame"; + msi-controller; + reg = <0x0 0x90000 0x0 0x1000>; + }; + v2m10: v2m@0xA0000 { + compatible = "arm,gic-v2m-frame"; + msi-controller; + reg = <0x0 0xA0000 0x0 0x1000>; + }; + v2m11: v2m@0xB0000 { + compatible = "arm,gic-v2m-frame"; + msi-controller; + reg = <0x0 0xB0000 0x0 0x1000>; + }; + v2m12: v2m@0xC0000 { + compatible = "arm,gic-v2m-frame"; + msi-controller; + reg = <0x0 0xC0000 0x0 0x1000>; + }; + v2m13: v2m@0xD0000 { + compatible = "arm,gic-v2m-frame"; + msi-controller; + reg = <0x0 0xD0000 0x0 0x1000>; + }; + v2m14: v2m@0xE0000 { + compatible = "arm,gic-v2m-frame"; + msi-controller; + reg = <0x0 0xE0000 0x0 0x1000>; + }; + v2m15: v2m@0xF0000 { + compatible = "arm,gic-v2m-frame"; + msi-controller; + reg = <0x0 0xF0000 0x0 0x1000>; + }; }; pmu { -- cgit v1.2.3-59-g8ed1b From b055e9de9a094887e879d44c20d753f494307b66 Mon Sep 17 00:00:00 2001 From: Duc Dang Date: Mon, 12 Oct 2015 16:09:17 -0700 Subject: arm64: dts: Add PCIe node for APM X-Gene v2 platforms This patch adds PCIe node to support PCIe controller with MSI capability for APM X-Gene v2 platform. Signed-off-by: Duc Dang --- arch/arm64/boot/dts/apm/apm-shadowcat.dtsi | 59 ++++++++++++++++++++++++++++++ 1 file changed, 59 insertions(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi b/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi index b4e51925dfd2..d50e19f24397 100644 --- a/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi +++ b/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi @@ -258,6 +258,15 @@ clock-output-names = "pcie0clk"; }; + pcie1clk: pcie1clk@1f2cc000 { + compatible = "apm,xgene-device-clock"; + #clock-cells = <1>; + clocks = <&socplldiv2 0>; + reg = <0x0 0x1f2cc000 0x0 0x1000>; + reg-names = "csr-reg"; + clock-output-names = "pcie1clk"; + }; + xge0clk: xge0clk@1f61c000 { compatible = "apm,xgene-device-clock"; #clock-cells = <1>; @@ -316,6 +325,56 @@ interrupts = <0x0 0x4c 0x4>; }; + pcie0: pcie@1f2b0000 { + status = "disabled"; + device_type = "pci"; + compatible = "apm,xgene-pcie", "apm,xgene2-pcie"; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + reg = < 0x00 0x1f2b0000 0x0 0x00010000 /* Controller registers */ + 0xc0 0xd0000000 0x0 0x00040000>; /* PCI config space */ + reg-names = "csr", "cfg"; + ranges = <0x01000000 0x00 0x00000000 0xc0 0x10000000 0x00 0x00010000 /* io */ + 0x02000000 0x00 0x20000000 0xc1 0x20000000 0x00 0x20000000 /* mem */ + 0x43000000 0xe0 0x00000000 0xe0 0x00000000 0x20 0x00000000>; /* mem */ + dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000 + 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 0x10 0x1 + 0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 0x11 0x1 + 0x0 0x0 0x0 0x3 &gic 0x0 0x0 0x0 0x12 0x1 + 0x0 0x0 0x0 0x4 &gic 0x0 0x0 0x0 0x13 0x1>; + dma-coherent; + clocks = <&pcie0clk 0>; + msi-parent = <&v2m0>; + }; + + pcie1: pcie@1f2c0000 { + status = "disabled"; + device_type = "pci"; + compatible = "apm,xgene-pcie", "apm,xgene2-pcie"; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + reg = < 0x00 0x1f2c0000 0x0 0x00010000 /* Controller registers */ + 0xa0 0xd0000000 0x0 0x00040000>; /* PCI config space */ + reg-names = "csr", "cfg"; + ranges = <0x01000000 0x00 0x00000000 0xa0 0x10000000 0x00 0x00010000 /* io */ + 0x02000000 0x00 0x20000000 0xa1 0x20000000 0x00 0x20000000 /* mem */ + 0x43000000 0xb0 0x00000000 0xb0 0x00000000 0x10 0x00000000>; /* mem */ + dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000 + 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 0x16 0x1 + 0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 0x17 0x1 + 0x0 0x0 0x0 0x3 &gic 0x0 0x0 0x0 0x18 0x1 + 0x0 0x0 0x0 0x4 &gic 0x0 0x0 0x0 0x19 0x1>; + dma-coherent; + clocks = <&pcie1clk 0>; + msi-parent = <&v2m0>; + }; + sata1: sata@1a000000 { compatible = "apm,xgene-ahci"; reg = <0x0 0x1a000000 0x0 0x1000>, -- cgit v1.2.3-59-g8ed1b From bd41023315285cbc46ff4738cef2a03762638921 Mon Sep 17 00:00:00 2001 From: Duc Dang Date: Wed, 14 Oct 2015 13:36:24 -0700 Subject: arm64: dts: Add USB nodes for APM X-Gene v1 platforms This patch adds USB nodes into APM X-Gene v1 device tree to enable USB support for X-Gene v1 platforms. Signed-off-by: Duc Dang --- arch/arm64/boot/dts/apm/apm-storm.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/apm/apm-storm.dtsi b/arch/arm64/boot/dts/apm/apm-storm.dtsi index 32f9ba9b6962..72680fa8a2da 100644 --- a/arch/arm64/boot/dts/apm/apm-storm.dtsi +++ b/arch/arm64/boot/dts/apm/apm-storm.dtsi @@ -799,6 +799,25 @@ phy-names = "sata-phy"; }; + /* Do not change dwusb name, coded for backward compatibility */ + usb0: dwusb@19000000 { + status = "disabled"; + compatible = "snps,dwc3"; + reg = <0x0 0x19000000 0x0 0x100000>; + interrupts = <0x0 0x89 0x4>; + dma-coherent; + dr_mode = "host"; + }; + + usb1: dwusb@19800000 { + status = "disabled"; + compatible = "snps,dwc3"; + reg = <0x0 0x19800000 0x0 0x100000>; + interrupts = <0x0 0x8a 0x4>; + dma-coherent; + dr_mode = "host"; + }; + sbgpio: sbgpio@17001000{ compatible = "apm,xgene-gpio-sb"; reg = <0x0 0x17001000 0x0 0x400>; -- cgit v1.2.3-59-g8ed1b From 30fd9d51fe34f89086eb6633ef8938aab22f0534 Mon Sep 17 00:00:00 2001 From: Duc Dang Date: Wed, 14 Oct 2015 13:44:17 -0700 Subject: arm64: dts: Add USB nodes for APM X-Gene v2 platforms This patch adds USB node into APM X-Gene v2 device tree to enable USB support for X-Gene v2 platforms. Signed-off-by: Duc Dang --- arch/arm64/boot/dts/apm/apm-shadowcat.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi b/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi index d50e19f24397..e7e6b4d96999 100644 --- a/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi +++ b/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi @@ -325,6 +325,15 @@ interrupts = <0x0 0x4c 0x4>; }; + usb0: dwusb@19000000 { + status = "disabled"; + compatible = "snps,dwc3"; + reg = <0x0 0x19000000 0x0 0x100000>; + interrupts = <0x0 0x5d 0x4>; + dma-coherent; + dr_mode = "host"; + }; + pcie0: pcie@1f2b0000 { status = "disabled"; device_type = "pci"; -- cgit v1.2.3-59-g8ed1b From 0a09223f3dae977e95f708b1de8aa5cdc017fbe3 Mon Sep 17 00:00:00 2001 From: Duc Dang Date: Wed, 14 Oct 2015 16:56:03 -0700 Subject: arm64: dts: Add APM X-Gene v1 SoC GFC GPIO controller DTS entries This patch adds the flash controller muxed gpio dts node for APM X-Gene v1 SoC platforms. Signed-off-by: Duc Dang --- arch/arm64/boot/dts/apm/apm-storm.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/apm/apm-storm.dtsi b/arch/arm64/boot/dts/apm/apm-storm.dtsi index 72680fa8a2da..5af9c1c3cd79 100644 --- a/arch/arm64/boot/dts/apm/apm-storm.dtsi +++ b/arch/arm64/boot/dts/apm/apm-storm.dtsi @@ -725,6 +725,13 @@ clocks = <&sdioclk 0>, <&ahbclk 0>; }; + gfcgpio: gfcgpio0@1701c000 { + compatible = "apm,xgene-gpio"; + reg = <0x0 0x1701c000 0x0 0x40>; + gpio-controller; + #gpio-cells = <2>; + }; + phy1: phy@1f21a000 { compatible = "apm,xgene-phy"; reg = <0x0 0x1f21a000 0x0 0x100>; -- cgit v1.2.3-59-g8ed1b From 9e81a200ea57563204e3c9f636440ad78535115a Mon Sep 17 00:00:00 2001 From: Duc Dang Date: Wed, 14 Oct 2015 17:24:29 -0700 Subject: arm64: dts: Add APM X-Gene v2 SoC GFC GPIO controller DTS entry This patch adds the flash controller muxed gpio dts node for APM X-Gene v2 SoC platforms. Signed-off-by: Duc Dang --- arch/arm64/boot/dts/apm/apm-shadowcat.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi b/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi index e7e6b4d96999..e32851efd4ec 100644 --- a/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi +++ b/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi @@ -424,6 +424,13 @@ clocks = <&sdioclk 0>, <&ahbclk 0>; }; + gfcgpio: gfcgpio@1f63c000 { + compatible = "apm,xgene-gpio"; + reg = <0x0 0x1f63c000 0x0 0x40>; + gpio-controller; + #gpio-cells = <2>; + }; + sbgpio: sbgpio@17001000{ compatible = "apm,xgene-gpio-sb"; reg = <0x0 0x17001000 0x0 0x400>; -- cgit v1.2.3-59-g8ed1b From e38ec5b9a9beb6a560f1915e749ffc92f4504ed9 Mon Sep 17 00:00:00 2001 From: Duc Dang Date: Wed, 14 Oct 2015 17:27:16 -0700 Subject: arm64: dts: Add Designware GPIO dts binding for APM X-Gene v1 platform This patch adds Designware GPIO dts binding for APM X-Gene v1 platform. Signed-off-by: Duc Dang --- arch/arm64/boot/dts/apm/apm-storm.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/apm/apm-storm.dtsi b/arch/arm64/boot/dts/apm/apm-storm.dtsi index 5af9c1c3cd79..db190a44cb1b 100644 --- a/arch/arm64/boot/dts/apm/apm-storm.dtsi +++ b/arch/arm64/boot/dts/apm/apm-storm.dtsi @@ -732,6 +732,21 @@ #gpio-cells = <2>; }; + dwgpio: dwgpio@1c024000 { + compatible = "snps,dw-apb-gpio"; + reg = <0x0 0x1c024000 0x0 0x1000>; + reg-io-width = <4>; + #address-cells = <1>; + #size-cells = <0>; + + porta: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + snps,nr-gpios = <32>; + reg = <0>; + }; + }; + phy1: phy@1f21a000 { compatible = "apm,xgene-phy"; reg = <0x0 0x1f21a000 0x0 0x100>; -- cgit v1.2.3-59-g8ed1b From 9ba6739d28a4dc9c7232fd4a819a4fb907271664 Mon Sep 17 00:00:00 2001 From: Duc Dang Date: Wed, 14 Oct 2015 17:32:42 -0700 Subject: arm64: dts: Add APM X-Gene v2 SoC Designware GPIO controller DTS entry This patch adds Designware GPIO controller DTS node for APM X-Gene v2 platforms. Signed-off-by: Duc Dang --- arch/arm64/boot/dts/apm/apm-shadowcat.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi b/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi index e32851efd4ec..29879abf5f7a 100644 --- a/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi +++ b/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi @@ -431,6 +431,21 @@ #gpio-cells = <2>; }; + dwgpio: dwgpio@1c024000 { + compatible = "snps,dw-apb-gpio"; + reg = <0x0 0x1c024000 0x0 0x1000>; + reg-io-width = <4>; + #address-cells = <1>; + #size-cells = <0>; + + porta: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + snps,nr-gpios = <32>; + reg = <0>; + }; + }; + sbgpio: sbgpio@17001000{ compatible = "apm,xgene-gpio-sb"; reg = <0x0 0x17001000 0x0 0x400>; -- cgit v1.2.3-59-g8ed1b From 1a47bc826c55c6b1375b33fd611a3e8d916c1cc2 Mon Sep 17 00:00:00 2001 From: Duc Dang Date: Thu, 15 Oct 2015 12:06:48 -0700 Subject: arm64: dts: Add APM X-Gene v2 SoC EDAC DTS entries This patch adds EDAC DTS entries for APM X-Gene v2 SoC. Signed-off-by: Duc Dang --- arch/arm64/boot/dts/apm/apm-shadowcat.dtsi | 93 ++++++++++++++++++++++++++++++ 1 file changed, 93 insertions(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi b/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi index 29879abf5f7a..c1557b1d5a6b 100644 --- a/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi +++ b/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi @@ -315,6 +315,99 @@ mask = <0x1>; }; + csw: csw@7e200000 { + compatible = "apm,xgene-csw", "syscon"; + reg = <0x0 0x7e200000 0x0 0x1000>; + }; + + mcba: mcba@7e700000 { + compatible = "apm,xgene-mcb", "syscon"; + reg = <0x0 0x7e700000 0x0 0x1000>; + }; + + mcbb: mcbb@7e720000 { + compatible = "apm,xgene-mcb", "syscon"; + reg = <0x0 0x7e720000 0x0 0x1000>; + }; + + efuse: efuse@1054a000 { + compatible = "apm,xgene-efuse", "syscon"; + reg = <0x0 0x1054a000 0x0 0x20>; + }; + + edac@78800000 { + compatible = "apm,xgene-edac"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + regmap-csw = <&csw>; + regmap-mcba = <&mcba>; + regmap-mcbb = <&mcbb>; + regmap-efuse = <&efuse>; + reg = <0x0 0x78800000 0x0 0x100>; + interrupts = <0x0 0x20 0x4>, + <0x0 0x21 0x4>, + <0x0 0x27 0x4>; + + edacmc@7e800000 { + compatible = "apm,xgene-edac-mc"; + reg = <0x0 0x7e800000 0x0 0x1000>; + memory-controller = <0>; + }; + + edacmc@7e840000 { + compatible = "apm,xgene-edac-mc"; + reg = <0x0 0x7e840000 0x0 0x1000>; + memory-controller = <1>; + }; + + edacmc@7e880000 { + compatible = "apm,xgene-edac-mc"; + reg = <0x0 0x7e880000 0x0 0x1000>; + memory-controller = <2>; + }; + + edacmc@7e8c0000 { + compatible = "apm,xgene-edac-mc"; + reg = <0x0 0x7e8c0000 0x0 0x1000>; + memory-controller = <3>; + }; + + edacpmd@7c000000 { + compatible = "apm,xgene-edac-pmd"; + reg = <0x0 0x7c000000 0x0 0x200000>; + pmd-controller = <0>; + }; + + edacpmd@7c200000 { + compatible = "apm,xgene-edac-pmd"; + reg = <0x0 0x7c200000 0x0 0x200000>; + pmd-controller = <1>; + }; + + edacpmd@7c400000 { + compatible = "apm,xgene-edac-pmd"; + reg = <0x0 0x7c400000 0x0 0x200000>; + pmd-controller = <2>; + }; + + edacpmd@7c600000 { + compatible = "apm,xgene-edac-pmd"; + reg = <0x0 0x7c600000 0x0 0x200000>; + pmd-controller = <3>; + }; + + edacl3@7e600000 { + compatible = "apm,xgene-edac-l3-v2"; + reg = <0x0 0x7e600000 0x0 0x1000>; + }; + + edacsoc@7e930000 { + compatible = "apm,xgene-edac-soc"; + reg = <0x0 0x7e930000 0x0 0x1000>; + }; + }; + serial0: serial@10600000 { device_type = "serial"; compatible = "ns16550"; -- cgit v1.2.3-59-g8ed1b From 62ff9683b5980327b2952f188e529fd67fddf94a Mon Sep 17 00:00:00 2001 From: Duc Dang Date: Fri, 16 Oct 2015 12:45:24 -0700 Subject: arm64: dts: Add Designware I2C controller DTS entries for X-Gene v1 SoC This patch adds DTS entries for Designware I2C controller used in APM X-Gene v1 SoC evaluation platform (Mustang board). APM X-Gene v1 SoC has 2 I2C controllers. On Mustang board, I2C1 is used to implement proxy I2C interface; I2C1 can be used as I2C slave port (for BMC) or as I2C master port (if no BMC is used). Only I2C1 DT entry is added in this patch with default status as 'disabled'. Signed-off-by: Duc Dang --- arch/arm64/boot/dts/apm/apm-storm.dtsi | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/apm/apm-storm.dtsi b/arch/arm64/boot/dts/apm/apm-storm.dtsi index db190a44cb1b..6297b7cdbe80 100644 --- a/arch/arm64/boot/dts/apm/apm-storm.dtsi +++ b/arch/arm64/boot/dts/apm/apm-storm.dtsi @@ -417,6 +417,20 @@ reg-names = "csr-reg"; clock-output-names = "dmaclk"; }; + + i2cclk: i2cclk@17000000 { + status = "disabled"; + compatible = "apm,xgene-device-clock"; + #clock-cells = <1>; + clocks = <&ahbclk 0>; + reg = <0x0 0x17000000 0x0 0x2000>; + reg-names = "csr-reg"; + csr-offset = <0xc>; + csr-mask = <0x4>; + enable-offset = <0x10>; + enable-mask = <0x4>; + clock-output-names = "i2cclk"; + }; }; msi: msi@79000000 { @@ -747,6 +761,18 @@ }; }; + i2c0: i2c0@10512000 { + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0x0 0x10512000 0x0 0x1000>; + interrupts = <0 0x44 0x4>; + #clock-cells = <1>; + clocks = <&i2cclk 0>; + bus_num = <0>; + }; + phy1: phy@1f21a000 { compatible = "apm,xgene-phy"; reg = <0x0 0x1f21a000 0x0 0x100>; -- cgit v1.2.3-59-g8ed1b From d0181354dfd13a01c67afd64264f4fa1c18dc86a Mon Sep 17 00:00:00 2001 From: Duc Dang Date: Wed, 21 Oct 2015 19:07:28 -0700 Subject: arm64: dts: Add Designware I2C controller DTS entries for X-Gene v2 SoC platform This patch adds DTS entries for Designware I2C controllers used in APM X-Gene v2 evaluation platform (Merlin board). X-Gene v2 has total 5 I2C controllers. On Merlin board only I2C1 and I2C4 controllers are available in Linux, where the other 3 controllers are used for management purpose (power management, BMC function). Signed-off-by: Duc Dang --- arch/arm64/boot/dts/apm/apm-shadowcat.dtsi | 59 ++++++++++++++++++++++++++++++ 1 file changed, 59 insertions(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi b/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi index c1557b1d5a6b..ec0e9610b0b8 100644 --- a/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi +++ b/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi @@ -232,6 +232,18 @@ clock-output-names = "ahbclk"; }; + sbapbclk: sbapbclk@1704c000 { + compatible = "apm,xgene-device-clock"; + #clock-cells = <1>; + clocks = <&ahbclk 0>; + reg = <0x0 0x1704c000 0x0 0x2000>; + reg-names = "div-reg"; + divider-offset = <0x10>; + divider-width = <0x2>; + divider-shift = <0x0>; + clock-output-names = "sbapbclk"; + }; + sdioclk: sdioclk@1f2ac000 { compatible = "apm,xgene-device-clock"; #clock-cells = <1>; @@ -301,6 +313,32 @@ enable-mask = <0x10>; clock-output-names = "rngpkaclk"; }; + + i2c1clk: i2c1clk@17000000 { + compatible = "apm,xgene-device-clock"; + #clock-cells = <1>; + clocks = <&sbapbclk 0>; + reg = <0x0 0x17000000 0x0 0x2000>; + reg-names = "csr-reg"; + csr-offset = <0xc>; + csr-mask = <0x4>; + enable-offset = <0x10>; + enable-mask = <0x4>; + clock-output-names = "i2c1clk"; + }; + + i2c4clk: i2c4clk@1704c000 { + compatible = "apm,xgene-device-clock"; + #clock-cells = <1>; + clocks = <&sbapbclk 0>; + reg = <0x0 0x1704c000 0x0 0x1000>; + reg-names = "csr-reg"; + csr-offset = <0x0>; + csr-mask = <0x40>; + enable-offset = <0x8>; + enable-mask = <0x40>; + clock-output-names = "i2c4clk"; + }; }; scu: system-clk-controller@17000000 { @@ -589,5 +627,26 @@ interrupts = <0x0 0x41 0x4>; clocks = <&rngpkaclk 0>; }; + + i2c1: i2c1@10511000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0x0 0x10511000 0x0 0x1000>; + interrupts = <0 0x45 0x4>; + #clock-cells = <1>; + clocks = <&i2c1clk 0>; + bus_num = <1>; + }; + + i2c4: i2c4@10640000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0x0 0x10640000 0x0 0x1000>; + interrupts = <0 0x3A 0x4>; + clocks = <&i2c4clk 0>; + bus_num = <4>; + }; }; }; -- cgit v1.2.3-59-g8ed1b From 79402f35f00f3043ae91dd6470f7734263cdde85 Mon Sep 17 00:00:00 2001 From: Duc Dang Date: Wed, 21 Oct 2015 19:17:42 -0700 Subject: arm64: dts: Add RTC DTS entry for X-Gene v2 SoC platform Add Dallas DS1337 RTC DTS entry to support RTC function on X-Gene v2 evaluation platform. Signed-off-by: Duc Dang --- arch/arm64/boot/dts/apm/apm-merlin.dts | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/apm/apm-merlin.dts b/arch/arm64/boot/dts/apm/apm-merlin.dts index a0092f977591..e5ba8d5d0cae 100644 --- a/arch/arm64/boot/dts/apm/apm-merlin.dts +++ b/arch/arm64/boot/dts/apm/apm-merlin.dts @@ -74,3 +74,11 @@ &mmc0 { status = "ok"; }; + +&i2c4 { + rtc68: rtc@68 { + compatible = "dallas,ds1337"; + reg = <0x68>; + status = "ok"; + }; +}; -- cgit v1.2.3-59-g8ed1b From 8000bc3fe99a304e244edfaf185b418b22e5579c Mon Sep 17 00:00:00 2001 From: Duc Dang Date: Mon, 26 Oct 2015 02:31:43 -0700 Subject: arm64: dts: Add L2 cache topology for APM X-Gene SoC In APM X-Gene SoC (both v1 and v2), each pair of processors shares the same L2 cache. This patch adds l2-cache entries into X-Gene SoC device tree to demonstrate this configuration. Signed-off-by: Duc Dang --- arch/arm64/boot/dts/apm/apm-shadowcat.dtsi | 20 ++++++++++++++++++++ arch/arm64/boot/dts/apm/apm-storm.dtsi | 20 ++++++++++++++++++++ 2 files changed, 40 insertions(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi b/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi index ec0e9610b0b8..c617aa4972ab 100644 --- a/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi +++ b/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi @@ -25,6 +25,7 @@ reg = <0x0 0x000>; enable-method = "spin-table"; cpu-release-addr = <0x1 0x0000fff8>; + next-level-cache = <&xgene_L2_0>; }; cpu@001 { device_type = "cpu"; @@ -32,6 +33,7 @@ reg = <0x0 0x001>; enable-method = "spin-table"; cpu-release-addr = <0x1 0x0000fff8>; + next-level-cache = <&xgene_L2_0>; }; cpu@100 { device_type = "cpu"; @@ -39,6 +41,7 @@ reg = <0x0 0x100>; enable-method = "spin-table"; cpu-release-addr = <0x1 0x0000fff8>; + next-level-cache = <&xgene_L2_1>; }; cpu@101 { device_type = "cpu"; @@ -46,6 +49,7 @@ reg = <0x0 0x101>; enable-method = "spin-table"; cpu-release-addr = <0x1 0x0000fff8>; + next-level-cache = <&xgene_L2_1>; }; cpu@200 { device_type = "cpu"; @@ -53,6 +57,7 @@ reg = <0x0 0x200>; enable-method = "spin-table"; cpu-release-addr = <0x1 0x0000fff8>; + next-level-cache = <&xgene_L2_2>; }; cpu@201 { device_type = "cpu"; @@ -60,6 +65,7 @@ reg = <0x0 0x201>; enable-method = "spin-table"; cpu-release-addr = <0x1 0x0000fff8>; + next-level-cache = <&xgene_L2_2>; }; cpu@300 { device_type = "cpu"; @@ -67,6 +73,7 @@ reg = <0x0 0x300>; enable-method = "spin-table"; cpu-release-addr = <0x1 0x0000fff8>; + next-level-cache = <&xgene_L2_3>; }; cpu@301 { device_type = "cpu"; @@ -74,6 +81,19 @@ reg = <0x0 0x301>; enable-method = "spin-table"; cpu-release-addr = <0x1 0x0000fff8>; + next-level-cache = <&xgene_L2_3>; + }; + xgene_L2_0: l2-cache-0 { + compatible = "cache"; + }; + xgene_L2_1: l2-cache-1 { + compatible = "cache"; + }; + xgene_L2_2: l2-cache-2 { + compatible = "cache"; + }; + xgene_L2_3: l2-cache-3 { + compatible = "cache"; }; }; diff --git a/arch/arm64/boot/dts/apm/apm-storm.dtsi b/arch/arm64/boot/dts/apm/apm-storm.dtsi index 6297b7cdbe80..a21e08a88991 100644 --- a/arch/arm64/boot/dts/apm/apm-storm.dtsi +++ b/arch/arm64/boot/dts/apm/apm-storm.dtsi @@ -25,6 +25,7 @@ reg = <0x0 0x000>; enable-method = "spin-table"; cpu-release-addr = <0x1 0x0000fff8>; + next-level-cache = <&xgene_L2_0>; }; cpu@001 { device_type = "cpu"; @@ -32,6 +33,7 @@ reg = <0x0 0x001>; enable-method = "spin-table"; cpu-release-addr = <0x1 0x0000fff8>; + next-level-cache = <&xgene_L2_0>; }; cpu@100 { device_type = "cpu"; @@ -39,6 +41,7 @@ reg = <0x0 0x100>; enable-method = "spin-table"; cpu-release-addr = <0x1 0x0000fff8>; + next-level-cache = <&xgene_L2_1>; }; cpu@101 { device_type = "cpu"; @@ -46,6 +49,7 @@ reg = <0x0 0x101>; enable-method = "spin-table"; cpu-release-addr = <0x1 0x0000fff8>; + next-level-cache = <&xgene_L2_1>; }; cpu@200 { device_type = "cpu"; @@ -53,6 +57,7 @@ reg = <0x0 0x200>; enable-method = "spin-table"; cpu-release-addr = <0x1 0x0000fff8>; + next-level-cache = <&xgene_L2_2>; }; cpu@201 { device_type = "cpu"; @@ -60,6 +65,7 @@ reg = <0x0 0x201>; enable-method = "spin-table"; cpu-release-addr = <0x1 0x0000fff8>; + next-level-cache = <&xgene_L2_2>; }; cpu@300 { device_type = "cpu"; @@ -67,6 +73,7 @@ reg = <0x0 0x300>; enable-method = "spin-table"; cpu-release-addr = <0x1 0x0000fff8>; + next-level-cache = <&xgene_L2_3>; }; cpu@301 { device_type = "cpu"; @@ -74,6 +81,19 @@ reg = <0x0 0x301>; enable-method = "spin-table"; cpu-release-addr = <0x1 0x0000fff8>; + next-level-cache = <&xgene_L2_3>; + }; + xgene_L2_0: l2-cache-0 { + compatible = "cache"; + }; + xgene_L2_1: l2-cache-1 { + compatible = "cache"; + }; + xgene_L2_2: l2-cache-2 { + compatible = "cache"; + }; + xgene_L2_3: l2-cache-3 { + compatible = "cache"; }; }; -- cgit v1.2.3-59-g8ed1b From 9589f7721e16007ae040b55993dccfed00ddb296 Mon Sep 17 00:00:00 2001 From: Alim Akhtar Date: Fri, 6 Nov 2015 08:36:39 +0530 Subject: arm64: dts: Add S2MPS15 PMIC node on exynos7-espresso This patch adds PMIC (S2MPS15) node on Espresso board, which includes regulators and pmic-clk sub-nodes. This patch also adds {vmmc,vqmmc}-supply properties for mmc2 node. Signed-off-by: Abhilash Kesavan Signed-off-by: Alim Akhtar Reviewed-by: Javier Martinez Canillas Reviewed-by: Krzysztof Kozlowski Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/exynos/exynos7-espresso.dts | 280 ++++++++++++++++++++++++ 1 file changed, 280 insertions(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/exynos/exynos7-espresso.dts b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts index 5424cc450f72..f5a3da50ac57 100644 --- a/arch/arm64/boot/dts/exynos/exynos7-espresso.dts +++ b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts @@ -11,6 +11,7 @@ /dts-v1/; #include "exynos7.dtsi" +#include / { model = "Samsung Exynos7 Espresso board based on EXYNOS7"; @@ -52,6 +53,283 @@ status = "okay"; }; +&hsi2c_4 { + samsung,i2c-sda-delay = <100>; + samsung,i2c-max-bus-freq = <200000>; + status = "okay"; + + s2mps15_pmic@66 { + compatible = "samsung,s2mps15-pmic"; + reg = <0x66>; + interrupts = <2 IRQ_TYPE_NONE>; + interrupt-parent = <&gpa0>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_irq>; + wakeup-source; + + s2mps15_osc: clocks { + compatible = "samsung,s2mps13-clk"; + #clock-cells = <1>; + clock-output-names = "s2mps13_ap", "s2mps13_cp", + "s2mps13_bt"; + }; + + regulators { + ldo1_reg: LDO1 { + regulator-name = "vdd_ldo1"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <900000>; + regulator-always-on; + regulator-enable-ramp-delay = <125>; + }; + + ldo2_reg: LDO2 { + regulator-name = "vqmmc-sdcard"; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-enable-ramp-delay = <125>; + }; + + ldo3_reg: LDO3 { + regulator-name = "vdd_ldo3"; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <1980000>; + regulator-always-on; + regulator-boot-on; + regulator-enable-ramp-delay = <125>; + }; + + ldo4_reg: LDO4 { + regulator-name = "vdd_ldo4"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1110000>; + regulator-always-on; + regulator-enable-ramp-delay = <125>; + }; + + ldo5_reg: LDO5 { + regulator-name = "vdd_ldo5"; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <1980000>; + regulator-always-on; + regulator-enable-ramp-delay = <125>; + }; + + ldo6_reg: LDO6 { + regulator-name = "vdd_ldo6"; + regulator-min-microvolt = <2250000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <125>; + }; + + ldo7_reg: LDO7 { + regulator-name = "vdd_ldo7"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1150000>; + regulator-enable-ramp-delay = <125>; + }; + + ldo8_reg: LDO8 { + regulator-name = "vdd_ldo8"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1000000>; + regulator-enable-ramp-delay = <125>; + }; + + ldo9_reg: LDO9 { + regulator-name = "vdd_ldo9"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1000000>; + regulator-enable-ramp-delay = <125>; + }; + + ldo10_reg: LDO10 { + regulator-name = "vdd_ldo10"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1000000>; + regulator-enable-ramp-delay = <125>; + }; + + ldo11_reg: LDO11 { + regulator-name = "vdd_ldo11"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + regulator-enable-ramp-delay = <125>; + }; + + ldo12_reg: LDO12 { + regulator-name = "vdd_ldo12"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1300000>; + regulator-enable-ramp-delay = <125>; + }; + + ldo13_reg: LDO13 { + regulator-name = "vdd_ldo13"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + regulator-enable-ramp-delay = <125>; + }; + + ldo14_reg: LDO14 { + regulator-name = "vdd_ldo14"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3375000>; + regulator-enable-ramp-delay = <125>; + }; + + ldo17_reg: LDO17 { + regulator-name = "vmmc-sdcard"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3375000>; + regulator-enable-ramp-delay = <125>; + }; + + ldo18_reg: LDO18 { + regulator-name = "vdd_ldo18"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <2275000>; + regulator-enable-ramp-delay = <125>; + }; + + ldo19_reg: LDO19 { + regulator-name = "vdd_ldo19"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3375000>; + regulator-enable-ramp-delay = <125>; + }; + + ldo21_reg: LDO21 { + regulator-name = "vdd_ldo21"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3375000>; + regulator-enable-ramp-delay = <125>; + }; + + ldo23_reg: LDO23 { + regulator-name = "vdd_ldo23"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <2275000>; + regulator-enable-ramp-delay = <125>; + }; + + ldo25_reg: LDO25 { + regulator-name = "vdd_ldo25"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3375000>; + regulator-enable-ramp-delay = <125>; + }; + + ldo26_reg: LDO26 { + regulator-name = "vdd_ldo26"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1470000>; + regulator-enable-ramp-delay = <125>; + }; + + ldo27_reg: LDO27 { + regulator-name = "vdd_ldo27"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <2275000>; + regulator-enable-ramp-delay = <125>; + }; + + buck1_reg: BUCK1 { + regulator-name = "vdd_mif"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + regulator-ramp-delay = <25000>; + regulator-enable-ramp-delay = <250>; + }; + + buck2_reg: BUCK2 { + regulator-name = "vdd_atlas"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + regulator-ramp-delay = <12500>; + regulator-enable-ramp-delay = <250>; + }; + + buck4_reg: BUCK4 { + regulator-name = "vdd_int"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + regulator-ramp-delay = <12500>; + regulator-enable-ramp-delay = <250>; + }; + + buck5_reg: BUCK5 { + regulator-name = "vdd_buck5"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1300000>; + regulator-ramp-delay = <25000>; + regulator-enable-ramp-delay = <250>; + }; + + buck6_reg: BUCK6 { + regulator-name = "vdd_g3d"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1400000>; + regulator-ramp-delay = <12500>; + regulator-enable-ramp-delay = <250>; + }; + + buck7_reg: BUCK7 { + regulator-name = "vdd_buck7"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-ramp-delay = <25000>; + regulator-enable-ramp-delay = <250>; + }; + + buck8_reg: BUCK8 { + regulator-name = "vdd_buck8"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-ramp-delay = <25000>; + regulator-enable-ramp-delay = <250>; + }; + + buck9_reg: BUCK9 { + regulator-name = "vdd_buck9"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2100000>; + regulator-always-on; + regulator-ramp-delay = <25000>; + regulator-enable-ramp-delay = <250>; + }; + + buck10_reg: BUCK10 { + regulator-name = "vdd_buck10"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + regulator-ramp-delay = <25000>; + regulator-enable-ramp-delay = <250>; + }; + }; + }; +}; + +&pinctrl_alive { + pmic_irq: pmic-irq { + samsung,pins = "gpa0-2"; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; +}; + &mmc_0 { status = "okay"; num-slots = <1>; @@ -80,5 +358,7 @@ pinctrl-names = "default"; pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>; bus-width = <4>; + vmmc-supply = <&ldo17_reg>; + vqmmc-supply = <&ldo2_reg>; disable-wp; }; -- cgit v1.2.3-59-g8ed1b From 4fe5dc4873663fc4cfbdae7a45a1b4378a2d7993 Mon Sep 17 00:00:00 2001 From: Alim Akhtar Date: Fri, 6 Nov 2015 08:36:40 +0530 Subject: arm64: dts: Enable HS200 mode operation on exynos7-espresso This patch enables HS200 mode operation on Exynos7 based Espresso board. This also removes _broken-cd_ property as per mmc binding documentation which says one of the properties between broken-cd and non-removable should be used. And we already use _non-removable_ as emmc is mounted on the board which is a non-removable device. Signed-off-by: Alim Akhtar Reviewed-by: Javier Martinez Canillas Reviewed-by: Krzysztof Kozlowski Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/exynos/exynos7-espresso.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/exynos/exynos7-espresso.dts b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts index f5a3da50ac57..d8767b00862e 100644 --- a/arch/arm64/boot/dts/exynos/exynos7-espresso.dts +++ b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts @@ -333,8 +333,8 @@ &mmc_0 { status = "okay"; num-slots = <1>; - broken-cd; cap-mmc-highspeed; + mmc-hs200-1_8v; non-removable; card-detect-delay = <200>; clock-frequency = <800000000>; -- cgit v1.2.3-59-g8ed1b From fb026cb6524744c8bd0f133f4b0d8e2595d04e15 Mon Sep 17 00:00:00 2001 From: Alim Akhtar Date: Mon, 19 Oct 2015 15:28:03 +0530 Subject: arm64: dts: Add reboot node for exynos7 This patch add syscon-reboot node to reboot exynos7 based SoCs. Signed-off-by: Alim Akhtar Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/exynos/exynos7.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi b/arch/arm64/boot/dts/exynos/exynos7.dtsi index f9c5a549c2c0..93108f1a90f9 100644 --- a/arch/arm64/boot/dts/exynos/exynos7.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi @@ -454,6 +454,13 @@ reg = <0x105c0000 0x5000>; }; + reboot: syscon-reboot { + compatible = "syscon-reboot"; + regmap = <&pmu_system_controller>; + offset = <0x0400>; + mask = <0x1>; + }; + rtc: rtc@10590000 { compatible = "samsung,s3c6410-rtc"; reg = <0x10590000 0x100>; -- cgit v1.2.3-59-g8ed1b From ff08868ef0154cef01d3a50ae1f19dc968fc95f3 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Sat, 7 Nov 2015 22:39:26 +0100 Subject: arm64: dts: rockchip: Setup rk3368 ethernet0 alias for u-boot Add an ethernet0 alias for the RK3368 mac interface so that u-boot can find the device-node and fill in the mac address on boards that support a wired network interface. Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3368.dtsi | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/rockchip/rk3368.dtsi b/arch/arm64/boot/dts/rockchip/rk3368.dtsi index cc093a482aa4..1f10b85b64ab 100644 --- a/arch/arm64/boot/dts/rockchip/rk3368.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3368.dtsi @@ -53,6 +53,7 @@ #size-cells = <2>; aliases { + ethernet0 = &gmac; i2c0 = &i2c0; i2c1 = &i2c1; i2c2 = &i2c2; -- cgit v1.2.3-59-g8ed1b From cb27c89b7817935c0a532b39e6a77dd2e2fc3e56 Mon Sep 17 00:00:00 2001 From: Jisheng Zhang Date: Fri, 16 Oct 2015 15:37:11 +0800 Subject: arm64: dts: berlin4ct: add the pinctrl node Add the avio, soc, sm pinctrl nodes for Marvell berlin4ct SoC. Signed-off-by: Jisheng Zhang Acked-by: Sebastian Hesselbarth Acked-by: Antoine Tenart Acked-by: Linus Walleij Signed-off-by: Sebastian Hesselbarth --- arch/arm64/boot/dts/marvell/berlin4ct.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/marvell/berlin4ct.dtsi b/arch/arm64/boot/dts/marvell/berlin4ct.dtsi index a3b5f1d4a240..8e66355c8306 100644 --- a/arch/arm64/boot/dts/marvell/berlin4ct.dtsi +++ b/arch/arm64/boot/dts/marvell/berlin4ct.dtsi @@ -225,6 +225,16 @@ }; }; + soc_pinctrl: pin-controller@ea8000 { + compatible = "marvell,berlin4ct-soc-pinctrl"; + reg = <0xea8000 0x14>; + }; + + avio_pinctrl: pin-controller@ea8400 { + compatible = "marvell,berlin4ct-avio-pinctrl"; + reg = <0xea8400 0x8>; + }; + apb@fc0000 { compatible = "simple-bus"; #address-cells = <1>; @@ -280,5 +290,10 @@ status = "disabled"; }; }; + + system_pinctrl: pin-controller@fe2200 { + compatible = "marvell,berlin4ct-system-pinctrl"; + reg = <0xfe2200 0xc>; + }; }; }; -- cgit v1.2.3-59-g8ed1b From d9c1567f8427519b5b61cbca5477f96a1590d51b Mon Sep 17 00:00:00 2001 From: Jisheng Zhang Date: Fri, 16 Oct 2015 15:37:12 +0800 Subject: arm64: dts: berlin4ct: add default pinmux for uart0 Add urt0 txd and rxd muxing setup in the dtsi because uart0 always uses them to work, no other possibilities. Signed-off-by: Jisheng Zhang Acked-by: Sebastian Hesselbarth Acked-by: Antoine Tenart Acked-by: Linus Walleij Signed-off-by: Sebastian Hesselbarth --- arch/arm64/boot/dts/marvell/berlin4ct.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/marvell/berlin4ct.dtsi b/arch/arm64/boot/dts/marvell/berlin4ct.dtsi index 8e66355c8306..a4a18764ae98 100644 --- a/arch/arm64/boot/dts/marvell/berlin4ct.dtsi +++ b/arch/arm64/boot/dts/marvell/berlin4ct.dtsi @@ -288,12 +288,19 @@ clocks = <&osc>; reg-shift = <2>; status = "disabled"; + pinctrl-0 = <&uart0_pmux>; + pinctrl-names = "default"; }; }; system_pinctrl: pin-controller@fe2200 { compatible = "marvell,berlin4ct-system-pinctrl"; reg = <0xfe2200 0xc>; + + uart0_pmux: uart0-pmux { + groups = "SM_URT0_TXD", "SM_URT0_RXD"; + function = "uart0"; + }; }; }; }; -- cgit v1.2.3-59-g8ed1b From 7b08623add8205b18e56c5b4549e83657756aec3 Mon Sep 17 00:00:00 2001 From: Takeshi Kihara Date: Thu, 29 Oct 2015 08:09:18 +0900 Subject: arm64: dts: r8a7795: add GPIO nodes Signed-off-by: Takeshi Kihara Signed-off-by: Ulrich Hecht Signed-off-by: Simon Horman Acked-by: by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a7795.dtsi | 112 +++++++++++++++++++++++++++++++ 1 file changed, 112 insertions(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi index e26eecf1230f..44967a8f00ac 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi @@ -60,6 +60,118 @@ (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>; }; + gpio0: gpio@e6050000 { + compatible = "renesas,gpio-r8a7795", + "renesas,gpio-rcar"; + reg = <0 0xe6050000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 0 16>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 912>; + power-domains = <&cpg>; + }; + + gpio1: gpio@e6051000 { + compatible = "renesas,gpio-r8a7795", + "renesas,gpio-rcar"; + reg = <0 0xe6051000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 32 28>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 911>; + power-domains = <&cpg>; + }; + + gpio2: gpio@e6052000 { + compatible = "renesas,gpio-r8a7795", + "renesas,gpio-rcar"; + reg = <0 0xe6052000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 64 15>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 910>; + power-domains = <&cpg>; + }; + + gpio3: gpio@e6053000 { + compatible = "renesas,gpio-r8a7795", + "renesas,gpio-rcar"; + reg = <0 0xe6053000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 96 16>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 909>; + power-domains = <&cpg>; + }; + + gpio4: gpio@e6054000 { + compatible = "renesas,gpio-r8a7795", + "renesas,gpio-rcar"; + reg = <0 0xe6054000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 128 18>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 908>; + power-domains = <&cpg>; + }; + + gpio5: gpio@e6055000 { + compatible = "renesas,gpio-r8a7795", + "renesas,gpio-rcar"; + reg = <0 0xe6055000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 160 26>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 907>; + power-domains = <&cpg>; + }; + + gpio6: gpio@e6055400 { + compatible = "renesas,gpio-r8a7795", + "renesas,gpio-rcar"; + reg = <0 0xe6055400 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 192 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 906>; + power-domains = <&cpg>; + }; + + gpio7: gpio@e6055800 { + compatible = "renesas,gpio-r8a7795", + "renesas,gpio-rcar"; + reg = <0 0xe6055800 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 224 4>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 905>; + power-domains = <&cpg>; + }; + timer { compatible = "arm,armv8-timer"; interrupts = Date: Fri, 2 Oct 2015 23:05:19 +0800 Subject: arm64: dts: mt8173: add timer node Add device node to enable GPT timer. Signed-off-by: Daniel Kurtz Signed-off-by: Eddie Huang Signed-off-by: Yingjoe Chen Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8173.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi index 4dd5f93d0303..d301ce5c9da9 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi @@ -247,6 +247,15 @@ reg = <0 0x10007000 0 0x100>; }; + timer: timer@10008000 { + compatible = "mediatek,mt8173-timer", + "mediatek,mt6577-timer"; + reg = <0 0x10008000 0 0x1000>; + interrupts = ; + clocks = <&infracfg CLK_INFRA_CLK_13M>, + <&topckgen CLK_TOP_RTC_SEL>; + }; + pwrap: pwrap@1000d000 { compatible = "mediatek,mt8173-pwrap"; reg = <0 0x1000d000 0 0x1000>; -- cgit v1.2.3-59-g8ed1b From 61aee93425149e2288c4ab1466847093af678de6 Mon Sep 17 00:00:00 2001 From: YH Huang Date: Tue, 6 Oct 2015 15:40:43 +0800 Subject: arm64: dts: mt8173: add MT8173 display PWM driver support node Add display PWM node in mt8173-evb.dts and mt8173.dtsi. Signed-off-by: YH Huang Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8173-evb.dts | 13 +++++++++++++ arch/arm64/boot/dts/mediatek/mt8173.dtsi | 22 ++++++++++++++++++++++ 2 files changed, 35 insertions(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/mediatek/mt8173-evb.dts b/arch/arm64/boot/dts/mediatek/mt8173-evb.dts index 811cb760ba49..1b3fabd10307 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173-evb.dts +++ b/arch/arm64/boot/dts/mediatek/mt8173-evb.dts @@ -92,6 +92,13 @@ }; &pio { + disp_pwm0_pins: disp_pwm0_pins { + pins1 { + pinmux = ; + output-low; + }; + }; + mmc0_pins_default: mmc0default { pins_cmd_dat { pinmux = , @@ -190,6 +197,12 @@ }; }; +&pwm0 { + pinctrl-names = "default"; + pinctrl-0 = <&disp_pwm0_pins>; + status = "okay"; +}; + &pwrap { pmic: mt6397 { compatible = "mediatek,mt6397"; diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi index d301ce5c9da9..ed0047a3b687 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi @@ -525,6 +525,28 @@ #clock-cells = <1>; }; + pwm0: pwm@1401e000 { + compatible = "mediatek,mt8173-disp-pwm", + "mediatek,mt6595-disp-pwm"; + reg = <0 0x1401e000 0 0x1000>; + #pwm-cells = <2>; + clocks = <&mmsys CLK_MM_DISP_PWM026M>, + <&mmsys CLK_MM_DISP_PWM0MM>; + clock-names = "main", "mm"; + status = "disabled"; + }; + + pwm1: pwm@1401f000 { + compatible = "mediatek,mt8173-disp-pwm", + "mediatek,mt6595-disp-pwm"; + reg = <0 0x1401f000 0 0x1000>; + #pwm-cells = <2>; + clocks = <&mmsys CLK_MM_DISP_PWM126M>, + <&mmsys CLK_MM_DISP_PWM1MM>; + clock-names = "main", "mm"; + status = "disabled"; + }; + imgsys: clock-controller@15000000 { compatible = "mediatek,mt8173-imgsys", "syscon"; reg = <0 0x15000000 0 0x1000>; -- cgit v1.2.3-59-g8ed1b From 05bdabe7ebc780e3cd9275f0f5795d337fa5acca Mon Sep 17 00:00:00 2001 From: Fan Chen Date: Fri, 28 Aug 2015 10:11:59 +0800 Subject: arm64: dts: mediatek: mt8173 PSCI-1.0 support This patch adds psci comatible properties to support all mandatory functions of PSCI-1.0, PSCI-0.2 and PSCI-0.1, and system suspend can be supported in PSCI-1.0. Signed-off-by: Fan Chen Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8173.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi index ed0047a3b687..b83f06b00718 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi @@ -95,7 +95,7 @@ }; psci { - compatible = "arm,psci"; + compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci"; method = "smc"; cpu_suspend = <0x84000001>; cpu_off = <0x84000002>; -- cgit v1.2.3-59-g8ed1b From a92843c8a6f8c039ff671a27e137f39c0846797c Mon Sep 17 00:00:00 2001 From: Kazuya Mizuguchi Date: Mon, 2 Nov 2015 13:31:44 +0900 Subject: arm64: dts: r8a7795: add EthernetAVB device node Signed-off-by: Kazuya Mizuguchi Signed-off-by: Simon Horman Acked-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a7795.dtsi | 42 ++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi index 44967a8f00ac..2b22cbfb13f3 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi @@ -210,6 +210,48 @@ /* Empty node for now */ }; + avb: ethernet@e6800000 { + compatible = "renesas,etheravb-r8a7795"; + reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15", + "ch16", "ch17", "ch18", "ch19", + "ch20", "ch21", "ch22", "ch23", + "ch24"; + clocks = <&cpg CPG_MOD 812>; + power-domains = <&cpg>; + phy-mode = "rgmii-id"; + #address-cells = <1>; + #size-cells = <0>; + }; + scif0: serial@e6e60000 { compatible = "renesas,scif-r8a7795", "renesas,scif"; reg = <0 0xe6e60000 0 64>; -- cgit v1.2.3-59-g8ed1b From 6fa501c549aa170b790bf68da6ffed8fe1efdaee Mon Sep 17 00:00:00 2001 From: Kazuya Mizuguchi Date: Mon, 2 Nov 2015 13:31:45 +0900 Subject: arm64: dts: r8a7795: enable EthernetAVB on Salvator-X Signed-off-by: Kazuya Mizuguchi Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts | 31 ++++++++++++++++++++++ 1 file changed, 31 insertions(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts index a3db98384e53..afdf53874da1 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts +++ b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts @@ -45,6 +45,11 @@ renesas,groups = "scif2_data_a"; renesas,function = "scif2"; }; + + avb_pins: avb { + renesas,groups = "avb_mdc"; + renesas,function = "avb"; + }; }; &scif1 { @@ -60,3 +65,29 @@ status = "okay"; }; + +&avb { + pinctrl-0 = <&avb_pins>; + pinctrl-names = "default"; + renesas,no-ether-link; + phy-handle = <&phy0>; + status = "okay"; + + phy0: ethernet-phy@0 { + rxc-skew-ps = <900>; + rxdv-skew-ps = <0>; + rxd0-skew-ps = <0>; + rxd1-skew-ps = <0>; + rxd2-skew-ps = <0>; + rxd3-skew-ps = <0>; + txc-skew-ps = <900>; + txen-skew-ps = <0>; + txd0-skew-ps = <0>; + txd1-skew-ps = <0>; + txd2-skew-ps = <0>; + txd3-skew-ps = <0>; + reg = <0>; + interrupt-parent = <&gpio2>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + }; +}; -- cgit v1.2.3-59-g8ed1b From b2407c566ba29215aaf0d2983908d49ccb9e5c87 Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Mon, 2 Nov 2015 13:31:46 +0900 Subject: arm64: dts: r8a7795: enable nfs root on Salvator-X board As has been the practice for boards for 32bit ARM Renesas SoCs Signed-off-by: Simon Horman Acked-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts index afdf53874da1..548f93f983a2 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts +++ b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts @@ -21,7 +21,7 @@ }; chosen { - bootargs = "ignore_loglevel"; + bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp"; stdout-path = "serial0:115200n8"; }; -- cgit v1.2.3-59-g8ed1b From 10ca6db79ab07021e74aad99631a276b954a554e Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 2 Nov 2015 13:31:48 +0900 Subject: arm64: renesas: salvator-x: Setup ethernet0 alias for U-Boot Add an ethernet0 alias for the wired network card so that U-Boot can find the device-node and add an appropriate "local-mac-address" property. Signed-off-by: Geert Uytterhoeven Acked-by: Laurent Pinchart Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts index 548f93f983a2..35ebb063bff6 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts +++ b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts @@ -18,6 +18,7 @@ aliases { serial0 = &scif2; serial1 = &scif1; + ethernet0 = &avb; }; chosen { -- cgit v1.2.3-59-g8ed1b From 32bc0c51be7c9db3762cbb34af465676c769886b Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Wed, 28 Oct 2015 08:05:27 +0900 Subject: arm64: renesas: r8a7795: add I2C support Signed-off-by: Kuninori Morimoto [geert: aAdd clock-output-names properties] Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman Acked-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a7795.dtsi | 87 ++++++++++++++++++++++++++++++++ 1 file changed, 87 insertions(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi index 2b22cbfb13f3..c01a7e4f59a4 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi @@ -16,6 +16,16 @@ #address-cells = <2>; #size-cells = <2>; + aliases { + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c5; + i2c6 = &i2c6; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -323,5 +333,82 @@ power-domains = <&cpg>; status = "disabled"; }; + + i2c0: i2c@e6500000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7795"; + reg = <0 0xe6500000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 931>; + power-domains = <&cpg>; + status = "disabled"; + }; + + i2c1: i2c@e6508000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7795"; + reg = <0 0xe6508000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 930>; + power-domains = <&cpg>; + status = "disabled"; + }; + + i2c2: i2c@e6510000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7795"; + reg = <0 0xe6510000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 929>; + power-domains = <&cpg>; + status = "disabled"; + }; + + i2c3: i2c@e66d0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7795"; + reg = <0 0xe66d0000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 928>; + power-domains = <&cpg>; + status = "disabled"; + }; + + i2c4: i2c@e66d8000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7795"; + reg = <0 0xe66d8000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 927>; + power-domains = <&cpg>; + status = "disabled"; + }; + + i2c5: i2c@e66e0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7795"; + reg = <0 0xe66e0000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 919>; + power-domains = <&cpg>; + status = "disabled"; + }; + + i2c6: i2c@e66e8000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7795"; + reg = <0 0xe66e8000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 918>; + power-domains = <&cpg>; + status = "disabled"; + }; }; }; -- cgit v1.2.3-59-g8ed1b From 637d801e0bb802dc18520ed6b7377acb2a9732ee Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Wed, 28 Oct 2015 08:05:28 +0900 Subject: arm64: renesas: salvator-x: enable I2C Signed-off-by: Kuninori Morimoto Signed-off-by: Simon Horman Acked-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts index 35ebb063bff6..d829fdae3c56 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts +++ b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts @@ -47,6 +47,11 @@ renesas,function = "scif2"; }; + i2c2_pins: i2c2 { + renesas,groups = "i2c2_a"; + renesas,function = "i2c2"; + }; + avb_pins: avb { renesas,groups = "avb_mdc"; renesas,function = "avb"; @@ -67,6 +72,13 @@ status = "okay"; }; +&i2c2 { + pinctrl-0 = <&i2c2_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + &avb { pinctrl-0 = <&avb_pins>; pinctrl-names = "default"; -- cgit v1.2.3-59-g8ed1b From d8bd64c1514ed5dca1c864b24a08d3314829eeb8 Mon Sep 17 00:00:00 2001 From: Jon Mason Date: Fri, 20 Nov 2015 10:17:20 -0500 Subject: ARM64: dts: enable clock support for Broadcom NS2 Add device tree entries for clock support for Broadcom Northstar 2 SoC Signed-off-by: Jon Mason Reviewed-by: Ray Jui Signed-off-by: Florian Fainelli --- arch/arm64/boot/dts/broadcom/ns2.dtsi | 80 ++++++++++++++++++++++++++++++++++- 1 file changed, 79 insertions(+), 1 deletion(-) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/broadcom/ns2.dtsi b/arch/arm64/boot/dts/broadcom/ns2.dtsi index 96108228410c..a510d3a8e647 100644 --- a/arch/arm64/boot/dts/broadcom/ns2.dtsi +++ b/arch/arm64/boot/dts/broadcom/ns2.dtsi @@ -31,6 +31,7 @@ */ #include +#include /memreserve/ 0x84b00000 0x00000008; @@ -109,6 +110,33 @@ <&A57_3>; }; + clocks { + #address-cells = <1>; + #size-cells = <1>; + + osc: oscillator { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <25000000>; + }; + + iprocmed: iprocmed { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&genpll_scr BCM_NS2_GENPLL_SCR_SCR_CLK>; + clock-div = <2>; + clock-mult = <1>; + }; + + iprocslow: iprocslow { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&genpll_scr BCM_NS2_GENPLL_SCR_SCR_CLK>; + clock-div = <4>; + clock-mult = <1>; + }; + }; + soc: soc { compatible = "simple-bus"; #address-cells = <1>; @@ -156,6 +184,56 @@ mmu-masters; }; + lcpll_ddr: lcpll_ddr@6501d058 { + #clock-cells = <1>; + compatible = "brcm,ns2-lcpll-ddr"; + reg = <0x6501d058 0x20>, + <0x6501c020 0x4>, + <0x6501d04c 0x4>; + clocks = <&osc>; + clock-output-names = "lcpll_ddr", "pcie_sata_usb", + "ddr", "ddr_ch2_unused", + "ddr_ch3_unused", "ddr_ch4_unused", + "ddr_ch5_unused"; + }; + + lcpll_ports: lcpll_ports@6501d078 { + #clock-cells = <1>; + compatible = "brcm,ns2-lcpll-ports"; + reg = <0x6501d078 0x20>, + <0x6501c020 0x4>, + <0x6501d054 0x4>; + clocks = <&osc>; + clock-output-names = "lcpll_ports", "wan", "rgmii", + "ports_ch2_unused", + "ports_ch3_unused", + "ports_ch4_unused", + "ports_ch5_unused"; + }; + + genpll_scr: genpll_scr@6501d098 { + #clock-cells = <1>; + compatible = "brcm,ns2-genpll-scr"; + reg = <0x6501d098 0x32>, + <0x6501c020 0x4>, + <0x6501d044 0x4>; + clocks = <&osc>; + clock-output-names = "genpll_scr", "scr", "fs", + "audio_ref", "scr_ch3_unused", + "scr_ch4_unused", "scr_ch5_unused"; + }; + + genpll_sw: genpll_sw@6501d0c4 { + #clock-cells = <1>; + compatible = "brcm,ns2-genpll-sw"; + reg = <0x6501d0c4 0x32>, + <0x6501c020 0x4>, + <0x6501d044 0x4>; + clocks = <&osc>; + clock-output-names = "genpll_sw", "rpe", "250", "nic", + "chimp", "port", "sdio"; + }; + crmu: crmu@65024000 { compatible = "syscon"; reg = <0x65024000 0x100>; @@ -204,7 +282,7 @@ interrupts = ; reg-shift = <2>; reg-io-width = <4>; - clock-frequency = <23961600>; + clocks = <&osc>; status = "disabled"; }; -- cgit v1.2.3-59-g8ed1b From c68bb56efb25e2d326ae413e399cdb1b4528e173 Mon Sep 17 00:00:00 2001 From: Caesar Wang Date: Mon, 9 Nov 2015 12:49:00 +0800 Subject: arm64: dts: rockchip: Add the thermal data found on RK3368 This patchset add the thermal for RK3368 dts, Since the two CPU clusters, with four CPU core for each cluster, one cluster is optimized for high-performance(big cluster) and the othe is optimized for low power(little cluster). This patch adds the second order for thermal throttle, and the critical temperature for thermal over-tempeature protection on Software. Signed-off-by: Caesar Wang Acked-by: Eduardo Valentin Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3368-thermal.dtsi | 112 +++++++++++++++++++++++ 1 file changed, 112 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3368-thermal.dtsi (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/rockchip/rk3368-thermal.dtsi b/arch/arm64/boot/dts/rockchip/rk3368-thermal.dtsi new file mode 100644 index 000000000000..a10010f92f96 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3368-thermal.dtsi @@ -0,0 +1,112 @@ +/* + * Device Tree Source for RK3368 SoC thermal + * + * Copyright (c) 2015, Fuzhou Rockchip Electronics Co., Ltd + * Caesar Wang + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include + +cpu_thermal: cpu_thermal { + polling-delay-passive = <100>; /* milliseconds */ + polling-delay = <5000>; /* milliseconds */ + + thermal-sensors = <&tsadc 0>; + + trips { + cpu_alert0: cpu_alert0 { + temperature = <75000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + cpu_alert1: cpu_alert1 { + temperature = <80000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + cpu_crit: cpu_crit { + temperature = <95000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu_alert0>; + cooling-device = + <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + map1 { + trip = <&cpu_alert1>; + cooling-device = + <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; +}; + +gpu_thermal: gpu_thermal { + polling-delay-passive = <100>; /* milliseconds */ + polling-delay = <5000>; /* milliseconds */ + + thermal-sensors = <&tsadc 1>; + + trips { + gpu_alert0: gpu_alert0 { + temperature = <80000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + gpu_crit: gpu_crit { + temperature = <1150000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&gpu_alert0>; + cooling-device = + <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; +}; -- cgit v1.2.3-59-g8ed1b From f990238f859e95841ecd151da258ea999555f609 Mon Sep 17 00:00:00 2001 From: Caesar Wang Date: Mon, 9 Nov 2015 12:49:01 +0800 Subject: arm64: dts: rockchip: Add main thermal info to rk3368.dtsi This patch add the thermal needed info on RK3368. Meanwhile, support the trips to throttle for thermal. Signed-off-by: Caesar Wang Acked-by: Eduardo Valentin Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3368.dtsi | 36 ++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/rockchip/rk3368.dtsi b/arch/arm64/boot/dts/rockchip/rk3368.dtsi index 1f10b85b64ab..02fe8718d6f0 100644 --- a/arch/arm64/boot/dts/rockchip/rk3368.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3368.dtsi @@ -45,6 +45,7 @@ #include #include #include +#include / { compatible = "rockchip,rk3368"; @@ -124,6 +125,8 @@ reg = <0x0 0x0>; cpu-idle-states = <&cpu_sleep>; enable-method = "psci"; + + #cooling-cells = <2>; /* min followed by max */ }; cpu_l1: cpu@1 { @@ -156,6 +159,8 @@ reg = <0x0 0x100>; cpu-idle-states = <&cpu_sleep>; enable-method = "psci"; + + #cooling-cells = <2>; /* min followed by max */ }; cpu_b1: cpu@101 { @@ -405,6 +410,27 @@ status = "disabled"; }; + thermal-zones { + #include "rk3368-thermal.dtsi" + }; + + tsadc: tsadc@ff280000 { + compatible = "rockchip,rk3368-tsadc"; + reg = <0x0 0xff280000 0x0 0x100>; + interrupts = ; + clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; + clock-names = "tsadc", "apb_pclk"; + resets = <&cru SRST_TSADC>; + reset-names = "tsadc-apb"; + pinctrl-names = "init", "default", "sleep"; + pinctrl-0 = <&otp_gpio>; + pinctrl-1 = <&otp_out>; + pinctrl-2 = <&otp_gpio>; + #thermal-sensor-cells = <1>; + rockchip,hw-tshut-temp = <95000>; + status = "disabled"; + }; + gmac: ethernet@ff290000 { compatible = "rockchip,rk3368-gmac"; reg = <0x0 0xff290000 0x0 0x10000>; @@ -830,6 +856,16 @@ }; }; + tsadc { + otp_gpio: otp-gpio { + rockchip,pins = <0 10 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + otp_out: otp-out { + rockchip,pins = <0 10 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + uart0 { uart0_xfer: uart0-xfer { rockchip,pins = <2 24 RK_FUNC_1 &pcfg_pull_up>, -- cgit v1.2.3-59-g8ed1b From 10a37de377e8c481f5bd0e89ae1c35fc2acdc4b4 Mon Sep 17 00:00:00 2001 From: Caesar Wang Date: Mon, 9 Nov 2015 12:49:02 +0800 Subject: arm64: dts: rockchip: Enable the Thermal on R88 board This patch enable the TS-ADC. When a thermal temperature is invoked use the CRU to reset the chip on R88 board. TSHUT is low active on this board. Signed-off-by: Caesar Wang Acked-by: Eduardo Valentin Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3368-r88.dts | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/rockchip/rk3368-r88.dts b/arch/arm64/boot/dts/rockchip/rk3368-r88.dts index 401a81231eb9..104cbee762bb 100644 --- a/arch/arm64/boot/dts/rockchip/rk3368-r88.dts +++ b/arch/arm64/boot/dts/rockchip/rk3368-r88.dts @@ -336,6 +336,12 @@ status = "okay"; }; +&tsadc { + rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */ + rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */ + status = "okay"; +}; + &uart2 { status = "okay"; }; -- cgit v1.2.3-59-g8ed1b From 4fa04299184604d5ae85a3ebe795e19eb564fc67 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 19 Nov 2015 19:29:11 +0100 Subject: arm64: renesas: r8a7795 dtsi: Add all HSCIF nodes Add the device nodes for all HSCIF serial ports, incl. clocks, clock domain, and dma properties. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a7795.dtsi | 60 ++++++++++++++++++++++++++++++++ 1 file changed, 60 insertions(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi index c01a7e4f59a4..348baebffeac 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi @@ -262,6 +262,66 @@ #size-cells = <0>; }; + hscif0: serial@e6540000 { + compatible = "renesas,hscif-r8a7795", "renesas,hscif"; + reg = <0 0xe6540000 0 96>; + interrupts = ; + clocks = <&cpg CPG_MOD 520>; + clock-names = "sci_ick"; + dmas = <&dmac1 0x31>, <&dmac1 0x30>; + dma-names = "tx", "rx"; + power-domains = <&cpg>; + status = "disabled"; + }; + + hscif1: serial@e6550000 { + compatible = "renesas,hscif-r8a7795", "renesas,hscif"; + reg = <0 0xe6550000 0 96>; + interrupts = ; + clocks = <&cpg CPG_MOD 519>; + clock-names = "sci_ick"; + dmas = <&dmac1 0x33>, <&dmac1 0x32>; + dma-names = "tx", "rx"; + power-domains = <&cpg>; + status = "disabled"; + }; + + hscif2: serial@e6560000 { + compatible = "renesas,hscif-r8a7795", "renesas,hscif"; + reg = <0 0xe6560000 0 96>; + interrupts = ; + clocks = <&cpg CPG_MOD 518>; + clock-names = "sci_ick"; + dmas = <&dmac1 0x35>, <&dmac1 0x34>; + dma-names = "tx", "rx"; + power-domains = <&cpg>; + status = "disabled"; + }; + + hscif3: serial@e66a0000 { + compatible = "renesas,hscif-r8a7795", "renesas,hscif"; + reg = <0 0xe66a0000 0 96>; + interrupts = ; + clocks = <&cpg CPG_MOD 517>; + clock-names = "sci_ick"; + dmas = <&dmac0 0x37>, <&dmac0 0x36>; + dma-names = "tx", "rx"; + power-domains = <&cpg>; + status = "disabled"; + }; + + hscif4: serial@e66b0000 { + compatible = "renesas,hscif-r8a7795", "renesas,hscif"; + reg = <0 0xe66b0000 0 96>; + interrupts = ; + clocks = <&cpg CPG_MOD 516>; + clock-names = "sci_ick"; + dmas = <&dmac0 0x39>, <&dmac0 0x38>; + dma-names = "tx", "rx"; + power-domains = <&cpg>; + status = "disabled"; + }; + scif0: serial@e6e60000 { compatible = "renesas,scif-r8a7795", "renesas,scif"; reg = <0 0xe6e60000 0 64>; -- cgit v1.2.3-59-g8ed1b From b281f4c8c198533d3e7dfb0f0302a2c3d96f6bc8 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Wed, 25 Nov 2015 06:36:02 +0000 Subject: arm64: renesas: r8a7795: add AUDIO_DMAC support Signed-off-by: Kuninori Morimoto Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a7795.dtsi | 64 ++++++++++++++++++++++++++++++++ 1 file changed, 64 insertions(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi index 348baebffeac..2cc58114d1ef 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi @@ -203,6 +203,70 @@ #power-domain-cells = <0>; }; + audma0: dma-controller@ec700000 { + compatible = "renesas,rcar-dmac"; + reg = <0 0xec700000 0 0x10000>; + interrupts = <0 350 IRQ_TYPE_LEVEL_HIGH + 0 320 IRQ_TYPE_LEVEL_HIGH + 0 321 IRQ_TYPE_LEVEL_HIGH + 0 322 IRQ_TYPE_LEVEL_HIGH + 0 323 IRQ_TYPE_LEVEL_HIGH + 0 324 IRQ_TYPE_LEVEL_HIGH + 0 325 IRQ_TYPE_LEVEL_HIGH + 0 326 IRQ_TYPE_LEVEL_HIGH + 0 327 IRQ_TYPE_LEVEL_HIGH + 0 328 IRQ_TYPE_LEVEL_HIGH + 0 329 IRQ_TYPE_LEVEL_HIGH + 0 330 IRQ_TYPE_LEVEL_HIGH + 0 331 IRQ_TYPE_LEVEL_HIGH + 0 332 IRQ_TYPE_LEVEL_HIGH + 0 333 IRQ_TYPE_LEVEL_HIGH + 0 334 IRQ_TYPE_LEVEL_HIGH + 0 335 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15"; + clocks = <&cpg CPG_MOD 502>; + clock-names = "fck"; + power-domains = <&cpg>; + #dma-cells = <1>; + dma-channels = <16>; + }; + + audma1: dma-controller@ec720000 { + compatible = "renesas,rcar-dmac"; + reg = <0 0xec720000 0 0x10000>; + interrupts = <0 351 IRQ_TYPE_LEVEL_HIGH + 0 336 IRQ_TYPE_LEVEL_HIGH + 0 337 IRQ_TYPE_LEVEL_HIGH + 0 338 IRQ_TYPE_LEVEL_HIGH + 0 339 IRQ_TYPE_LEVEL_HIGH + 0 340 IRQ_TYPE_LEVEL_HIGH + 0 341 IRQ_TYPE_LEVEL_HIGH + 0 342 IRQ_TYPE_LEVEL_HIGH + 0 343 IRQ_TYPE_LEVEL_HIGH + 0 344 IRQ_TYPE_LEVEL_HIGH + 0 345 IRQ_TYPE_LEVEL_HIGH + 0 346 IRQ_TYPE_LEVEL_HIGH + 0 347 IRQ_TYPE_LEVEL_HIGH + 0 348 IRQ_TYPE_LEVEL_HIGH + 0 349 IRQ_TYPE_LEVEL_HIGH + 0 382 IRQ_TYPE_LEVEL_HIGH + 0 383 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15"; + clocks = <&cpg CPG_MOD 501>; + clock-names = "fck"; + power-domains = <&cpg>; + #dma-cells = <1>; + dma-channels = <16>; + }; + pfc: pfc@e6060000 { compatible = "renesas,pfc-r8a7795"; reg = <0 0xe6060000 0 0x50c>; -- cgit v1.2.3-59-g8ed1b From 623197b90c7aa97c0626b0aec06f95d05666b3e0 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Wed, 25 Nov 2015 06:36:25 +0000 Subject: arm64: renesas: r8a7795: Sound SSI PIO support This patch adds SSI for PIO sound support Signed-off-by: Kuninori Morimoto Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a7795.dtsi | 95 ++++++++++++++++++++++++++++++++ 1 file changed, 95 insertions(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi index 2cc58114d1ef..15753f4dcf4e 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi @@ -52,6 +52,29 @@ clock-frequency = <0>; }; + /* + * The external audio clocks are configured as 0 Hz fixed frequency + * clocks by default. + * Boards that provide audio clocks should override them. + */ + audio_clk_a: audio_clk_a { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + audio_clk_b: audio_clk_b { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + audio_clk_c: audio_clk_c { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + soc { compatible = "simple-bus"; interrupt-parent = <&gic>; @@ -534,5 +557,77 @@ power-domains = <&cpg>; status = "disabled"; }; + + rcar_sound: sound@ec500000 { + /* + * #sound-dai-cells is required + * + * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; + * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; + */ + /* + * #clock-cells is required for audio_clkout0/1/2/3 + * + * clkout : #clock-cells = <0>; <&rcar_sound>; + * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>; + */ + compatible = "renesas,rcar_sound-r8a7795", "renesas,rcar_sound-gen3"; + reg = <0 0xec500000 0 0x1000>, /* SCU */ + <0 0xec5a0000 0 0x100>, /* ADG */ + <0 0xec540000 0 0x1000>, /* SSIU */ + <0 0xec541000 0 0x280>, /* SSI */ + <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/ + reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; + + clocks = <&cpg CPG_MOD 1005>, + <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, + <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, + <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, + <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, + <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, + <&audio_clk_a>, <&audio_clk_b>, + <&audio_clk_c>, + <&cpg CPG_CORE R8A7795_CLK_S0D4>; + clock-names = "ssi-all", + "ssi.9", "ssi.8", "ssi.7", "ssi.6", + "ssi.5", "ssi.4", "ssi.3", "ssi.2", + "ssi.1", "ssi.0", + "clk_a", "clk_b", "clk_c", "clk_i"; + power-domains = <&cpg>; + status = "disabled"; + + rcar_sound,ssi { + ssi0: ssi@0 { + interrupts = <0 370 IRQ_TYPE_LEVEL_HIGH>; + }; + ssi1: ssi@1 { + interrupts = <0 371 IRQ_TYPE_LEVEL_HIGH>; + }; + ssi2: ssi@2 { + interrupts = <0 372 IRQ_TYPE_LEVEL_HIGH>; + }; + ssi3: ssi@3 { + interrupts = <0 373 IRQ_TYPE_LEVEL_HIGH>; + }; + ssi4: ssi@4 { + interrupts = <0 374 IRQ_TYPE_LEVEL_HIGH>; + }; + ssi5: ssi@5 { + interrupts = <0 375 IRQ_TYPE_LEVEL_HIGH>; + }; + ssi6: ssi@6 { + interrupts = <0 376 IRQ_TYPE_LEVEL_HIGH>; + }; + ssi7: ssi@7 { + interrupts = <0 377 IRQ_TYPE_LEVEL_HIGH>; + }; + ssi8: ssi@8 { + interrupts = <0 378 IRQ_TYPE_LEVEL_HIGH>; + }; + ssi9: ssi@9 { + interrupts = <0 379 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + }; }; }; -- cgit v1.2.3-59-g8ed1b From 10d18ab8392bb6e81224f37054693a0ea4366a0c Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Wed, 25 Nov 2015 06:36:48 +0000 Subject: arm64: renesas: r8a7795: Sound SSI DMA support Signed-off-by: Kuninori Morimoto Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a7795.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi index 15753f4dcf4e..5d684e961675 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi @@ -599,33 +599,53 @@ rcar_sound,ssi { ssi0: ssi@0 { interrupts = <0 370 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>; + dma-names = "rx", "tx", "rxu", "txu"; }; ssi1: ssi@1 { interrupts = <0 371 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>; + dma-names = "rx", "tx", "rxu", "txu"; }; ssi2: ssi@2 { interrupts = <0 372 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>; + dma-names = "rx", "tx", "rxu", "txu"; }; ssi3: ssi@3 { interrupts = <0 373 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>; + dma-names = "rx", "tx", "rxu", "txu"; }; ssi4: ssi@4 { interrupts = <0 374 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>; + dma-names = "rx", "tx", "rxu", "txu"; }; ssi5: ssi@5 { interrupts = <0 375 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>; + dma-names = "rx", "tx", "rxu", "txu"; }; ssi6: ssi@6 { interrupts = <0 376 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>; + dma-names = "rx", "tx", "rxu", "txu"; }; ssi7: ssi@7 { interrupts = <0 377 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>; + dma-names = "rx", "tx", "rxu", "txu"; }; ssi8: ssi@8 { interrupts = <0 378 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>; + dma-names = "rx", "tx", "rxu", "txu"; }; ssi9: ssi@9 { interrupts = <0 379 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>; + dma-names = "rx", "tx", "rxu", "txu"; }; }; }; -- cgit v1.2.3-59-g8ed1b From b868ff51d5625a28a50ce8d40992d562535d3972 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Wed, 25 Nov 2015 06:37:08 +0000 Subject: arm64: renesas: r8a7795: Sound SRC support Signed-off-by: Kuninori Morimoto Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a7795.dtsi | 61 ++++++++++++++++++++++++++++++++ 1 file changed, 61 insertions(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi index 5d684e961675..c3b2089de531 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi @@ -585,6 +585,11 @@ <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, + <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, + <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, + <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, + <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, + <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, <&cpg CPG_CORE R8A7795_CLK_S0D4>; @@ -592,10 +597,66 @@ "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5", "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0", + "src.9", "src.8", "src.7", "src.6", + "src.5", "src.4", "src.3", "src.2", + "src.1", "src.0", "clk_a", "clk_b", "clk_c", "clk_i"; power-domains = <&cpg>; status = "disabled"; + rcar_sound,src { + src0: src@0 { + interrupts = <0 352 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x85>, <&audma1 0x9a>; + dma-names = "rx", "tx"; + }; + src1: src@1 { + interrupts = <0 353 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x87>, <&audma1 0x9c>; + dma-names = "rx", "tx"; + }; + src2: src@2 { + interrupts = <0 354 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x89>, <&audma1 0x9e>; + dma-names = "rx", "tx"; + }; + src3: src@3 { + interrupts = <0 355 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x8b>, <&audma1 0xa0>; + dma-names = "rx", "tx"; + }; + src4: src@4 { + interrupts = <0 356 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x8d>, <&audma1 0xb0>; + dma-names = "rx", "tx"; + }; + src5: src@5 { + interrupts = <0 357 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x8f>, <&audma1 0xb2>; + dma-names = "rx", "tx"; + }; + src6: src@6 { + interrupts = <0 358 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x91>, <&audma1 0xb4>; + dma-names = "rx", "tx"; + }; + src7: src@7 { + interrupts = <0 359 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x93>, <&audma1 0xb6>; + dma-names = "rx", "tx"; + }; + src8: src@8 { + interrupts = <0 360 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x95>, <&audma1 0xb8>; + dma-names = "rx", "tx"; + }; + src9: src@9 { + interrupts = <0 361 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x97>, <&audma1 0xba>; + dma-names = "rx", "tx"; + }; + }; + rcar_sound,ssi { ssi0: ssi@0 { interrupts = <0 370 IRQ_TYPE_LEVEL_HIGH>; -- cgit v1.2.3-59-g8ed1b From b9dd9450ce0cfb60d8e4afd37191f86f3afba6c2 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Wed, 25 Nov 2015 06:37:29 +0000 Subject: arm64: renesas: r8a7795: Sound DVC support Signed-off-by: Kuninori Morimoto Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a7795.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi index c3b2089de531..b1902ea1dae4 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi @@ -590,6 +590,7 @@ <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, + <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, <&cpg CPG_CORE R8A7795_CLK_S0D4>; @@ -600,10 +601,22 @@ "src.9", "src.8", "src.7", "src.6", "src.5", "src.4", "src.3", "src.2", "src.1", "src.0", + "dvc.0", "dvc.1", "clk_a", "clk_b", "clk_c", "clk_i"; power-domains = <&cpg>; status = "disabled"; + rcar_sound,dvc { + dvc0: dvc@0 { + dmas = <&audma0 0xbc>; + dma-names = "tx"; + }; + dvc1: dvc@1 { + dmas = <&audma0 0xbe>; + dma-names = "tx"; + }; + }; + rcar_sound,src { src0: src@0 { interrupts = <0 352 IRQ_TYPE_LEVEL_HIGH>; -- cgit v1.2.3-59-g8ed1b From 994aadf019e9ca7d16634f4e3b442950cefb4a05 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Wed, 25 Nov 2015 06:37:49 +0000 Subject: arm64: renesas: salvator-x: Sound SSI PIO support This patch adds PIO sound support for Salvator-X board. It can use 44.1kHz base sound only at this point, since 48kHz base sound needs CS2000, but it is not yet upstreamed. Signed-off-by: Kuninori Morimoto Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts | 76 ++++++++++++++++++++++ 1 file changed, 76 insertions(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts index d829fdae3c56..90ca7faa629c 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts +++ b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts @@ -31,6 +31,28 @@ /* first 128MB is reserved for secure area. */ reg = <0x0 0x48000000 0x0 0x38000000>; }; + + x12_clk: x12_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24576000>; + }; + + rsnd_ak4613: sound { + compatible = "simple-audio-card"; + + simple-audio-card,format = "left_j"; + simple-audio-card,bitclock-master = <&sndcpu>; + simple-audio-card,frame-master = <&sndcpu>; + + sndcpu: simple-audio-card,cpu { + sound-dai = <&rcar_sound>; + }; + + sndcodec: simple-audio-card,codec { + sound-dai = <&ak4613>; + }; + }; }; &extal_clk { @@ -56,6 +78,17 @@ renesas,groups = "avb_mdc"; renesas,function = "avb"; }; + + sound_pins: sound { + renesas,groups = "ssi01239_ctrl", "ssi0_data", "ssi1_data_a"; + renesas,function = "ssi"; + }; + + sound_clk_pins: sound_clk { + renesas,groups = "audio_clk_a_a", "audio_clk_b_a", "audio_clk_c_a", + "audio_clkout_a", "audio_clkout3_a"; + renesas,function = "audio_clk"; + }; }; &scif1 { @@ -77,6 +110,49 @@ pinctrl-names = "default"; status = "okay"; + + clock-frequency = <100000>; + + ak4613: codec@10 { + compatible = "asahi-kasei,ak4613"; + #sound-dai-cells = <0>; + reg = <0x10>; + clocks = <&rcar_sound 3>; + }; +}; + +&rcar_sound { + pinctrl-0 = <&sound_pins &sound_clk_pins>; + pinctrl-names = "default"; + + /* Single DAI */ + #sound-dai-cells = <0>; + + /* audio_clkout0/1/2/3 */ + #clock-cells = <1>; + clock-frequency = <11289600>; + + status = "okay"; + + rcar_sound,dai { + dai0 { + playback = <&ssi0>; + capture = <&ssi1>; + }; + }; +}; + +&ssi0 { + pio-transfer; +}; + +&ssi1 { + pio-transfer; + shared-pin; +}; + +&audio_clk_a { + clock-frequency = <22579200>; }; &avb { -- cgit v1.2.3-59-g8ed1b From d70726f4280f1d49f4e4a71008dad79e51251c24 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Wed, 25 Nov 2015 06:38:08 +0000 Subject: arm64: renesas: salvator-x: Sound SSI DMA support DMA transfer to/from SSI DMA [MEM] -> [SSI] DMA [MEM] <- [SSI] Signed-off-by: Kuninori Morimoto Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts index 90ca7faa629c..9c5fd4a32000 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts +++ b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts @@ -143,11 +143,11 @@ }; &ssi0 { - pio-transfer; + no-busif; }; &ssi1 { - pio-transfer; + no-busif; shared-pin; }; -- cgit v1.2.3-59-g8ed1b From b1d11d6743fccb533e724485dc83cce08579088d Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Wed, 25 Nov 2015 06:38:31 +0000 Subject: arm64: renesas: salvator-x: Sound SSI DMA support via BUSIF DMA transfer to/from SSIU DMA [MEM] -> [SSIU] -> [SSI] DMA [MEM] <- [SSIU] <- [SSI] Signed-off-by: Kuninori Morimoto Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts | 5 ----- 1 file changed, 5 deletions(-) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts index 9c5fd4a32000..e49e5dc6dafc 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts +++ b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts @@ -142,12 +142,7 @@ }; }; -&ssi0 { - no-busif; -}; - &ssi1 { - no-busif; shared-pin; }; -- cgit v1.2.3-59-g8ed1b From f7df91f5f2f987f2639d292dc3f9101ad7318cf7 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Wed, 25 Nov 2015 06:38:52 +0000 Subject: arm64: renesas: salvator-x: Sound SRC support Signed-off-by: Kuninori Morimoto Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts index e49e5dc6dafc..47bf252774d7 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts +++ b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts @@ -136,8 +136,8 @@ rcar_sound,dai { dai0 { - playback = <&ssi0>; - capture = <&ssi1>; + playback = <&ssi0 &src0>; + capture = <&ssi1 &src1>; }; }; }; -- cgit v1.2.3-59-g8ed1b From 672b79312c04016481a11d4b996b4512207ffbd3 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Wed, 25 Nov 2015 06:39:13 +0000 Subject: arm64: renesas: salvator-x: Sound DVC support Signed-off-by: Kuninori Morimoto Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts | 27 ++++++++++++++++++++-- 1 file changed, 25 insertions(+), 2 deletions(-) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts index 47bf252774d7..c5f709e7c0ba 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts +++ b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts @@ -8,6 +8,29 @@ * kind, whether express or implied. */ +/* + * SSI-AK4613 + * + * This command is required when Playback/Capture + * + * amixer set "DVC Out" 100% + * amixer set "DVC In" 100% + * + * You can use Mute + * + * amixer set "DVC Out Mute" on + * amixer set "DVC In Mute" on + * + * You can use Volume Ramp + * + * amixer set "DVC Out Ramp Up Rate" "0.125 dB/64 steps" + * amixer set "DVC Out Ramp Down Rate" "0.125 dB/512 steps" + * amixer set "DVC Out Ramp" on + * aplay xxx.wav & + * amixer set "DVC Out" 80% // Volume Down + * amixer set "DVC Out" 100% // Volume Up + */ + /dts-v1/; #include "r8a7795.dtsi" @@ -136,8 +159,8 @@ rcar_sound,dai { dai0 { - playback = <&ssi0 &src0>; - capture = <&ssi1 &src1>; + playback = <&ssi0 &src0 &dvc0>; + capture = <&ssi1 &src1 &dvc1>; }; }; }; -- cgit v1.2.3-59-g8ed1b From d2318f3402539c15d89166b0863d9367a8f8d3bf Mon Sep 17 00:00:00 2001 From: Jisheng Zhang Date: Mon, 16 Nov 2015 19:09:50 +0800 Subject: arm64: dts: berlin4ct: add watchdog nodes The Marvell Berlin BG4CT has 3 watchdogs which are compatible with the snps,dw-wdt driver sit in the sysmgr domain. This patch adds the corresponding device tree nodes. Signed-off-by: Jisheng Zhang Signed-off-by: Sebastian Hesselbarth --- arch/arm64/boot/dts/marvell/berlin4ct.dtsi | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/marvell/berlin4ct.dtsi b/arch/arm64/boot/dts/marvell/berlin4ct.dtsi index a4a18764ae98..a2d4e2dd3209 100644 --- a/arch/arm64/boot/dts/marvell/berlin4ct.dtsi +++ b/arch/arm64/boot/dts/marvell/berlin4ct.dtsi @@ -251,6 +251,29 @@ interrupts = ; }; + wdt0: watchdog@3000 { + compatible = "snps,dw-wdt"; + reg = <0x3000 0x100>; + clocks = <&osc>; + interrupts = <0>; + }; + + wdt1: watchdog@4000 { + compatible = "snps,dw-wdt"; + reg = <0x4000 0x100>; + clocks = <&osc>; + interrupts = <1>; + status = "disabled"; + }; + + wdt2: watchdog@5000 { + compatible = "snps,dw-wdt"; + reg = <0x5000 0x100>; + clocks = <&osc>; + interrupts = <2>; + status = "disabled"; + }; + sm_gpio0: gpio@8000 { compatible = "snps,dw-apb-gpio"; reg = <0x8000 0x400>; -- cgit v1.2.3-59-g8ed1b From 5fbb15316fdd8f00143179ffb3a03f501c4b50dc Mon Sep 17 00:00:00 2001 From: Jisheng Zhang Date: Mon, 16 Nov 2015 19:37:49 +0800 Subject: arm64: dts: berlin: PSCI-1.0 support The firmware can support PSCI-1.0 in fact. This change also enables suspend to ram on Marvell berlin arm64 SoC. Signed-off-by: Jisheng Zhang Signed-off-by: Sebastian Hesselbarth --- arch/arm64/boot/dts/marvell/berlin4ct.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/marvell/berlin4ct.dtsi b/arch/arm64/boot/dts/marvell/berlin4ct.dtsi index a2d4e2dd3209..6cd77272ab88 100644 --- a/arch/arm64/boot/dts/marvell/berlin4ct.dtsi +++ b/arch/arm64/boot/dts/marvell/berlin4ct.dtsi @@ -55,7 +55,7 @@ }; psci { - compatible = "arm,psci-0.2"; + compatible = "arm,psci-1.0", "arm,psci-0.2"; method = "smc"; }; -- cgit v1.2.3-59-g8ed1b From 40fbe14b54bac16d5ec2fcf077b8aa54fb9de6b2 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Fri, 27 Nov 2015 01:04:41 +0000 Subject: arm64: renesas: salvator-x: set ak4613 In/Out pin as single-end Signed-off-by: Kuninori Morimoto Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts index c5f709e7c0ba..beeacfaf18d0 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts +++ b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts @@ -141,6 +141,15 @@ #sound-dai-cells = <0>; reg = <0x10>; clocks = <&rcar_sound 3>; + + asahi-kasei,in1-single-end; + asahi-kasei,in2-single-end; + asahi-kasei,out1-single-end; + asahi-kasei,out2-single-end; + asahi-kasei,out3-single-end; + asahi-kasei,out4-single-end; + asahi-kasei,out5-single-end; + asahi-kasei,out6-single-end; }; }; -- cgit v1.2.3-59-g8ed1b From 8a8f181d2cfdbff772ff2cc895f59bb28beafbdf Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Tue, 1 Dec 2015 05:36:34 +0000 Subject: arm64: renesas: salvator-x: use CS2000 as AUDIO_CLK_B CS2000 needs AUDIO_CLKOUT as master clock which is generated by Renesas sound, and Renesas sound needs CS2000 as ADUIO_CLK_B. Because of this relationship, it will be dead-lock when driver probe. cs2000: clk_multiplier@4f { ... clocks = <&rcar_sound 0>, <&x12_clk>; ... }; &rcar_sound { ... assigned-clocks = <&cs2000>; ... }; This patch is using dummy audio_clkout to avoid this issue. Signed-off-by: Kuninori Morimoto Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts | 38 ++++++++++++++++++++++ 1 file changed, 38 insertions(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts index beeacfaf18d0..75af5ec5a4d4 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts +++ b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts @@ -61,6 +61,16 @@ clock-frequency = <24576000>; }; + audio_clkout: audio_clkout { + /* + * This is same as <&rcar_sound 0> + * but needed to avoid cs2000/rcar_sound probe dead-lock + */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <11289600>; + }; + rsnd_ak4613: sound { compatible = "simple-audio-card"; @@ -151,6 +161,17 @@ asahi-kasei,out5-single-end; asahi-kasei,out6-single-end; }; + + cs2000: clk_multiplier@4f { + #clock-cells = <0>; + compatible = "cirrus,cs2000-cp"; + reg = <0x4f>; + clocks = <&audio_clkout>, <&x12_clk>; + clock-names = "clk_in", "ref_clk"; + + assigned-clocks = <&cs2000>; + assigned-clock-rates = <24576000>; /* 1/1 divide */ + }; }; &rcar_sound { @@ -166,6 +187,23 @@ status = "okay"; + /* update to */ + clocks = <&cpg CPG_MOD 1005>, + <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, + <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, + <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, + <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, + <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, + <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, + <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, + <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, + <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, + <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, + <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, + <&audio_clk_a>, <&cs2000>, + <&audio_clk_c>, + <&cpg CPG_CORE R8A7795_CLK_S0D4>; + rcar_sound,dai { dai0 { playback = <&ssi0 &src0 &dvc0>; -- cgit v1.2.3-59-g8ed1b From fa54322a94ef300c596191d11c35748041da35dc Mon Sep 17 00:00:00 2001 From: Caesar Wang Date: Tue, 1 Dec 2015 17:13:26 +0800 Subject: arm64: dts: rockchip: add the pwm node info for RK3368 SoCs The pulse-width modulator (PWM) feature is very common in embedded systems. On the rk3368 there exist 4 built-in PWM channels. In general, the pwm pins can via the pinctrl to configure iomux mode except the pwm2 since the pwm2 iomux mode from the SoC control register. Signed-off-by: Caesar Wang Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3368.dtsi | 60 ++++++++++++++++++++++++++++++++ 1 file changed, 60 insertions(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/rockchip/rk3368.dtsi b/arch/arm64/boot/dts/rockchip/rk3368.dtsi index 02fe8718d6f0..61ca1abde947 100644 --- a/arch/arm64/boot/dts/rockchip/rk3368.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3368.dtsi @@ -498,6 +498,48 @@ status = "disabled"; }; + pwm0: pwm@ff680000 { + compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm"; + reg = <0x0 0xff680000 0x0 0x10>; + #pwm-cells = <3>; + pinctrl-names = "default"; + pinctrl-0 = <&pwm0_pin>; + clocks = <&cru PCLK_PWM1>; + clock-names = "pwm"; + status = "disabled"; + }; + + pwm1: pwm@ff680010 { + compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm"; + reg = <0x0 0xff680010 0x0 0x10>; + #pwm-cells = <3>; + pinctrl-names = "default"; + pinctrl-0 = <&pwm1_pin>; + clocks = <&cru PCLK_PWM1>; + clock-names = "pwm"; + status = "disabled"; + }; + + pwm2: pwm@ff680020 { + compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm"; + reg = <0x0 0xff680020 0x0 0x10>; + #pwm-cells = <3>; + clocks = <&cru PCLK_PWM1>; + clock-names = "pwm"; + status = "disabled"; + }; + + pwm3: pwm@ff680030 { + compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm"; + reg = <0x0 0xff680030 0x0 0x10>; + #pwm-cells = <3>; + pinctrl-names = "default"; + pinctrl-0 = <&pwm3_pin>; + clocks = <&cru PCLK_PWM1>; + clock-names = "pwm"; + status = "disabled"; + }; + uart2: serial@ff690000 { compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart"; reg = <0x0 0xff690000 0x0 0x100>; @@ -739,6 +781,24 @@ }; }; + pwm0 { + pwm0_pin: pwm0-pin { + rockchip,pins = <3 8 RK_FUNC_2 &pcfg_pull_none>; + }; + }; + + pwm1 { + pwm1_pin: pwm1-pin { + rockchip,pins = <0 8 RK_FUNC_2 &pcfg_pull_none>; + }; + }; + + pwm3 { + pwm3_pin: pwm3-pin { + rockchip,pins = <3 29 RK_FUNC_3 &pcfg_pull_none>; + }; + }; + sdio0 { sdio0_bus1: sdio0-bus1 { rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>; -- cgit v1.2.3-59-g8ed1b From 5378e28c9776fbab6065cfb54417acff3ea5f1fd Mon Sep 17 00:00:00 2001 From: Caesar Wang Date: Tue, 1 Dec 2015 17:13:25 +0800 Subject: arm64: dts: rockchip: add rk3368 evaluation board This board is similar with the rk3288 evb board but the rk3368 top board. There exist the act8846 as the pmic. Moment, add the balight/thermal/emmc/usb.. stuff, Let the board can happy work. Signed-off-by: Caesar Wang Signed-off-by: Heiko Stuebner --- Documentation/devicetree/bindings/arm/rockchip.txt | 4 + arch/arm64/boot/dts/rockchip/Makefile | 1 + .../arm64/boot/dts/rockchip/rk3368-evb-act8846.dts | 176 +++++++++++++ arch/arm64/boot/dts/rockchip/rk3368-evb.dtsi | 281 +++++++++++++++++++++ 4 files changed, 462 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3368-evb-act8846.dts create mode 100644 arch/arm64/boot/dts/rockchip/rk3368-evb.dtsi (limited to 'arch/arm64/boot') diff --git a/Documentation/devicetree/bindings/arm/rockchip.txt b/Documentation/devicetree/bindings/arm/rockchip.txt index 8e985dd2f181..c40c091f6923 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.txt +++ b/Documentation/devicetree/bindings/arm/rockchip.txt @@ -69,6 +69,10 @@ Rockchip platforms device tree bindings "google,veyron-speedy-rev3", "google,veyron-speedy-rev2", "google,veyron-speedy", "google,veyron", "rockchip,rk3288"; +- Rockchip RK3368 evb: + Required root node properties: + - compatible = "rockchip,rk3368-evb-act8846", "rockchip,rk3368"; + - Rockchip R88 board: Required root node properties: - compatible = "rockchip,r88", "rockchip,rk3368"; diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index 601e6a236c1d..e3f0b5f4ba4e 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -1,3 +1,4 @@ +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-evb-act8846.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-r88.dtb always := $(dtb-y) diff --git a/arch/arm64/boot/dts/rockchip/rk3368-evb-act8846.dts b/arch/arm64/boot/dts/rockchip/rk3368-evb-act8846.dts new file mode 100644 index 000000000000..eed6d3c775ce --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3368-evb-act8846.dts @@ -0,0 +1,176 @@ +/* + * Copyright (c) 2015 Caesar Wang + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "rk3368-evb.dtsi" + +/ { + model = "Rockchip RK3368 EVB with ACT8846 pmic"; + compatible = "rockchip,rk3368-evb-act8846", "rockchip,rk3368"; +}; + +&i2c0 { + clock-frequency = <400000>; + + vdd_cpu: syr827@40 { + compatible = "silergy,syr827"; + reg = <0x40>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc_sys>; + }; + + vdd_gpu: syr828@41 { + compatible = "silergy,syr828"; + reg = <0x41>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_gpu"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + vin-supply = <&vcc_sys>; + }; + + act8846: act8846@5a { + compatible = "active-semi,act8846"; + reg = <0x5a>; + status = "okay"; + + vp1-supply = <&vcc_sys>; + vp2-supply = <&vcc_sys>; + vp3-supply = <&vcc_sys>; + vp4-supply = <&vcc_sys>; + inl1-supply = <&vcc_io>; + inl2-supply = <&vcc_sys>; + inl3-supply = <&vcc_20>; + + regulators { + vcc_ddr: REG1 { + regulator-name = "VCC_DDR"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + vcc_io: REG2 { + regulator-name = "VCC_IO"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vdd_log: REG3 { + regulator-name = "VDD_LOG"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + vcc_20: REG4 { + regulator-name = "VCC_20"; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + regulator-always-on; + }; + + vccio_sd: REG5 { + regulator-name = "VCCIO_SD"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vdd10_lcd: REG6 { + regulator-name = "VDD10_LCD"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + vcca_codec: REG7 { + regulator-name = "VCCA_CODEC"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vcca_tp: REG8 { + regulator-name = "VCCA_TP"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vccio_pmu: REG9 { + regulator-name = "VCCIO_PMU"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vdd_10: REG10 { + regulator-name = "VDD_10"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + vcc_18: REG11 { + regulator-name = "VCC_18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + vcc18_lcd: REG12 { + regulator-name = "VCC18_LCD"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3368-evb.dtsi b/arch/arm64/boot/dts/rockchip/rk3368-evb.dtsi new file mode 100644 index 000000000000..8c219ccf67a3 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3368-evb.dtsi @@ -0,0 +1,281 @@ +/* + * Copyright (c) 2015 Caesar Wang + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include +#include "rk3368.dtsi" + +/ { + chosen { + stdout-path = "serial2:115200n8"; + }; + + memory { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x40000000>; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + brightness-levels = < + 0 1 2 3 4 5 6 7 + 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 + 24 25 26 27 28 29 30 31 + 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255>; + default-brightness-level = <128>; + enable-gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&bl_en>; + pwms = <&pwm0 0 1000000 PWM_POLARITY_INVERTED>; + pwm-delay-us = <10000>; + }; + + emmc_pwrseq: emmc-pwrseq { + compatible = "mmc-pwrseq-emmc"; + pinctrl-0 = <&emmc_reset>; + pinctrl-names = "default"; + reset-gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>; + }; + + keys: gpio-keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pwr_key>; + + button@0 { + gpio-key,wakeup = <1>; + gpios = <&gpio0 2 GPIO_ACTIVE_LOW>; + label = "GPIO Power"; + linux,code = <116>; + }; + }; + + /* supplies both host and otg */ + vcc_host: vcc-host-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&host_vbus_drv>; + regulator-name = "vcc_host"; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc_sys>; + }; + + vcc_lan: vcc-lan-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_lan"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc_io>; + }; + + vcc_sys: vcc-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_sys"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; +}; + +&emmc { + broken-cd; + bus-width = <8>; + cap-mmc-highspeed; + disable-wp; + mmc-pwrseq = <&emmc_pwrseq>; + non-removable; + num-slots = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; + status = "okay"; +}; + +&gmac { + phy-supply = <&vcc_lan>; + phy-mode = "rmii"; + clock_in_out = "output"; + snps,reset-gpio = <&gpio3 12 0>; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 1000000>; + pinctrl-names = "default"; + pinctrl-0 = <&rmii_pins>; + tx_delay = <0x30>; + rx_delay = <0x10>; + status = "ok"; +}; + +&i2c0 { + status = "okay"; +}; + +&pinctrl { + pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma { + bias-disable; + drive-strength = <8>; + }; + + pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma { + bias-pull-up; + drive-strength = <8>; + }; + + backlight { + bl_en: bl-en { + rockchip,pins = <0 20 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + emmc { + emmc_bus8: emmc-bus8 { + rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up_drv_8ma>, + <1 19 RK_FUNC_2 &pcfg_pull_up_drv_8ma>, + <1 20 RK_FUNC_2 &pcfg_pull_up_drv_8ma>, + <1 21 RK_FUNC_2 &pcfg_pull_up_drv_8ma>, + <1 22 RK_FUNC_2 &pcfg_pull_up_drv_8ma>, + <1 23 RK_FUNC_2 &pcfg_pull_up_drv_8ma>, + <1 24 RK_FUNC_2 &pcfg_pull_up_drv_8ma>, + <1 25 RK_FUNC_2 &pcfg_pull_up_drv_8ma>; + }; + + emmc-clk { + rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none_drv_8ma>; + }; + + emmc-cmd { + rockchip,pins = <1 26 RK_FUNC_2 &pcfg_pull_up_drv_8ma>; + }; + + emmc_reset: emmc-reset { + rockchip,pins = <2 3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + keys { + pwr_key: pwr-key { + rockchip,pins = <0 2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + pmic { + pmic_int: pmic-int { + rockchip,pins = <0 1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + sdio { + wifi_reg_on: wifi-reg-on { + rockchip,pins = <3 4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_rst: bt-rst { + rockchip,pins = <3 5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + host_vbus_drv: host-vbus-drv { + rockchip,pins = <0 4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pwm0 { + status = "okay"; +}; + +&tsadc { + rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */ + rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */ + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_otg { + dr_mode = "host"; + status = "okay"; +}; + +&wdt { + status = "okay"; +}; -- cgit v1.2.3-59-g8ed1b From 1544f99c0ac08376c0a3888aef7722d9f678020c Mon Sep 17 00:00:00 2001 From: Jisheng Zhang Date: Mon, 30 Nov 2015 21:41:58 +0800 Subject: arm64: dts: berlin4ct: support cpuidle-dt This patch adds an idle-states node to describe the berlin4ct idle states and also adds references to the idle-states node in all CPU nodes. After this patch cpuidle is enabled. Signed-off-by: Jisheng Zhang Acked-by: Lorenzo Pieralisi Signed-off-by: Sebastian Hesselbarth --- arch/arm64/boot/dts/marvell/berlin4ct.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/marvell/berlin4ct.dtsi b/arch/arm64/boot/dts/marvell/berlin4ct.dtsi index 6cd77272ab88..099ad93bb49b 100644 --- a/arch/arm64/boot/dts/marvell/berlin4ct.dtsi +++ b/arch/arm64/boot/dts/marvell/berlin4ct.dtsi @@ -68,6 +68,7 @@ device_type = "cpu"; reg = <0x0>; enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0>; }; cpu1: cpu@1 { @@ -75,6 +76,7 @@ device_type = "cpu"; reg = <0x1>; enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0>; }; cpu2: cpu@2 { @@ -82,6 +84,7 @@ device_type = "cpu"; reg = <0x2>; enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0>; }; cpu3: cpu@3 { @@ -89,6 +92,19 @@ device_type = "cpu"; reg = <0x3>; enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0>; + }; + + idle-states { + entry-method = "psci"; + CPU_SLEEP_0: cpu-sleep-0 { + compatible = "arm,idle-state"; + local-timer-stop; + arm,psci-suspend-param = <0x0010000>; + entry-latency-us = <75>; + exit-latency-us = <155>; + min-residency-us = <1000>; + }; }; }; -- cgit v1.2.3-59-g8ed1b From 806c765ee9da58ca0ade34345f1b114dc0be97fd Mon Sep 17 00:00:00 2001 From: "Ivan T. Ivanov" Date: Fri, 18 Sep 2015 16:18:53 +0300 Subject: arm64: dts: qcom: 8x16: UART1 add CTS_N, RTS_N pin configurations Add devicetree bindings for UART1 CTS_N and RTS_N pins. Signed-off-by: Ivan T. Ivanov Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/msm8916-pins.dtsi | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi b/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi index 49ec55a37614..d656e892fd52 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi @@ -16,10 +16,13 @@ blsp1_uart1_default: blsp1_uart1_default { pinmux { function = "blsp_uart1"; - pins = "gpio0", "gpio1"; + // TX, RX, CTS_N, RTS_N + pins = "gpio0", "gpio1", + "gpio2", "gpio3"; }; pinconf { - pins = "gpio0", "gpio1"; + pins = "gpio0", "gpio1", + "gpio2", "gpio3"; drive-strength = <16>; bias-disable; }; @@ -28,10 +31,12 @@ blsp1_uart1_sleep: blsp1_uart1_sleep { pinmux { function = "gpio"; - pins = "gpio0", "gpio1"; + pins = "gpio0", "gpio1", + "gpio2", "gpio3"; }; pinconf { - pins = "gpio0", "gpio1"; + pins = "gpio0", "gpio1", + "gpio2", "gpio3"; drive-strength = <2>; bias-pull-down; }; -- cgit v1.2.3-59-g8ed1b From d66dd9e08fc7f3220d61ce4992f2db00b2f701af Mon Sep 17 00:00:00 2001 From: "Ivan T. Ivanov" Date: Fri, 18 Sep 2015 16:18:54 +0300 Subject: arm64: dts: qcom: 8x16: UART1 and UART2 use DMA for RX and TX Add DMA channels definitions for UART1 and UART2 controllers. Signed-off-by: Ivan T. Ivanov Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/msm8916.dtsi | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index 8d184ff19642..82881948aaeb 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -109,6 +109,8 @@ interrupts = ; clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; + dmas = <&blsp_dma 1>, <&blsp_dma 0>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -118,6 +120,8 @@ interrupts = ; clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; + dmas = <&blsp_dma 3>, <&blsp_dma 2>; + dma-names = "rx", "tx"; status = "disabled"; }; -- cgit v1.2.3-59-g8ed1b From 87ac9de3b44fd6dc8d95a59e67b086c3e57285f8 Mon Sep 17 00:00:00 2001 From: Caesar Wang Date: Wed, 2 Dec 2015 19:12:20 +0800 Subject: arm64: dts: rockchip: correct voltage range for rk3368-evb-act8846 board In general, the logic voltage is affected by ddr frequency factors. We should fix the correct voltage range since assuemd that we have the ddr frequency driver in mainline. AFAIK, the 1.8v voltage is used by the SD3.0 card. Signed-off-by: Caesar Wang Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3368-evb-act8846.dts | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/rockchip/rk3368-evb-act8846.dts b/arch/arm64/boot/dts/rockchip/rk3368-evb-act8846.dts index eed6d3c775ce..8a5275f0539b 100644 --- a/arch/arm64/boot/dts/rockchip/rk3368-evb-act8846.dts +++ b/arch/arm64/boot/dts/rockchip/rk3368-evb-act8846.dts @@ -104,8 +104,8 @@ vdd_log: REG3 { regulator-name = "VDD_LOG"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1500000>; regulator-always-on; }; @@ -118,7 +118,7 @@ vccio_sd: REG5 { regulator-name = "VCCIO_SD"; - regulator-min-microvolt = <3300000>; + regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; regulator-always-on; }; -- cgit v1.2.3-59-g8ed1b From 8fc5abd40efadf57ca43189c9c14c4de3db6300e Mon Sep 17 00:00:00 2001 From: Matthias Brugger Date: Fri, 11 Dec 2015 14:22:19 +0100 Subject: arm64: dts: rockchip: Fix typo in rk3368 sdmmc card detect pin name The card detect pin is currently called sdmcc-cd. This patch fixes the typo and renames the pin to sdmmc-cd. Signed-off-by: Matthias Brugger Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3368.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/rockchip/rk3368.dtsi b/arch/arm64/boot/dts/rockchip/rk3368.dtsi index 61ca1abde947..d8ccb17b9da0 100644 --- a/arch/arm64/boot/dts/rockchip/rk3368.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3368.dtsi @@ -849,7 +849,7 @@ rockchip,pins = <2 10 RK_FUNC_1 &pcfg_pull_up>; }; - sdmmc_cd: sdmcc-cd { + sdmmc_cd: sdmmc-cd { rockchip,pins = <2 11 RK_FUNC_1 &pcfg_pull_up>; }; -- cgit v1.2.3-59-g8ed1b From b8084e5b34e83875846053bf9cd951b7640e40fe Mon Sep 17 00:00:00 2001 From: Caesar Wang Date: Fri, 25 Sep 2015 10:14:58 +0800 Subject: arm64: dts: rockchip: Add the broadcast-timer for RK3368 SoC There is a need of a broadcast timer in this case to ensure proper wakeup when the cpus are in sleep mode and a timer expires. Signed-off-by: Caesar Wang Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3368.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/rockchip/rk3368.dtsi b/arch/arm64/boot/dts/rockchip/rk3368.dtsi index d8ccb17b9da0..122777b1441e 100644 --- a/arch/arm64/boot/dts/rockchip/rk3368.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3368.dtsi @@ -579,6 +579,12 @@ status = "disabled"; }; + timer@ff810000 { + compatible = "rockchip,rk3368-timer", "rockchip,rk3288-timer"; + reg = <0x0 0xff810000 0x0 0x20>; + interrupts = ; + }; + gic: interrupt-controller@ffb71000 { compatible = "arm,gic-400"; interrupt-controller; -- cgit v1.2.3-59-g8ed1b From bdd5739008617c594ac231b1427d23f2c9000fcd Mon Sep 17 00:00:00 2001 From: Soren Brinkmann Date: Fri, 23 Oct 2015 09:25:32 -0700 Subject: ARM64: zynqmp: DT: Add interrupt-controller property to GPIO GPIO can be used as interrupt-controller. Add the missing properties to the GPIO node. Signed-off-by: Soren Brinkmann Signed-off-by: Michal Simek --- arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi index 857eda5c7217..200fb588d0f5 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi @@ -133,6 +133,8 @@ clocks = <&misc_clk>; interrupt-parent = <&gic>; interrupts = <0 16 4>; + interrupt-controller; + #interrupt-cells = <2>; reg = <0x0 0xff0a0000 0x1000>; }; -- cgit v1.2.3-59-g8ed1b From 503b01ec9b5f829c583e14dc5d8c5fda6ac8d915 Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Fri, 20 Nov 2015 15:31:17 -0800 Subject: arm64: dts: qcom: Make msm8916-mtp compatible string compliant This compatible string isn't compliant with the format for subtypes. Replace it with a compliant compatible type. Signed-off-by: Stephen Boyd Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/msm8916-mtp.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/msm8916-mtp.dts b/arch/arm64/boot/dts/qcom/msm8916-mtp.dts index fced77f0fd3a..b0a064d3806b 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-mtp.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-mtp.dts @@ -17,6 +17,6 @@ / { model = "Qualcomm Technologies, Inc. MSM 8916 MTP"; - compatible = "qcom,msm8916-mtp", "qcom,msm8916-mtp-smb1360", + compatible = "qcom,msm8916-mtp", "qcom,msm8916-mtp/1", "qcom,msm8916", "qcom,mtp"; }; -- cgit v1.2.3-59-g8ed1b From 2bce84c1a0c3ff04d29e6ef02823074588e90aa1 Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Fri, 20 Nov 2015 15:31:19 -0800 Subject: arm64: dts: qcom: Alias pm8916 on msm8916 devices Add an alias for pm8916 on msm8916 based SoCs so that the newly updated dtbTool can find the pmic compatible string and add the pmic-id element to the QCDT header. Signed-off-by: Stephen Boyd Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi | 1 + arch/arm64/boot/dts/qcom/msm8916-mtp.dtsi | 1 + arch/arm64/boot/dts/qcom/pm8916.dtsi | 6 +++--- 3 files changed, 5 insertions(+), 3 deletions(-) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi index 6b8abbe68746..46bfcb9b2e84 100644 --- a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi +++ b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi @@ -20,6 +20,7 @@ aliases { serial0 = &blsp1_uart2; serial1 = &blsp1_uart1; + usid0 = &pm8916_0; }; chosen { diff --git a/arch/arm64/boot/dts/qcom/msm8916-mtp.dtsi b/arch/arm64/boot/dts/qcom/msm8916-mtp.dtsi index a1aa0b201e92..ceeb8a6feed6 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-mtp.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-mtp.dtsi @@ -17,6 +17,7 @@ / { aliases { serial0 = &blsp1_uart2; + usid0 = &pm8916_0; }; chosen { diff --git a/arch/arm64/boot/dts/qcom/pm8916.dtsi b/arch/arm64/boot/dts/qcom/pm8916.dtsi index b222ece7e3d2..37432451ee4c 100644 --- a/arch/arm64/boot/dts/qcom/pm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8916.dtsi @@ -4,8 +4,8 @@ &spmi_bus { - usid0: pm8916@0 { - compatible = "qcom,spmi-pmic"; + pm8916_0: pm8916@0 { + compatible = "qcom,pm8916", "qcom,spmi-pmic"; reg = <0x0 SPMI_USID>; #address-cells = <1>; #size-cells = <0>; @@ -90,7 +90,7 @@ }; }; - usid1: pm8916@1 { + pm8916_1: pm8916@1 { compatible = "qcom,spmi-pmic"; reg = <0x1 SPMI_USID>; #address-cells = <1>; -- cgit v1.2.3-59-g8ed1b From f4fb6aeafaaa1c795f4ada9388051295830460c7 Mon Sep 17 00:00:00 2001 From: Georgi Djakov Date: Thu, 3 Dec 2015 16:02:52 +0200 Subject: arm64: dts: qcom: msm8916: Add fixed rate on-board oscillators Currently the rates of the xo and sleep clocks are hard-coded in the GCC driver, but this is a board layout description that actually should be in the DT. Moving them into DT also allows us to insert the RPM controlled clocks between the DT and GCC clocks. Signed-off-by: Georgi Djakov Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/msm8916.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index 82881948aaeb..f9844097640d 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -74,6 +74,20 @@ ; }; + clocks { + xo_board: xo_board { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <19200000>; + }; + + sleep_clk: sleep_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + }; + soc: soc { #address-cells = <1>; #size-cells = <1>; -- cgit v1.2.3-59-g8ed1b From b98e6c76586e92c407cd543f5a9b4efe802117d7 Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Fri, 11 Dec 2015 18:12:50 +0000 Subject: arm64: dts: fix the i2c aliasing to match to schematics. This patch fixes the i2c bus number aliasing so that it matches with the schematics bus naming. Without this patch the user might would get bus numbers depending on the order the devices are probed. Signed-off-by: Srinivas Kandagatla Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi | 3 +++ 1 file changed, 3 insertions(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi index 46bfcb9b2e84..0f775d7bba6d 100644 --- a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi +++ b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi @@ -21,6 +21,9 @@ serial0 = &blsp1_uart2; serial1 = &blsp1_uart1; usid0 = &pm8916_0; + i2c0 = &blsp_i2c2; + i2c1 = &blsp_i2c6; + i2c3 = &blsp_i2c4; }; chosen { -- cgit v1.2.3-59-g8ed1b From c240f29e75e686baa5b5ddc801e70022dd6bf358 Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Fri, 11 Dec 2015 18:13:12 +0000 Subject: arm64: dts: set the default i2c pin drive strength to 16mA 2mA drive strength is not enough when we connect multiple i2c devices on the bus with different pull up resistors. This issue was detected when multiple i2c devices connected on the other side of level shifters on Linaro sensor board. Maxing up to 16mA made i2c much stable. Signed-off-by: Srinivas Kandagatla Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/msm8916-pins.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi b/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi index d656e892fd52..955c6f174d4c 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi @@ -277,7 +277,7 @@ }; pinconf { pins = "gpio6", "gpio7"; - drive-strength = <2>; + drive-strength = <16>; bias-disable = <0>; }; }; @@ -301,7 +301,7 @@ }; pinconf { pins = "gpio14", "gpio15"; - drive-strength = <2>; + drive-strength = <16>; bias-disable = <0>; }; }; @@ -325,7 +325,7 @@ }; pinconf { pins = "gpio22", "gpio23"; - drive-strength = <2>; + drive-strength = <16>; bias-disable = <0>; }; }; -- cgit v1.2.3-59-g8ed1b From a0ece65777c35bf1e69fafbbf2be9566eca070c1 Mon Sep 17 00:00:00 2001 From: Andy Gross Date: Thu, 24 Sep 2015 14:18:52 -0500 Subject: arm64: dts: qcom: Add MSM8916 SMEM nodes This patch adds the nodes necessary to support the SMEM driver on MSM8916 platforms. Signed-off-by: Andy Gross Acked-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8916.dtsi | 41 +++++++++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index f9844097640d..058e3551d581 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -37,6 +37,22 @@ reg = <0 0 0 0>; }; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + reserve_aligned@86000000 { + reg = <0x0 0x86000000 0x0 0x0300000>; + no-map; + }; + + smem_mem: smem_region@86300000 { + reg = <0x0 0x86300000 0x0 0x0100000>; + no-map; + }; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -88,6 +104,15 @@ }; }; + smem { + compatible = "qcom,smem"; + + memory-region = <&smem_mem>; + qcom,rpm-msg-ram = <&rpm_msg_ram>; + + hwlocks = <&tcsr_mutex 3>; + }; + soc: soc { #address-cells = <1>; #size-cells = <1>; @@ -117,6 +142,22 @@ reg = <0x1800000 0x80000>; }; + tcsr_mutex_regs: syscon@1905000 { + compatible = "syscon"; + reg = <0x1905000 0x20000>; + }; + + tcsr_mutex: hwlock { + compatible = "qcom,tcsr-mutex"; + syscon = <&tcsr_mutex_regs 0 0x1000>; + #hwlock-cells = <1>; + }; + + rpm_msg_ram: memory@60000 { + compatible = "qcom,rpm-msg-ram"; + reg = <0x60000 0x8000>; + }; + blsp1_uart1: serial@78af000 { compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; reg = <0x78af000 0x200>; -- cgit v1.2.3-59-g8ed1b From 8fd55d41cabb2db4adf659316456d014a8c3e77f Mon Sep 17 00:00:00 2001 From: Andy Gross Date: Thu, 24 Sep 2015 14:18:53 -0500 Subject: arm64: dts: qcom: Add RPM/SMD support on MSM8916 Add support for the SMD and RPM devices found on MSM8916 platforms. Signed-off-by: Andy Gross Acked-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8916.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index 058e3551d581..fc6e8d60b736 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -169,6 +169,11 @@ status = "disabled"; }; + apcs: syscon@b011000 { + compatible = "syscon"; + reg = <0x0b011000 0x1000>; + }; + blsp1_uart2: serial@78b0000 { compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; reg = <0x78b0000 0x200>; @@ -497,6 +502,21 @@ clock-names = "core"; }; }; + + smd { + compatible = "qcom,smd"; + + rpm { + interrupts = ; + qcom,ipc = <&apcs 8 0>; + qcom,smd-edge = <15>; + + rpm_requests { + compatible = "qcom,rpm-msm8916"; + qcom,smd-channels = "rpm_requests"; + }; + }; + }; }; #include "msm8916-pins.dtsi" -- cgit v1.2.3-59-g8ed1b From 9e1dfb858de43bb3dfbbb32cec57433e9b250dee Mon Sep 17 00:00:00 2001 From: Andy Gross Date: Thu, 24 Sep 2015 14:18:54 -0500 Subject: arm64: dts: Add PM8916 support on MSM8916 This patch adds the PM8916 regulator nodes found on MSM8916 platforms. Signed-off-by: Andy Gross Acked-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8916.dtsi | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index fc6e8d60b736..915321479998 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -514,6 +514,34 @@ rpm_requests { compatible = "qcom,rpm-msm8916"; qcom,smd-channels = "rpm_requests"; + + pm8916-regulators { + compatible = "qcom,rpm-pm8916-regulators"; + + pm8916_s1: s1 {}; + pm8916_s2: s2 {}; + pm8916_s3: s3 {}; + pm8916_s4: s4 {}; + + pm8916_l1: l1 {}; + pm8916_l2: l2 {}; + pm8916_l3: l3 {}; + pm8916_l4: l4 {}; + pm8916_l5: l5 {}; + pm8916_l6: l6 {}; + pm8916_l7: l7 {}; + pm8916_l8: l8 {}; + pm8916_l9: l9 {}; + pm8916_l10: l10 {}; + pm8916_l11: l11 {}; + pm8916_l12: l12 {}; + pm8916_l13: l13 {}; + pm8916_l14: l14 {}; + pm8916_l15: l15 {}; + pm8916_l16: l16 {}; + pm8916_l17: l17 {}; + pm8916_l18: l18 {}; + }; }; }; }; -- cgit v1.2.3-59-g8ed1b From 12e5155783bfdd50d93f9868b2209db190df8b68 Mon Sep 17 00:00:00 2001 From: Gaku Inami Date: Fri, 4 Dec 2015 14:38:51 +0100 Subject: arm64: dts: r8a7795: Add PSCI node Add PSCI node for r8a7795 SoC, and cpu node enable-method property is set to "psci". Signed-off-by: Gaku Inami Signed-off-by: Takeshi Kihara Signed-off-by: Dirk Behme Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a7795.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi index b1902ea1dae4..051ff143506e 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi @@ -26,6 +26,11 @@ i2c6 = &i2c6; }; + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -35,6 +40,7 @@ compatible = "arm,cortex-a57", "arm,armv8"; reg = <0x0>; device_type = "cpu"; + enable-method = "psci"; }; }; -- cgit v1.2.3-59-g8ed1b From 0ed1a79ed0c17631fb41d336a4eddb9bbd299b64 Mon Sep 17 00:00:00 2001 From: Gaku Inami Date: Fri, 4 Dec 2015 14:38:52 +0100 Subject: arm64: dts: r8a7795: Add Cortex-A57 CPU cores Add Cortex-A57 CPU cores to r8a7795 SoC for a total of 4 x Cortex-A57. Signed-off-by: Gaku Inami Signed-off-by: Takeshi Kihara Sigend-off-by: Dirk Behme Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a7795.dtsi | 31 +++++++++++++++++++++++++------ 1 file changed, 25 insertions(+), 6 deletions(-) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi index 051ff143506e..4d43cf31418f 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi @@ -35,13 +35,31 @@ #address-cells = <1>; #size-cells = <0>; - /* 1 core only at this point */ a57_0: cpu@0 { compatible = "arm,cortex-a57", "arm,armv8"; reg = <0x0>; device_type = "cpu"; enable-method = "psci"; }; + + a57_1: cpu@1 { + compatible = "arm,cortex-a57","arm,armv8"; + reg = <0x1>; + device_type = "cpu"; + enable-method = "psci"; + }; + a57_2: cpu@2 { + compatible = "arm,cortex-a57","arm,armv8"; + reg = <0x2>; + device_type = "cpu"; + enable-method = "psci"; + }; + a57_3: cpu@3 { + compatible = "arm,cortex-a57","arm,armv8"; + reg = <0x3>; + device_type = "cpu"; + enable-method = "psci"; + }; }; extal_clk: extal { @@ -84,6 +102,7 @@ soc { compatible = "simple-bus"; interrupt-parent = <&gic>; + #address-cells = <2>; #size-cells = <2>; ranges; @@ -96,7 +115,7 @@ reg = <0x0 0xf1010000 0 0x1000>, <0x0 0xf1020000 0 0x2000>; interrupts = ; + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; }; gpio0: gpio@e6050000 { @@ -214,13 +233,13 @@ timer { compatible = "arm,armv8-timer"; interrupts = , + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, , + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, , + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, ; + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; }; cpg: clock-controller@e6150000 { -- cgit v1.2.3-59-g8ed1b From a6b6b478459be0c5614626ba6ac95df05a7fc5e9 Mon Sep 17 00:00:00 2001 From: Yoshifumi Hosoya Date: Fri, 4 Dec 2015 14:38:53 +0100 Subject: arm64: dts: r8a7795: Add pmu device nodes Enabling the performance monitor unit on r8a7795. Signed-off-by: Masaru Nagai Signed-off-by: Yoshifumi Hosoya Signed-off-by: Dirk Behme Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a7795.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi index 4d43cf31418f..b9229a49dabc 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi @@ -230,6 +230,18 @@ power-domains = <&cpg>; }; + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = , + , + , + ; + interrupt-affinity = <&a57_0>, + <&a57_1>, + <&a57_2>, + <&a57_3>; + }; + timer { compatible = "arm,armv8-timer"; interrupts = Date: Tue, 8 Dec 2015 10:37:53 +0100 Subject: arm64: renesas: r8a7795: add internal delay for i2c IPs Signed-off-by: Wolfram Sang Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a7795.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi index b9229a49dabc..e14251164480 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi @@ -526,6 +526,7 @@ interrupts = ; clocks = <&cpg CPG_MOD 931>; power-domains = <&cpg>; + i2c-scl-internal-delay-ns = <110>; status = "disabled"; }; @@ -537,6 +538,7 @@ interrupts = ; clocks = <&cpg CPG_MOD 930>; power-domains = <&cpg>; + i2c-scl-internal-delay-ns = <6>; status = "disabled"; }; @@ -548,6 +550,7 @@ interrupts = ; clocks = <&cpg CPG_MOD 929>; power-domains = <&cpg>; + i2c-scl-internal-delay-ns = <6>; status = "disabled"; }; @@ -559,6 +562,7 @@ interrupts = ; clocks = <&cpg CPG_MOD 928>; power-domains = <&cpg>; + i2c-scl-internal-delay-ns = <110>; status = "disabled"; }; @@ -570,6 +574,7 @@ interrupts = ; clocks = <&cpg CPG_MOD 927>; power-domains = <&cpg>; + i2c-scl-internal-delay-ns = <110>; status = "disabled"; }; @@ -581,6 +586,7 @@ interrupts = ; clocks = <&cpg CPG_MOD 919>; power-domains = <&cpg>; + i2c-scl-internal-delay-ns = <110>; status = "disabled"; }; @@ -592,6 +598,7 @@ interrupts = ; clocks = <&cpg CPG_MOD 918>; power-domains = <&cpg>; + i2c-scl-internal-delay-ns = <6>; status = "disabled"; }; -- cgit v1.2.3-59-g8ed1b From 4c13472b8cc4a326041584b88c534663bb829102 Mon Sep 17 00:00:00 2001 From: Kouei Abe Date: Mon, 14 Dec 2015 16:42:34 +0100 Subject: arm64: dts: r8a7795: Add SATA controller node This adds SATA device node to r8a7795.dtsi. Signed-off-by: Kouei Abe [uli: adjusted for new MSTP clock scheme] Signed-off-by: Ulrich Hecht Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a7795.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi index e14251164480..9ce6a5ea6629 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi @@ -767,5 +767,13 @@ }; }; }; + + sata: sata@ee300000 { + compatible = "renesas,sata-r8a7795"; + reg = <0 0xee300000 0 0x1fff>; + interrupts = ; + clocks = <&cpg CPG_MOD 915>; + status = "disabled"; + }; }; }; -- cgit v1.2.3-59-g8ed1b From 52ee9fb34aa4b839b784e2e224a7c525cc51c955 Mon Sep 17 00:00:00 2001 From: Kouei Abe Date: Mon, 14 Dec 2015 16:42:35 +0100 Subject: arm64: dts: salvator-x: Enable SATA controller This enables SATA device in r8a7795-salvator-x.dts. Signed-off-by: Kouei Abe Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts index 75af5ec5a4d4..265d12ff6022 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts +++ b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts @@ -212,6 +212,10 @@ }; }; +&sata { + status = "okay"; +}; + &ssi1 { shared-pin; }; -- cgit v1.2.3-59-g8ed1b From 2eb2b5066197eab00c55dcd1132f17836e4975b2 Mon Sep 17 00:00:00 2001 From: Ulrich Hecht Date: Wed, 16 Dec 2015 11:34:21 +0100 Subject: arm64: renesas: r8a7795: fix SATA clock assignment SATA clock is 815, not 915. Signed-off-by: Ulrich Hecht Acked-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a7795.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi index 9ce6a5ea6629..bb353cde1253 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi @@ -772,7 +772,7 @@ compatible = "renesas,sata-r8a7795"; reg = <0 0xee300000 0 0x1fff>; interrupts = ; - clocks = <&cpg CPG_MOD 915>; + clocks = <&cpg CPG_MOD 815>; status = "disabled"; }; }; -- cgit v1.2.3-59-g8ed1b From e1a0ebc8d82b64440d3ca7eac6a8489937ee2519 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Sat, 28 Nov 2015 02:22:31 +0900 Subject: arm64: dts: uniphier: add PH1-LD10 SoC/board support This is the first ARMv8 SoC from Socionext Inc. Signed-off-by: Masahiro Yamada Signed-off-by: Olof Johansson --- MAINTAINERS | 1 + arch/arm64/boot/dts/Makefile | 1 + arch/arm64/boot/dts/socionext/Makefile | 4 + .../boot/dts/socionext/uniphier-ph1-ld10-ref.dts | 95 +++++++ .../boot/dts/socionext/uniphier-ph1-ld10.dtsi | 280 +++++++++++++++++++++ .../arm64/boot/dts/socionext/uniphier-pinctrl.dtsi | 1 + .../boot/dts/socionext/uniphier-support-card.dtsi | 1 + 7 files changed, 383 insertions(+) create mode 100644 arch/arm64/boot/dts/socionext/Makefile create mode 100644 arch/arm64/boot/dts/socionext/uniphier-ph1-ld10-ref.dts create mode 100644 arch/arm64/boot/dts/socionext/uniphier-ph1-ld10.dtsi create mode 120000 arch/arm64/boot/dts/socionext/uniphier-pinctrl.dtsi create mode 120000 arch/arm64/boot/dts/socionext/uniphier-support-card.dtsi (limited to 'arch/arm64/boot') diff --git a/MAINTAINERS b/MAINTAINERS index 6d16447fdfa8..04aacf80f23e 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1651,6 +1651,7 @@ F: arch/arm/boot/dts/uniphier* F: arch/arm/include/asm/hardware/cache-uniphier.h F: arch/arm/mach-uniphier/ F: arch/arm/mm/cache-uniphier.c +F: arch/arm64/boot/dts/socionext/ F: drivers/i2c/busses/i2c-uniphier* F: drivers/pinctrl/uniphier/ F: drivers/tty/serial/8250/8250_uniphier.c diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile index 0e775e4d6a00..76e7510835b2 100644 --- a/arch/arm64/boot/dts/Makefile +++ b/arch/arm64/boot/dts/Makefile @@ -12,6 +12,7 @@ dts-dirs += mediatek dts-dirs += qcom dts-dirs += renesas dts-dirs += rockchip +dts-dirs += socionext dts-dirs += sprd dts-dirs += xilinx diff --git a/arch/arm64/boot/dts/socionext/Makefile b/arch/arm64/boot/dts/socionext/Makefile new file mode 100644 index 000000000000..8d727717c24e --- /dev/null +++ b/arch/arm64/boot/dts/socionext/Makefile @@ -0,0 +1,4 @@ +dtb-$(CONFIG_ARCH_UNIPHIER) += uniphier-ph1-ld10-ref.dtb + +always := $(dtb-y) +clean-files := *.dtb diff --git a/arch/arm64/boot/dts/socionext/uniphier-ph1-ld10-ref.dts b/arch/arm64/boot/dts/socionext/uniphier-ph1-ld10-ref.dts new file mode 100644 index 000000000000..3e533178ba2f --- /dev/null +++ b/arch/arm64/boot/dts/socionext/uniphier-ph1-ld10-ref.dts @@ -0,0 +1,95 @@ +/* + * Device Tree Source for UniPhier PH1-LD10 Reference Board + * + * Copyright (C) 2015 Masahiro Yamada + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +/include/ "uniphier-ph1-ld10.dtsi" +/include/ "uniphier-support-card.dtsi" + +/ { + model = "UniPhier PH1-LD10 Reference Board"; + compatible = "socionext,ph1-ld10-ref", "socionext,ph1-ld10"; + + memory { + device_type = "memory"; + reg = <0 0x80000000 0 0xc0000000>; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + aliases { + serial0 = &serial0; + serial1 = &serial1; + serial2 = &serial2; + serial3 = &serial3; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c5; + i2c6 = &i2c6; + }; +}; + +&extbus { + ranges = <1 0x00000000 0x42000000 0x02000000>; +}; + +&support_card { + ranges = <0x00000000 1 0x01f00000 0x00100000>; +}; + +ðsc { + interrupts = <0 48 4>; +}; + +&serial0 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/socionext/uniphier-ph1-ld10.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ph1-ld10.dtsi new file mode 100644 index 000000000000..0296af9cbbdb --- /dev/null +++ b/arch/arm64/boot/dts/socionext/uniphier-ph1-ld10.dtsi @@ -0,0 +1,280 @@ +/* + * Device Tree Source for UniPhier PH1-LD10 SoC + * + * Copyright (C) 2015 Masahiro Yamada + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/ { + compatible = "socionext,ph1-ld10"; + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&gic>; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + core1 { + cpu = <&cpu1>; + }; + }; + + cluster1 { + core0 { + cpu = <&cpu2>; + }; + core1 { + cpu = <&cpu3>; + }; + }; + }; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0 0x000>; + enable-method = "spin-table"; + cpu-release-addr = <0 0x80000100>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0 0x001>; + enable-method = "spin-table"; + cpu-release-addr = <0 0x80000100>; + }; + + cpu2: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0 0x100>; + enable-method = "spin-table"; + cpu-release-addr = <0 0x80000100>; + }; + + cpu3: cpu@101 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0 0x101>; + enable-method = "spin-table"; + cpu-release-addr = <0 0x80000100>; + }; + }; + + clocks { + uart_clk: uart_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <58820000>; + }; + + i2c_clk: i2c_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <50000000>; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <1 13 0xf01>, + <1 14 0xf01>, + <1 11 0xf01>, + <1 10 0xf01>; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0xffffffff>; + + extbus: extbus { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <1>; + }; + + serial0: serial@54006800 { + compatible = "socionext,uniphier-uart"; + status = "disabled"; + reg = <0x54006800 0x40>; + interrupts = <0 33 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart0>; + clocks = <&uart_clk>; + }; + + serial1: serial@54006900 { + compatible = "socionext,uniphier-uart"; + status = "disabled"; + reg = <0x54006900 0x40>; + interrupts = <0 35 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + clocks = <&uart_clk>; + }; + + serial2: serial@54006a00 { + compatible = "socionext,uniphier-uart"; + status = "disabled"; + reg = <0x54006a00 0x40>; + interrupts = <0 37 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + clocks = <&uart_clk>; + }; + + serial3: serial@54006b00 { + compatible = "socionext,uniphier-uart"; + status = "disabled"; + reg = <0x54006b00 0x40>; + interrupts = <0 177 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + clocks = <&uart_clk>; + }; + + i2c0: i2c@58780000 { + compatible = "socionext,uniphier-fi2c"; + status = "disabled"; + reg = <0x58780000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 41 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0>; + clocks = <&i2c_clk>; + clock-frequency = <100000>; + }; + + i2c1: i2c@58781000 { + compatible = "socionext,uniphier-fi2c"; + status = "disabled"; + reg = <0x58781000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 42 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + clocks = <&i2c_clk>; + clock-frequency = <100000>; + }; + + i2c2: i2c@58782000 { + compatible = "socionext,uniphier-fi2c"; + status = "disabled"; + reg = <0x58782000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 43 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + clocks = <&i2c_clk>; + clock-frequency = <100000>; + }; + + i2c3: i2c@58783000 { + compatible = "socionext,uniphier-fi2c"; + status = "disabled"; + reg = <0x58783000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 44 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + clocks = <&i2c_clk>; + clock-frequency = <100000>; + }; + + i2c4: i2c@58784000 { + compatible = "socionext,uniphier-fi2c"; + reg = <0x58784000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 45 4>; + clocks = <&i2c_clk>; + clock-frequency = <400000>; + }; + + i2c5: i2c@58785000 { + compatible = "socionext,uniphier-fi2c"; + reg = <0x58785000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 25 4>; + clocks = <&i2c_clk>; + clock-frequency = <400000>; + }; + + i2c6: i2c@58786000 { + compatible = "socionext,uniphier-fi2c"; + reg = <0x58786000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 26 4>; + clocks = <&i2c_clk>; + clock-frequency = <400000>; + }; + + pinctrl: pinctrl@5f801000 { + compatible = "socionext,ph1-ld10-pinctrl", "syscon"; + reg = <0x5f801000 0xe00>; + }; + + gic: interrupt-controller@5fe00000 { + compatible = "arm,gic-v3"; + reg = <0x5fe00000 0x10000>, /* GICD */ + <0x5fe80000 0x80000>; /* GICR */ + interrupt-controller; + #interrupt-cells = <3>; + interrupts = <1 9 4>; + }; + }; +}; + +/include/ "uniphier-pinctrl.dtsi" diff --git a/arch/arm64/boot/dts/socionext/uniphier-pinctrl.dtsi b/arch/arm64/boot/dts/socionext/uniphier-pinctrl.dtsi new file mode 120000 index 000000000000..f42fb6f38bd3 --- /dev/null +++ b/arch/arm64/boot/dts/socionext/uniphier-pinctrl.dtsi @@ -0,0 +1 @@ +../../../../arm/boot/dts/uniphier-pinctrl.dtsi \ No newline at end of file diff --git a/arch/arm64/boot/dts/socionext/uniphier-support-card.dtsi b/arch/arm64/boot/dts/socionext/uniphier-support-card.dtsi new file mode 120000 index 000000000000..1246db9be2a1 --- /dev/null +++ b/arch/arm64/boot/dts/socionext/uniphier-support-card.dtsi @@ -0,0 +1 @@ +../../../../arm/boot/dts/uniphier-support-card.dtsi \ No newline at end of file -- cgit v1.2.3-59-g8ed1b From 6d453cd22357f19ae04fa9f65a90f7f23117f2aa Mon Sep 17 00:00:00 2001 From: Mingkai Hu Date: Fri, 4 Dec 2015 16:56:02 -0600 Subject: arm64: dts: add Freescale LS1043a SoC support LS1043a is an SoC with 4 ARMv8 A53 cores and most other IP blocks are similar to LS1021a which also complies to Freescale Chassis 2.1 spec. Created LS1043a SoC DTSI file to be included by board level DTS files. Signed-off-by: Li Yang Signed-off-by: Hou Zhiqiang Signed-off-by: Mingkai Hu Signed-off-by: Wenbin Song Signed-off-by: Olof Johansson --- arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 527 +++++++++++++++++++++++++ 1 file changed, 527 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi new file mode 100644 index 000000000000..42a61549afd4 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi @@ -0,0 +1,527 @@ +/* + * Device Tree Include file for Freescale Layerscape-1043A family SoC. + * + * Copyright 2014-2015, Freescale Semiconductor + * + * Mingkai Hu + * + * This file is dual-licensed: you can use it either under the terms + * of the GPLv2 or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/ { + compatible = "fsl,ls1043a"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + /* + * We expect the enable-method for cpu's to be "psci", but this + * is dependent on the SoC FW, which will fill this in. + * + * Currently supported enable-method is psci v0.2 + */ + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x0>; + clocks = <&clockgen 1 0>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x1>; + clocks = <&clockgen 1 0>; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x2>; + clocks = <&clockgen 1 0>; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x3>; + clocks = <&clockgen 1 0>; + }; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0 0x80000000>; + /* DRAM space 1, size: 2GiB DRAM */ + }; + + sysclk: sysclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + clock-output-names = "sysclk"; + }; + + reboot { + compatible ="syscon-reboot"; + regmap = <&dcfg>; + offset = <0xb0>; + mask = <0x02>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <1 13 0x1>, /* Physical Secure PPI */ + <1 14 0x1>, /* Physical Non-Secure PPI */ + <1 11 0x1>, /* Virtual PPI */ + <1 10 0x1>; /* Hypervisor PPI */ + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = <0 106 0x4>, + <0 107 0x4>, + <0 95 0x4>, + <0 97 0x4>; + interrupt-affinity = <&cpu0>, + <&cpu1>, + <&cpu2>, + <&cpu3>; + }; + + gic: interrupt-controller@1400000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x0 0x1401000 0 0x1000>, /* GICD */ + <0x0 0x1402000 0 0x2000>, /* GICC */ + <0x0 0x1404000 0 0x2000>, /* GICH */ + <0x0 0x1406000 0 0x2000>; /* GICV */ + interrupts = <1 9 0xf08>; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + clockgen: clocking@1ee1000 { + compatible = "fsl,ls1043a-clockgen"; + reg = <0x0 0x1ee1000 0x0 0x1000>; + #clock-cells = <2>; + clocks = <&sysclk>; + }; + + scfg: scfg@1570000 { + compatible = "fsl,ls1043a-scfg", "syscon"; + reg = <0x0 0x1570000 0x0 0x10000>; + big-endian; + }; + + dcfg: dcfg@1ee0000 { + compatible = "fsl,ls1043a-dcfg", "syscon"; + reg = <0x0 0x1ee0000 0x0 0x10000>; + big-endian; + }; + + ifc: ifc@1530000 { + compatible = "fsl,ifc", "simple-bus"; + reg = <0x0 0x1530000 0x0 0x10000>; + interrupts = <0 43 0x4>; + }; + + esdhc: esdhc@1560000 { + compatible = "fsl,ls1043a-esdhc", "fsl,esdhc"; + reg = <0x0 0x1560000 0x0 0x10000>; + interrupts = <0 62 0x4>; + clock-frequency = <0>; + voltage-ranges = <1800 1800 3300 3300>; + sdhci,auto-cmd12; + big-endian; + bus-width = <4>; + }; + + dspi0: dspi@2100000 { + compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2100000 0x0 0x10000>; + interrupts = <0 64 0x4>; + clock-names = "dspi"; + clocks = <&clockgen 4 0>; + spi-num-chipselects = <5>; + big-endian; + status = "disabled"; + }; + + dspi1: dspi@2110000 { + compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2110000 0x0 0x10000>; + interrupts = <0 65 0x4>; + clock-names = "dspi"; + clocks = <&clockgen 4 0>; + spi-num-chipselects = <5>; + big-endian; + status = "disabled"; + }; + + i2c0: i2c@2180000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2180000 0x0 0x10000>; + interrupts = <0 56 0x4>; + clock-names = "i2c"; + clocks = <&clockgen 4 0>; + dmas = <&edma0 1 39>, + <&edma0 1 38>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + i2c1: i2c@2190000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2190000 0x0 0x10000>; + interrupts = <0 57 0x4>; + clock-names = "i2c"; + clocks = <&clockgen 4 0>; + status = "disabled"; + }; + + i2c2: i2c@21a0000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x21a0000 0x0 0x10000>; + interrupts = <0 58 0x4>; + clock-names = "i2c"; + clocks = <&clockgen 4 0>; + status = "disabled"; + }; + + i2c3: i2c@21b0000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x21b0000 0x0 0x10000>; + interrupts = <0 59 0x4>; + clock-names = "i2c"; + clocks = <&clockgen 4 0>; + status = "disabled"; + }; + + duart0: serial@21c0500 { + compatible = "fsl,ns16550", "ns16550a"; + reg = <0x00 0x21c0500 0x0 0x100>; + interrupts = <0 54 0x4>; + clocks = <&clockgen 4 0>; + }; + + duart1: serial@21c0600 { + compatible = "fsl,ns16550", "ns16550a"; + reg = <0x00 0x21c0600 0x0 0x100>; + interrupts = <0 54 0x4>; + clocks = <&clockgen 4 0>; + }; + + duart2: serial@21d0500 { + compatible = "fsl,ns16550", "ns16550a"; + reg = <0x0 0x21d0500 0x0 0x100>; + interrupts = <0 55 0x4>; + clocks = <&clockgen 4 0>; + }; + + duart3: serial@21d0600 { + compatible = "fsl,ns16550", "ns16550a"; + reg = <0x0 0x21d0600 0x0 0x100>; + interrupts = <0 55 0x4>; + clocks = <&clockgen 4 0>; + }; + + gpio1: gpio@2300000 { + compatible = "fsl,ls1043a-gpio"; + reg = <0x0 0x2300000 0x0 0x10000>; + interrupts = <0 66 0x4>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio@2310000 { + compatible = "fsl,ls1043a-gpio"; + reg = <0x0 0x2310000 0x0 0x10000>; + interrupts = <0 67 0x4>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio@2320000 { + compatible = "fsl,ls1043a-gpio"; + reg = <0x0 0x2320000 0x0 0x10000>; + interrupts = <0 68 0x4>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio4: gpio@2330000 { + compatible = "fsl,ls1043a-gpio"; + reg = <0x0 0x2330000 0x0 0x10000>; + interrupts = <0 134 0x4>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + lpuart0: serial@2950000 { + compatible = "fsl,ls1021a-lpuart"; + reg = <0x0 0x2950000 0x0 0x1000>; + interrupts = <0 48 0x4>; + clocks = <&clockgen 0 0>; + clock-names = "ipg"; + status = "disabled"; + }; + + lpuart1: serial@2960000 { + compatible = "fsl,ls1021a-lpuart"; + reg = <0x0 0x2960000 0x0 0x1000>; + interrupts = <0 49 0x4>; + clocks = <&clockgen 4 0>; + clock-names = "ipg"; + status = "disabled"; + }; + + lpuart2: serial@2970000 { + compatible = "fsl,ls1021a-lpuart"; + reg = <0x0 0x2970000 0x0 0x1000>; + interrupts = <0 50 0x4>; + clocks = <&clockgen 4 0>; + clock-names = "ipg"; + status = "disabled"; + }; + + lpuart3: serial@2980000 { + compatible = "fsl,ls1021a-lpuart"; + reg = <0x0 0x2980000 0x0 0x1000>; + interrupts = <0 51 0x4>; + clocks = <&clockgen 4 0>; + clock-names = "ipg"; + status = "disabled"; + }; + + lpuart4: serial@2990000 { + compatible = "fsl,ls1021a-lpuart"; + reg = <0x0 0x2990000 0x0 0x1000>; + interrupts = <0 52 0x4>; + clocks = <&clockgen 4 0>; + clock-names = "ipg"; + status = "disabled"; + }; + + lpuart5: serial@29a0000 { + compatible = "fsl,ls1021a-lpuart"; + reg = <0x0 0x29a0000 0x0 0x1000>; + interrupts = <0 53 0x4>; + clocks = <&clockgen 4 0>; + clock-names = "ipg"; + status = "disabled"; + }; + + wdog0: wdog@2ad0000 { + compatible = "fsl,ls1043a-wdt", "fsl,imx21-wdt"; + reg = <0x0 0x2ad0000 0x0 0x10000>; + interrupts = <0 83 0x4>; + clocks = <&clockgen 4 0>; + clock-names = "wdog"; + big-endian; + }; + + edma0: edma@2c00000 { + #dma-cells = <2>; + compatible = "fsl,vf610-edma"; + reg = <0x0 0x2c00000 0x0 0x10000>, + <0x0 0x2c10000 0x0 0x10000>, + <0x0 0x2c20000 0x0 0x10000>; + interrupts = <0 103 0x4>, + <0 103 0x4>; + interrupt-names = "edma-tx", "edma-err"; + dma-channels = <32>; + big-endian; + clock-names = "dmamux0", "dmamux1"; + clocks = <&clockgen 4 0>, + <&clockgen 4 0>; + }; + + usb0: usb3@2f00000 { + compatible = "snps,dwc3"; + reg = <0x0 0x2f00000 0x0 0x10000>; + interrupts = <0 60 0x4>; + dr_mode = "host"; + }; + + usb1: usb3@3000000 { + compatible = "snps,dwc3"; + reg = <0x0 0x3000000 0x0 0x10000>; + interrupts = <0 61 0x4>; + dr_mode = "host"; + }; + + usb2: usb3@3100000 { + compatible = "snps,dwc3"; + reg = <0x0 0x3100000 0x0 0x10000>; + interrupts = <0 63 0x4>; + dr_mode = "host"; + }; + + sata: sata@3200000 { + compatible = "fsl,ls1043a-ahci", "fsl,ls1021a-ahci"; + reg = <0x0 0x3200000 0x0 0x10000>; + interrupts = <0 69 0x4>; + clocks = <&clockgen 4 0>; + }; + + msi1: msi-controller1@1571000 { + compatible = "fsl,1s1043a-msi"; + reg = <0x0 0x1571000 0x0 0x8>; + msi-controller; + interrupts = <0 116 0x4>; + }; + + msi2: msi-controller2@1572000 { + compatible = "fsl,1s1043a-msi"; + reg = <0x0 0x1572000 0x0 0x8>; + msi-controller; + interrupts = <0 126 0x4>; + }; + + msi3: msi-controller3@1573000 { + compatible = "fsl,1s1043a-msi"; + reg = <0x0 0x1573000 0x0 0x8>; + msi-controller; + interrupts = <0 160 0x4>; + }; + + pcie@3400000 { + compatible = "fsl,ls1043a-pcie", "snps,dw-pcie"; + reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ + 0x40 0x00000000 0x0 0x00002000>; /* configuration space */ + reg-names = "regs", "config"; + interrupts = <0 118 0x4>, /* controller interrupt */ + <0 117 0x4>; /* PME interrupt */ + interrupt-names = "intr", "pme"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + num-lanes = <4>; + bus-range = <0x0 0xff>; + ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */ + 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ + msi-parent = <&msi1>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0000 0 0 1 &gic 0 110 0x4>, + <0000 0 0 2 &gic 0 111 0x4>, + <0000 0 0 3 &gic 0 112 0x4>, + <0000 0 0 4 &gic 0 113 0x4>; + }; + + pcie@3500000 { + compatible = "fsl,ls1043a-pcie", "snps,dw-pcie"; + reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */ + 0x48 0x00000000 0x0 0x00002000>; /* configuration space */ + reg-names = "regs", "config"; + interrupts = <0 128 0x4>, + <0 127 0x4>; + interrupt-names = "intr", "pme"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + num-lanes = <2>; + bus-range = <0x0 0xff>; + ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */ + 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ + msi-parent = <&msi2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0000 0 0 1 &gic 0 120 0x4>, + <0000 0 0 2 &gic 0 121 0x4>, + <0000 0 0 3 &gic 0 122 0x4>, + <0000 0 0 4 &gic 0 123 0x4>; + }; + + pcie@3600000 { + compatible = "fsl,ls1043a-pcie", "snps,dw-pcie"; + reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */ + 0x50 0x00000000 0x0 0x00002000>; /* configuration space */ + reg-names = "regs", "config"; + interrupts = <0 162 0x4>, + <0 161 0x4>; + interrupt-names = "intr", "pme"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + num-lanes = <2>; + bus-range = <0x0 0xff>; + ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */ + 0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ + msi-parent = <&msi3>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0000 0 0 1 &gic 0 154 0x4>, + <0000 0 0 2 &gic 0 155 0x4>, + <0000 0 0 3 &gic 0 156 0x4>, + <0000 0 0 4 &gic 0 157 0x4>; + }; + }; + +}; -- cgit v1.2.3-59-g8ed1b From ac0ca416340c2940c022eb4ddc89ffe5746c0f01 Mon Sep 17 00:00:00 2001 From: Shaohui Xie Date: Fri, 4 Dec 2015 16:56:03 -0600 Subject: arm64: dts: add LS1043a-RDB board support Signed-off-by: Shaohui Xie Signed-off-by: Mingkai Hu Signed-off-by: Wenbin Song Signed-off-by: Hou Zhiqiang Signed-off-by: Li Yang Signed-off-by: Olof Johansson --- arch/arm64/boot/dts/freescale/Makefile | 1 + arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts | 116 ++++++++++++++++++++++ 2 files changed, 117 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index c4957a4aa5aa..f3c25165dad3 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -1,6 +1,7 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-qds.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-rdb.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-simu.dtb +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-rdb.dtb always := $(dtb-y) subdir-y := $(dts-dirs) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts new file mode 100644 index 000000000000..ce235577e90f --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts @@ -0,0 +1,116 @@ +/* + * Device Tree Include file for Freescale Layerscape-1043A family SoC. + * + * Copyright 2014-2015, Freescale Semiconductor + * + * Mingkai Hu + * + * This file is dual-licensed: you can use it either under the terms + * of the GPLv2 or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +/include/ "fsl-ls1043a.dtsi" + +/ { + model = "LS1043A RDB Board"; +}; + +&i2c0 { + status = "okay"; + ina220@40 { + compatible = "ti,ina220"; + reg = <0x40>; + shunt-resistor = <1000>; + }; + adt7461a@4c { + compatible = "adi,adt7461"; + reg = <0x4c>; + }; + eeprom@52 { + compatible = "at24,24c512"; + reg = <0x52>; + }; + eeprom@53 { + compatible = "at24,24c512"; + reg = <0x53>; + }; + rtc@68 { + compatible = "pericom,pt7c4338"; + reg = <0x68>; + }; +}; + +&ifc { + status = "okay"; + #address-cells = <2>; + #size-cells = <1>; + /* NOR, NAND Flashes and FPGA on board */ + ranges = <0x0 0x0 0x0 0x60000000 0x08000000 + 0x1 0x0 0x0 0x7e800000 0x00010000 + 0x2 0x0 0x0 0x7fb00000 0x00000100>; + + nor@0,0 { + compatible = "cfi-flash"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x0 0x0 0x8000000>; + bank-width = <2>; + device-width = <1>; + }; + + nand@1,0 { + compatible = "fsl,ifc-nand"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x1 0x0 0x10000>; + }; + + cpld: board-control@2,0 { + compatible = "fsl,ls1043ardb-cpld"; + reg = <0x2 0x0 0x0000100>; + }; +}; + +&duart0 { + status = "okay"; +}; + +&duart1 { + status = "okay"; +}; -- cgit v1.2.3-59-g8ed1b From c7a5675f525c668ec4dabd06705d5243f0d9da90 Mon Sep 17 00:00:00 2001 From: "J. German Rivera" Date: Fri, 4 Dec 2015 16:56:04 -0600 Subject: arm64: dts: Added syscon-reboot node for FSL's LS2080A SoC Added sys-reboot node to the FSL's LS2080A SoC DT to leverage the ARM-generic reboot mechanism for this SoC. This mechanism is enabled through CONFIG_POWER_RESET_SYSCON. Signed-off-by: J. German Rivera Signed-off-by: Li Yang Signed-off-by: Olof Johansson --- arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi index e81cd48d6245..65ac35f12fc4 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi @@ -153,6 +153,18 @@ }; }; + rstcr: syscon@1e60000 { + compatible = "fsl,ls2080a-rstcr", "syscon"; + reg = <0x0 0x1e60000 0x0 0x4>; + }; + + reboot { + compatible ="syscon-reboot"; + regmap = <&rstcr>; + offset = <0x0>; + mask = <0x2>; + }; + timer { compatible = "arm,armv8-timer"; interrupts = <1 13 0x8>, /* Physical Secure PPI, active-low */ -- cgit v1.2.3-59-g8ed1b From 28e10a8f3a03f39d087bb6180be2fb1f407664e5 Mon Sep 17 00:00:00 2001 From: "Jon Medhurst (Tixy)" Date: Wed, 9 Dec 2015 09:40:53 +0000 Subject: arm64: dts: juno: Add idle-states to device tree This patch adds idle-states bindings data collected through a set of benchmarking experiments (latency and energy consumption) on Juno boards. Latencies data represents the worst case scenarios as required by the DT idle-states bindings. Signed-off-by: Jon Medhurst Acked-by: Lorenzo Pieralisi Signed-off-by: Olof Johansson --- arch/arm64/boot/dts/arm/juno-r1.dts | 28 ++++++++++++++++++++++++++++ arch/arm64/boot/dts/arm/juno.dts | 28 ++++++++++++++++++++++++++++ 2 files changed, 56 insertions(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/arm/juno-r1.dts b/arch/arm64/boot/dts/arm/juno-r1.dts index 93bc3d7d51c0..8826f834f54f 100644 --- a/arch/arm64/boot/dts/arm/juno-r1.dts +++ b/arch/arm64/boot/dts/arm/juno-r1.dts @@ -60,6 +60,28 @@ }; }; + idle-states { + entry-method = "arm,psci"; + + CPU_SLEEP_0: cpu-sleep-0 { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x0010000>; + local-timer-stop; + entry-latency-us = <300>; + exit-latency-us = <1200>; + min-residency-us = <2000>; + }; + + CLUSTER_SLEEP_0: cluster-sleep-0 { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x1010000>; + local-timer-stop; + entry-latency-us = <300>; + exit-latency-us = <1200>; + min-residency-us = <2500>; + }; + }; + A57_0: cpu@0 { compatible = "arm,cortex-a57","arm,armv8"; reg = <0x0 0x0>; @@ -67,6 +89,7 @@ enable-method = "psci"; next-level-cache = <&A57_L2>; clocks = <&scpi_dvfs 0>; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; A57_1: cpu@1 { @@ -76,6 +99,7 @@ enable-method = "psci"; next-level-cache = <&A57_L2>; clocks = <&scpi_dvfs 0>; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; A53_0: cpu@100 { @@ -85,6 +109,7 @@ enable-method = "psci"; next-level-cache = <&A53_L2>; clocks = <&scpi_dvfs 1>; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; A53_1: cpu@101 { @@ -94,6 +119,7 @@ enable-method = "psci"; next-level-cache = <&A53_L2>; clocks = <&scpi_dvfs 1>; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; A53_2: cpu@102 { @@ -103,6 +129,7 @@ enable-method = "psci"; next-level-cache = <&A53_L2>; clocks = <&scpi_dvfs 1>; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; A53_3: cpu@103 { @@ -112,6 +139,7 @@ enable-method = "psci"; next-level-cache = <&A53_L2>; clocks = <&scpi_dvfs 1>; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; A57_L2: l2-cache0 { diff --git a/arch/arm64/boot/dts/arm/juno.dts b/arch/arm64/boot/dts/arm/juno.dts index 53442b5ee4ff..dcfcf15a17f5 100644 --- a/arch/arm64/boot/dts/arm/juno.dts +++ b/arch/arm64/boot/dts/arm/juno.dts @@ -60,6 +60,28 @@ }; }; + idle-states { + entry-method = "arm,psci"; + + CPU_SLEEP_0: cpu-sleep-0 { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x0010000>; + local-timer-stop; + entry-latency-us = <300>; + exit-latency-us = <1200>; + min-residency-us = <2000>; + }; + + CLUSTER_SLEEP_0: cluster-sleep-0 { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x1010000>; + local-timer-stop; + entry-latency-us = <300>; + exit-latency-us = <1200>; + min-residency-us = <2500>; + }; + }; + A57_0: cpu@0 { compatible = "arm,cortex-a57","arm,armv8"; reg = <0x0 0x0>; @@ -67,6 +89,7 @@ enable-method = "psci"; next-level-cache = <&A57_L2>; clocks = <&scpi_dvfs 0>; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; A57_1: cpu@1 { @@ -76,6 +99,7 @@ enable-method = "psci"; next-level-cache = <&A57_L2>; clocks = <&scpi_dvfs 0>; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; A53_0: cpu@100 { @@ -85,6 +109,7 @@ enable-method = "psci"; next-level-cache = <&A53_L2>; clocks = <&scpi_dvfs 1>; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; A53_1: cpu@101 { @@ -94,6 +119,7 @@ enable-method = "psci"; next-level-cache = <&A53_L2>; clocks = <&scpi_dvfs 1>; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; A53_2: cpu@102 { @@ -103,6 +129,7 @@ enable-method = "psci"; next-level-cache = <&A53_L2>; clocks = <&scpi_dvfs 1>; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; A53_3: cpu@103 { @@ -112,6 +139,7 @@ enable-method = "psci"; next-level-cache = <&A53_L2>; clocks = <&scpi_dvfs 1>; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; A57_L2: l2-cache0 { -- cgit v1.2.3-59-g8ed1b From 700dfee1901872625d0190e32dd8b1d0e29d0850 Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Thu, 10 Dec 2015 15:21:11 -0600 Subject: arm64: dts: apq8016-sbc: enable UART0 on LS connector The LS UART0 is not used by anything else and should be enabled for expansion boards. Signed-off-by: Rob Herring Cc: Srinivas Kandagatla Cc: Andy Gross Signed-off-by: Olof Johansson --- arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi index 6b8abbe68746..7505fa385ceb 100644 --- a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi +++ b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi @@ -27,6 +27,13 @@ }; soc { + serial@78af000 { + status = "okay"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&blsp1_uart1_default>; + pinctrl-1 = <&blsp1_uart1_sleep>; + }; + serial@78b0000 { status = "okay"; pinctrl-names = "default", "sleep"; -- cgit v1.2.3-59-g8ed1b From 262c45d43f425c7907a4c9857e7f37c82234a3be Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Thu, 10 Dec 2015 15:21:12 -0600 Subject: arm64: dts: apq8016-sbc: add label properties for UART, I2C, and SPI Add label properties to provide a way to identify UART, I2C and SPI ports based on their connector names. This follows naming convention in 96boards CE spec. Ports without external connections are not labelled. Signed-off-by: Rob Herring Cc: Srinivas Kandagatla Cc: Andy Gross Acked-by: Kevin Hilman Tested-by: Kevin Hilman Signed-off-by: Olof Johansson --- arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi index 7505fa385ceb..14fafa1e9c7c 100644 --- a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi +++ b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi @@ -28,6 +28,7 @@ soc { serial@78af000 { + label = "LS-UART0"; status = "okay"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&blsp1_uart1_default>; @@ -35,6 +36,7 @@ }; serial@78b0000 { + label = "LS-UART1"; status = "okay"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&blsp1_uart2_default>; @@ -43,26 +45,31 @@ i2c@78b6000 { /* On Low speed expansion */ + label = "LS-I2C0"; status = "okay"; }; i2c@78b8000 { /* On High speed expansion */ + label = "HS-I2C2"; status = "okay"; }; i2c@78ba000 { /* On Low speed expansion */ + label = "LS-I2C1"; status = "okay"; }; spi@78b7000 { /* On High speed expansion */ + label = "HS-SPI1"; status = "okay"; }; spi@78b9000 { /* On Low speed expansion */ + label = "LS-SPI0"; status = "okay"; }; -- cgit v1.2.3-59-g8ed1b From dd90caaca216b848e3093ebbd02bd4615de7e88b Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Thu, 10 Dec 2015 15:21:13 -0600 Subject: arm64: dts: hikey: add label properties to UARTs Add label properties to provide a way to identify UARTs based on their board or connector name. This follows naming convention in 96boards CE spec. Ports without external connections are not labelled. Signed-off-by: Rob Herring Signed-off-by: Olof Johansson --- arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts index 8d43a0fce522..818525197508 100644 --- a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts +++ b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts @@ -32,3 +32,10 @@ reg = <0x0 0x0 0x0 0x40000000>; }; }; + +&uart2 { + label = "LS-UART0"; +}; +&uart3 { + label = "LS-UART1"; +}; -- cgit v1.2.3-59-g8ed1b From 93beff2c1455497f35c21c561d475be1101dbdc2 Mon Sep 17 00:00:00 2001 From: Duc Dang Date: Tue, 29 Dec 2015 15:20:10 -0800 Subject: arm64: dts: Fix to use standard DT node names for X-Gene 1 and X-Gene 2 platforms Use devicetree standard node name for I2C (i2c@...), GFC GPIO (gpio@...), DW GPIO (gpio@...), Standby GPIO (gpio@...). The DT node name of USB (dwusb@...) still needs to be kept to maintain backward compatibility with old firmware. Signed-off-by: Duc Dang --- arch/arm64/boot/dts/apm/apm-shadowcat.dtsi | 11 ++++++----- arch/arm64/boot/dts/apm/apm-storm.dtsi | 8 ++++---- 2 files changed, 10 insertions(+), 9 deletions(-) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi b/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi index c617aa4972ab..4b3837bda5a6 100644 --- a/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi +++ b/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi @@ -476,6 +476,7 @@ interrupts = <0x0 0x4c 0x4>; }; + /* Do not change dwusb name, coded for backward compatibility */ usb0: dwusb@19000000 { status = "disabled"; compatible = "snps,dwc3"; @@ -575,14 +576,14 @@ clocks = <&sdioclk 0>, <&ahbclk 0>; }; - gfcgpio: gfcgpio@1f63c000 { + gfcgpio: gpio@1f63c000 { compatible = "apm,xgene-gpio"; reg = <0x0 0x1f63c000 0x0 0x40>; gpio-controller; #gpio-cells = <2>; }; - dwgpio: dwgpio@1c024000 { + dwgpio: gpio@1c024000 { compatible = "snps,dw-apb-gpio"; reg = <0x0 0x1c024000 0x0 0x1000>; reg-io-width = <4>; @@ -597,7 +598,7 @@ }; }; - sbgpio: sbgpio@17001000{ + sbgpio: gpio@17001000{ compatible = "apm,xgene-gpio-sb"; reg = <0x0 0x17001000 0x0 0x400>; #gpio-cells = <2>; @@ -648,7 +649,7 @@ clocks = <&rngpkaclk 0>; }; - i2c1: i2c1@10511000 { + i2c1: i2c@10511000 { #address-cells = <1>; #size-cells = <0>; compatible = "snps,designware-i2c"; @@ -659,7 +660,7 @@ bus_num = <1>; }; - i2c4: i2c4@10640000 { + i2c4: i2c@10640000 { #address-cells = <1>; #size-cells = <0>; compatible = "snps,designware-i2c"; diff --git a/arch/arm64/boot/dts/apm/apm-storm.dtsi b/arch/arm64/boot/dts/apm/apm-storm.dtsi index a21e08a88991..17f5dc265975 100644 --- a/arch/arm64/boot/dts/apm/apm-storm.dtsi +++ b/arch/arm64/boot/dts/apm/apm-storm.dtsi @@ -759,14 +759,14 @@ clocks = <&sdioclk 0>, <&ahbclk 0>; }; - gfcgpio: gfcgpio0@1701c000 { + gfcgpio: gpio0@1701c000 { compatible = "apm,xgene-gpio"; reg = <0x0 0x1701c000 0x0 0x40>; gpio-controller; #gpio-cells = <2>; }; - dwgpio: dwgpio@1c024000 { + dwgpio: gpio@1c024000 { compatible = "snps,dw-apb-gpio"; reg = <0x0 0x1c024000 0x0 0x1000>; reg-io-width = <4>; @@ -781,7 +781,7 @@ }; }; - i2c0: i2c0@10512000 { + i2c0: i2c@10512000 { status = "disabled"; #address-cells = <1>; #size-cells = <0>; @@ -886,7 +886,7 @@ dr_mode = "host"; }; - sbgpio: sbgpio@17001000{ + sbgpio: gpio@17001000{ compatible = "apm,xgene-gpio-sb"; reg = <0x0 0x17001000 0x0 0x400>; #gpio-cells = <2>; -- cgit v1.2.3-59-g8ed1b From 0fe8588fcaac6fff08937a338feb8e3082fe9e57 Mon Sep 17 00:00:00 2001 From: Duc Dang Date: Tue, 29 Dec 2015 17:02:05 -0800 Subject: arm64: dts: X-Gene v1: I2C0 clock is always on X-Gene v1 I2C0 and I2C1 controllers share the same clock enable register field. This patch remove clock node for I2C0 and leave I2C0 clock always on as having it toggled on/off will affect I2C1 operation. Signed-off-by: Duc Dang --- arch/arm64/boot/dts/apm/apm-storm.dtsi | 16 +--------------- 1 file changed, 1 insertion(+), 15 deletions(-) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/apm/apm-storm.dtsi b/arch/arm64/boot/dts/apm/apm-storm.dtsi index 17f5dc265975..fe30f7671ea3 100644 --- a/arch/arm64/boot/dts/apm/apm-storm.dtsi +++ b/arch/arm64/boot/dts/apm/apm-storm.dtsi @@ -437,20 +437,6 @@ reg-names = "csr-reg"; clock-output-names = "dmaclk"; }; - - i2cclk: i2cclk@17000000 { - status = "disabled"; - compatible = "apm,xgene-device-clock"; - #clock-cells = <1>; - clocks = <&ahbclk 0>; - reg = <0x0 0x17000000 0x0 0x2000>; - reg-names = "csr-reg"; - csr-offset = <0xc>; - csr-mask = <0x4>; - enable-offset = <0x10>; - enable-mask = <0x4>; - clock-output-names = "i2cclk"; - }; }; msi: msi@79000000 { @@ -789,7 +775,7 @@ reg = <0x0 0x10512000 0x0 0x1000>; interrupts = <0 0x44 0x4>; #clock-cells = <1>; - clocks = <&i2cclk 0>; + clocks = <&ahbclk 0>; bus_num = <0>; }; -- cgit v1.2.3-59-g8ed1b From 9ebf47bb748c17ebb2f9dde9169ed7a7612c3137 Mon Sep 17 00:00:00 2001 From: Duc Dang Date: Tue, 29 Dec 2015 17:05:31 -0800 Subject: arm64: dts: X-Gene v2: I2C1 clock is always on X-Gene v2 I2C0 and I2C1 controllers share the same clock enable register field. This patch remove clock node for I2C1 and leave I2C1 clock always on as having it toggled on/off will affect I2C0 operation. Signed-off-by: Duc Dang --- arch/arm64/boot/dts/apm/apm-shadowcat.dtsi | 15 +-------------- 1 file changed, 1 insertion(+), 14 deletions(-) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi b/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi index 4b3837bda5a6..5d87a3dc44b8 100644 --- a/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi +++ b/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi @@ -334,19 +334,6 @@ clock-output-names = "rngpkaclk"; }; - i2c1clk: i2c1clk@17000000 { - compatible = "apm,xgene-device-clock"; - #clock-cells = <1>; - clocks = <&sbapbclk 0>; - reg = <0x0 0x17000000 0x0 0x2000>; - reg-names = "csr-reg"; - csr-offset = <0xc>; - csr-mask = <0x4>; - enable-offset = <0x10>; - enable-mask = <0x4>; - clock-output-names = "i2c1clk"; - }; - i2c4clk: i2c4clk@1704c000 { compatible = "apm,xgene-device-clock"; #clock-cells = <1>; @@ -656,7 +643,7 @@ reg = <0x0 0x10511000 0x0 0x1000>; interrupts = <0 0x45 0x4>; #clock-cells = <1>; - clocks = <&i2c1clk 0>; + clocks = <&sbapbclk 0>; bus_num = <1>; }; -- cgit v1.2.3-59-g8ed1b From d50a8b4843f7160db6e44844b9d733e866c20a89 Mon Sep 17 00:00:00 2001 From: Bhupesh Sharma Date: Mon, 28 Dec 2015 15:31:24 +0530 Subject: dts/ls2080a: Update DTSI to add support of SP805 WDT This patch updates the LS2080a DTSI (DTS Include) file to add support for eight SP805 Watchdog units which can be used to reset the eight Cortex-A57 cores available on LS2080A. Signed-off-by: Bhupesh Sharma Signed-off-by: Arnd Bergmann --- arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi | 56 ++++++++++++++++++++++++++ 1 file changed, 56 insertions(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi index 65ac35f12fc4..1d4ed36767f1 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi @@ -205,6 +205,62 @@ interrupts = <0 32 0x4>; /* Level high type */ }; + cluster1_core0_watchdog: wdt@c000000 { + compatible = "arm,sp805-wdt", "arm,primecell"; + reg = <0x0 0xc000000 0x0 0x1000>; + clocks = <&clockgen 4 3>, <&clockgen 4 3>; + clock-names = "apb_pclk", "wdog_clk"; + }; + + cluster1_core1_watchdog: wdt@c010000 { + compatible = "arm,sp805-wdt", "arm,primecell"; + reg = <0x0 0xc010000 0x0 0x1000>; + clocks = <&clockgen 4 3>, <&clockgen 4 3>; + clock-names = "apb_pclk", "wdog_clk"; + }; + + cluster2_core0_watchdog: wdt@c100000 { + compatible = "arm,sp805-wdt", "arm,primecell"; + reg = <0x0 0xc100000 0x0 0x1000>; + clocks = <&clockgen 4 3>, <&clockgen 4 3>; + clock-names = "apb_pclk", "wdog_clk"; + }; + + cluster2_core1_watchdog: wdt@c110000 { + compatible = "arm,sp805-wdt", "arm,primecell"; + reg = <0x0 0xc110000 0x0 0x1000>; + clocks = <&clockgen 4 3>, <&clockgen 4 3>; + clock-names = "apb_pclk", "wdog_clk"; + }; + + cluster3_core0_watchdog: wdt@c200000 { + compatible = "arm,sp805-wdt", "arm,primecell"; + reg = <0x0 0xc200000 0x0 0x1000>; + clocks = <&clockgen 4 3>, <&clockgen 4 3>; + clock-names = "apb_pclk", "wdog_clk"; + }; + + cluster3_core1_watchdog: wdt@c210000 { + compatible = "arm,sp805-wdt", "arm,primecell"; + reg = <0x0 0xc210000 0x0 0x1000>; + clocks = <&clockgen 4 3>, <&clockgen 4 3>; + clock-names = "apb_pclk", "wdog_clk"; + }; + + cluster4_core0_watchdog: wdt@c300000 { + compatible = "arm,sp805-wdt", "arm,primecell"; + reg = <0x0 0xc300000 0x0 0x1000>; + clocks = <&clockgen 4 3>, <&clockgen 4 3>; + clock-names = "apb_pclk", "wdog_clk"; + }; + + cluster4_core1_watchdog: wdt@c310000 { + compatible = "arm,sp805-wdt", "arm,primecell"; + reg = <0x0 0xc310000 0x0 0x1000>; + clocks = <&clockgen 4 3>, <&clockgen 4 3>; + clock-names = "apb_pclk", "wdog_clk"; + }; + fsl_mc: fsl-mc@80c000000 { compatible = "fsl,qoriq-mc"; reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */ -- cgit v1.2.3-59-g8ed1b