From fe100b382c1c052b63c14091fd8bb3fe932453ae Mon Sep 17 00:00:00 2001 From: Joel Stanley Date: Mon, 21 Sep 2020 18:46:44 +0930 Subject: ARM: dts: aspeed: Add silicon id node This register describes the silicon id and chip unique id. It varies between CPU revisions, but is always part of the SCU. Reviewed-by: Andrew Jeffery Link: https://lore.kernel.org/r/20200921091644.133107-4-joel@jms.id.au Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-g4.dtsi | 5 +++++ arch/arm/boot/dts/aspeed-g5.dtsi | 5 +++++ arch/arm/boot/dts/aspeed-g6.dtsi | 5 +++++ 3 files changed, 15 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi index 82f0213e3a3c..b3dafbc8caca 100644 --- a/arch/arm/boot/dts/aspeed-g4.dtsi +++ b/arch/arm/boot/dts/aspeed-g4.dtsi @@ -192,6 +192,11 @@ status = "disabled"; }; + silicon-id@7c { + compatible = "aspeed,ast2400-silicon-id", "aspeed,silicon-id"; + reg = <0x7c 0x4>; + }; + pinctrl: pinctrl@80 { reg = <0x80 0x18>, <0xa0 0x10>; compatible = "aspeed,ast2400-pinctrl"; diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi index 9c91afb2b404..c6862182313a 100644 --- a/arch/arm/boot/dts/aspeed-g5.dtsi +++ b/arch/arm/boot/dts/aspeed-g5.dtsi @@ -239,6 +239,11 @@ status = "disabled"; }; + silicon-id@7c { + compatible = "aspeed,ast2500-silicon-id", "aspeed,silicon-id"; + reg = <0x7c 0x4 0x150 0x8>; + }; + pinctrl: pinctrl@80 { compatible = "aspeed,ast2500-pinctrl"; reg = <0x80 0x18>, <0xa0 0x10>; diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed-g6.dtsi index b58220a49cbd..1ce3a1f06f7f 100644 --- a/arch/arm/boot/dts/aspeed-g6.dtsi +++ b/arch/arm/boot/dts/aspeed-g6.dtsi @@ -311,6 +311,11 @@ compatible = "aspeed,ast2600-pinctrl"; }; + silicon-id@14 { + compatible = "aspeed,ast2600-silicon-id", "aspeed,silicon-id"; + reg = <0x14 0x4 0x5b0 0x8>; + }; + smp-memram@180 { compatible = "aspeed,ast2600-smpmem"; reg = <0x180 0x40>; -- cgit v1.2.3-59-g8ed1b From 1510723087d28f29112297517dbc8002ed1d4a68 Mon Sep 17 00:00:00 2001 From: Al Viro Date: Tue, 16 Jun 2020 00:23:07 -0400 Subject: arm: kill dump_task_regs() the last user had been fdpic Signed-off-by: Al Viro --- arch/arm/include/asm/elf.h | 4 ---- arch/arm/kernel/process.c | 9 --------- 2 files changed, 13 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/include/asm/elf.h b/arch/arm/include/asm/elf.h index b078d992414b..61941f369861 100644 --- a/arch/arm/include/asm/elf.h +++ b/arch/arm/include/asm/elf.h @@ -111,10 +111,6 @@ extern int elf_check_arch(const struct elf32_hdr *); extern int arm_elf_read_implies_exec(int); #define elf_read_implies_exec(ex,stk) arm_elf_read_implies_exec(stk) -struct task_struct; -int dump_task_regs(struct task_struct *t, elf_gregset_t *elfregs); -#define ELF_CORE_COPY_TASK_REGS dump_task_regs - #define CORE_DUMP_USE_REGSET #define ELF_EXEC_PAGESIZE 4096 diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c index 8e6ace03e960..d0220da1d1b1 100644 --- a/arch/arm/kernel/process.c +++ b/arch/arm/kernel/process.c @@ -272,15 +272,6 @@ int copy_thread(unsigned long clone_flags, unsigned long stack_start, return 0; } -/* - * Fill in the task's elfregs structure for a core dump. - */ -int dump_task_regs(struct task_struct *t, elf_gregset_t *elfregs) -{ - elf_core_copy_regs(elfregs, task_pt_regs(t)); - return 1; -} - unsigned long get_wchan(struct task_struct *p) { struct stackframe frame; -- cgit v1.2.3-59-g8ed1b From 79bd11db8ba8046943dddf740d58baac54326f56 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 20 Sep 2020 21:57:49 +0200 Subject: ARM: dts: imx: align GPIO hog names with dtschema dtschema for GPIO controllers expects GPIO hogs to end with 'hog' suffix. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx51-zii-rdu1.dts | 2 +- arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi | 8 ++++---- arch/arm/boot/dts/imx6ul-ccimx6ulsbcpro.dts | 2 +- 3 files changed, 6 insertions(+), 6 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx51-zii-rdu1.dts b/arch/arm/boot/dts/imx51-zii-rdu1.dts index e559ab0c3645..ec8ca3ac2c1c 100644 --- a/arch/arm/boot/dts/imx51-zii-rdu1.dts +++ b/arch/arm/boot/dts/imx51-zii-rdu1.dts @@ -451,7 +451,7 @@ "", "", "", "", "", "", "", ""; - unused-sd3-wp-gpio { + unused-sd3-wp-hog { /* * See pinctrl_esdhc1 below for more details on this */ diff --git a/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi b/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi index 66b15748e287..c0a76202e16b 100644 --- a/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi +++ b/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi @@ -330,28 +330,28 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio3_hog>; - usb-emulation { + usb-emulation-hog { gpio-hog; gpios = <19 GPIO_ACTIVE_HIGH>; output-low; line-name = "usb-emulation"; }; - usb-mode1 { + usb-mode1-hog { gpio-hog; gpios = <20 GPIO_ACTIVE_HIGH>; output-high; line-name = "usb-mode1"; }; - usb-pwr { + usb-pwr-hog { gpio-hog; gpios = <22 GPIO_ACTIVE_LOW>; output-high; line-name = "usb-pwr-ctrl-en-n"; }; - usb-mode2 { + usb-mode2-hog { gpio-hog; gpios = <23 GPIO_ACTIVE_HIGH>; output-high; diff --git a/arch/arm/boot/dts/imx6ul-ccimx6ulsbcpro.dts b/arch/arm/boot/dts/imx6ul-ccimx6ulsbcpro.dts index a0bbec57ddc7..3ec042bfccba 100644 --- a/arch/arm/boot/dts/imx6ul-ccimx6ulsbcpro.dts +++ b/arch/arm/boot/dts/imx6ul-ccimx6ulsbcpro.dts @@ -110,7 +110,7 @@ }; &gpio5 { - emmc-usd-mux { + emmc-usd-mux-hog { gpio-hog; gpios = <1 GPIO_ACTIVE_LOW>; output-high; -- cgit v1.2.3-59-g8ed1b From 9b533dc8f340f5e9e7f2ed610510b2191d5e447c Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Tue, 29 Sep 2020 15:05:02 +0100 Subject: ARM: dts: r8a7742-iwg21d-q7: Add LCD support The iwg21d comes with a 7" capacitive touch screen, therefore add support for it. Signed-off-by: Lad Prabhakar Reviewed-by: Marian-Cristian Rotariu Reviewed-by: Laurent Pinchart Link: https://lore.kernel.org/r/20200929140502.16017-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm/boot/dts/r8a7742-iwg21d-q7.dts | 99 +++++++++++++++++++++++++++++++++ 1 file changed, 99 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts b/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts index c2c05c9685d1..0063ef92f50e 100644 --- a/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts +++ b/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts @@ -30,6 +30,7 @@ /dts-v1/; #include "r8a7742-iwg21m.dtsi" +#include / { model = "iWave Systems RainboW-G21D-Qseven board based on RZ/G1H"; @@ -52,6 +53,16 @@ clock-frequency = <26000000>; }; + lcd_backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&tpu 2 5000000 0>; + brightness-levels = <0 4 8 16 32 64 128 255>; + pinctrl-0 = <&backlight_pins>; + pinctrl-names = "default"; + default-brightness-level = <7>; + enable-gpios = <&gpio3 11 GPIO_ACTIVE_HIGH>; + }; + leds { compatible = "gpio-leds"; @@ -62,6 +73,41 @@ }; }; + lvds-receiver { + compatible = "ti,ds90cf384a", "lvds-decoder"; + power-supply = <&vcc_3v3_tft1>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + lvds_receiver_in: endpoint { + remote-endpoint = <&lvds0_out>; + }; + }; + port@1 { + reg = <1>; + lvds_receiver_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; + }; + + panel { + compatible = "edt,etm0700g0dh6"; + backlight = <&lcd_backlight>; + power-supply = <&vcc_3v3_tft1>; + + port { + panel_in: endpoint { + remote-endpoint = <&lvds_receiver_out>; + }; + }; + }; + reg_1p5v: 1p5v { compatible = "regulator-fixed"; regulator-name = "1P5V"; @@ -85,6 +131,17 @@ }; }; + vcc_3v3_tft1: regulator-panel { + compatible = "regulator-fixed"; + + regulator-name = "vcc-3v3-tft1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + startup-delay-us = <500>; + gpio = <&gpio5 28 GPIO_ACTIVE_HIGH>; + }; + vcc_sdhi2: regulator-vcc-sdhi2 { compatible = "regulator-fixed"; @@ -139,6 +196,16 @@ VDDIO-supply = <®_3p3v>; VDDD-supply = <®_1p5v>; }; + + touch: touchpanel@38 { + compatible = "edt,edt-ft5406"; + reg = <0x38>; + interrupt-parent = <&gpio0>; + interrupts = <24 IRQ_TYPE_EDGE_FALLING>; + /* GP1_29 is also shared with audio codec reset pin */ + reset-gpios = <&gpio1 29 GPIO_ACTIVE_LOW>; + vcc-supply = <&vcc_3v3_tft1>; + }; }; &can1 { @@ -152,6 +219,18 @@ status = "okay"; }; +&du { + status = "okay"; +}; + +&gpio0 { + touch-interrupt { + gpio-hog; + gpios = <24 GPIO_ACTIVE_LOW>; + input; + }; +}; + &gpio1 { can-trx-en-gpio{ gpio-hog; @@ -167,6 +246,17 @@ status = "okay"; }; +&lvds0 { + status = "okay"; + ports { + port@1 { + lvds0_out: endpoint { + remote-endpoint = <&lvds_receiver_in>; + }; + }; + }; +}; + &msiof0 { pinctrl-0 = <&msiof0_pins>; pinctrl-names = "default"; @@ -229,6 +319,11 @@ function = "avb"; }; + backlight_pins: backlight { + groups = "tpu0_to2"; + function = "tpu0"; + }; + can1_pins: can1 { groups = "can1_data_b"; function = "can1"; @@ -335,6 +430,10 @@ shared-pin; }; +&tpu { + status = "okay"; +}; + &usbphy { status = "okay"; }; -- cgit v1.2.3-59-g8ed1b From d311d818fa8cfa791d05de9e03b0d9babfc82dd2 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Wed, 14 Oct 2020 15:55:58 +0100 Subject: ARM: dts: r8a7742-iwg21d-q7-dbcm-ca: Enable VIN instances Enable VIN instances along with OV5640 as endpoints on the adapter board. Signed-off-by: Lad Prabhakar Reviewed-by: Biju Das Link: https://lore.kernel.org/r/20201014145558.12854-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ca.dts | 222 ++++++++++++++++++++++++ 1 file changed, 222 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ca.dts b/arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ca.dts index 961c0f2eeefb..98c3fbd89fa6 100644 --- a/arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ca.dts +++ b/arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ca.dts @@ -20,6 +20,30 @@ serial5 = &hscif0; ethernet1 = ðer; }; + + mclk_cam1: mclk-cam1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + }; + + mclk_cam2: mclk-cam2 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + }; + + mclk_cam3: mclk-cam3 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + }; + + mclk_cam4: mclk-cam4 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + }; }; &avb { @@ -47,6 +71,19 @@ }; }; +&gpio0 { + /* Disable hogging GP0_18 to output LOW */ + /delete-node/ qspi_en; + + /* Hog GP0_18 to output HIGH to enable VIN2 */ + vin2_en { + gpio-hog; + gpios = <18 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "VIN2_EN"; + }; +}; + &hscif0 { pinctrl-0 = <&hscif0_pins>; pinctrl-names = "default"; @@ -54,6 +91,94 @@ status = "okay"; }; +&i2c0 { + ov5640@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + clocks = <&mclk_cam1>; + clock-names = "xclk"; + + port { + ov5640_0: endpoint { + bus-width = <8>; + data-shift = <2>; + bus-type = <6>; + pclk-sample = <1>; + remote-endpoint = <&vin0ep>; + }; + }; + }; +}; + +&i2c1 { + pinctrl-0 = <&i2c1_pins>; + pinctrl-names = "default"; + + status = "okay"; + clock-frequency = <400000>; + + ov5640@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + clocks = <&mclk_cam2>; + clock-names = "xclk"; + + port { + ov5640_1: endpoint { + bus-width = <8>; + data-shift = <2>; + bus-type = <6>; + pclk-sample = <1>; + remote-endpoint = <&vin1ep>; + }; + }; + }; +}; + +&i2c2 { + ov5640@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + clocks = <&mclk_cam3>; + clock-names = "xclk"; + + port { + ov5640_2: endpoint { + bus-width = <8>; + data-shift = <2>; + bus-type = <6>; + pclk-sample = <1>; + remote-endpoint = <&vin2ep>; + }; + }; + }; +}; + +&i2c3 { + pinctrl-0 = <&i2c3_pins>; + pinctrl-names = "default"; + + status = "okay"; + clock-frequency = <400000>; + + ov5640@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + clocks = <&mclk_cam4>; + clock-names = "xclk"; + + port { + ov5640_3: endpoint { + bus-width = <8>; + data-shift = <2>; + bus-type = <6>; + pclk-sample = <1>; + remote-endpoint = <&vin3ep>; + }; + }; + }; +}; + &pfc { can0_pins: can0 { groups = "can0_data_d"; @@ -70,6 +195,16 @@ function = "hscif0"; }; + i2c1_pins: i2c1 { + groups = "i2c1_c"; + function = "i2c1"; + }; + + i2c3_pins: i2c3 { + groups = "i2c3"; + function = "i2c3"; + }; + scif0_pins: scif0 { groups = "scif0_data"; function = "scif0"; @@ -84,6 +219,31 @@ groups = "scifb1_data"; function = "scifb1"; }; + + vin0_8bit_pins: vin0 { + groups = "vin0_data8", "vin0_clk", "vin0_sync"; + function = "vin0"; + }; + + vin1_8bit_pins: vin1 { + groups = "vin1_data8_b", "vin1_clk_b", "vin1_sync_b"; + function = "vin1"; + }; + + vin2_pins: vin2 { + groups = "vin2_g8", "vin2_clk"; + function = "vin2"; + }; + + vin3_pins: vin3 { + groups = "vin3_data8", "vin3_clk", "vin3_sync"; + function = "vin3"; + }; +}; + +&qspi { + /* Pins shared with VIN2, keep status disabled */ + status = "disabled"; }; &scif0 { @@ -106,3 +266,65 @@ rts-gpios = <&gpio4 21 GPIO_ACTIVE_LOW>; cts-gpios = <&gpio4 17 GPIO_ACTIVE_LOW>; }; + +&vin0 { + /* + * Set SW2 switch on the SOM to 'ON' + * Set SW1 switch on camera board to 'OFF' as we are using 8bit mode + */ + status = "okay"; + pinctrl-0 = <&vin0_8bit_pins>; + pinctrl-names = "default"; + + port { + vin0ep: endpoint { + remote-endpoint = <&ov5640_0>; + bus-width = <8>; + bus-type = <6>; + }; + }; +}; + +&vin1 { + /* Set SW1 switch on the SOM to 'ON' */ + status = "okay"; + pinctrl-0 = <&vin1_8bit_pins>; + pinctrl-names = "default"; + + port { + vin1ep: endpoint { + remote-endpoint = <&ov5640_1>; + bus-width = <8>; + bus-type = <6>; + }; + }; +}; + +&vin2 { + status = "okay"; + pinctrl-0 = <&vin2_pins>; + pinctrl-names = "default"; + + port { + vin2ep: endpoint { + remote-endpoint = <&ov5640_2>; + bus-width = <8>; + data-shift = <8>; + bus-type = <6>; + }; + }; +}; + +&vin3 { + status = "okay"; + pinctrl-0 = <&vin3_pins>; + pinctrl-names = "default"; + + port { + vin3ep: endpoint { + remote-endpoint = <&ov5640_3>; + bus-width = <8>; + bus-type = <6>; + }; + }; +}; -- cgit v1.2.3-59-g8ed1b From 486d49914307e4e1ff0f5087f803cfa1e44a13bf Mon Sep 17 00:00:00 2001 From: Iskren Chernev Date: Sun, 20 Sep 2020 17:48:53 +0300 Subject: ARM: dts: qcom: msm8974-klte: Merge pinctrl nodes commit cd13c72c1853f219e1f ("ARM: dts: qcom: msm8974-klte: Add max77826 pmic node") and commit 8bf7a360a92cc6b2aebc8 ("ARM: dts: qcom: msm8974-klte: Add sdhci1 node") both added pinctrl node. This patch merges the two nodes. Signed-off-by: Iskren Chernev Link: https://lore.kernel.org/r/20200920144859.813032-2-iskren.chernev@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts | 22 ++++++++++------------ 1 file changed, 10 insertions(+), 12 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts b/arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts index d4dc98214225..9520c6e7910c 100644 --- a/arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts +++ b/arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts @@ -258,6 +258,16 @@ bias-pull-up; }; }; + + i2c6_pins: i2c6 { + mux { + pins = "gpio29", "gpio30"; + function = "blsp_i2c6"; + + drive-strength = <2>; + bias-disable; + }; + }; }; sdhci@f9824900 { @@ -298,18 +308,6 @@ }; }; - pinctrl@fd510000 { - i2c6_pins: i2c6 { - mux { - pins = "gpio29", "gpio30"; - function = "blsp_i2c6"; - - drive-strength = <2>; - bias-disable; - }; - }; - }; - i2c@f9928000 { status = "okay"; -- cgit v1.2.3-59-g8ed1b From a193dc521c97c07098bf0b6345966561a1f0ab9f Mon Sep 17 00:00:00 2001 From: Iskren Chernev Date: Sun, 20 Sep 2020 17:48:54 +0300 Subject: ARM: dts: qcom: msm8974-klte: Add support for touchkey Add support for the touchkey found on the Samsung Galaxy S5. The touchkey is responsible for handling the application and back buttons found around the home button. Signed-off-by: Iskren Chernev Link: https://lore.kernel.org/r/20200920144859.813032-3-iskren.chernev@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts | 44 ++++++++++++++++++++++++- 1 file changed, 43 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts b/arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts index 9520c6e7910c..750e2f261139 100644 --- a/arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts +++ b/arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts @@ -145,7 +145,7 @@ }; pma8084_l19: l19 { - regulator-min-microvolt = <2900000>; + regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; @@ -203,6 +203,31 @@ }; }; + i2c-gpio-touchkey { + compatible = "i2c-gpio"; + #address-cells = <1>; + #size-cells = <0>; + sda-gpios = <&msmgpio 95 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&msmgpio 96 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c_touchkey_pins>; + + touchkey@20 { + compatible = "cypress,tm2-touchkey"; + reg = <0x20>; + + interrupt-parent = <&pma8084_gpios>; + interrupts = <6 IRQ_TYPE_EDGE_FALLING>; + pinctrl-names = "default"; + pinctrl-0 = <&touchkey_pin>; + + vcc-supply = <&max77826_ldo15>; + vdd-supply = <&pma8084_l19>; + + linux,keycodes = ; + }; + }; + /delete-node/ vreg-boost; }; @@ -268,6 +293,15 @@ bias-disable; }; }; + + i2c_touchkey_pins: i2c-touchkey { + mux { + pins = "gpio95", "gpio96"; + function = "gpio"; + input-enable; + bias-pull-up; + }; + }; }; sdhci@f9824900 { @@ -418,6 +452,14 @@ bias-pull-up; power-source = ; }; + + touchkey_pin: touchkey-int-pin { + pins = "gpio6"; + function = "normal"; + bias-disable; + input-enable; + power-source = ; + }; }; }; }; -- cgit v1.2.3-59-g8ed1b From 972f5a62a698857f4a02a6667f53ca158ce7421d Mon Sep 17 00:00:00 2001 From: Iskren Chernev Date: Sun, 20 Sep 2020 17:48:55 +0300 Subject: ARM: dts: qcom: msm8974-klte: Add support for touchscreen Add support for the touchscreen found on the Samsung Galaxy S5. Signed-off-by: Iskren Chernev Link: https://lore.kernel.org/r/20200920144859.813032-4-iskren.chernev@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts | 54 +++++++++++++++++++++++++ 1 file changed, 54 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts b/arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts index 750e2f261139..085636f182d0 100644 --- a/arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts +++ b/arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts @@ -284,6 +284,16 @@ }; }; + i2c2_pins: i2c2 { + mux { + pins = "gpio6", "gpio7"; + function = "blsp_i2c2"; + + drive-strength = <2>; + bias-disable; + }; + }; + i2c6_pins: i2c6 { mux { pins = "gpio29", "gpio30"; @@ -342,6 +352,42 @@ }; }; + i2c@f9924000 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins>; + + touchscreen@20 { + compatible = "syna,rmi4-i2c"; + reg = <0x20>; + + interrupt-parent = <&pma8084_gpios>; + interrupts = <8 IRQ_TYPE_EDGE_FALLING>; + + vdd-supply = <&max77826_ldo13>; + vio-supply = <&pma8084_lvs2>; + + pinctrl-names = "default"; + pinctrl-0 = <&touch_pin>; + + syna,startup-delay-ms = <100>; + + #address-cells = <1>; + #size-cells = <0>; + + rmi4-f01@1 { + reg = <0x1>; + syna,nosleep-mode = <1>; + }; + + rmi4-f12@12 { + reg = <0x12>; + syna,sensor-type = <1>; + }; + }; + }; + i2c@f9928000 { status = "okay"; @@ -460,6 +506,14 @@ input-enable; power-source = ; }; + + touch_pin: touchscreen-int-pin { + pins = "gpio8"; + function = "normal"; + bias-disable; + input-enable; + power-source = ; + }; }; }; }; -- cgit v1.2.3-59-g8ed1b From 60367221d7d46d623dbef4cd30924e99c97ff2e5 Mon Sep 17 00:00:00 2001 From: Iskren Chernev Date: Sun, 20 Sep 2020 17:48:56 +0300 Subject: ARM: dts: qcom: msm8974-klte: Add support for led The klte uses a Panasonic AN30259A LED controller for it's indicator led. Signed-off-by: Iskren Chernev Link: https://lore.kernel.org/r/20200920144859.813032-5-iskren.chernev@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts | 48 +++++++++++++++++++++++++ 1 file changed, 48 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts b/arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts index 085636f182d0..7b398da9b75e 100644 --- a/arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts +++ b/arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts @@ -4,6 +4,7 @@ #include #include #include +#include / { model = "Samsung Galaxy S5"; @@ -228,6 +229,44 @@ }; }; + i2c-gpio-led { + compatible = "i2c-gpio"; + #address-cells = <1>; + #size-cells = <0>; + scl-gpios = <&msmgpio 121 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&msmgpio 120 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c_led_pins>; + + i2c-gpio,delay-us = <2>; + + led-controller@30 { + compatible = "panasonic,an30259a"; + reg = <0x30>; + + #address-cells = <1>; + #size-cells = <0>; + + led@1 { + reg = <1>; + function = LED_FUNCTION_STATUS; + color = ; + }; + + led@2 { + reg = <2>; + function = LED_FUNCTION_STATUS; + color = ; + }; + + led@3 { + reg = <3>; + function = LED_FUNCTION_STATUS; + color = ; + }; + }; + }; + /delete-node/ vreg-boost; }; @@ -312,6 +351,15 @@ bias-pull-up; }; }; + + i2c_led_pins: i2c-led { + mux { + pins = "gpio120", "gpio121"; + function = "gpio"; + input-enable; + bias-pull-down; + }; + }; }; sdhci@f9824900 { -- cgit v1.2.3-59-g8ed1b From 99128e7503bed5475aadd10fa97b1d7ffc5a35c2 Mon Sep 17 00:00:00 2001 From: Iskren Chernev Date: Sun, 20 Sep 2020 17:48:57 +0300 Subject: ARM: dts: qcom: msm8974-klte: Add gpio expander chip The Samsung Galaxy S5 has a GPIO Expander chip, the PCAL6416A with 16 ports on a i2c bus. These pins are used for WiFi, NFC, IR among other things. Signed-off-by: Iskren Chernev Link: https://lore.kernel.org/r/20200920144859.813032-6-iskren.chernev@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts | 29 +++++++++++++++++++++++-- 1 file changed, 27 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts b/arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts index 7b398da9b75e..29099b83b231 100644 --- a/arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts +++ b/arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts @@ -236,10 +236,25 @@ scl-gpios = <&msmgpio 121 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; sda-gpios = <&msmgpio 120 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; pinctrl-names = "default"; - pinctrl-0 = <&i2c_led_pins>; + pinctrl-0 = <&i2c_led_gpioex_pins>; i2c-gpio,delay-us = <2>; + gpio_expander: gpio@20 { + compatible = "nxp,pcal6416"; + reg = <0x20>; + + gpio-controller; + #gpio-cells = <2>; + + vcc-supply = <&pma8084_s4>; + + pinctrl-names = "default"; + pinctrl-0 = <&gpioex_pin>; + + reset-gpios = <&msmgpio 145 GPIO_ACTIVE_LOW>; + }; + led-controller@30 { compatible = "panasonic,an30259a"; reg = <0x30>; @@ -352,7 +367,7 @@ }; }; - i2c_led_pins: i2c-led { + i2c_led_gpioex_pins: i2c-led-gpioex { mux { pins = "gpio120", "gpio121"; function = "gpio"; @@ -360,6 +375,16 @@ bias-pull-down; }; }; + + gpioex_pin: gpioex { + res { + pins = "gpio145"; + function = "gpio"; + + bias-pull-up; + drive-strength = <2>; + }; + }; }; sdhci@f9824900 { -- cgit v1.2.3-59-g8ed1b From 19524d5b1700616d4cfad9922238bd31ad758074 Mon Sep 17 00:00:00 2001 From: Iskren Chernev Date: Sun, 20 Sep 2020 17:48:58 +0300 Subject: ARM: dts: qcom: msm8974-klte: Add support for wifi The Samsung Galaxy S5 (klte), uses a Broadcom 4354 Chip connected on the SDIO bus. The chip also requires a corresponding firmware + txt file[1]. [1] https://gitlab.com/postmarketOS/pmaports/-/blob/master/firmware/firmware-samsung-klte/APKBUILD Signed-off-by: Iskren Chernev Link: https://lore.kernel.org/r/20200920144859.813032-7-iskren.chernev@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts | 74 +++++++++++++++++++++++++ 1 file changed, 74 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts b/arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts index 29099b83b231..989447beb431 100644 --- a/arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts +++ b/arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts @@ -282,6 +282,17 @@ }; }; + vreg_wlan: wlan-regulator { + compatible = "regulator-fixed"; + + regulator-name = "wl-reg"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&gpio_expander 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + /delete-node/ vreg-boost; }; @@ -338,6 +349,20 @@ }; }; + sdhc3_pin_a: sdhc3-pin-active { + clk { + pins = "sdc2_clk"; + drive-strength = <6>; + bias-disable; + }; + + cmd-data { + pins = "sdc2_cmd", "sdc2_data"; + drive-strength = <6>; + bias-pull-up; + }; + }; + i2c2_pins: i2c2 { mux { pins = "gpio6", "gpio7"; @@ -385,6 +410,16 @@ drive-strength = <2>; }; }; + + wifi_pin: wifi { + int { + pins = "gpio92"; + function = "gpio"; + + input-enable; + bias-pull-down; + }; + }; }; sdhci@f9824900 { @@ -400,6 +435,36 @@ pinctrl-0 = <&sdhc1_pin_a>; }; + sdhci@f98a4900 { + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + + max-frequency = <100000000>; + + pinctrl-names = "default"; + pinctrl-0 = <&sdhc3_pin_a>; + + vmmc-supply = <&vreg_wlan>; + vqmmc-supply = <&pma8084_s4>; + + bus-width = <4>; + non-removable; + + wifi@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + + interrupt-parent = <&msmgpio>; + interrupts = <92 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "host-wake"; + + pinctrl-names = "default"; + pinctrl-0 = <&wlan_sleep_clk_pin &wifi_pin>; + }; + }; + usb@f9a55000 { status = "ok"; @@ -587,6 +652,15 @@ input-enable; power-source = ; }; + + wlan_sleep_clk_pin: wlan-sleep-clk-pin { + pins = "gpio16"; + function = "func2"; + + output-high; + power-source = ; + qcom,drive-strength = ; + }; }; }; }; -- cgit v1.2.3-59-g8ed1b From 5434dcef54964e1f8a293e43b93ba6b45cc477ae Mon Sep 17 00:00:00 2001 From: Iskren Chernev Date: Sun, 20 Sep 2020 17:48:59 +0300 Subject: ARM: dts: qcom: msm8974-klte: Add support for SD card The Samsung Galaxy S5 (klte), has 3 SDHCI nodes used for internal storage, WiFi, external SD card slot. The external SD card slot is similar to the internal storage. Signed-off-by: Iskren Chernev Link: https://lore.kernel.org/r/20200920144859.813032-8-iskren.chernev@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts | 44 ++++++++++++++++++++++++- 1 file changed, 43 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts b/arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts index 989447beb431..b0899107f3ce 100644 --- a/arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts +++ b/arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts @@ -12,6 +12,8 @@ aliases { serial0 = &blsp1_uart1; + sdhc1 = &sdhc_1; /* SDC1 eMMC slot */ + sdhc2 = &sdhc_2; /* SDC2 SD card slot */ }; chosen { @@ -161,6 +163,9 @@ pma8084_l21: l21 { regulator-min-microvolt = <2950000>; regulator-max-microvolt = <2950000>; + + regulator-allow-set-load; + regulator-system-load = <200000>; }; pma8084_l22: l22 { @@ -349,6 +354,24 @@ }; }; + sdhc2_pin_a: sdhc2-pin-active { + clk-cmd-data { + pins = "gpio35", "gpio36", "gpio37", "gpio38", + "gpio39", "gpio40"; + function = "sdc3"; + drive-strength = <8>; + bias-disable; + }; + }; + + sdhc2_cd_pin: sdhc2-cd { + pins = "gpio62"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + }; + sdhc3_pin_a: sdhc3-pin-active { clk { pins = "sdc2_clk"; @@ -422,7 +445,7 @@ }; }; - sdhci@f9824900 { + sdhc_1: sdhci@f9824900 { status = "ok"; vmmc-supply = <&pma8084_l20>; @@ -435,6 +458,25 @@ pinctrl-0 = <&sdhc1_pin_a>; }; + sdhc_2: sdhci@f9864900 { + status = "ok"; + + max-frequency = <100000000>; + + vmmc-supply = <&pma8084_l21>; + vqmmc-supply = <&pma8084_l13>; + + bus-width = <4>; + + /* cd-gpio is intentionally disabled. If enabled, an SD card + * present during boot is not initialized correctly. Without + * cd-gpios the driver resorts to polling, so hotplug works. + */ + pinctrl-names = "default"; + pinctrl-0 = <&sdhc2_pin_a /* &sdhc2_cd_pin */>; + // cd-gpios = <&msmgpio 62 GPIO_ACTIVE_LOW>; + }; + sdhci@f98a4900 { status = "okay"; -- cgit v1.2.3-59-g8ed1b From 292f70d7cdd506e21d12de650f626b95d31b7ec7 Mon Sep 17 00:00:00 2001 From: Nicholas Piggin Date: Wed, 2 Sep 2020 00:15:20 +1000 Subject: arm: use asm-generic/mmu_context.h for no-op implementations Signed-off-by: Nicholas Piggin Cc: Russell King Cc: linux-arm-kernel@lists.infradead.org Signed-off-by: Arnd Bergmann --- arch/arm/include/asm/mmu_context.h | 26 +++----------------------- 1 file changed, 3 insertions(+), 23 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/include/asm/mmu_context.h b/arch/arm/include/asm/mmu_context.h index f99ed524fe41..84e58956fcab 100644 --- a/arch/arm/include/asm/mmu_context.h +++ b/arch/arm/include/asm/mmu_context.h @@ -26,6 +26,8 @@ void __check_vmalloc_seq(struct mm_struct *mm); #ifdef CONFIG_CPU_HAS_ASID void check_and_switch_context(struct mm_struct *mm, struct task_struct *tsk); + +#define init_new_context init_new_context static inline int init_new_context(struct task_struct *tsk, struct mm_struct *mm) { @@ -92,32 +94,10 @@ static inline void finish_arch_post_lock_switch(void) #endif /* CONFIG_MMU */ -static inline int -init_new_context(struct task_struct *tsk, struct mm_struct *mm) -{ - return 0; -} - - #endif /* CONFIG_CPU_HAS_ASID */ -#define destroy_context(mm) do { } while(0) #define activate_mm(prev,next) switch_mm(prev, next, NULL) -/* - * This is called when "tsk" is about to enter lazy TLB mode. - * - * mm: describes the currently active mm context - * tsk: task which is entering lazy tlb - * cpu: cpu number which is entering lazy tlb - * - * tsk->mm will be NULL - */ -static inline void -enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk) -{ -} - /* * This is the actual mm switch as far as the scheduler * is concerned. No registers are touched. We avoid @@ -149,6 +129,6 @@ switch_mm(struct mm_struct *prev, struct mm_struct *next, #endif } -#define deactivate_mm(tsk,mm) do { } while (0) +#include #endif -- cgit v1.2.3-59-g8ed1b From 4a6dbc65f6efa76a10ae6b64ad30ea12a991d7f0 Mon Sep 17 00:00:00 2001 From: Alexander Dahl Date: Mon, 5 Oct 2020 22:34:46 +0200 Subject: ARM: dts: exynos: Fix schema warnings for pwm-leds The node names for devices using the pwm-leds driver follow a certain naming scheme (now). Parent node name is not enforced, but recommended by DT project. arch/arm/boot/dts/exynos5410-odroidxu.dt.yaml: pwmleds: 'blueled', 'greenled' do not match any of the regexes: '^led(-[0-9a-f]+)?$', 'pinctrl-[0-9]+' arch/arm/boot/dts/exynos5422-odroidhc1.dt.yaml: pwmleds: 'blueled' does not match any of the regexes: '^led(-[0-9a-f]+)?$', 'pinctrl-[0-9]+' From schema: Documentation/devicetree/bindings/leds/leds-pwm.yaml Signed-off-by: Alexander Dahl Link: https://lore.kernel.org/r/20201005203451.9985-8-post@lespocky.de Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos5422-odroidhc1.dts | 4 ++-- arch/arm/boot/dts/exynos5422-odroidxu4.dts | 4 ++-- arch/arm/boot/dts/exynos54xx-odroidxu-leds.dtsi | 11 ++++++----- 3 files changed, 10 insertions(+), 9 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/exynos5422-odroidhc1.dts b/arch/arm/boot/dts/exynos5422-odroidhc1.dts index 812659260278..20c222b33f98 100644 --- a/arch/arm/boot/dts/exynos5422-odroidhc1.dts +++ b/arch/arm/boot/dts/exynos5422-odroidhc1.dts @@ -15,10 +15,10 @@ compatible = "hardkernel,odroid-hc1", "samsung,exynos5800", \ "samsung,exynos5"; - pwmleds { + led-controller { compatible = "pwm-leds"; - blueled { + led-1 { label = "blue:heartbeat"; pwms = <&pwm 2 2000000 0>; pwm-names = "pwm2"; diff --git a/arch/arm/boot/dts/exynos5422-odroidxu4.dts b/arch/arm/boot/dts/exynos5422-odroidxu4.dts index ddd55d3bcadd..ede782257643 100644 --- a/arch/arm/boot/dts/exynos5422-odroidxu4.dts +++ b/arch/arm/boot/dts/exynos5422-odroidxu4.dts @@ -17,10 +17,10 @@ compatible = "hardkernel,odroid-xu4", "samsung,exynos5800", \ "samsung,exynos5"; - pwmleds { + led-controller { compatible = "pwm-leds"; - blueled { + led-1 { label = "blue:heartbeat"; pwms = <&pwm 2 2000000 0>; pwm-names = "pwm2"; diff --git a/arch/arm/boot/dts/exynos54xx-odroidxu-leds.dtsi b/arch/arm/boot/dts/exynos54xx-odroidxu-leds.dtsi index 56acd832f0b3..2fc3e86dc5f7 100644 --- a/arch/arm/boot/dts/exynos54xx-odroidxu-leds.dtsi +++ b/arch/arm/boot/dts/exynos54xx-odroidxu-leds.dtsi @@ -11,10 +11,10 @@ #include / { - pwmleds { + led-controller-1 { compatible = "pwm-leds"; - greenled { + led-1 { label = "green:mmc0"; pwms = <&pwm 1 2000000 0>; pwm-names = "pwm1"; @@ -26,7 +26,7 @@ linux,default-trigger = "mmc0"; }; - blueled { + led-2 { label = "blue:heartbeat"; pwms = <&pwm 2 2000000 0>; pwm-names = "pwm2"; @@ -35,9 +35,10 @@ }; }; - gpioleds { + led-controller-2 { compatible = "gpio-leds"; - redled { + + led-3 { label = "red:microSD"; gpios = <&gpx2 3 GPIO_ACTIVE_HIGH>; default-state = "off"; -- cgit v1.2.3-59-g8ed1b From 95f075fec383bd15cb0297254d84d3bd880eba9d Mon Sep 17 00:00:00 2001 From: Marek Szyprowski Date: Fri, 9 Oct 2020 15:48:55 +0200 Subject: ARM: exynos_defconfig: enable sound driver for Midas platform Sound driver for Midas platform (Exnyos4412 SoC based) has been recently merged, so enable it for tests like other sound drivers for Exynos based boards. Signed-off-by: Marek Szyprowski Link: https://lore.kernel.org/r/20201009134855.4520-1-m.szyprowski@samsung.com Signed-off-by: Krzysztof Kozlowski --- arch/arm/configs/exynos_defconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm') diff --git a/arch/arm/configs/exynos_defconfig b/arch/arm/configs/exynos_defconfig index cf82c9d23a08..8c1fd6408108 100644 --- a/arch/arm/configs/exynos_defconfig +++ b/arch/arm/configs/exynos_defconfig @@ -245,6 +245,7 @@ CONFIG_SND_SOC_SMDK_WM8994_PCM=y CONFIG_SND_SOC_SNOW=y CONFIG_SND_SOC_ODROID=y CONFIG_SND_SOC_ARNDALE=y +CONFIG_SND_SOC_SAMSUNG_MIDAS_WM1811=y CONFIG_SND_SIMPLE_CARD=y CONFIG_USB=y CONFIG_USB_ANNOUNCE_NEW_DEVICES=y -- cgit v1.2.3-59-g8ed1b From c19345ea65a86c0936a3ce04a4035532c77f0187 Mon Sep 17 00:00:00 2001 From: Marek Szyprowski Date: Fri, 9 Oct 2020 15:49:07 +0200 Subject: ARM: multi_v7_defconfig: enable sound driver for Midas platform Sound driver for Midas platform (Exnyos4412 SoC based) has been recently merged, so enable it for tests like other sound drivers for Exynos based boards. Signed-off-by: Marek Szyprowski Link: https://lore.kernel.org/r/20201009134907.4578-1-m.szyprowski@samsung.com Signed-off-by: Krzysztof Kozlowski --- arch/arm/configs/multi_v7_defconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm') diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig index e731cdf7c88c..138a9e8fe35d 100644 --- a/arch/arm/configs/multi_v7_defconfig +++ b/arch/arm/configs/multi_v7_defconfig @@ -737,6 +737,7 @@ CONFIG_SND_SOC_SMDK_WM8994_PCM=m CONFIG_SND_SOC_SNOW=m CONFIG_SND_SOC_ODROID=m CONFIG_SND_SOC_ARNDALE=m +CONFIG_SND_SOC_SAMSUNG_MIDAS_WM1811=m CONFIG_SND_SOC_SH4_FSI=m CONFIG_SND_SOC_RCAR=m CONFIG_SND_SOC_STI=m -- cgit v1.2.3-59-g8ed1b From ecc1ff532b499d20304a4f682247137025814c34 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 15 Oct 2020 20:20:41 +0200 Subject: ARM: dts: exynos: fix roles of USB 3.0 ports on Odroid XU On Odroid XU board the USB3-0 port is a microUSB and USB3-1 port is USB type A (host). The roles were copied from Odroid XU3 (Exynos5422) design which has it reversed. Fixes: 8149afe4dbf9 ("ARM: dts: exynos: Add initial support for Odroid XU board") Signed-off-by: Krzysztof Kozlowski Cc: Link: https://lore.kernel.org/r/20201015182044.480562-1-krzk@kernel.org Tested-by: Gabriel Ribba Esteva --- arch/arm/boot/dts/exynos5410-odroidxu.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/exynos5410-odroidxu.dts b/arch/arm/boot/dts/exynos5410-odroidxu.dts index 75b4150c26d7..f4727a823571 100644 --- a/arch/arm/boot/dts/exynos5410-odroidxu.dts +++ b/arch/arm/boot/dts/exynos5410-odroidxu.dts @@ -637,11 +637,11 @@ }; &usbdrd_dwc3_0 { - dr_mode = "host"; + dr_mode = "peripheral"; }; &usbdrd_dwc3_1 { - dr_mode = "peripheral"; + dr_mode = "host"; }; &usbdrd3_0 { -- cgit v1.2.3-59-g8ed1b From 3d992fd8f4e0f09c980726308d2f2725587b32d6 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 15 Oct 2020 20:20:42 +0200 Subject: ARM: dts: exynos: fix USB 3.0 VBUS control and over-current pins on Exynos5410 The VBUS control (PWREN) and over-current pins of USB 3.0 DWC3 controllers are on Exynos5410 regular GPIOs. This is different than for example on Exynos5422 where these are special ETC pins with proper reset values (pulls, functions). Therefore these pins should be configured to enable proper USB 3.0 peripheral and host modes. This also fixes over-current warning: [ 6.024658] usb usb4-port1: over-current condition [ 6.028271] usb usb3-port1: over-current condition Fixes: cb0896562228 ("ARM: dts: exynos: Add USB to Exynos5410") Signed-off-by: Krzysztof Kozlowski Cc: Link: https://lore.kernel.org/r/20201015182044.480562-2-krzk@kernel.org Tested-by: Gabriel Ribba Esteva --- arch/arm/boot/dts/exynos5410-pinctrl.dtsi | 28 ++++++++++++++++++++++++++++ arch/arm/boot/dts/exynos5410.dtsi | 4 ++++ 2 files changed, 32 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/exynos5410-pinctrl.dtsi b/arch/arm/boot/dts/exynos5410-pinctrl.dtsi index e5d0a2a4f648..d0aa18443a69 100644 --- a/arch/arm/boot/dts/exynos5410-pinctrl.dtsi +++ b/arch/arm/boot/dts/exynos5410-pinctrl.dtsi @@ -560,6 +560,34 @@ interrupt-controller; #interrupt-cells = <2>; }; + + usb3_1_oc: usb3-1-oc { + samsung,pins = "gpk2-4", "gpk2-5"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + usb3_1_vbusctrl: usb3-1-vbusctrl { + samsung,pins = "gpk2-6", "gpk2-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + usb3_0_oc: usb3-0-oc { + samsung,pins = "gpk3-0", "gpk3-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + usb3_0_vbusctrl: usb3-0-vbusctrl { + samsung,pins = "gpk3-2", "gpk3-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; }; &pinctrl_2 { diff --git a/arch/arm/boot/dts/exynos5410.dtsi b/arch/arm/boot/dts/exynos5410.dtsi index 60a87684b1af..584ce62361b1 100644 --- a/arch/arm/boot/dts/exynos5410.dtsi +++ b/arch/arm/boot/dts/exynos5410.dtsi @@ -390,6 +390,8 @@ &usbdrd3_0 { clocks = <&clock CLK_USBD300>; clock-names = "usbdrd30"; + pinctrl-names = "default"; + pinctrl-0 = <&usb3_0_oc>, <&usb3_0_vbusctrl>; }; &usbdrd_phy0 { @@ -401,6 +403,8 @@ &usbdrd3_1 { clocks = <&clock CLK_USBD301>; clock-names = "usbdrd30"; + pinctrl-names = "default"; + pinctrl-0 = <&usb3_1_oc>, <&usb3_1_vbusctrl>; }; &usbdrd_dwc3_1 { -- cgit v1.2.3-59-g8ed1b From bd7e7ff56feea7810df900fb09c9741d259861d9 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 15 Oct 2020 20:20:43 +0200 Subject: ARM: dts: exynos: fix USB 3.0 pins supply being turned off on Odroid XU On Odroid XU LDO12 and LDO15 supplies the power to USB 3.0 blocks but the GPK GPIO pins are supplied by LDO7 (VDDQ_LCD). LDO7 also supplies GPJ GPIO pins. The Exynos pinctrl driver does not take any supplies, so to have entire GPIO block always available, make the regulator always on. Fixes: 88644b4c750b ("ARM: dts: exynos: Configure PWM, usb3503, PMIC and thermal on Odroid XU board") Signed-off-by: Krzysztof Kozlowski Cc: Link: https://lore.kernel.org/r/20201015182044.480562-3-krzk@kernel.org Tested-by: Gabriel Ribba Esteva --- arch/arm/boot/dts/exynos5410-odroidxu.dts | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/exynos5410-odroidxu.dts b/arch/arm/boot/dts/exynos5410-odroidxu.dts index f4727a823571..bd1d8499a108 100644 --- a/arch/arm/boot/dts/exynos5410-odroidxu.dts +++ b/arch/arm/boot/dts/exynos5410-odroidxu.dts @@ -327,6 +327,8 @@ regulator-name = "vddq_lcd"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; + /* Supplies also GPK and GPJ */ + regulator-always-on; }; ldo8_reg: LDO8 { -- cgit v1.2.3-59-g8ed1b From 4b6533c04ad97abeb6011f3028005aa62bb7737b Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 15 Oct 2020 20:20:44 +0200 Subject: ARM: dts: exynos: disable pull up of USB 3.0 over-current on Odroid XU The Odroid XU has external pull ups for USB 3.0 over-current pins, so disable the internal one. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20201015182044.480562-4-krzk@kernel.org Tested-by: Gabriel Ribba Esteva --- arch/arm/boot/dts/exynos5410-odroidxu.dts | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/exynos5410-odroidxu.dts b/arch/arm/boot/dts/exynos5410-odroidxu.dts index bd1d8499a108..dd300cea6a20 100644 --- a/arch/arm/boot/dts/exynos5410-odroidxu.dts +++ b/arch/arm/boot/dts/exynos5410-odroidxu.dts @@ -638,6 +638,16 @@ vtmu-supply = <&ldo10_reg>; }; +&usb3_0_oc { + /* External pull up */ + samsung,pin-pud = ; +}; + +&usb3_1_oc { + /* External pull up */ + samsung,pin-pud = ; +}; + &usbdrd_dwc3_0 { dr_mode = "peripheral"; }; -- cgit v1.2.3-59-g8ed1b From 214a7c874e266f79486f31465077d67957f18010 Mon Sep 17 00:00:00 2001 From: Serge Semin Date: Tue, 20 Oct 2020 14:59:34 +0300 Subject: ARM: dts: exynos: Correct DWC USB3 compatible string Syonpsys IP cores are supposed to be defined with "snps" vendor-prefix. Use it instead of the deprecated "synopsys" one. Signed-off-by: Serge Semin Link: https://lore.kernel.org/r/20201020115959.2658-5-Sergey.Semin@baikalelectronics.ru Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos5250.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi index bd2d8835dd36..d909ce8cac27 100644 --- a/arch/arm/boot/dts/exynos5250.dtsi +++ b/arch/arm/boot/dts/exynos5250.dtsi @@ -636,7 +636,7 @@ ranges; usbdrd_dwc3: dwc3@12000000 { - compatible = "synopsys,dwc3"; + compatible = "snps,dwc3"; reg = <0x12000000 0x10000>; interrupts = ; phys = <&usbdrd_phy 0>, <&usbdrd_phy 1>; -- cgit v1.2.3-59-g8ed1b From 3e667f65cdc324be140a99179041a08b33ee61f5 Mon Sep 17 00:00:00 2001 From: Serge Semin Date: Tue, 20 Oct 2020 14:59:49 +0300 Subject: ARM: dts: exynos: Harmonize DWC USB3 DT nodes name In accordance with the DWC USB3 bindings the corresponding node name is suppose to comply with the Generic USB HCD DT schema, which requires the USB nodes to have the name acceptable by the regexp: "^usb(@.*)?" . Make sure the "snps,dwc3"-compatible nodes are correctly named. Signed-off-by: Serge Semin Link: https://lore.kernel.org/r/20201020115959.2658-20-Sergey.Semin@baikalelectronics.ru Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos5250.dtsi | 2 +- arch/arm/boot/dts/exynos54xx.dtsi | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi index d909ce8cac27..84677332a5a2 100644 --- a/arch/arm/boot/dts/exynos5250.dtsi +++ b/arch/arm/boot/dts/exynos5250.dtsi @@ -635,7 +635,7 @@ #size-cells = <1>; ranges; - usbdrd_dwc3: dwc3@12000000 { + usbdrd_dwc3: usb@12000000 { compatible = "snps,dwc3"; reg = <0x12000000 0x10000>; interrupts = ; diff --git a/arch/arm/boot/dts/exynos54xx.dtsi b/arch/arm/boot/dts/exynos54xx.dtsi index 8aa5117e58ce..339243d19a80 100644 --- a/arch/arm/boot/dts/exynos54xx.dtsi +++ b/arch/arm/boot/dts/exynos54xx.dtsi @@ -148,7 +148,7 @@ #size-cells = <1>; ranges; - usbdrd_dwc3_0: dwc3@12000000 { + usbdrd_dwc3_0: usb@12000000 { compatible = "snps,dwc3"; reg = <0x12000000 0x10000>; interrupts = ; @@ -170,7 +170,7 @@ #size-cells = <1>; ranges; - usbdrd_dwc3_1: dwc3@12400000 { + usbdrd_dwc3_1: usb@12400000 { compatible = "snps,dwc3"; reg = <0x12400000 0x10000>; phys = <&usbdrd_phy1 0>, <&usbdrd_phy1 1>; -- cgit v1.2.3-59-g8ed1b From b35f80f2e3229ddc59a616ec0f085ef73278c3bf Mon Sep 17 00:00:00 2001 From: Lukasz Luba Date: Wed, 8 Jul 2020 16:34:20 +0100 Subject: ARM: dts: exynos: Remove interrupts from DMC controller in Exynos5422 The interrupts in Dynamic Memory Controller in Exynos5422 and Odroid XU3-family boards are no longer needed. They have been used in order to workaround some issues in scheduled work in devfreq. Now when the devfreq framework design is improved, remove the interrupt driven approach and rely on devfreq monitoring mechanism with fixed intervals. Reported-by: Willy Wolff Signed-off-by: Lukasz Luba Link: https://lore.kernel.org/r/20200708153420.29484-3-lukasz.luba@arm.com Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos5420.dtsi | 3 --- 1 file changed, 3 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index 83580f076a58..23a8fd5c8a6e 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -240,9 +240,6 @@ dmc: memory-controller@10c20000 { compatible = "samsung,exynos5422-dmc"; reg = <0x10c20000 0x10000>, <0x10c30000 0x10000>; - interrupt-parent = <&combiner>; - interrupts = <16 0>, <16 1>; - interrupt-names = "drex_0", "drex_1"; clocks = <&clock CLK_FOUT_SPLL>, <&clock CLK_MOUT_SCLK_SPLL>, <&clock CLK_FF_DOUT_SPLL2>, -- cgit v1.2.3-59-g8ed1b From e9a2f8b599d0bc22a1b13e69527246ac39c697b4 Mon Sep 17 00:00:00 2001 From: Ard Biesheuvel Date: Sun, 11 Oct 2020 10:20:16 +0100 Subject: ARM: 9011/1: centralize phys-to-virt conversion of DT/ATAGS address Before moving the DT mapping out of the linear region, let's prepare for this change by removing all the phys-to-virt translations of the __atags_pointer variable, and perform this translation only once at setup time. Tested-by: Linus Walleij Reviewed-by: Linus Walleij Acked-by: Nicolas Pitre Signed-off-by: Ard Biesheuvel Signed-off-by: Russell King --- arch/arm/include/asm/prom.h | 4 ++-- arch/arm/kernel/atags.h | 4 ++-- arch/arm/kernel/atags_parse.c | 6 +++--- arch/arm/kernel/devtree.c | 6 +++--- arch/arm/kernel/setup.c | 14 +++++++++----- arch/arm/mm/mmu.c | 4 ++-- 6 files changed, 21 insertions(+), 17 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/include/asm/prom.h b/arch/arm/include/asm/prom.h index 1e36c40533c1..402e3f34c7ed 100644 --- a/arch/arm/include/asm/prom.h +++ b/arch/arm/include/asm/prom.h @@ -9,12 +9,12 @@ #ifdef CONFIG_OF -extern const struct machine_desc *setup_machine_fdt(unsigned int dt_phys); +extern const struct machine_desc *setup_machine_fdt(void *dt_virt); extern void __init arm_dt_init_cpu_maps(void); #else /* CONFIG_OF */ -static inline const struct machine_desc *setup_machine_fdt(unsigned int dt_phys) +static inline const struct machine_desc *setup_machine_fdt(void *dt_virt) { return NULL; } diff --git a/arch/arm/kernel/atags.h b/arch/arm/kernel/atags.h index 067e12edc341..f2819c25b602 100644 --- a/arch/arm/kernel/atags.h +++ b/arch/arm/kernel/atags.h @@ -2,11 +2,11 @@ void convert_to_tag_list(struct tag *tags); #ifdef CONFIG_ATAGS -const struct machine_desc *setup_machine_tags(phys_addr_t __atags_pointer, +const struct machine_desc *setup_machine_tags(void *__atags_vaddr, unsigned int machine_nr); #else static inline const struct machine_desc * __init __noreturn -setup_machine_tags(phys_addr_t __atags_pointer, unsigned int machine_nr) +setup_machine_tags(void *__atags_vaddr, unsigned int machine_nr) { early_print("no ATAGS support: can't continue\n"); while (true); diff --git a/arch/arm/kernel/atags_parse.c b/arch/arm/kernel/atags_parse.c index 6c12d9fe694e..373b61f9a4f0 100644 --- a/arch/arm/kernel/atags_parse.c +++ b/arch/arm/kernel/atags_parse.c @@ -174,7 +174,7 @@ static void __init squash_mem_tags(struct tag *tag) } const struct machine_desc * __init -setup_machine_tags(phys_addr_t __atags_pointer, unsigned int machine_nr) +setup_machine_tags(void *atags_vaddr, unsigned int machine_nr) { struct tag *tags = (struct tag *)&default_tags; const struct machine_desc *mdesc = NULL, *p; @@ -195,8 +195,8 @@ setup_machine_tags(phys_addr_t __atags_pointer, unsigned int machine_nr) if (!mdesc) return NULL; - if (__atags_pointer) - tags = phys_to_virt(__atags_pointer); + if (atags_vaddr) + tags = atags_vaddr; else if (mdesc->atag_offset) tags = (void *)(PAGE_OFFSET + mdesc->atag_offset); diff --git a/arch/arm/kernel/devtree.c b/arch/arm/kernel/devtree.c index 7f0745a97e20..28311dd0fee6 100644 --- a/arch/arm/kernel/devtree.c +++ b/arch/arm/kernel/devtree.c @@ -203,12 +203,12 @@ static const void * __init arch_get_next_mach(const char *const **match) /** * setup_machine_fdt - Machine setup when an dtb was passed to the kernel - * @dt_phys: physical address of dt blob + * @dt_virt: virtual address of dt blob * * If a dtb was passed to the kernel in r2, then use it to choose the * correct machine_desc and to setup the system. */ -const struct machine_desc * __init setup_machine_fdt(unsigned int dt_phys) +const struct machine_desc * __init setup_machine_fdt(void *dt_virt) { const struct machine_desc *mdesc, *mdesc_best = NULL; @@ -221,7 +221,7 @@ const struct machine_desc * __init setup_machine_fdt(unsigned int dt_phys) mdesc_best = &__mach_desc_GENERIC_DT; #endif - if (!dt_phys || !early_init_dt_verify(phys_to_virt(dt_phys))) + if (!dt_virt || !early_init_dt_verify(dt_virt)) return NULL; mdesc = of_flat_dt_match_machine(mdesc_best, arch_get_next_mach); diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c index 3f65d0ac9f63..306bcd9844be 100644 --- a/arch/arm/kernel/setup.c +++ b/arch/arm/kernel/setup.c @@ -89,6 +89,7 @@ unsigned int cacheid __read_mostly; EXPORT_SYMBOL(cacheid); unsigned int __atags_pointer __initdata; +void *atags_vaddr __initdata; unsigned int system_rev; EXPORT_SYMBOL(system_rev); @@ -1081,19 +1082,22 @@ void __init hyp_mode_check(void) void __init setup_arch(char **cmdline_p) { - const struct machine_desc *mdesc; + const struct machine_desc *mdesc = NULL; + + if (__atags_pointer) + atags_vaddr = phys_to_virt(__atags_pointer); setup_processor(); - mdesc = setup_machine_fdt(__atags_pointer); + if (atags_vaddr) + mdesc = setup_machine_fdt(atags_vaddr); if (!mdesc) - mdesc = setup_machine_tags(__atags_pointer, __machine_arch_type); + mdesc = setup_machine_tags(atags_vaddr, __machine_arch_type); if (!mdesc) { early_print("\nError: invalid dtb and unrecognized/unsupported machine ID\n"); early_print(" r1=0x%08x, r2=0x%08x\n", __machine_arch_type, __atags_pointer); if (__atags_pointer) - early_print(" r2[]=%*ph\n", 16, - phys_to_virt(__atags_pointer)); + early_print(" r2[]=%*ph\n", 16, atags_vaddr); dump_machine_table(); } diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c index ab69250a86bc..55991fe60054 100644 --- a/arch/arm/mm/mmu.c +++ b/arch/arm/mm/mmu.c @@ -1489,7 +1489,7 @@ static void __init map_lowmem(void) } #ifdef CONFIG_ARM_PV_FIXUP -extern unsigned long __atags_pointer; +extern void *atags_vaddr; typedef void pgtables_remap(long long offset, unsigned long pgd, void *bdata); pgtables_remap lpae_pgtables_remap_asm; @@ -1520,7 +1520,7 @@ static void __init early_paging_init(const struct machine_desc *mdesc) */ lpae_pgtables_remap = (pgtables_remap *)(unsigned long)__pa(lpae_pgtables_remap_asm); pa_pgd = __pa(swapper_pg_dir); - boot_data = __va(__atags_pointer); + boot_data = atags_vaddr; barrier(); pr_info("Switching physical address space to 0x%08llx\n", -- cgit v1.2.3-59-g8ed1b From 7a1be318f5795cb66fa0dc86b3ace427fe68057f Mon Sep 17 00:00:00 2001 From: Ard Biesheuvel Date: Sun, 11 Oct 2020 10:21:37 +0100 Subject: ARM: 9012/1: move device tree mapping out of linear region On ARM, setting up the linear region is tricky, given the constraints around placement and alignment of the memblocks, and how the kernel itself as well as the DT are placed in physical memory. Let's simplify matters a bit, by moving the device tree mapping to the top of the address space, right between the end of the vmalloc region and the start of the the fixmap region, and create a read-only mapping for it that is independent of the size of the linear region, and how it is organized. Since this region was formerly used as a guard region, which will now be populated fully on LPAE builds by this read-only mapping (which will still be able to function as a guard region for stray writes), bump the start of the [underutilized] fixmap region by 512 KB as well, to ensure that there is always a proper guard region here. Doing so still leaves ample room for the fixmap space, even with NR_CPUS set to its maximum value of 32. Tested-by: Linus Walleij Reviewed-by: Linus Walleij Reviewed-by: Nicolas Pitre Signed-off-by: Ard Biesheuvel Signed-off-by: Russell King --- Documentation/arm/memory.rst | 7 ++++++- arch/arm/include/asm/fixmap.h | 2 +- arch/arm/include/asm/memory.h | 5 +++++ arch/arm/kernel/head.S | 5 ++--- arch/arm/kernel/setup.c | 11 ++++++++--- arch/arm/mm/init.c | 1 - arch/arm/mm/mmu.c | 20 ++++++++++++++------ arch/arm/mm/pv-fixup-asm.S | 4 ++-- 8 files changed, 38 insertions(+), 17 deletions(-) (limited to 'arch/arm') diff --git a/Documentation/arm/memory.rst b/Documentation/arm/memory.rst index 0521b4ce5c96..34bb23c44a71 100644 --- a/Documentation/arm/memory.rst +++ b/Documentation/arm/memory.rst @@ -45,9 +45,14 @@ fffe8000 fffeffff DTCM mapping area for platforms with fffe0000 fffe7fff ITCM mapping area for platforms with ITCM mounted inside the CPU. -ffc00000 ffefffff Fixmap mapping region. Addresses provided +ffc80000 ffefffff Fixmap mapping region. Addresses provided by fix_to_virt() will be located here. +ffc00000 ffc7ffff Guard region + +ff800000 ffbfffff Permanent, fixed read-only mapping of the + firmware provided DT blob + fee00000 feffffff Mapping of PCI I/O space. This is a static mapping within the vmalloc space. diff --git a/arch/arm/include/asm/fixmap.h b/arch/arm/include/asm/fixmap.h index fc56fc3e1931..9575b404019c 100644 --- a/arch/arm/include/asm/fixmap.h +++ b/arch/arm/include/asm/fixmap.h @@ -2,7 +2,7 @@ #ifndef _ASM_FIXMAP_H #define _ASM_FIXMAP_H -#define FIXADDR_START 0xffc00000UL +#define FIXADDR_START 0xffc80000UL #define FIXADDR_END 0xfff00000UL #define FIXADDR_TOP (FIXADDR_END - PAGE_SIZE) diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h index 99035b5891ef..bb79e52aeb90 100644 --- a/arch/arm/include/asm/memory.h +++ b/arch/arm/include/asm/memory.h @@ -67,6 +67,10 @@ */ #define XIP_VIRT_ADDR(physaddr) (MODULES_VADDR + ((physaddr) & 0x000fffff)) +#define FDT_FIXED_BASE UL(0xff800000) +#define FDT_FIXED_SIZE (2 * PMD_SIZE) +#define FDT_VIRT_ADDR(physaddr) ((void *)(FDT_FIXED_BASE | (physaddr) % PMD_SIZE)) + #if !defined(CONFIG_SMP) && !defined(CONFIG_ARM_LPAE) /* * Allow 16MB-aligned ioremap pages @@ -107,6 +111,7 @@ extern unsigned long vectors_base; #define MODULES_VADDR PAGE_OFFSET #define XIP_VIRT_ADDR(physaddr) (physaddr) +#define FDT_VIRT_ADDR(physaddr) ((void *)(physaddr)) #endif /* !CONFIG_MMU */ diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S index f8904227e7fd..9b18d8c66129 100644 --- a/arch/arm/kernel/head.S +++ b/arch/arm/kernel/head.S @@ -275,9 +275,8 @@ __create_page_tables: */ mov r0, r2, lsr #SECTION_SHIFT movs r0, r0, lsl #SECTION_SHIFT - subne r3, r0, r8 - addne r3, r3, #PAGE_OFFSET - addne r3, r4, r3, lsr #(SECTION_SHIFT - PMD_ORDER) + ldrne r3, =FDT_FIXED_BASE >> (SECTION_SHIFT - PMD_ORDER) + addne r3, r3, r4 orrne r6, r7, r0 strne r6, [r3], #1 << PMD_ORDER addne r6, r6, #1 << SECTION_SHIFT diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c index 306bcd9844be..694aa6b4bd03 100644 --- a/arch/arm/kernel/setup.c +++ b/arch/arm/kernel/setup.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include #include @@ -89,7 +90,6 @@ unsigned int cacheid __read_mostly; EXPORT_SYMBOL(cacheid); unsigned int __atags_pointer __initdata; -void *atags_vaddr __initdata; unsigned int system_rev; EXPORT_SYMBOL(system_rev); @@ -1083,13 +1083,18 @@ void __init hyp_mode_check(void) void __init setup_arch(char **cmdline_p) { const struct machine_desc *mdesc = NULL; + void *atags_vaddr = NULL; if (__atags_pointer) - atags_vaddr = phys_to_virt(__atags_pointer); + atags_vaddr = FDT_VIRT_ADDR(__atags_pointer); setup_processor(); - if (atags_vaddr) + if (atags_vaddr) { mdesc = setup_machine_fdt(atags_vaddr); + if (mdesc) + memblock_reserve(__atags_pointer, + fdt_totalsize(atags_vaddr)); + } if (!mdesc) mdesc = setup_machine_tags(atags_vaddr, __machine_arch_type); if (!mdesc) { diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c index d57112a276f5..a391804c7ce3 100644 --- a/arch/arm/mm/init.c +++ b/arch/arm/mm/init.c @@ -223,7 +223,6 @@ void __init arm_memblock_init(const struct machine_desc *mdesc) if (mdesc->reserve) mdesc->reserve(); - early_init_fdt_reserve_self(); early_init_fdt_scan_reserved_mem(); /* reserve memory for DMA contiguous allocations */ diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c index 55991fe60054..fa259825310c 100644 --- a/arch/arm/mm/mmu.c +++ b/arch/arm/mm/mmu.c @@ -39,6 +39,8 @@ #include "mm.h" #include "tcm.h" +extern unsigned long __atags_pointer; + /* * empty_zero_page is a special page that is used for * zero-initialized data and COW. @@ -946,7 +948,7 @@ static void __init create_mapping(struct map_desc *md) return; } - if ((md->type == MT_DEVICE || md->type == MT_ROM) && + if (md->type == MT_DEVICE && md->virtual >= PAGE_OFFSET && md->virtual < FIXADDR_START && (md->virtual < VMALLOC_START || md->virtual >= VMALLOC_END)) { pr_warn("BUG: mapping for 0x%08llx at 0x%08lx out of vmalloc space\n", @@ -1333,6 +1335,15 @@ static void __init devicemaps_init(const struct machine_desc *mdesc) for (addr = VMALLOC_START; addr < (FIXADDR_TOP & PMD_MASK); addr += PMD_SIZE) pmd_clear(pmd_off_k(addr)); + if (__atags_pointer) { + /* create a read-only mapping of the device tree */ + map.pfn = __phys_to_pfn(__atags_pointer & SECTION_MASK); + map.virtual = FDT_FIXED_BASE; + map.length = FDT_FIXED_SIZE; + map.type = MT_ROM; + create_mapping(&map); + } + /* * Map the kernel if it is XIP. * It is always first in the modulearea. @@ -1489,8 +1500,7 @@ static void __init map_lowmem(void) } #ifdef CONFIG_ARM_PV_FIXUP -extern void *atags_vaddr; -typedef void pgtables_remap(long long offset, unsigned long pgd, void *bdata); +typedef void pgtables_remap(long long offset, unsigned long pgd); pgtables_remap lpae_pgtables_remap_asm; /* @@ -1503,7 +1513,6 @@ static void __init early_paging_init(const struct machine_desc *mdesc) unsigned long pa_pgd; unsigned int cr, ttbcr; long long offset; - void *boot_data; if (!mdesc->pv_fixup) return; @@ -1520,7 +1529,6 @@ static void __init early_paging_init(const struct machine_desc *mdesc) */ lpae_pgtables_remap = (pgtables_remap *)(unsigned long)__pa(lpae_pgtables_remap_asm); pa_pgd = __pa(swapper_pg_dir); - boot_data = atags_vaddr; barrier(); pr_info("Switching physical address space to 0x%08llx\n", @@ -1556,7 +1564,7 @@ static void __init early_paging_init(const struct machine_desc *mdesc) * needs to be assembly. It's fairly simple, as we're using the * temporary tables setup by the initial assembly code. */ - lpae_pgtables_remap(offset, pa_pgd, boot_data); + lpae_pgtables_remap(offset, pa_pgd); /* Re-enable the caches and cacheable TLB walks */ asm volatile("mcr p15, 0, %0, c2, c0, 2" : : "r" (ttbcr)); diff --git a/arch/arm/mm/pv-fixup-asm.S b/arch/arm/mm/pv-fixup-asm.S index 8eade0416739..5c5e1952000a 100644 --- a/arch/arm/mm/pv-fixup-asm.S +++ b/arch/arm/mm/pv-fixup-asm.S @@ -39,8 +39,8 @@ ENTRY(lpae_pgtables_remap_asm) /* Update level 2 entries for the boot data */ add r7, r2, #0x1000 - add r7, r7, r3, lsr #SECTION_SHIFT - L2_ORDER - bic r7, r7, #(1 << L2_ORDER) - 1 + movw r3, #FDT_FIXED_BASE >> (SECTION_SHIFT - L2_ORDER) + add r7, r7, r3 ldrd r4, r5, [r7] adds r4, r4, r0 adc r5, r5, r1 -- cgit v1.2.3-59-g8ed1b From d5d44e7e3507b0ad868f68e0c5bca6a57afa1b8b Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Sun, 25 Oct 2020 23:50:09 +0100 Subject: ARM: 9013/2: Disable KASan instrumentation for some code Disable instrumentation for arch/arm/boot/compressed/* since that code is executed before the kernel has even set up its mappings and definately out of scope for KASan. Disable instrumentation of arch/arm/vdso/* because that code is not linked with the kernel image, so the KASan management code would fail to link. Disable instrumentation of arch/arm/mm/physaddr.c. See commit ec6d06efb0ba ("arm64: Add support for CONFIG_DEBUG_VIRTUAL") for more details. Disable kasan check in the function unwind_pop_register because it does not matter that kasan checks failed when unwind_pop_register() reads the stack memory of a task. Cc: Andrey Ryabinin Cc: Alexander Potapenko Cc: Dmitry Vyukov Cc: kasan-dev@googlegroups.com Reviewed-by: Ard Biesheuvel Tested-by: Ard Biesheuvel # QEMU/KVM/mach-virt/LPAE/8G Tested-by: Florian Fainelli # Brahma SoCs Tested-by: Ahmad Fatoum # i.MX6Q Reported-by: Florian Fainelli Reported-by: Marc Zyngier Signed-off-by: Abbott Liu Signed-off-by: Florian Fainelli Signed-off-by: Linus Walleij Signed-off-by: Russell King --- arch/arm/boot/compressed/Makefile | 1 + arch/arm/kernel/unwind.c | 6 +++++- arch/arm/mm/Makefile | 2 ++ arch/arm/vdso/Makefile | 2 ++ 4 files changed, 10 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/compressed/Makefile b/arch/arm/boot/compressed/Makefile index 47f001ca5499..a815b1ae990d 100644 --- a/arch/arm/boot/compressed/Makefile +++ b/arch/arm/boot/compressed/Makefile @@ -24,6 +24,7 @@ OBJS += hyp-stub.o endif GCOV_PROFILE := n +KASAN_SANITIZE := n # Prevents link failures: __sanitizer_cov_trace_pc() is not linked in. KCOV_INSTRUMENT := n diff --git a/arch/arm/kernel/unwind.c b/arch/arm/kernel/unwind.c index d2bd0df2318d..f35eb584a18a 100644 --- a/arch/arm/kernel/unwind.c +++ b/arch/arm/kernel/unwind.c @@ -236,7 +236,11 @@ static int unwind_pop_register(struct unwind_ctrl_block *ctrl, if (*vsp >= (unsigned long *)ctrl->sp_high) return -URC_FAILURE; - ctrl->vrs[reg] = *(*vsp)++; + /* Use READ_ONCE_NOCHECK here to avoid this memory access + * from being tracked by KASAN. + */ + ctrl->vrs[reg] = READ_ONCE_NOCHECK(*(*vsp)); + (*vsp)++; return URC_OK; } diff --git a/arch/arm/mm/Makefile b/arch/arm/mm/Makefile index 7cb1699fbfc4..99699c32d8a5 100644 --- a/arch/arm/mm/Makefile +++ b/arch/arm/mm/Makefile @@ -7,6 +7,7 @@ obj-y := extable.o fault.o init.o iomap.o obj-y += dma-mapping$(MMUEXT).o obj-$(CONFIG_MMU) += fault-armv.o flush.o idmap.o ioremap.o \ mmap.o pgd.o mmu.o pageattr.o +KASAN_SANITIZE_mmu.o := n ifneq ($(CONFIG_MMU),y) obj-y += nommu.o @@ -16,6 +17,7 @@ endif obj-$(CONFIG_ARM_PTDUMP_CORE) += dump.o obj-$(CONFIG_ARM_PTDUMP_DEBUGFS) += ptdump_debugfs.o obj-$(CONFIG_MODULES) += proc-syms.o +KASAN_SANITIZE_physaddr.o := n obj-$(CONFIG_DEBUG_VIRTUAL) += physaddr.o obj-$(CONFIG_ALIGNMENT_TRAP) += alignment.o diff --git a/arch/arm/vdso/Makefile b/arch/arm/vdso/Makefile index 150ce6e6a5d3..b558bee0e1f6 100644 --- a/arch/arm/vdso/Makefile +++ b/arch/arm/vdso/Makefile @@ -42,6 +42,8 @@ GCOV_PROFILE := n # Prevents link failures: __sanitizer_cov_trace_pc() is not linked in. KCOV_INSTRUMENT := n +KASAN_SANITIZE := n + # Force dependency $(obj)/vdso.o : $(obj)/vdso.so -- cgit v1.2.3-59-g8ed1b From d6d51a96c7d63b7450860a3037f2d62388286a52 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Sun, 25 Oct 2020 23:52:08 +0100 Subject: ARM: 9014/2: Replace string mem* functions for KASan Functions like memset()/memmove()/memcpy() do a lot of memory accesses. If a bad pointer is passed to one of these functions it is important to catch this. Compiler instrumentation cannot do this since these functions are written in assembly. KASan replaces these memory functions with instrumented variants. The original functions are declared as weak symbols so that the strong definitions in mm/kasan/kasan.c can replace them. The original functions have aliases with a '__' prefix in their name, so we can call the non-instrumented variant if needed. We must use __memcpy()/__memset() in place of memcpy()/memset() when we copy .data to RAM and when we clear .bss, because kasan_early_init cannot be called before the initialization of .data and .bss. For the kernel compression and EFI libstub's custom string libraries we need a special quirk: even if these are built without KASan enabled, they rely on the global headers for their custom string libraries, which means that e.g. memcpy() will be defined to __memcpy() and we get link failures. Since these implementations are written i C rather than assembly we use e.g. __alias(memcpy) to redirected any users back to the local implementation. Cc: Andrey Ryabinin Cc: Alexander Potapenko Cc: Dmitry Vyukov Cc: kasan-dev@googlegroups.com Reviewed-by: Ard Biesheuvel Tested-by: Ard Biesheuvel # QEMU/KVM/mach-virt/LPAE/8G Tested-by: Florian Fainelli # Brahma SoCs Tested-by: Ahmad Fatoum # i.MX6Q Reported-by: Russell King - ARM Linux Signed-off-by: Ahmad Fatoum Signed-off-by: Abbott Liu Signed-off-by: Florian Fainelli Signed-off-by: Linus Walleij Signed-off-by: Russell King --- arch/arm/boot/compressed/string.c | 19 +++++++++++++++++++ arch/arm/include/asm/string.h | 26 ++++++++++++++++++++++++++ arch/arm/kernel/head-common.S | 4 ++-- arch/arm/lib/memcpy.S | 3 +++ arch/arm/lib/memmove.S | 5 ++++- arch/arm/lib/memset.S | 3 +++ 6 files changed, 57 insertions(+), 3 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/compressed/string.c b/arch/arm/boot/compressed/string.c index ade5079bebbf..8c0fa276d994 100644 --- a/arch/arm/boot/compressed/string.c +++ b/arch/arm/boot/compressed/string.c @@ -7,6 +7,25 @@ #include +/* + * The decompressor is built without KASan but uses the same redirects as the + * rest of the kernel when CONFIG_KASAN is enabled, defining e.g. memcpy() + * to __memcpy() but since we are not linking with the main kernel string + * library in the decompressor, that will lead to link failures. + * + * Undefine KASan's versions, define the wrapped functions and alias them to + * the right names so that when e.g. __memcpy() appear in the code, it will + * still be linked to this local version of memcpy(). + */ +#ifdef CONFIG_KASAN +#undef memcpy +#undef memmove +#undef memset +void *__memcpy(void *__dest, __const void *__src, size_t __n) __alias(memcpy); +void *__memmove(void *__dest, __const void *__src, size_t count) __alias(memmove); +void *__memset(void *s, int c, size_t count) __alias(memset); +#endif + void *memcpy(void *__dest, __const void *__src, size_t __n) { int i = 0; diff --git a/arch/arm/include/asm/string.h b/arch/arm/include/asm/string.h index 111a1d8a41dd..6c607c68f3ad 100644 --- a/arch/arm/include/asm/string.h +++ b/arch/arm/include/asm/string.h @@ -5,6 +5,9 @@ /* * We don't do inline string functions, since the * optimised inline asm versions are not small. + * + * The __underscore versions of some functions are for KASan to be able + * to replace them with instrumented versions. */ #define __HAVE_ARCH_STRRCHR @@ -15,15 +18,18 @@ extern char * strchr(const char * s, int c); #define __HAVE_ARCH_MEMCPY extern void * memcpy(void *, const void *, __kernel_size_t); +extern void *__memcpy(void *dest, const void *src, __kernel_size_t n); #define __HAVE_ARCH_MEMMOVE extern void * memmove(void *, const void *, __kernel_size_t); +extern void *__memmove(void *dest, const void *src, __kernel_size_t n); #define __HAVE_ARCH_MEMCHR extern void * memchr(const void *, int, __kernel_size_t); #define __HAVE_ARCH_MEMSET extern void * memset(void *, int, __kernel_size_t); +extern void *__memset(void *s, int c, __kernel_size_t n); #define __HAVE_ARCH_MEMSET32 extern void *__memset32(uint32_t *, uint32_t v, __kernel_size_t); @@ -39,4 +45,24 @@ static inline void *memset64(uint64_t *p, uint64_t v, __kernel_size_t n) return __memset64(p, v, n * 8, v >> 32); } +/* + * For files that are not instrumented (e.g. mm/slub.c) we + * must use non-instrumented versions of the mem* + * functions named __memcpy() etc. All such kernel code has + * been tagged with KASAN_SANITIZE_file.o = n, which means + * that the address sanitization argument isn't passed to the + * compiler, and __SANITIZE_ADDRESS__ is not set. As a result + * these defines kick in. + */ +#if defined(CONFIG_KASAN) && !defined(__SANITIZE_ADDRESS__) +#define memcpy(dst, src, len) __memcpy(dst, src, len) +#define memmove(dst, src, len) __memmove(dst, src, len) +#define memset(s, c, n) __memset(s, c, n) + +#ifndef __NO_FORTIFY +#define __NO_FORTIFY /* FORTIFY_SOURCE uses __builtin_memcpy, etc. */ +#endif + +#endif + #endif diff --git a/arch/arm/kernel/head-common.S b/arch/arm/kernel/head-common.S index 4a3982812a40..6840c7c60a85 100644 --- a/arch/arm/kernel/head-common.S +++ b/arch/arm/kernel/head-common.S @@ -95,7 +95,7 @@ __mmap_switched: THUMB( ldmia r4!, {r0, r1, r2, r3} ) THUMB( mov sp, r3 ) sub r2, r2, r1 - bl memcpy @ copy .data to RAM + bl __memcpy @ copy .data to RAM #endif ARM( ldmia r4!, {r0, r1, sp} ) @@ -103,7 +103,7 @@ __mmap_switched: THUMB( mov sp, r3 ) sub r2, r1, r0 mov r1, #0 - bl memset @ clear .bss + bl __memset @ clear .bss ldmia r4, {r0, r1, r2, r3} str r9, [r0] @ Save processor ID diff --git a/arch/arm/lib/memcpy.S b/arch/arm/lib/memcpy.S index 09a333153dc6..ad4625d16e11 100644 --- a/arch/arm/lib/memcpy.S +++ b/arch/arm/lib/memcpy.S @@ -58,6 +58,8 @@ /* Prototype: void *memcpy(void *dest, const void *src, size_t n); */ +.weak memcpy +ENTRY(__memcpy) ENTRY(mmiocpy) ENTRY(memcpy) @@ -65,3 +67,4 @@ ENTRY(memcpy) ENDPROC(memcpy) ENDPROC(mmiocpy) +ENDPROC(__memcpy) diff --git a/arch/arm/lib/memmove.S b/arch/arm/lib/memmove.S index b50e5770fb44..fd123ea5a5a4 100644 --- a/arch/arm/lib/memmove.S +++ b/arch/arm/lib/memmove.S @@ -24,12 +24,14 @@ * occurring in the opposite direction. */ +.weak memmove +ENTRY(__memmove) ENTRY(memmove) UNWIND( .fnstart ) subs ip, r0, r1 cmphi r2, ip - bls memcpy + bls __memcpy stmfd sp!, {r0, r4, lr} UNWIND( .fnend ) @@ -222,3 +224,4 @@ ENTRY(memmove) 18: backward_copy_shift push=24 pull=8 ENDPROC(memmove) +ENDPROC(__memmove) diff --git a/arch/arm/lib/memset.S b/arch/arm/lib/memset.S index 6ca4535c47fb..0e7ff0423f50 100644 --- a/arch/arm/lib/memset.S +++ b/arch/arm/lib/memset.S @@ -13,6 +13,8 @@ .text .align 5 +.weak memset +ENTRY(__memset) ENTRY(mmioset) ENTRY(memset) UNWIND( .fnstart ) @@ -132,6 +134,7 @@ UNWIND( .fnstart ) UNWIND( .fnend ) ENDPROC(memset) ENDPROC(mmioset) +ENDPROC(__memset) ENTRY(__memset32) UNWIND( .fnstart ) -- cgit v1.2.3-59-g8ed1b From c12366ba441da2f6f2b915410aca2b5b39c16514 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Sun, 25 Oct 2020 23:53:46 +0100 Subject: ARM: 9015/2: Define the virtual space of KASan's shadow region Define KASAN_SHADOW_OFFSET,KASAN_SHADOW_START and KASAN_SHADOW_END for the Arm kernel address sanitizer. We are "stealing" lowmem (the 4GB addressable by a 32bit architecture) out of the virtual address space to use as shadow memory for KASan as follows: +----+ 0xffffffff | | | | |-> Static kernel image (vmlinux) BSS and page table | |/ +----+ PAGE_OFFSET | | | | |-> Loadable kernel modules virtual address space area | |/ +----+ MODULES_VADDR = KASAN_SHADOW_END | | | | |-> The shadow area of kernel virtual address. | |/ +----+-> TASK_SIZE (start of kernel space) = KASAN_SHADOW_START the | | shadow address of MODULES_VADDR | | | | | | | | |-> The user space area in lowmem. The kernel address | | | sanitizer do not use this space, nor does it map it. | | | | | | | | | | | | | |/ ------ 0 0 .. TASK_SIZE is the memory that can be used by shared userspace/kernelspace. It us used for userspace processes and for passing parameters and memory buffers in system calls etc. We do not need to shadow this area. KASAN_SHADOW_START: This value begins with the MODULE_VADDR's shadow address. It is the start of kernel virtual space. Since we have modules to load, we need to cover also that area with shadow memory so we can find memory bugs in modules. KASAN_SHADOW_END This value is the 0x100000000's shadow address: the mapping that would be after the end of the kernel memory at 0xffffffff. It is the end of kernel address sanitizer shadow area. It is also the start of the module area. KASAN_SHADOW_OFFSET: This value is used to map an address to the corresponding shadow address by the following formula: shadow_addr = (address >> 3) + KASAN_SHADOW_OFFSET; As you would expect, >> 3 is equal to dividing by 8, meaning each byte in the shadow memory covers 8 bytes of kernel memory, so one bit shadow memory per byte of kernel memory is used. The KASAN_SHADOW_OFFSET is provided in a Kconfig option depending on the VMSPLIT layout of the system: the kernel and userspace can split up lowmem in different ways according to needs, so we calculate the shadow offset depending on this. When kasan is enabled, the definition of TASK_SIZE is not an 8-bit rotated constant, so we need to modify the TASK_SIZE access code in the *.s file. The kernel and modules may use different amounts of memory, according to the VMSPLIT configuration, which in turn determines the PAGE_OFFSET. We use the following KASAN_SHADOW_OFFSETs depending on how the virtual memory is split up: - 0x1f000000 if we have 1G userspace / 3G kernelspace split: - The kernel address space is 3G (0xc0000000) - PAGE_OFFSET is then set to 0x40000000 so the kernel static image (vmlinux) uses addresses 0x40000000 .. 0xffffffff - On top of that we have the MODULES_VADDR which under the worst case (using ARM instructions) is PAGE_OFFSET - 16M (0x01000000) = 0x3f000000 so the modules use addresses 0x3f000000 .. 0x3fffffff - So the addresses 0x3f000000 .. 0xffffffff need to be covered with shadow memory. That is 0xc1000000 bytes of memory. - 1/8 of that is needed for its shadow memory, so 0x18200000 bytes of shadow memory is needed. We "steal" that from the remaining lowmem. - The KASAN_SHADOW_START becomes 0x26e00000, to KASAN_SHADOW_END at 0x3effffff. - Now we can calculate the KASAN_SHADOW_OFFSET for any kernel address as 0x3f000000 needs to map to the first byte of shadow memory and 0xffffffff needs to map to the last byte of shadow memory. Since: SHADOW_ADDR = (address >> 3) + KASAN_SHADOW_OFFSET 0x26e00000 = (0x3f000000 >> 3) + KASAN_SHADOW_OFFSET KASAN_SHADOW_OFFSET = 0x26e00000 - (0x3f000000 >> 3) KASAN_SHADOW_OFFSET = 0x26e00000 - 0x07e00000 KASAN_SHADOW_OFFSET = 0x1f000000 - 0x5f000000 if we have 2G userspace / 2G kernelspace split: - The kernel space is 2G (0x80000000) - PAGE_OFFSET is set to 0x80000000 so the kernel static image uses 0x80000000 .. 0xffffffff. - On top of that we have the MODULES_VADDR which under the worst case (using ARM instructions) is PAGE_OFFSET - 16M (0x01000000) = 0x7f000000 so the modules use addresses 0x7f000000 .. 0x7fffffff - So the addresses 0x7f000000 .. 0xffffffff need to be covered with shadow memory. That is 0x81000000 bytes of memory. - 1/8 of that is needed for its shadow memory, so 0x10200000 bytes of shadow memory is needed. We "steal" that from the remaining lowmem. - The KASAN_SHADOW_START becomes 0x6ee00000, to KASAN_SHADOW_END at 0x7effffff. - Now we can calculate the KASAN_SHADOW_OFFSET for any kernel address as 0x7f000000 needs to map to the first byte of shadow memory and 0xffffffff needs to map to the last byte of shadow memory. Since: SHADOW_ADDR = (address >> 3) + KASAN_SHADOW_OFFSET 0x6ee00000 = (0x7f000000 >> 3) + KASAN_SHADOW_OFFSET KASAN_SHADOW_OFFSET = 0x6ee00000 - (0x7f000000 >> 3) KASAN_SHADOW_OFFSET = 0x6ee00000 - 0x0fe00000 KASAN_SHADOW_OFFSET = 0x5f000000 - 0x9f000000 if we have 3G userspace / 1G kernelspace split, and this is the default split for ARM: - The kernel address space is 1GB (0x40000000) - PAGE_OFFSET is set to 0xc0000000 so the kernel static image uses 0xc0000000 .. 0xffffffff. - On top of that we have the MODULES_VADDR which under the worst case (using ARM instructions) is PAGE_OFFSET - 16M (0x01000000) = 0xbf000000 so the modules use addresses 0xbf000000 .. 0xbfffffff - So the addresses 0xbf000000 .. 0xffffffff need to be covered with shadow memory. That is 0x41000000 bytes of memory. - 1/8 of that is needed for its shadow memory, so 0x08200000 bytes of shadow memory is needed. We "steal" that from the remaining lowmem. - The KASAN_SHADOW_START becomes 0xb6e00000, to KASAN_SHADOW_END at 0xbfffffff. - Now we can calculate the KASAN_SHADOW_OFFSET for any kernel address as 0xbf000000 needs to map to the first byte of shadow memory and 0xffffffff needs to map to the last byte of shadow memory. Since: SHADOW_ADDR = (address >> 3) + KASAN_SHADOW_OFFSET 0xb6e00000 = (0xbf000000 >> 3) + KASAN_SHADOW_OFFSET KASAN_SHADOW_OFFSET = 0xb6e00000 - (0xbf000000 >> 3) KASAN_SHADOW_OFFSET = 0xb6e00000 - 0x17e00000 KASAN_SHADOW_OFFSET = 0x9f000000 - 0x8f000000 if we have 3G userspace / 1G kernelspace with full 1 GB low memory (VMSPLIT_3G_OPT): - The kernel address space is 1GB (0x40000000) - PAGE_OFFSET is set to 0xb0000000 so the kernel static image uses 0xb0000000 .. 0xffffffff. - On top of that we have the MODULES_VADDR which under the worst case (using ARM instructions) is PAGE_OFFSET - 16M (0x01000000) = 0xaf000000 so the modules use addresses 0xaf000000 .. 0xaffffff - So the addresses 0xaf000000 .. 0xffffffff need to be covered with shadow memory. That is 0x51000000 bytes of memory. - 1/8 of that is needed for its shadow memory, so 0x0a200000 bytes of shadow memory is needed. We "steal" that from the remaining lowmem. - The KASAN_SHADOW_START becomes 0xa4e00000, to KASAN_SHADOW_END at 0xaeffffff. - Now we can calculate the KASAN_SHADOW_OFFSET for any kernel address as 0xaf000000 needs to map to the first byte of shadow memory and 0xffffffff needs to map to the last byte of shadow memory. Since: SHADOW_ADDR = (address >> 3) + KASAN_SHADOW_OFFSET 0xa4e00000 = (0xaf000000 >> 3) + KASAN_SHADOW_OFFSET KASAN_SHADOW_OFFSET = 0xa4e00000 - (0xaf000000 >> 3) KASAN_SHADOW_OFFSET = 0xa4e00000 - 0x15e00000 KASAN_SHADOW_OFFSET = 0x8f000000 - The default value of 0xffffffff for KASAN_SHADOW_OFFSET is an error value. We should always match one of the above shadow offsets. When we do this, TASK_SIZE will sometimes get a bit odd values that will not fit into immediate mov assembly instructions. To account for this, we need to rewrite some assembly using TASK_SIZE like this: - mov r1, #TASK_SIZE + ldr r1, =TASK_SIZE or - cmp r4, #TASK_SIZE + ldr r0, =TASK_SIZE + cmp r4, r0 this is done to avoid the immediate #TASK_SIZE that need to fit into a limited number of bits. Cc: Andrey Ryabinin Cc: Alexander Potapenko Cc: Dmitry Vyukov Cc: kasan-dev@googlegroups.com Cc: Mike Rapoport Reviewed-by: Ard Biesheuvel Tested-by: Ard Biesheuvel # QEMU/KVM/mach-virt/LPAE/8G Tested-by: Florian Fainelli # Brahma SoCs Tested-by: Ahmad Fatoum # i.MX6Q Reported-by: Ard Biesheuvel Signed-off-by: Abbott Liu Signed-off-by: Florian Fainelli Signed-off-by: Linus Walleij Signed-off-by: Russell King --- Documentation/arm/memory.rst | 5 +++ arch/arm/Kconfig | 9 +++++ arch/arm/include/asm/kasan_def.h | 81 ++++++++++++++++++++++++++++++++++++++ arch/arm/include/asm/memory.h | 5 +++ arch/arm/include/asm/uaccess-asm.h | 2 +- arch/arm/kernel/entry-armv.S | 3 +- arch/arm/kernel/entry-common.S | 9 +++-- arch/arm/mm/mmu.c | 18 +++++++++ 8 files changed, 127 insertions(+), 5 deletions(-) create mode 100644 arch/arm/include/asm/kasan_def.h (limited to 'arch/arm') diff --git a/Documentation/arm/memory.rst b/Documentation/arm/memory.rst index 34bb23c44a71..0cb1e2938823 100644 --- a/Documentation/arm/memory.rst +++ b/Documentation/arm/memory.rst @@ -77,6 +77,11 @@ MODULES_VADDR MODULES_END-1 Kernel module space Kernel modules inserted via insmod are placed here using dynamic mappings. +TASK_SIZE MODULES_VADDR-1 KASAn shadow memory when KASan is in use. + The range from MODULES_VADDR to the top + of the memory is shadowed here with 1 bit + per byte of memory. + 00001000 TASK_SIZE-1 User space mappings Per-thread mappings are placed here via the mmap() system call. diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index fe2f17eb2b50..194032568b7a 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1323,6 +1323,15 @@ config PAGE_OFFSET default 0xB0000000 if VMSPLIT_3G_OPT default 0xC0000000 +config KASAN_SHADOW_OFFSET + hex + depends on KASAN + default 0x1f000000 if PAGE_OFFSET=0x40000000 + default 0x5f000000 if PAGE_OFFSET=0x80000000 + default 0x9f000000 if PAGE_OFFSET=0xC0000000 + default 0x8f000000 if PAGE_OFFSET=0xB0000000 + default 0xffffffff + config NR_CPUS int "Maximum number of CPUs (2-32)" range 2 32 diff --git a/arch/arm/include/asm/kasan_def.h b/arch/arm/include/asm/kasan_def.h new file mode 100644 index 000000000000..5739605aa7cf --- /dev/null +++ b/arch/arm/include/asm/kasan_def.h @@ -0,0 +1,81 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * arch/arm/include/asm/kasan_def.h + * + * Copyright (c) 2018 Huawei Technologies Co., Ltd. + * + * Author: Abbott Liu + */ + +#ifndef __ASM_KASAN_DEF_H +#define __ASM_KASAN_DEF_H + +#ifdef CONFIG_KASAN + +/* + * Define KASAN_SHADOW_OFFSET,KASAN_SHADOW_START and KASAN_SHADOW_END for + * the Arm kernel address sanitizer. We are "stealing" lowmem (the 4GB + * addressable by a 32bit architecture) out of the virtual address + * space to use as shadow memory for KASan as follows: + * + * +----+ 0xffffffff + * | | \ + * | | |-> Static kernel image (vmlinux) BSS and page table + * | |/ + * +----+ PAGE_OFFSET + * | | \ + * | | |-> Loadable kernel modules virtual address space area + * | |/ + * +----+ MODULES_VADDR = KASAN_SHADOW_END + * | | \ + * | | |-> The shadow area of kernel virtual address. + * | |/ + * +----+-> TASK_SIZE (start of kernel space) = KASAN_SHADOW_START the + * | |\ shadow address of MODULES_VADDR + * | | | + * | | | + * | | |-> The user space area in lowmem. The kernel address + * | | | sanitizer do not use this space, nor does it map it. + * | | | + * | | | + * | | | + * | | | + * | |/ + * ------ 0 + * + * 1) KASAN_SHADOW_START + * This value begins with the MODULE_VADDR's shadow address. It is the + * start of kernel virtual space. Since we have modules to load, we need + * to cover also that area with shadow memory so we can find memory + * bugs in modules. + * + * 2) KASAN_SHADOW_END + * This value is the 0x100000000's shadow address: the mapping that would + * be after the end of the kernel memory at 0xffffffff. It is the end of + * kernel address sanitizer shadow area. It is also the start of the + * module area. + * + * 3) KASAN_SHADOW_OFFSET: + * This value is used to map an address to the corresponding shadow + * address by the following formula: + * + * shadow_addr = (address >> 3) + KASAN_SHADOW_OFFSET; + * + * As you would expect, >> 3 is equal to dividing by 8, meaning each + * byte in the shadow memory covers 8 bytes of kernel memory, so one + * bit shadow memory per byte of kernel memory is used. + * + * The KASAN_SHADOW_OFFSET is provided in a Kconfig option depending + * on the VMSPLIT layout of the system: the kernel and userspace can + * split up lowmem in different ways according to needs, so we calculate + * the shadow offset depending on this. + */ + +#define KASAN_SHADOW_SCALE_SHIFT 3 +#define KASAN_SHADOW_OFFSET _AC(CONFIG_KASAN_SHADOW_OFFSET, UL) +#define KASAN_SHADOW_END ((UL(1) << (32 - KASAN_SHADOW_SCALE_SHIFT)) \ + + KASAN_SHADOW_OFFSET) +#define KASAN_SHADOW_START ((KASAN_SHADOW_END >> 3) + KASAN_SHADOW_OFFSET) + +#endif +#endif diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h index bb79e52aeb90..598dbdca2017 100644 --- a/arch/arm/include/asm/memory.h +++ b/arch/arm/include/asm/memory.h @@ -18,6 +18,7 @@ #ifdef CONFIG_NEED_MACH_MEMORY_H #include #endif +#include /* PAGE_OFFSET - the virtual address of the start of the kernel image */ #define PAGE_OFFSET UL(CONFIG_PAGE_OFFSET) @@ -28,7 +29,11 @@ * TASK_SIZE - the maximum size of a user space task. * TASK_UNMAPPED_BASE - the lower boundary of the mmap VM area */ +#ifndef CONFIG_KASAN #define TASK_SIZE (UL(CONFIG_PAGE_OFFSET) - UL(SZ_16M)) +#else +#define TASK_SIZE (KASAN_SHADOW_START) +#endif #define TASK_UNMAPPED_BASE ALIGN(TASK_SIZE / 3, SZ_16M) /* diff --git a/arch/arm/include/asm/uaccess-asm.h b/arch/arm/include/asm/uaccess-asm.h index 907571fd05c6..e6eb7a2aaf1e 100644 --- a/arch/arm/include/asm/uaccess-asm.h +++ b/arch/arm/include/asm/uaccess-asm.h @@ -85,7 +85,7 @@ */ .macro uaccess_entry, tsk, tmp0, tmp1, tmp2, disable ldr \tmp1, [\tsk, #TI_ADDR_LIMIT] - mov \tmp2, #TASK_SIZE + ldr \tmp2, =TASK_SIZE str \tmp2, [\tsk, #TI_ADDR_LIMIT] DACR( mrc p15, 0, \tmp0, c3, c0, 0) DACR( str \tmp0, [sp, #SVC_DACR]) diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S index 55a47df04773..c4220f51fcf3 100644 --- a/arch/arm/kernel/entry-armv.S +++ b/arch/arm/kernel/entry-armv.S @@ -427,7 +427,8 @@ ENDPROC(__fiq_abt) @ if it was interrupted in a critical region. Here we @ perform a quick test inline since it should be false @ 99.9999% of the time. The rest is done out of line. - cmp r4, #TASK_SIZE + ldr r0, =TASK_SIZE + cmp r4, r0 blhs kuser_cmpxchg64_fixup #endif #endif diff --git a/arch/arm/kernel/entry-common.S b/arch/arm/kernel/entry-common.S index 271cb8a1eba1..fee279e28a72 100644 --- a/arch/arm/kernel/entry-common.S +++ b/arch/arm/kernel/entry-common.S @@ -50,7 +50,8 @@ __ret_fast_syscall: UNWIND(.cantunwind ) disable_irq_notrace @ disable interrupts ldr r2, [tsk, #TI_ADDR_LIMIT] - cmp r2, #TASK_SIZE + ldr r1, =TASK_SIZE + cmp r2, r1 blne addr_limit_check_failed ldr r1, [tsk, #TI_FLAGS] @ re-check for syscall tracing tst r1, #_TIF_SYSCALL_WORK | _TIF_WORK_MASK @@ -87,7 +88,8 @@ __ret_fast_syscall: #endif disable_irq_notrace @ disable interrupts ldr r2, [tsk, #TI_ADDR_LIMIT] - cmp r2, #TASK_SIZE + ldr r1, =TASK_SIZE + cmp r2, r1 blne addr_limit_check_failed ldr r1, [tsk, #TI_FLAGS] @ re-check for syscall tracing tst r1, #_TIF_SYSCALL_WORK | _TIF_WORK_MASK @@ -128,7 +130,8 @@ ret_slow_syscall: disable_irq_notrace @ disable interrupts ENTRY(ret_to_user_from_irq) ldr r2, [tsk, #TI_ADDR_LIMIT] - cmp r2, #TASK_SIZE + ldr r1, =TASK_SIZE + cmp r2, r1 blne addr_limit_check_failed ldr r1, [tsk, #TI_FLAGS] tst r1, #_TIF_WORK_MASK diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c index fa259825310c..c06ebfbc48c4 100644 --- a/arch/arm/mm/mmu.c +++ b/arch/arm/mm/mmu.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include @@ -1255,8 +1256,25 @@ static inline void prepare_page_table(void) /* * Clear out all the mappings below the kernel image. */ +#ifdef CONFIG_KASAN + /* + * KASan's shadow memory inserts itself between the TASK_SIZE + * and MODULES_VADDR. Do not clear the KASan shadow memory mappings. + */ + for (addr = 0; addr < KASAN_SHADOW_START; addr += PMD_SIZE) + pmd_clear(pmd_off_k(addr)); + /* + * Skip over the KASan shadow area. KASAN_SHADOW_END is sometimes + * equal to MODULES_VADDR and then we exit the pmd clearing. If we + * are using a thumb-compiled kernel, there there will be 8MB more + * to clear as KASan always offset to 16 MB below MODULES_VADDR. + */ + for (addr = KASAN_SHADOW_END; addr < MODULES_VADDR; addr += PMD_SIZE) + pmd_clear(pmd_off_k(addr)); +#else for (addr = 0; addr < MODULES_VADDR; addr += PMD_SIZE) pmd_clear(pmd_off_k(addr)); +#endif #ifdef CONFIG_XIP_KERNEL /* The XIP kernel is mapped in the module area -- skip over it */ -- cgit v1.2.3-59-g8ed1b From 5615f69bc2097452ecc954f5264d784e158d6801 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Sun, 25 Oct 2020 23:55:16 +0100 Subject: ARM: 9016/2: Initialize the mapping of KASan shadow memory This patch initializes KASan shadow region's page table and memory. There are two stage for KASan initializing: 1. At early boot stage the whole shadow region is mapped to just one physical page (kasan_zero_page). It is finished by the function kasan_early_init which is called by __mmap_switched(arch/arm/kernel/ head-common.S) 2. After the calling of paging_init, we use kasan_zero_page as zero shadow for some memory that KASan does not need to track, and we allocate a new shadow space for the other memory that KASan need to track. These issues are finished by the function kasan_init which is call by setup_arch. When using KASan we also need to increase the THREAD_SIZE_ORDER from 1 to 2 as the extra calls for shadow memory uses quite a bit of stack. As we need to make a temporary copy of the PGD when setting up shadow memory we create a helpful PGD_SIZE definition for both LPAE and non-LPAE setups. The KASan core code unconditionally calls pud_populate() so this needs to be changed from BUG() to do {} while (0) when building with KASan enabled. After the initial development by Andre Ryabinin several modifications have been made to this code: Abbott Liu - Add support ARM LPAE: If LPAE is enabled, KASan shadow region's mapping table need be copied in the pgd_alloc() function. - Change kasan_pte_populate,kasan_pmd_populate,kasan_pud_populate, kasan_pgd_populate from .meminit.text section to .init.text section. Reported by Florian Fainelli Linus Walleij : - Drop the custom mainpulation of TTBR0 and just use cpu_switch_mm() to switch the pgd table. - Adopt to handle 4th level page tabel folding. - Rewrite the entire page directory and page entry initialization sequence to be recursive based on ARM64:s kasan_init.c. Ard Biesheuvel : - Necessary underlying fixes. - Crucial bug fixes to the memory set-up code. Co-developed-by: Andrey Ryabinin Co-developed-by: Abbott Liu Co-developed-by: Ard Biesheuvel Cc: Alexander Potapenko Cc: Dmitry Vyukov Cc: kasan-dev@googlegroups.com Cc: Mike Rapoport Acked-by: Mike Rapoport Reviewed-by: Ard Biesheuvel Tested-by: Ard Biesheuvel # QEMU/KVM/mach-virt/LPAE/8G Tested-by: Florian Fainelli # Brahma SoCs Tested-by: Ahmad Fatoum # i.MX6Q Reported-by: Russell King - ARM Linux Reported-by: Florian Fainelli Signed-off-by: Andrey Ryabinin Signed-off-by: Abbott Liu Signed-off-by: Florian Fainelli Signed-off-by: Ard Biesheuvel Signed-off-by: Linus Walleij Signed-off-by: Russell King --- arch/arm/include/asm/kasan.h | 33 +++++ arch/arm/include/asm/pgalloc.h | 8 +- arch/arm/include/asm/thread_info.h | 8 + arch/arm/kernel/head-common.S | 3 + arch/arm/kernel/setup.c | 2 + arch/arm/mm/Makefile | 3 + arch/arm/mm/kasan_init.c | 291 +++++++++++++++++++++++++++++++++++++ arch/arm/mm/pgd.c | 16 +- 8 files changed, 362 insertions(+), 2 deletions(-) create mode 100644 arch/arm/include/asm/kasan.h create mode 100644 arch/arm/mm/kasan_init.c (limited to 'arch/arm') diff --git a/arch/arm/include/asm/kasan.h b/arch/arm/include/asm/kasan.h new file mode 100644 index 000000000000..303c35df3135 --- /dev/null +++ b/arch/arm/include/asm/kasan.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * arch/arm/include/asm/kasan.h + * + * Copyright (c) 2015 Samsung Electronics Co., Ltd. + * Author: Andrey Ryabinin + * + */ + +#ifndef __ASM_KASAN_H +#define __ASM_KASAN_H + +#ifdef CONFIG_KASAN + +#include + +#define KASAN_SHADOW_SCALE_SHIFT 3 + +/* + * The compiler uses a shadow offset assuming that addresses start + * from 0. Kernel addresses don't start from 0, so shadow + * for kernel really starts from 'compiler's shadow offset' + + * ('kernel address space start' >> KASAN_SHADOW_SCALE_SHIFT) + */ + +asmlinkage void kasan_early_init(void); +extern void kasan_init(void); + +#else +static inline void kasan_init(void) { } +#endif + +#endif diff --git a/arch/arm/include/asm/pgalloc.h b/arch/arm/include/asm/pgalloc.h index 15f4674715f8..fdee1f04f4f3 100644 --- a/arch/arm/include/asm/pgalloc.h +++ b/arch/arm/include/asm/pgalloc.h @@ -21,6 +21,7 @@ #define _PAGE_KERNEL_TABLE (PMD_TYPE_TABLE | PMD_BIT4 | PMD_DOMAIN(DOMAIN_KERNEL)) #ifdef CONFIG_ARM_LPAE +#define PGD_SIZE (PTRS_PER_PGD * sizeof(pgd_t)) static inline void pud_populate(struct mm_struct *mm, pud_t *pud, pmd_t *pmd) { @@ -28,14 +29,19 @@ static inline void pud_populate(struct mm_struct *mm, pud_t *pud, pmd_t *pmd) } #else /* !CONFIG_ARM_LPAE */ +#define PGD_SIZE (PAGE_SIZE << 2) /* * Since we have only two-level page tables, these are trivial */ #define pmd_alloc_one(mm,addr) ({ BUG(); ((pmd_t *)2); }) #define pmd_free(mm, pmd) do { } while (0) +#ifdef CONFIG_KASAN +/* The KASan core unconditionally calls pud_populate() on all architectures */ +#define pud_populate(mm,pmd,pte) do { } while (0) +#else #define pud_populate(mm,pmd,pte) BUG() - +#endif #endif /* CONFIG_ARM_LPAE */ extern pgd_t *pgd_alloc(struct mm_struct *mm); diff --git a/arch/arm/include/asm/thread_info.h b/arch/arm/include/asm/thread_info.h index 536b6b979f63..56fae7861fd3 100644 --- a/arch/arm/include/asm/thread_info.h +++ b/arch/arm/include/asm/thread_info.h @@ -13,7 +13,15 @@ #include #include +#ifdef CONFIG_KASAN +/* + * KASan uses a lot of extra stack space so the thread size order needs to + * be increased. + */ +#define THREAD_SIZE_ORDER 2 +#else #define THREAD_SIZE_ORDER 1 +#endif #define THREAD_SIZE (PAGE_SIZE << THREAD_SIZE_ORDER) #define THREAD_START_SP (THREAD_SIZE - 8) diff --git a/arch/arm/kernel/head-common.S b/arch/arm/kernel/head-common.S index 6840c7c60a85..89c80154b9ef 100644 --- a/arch/arm/kernel/head-common.S +++ b/arch/arm/kernel/head-common.S @@ -111,6 +111,9 @@ __mmap_switched: str r8, [r2] @ Save atags pointer cmp r3, #0 strne r10, [r3] @ Save control register values +#ifdef CONFIG_KASAN + bl kasan_early_init +#endif mov lr, #0 b start_kernel ENDPROC(__mmap_switched) diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c index 694aa6b4bd03..f4bd8b654255 100644 --- a/arch/arm/kernel/setup.c +++ b/arch/arm/kernel/setup.c @@ -59,6 +59,7 @@ #include #include #include +#include #include "atags.h" @@ -1145,6 +1146,7 @@ void __init setup_arch(char **cmdline_p) early_ioremap_reset(); paging_init(mdesc); + kasan_init(); request_standard_resources(mdesc); if (mdesc->restart) diff --git a/arch/arm/mm/Makefile b/arch/arm/mm/Makefile index 99699c32d8a5..4536159bc8fa 100644 --- a/arch/arm/mm/Makefile +++ b/arch/arm/mm/Makefile @@ -113,3 +113,6 @@ obj-$(CONFIG_CACHE_L2X0_PMU) += cache-l2x0-pmu.o obj-$(CONFIG_CACHE_XSC3L2) += cache-xsc3l2.o obj-$(CONFIG_CACHE_TAUROS2) += cache-tauros2.o obj-$(CONFIG_CACHE_UNIPHIER) += cache-uniphier.o + +KASAN_SANITIZE_kasan_init.o := n +obj-$(CONFIG_KASAN) += kasan_init.o diff --git a/arch/arm/mm/kasan_init.c b/arch/arm/mm/kasan_init.c new file mode 100644 index 000000000000..9c348042a724 --- /dev/null +++ b/arch/arm/mm/kasan_init.c @@ -0,0 +1,291 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * This file contains kasan initialization code for ARM. + * + * Copyright (c) 2018 Samsung Electronics Co., Ltd. + * Author: Andrey Ryabinin + * Author: Linus Walleij + */ + +#define pr_fmt(fmt) "kasan: " fmt +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "mm.h" + +static pgd_t tmp_pgd_table[PTRS_PER_PGD] __initdata __aligned(PGD_SIZE); + +pmd_t tmp_pmd_table[PTRS_PER_PMD] __page_aligned_bss; + +static __init void *kasan_alloc_block(size_t size) +{ + return memblock_alloc_try_nid(size, size, __pa(MAX_DMA_ADDRESS), + MEMBLOCK_ALLOC_KASAN, NUMA_NO_NODE); +} + +static void __init kasan_pte_populate(pmd_t *pmdp, unsigned long addr, + unsigned long end, bool early) +{ + unsigned long next; + pte_t *ptep = pte_offset_kernel(pmdp, addr); + + do { + pte_t entry; + void *p; + + next = addr + PAGE_SIZE; + + if (!early) { + if (!pte_none(READ_ONCE(*ptep))) + continue; + + p = kasan_alloc_block(PAGE_SIZE); + if (!p) { + panic("%s failed to allocate shadow page for address 0x%lx\n", + __func__, addr); + return; + } + memset(p, KASAN_SHADOW_INIT, PAGE_SIZE); + entry = pfn_pte(virt_to_pfn(p), + __pgprot(pgprot_val(PAGE_KERNEL))); + } else if (pte_none(READ_ONCE(*ptep))) { + /* + * The early shadow memory is mapping all KASan + * operations to one and the same page in memory, + * "kasan_early_shadow_page" so that the instrumentation + * will work on a scratch area until we can set up the + * proper KASan shadow memory. + */ + entry = pfn_pte(virt_to_pfn(kasan_early_shadow_page), + __pgprot(_L_PTE_DEFAULT | L_PTE_DIRTY | L_PTE_XN)); + } else { + /* + * Early shadow mappings are PMD_SIZE aligned, so if the + * first entry is already set, they must all be set. + */ + return; + } + + set_pte_at(&init_mm, addr, ptep, entry); + } while (ptep++, addr = next, addr != end); +} + +/* + * The pmd (page middle directory) is only used on LPAE + */ +static void __init kasan_pmd_populate(pud_t *pudp, unsigned long addr, + unsigned long end, bool early) +{ + unsigned long next; + pmd_t *pmdp = pmd_offset(pudp, addr); + + do { + if (pmd_none(*pmdp)) { + /* + * We attempt to allocate a shadow block for the PMDs + * used by the PTEs for this address if it isn't already + * allocated. + */ + void *p = early ? kasan_early_shadow_pte : + kasan_alloc_block(PAGE_SIZE); + + if (!p) { + panic("%s failed to allocate shadow block for address 0x%lx\n", + __func__, addr); + return; + } + pmd_populate_kernel(&init_mm, pmdp, p); + flush_pmd_entry(pmdp); + } + + next = pmd_addr_end(addr, end); + kasan_pte_populate(pmdp, addr, next, early); + } while (pmdp++, addr = next, addr != end); +} + +static void __init kasan_pgd_populate(unsigned long addr, unsigned long end, + bool early) +{ + unsigned long next; + pgd_t *pgdp; + p4d_t *p4dp; + pud_t *pudp; + + pgdp = pgd_offset_k(addr); + + do { + /* + * Allocate and populate the shadow block of p4d folded into + * pud folded into pmd if it doesn't already exist + */ + if (!early && pgd_none(*pgdp)) { + void *p = kasan_alloc_block(PAGE_SIZE); + + if (!p) { + panic("%s failed to allocate shadow block for address 0x%lx\n", + __func__, addr); + return; + } + pgd_populate(&init_mm, pgdp, p); + } + + next = pgd_addr_end(addr, end); + /* + * We just immediately jump over the p4d and pud page + * directories since we believe ARM32 will never gain four + * nor five level page tables. + */ + p4dp = p4d_offset(pgdp, addr); + pudp = pud_offset(p4dp, addr); + + kasan_pmd_populate(pudp, addr, next, early); + } while (pgdp++, addr = next, addr != end); +} + +extern struct proc_info_list *lookup_processor_type(unsigned int); + +void __init kasan_early_init(void) +{ + struct proc_info_list *list; + + /* + * locate processor in the list of supported processor + * types. The linker builds this table for us from the + * entries in arch/arm/mm/proc-*.S + */ + list = lookup_processor_type(read_cpuid_id()); + if (list) { +#ifdef MULTI_CPU + processor = *list->proc; +#endif + } + + BUILD_BUG_ON((KASAN_SHADOW_END - (1UL << 29)) != KASAN_SHADOW_OFFSET); + /* + * We walk the page table and set all of the shadow memory to point + * to the scratch page. + */ + kasan_pgd_populate(KASAN_SHADOW_START, KASAN_SHADOW_END, true); +} + +static void __init clear_pgds(unsigned long start, + unsigned long end) +{ + for (; start && start < end; start += PMD_SIZE) + pmd_clear(pmd_off_k(start)); +} + +static int __init create_mapping(void *start, void *end) +{ + void *shadow_start, *shadow_end; + + shadow_start = kasan_mem_to_shadow(start); + shadow_end = kasan_mem_to_shadow(end); + + pr_info("Mapping kernel virtual memory block: %px-%px at shadow: %px-%px\n", + start, end, shadow_start, shadow_end); + + kasan_pgd_populate((unsigned long)shadow_start & PAGE_MASK, + PAGE_ALIGN((unsigned long)shadow_end), false); + return 0; +} + +void __init kasan_init(void) +{ + phys_addr_t pa_start, pa_end; + u64 i; + + /* + * We are going to perform proper setup of shadow memory. + * + * At first we should unmap early shadow (clear_pgds() call bellow). + * However, instrumented code can't execute without shadow memory. + * + * To keep the early shadow memory MMU tables around while setting up + * the proper shadow memory, we copy swapper_pg_dir (the initial page + * table) to tmp_pgd_table and use that to keep the early shadow memory + * mapped until the full shadow setup is finished. Then we swap back + * to the proper swapper_pg_dir. + */ + + memcpy(tmp_pgd_table, swapper_pg_dir, sizeof(tmp_pgd_table)); +#ifdef CONFIG_ARM_LPAE + /* We need to be in the same PGD or this won't work */ + BUILD_BUG_ON(pgd_index(KASAN_SHADOW_START) != + pgd_index(KASAN_SHADOW_END)); + memcpy(tmp_pmd_table, + pgd_page_vaddr(*pgd_offset_k(KASAN_SHADOW_START)), + sizeof(tmp_pmd_table)); + set_pgd(&tmp_pgd_table[pgd_index(KASAN_SHADOW_START)], + __pgd(__pa(tmp_pmd_table) | PMD_TYPE_TABLE | L_PGD_SWAPPER)); +#endif + cpu_switch_mm(tmp_pgd_table, &init_mm); + local_flush_tlb_all(); + + clear_pgds(KASAN_SHADOW_START, KASAN_SHADOW_END); + + kasan_populate_early_shadow(kasan_mem_to_shadow((void *)VMALLOC_START), + kasan_mem_to_shadow((void *)-1UL) + 1); + + for_each_mem_range(i, &pa_start, &pa_end) { + void *start = __va(pa_start); + void *end = __va(pa_end); + + /* Do not attempt to shadow highmem */ + if (pa_start >= arm_lowmem_limit) { + pr_info("Skip highmem block at %pa-%pa\n", &pa_start, &pa_end); + continue; + } + if (pa_end > arm_lowmem_limit) { + pr_info("Truncating shadow for memory block at %pa-%pa to lowmem region at %pa\n", + &pa_start, &pa_end, &arm_lowmem_limit); + end = __va(arm_lowmem_limit); + } + if (start >= end) { + pr_info("Skipping invalid memory block %pa-%pa (virtual %p-%p)\n", + &pa_start, &pa_end, start, end); + continue; + } + + create_mapping(start, end); + } + + /* + * 1. The module global variables are in MODULES_VADDR ~ MODULES_END, + * so we need to map this area. + * 2. PKMAP_BASE ~ PKMAP_BASE+PMD_SIZE's shadow and MODULES_VADDR + * ~ MODULES_END's shadow is in the same PMD_SIZE, so we can't + * use kasan_populate_zero_shadow. + */ + create_mapping((void *)MODULES_VADDR, (void *)(PKMAP_BASE + PMD_SIZE)); + + /* + * KAsan may reuse the contents of kasan_early_shadow_pte directly, so + * we should make sure that it maps the zero page read-only. + */ + for (i = 0; i < PTRS_PER_PTE; i++) + set_pte_at(&init_mm, KASAN_SHADOW_START + i*PAGE_SIZE, + &kasan_early_shadow_pte[i], + pfn_pte(virt_to_pfn(kasan_early_shadow_page), + __pgprot(pgprot_val(PAGE_KERNEL) + | L_PTE_RDONLY))); + + cpu_switch_mm(swapper_pg_dir, &init_mm); + local_flush_tlb_all(); + + memset(kasan_early_shadow_page, 0, PAGE_SIZE); + pr_info("Kernel address sanitizer initialized\n"); + init_task.kasan_depth = 0; +} diff --git a/arch/arm/mm/pgd.c b/arch/arm/mm/pgd.c index c5e1b27046a8..f8e9bc58a84f 100644 --- a/arch/arm/mm/pgd.c +++ b/arch/arm/mm/pgd.c @@ -66,7 +66,21 @@ pgd_t *pgd_alloc(struct mm_struct *mm) new_pmd = pmd_alloc(mm, new_pud, 0); if (!new_pmd) goto no_pmd; -#endif +#ifdef CONFIG_KASAN + /* + * Copy PMD table for KASAN shadow mappings. + */ + init_pgd = pgd_offset_k(TASK_SIZE); + init_p4d = p4d_offset(init_pgd, TASK_SIZE); + init_pud = pud_offset(init_p4d, TASK_SIZE); + init_pmd = pmd_offset(init_pud, TASK_SIZE); + new_pmd = pmd_offset(new_pud, TASK_SIZE); + memcpy(new_pmd, init_pmd, + (pmd_index(MODULES_VADDR) - pmd_index(TASK_SIZE)) + * sizeof(pmd_t)); + clean_dcache_area(new_pmd, PTRS_PER_PMD * sizeof(pmd_t)); +#endif /* CONFIG_KASAN */ +#endif /* CONFIG_LPAE */ if (!vectors_high()) { /* -- cgit v1.2.3-59-g8ed1b From 421015713b306e47af95d4d61cdfbd96d462e4cb Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Sun, 25 Oct 2020 23:56:18 +0100 Subject: ARM: 9017/2: Enable KASan for ARM This patch enables the kernel address sanitizer for ARM. XIP_KERNEL has not been tested and is therefore not allowed for now. Cc: Andrey Ryabinin Cc: Alexander Potapenko Cc: Dmitry Vyukov Cc: kasan-dev@googlegroups.com Acked-by: Dmitry Vyukov Reviewed-by: Ard Biesheuvel Tested-by: Ard Biesheuvel # QEMU/KVM/mach-virt/LPAE/8G Tested-by: Florian Fainelli # Brahma SoCs Tested-by: Ahmad Fatoum # i.MX6Q Signed-off-by: Abbott Liu Signed-off-by: Florian Fainelli Signed-off-by: Linus Walleij Signed-off-by: Russell King --- Documentation/dev-tools/kasan.rst | 4 ++-- Documentation/features/debug/KASAN/arch-support.txt | 2 +- arch/arm/Kconfig | 1 + 3 files changed, 4 insertions(+), 3 deletions(-) (limited to 'arch/arm') diff --git a/Documentation/dev-tools/kasan.rst b/Documentation/dev-tools/kasan.rst index c09c9ca2ff1c..3edd3946d4c7 100644 --- a/Documentation/dev-tools/kasan.rst +++ b/Documentation/dev-tools/kasan.rst @@ -18,8 +18,8 @@ out-of-bounds accesses for global variables is only supported since Clang 11. Tag-based KASAN is only supported in Clang. -Currently generic KASAN is supported for the x86_64, arm64, xtensa, s390 and -riscv architectures, and tag-based KASAN is supported only for arm64. +Currently generic KASAN is supported for the x86_64, arm, arm64, xtensa, s390 +and riscv architectures, and tag-based KASAN is supported only for arm64. Usage ----- diff --git a/Documentation/features/debug/KASAN/arch-support.txt b/Documentation/features/debug/KASAN/arch-support.txt index c3fe9b266e7b..b2288dc14b72 100644 --- a/Documentation/features/debug/KASAN/arch-support.txt +++ b/Documentation/features/debug/KASAN/arch-support.txt @@ -8,7 +8,7 @@ ----------------------- | alpha: | TODO | | arc: | TODO | - | arm: | TODO | + | arm: | ok | | arm64: | ok | | c6x: | TODO | | csky: | TODO | diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 194032568b7a..2c5eb5c2b310 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -67,6 +67,7 @@ config ARM select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU + select HAVE_ARCH_KASAN if MMU && !XIP_KERNEL select HAVE_ARCH_MMAP_RND_BITS if MMU select HAVE_ARCH_SECCOMP select HAVE_ARCH_SECCOMP_FILTER if AEABI && !OABI_COMPAT -- cgit v1.2.3-59-g8ed1b From fa769f29f12419db48f4e447e2da9719cc83f3e8 Mon Sep 17 00:00:00 2001 From: Yu-Tung Chang Date: Mon, 26 Oct 2020 15:35:36 +0800 Subject: ARM: dts: sun8i: add FriendlyArm ZeroPi support The ZeroPi is another fun board developed by FriendlyELEC for makers, hobbyists and fans. ZeroPi key features - Allwinner H3, Quad-core Cortex-A7@1.2GHz - 256MB/512MB DDR3 RAM - microsd slot - 10/100/1000Mbps Ethernet - Debug Serial Port - DC 5V/2A power-supply Signed-off-by: Yu-Tung Chang Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20201026073536.13617-2-mtwget@gmail.com --- Documentation/devicetree/bindings/arm/sunxi.yaml | 5 ++ arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/sun8i-h3-zeropi.dts | 85 ++++++++++++++++++++++++ 3 files changed, 91 insertions(+) create mode 100644 arch/arm/boot/dts/sun8i-h3-zeropi.dts (limited to 'arch/arm') diff --git a/Documentation/devicetree/bindings/arm/sunxi.yaml b/Documentation/devicetree/bindings/arm/sunxi.yaml index afa00268c7db..0f23133672a3 100644 --- a/Documentation/devicetree/bindings/arm/sunxi.yaml +++ b/Documentation/devicetree/bindings/arm/sunxi.yaml @@ -251,6 +251,11 @@ properties: - const: friendlyarm,nanopi-neo-plus2 - const: allwinner,sun50i-h5 + - description: FriendlyARM ZeroPi + items: + - const: friendlyarm,zeropi + - const: allwinner,sun8i-h3 + - description: Gemei G9 Tablet items: - const: gemei,g9 diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index ce66ffd5a1bb..4f0adfead547 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1201,6 +1201,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \ sun8i-h3-orangepi-plus2e.dtb \ sun8i-h3-orangepi-zero-plus2.dtb \ sun8i-h3-rervision-dvk.dtb \ + sun8i-h3-zeropi.dtb \ sun8i-h3-emlid-neutis-n5h3-devboard.dtb \ sun8i-r16-bananapi-m2m.dtb \ sun8i-r16-nintendo-nes-classic.dtb \ diff --git a/arch/arm/boot/dts/sun8i-h3-zeropi.dts b/arch/arm/boot/dts/sun8i-h3-zeropi.dts new file mode 100644 index 000000000000..7d3e7323b661 --- /dev/null +++ b/arch/arm/boot/dts/sun8i-h3-zeropi.dts @@ -0,0 +1,85 @@ +/* + * Copyright (C) 2020 Yu-Tung Chang + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "sun8i-h3-nanopi.dtsi" + +/ { + model = "FriendlyARM ZeroPi"; + compatible = "friendlyarm,zeropi", "allwinner,sun8i-h3"; + + aliases { + ethernet0 = &emac; + }; + + reg_gmac_3v3: gmac-3v3 { + compatible = "regulator-fixed"; + regulator-name = "gmac-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <100000>; + enable-active-high; + gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; /* PD6 */ + }; +}; + +&external_mdio { + ext_rgmii_phy: ethernet-phy@7 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <7>; + }; +}; + +&emac { + pinctrl-names = "default"; + pinctrl-0 = <&emac_rgmii_pins>; + phy-supply = <®_gmac_3v3>; + phy-handle = <&ext_rgmii_phy>; + phy-mode = "rgmii-id"; + + allwinner,leds-active-low; + status = "okay"; +}; + +&usb_otg { + status = "okay"; + dr_mode = "host"; +}; -- cgit v1.2.3-59-g8ed1b From 950d46f7c18a928e17f866a9ce5bf9c1132e5f33 Mon Sep 17 00:00:00 2001 From: Marek Szyprowski Date: Fri, 11 Sep 2020 14:22:20 +0200 Subject: ARM: dts: exynos: Remove 'opp-shared' from Exynos3 bus OPP-tables Commits 1019fe2c7280 ("ARM: dts: exynos: Adjust bus related OPPs to the values correct for Exynos5422 Odroids") and 9ff416cf45a0 ("ARM: dts: exynos: Disable frequency scaling for FSYS bus on Odroid XU3 family") revealed that 'opp-shared' property for the Exynos bus OPPs was used incorrectly, what had the side-effect of disabling frequency scaling for the second and latter buses sharing given OPP-table. Fix this by removing bogus 'opp-shared' properties from Exynos3 bus OPP-tables. This restores frequency scaling for the following buses: RightBus, LCD0, FSYS and MFC. Signed-off-by: Marek Szyprowski Link: https://lore.kernel.org/r/20200911122220.13698-1-m.szyprowski@samsung.com Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos3250.dtsi | 5 ----- 1 file changed, 5 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi index a1e93fb7f694..75ed82600ec8 100644 --- a/arch/arm/boot/dts/exynos3250.dtsi +++ b/arch/arm/boot/dts/exynos3250.dtsi @@ -775,7 +775,6 @@ bus_dmc_opp_table: opp_table1 { compatible = "operating-points-v2"; - opp-shared; opp-50000000 { opp-hz = /bits/ 64 <50000000>; @@ -865,7 +864,6 @@ bus_leftbus_opp_table: opp_table2 { compatible = "operating-points-v2"; - opp-shared; opp-50000000 { opp-hz = /bits/ 64 <50000000>; @@ -891,7 +889,6 @@ bus_mcuisp_opp_table: opp_table3 { compatible = "operating-points-v2"; - opp-shared; opp-50000000 { opp-hz = /bits/ 64 <50000000>; @@ -912,7 +909,6 @@ bus_isp_opp_table: opp_table4 { compatible = "operating-points-v2"; - opp-shared; opp-50000000 { opp-hz = /bits/ 64 <50000000>; @@ -933,7 +929,6 @@ bus_peril_opp_table: opp_table5 { compatible = "operating-points-v2"; - opp-shared; opp-50000000 { opp-hz = /bits/ 64 <50000000>; -- cgit v1.2.3-59-g8ed1b From a23beead41a18c3be3ca409cb52f35bc02e601b9 Mon Sep 17 00:00:00 2001 From: Marek Szyprowski Date: Fri, 11 Sep 2020 14:22:36 +0200 Subject: ARM: dts: exynos: Remove 'opp-shared' from Exynos4412 bus OPP-tables Commits 1019fe2c7280 ("ARM: dts: exynos: Adjust bus related OPPs to the values correct for Exynos5422 Odroids") and 9ff416cf45a0 ("ARM: dts: exynos: Disable frequency scaling for FSYS bus on Odroid XU3 family") revealed that 'opp-shared' property for the Exynos bus OPPs was used incorrectly, what had the side-effect of disabling frequency scaling for the second and latter buses sharing given OPP-table. Fix this by removing bogus 'opp-shared' properties from Exynos4412 bus OPP-tables. This restores frequency scaling for the following buses: C2C, RightBus, and MFC. Signed-off-by: Marek Szyprowski Link: https://lore.kernel.org/r/20200911122236.16805-1-m.szyprowski@samsung.com Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos4412.dtsi | 6 ------ 1 file changed, 6 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/exynos4412.dtsi b/arch/arm/boot/dts/exynos4412.dtsi index e76881dc0014..fa8e8d6bc4d5 100644 --- a/arch/arm/boot/dts/exynos4412.dtsi +++ b/arch/arm/boot/dts/exynos4412.dtsi @@ -404,7 +404,6 @@ bus_dmc_opp_table: opp-table1 { compatible = "operating-points-v2"; - opp-shared; opp-100000000 { opp-hz = /bits/ 64 <100000000>; @@ -431,7 +430,6 @@ bus_acp_opp_table: opp-table2 { compatible = "operating-points-v2"; - opp-shared; opp-100000000 { opp-hz = /bits/ 64 <100000000>; @@ -497,7 +495,6 @@ bus_leftbus_opp_table: opp-table3 { compatible = "operating-points-v2"; - opp-shared; opp-100000000 { opp-hz = /bits/ 64 <100000000>; @@ -520,7 +517,6 @@ bus_display_opp_table: opp-table4 { compatible = "operating-points-v2"; - opp-shared; opp-160000000 { opp-hz = /bits/ 64 <160000000>; @@ -532,7 +528,6 @@ bus_fsys_opp_table: opp-table5 { compatible = "operating-points-v2"; - opp-shared; opp-100000000 { opp-hz = /bits/ 64 <100000000>; @@ -544,7 +539,6 @@ bus_peri_opp_table: opp-table6 { compatible = "operating-points-v2"; - opp-shared; opp-50000000 { opp-hz = /bits/ 64 <50000000>; -- cgit v1.2.3-59-g8ed1b From 886f82ce9f1f4559c139fdb2d79d158999ca38cd Mon Sep 17 00:00:00 2001 From: Billy Tsai Date: Mon, 12 Oct 2020 11:31:48 +0800 Subject: ARM: dts: aspeed-g6: Fix the GPIO memory size The GPIO controller is a GPIO controller followed by some SGPIO controllers, which are a different type of device with their own binding and drivers. Make the gpio node cover the only conventional GPIO controller. Fixes: 8dbcb5b709b9 ("ARM: dts: aspeed-g6: Add gpio devices") Signed-off-by: Billy Tsai Reviewed-by: Andrew Jeffery Reviewed-by: Joel Stanley Link: https://lore.kernel.org/r/20201012033150.21056-2-billy_tsai@aspeedtech.com Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-g6.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed-g6.dtsi index b58220a49cbd..bf97aaad7be9 100644 --- a/arch/arm/boot/dts/aspeed-g6.dtsi +++ b/arch/arm/boot/dts/aspeed-g6.dtsi @@ -357,7 +357,7 @@ #gpio-cells = <2>; gpio-controller; compatible = "aspeed,ast2600-gpio"; - reg = <0x1e780000 0x800>; + reg = <0x1e780000 0x400>; interrupts = ; gpio-ranges = <&pinctrl 0 0 208>; ngpios = <208>; -- cgit v1.2.3-59-g8ed1b From e3b123542cdc324d85a061356fbb6bb849bcb941 Mon Sep 17 00:00:00 2001 From: Konstantin Aladyshev Date: Tue, 27 Oct 2020 15:37:20 +0300 Subject: ARM: dts: aspeed: amd-ethanolx: Update KCS nodes to use v2 binding KCS nodes compatible property was changed in the dtsi to use v2 binding before ethanolx was merged, making the ethanolx device tree incorrect. Update it to use the new binding so the driver loads. Fixes: fa4c8ec6feaa ("ARM: dts: aspeed: Change KCS nodes to v2 binding") Signed-off-by: Konstantin Aladyshev Reviewed-by: Joel Stanley Link: https://lore.kernel.org/r/20201027123722.2935-1-aladyshev22@gmail.com Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-amd-ethanolx.dts | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/aspeed-bmc-amd-ethanolx.dts b/arch/arm/boot/dts/aspeed-bmc-amd-ethanolx.dts index 60ba86f3e5bc..89ddc3847222 100644 --- a/arch/arm/boot/dts/aspeed-bmc-amd-ethanolx.dts +++ b/arch/arm/boot/dts/aspeed-bmc-amd-ethanolx.dts @@ -139,17 +139,17 @@ &kcs1 { status = "okay"; - kcs_addr = <0x60>; + aspeed,lpc-io-reg = <0x60>; }; &kcs2 { status = "okay"; - kcs_addr = <0x62>; + aspeed,lpc-io-reg = <0x62>; }; &kcs4 { status = "okay"; - kcs_addr = <0x97DE>; + aspeed,lpc-io-reg = <0x97DE>; }; &lpc_snoop { -- cgit v1.2.3-59-g8ed1b From 9e1cc9679776f5b9e42481d392b1550753ebd084 Mon Sep 17 00:00:00 2001 From: Joel Stanley Date: Tue, 22 Sep 2020 16:12:34 +0930 Subject: ARM: dts: aspeed: s2600wf: Fix VGA memory region location The VGA memory region is always from the top of RAM. On this board, that is 0x80000000 + 0x20000000 - 0x01000000 = 0x9f000000. This was not an issue in practice as the region is "reserved" by the vendor's u-boot reducing the amount of available RAM, and the only user is the host VGA device poking at RAM over PCIe. That is, nothing from the ARM touches it. It is worth fixing as developers copy existing device trees when building their machines, and the XDMA driver does use the memory region from the ARM side. Fixes: c4043ecac34a ("ARM: dts: aspeed: Add S2600WF BMC Machine") Reported-by: John Wang Link: https://lore.kernel.org/r/20200922064234.163799-1-joel@jms.id.au Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-intel-s2600wf.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/aspeed-bmc-intel-s2600wf.dts b/arch/arm/boot/dts/aspeed-bmc-intel-s2600wf.dts index 1deb30ec912c..6e9baf3bba53 100644 --- a/arch/arm/boot/dts/aspeed-bmc-intel-s2600wf.dts +++ b/arch/arm/boot/dts/aspeed-bmc-intel-s2600wf.dts @@ -22,9 +22,9 @@ #size-cells = <1>; ranges; - vga_memory: framebuffer@7f000000 { + vga_memory: framebuffer@9f000000 { no-map; - reg = <0x7f000000 0x01000000>; + reg = <0x9f000000 0x01000000>; /* 16M */ }; }; -- cgit v1.2.3-59-g8ed1b From e81059a5e4d8a4227b58a2bc7a5041d545a587a3 Mon Sep 17 00:00:00 2001 From: John Wang Date: Tue, 29 Sep 2020 14:39:54 +0800 Subject: ARM: dts: Add 64MiB OpenBMC flash layout This is an alternate layout used by OpenBMC systems The division of space is as follows: u-boot + env: 0.5MB kernel/FIT: 5MB rofs: 42.5MB rwfs: 16MB Signed-off-by: John Wang Link: https://lore.kernel.org/r/20200929063955.1206-1-wangzhiqiang.bj@bytedance.com Signed-off-by: Joel Stanley --- arch/arm/boot/dts/openbmc-flash-layout-64.dtsi | 35 ++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) create mode 100644 arch/arm/boot/dts/openbmc-flash-layout-64.dtsi (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/openbmc-flash-layout-64.dtsi b/arch/arm/boot/dts/openbmc-flash-layout-64.dtsi new file mode 100644 index 000000000000..c8e0409d889e --- /dev/null +++ b/arch/arm/boot/dts/openbmc-flash-layout-64.dtsi @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2020 Bytedance. + */ + +partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + u-boot@0 { + reg = <0x0 0x60000>; // 384KB + label = "u-boot"; + }; + + u-boot-env@e0000 { + reg = <0x60000 0x20000>; // 128KB + label = "u-boot-env"; + }; + + kernel@100000 { + reg = <0x80000 0x500000>; // 5MB + label = "kernel"; + }; + + rofs@a00000 { + reg = <0x580000 0x2a80000>; // 42.5MB + label = "rofs"; + }; + + rwfs@6000000 { + reg = <0x3000000 0x1000000>; // 16MB + label = "rwfs"; + }; +}; -- cgit v1.2.3-59-g8ed1b From b2826bdf910dccee07bede625c2005154bb6f698 Mon Sep 17 00:00:00 2001 From: Lotus Xu Date: Tue, 29 Sep 2020 14:39:55 +0800 Subject: ARM: dts: aspeed: Add Bytedance g220a BMC machine The g220a is a server platform with an ASPEED AST2500 BMC. Signed-off-by: Lotus Xu Signed-off-by: John Wang Reviewed-by: Joel Stanley Link: https://lore.kernel.org/r/20200929063955.1206-2-wangzhiqiang.bj@bytedance.com Signed-off-by: Joel Stanley --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/aspeed-bmc-bytedance-g220a.dts | 924 +++++++++++++++++++++++ 2 files changed, 925 insertions(+) create mode 100644 arch/arm/boot/dts/aspeed-bmc-bytedance-g220a.dts (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index ce66ffd5a1bb..21477ef5c5c9 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1381,6 +1381,7 @@ dtb-$(CONFIG_ARCH_ASPEED) += \ aspeed-bmc-amd-ethanolx.dtb \ aspeed-bmc-arm-centriq2400-rep.dtb \ aspeed-bmc-arm-stardragon4800-rep2.dtb \ + aspeed-bmc-bytedance-g220a.dtb \ aspeed-bmc-facebook-cmm.dtb \ aspeed-bmc-facebook-minipack.dtb \ aspeed-bmc-facebook-tiogapass.dtb \ diff --git a/arch/arm/boot/dts/aspeed-bmc-bytedance-g220a.dts b/arch/arm/boot/dts/aspeed-bmc-bytedance-g220a.dts new file mode 100644 index 000000000000..0aeec7017e43 --- /dev/null +++ b/arch/arm/boot/dts/aspeed-bmc-bytedance-g220a.dts @@ -0,0 +1,924 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright (C) 2020 Bytedance. +/dts-v1/; + +#include "aspeed-g5.dtsi" +#include +#include +#include + +/ { + model = "Bytedance G220A BMC"; + compatible = "bytedance,g220a-bmc", "aspeed,ast2500"; + + aliases { + serial4 = &uart5; + i2c14 = &channel_3_0; + i2c15 = &channel_3_1; + i2c16 = &channel_3_2; + i2c17 = &channel_3_3; + i2c18 = &channel_6_0; + i2c19 = &channel_6_1; + i2c20 = &channel_6_2; + i2c21 = &channel_6_3; + i2c22 = &channel_6_4; + i2c23 = &channel_6_5; + i2c24 = &channel_6_6; + i2c25 = &channel_6_7; + i2c26 = &channel_6_8; + i2c27 = &channel_6_9; + i2c28 = &channel_6_10; + i2c29 = &channel_6_11; + i2c30 = &channel_6_12; + i2c31 = &channel_6_13; + i2c32 = &channel_6_14; + i2c33 = &channel_6_15; + i2c34 = &channel_6_16; + i2c35 = &channel_6_17; + i2c36 = &channel_6_18; + i2c37 = &channel_6_19; + i2c38 = &channel_6_20; + i2c39 = &channel_6_21; + i2c40 = &channel_6_22; + i2c41 = &channel_6_23; + i2c42 = &channel_6_24; + i2c43 = &channel_6_25; + i2c44 = &channel_10_0; + i2c45 = &channel_10_1; + i2c46 = &channel_10_2; + i2c47 = &channel_10_3; + i2c48 = &channel_10_4; + i2c49 = &channel_10_5; + i2c50 = &channel_10_6; + i2c51 = &channel_10_7; + }; + + chosen { + stdout-path = &uart5; + bootargs = "console=ttyS4,115200 earlyprintk"; + }; + + memory@80000000 { + reg = <0x80000000 0x40000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + vga_memory: framebuffer@bc000000 { + no-map; + reg = <0xbc000000 0x04000000>; /* 64M */ + }; + + video_engine_memory: jpegbuffer { + size = <0x02000000>; /* 32M */ + alignment = <0x01000000>; + compatible = "shared-dma-pool"; + reusable; + }; + }; + + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, + <&adc 4>, <&adc 5>, <&adc 6>, <&adc 7>, + <&adc 8>, <&adc 9>, <&adc 10>, <&adc 11>, + <&adc 12>, <&adc 13>, <&adc 14>, <&adc 15>; + }; + + leds { + compatible = "gpio-leds"; + bmc_alive { + label = "bmc_alive"; + gpios = <&gpio ASPEED_GPIO(B, 0) GPIO_ACTIVE_LOW>; + linux,default-trigger = "timer"; + led-pattern = <1000 1000>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + burn-in-signal { + label = "burn-in"; + gpios = <&gpio ASPEED_GPIO(R, 5) GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + poll-interval = <1000>; + + rear-riser1-presence { + label = "rear-riser1-presence"; + gpios = <&pca0 1 GPIO_ACTIVE_LOW>; + linux,code = <1>; + }; + + alrt-pvddq-cpu0 { + label = "alrt-pvddq-cpu0"; + gpios = <&pca0 8 GPIO_ACTIVE_LOW>; + linux,code = <2>; + }; + + rear-riser0-presence { + label = "rear-riser0-presence"; + gpios = <&pca0 9 GPIO_ACTIVE_LOW>; + linux,code = <3>; + }; + + fault-pvddq-cpu0 { + label = "fault-pvddq-cpu0"; + gpios = <&pca0 10 GPIO_ACTIVE_LOW>; + linux,code = <4>; + }; + + alrt-pvddq-cpu1 { + label = "alrt-pvddq-cpu1"; + gpios = <&pca0 11 GPIO_ACTIVE_LOW>; + linux,code = <5>; + }; + + fault-pvddq-cpu1 { + label = "alrt-pvddq-cpu1"; + gpios = <&pca0 12 GPIO_ACTIVE_LOW>; + linux,code = <6>; + }; + + fault-pvccin-cpu1 { + label = "fault-pvccin-cpuq"; + gpios = <&pca0 13 GPIO_ACTIVE_LOW>; + linux,code = <7>; + }; + + bmc-rom0-wp { + label = "bmc-rom0-wp"; + gpios = <&pca1 0 GPIO_ACTIVE_LOW>; + linux,code = <8>; + }; + + bmc-rom1-wp { + label = "bmc-rom1-wp"; + gpios = <&pca1 1 GPIO_ACTIVE_LOW>; + linux,code = <9>; + }; + + fan0-presence { + label = "fan0-presence"; + gpios = <&pca1 2 GPIO_ACTIVE_LOW>; + linux,code = <10>; + }; + + fan1-presence { + label = "fan1-presence"; + gpios = <&pca1 3 GPIO_ACTIVE_LOW>; + linux,code = <11>; + }; + + fan2-presence { + label = "fan2-presence"; + gpios = <&pca1 4 GPIO_ACTIVE_LOW>; + linux,code = <12>; + }; + + fan3-presence { + label = "fan3-presence"; + gpios = <&pca1 5 GPIO_ACTIVE_LOW>; + linux,code = <13>; + }; + + fan4-presence { + label = "fan4-presence"; + gpios = <&pca1 6 GPIO_ACTIVE_LOW>; + linux,code = <14>; + }; + + fan5-presence { + label = "fan5-presence"; + gpios = <&pca1 7 GPIO_ACTIVE_LOW>; + linux,code = <15>; + }; + + front-bp1-presence { + label = "front-bp1-presence"; + gpios = <&pca1 8 GPIO_ACTIVE_LOW>; + linux,code = <16>; + }; + + rear-bp-presence { + label = "rear-bp-presence"; + gpios = <&pca1 9 GPIO_ACTIVE_LOW>; + linux,code = <17>; + }; + + fault-pvccin-cpu0 { + label = "fault-pvccin-cpu0"; + gpios = <&pca1 10 GPIO_ACTIVE_LOW>; + linux,code = <18>; + }; + + alrt-p1v05-pvcc { + label = "alrt-p1v05-pvcc1"; + gpios = <&pca1 11 GPIO_ACTIVE_LOW>; + linux,code = <19>; + }; + + fault-p1v05-pvccio { + label = "alrt-p1v05-pvcc1"; + gpios = <&pca1 12 GPIO_ACTIVE_LOW>; + linux,code = <20>; + }; + + alrt-p1v8-pvccio { + label = "alrt-p1v8-pvccio"; + gpios = <&pca1 13 GPIO_ACTIVE_LOW>; + linux,code = <21>; + }; + + fault-p1v8-pvccio { + label = "fault-p1v8-pvccio"; + gpios = <&pca1 14 GPIO_ACTIVE_LOW>; + linux,code = <22>; + }; + + front-bp0-presence { + label = "front-bp0-presence"; + gpios = <&pca1 15 GPIO_ACTIVE_LOW>; + linux,code = <23>; + }; + }; +}; + +&fmc { + status = "okay"; + flash@0 { + status = "okay"; + label = "bmc"; + m25p,fast-read; + spi-max-frequency = <50000000>; +#include "openbmc-flash-layout-64.dtsi" + }; +}; + +&spi1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi1_default>; + flash@0 { + status = "okay"; + m25p,fast-read; + label = "bios"; + spi-max-frequency = <100000000>; + }; +}; + +&adc { + status = "okay"; +}; + +&gpio { + status = "okay"; + gpio-line-names = + /*A0-A7*/ "SMRST_OCP_N","MAC2_LINK","BMC_CPLD_SMB_RST_R_N","BMC_CPLD_GPIO0", + "","","","", + /*B0-B7*/ "BMC_INIT_R_OK","FM_BOARD_REV_ID2","FM_PROJECT_ID7","FAULT_P12V_STBY_N", + "","CPU0_PROCHOT_LVT3_N","","BIOS_LOAD_DEFAULT_R_N", + /*C0-C7*/ "","","","","","","","", + /*D0-D7*/ "","","","","","","","", + /*E0-E7*/ "FM_PROJECT_ID0","FM_PROJECT_ID1","FM_PROJECT_ID2","FM_PROJECT_ID3", + "FM_PROJECT_ID4","FM_PROJECT_ID5","","", + /*F0-F7*/ "PSU0_PRSNT_N","PSU1_PRSNT_N","","FAULT_P12V_NVME_N", + "BIOS_DEBUG_MODE_R_N","DISABLE_CPU_DDR_R_SPD","COOLING_STRATEGY", + "PCH_GLB_RST_N", + /*G0-G7*/ "P12V_PMBUS_ALERT_N","CPLD_ALERT_N","BMC_RELOAD_N", + "P12V_PVDDQ_PMBUS_ALERT_N","BMC_JTAG_TCK_MUX_R_SEL","","NMI_OUT", + "NMI_BUTTON", + /*H0-H7*/ "BMC_CPLD_JTAG_TDI","BMC_CPLD_JTAG_TDO","BMC_CPLD_JTAG_TCK", + "BMC_CPLD_JTAG_TMS","FM_PROJECT_ID6","FM_BOARD_REV_ID0", + "PCA9546_U70_RST_N","IRQ_SML0_ALERT_N", + /*I0-I7*/ "FAULT_FRONT_RISER_P12V_N","FAULT_OCP_P12V_N","FM_BMC_PCH_SCI_R_N", + "","","","","", + /*J0-J7*/ "FM_CPU0_SKTOCC_N","FM_CPU1_SKTOCC_N","FM_CPU1_DISABLE_COD_N", + "","","","","", + /*K0-K7*/ "","","","","","","","", + /*L0-L7*/ "P12V_FAULT_N","PWRGD_P12V_PCIE_RISER","","LEAKAGE_DETECT_INPUT_N", + "","IRQ_SML1_PMBUS_ALERT_N","","", + /*M0-M7*/ "","","","","","","","", + /*N0-N7*/ "","","","","","","","", + /*O0-O7*/ "","","","","","","","", + /*P0-P7*/ "","","","","","","","", + /*Q0-Q7*/ "","","","","","","FM_PCH_THERMTRIP_N","INTRUDER_N", + /*R0-R7*/ "","PVCCIN_CPU1_SMBALERT_N","BMC_PREQ_R_N","FAULT_P12V_PCIE_RISER_N", + "ALT_P12V_PCIE_RISER_N","BURN_BOARD_N","PVCCIN_CPU0_SMBALERT_N","", + /*S0-S7*/ "BMC_PRDY_N","SIO_POWER_GOOD","FM_BMC_PWR_DEBUG_R_N", + "FM_BMC_XDP_DEBUG_EN","","","","", + /*T0-T7*/ "","","","","","","","", + /*U0-U7*/ "","","","","","","","", + /*V0-V7*/ "","","","","","","","", + /*W0-W7*/ "","","","","","","","", + /*X0-X7*/ "","","","","","","","", + /*Y0-Y7*/ "","PWRGD_PSU0_PWROK","CPU1_PROCHOT_LVT3_N","IRQ_BMC_PCH_SMI_LPC_N", + "","","","", + /*Z0-Z7*/ "XDP_PRSNT_N","BMC_XDP_SYS_PWROK","BMC_XDP_JTAG_SEL", + "PCH_BMC_SMI_ACTIVE_R_N","","","","", + /*AA0-AA7*/ "PWRGD_P12V_STBY_OCP","PS_PWROK","RST_PLTRST_BMC_R_N","HDA_SDO_R", + "FM_SLPS4_R_N","PWRGD_PSU1_PWROK","POWER_BUTTON","POWER_OUT", + /*AB0-AB7*/ "","RESET_OUT","SPI_BIOS_MODE_SELECT","POST_COMPLETE","","","","", + /*AC0-AC7*/ "","","","","","","","CPLD_PLTRST_B_N"; +}; + +&kcs3 { + aspeed,lpc-io-reg = <0xCA2>; + status = "okay"; +}; + +&kcs4 { + aspeed,lpc-io-reg = <0xCA4>; + status = "okay"; +}; + +&lpc_snoop { + snoop-ports = <0x80>; + status = "okay"; +}; + +&uart1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd1_default + &pinctrl_rxd1_default + &pinctrl_nrts1_default + &pinctrl_ndtr1_default + &pinctrl_ndsr1_default + &pinctrl_ncts1_default + &pinctrl_ndcd1_default + &pinctrl_nri1_default>; +}; + +&uart2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd2_default + &pinctrl_rxd2_default + &pinctrl_nrts2_default + &pinctrl_ndtr2_default + &pinctrl_ndsr2_default + &pinctrl_ncts2_default + &pinctrl_ndcd2_default + &pinctrl_nri2_default>; +}; + +&uart3 { + status = "okay"; +}; + +&uart4 { + status = "okay"; +}; + +&uart5 { + status = "okay"; +}; + +&mac0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rmii1_default>; + clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>, + <&syscon ASPEED_CLK_MAC1RCLK>; + clock-names = "MACCLK", "RCLK"; + use-ncsi; +}; + +&mac1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>; +}; + +&i2c0 { + status = "okay"; +}; + +&i2c1 { + status = "okay"; +}; + +&i2c2 { + status = "okay"; +}; + +&i2c3 { + status = "okay"; + i2c-switch@70 { + compatible = "nxp,pca9546"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + + channel_3_0: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + channel_3_1: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + channel_3_2: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + channel_3_3: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + }; +}; + +&i2c4 { + status = "okay"; + +}; + +&i2c5 { + status = "okay"; +}; + +&i2c6 { + status = "okay"; + i2c-switch@72 { + compatible = "nxp,pca9548"; + reg = <0x72>; + #address-cells = <1>; + #size-cells = <0>; + channel_6_0: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + channel_6_1: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + channel_6_2: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + channel_6_3: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + channel_6_4: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + + channel_6_5: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + + channel_6_6: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + + channel_6_7: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + }; + + i2c-switch@70 { + compatible = "nxp,pca9546"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + channel_6_8: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + i2c-switch@71 { + compatible = "nxp,pca9546"; + reg = <0x71>; + #address-cells = <1>; + #size-cells = <0>; + channel_6_12: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + }; + + channel_6_13: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + channel_6_14: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + channel_6_15: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + }; + }; + + channel_6_9: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + i2c-switch@71 { + compatible = "nxp,pca9546"; + reg = <0x71>; + #address-cells = <1>; + #size-cells = <0>; + channel_6_16: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + }; + + channel_6_17: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + channel_6_18: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + channel_6_19: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + }; + }; + + channel_6_10: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + i2c-switch@71 { + compatible = "nxp,pca9546"; + reg = <0x71>; + #address-cells = <1>; + #size-cells = <0>; + channel_6_20: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + channel_6_21: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + channel_6_22: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + channel_6_23: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + }; + }; + + channel_6_11: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + i2c-switch@71 { + compatible = "nxp,pca9546"; + reg = <0x71>; + #address-cells = <1>; + #size-cells = <0>; + channel_6_24: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + channel_6_25: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + }; + }; + }; +}; + +&i2c7 { + status = "okay"; +}; + +&i2c8 { + status = "okay"; + pca0:pca9555@24 { + compatible = "nxp,pca9555"; + reg = <0x24>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + gpio@1 { + reg = <1>; + type = ; + }; + + gpio@8 { + reg = <8>; + type = ; + }; + + gpio@9 { + reg = <9>; + type = ; + }; + + gpio@10 { + reg = <10>; + type = ; + }; + + gpio@11 { + reg = <11>; + type = ; + }; + + gpio@12 { + reg = <12>; + type = ; + }; + + gpio@13 { + reg = <13>; + type = ; + }; + }; + + pca1:pca9555@25 { + compatible = "nxp,pca9555"; + reg = <0x25>; + + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + gpio@0 { + reg = <0>; + type = ; + }; + + gpio@1 { + reg = <1>; + type = ; + }; + + gpio@2 { + reg = <2>; + type = ; + }; + + gpio@3 { + reg = <3>; + type = ; + }; + + gpio@4 { + reg = <4>; + type = ; + }; + + gpio@5 { + reg = <5>; + type = ; + }; + + gpio@6 { + reg = <6>; + type = ; + }; + + gpio@7 { + reg = <7>; + type = ; + }; + gpio@8 { + reg = <8>; + type = ; + }; + + gpio@9 { + reg = <9>; + type = ; + }; + + gpio@10 { + reg = <10>; + type = ; + }; + + gpio@11 { + reg = <11>; + type = ; + }; + + gpio@12 { + reg = <12>; + type = ; + }; + + gpio@13 { + reg = <13>; + type = ; + }; + + gpio@14 { + reg = <14>; + type = ; + }; + + gpio@15 { + reg = <15>; + type = ; + }; + }; +}; + +&i2c9 { + status = "okay"; +}; + +&i2c10 { + status = "okay"; + i2c-switch@70 { + compatible = "nxp,pca9546"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + channel_10_0: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + channel_10_1: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + channel_10_2: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + channel_10_3: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + }; + + i2c-switch@71 { + compatible = "nxp,pca9546"; + reg = <0x71>; + #address-cells = <1>; + #size-cells = <0>; + channel_10_4: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + channel_10_5: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + channel_10_6: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + channel_10_7: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + }; +}; + +&i2c11 { + status = "okay"; +}; + +&i2c12 { + status = "okay"; +}; + +&i2c13 { + status = "okay"; +}; + +&pwm_tacho { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_pwm1_default + &pinctrl_pwm2_default &pinctrl_pwm3_default + &pinctrl_pwm4_default &pinctrl_pwm5_default>; + + fan@0 { + reg = <0x00>; + aspeed,fan-tach-ch = /bits/ 8 <0x00 0x01>; + }; + fan@1 { + reg = <0x01>; + aspeed,fan-tach-ch = /bits/ 8 <0x02 0x03>; + }; + fan@2 { + reg = <0x02>; + aspeed,fan-tach-ch = /bits/ 8 <0x04 0x05>; + }; + fan@3 { + reg = <0x03>; + aspeed,fan-tach-ch = /bits/ 8 <0x06 0x07>; + }; + fan@4 { + reg = <0x04>; + aspeed,fan-tach-ch = /bits/ 8 <0x08 0x09>; + }; + fan@5 { + reg = <0x05>; + aspeed,fan-tach-ch = /bits/ 8 <0x0a 0x0b>; + }; +}; + +&gpio { + pin_gpio_i3 { + gpio-hog; + gpios = ; + output-low; + line-name = "NCSI_BMC_R_SEL"; + }; + + pin_gpio_b6 { + gpio-hog; + gpios = ; + output-low; + line-name = "EN_NCSI_SWITCH_N"; + }; +}; + +&video { + status = "okay"; + memory-region = <&video_engine_memory>; +}; + +&vhub { + status = "okay"; +}; -- cgit v1.2.3-59-g8ed1b From abe75295ba70bd1c245977c200ce65575dbaf081 Mon Sep 17 00:00:00 2001 From: John Wang Date: Wed, 14 Oct 2020 16:30:57 +0800 Subject: ARM: dts: aspeed: g220a: Add some gpios Add GPIO STRAP_BMC_BATTERY_GPIOS5, which is used for battery adc sensor. Change the INTRUDER_N to CHASSIS_INTRUSION, to make it more meaningful. Signed-off-by: John Wang Reviewed-by: Joel Stanley Link: https://lore.kernel.org/r/20201014083057.1026-1-wangzhiqiang.bj@bytedance.com Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-bytedance-g220a.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/aspeed-bmc-bytedance-g220a.dts b/arch/arm/boot/dts/aspeed-bmc-bytedance-g220a.dts index 0aeec7017e43..2feb25b0e43b 100644 --- a/arch/arm/boot/dts/aspeed-bmc-bytedance-g220a.dts +++ b/arch/arm/boot/dts/aspeed-bmc-bytedance-g220a.dts @@ -309,11 +309,11 @@ /*N0-N7*/ "","","","","","","","", /*O0-O7*/ "","","","","","","","", /*P0-P7*/ "","","","","","","","", - /*Q0-Q7*/ "","","","","","","FM_PCH_THERMTRIP_N","INTRUDER_N", + /*Q0-Q7*/ "","","","","","","FM_PCH_THERMTRIP_N","CHASSIS_INTRUSION", /*R0-R7*/ "","PVCCIN_CPU1_SMBALERT_N","BMC_PREQ_R_N","FAULT_P12V_PCIE_RISER_N", "ALT_P12V_PCIE_RISER_N","BURN_BOARD_N","PVCCIN_CPU0_SMBALERT_N","", /*S0-S7*/ "BMC_PRDY_N","SIO_POWER_GOOD","FM_BMC_PWR_DEBUG_R_N", - "FM_BMC_XDP_DEBUG_EN","","","","", + "FM_BMC_XDP_DEBUG_EN","","STRAP_BMC_BATTERY_GPIOS5","","", /*T0-T7*/ "","","","","","","","", /*U0-U7*/ "","","","","","","","", /*V0-V7*/ "","","","","","","","", -- cgit v1.2.3-59-g8ed1b From 9e3ed6fa024c7a1be3c41f64da779072c2b85b7f Mon Sep 17 00:00:00 2001 From: George Liu Date: Thu, 22 Oct 2020 16:10:02 +0800 Subject: ARM: dts: Fix label address for 64MiB OpenBMC flash layout Signed-off-by: George Liu Reviewed-by: John Wang Acked-by: Andrew Jeffery Link: https://lore.kernel.org/r/20201022081002.2665132-1-liuxiwei@inspur.com Signed-off-by: Joel Stanley --- arch/arm/boot/dts/openbmc-flash-layout-64.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/openbmc-flash-layout-64.dtsi b/arch/arm/boot/dts/openbmc-flash-layout-64.dtsi index c8e0409d889e..91163867be34 100644 --- a/arch/arm/boot/dts/openbmc-flash-layout-64.dtsi +++ b/arch/arm/boot/dts/openbmc-flash-layout-64.dtsi @@ -13,22 +13,22 @@ partitions { label = "u-boot"; }; - u-boot-env@e0000 { + u-boot-env@60000 { reg = <0x60000 0x20000>; // 128KB label = "u-boot-env"; }; - kernel@100000 { + kernel@80000 { reg = <0x80000 0x500000>; // 5MB label = "kernel"; }; - rofs@a00000 { + rofs@580000 { reg = <0x580000 0x2a80000>; // 42.5MB label = "rofs"; }; - rwfs@6000000 { + rwfs@3000000 { reg = <0x3000000 0x1000000>; // 16MB label = "rwfs"; }; -- cgit v1.2.3-59-g8ed1b From faa3b6dfd2527eace517e0cd1b147154c780d582 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Fri, 28 Aug 2020 21:33:02 +0530 Subject: ARM: dts: imx6q-icore-ofcap10: Use 10.1" Ampire panel compatible Adding display timings directly on device tree files make it difficult to maintain as a same copy of timings may exist on different files or panel-simple driver. We have a panel-simple driver for this particular usage so supporting on this driver will help to use the same timings on any device tree files if the board mounted on a similar vendor display. Engicam C.TOUCH OF 10.1" LCD board uses Ampire 10.1" TFT LCD and it has supported by panel-simple already, so simply use that binding. Signed-off-by: Jagan Teki Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6q-icore-ofcap10.dts | 28 ++++++++++++++++------------ 1 file changed, 16 insertions(+), 12 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx6q-icore-ofcap10.dts b/arch/arm/boot/dts/imx6q-icore-ofcap10.dts index 81cc346dd149..02aca1e28ce3 100644 --- a/arch/arm/boot/dts/imx6q-icore-ofcap10.dts +++ b/arch/arm/boot/dts/imx6q-icore-ofcap10.dts @@ -12,6 +12,17 @@ / { model = "Engicam i.CoreM6 Quad/Dual OpenFrame Capacitive touch 10.1 Kit"; compatible = "engicam,imx6-icore", "fsl,imx6q"; + + panel { + compatible = "ampire,am-1280800n3tzqw-t00h"; + backlight = <&backlight_lvds>; + + port { + panel_in: endpoint { + remote-endpoint = <&lvds0_out>; + }; + }; + }; }; &ldb { @@ -22,18 +33,11 @@ fsl,data-width = <24>; status = "okay"; - display-timings { - native-mode = <&timing0>; - timing0: timing0 { - clock-frequency = <60000000>; - hactive = <1280>; - vactive = <800>; - hback-porch = <40>; - hfront-porch = <40>; - vback-porch = <10>; - vfront-porch = <3>; - hsync-len = <80>; - vsync-len = <10>; + port@4 { + reg = <4>; + + lvds0_out: endpoint { + remote-endpoint = <&panel_in>; }; }; }; -- cgit v1.2.3-59-g8ed1b From 68e680c5faddb207ac4ebb50c88bcc88284bcd5f Mon Sep 17 00:00:00 2001 From: Matthias Schiffer Date: Fri, 18 Sep 2020 13:29:32 +0200 Subject: ARM: dts: imx7-mba7: update compatible strings Include the SoM compatible string. Signed-off-by: Matthias Schiffer Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx7d-mba7.dts | 2 +- arch/arm/boot/dts/imx7s-mba7.dts | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx7d-mba7.dts b/arch/arm/boot/dts/imx7d-mba7.dts index 221274c73dbd..9f4f7112e598 100644 --- a/arch/arm/boot/dts/imx7d-mba7.dts +++ b/arch/arm/boot/dts/imx7d-mba7.dts @@ -14,7 +14,7 @@ / { model = "TQ Systems TQMa7D board on MBa7 carrier board"; - compatible = "tq,imx7d-mba7", "fsl,imx7d"; + compatible = "tq,imx7d-mba7", "tq,imx7d-tqma7", "fsl,imx7d"; }; &fec2 { diff --git a/arch/arm/boot/dts/imx7s-mba7.dts b/arch/arm/boot/dts/imx7s-mba7.dts index a143d566a38b..d7d3f530f843 100644 --- a/arch/arm/boot/dts/imx7s-mba7.dts +++ b/arch/arm/boot/dts/imx7s-mba7.dts @@ -14,5 +14,5 @@ / { model = "TQ Systems TQMa7S board on MBa7 carrier board"; - compatible = "tq,imx7s-mba7", "fsl,imx7s"; + compatible = "tq,imx7s-mba7", "tq,imx7s-tqma7", "fsl,imx7s"; }; -- cgit v1.2.3-59-g8ed1b From f7defed53e35fada087a6bde29810be74576b86e Mon Sep 17 00:00:00 2001 From: Matthias Schiffer Date: Fri, 18 Sep 2020 13:29:33 +0200 Subject: ARM: dts: imx7-mba7: drop incorrect num-chipselects property This property was never set correctly; it should have been num-cs. As num-cs support is being removed as well, simply drop it. Signed-off-by: Matthias Schiffer Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx7-mba7.dtsi | 2 -- 1 file changed, 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx7-mba7.dtsi b/arch/arm/boot/dts/imx7-mba7.dtsi index 50abf18ad30b..d99912ade947 100644 --- a/arch/arm/boot/dts/imx7-mba7.dtsi +++ b/arch/arm/boot/dts/imx7-mba7.dtsi @@ -179,7 +179,6 @@ &ecspi1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi1>; - num-chipselects = <3>; cs-gpios = <&gpio4 0 GPIO_ACTIVE_LOW>, <&gpio4 1 GPIO_ACTIVE_LOW>, <&gpio4 2 GPIO_ACTIVE_LOW>; status = "okay"; @@ -188,7 +187,6 @@ &ecspi2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi2>; - num-chipselects = <1>; status = "okay"; }; -- cgit v1.2.3-59-g8ed1b From 2b01d7a1571b8558dcadee84d575ab31bf39efa2 Mon Sep 17 00:00:00 2001 From: Matthias Schiffer Date: Fri, 18 Sep 2020 13:29:34 +0200 Subject: ARM: dts: imx7-mba7: remove unsupported PHY LED setup These properties were never supported by the DP83867, and a patch implementing them was rejected in favor of a different solution. Remove them. Signed-off-by: Matthias Schiffer Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx7-mba7.dtsi | 4 ---- arch/arm/boot/dts/imx7d-mba7.dts | 4 ---- 2 files changed, 8 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx7-mba7.dtsi b/arch/arm/boot/dts/imx7-mba7.dtsi index d99912ade947..1af40032ab17 100644 --- a/arch/arm/boot/dts/imx7-mba7.dtsi +++ b/arch/arm/boot/dts/imx7-mba7.dtsi @@ -212,10 +212,6 @@ ti,rx-internal-delay = ; ti,tx-internal-delay = ; ti,fifo-depth = ; - /* LED1: Link/Activity, LED2: Error */ - ti,led-function = <0x0db0>; - /* Active low, LED1 and LED2 driven by phy */ - ti,led-ctrl = <0x1001>; }; }; }; diff --git a/arch/arm/boot/dts/imx7d-mba7.dts b/arch/arm/boot/dts/imx7d-mba7.dts index 9f4f7112e598..1101be373ddf 100644 --- a/arch/arm/boot/dts/imx7d-mba7.dts +++ b/arch/arm/boot/dts/imx7d-mba7.dts @@ -39,10 +39,6 @@ ti,rx-internal-delay = ; ti,tx-internal-delay = ; ti,fifo-depth = ; - /* LED1: Link/Activity, LED2: error */ - ti,led-function = <0x0db0>; - /* active low, LED1/2 driven by phy */ - ti,led-ctrl = <0x1001>; }; }; }; -- cgit v1.2.3-59-g8ed1b From e70f9b9c25eae1b1624a976773817470c51d1e9f Mon Sep 17 00:00:00 2001 From: Matthias Schiffer Date: Fri, 18 Sep 2020 13:29:35 +0200 Subject: ARM: dts: imx7-mba7: disable ethernet PHY clock outputs The clock outputs are not connected. Disable them to improve EMI behaviour. Signed-off-by: Matthias Schiffer Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx7-mba7.dtsi | 1 + arch/arm/boot/dts/imx7d-mba7.dts | 1 + 2 files changed, 2 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx7-mba7.dtsi b/arch/arm/boot/dts/imx7-mba7.dtsi index 1af40032ab17..9be225bb135a 100644 --- a/arch/arm/boot/dts/imx7-mba7.dtsi +++ b/arch/arm/boot/dts/imx7-mba7.dtsi @@ -212,6 +212,7 @@ ti,rx-internal-delay = ; ti,tx-internal-delay = ; ti,fifo-depth = ; + ti,clk-output-sel = ; }; }; }; diff --git a/arch/arm/boot/dts/imx7d-mba7.dts b/arch/arm/boot/dts/imx7d-mba7.dts index 1101be373ddf..5ef86de53013 100644 --- a/arch/arm/boot/dts/imx7d-mba7.dts +++ b/arch/arm/boot/dts/imx7d-mba7.dts @@ -39,6 +39,7 @@ ti,rx-internal-delay = ; ti,tx-internal-delay = ; ti,fifo-depth = ; + ti,clk-output-sel = ; }; }; }; -- cgit v1.2.3-59-g8ed1b From d50765205d8e59e4116a9dc512305cef15e70ad2 Mon Sep 17 00:00:00 2001 From: Matthias Schiffer Date: Fri, 18 Sep 2020 13:29:36 +0200 Subject: ARM: dts: imx7-mba7: configure watchdog The external watchdog reset is necessary, as the internal reset is unreliable on i.MX7. Signed-off-by: Matthias Schiffer Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx7-mba7.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx7-mba7.dtsi b/arch/arm/boot/dts/imx7-mba7.dtsi index 9be225bb135a..84b5809f384c 100644 --- a/arch/arm/boot/dts/imx7-mba7.dtsi +++ b/arch/arm/boot/dts/imx7-mba7.dtsi @@ -467,6 +467,12 @@ MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5 0x59 >; }; + + pinctrl_wdog1: wdog1grp { + fsl,pins = < + MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x30 + >; + }; }; &pwm1 { @@ -543,3 +549,9 @@ no-1-8-v; status = "okay"; }; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog1>; + fsl,ext-reset-output; +}; -- cgit v1.2.3-59-g8ed1b From ecb5ba9f112424ed43907cd95ddf6a5eb8c0e6fe Mon Sep 17 00:00:00 2001 From: Matthias Schiffer Date: Fri, 18 Sep 2020 13:29:37 +0200 Subject: ARM: dts: imx7-mba7: update MMC aliases Together with the recently merged support for alias-based MMC host numbering, this makes the MMC devices names match what the bootloader expects. Signed-off-by: Matthias Schiffer Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx7-mba7.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx7-mba7.dtsi b/arch/arm/boot/dts/imx7-mba7.dtsi index 84b5809f384c..215730e0453e 100644 --- a/arch/arm/boot/dts/imx7-mba7.dtsi +++ b/arch/arm/boot/dts/imx7-mba7.dtsi @@ -14,6 +14,12 @@ #include / { + aliases { + mmc0 = &usdhc3; + mmc1 = &usdhc1; + /delete-property/ mmc2; + }; + beeper { compatible = "gpio-beeper"; gpios = <&pca9555 0 GPIO_ACTIVE_HIGH>; -- cgit v1.2.3-59-g8ed1b From 0d5e50cf30d7c6ec56013234595ddefdaba64593 Mon Sep 17 00:00:00 2001 From: Matthias Schiffer Date: Fri, 18 Sep 2020 13:29:38 +0200 Subject: ARM: dts: imx7-mba7: add audio support The MBa7x is equipped with a TI TLV320AIC3204 audio codec. Signed-off-by: Matthias Schiffer Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx7-mba7.dtsi | 38 +++++++++++++++++++++++++++++++++++++- 1 file changed, 37 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx7-mba7.dtsi b/arch/arm/boot/dts/imx7-mba7.dtsi index 215730e0453e..9cfaf0a91100 100644 --- a/arch/arm/boot/dts/imx7-mba7.dtsi +++ b/arch/arm/boot/dts/imx7-mba7.dtsi @@ -170,6 +170,20 @@ regulator-max-microvolt = <3300000>; regulator-always-on; }; + + sound { + compatible = "fsl,imx-audio-tlv320aic32x4"; + model = "imx-audio-tlv320aic32x4"; + ssi-controller = <&sai1>; + audio-codec = <&tlv320aic32x4>; + audio-routing = + "IN3_L", "Mic Jack", + "Mic Jack", "Mic Bias", + "IN1_L", "Line In Jack", + "IN1_R", "Line In Jack", + "Line Out Jack", "LOL", + "Line Out Jack", "LOR"; + }; }; &adc1 { @@ -363,13 +377,25 @@ >; }; - pinctrl_pca9555: pca95550grp { fsl,pins = < MX7D_PAD_ENET1_TX_CLK__GPIO7_IO12 0x78 >; }; + pinctrl_sai1: sai1grp { + fsl,pins = < + MX7D_PAD_SAI1_MCLK__SAI1_MCLK 0x11 + MX7D_PAD_SAI1_RX_BCLK__SAI1_RX_BCLK 0x1c + MX7D_PAD_SAI1_RX_DATA__SAI1_RX_DATA0 0x1c + MX7D_PAD_SAI1_RX_SYNC__SAI2_RX_SYNC 0x1c + + MX7D_PAD_SAI1_TX_BCLK__SAI1_TX_BCLK 0x1c + MX7D_PAD_SAI1_TX_DATA__SAI1_TX_DATA0 0x14 + MX7D_PAD_SAI1_TX_SYNC__SAI1_TX_SYNC 0x14 + >; + }; + pinctrl_uart3: uart3grp { fsl,pins = < MX7D_PAD_UART3_RX_DATA__UART3_DCE_RX 0x7e @@ -487,6 +513,16 @@ status = "okay"; }; +&sai1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai1>; + assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>, + <&clks IMX7D_SAI1_ROOT_CLK>; + assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>; + assigned-clock-rates = <0>, <36864000>; + status = "okay"; +}; + &uart3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart3>; -- cgit v1.2.3-59-g8ed1b From 9af6702fa1e3ecdbed8c297e3c08103c2ceda112 Mon Sep 17 00:00:00 2001 From: Matthias Schiffer Date: Fri, 18 Sep 2020 13:29:40 +0200 Subject: ARM: dts: imx7-mba7: enable RS485 on UART7 The UART7 interface is connected to a full-duplex RS485 transceiver. Signed-off-by: Matthias Schiffer Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx7-mba7.dtsi | 3 +++ 1 file changed, 3 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx7-mba7.dtsi b/arch/arm/boot/dts/imx7-mba7.dtsi index 9cfaf0a91100..ea9f0a4ac4b5 100644 --- a/arch/arm/boot/dts/imx7-mba7.dtsi +++ b/arch/arm/boot/dts/imx7-mba7.dtsi @@ -561,6 +561,9 @@ assigned-clocks = <&clks IMX7D_UART7_ROOT_SRC>; assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; uart-has-rtscts; + linux,rs485-enabled-at-boot-time; + rs485-rts-active-low; + rs485-rx-during-tx; status = "okay"; }; -- cgit v1.2.3-59-g8ed1b From b8a4f64a3277fd30b1ee04bacf03d0dd3f5ade88 Mon Sep 17 00:00:00 2001 From: Matthias Schiffer Date: Fri, 18 Sep 2020 13:29:41 +0200 Subject: ARM: dts: imx7-mba7: specify USB over-current polarity Add over-current-active-low to usbotg1. Signed-off-by: Matthias Schiffer Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx7-mba7.dtsi | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx7-mba7.dtsi b/arch/arm/boot/dts/imx7-mba7.dtsi index ea9f0a4ac4b5..f9704c354e1d 100644 --- a/arch/arm/boot/dts/imx7-mba7.dtsi +++ b/arch/arm/boot/dts/imx7-mba7.dtsi @@ -578,6 +578,7 @@ srp-disable; hnp-disable; adp-disable; + over-current-active-low; dr_mode = "host"; status = "okay"; }; -- cgit v1.2.3-59-g8ed1b From 42ab1ba8873d0b144a9417231e7b15a26b6137ad Mon Sep 17 00:00:00 2001 From: Matthias Schiffer Date: Fri, 18 Sep 2020 13:29:42 +0200 Subject: ARM: dts: imx7-mba7: set dr_mode to otg on usbotg1 USBOTG1 has a Micro-USB port that can be used in host mode (using an OTG cable) or device mode. Signed-off-by: Matthias Schiffer Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx7-mba7.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx7-mba7.dtsi b/arch/arm/boot/dts/imx7-mba7.dtsi index f9704c354e1d..c6d1c63f7905 100644 --- a/arch/arm/boot/dts/imx7-mba7.dtsi +++ b/arch/arm/boot/dts/imx7-mba7.dtsi @@ -579,7 +579,7 @@ hnp-disable; adp-disable; over-current-active-low; - dr_mode = "host"; + dr_mode = "otg"; status = "okay"; }; -- cgit v1.2.3-59-g8ed1b From a8d54a39e95f5cff7ba25b344cbab9b598bbf937 Mon Sep 17 00:00:00 2001 From: Stefan Riedmueller Date: Tue, 22 Sep 2020 11:23:08 +0200 Subject: ARM: dts: imx6ul: segin: Fix stmpe touchscreen subnode name The touchscreen subnode name needs to be stmpe_touchscreen as mentioned in the dt-bindings. Signed-off-by: Stefan Riedmueller Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6ul-phytec-segin.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx6ul-phytec-segin.dtsi b/arch/arm/boot/dts/imx6ul-phytec-segin.dtsi index f1513e676c2f..7367279748f4 100644 --- a/arch/arm/boot/dts/imx6ul-phytec-segin.dtsi +++ b/arch/arm/boot/dts/imx6ul-phytec-segin.dtsi @@ -139,7 +139,7 @@ pinctrl-0 = <&pinctrl_stmpe>; status = "disabled"; - touchscreen { + stmpe_touchscreen { compatible = "st,stmpe-ts"; st,sample-time = <4>; st,mod-12b = <1>; -- cgit v1.2.3-59-g8ed1b From f0e24ec59076df374d4e8f15a9658e140858afb0 Mon Sep 17 00:00:00 2001 From: Stefan Riedmueller Date: Tue, 22 Sep 2020 11:23:09 +0200 Subject: ARM: dts: imx6: phytec: Set correct eeprom compatible Set the correct EEPROM compatible for phyCORE-i.MX 6 and phyFLEX-i.MX 6, as stated in the device tree bindings. Signed-off-by: Stefan Riedmueller Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi | 2 +- arch/arm/boot/dts/imx6qdl-phytec-phycore-som.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi index e361df26a168..d51852857758 100644 --- a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi +++ b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi @@ -116,7 +116,7 @@ status = "okay"; som_eeprom: eeprom@50 { - compatible = "atmel,24c32"; + compatible = "catalyst,24c32", "atmel,24c32"; reg = <0x50>; }; diff --git a/arch/arm/boot/dts/imx6qdl-phytec-phycore-som.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-phycore-som.dtsi index 41ebe4599e43..a3f4e8f6cc9e 100644 --- a/arch/arm/boot/dts/imx6qdl-phytec-phycore-som.dtsi +++ b/arch/arm/boot/dts/imx6qdl-phytec-phycore-som.dtsi @@ -84,7 +84,7 @@ status = "okay"; eeprom@50 { - compatible = "atmel,24c32"; + compatible = "st,24c32", "atmel,24c32"; reg = <0x50>; }; -- cgit v1.2.3-59-g8ed1b From 0d31d5a96b8c6c5914995f4352c2ab50e50a1865 Mon Sep 17 00:00:00 2001 From: Stefan Riedmueller Date: Tue, 22 Sep 2020 11:23:10 +0200 Subject: ARM: dts: imx6: phytec: Add eeprom pagesize Defining the EEPROM pagesize can increase the write speed significantly. Set it to the pagesize stated in the EEPROM's datasheet for phyCORE-i.MX 6UL, phyCORE-i.MX 6 and phyFLEX-i.MX 6. Signed-off-by: Stefan Riedmueller Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi | 1 + arch/arm/boot/dts/imx6qdl-phytec-phycore-som.dtsi | 1 + arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi | 1 + 3 files changed, 3 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi index d51852857758..7a1e53195785 100644 --- a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi +++ b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi @@ -117,6 +117,7 @@ som_eeprom: eeprom@50 { compatible = "catalyst,24c32", "atmel,24c32"; + pagesize = <32>; reg = <0x50>; }; diff --git a/arch/arm/boot/dts/imx6qdl-phytec-phycore-som.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-phycore-som.dtsi index a3f4e8f6cc9e..a80aa08a37cb 100644 --- a/arch/arm/boot/dts/imx6qdl-phytec-phycore-som.dtsi +++ b/arch/arm/boot/dts/imx6qdl-phytec-phycore-som.dtsi @@ -85,6 +85,7 @@ eeprom@50 { compatible = "st,24c32", "atmel,24c32"; + pagesize = <32>; reg = <0x50>; }; diff --git a/arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi b/arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi index 88f631c8fabb..19a062635ff6 100644 --- a/arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi +++ b/arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi @@ -75,6 +75,7 @@ eeprom@52 { compatible = "catalyst,24c32", "atmel,24c32"; + pagesize = <32>; reg = <0x52>; }; }; -- cgit v1.2.3-59-g8ed1b From fc2933c133744305236793025b00c2f7d258b687 Mon Sep 17 00:00:00 2001 From: Ard Biesheuvel Date: Wed, 28 Oct 2020 14:20:55 +0100 Subject: ARM: 9020/1: mm: use correct section size macro to describe the FDT virtual address Commit 149a3ffe62b9dbc3 ("9012/1: move device tree mapping out of linear region") created a permanent, read-only section mapping of the device tree blob provided by the firmware, and added a set of macros to get the base and size of the virtually mapped FDT based on the physical address. However, while the mapping code uses the SECTION_SIZE macro correctly, the macros use PMD_SIZE instead, which means something entirely different on ARM when using short descriptors, and is therefore not the right quantity to use here. So replace PMD_SIZE with SECTION_SIZE. While at it, change the names of the macro and its parameter to clarify that it returns the virtual address of the start of the FDT, based on the physical address in memory. Tested-by: Joel Stanley Tested-by: Marek Szyprowski Signed-off-by: Ard Biesheuvel Signed-off-by: Russell King --- arch/arm/include/asm/memory.h | 6 +++--- arch/arm/kernel/setup.c | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h index 598dbdca2017..38a163f50130 100644 --- a/arch/arm/include/asm/memory.h +++ b/arch/arm/include/asm/memory.h @@ -73,8 +73,8 @@ #define XIP_VIRT_ADDR(physaddr) (MODULES_VADDR + ((physaddr) & 0x000fffff)) #define FDT_FIXED_BASE UL(0xff800000) -#define FDT_FIXED_SIZE (2 * PMD_SIZE) -#define FDT_VIRT_ADDR(physaddr) ((void *)(FDT_FIXED_BASE | (physaddr) % PMD_SIZE)) +#define FDT_FIXED_SIZE (2 * SECTION_SIZE) +#define FDT_VIRT_BASE(physbase) ((void *)(FDT_FIXED_BASE | (physbase) % SECTION_SIZE)) #if !defined(CONFIG_SMP) && !defined(CONFIG_ARM_LPAE) /* @@ -116,7 +116,7 @@ extern unsigned long vectors_base; #define MODULES_VADDR PAGE_OFFSET #define XIP_VIRT_ADDR(physaddr) (physaddr) -#define FDT_VIRT_ADDR(physaddr) ((void *)(physaddr)) +#define FDT_VIRT_BASE(physbase) ((void *)(physbase)) #endif /* !CONFIG_MMU */ diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c index f4bd8b654255..d32f7652a5bf 100644 --- a/arch/arm/kernel/setup.c +++ b/arch/arm/kernel/setup.c @@ -1087,7 +1087,7 @@ void __init setup_arch(char **cmdline_p) void *atags_vaddr = NULL; if (__atags_pointer) - atags_vaddr = FDT_VIRT_ADDR(__atags_pointer); + atags_vaddr = FDT_VIRT_BASE(__atags_pointer); setup_processor(); if (atags_vaddr) { -- cgit v1.2.3-59-g8ed1b From 4e79f0211b473f8e1eab8211a9fd50cc41a3a061 Mon Sep 17 00:00:00 2001 From: Ard Biesheuvel Date: Mon, 21 Sep 2020 00:10:16 +0200 Subject: ARM: p2v: fix handling of LPAE translation in BE mode When running in BE mode on LPAE hardware with a PA-to-VA translation that exceeds 4 GB, we patch bits 39:32 of the offset into the wrong byte of the opcode. So fix that, by rotating the offset in r0 to the right by 8 bits, which will put the 8-bit immediate in bits 31:24. Note that this will also move bit #22 in its correct place when applying the rotation to the constant #0x400000. Fixes: d9a790df8e984 ("ARM: 7883/1: fix mov to mvn conversion in case of 64 bit phys_addr_t and BE") Acked-by: Nicolas Pitre Reviewed-by: Linus Walleij Signed-off-by: Ard Biesheuvel --- arch/arm/kernel/head.S | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S index f8904227e7fd..98c1e68bdfcb 100644 --- a/arch/arm/kernel/head.S +++ b/arch/arm/kernel/head.S @@ -671,12 +671,8 @@ ARM_BE8(rev16 ip, ip) ldrcc r7, [r4], #4 @ use branch for delay slot bcc 1b bx lr -#else -#ifdef CONFIG_CPU_ENDIAN_BE8 - moveq r0, #0x00004000 @ set bit 22, mov to mvn instruction #else moveq r0, #0x400000 @ set bit 22, mov to mvn instruction -#endif b 2f 1: ldr ip, [r7, r3] #ifdef CONFIG_CPU_ENDIAN_BE8 @@ -685,7 +681,7 @@ ARM_BE8(rev16 ip, ip) tst ip, #0x000f0000 @ check the rotation field orrne ip, ip, r6, lsl #24 @ mask in offset bits 31-24 biceq ip, ip, #0x00004000 @ clear bit 22 - orreq ip, ip, r0 @ mask in offset bits 7-0 + orreq ip, ip, r0, ror #8 @ mask in offset bits 7-0 #else bic ip, ip, #0x000000ff tst ip, #0xf00 @ check the rotation field -- cgit v1.2.3-59-g8ed1b From 0b1674638a5c69cbace63278625c199100955490 Mon Sep 17 00:00:00 2001 From: Ard Biesheuvel Date: Mon, 14 Sep 2020 11:23:39 +0300 Subject: ARM: assembler: introduce adr_l, ldr_l and str_l macros Like arm64, ARM supports position independent code sequences that produce symbol references with a greater reach than the ordinary adr/ldr instructions. Since on ARM, the adrl pseudo-instruction is only supported in ARM mode (and not at all when using Clang), having a adr_l macro like we do on arm64 is useful, and increases symmetry as well. Currently, we use open coded instruction sequences involving literals and arithmetic operations. Instead, we can use movw/movt pairs on v7 CPUs, circumventing the D-cache entirely. E.g., on v7+ CPUs, we can emit a PC-relative reference as follows: movw , #:lower16: - (1f + 8) movt , #:upper16: - (1f + 8) 1: add , , pc For older CPUs, we can emit the literal into a subsection, allowing it to be emitted out of line while retaining the ability to perform arithmetic on label offsets. E.g., on pre-v7 CPUs, we can emit a PC-relative reference as follows: ldr , 2f 1: add , , pc .subsection 1 2: .long - (1b + 8) .previous This is allowed by the assembler because, unlike ordinary sections, subsections are combined into a single section in the object file, and so the label references are not true cross-section references that are visible as relocations. (Subsections have been available in binutils since 2004 at least, so they should not cause any issues with older toolchains.) So use the above to implement the macros mov_l, adr_l, ldr_l and str_l, all of which will use movw/movt pairs on v7 and later CPUs, and use PC-relative literals otherwise. Reviewed-by: Nicolas Pitre Reviewed-by: Linus Walleij Signed-off-by: Ard Biesheuvel --- arch/arm/include/asm/assembler.h | 84 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 84 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h index feac2c8b86f2..72627c5fb3b2 100644 --- a/arch/arm/include/asm/assembler.h +++ b/arch/arm/include/asm/assembler.h @@ -494,4 +494,88 @@ THUMB( orr \reg , \reg , #PSR_T_BIT ) #define _ASM_NOKPROBE(entry) #endif + .macro __adldst_l, op, reg, sym, tmp, c + .if __LINUX_ARM_ARCH__ < 7 + ldr\c \tmp, .La\@ + .subsection 1 + .align 2 +.La\@: .long \sym - .Lpc\@ + .previous + .else + .ifnb \c + THUMB( ittt \c ) + .endif + movw\c \tmp, #:lower16:\sym - .Lpc\@ + movt\c \tmp, #:upper16:\sym - .Lpc\@ + .endif + +#ifndef CONFIG_THUMB2_KERNEL + .set .Lpc\@, . + 8 // PC bias + .ifc \op, add + add\c \reg, \tmp, pc + .else + \op\c \reg, [pc, \tmp] + .endif +#else +.Lb\@: add\c \tmp, \tmp, pc + /* + * In Thumb-2 builds, the PC bias depends on whether we are currently + * emitting into a .arm or a .thumb section. The size of the add opcode + * above will be 2 bytes when emitting in Thumb mode and 4 bytes when + * emitting in ARM mode, so let's use this to account for the bias. + */ + .set .Lpc\@, . + (. - .Lb\@) + + .ifnc \op, add + \op\c \reg, [\tmp] + .endif +#endif + .endm + + /* + * mov_l - move a constant value or [relocated] address into a register + */ + .macro mov_l, dst:req, imm:req + .if __LINUX_ARM_ARCH__ < 7 + ldr \dst, =\imm + .else + movw \dst, #:lower16:\imm + movt \dst, #:upper16:\imm + .endif + .endm + + /* + * adr_l - adr pseudo-op with unlimited range + * + * @dst: destination register + * @sym: name of the symbol + * @cond: conditional opcode suffix + */ + .macro adr_l, dst:req, sym:req, cond + __adldst_l add, \dst, \sym, \dst, \cond + .endm + + /* + * ldr_l - ldr pseudo-op with unlimited range + * + * @dst: destination register + * @sym: name of the symbol + * @cond: conditional opcode suffix + */ + .macro ldr_l, dst:req, sym:req, cond + __adldst_l ldr, \dst, \sym, \dst, \cond + .endm + + /* + * str_l - str pseudo-op with unlimited range + * + * @src: source register + * @sym: name of the symbol + * @tmp: mandatory scratch register + * @cond: conditional opcode suffix + */ + .macro str_l, src:req, sym:req, tmp:req, cond + __adldst_l str, \src, \sym, \tmp, \cond + .endm + #endif /* __ASM_ASSEMBLER_H__ */ -- cgit v1.2.3-59-g8ed1b From 22f2d23098f7d34fc5142531cffb241d14611684 Mon Sep 17 00:00:00 2001 From: Ard Biesheuvel Date: Mon, 14 Sep 2020 11:24:37 +0300 Subject: ARM: module: add support for place relative relocations When using the new adr_l/ldr_l/str_l macros to refer to external symbols from modules, the linker may emit place relative ELF relocations that need to be fixed up by the module loader. So add support for these. Reviewed-by: Nicolas Pitre Signed-off-by: Ard Biesheuvel --- arch/arm/include/asm/elf.h | 5 +++++ arch/arm/kernel/module.c | 20 ++++++++++++++++++-- 2 files changed, 23 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/include/asm/elf.h b/arch/arm/include/asm/elf.h index b078d992414b..0ac62a54b73c 100644 --- a/arch/arm/include/asm/elf.h +++ b/arch/arm/include/asm/elf.h @@ -51,6 +51,7 @@ typedef struct user_fp elf_fpregset_t; #define R_ARM_NONE 0 #define R_ARM_PC24 1 #define R_ARM_ABS32 2 +#define R_ARM_REL32 3 #define R_ARM_CALL 28 #define R_ARM_JUMP24 29 #define R_ARM_TARGET1 38 @@ -58,11 +59,15 @@ typedef struct user_fp elf_fpregset_t; #define R_ARM_PREL31 42 #define R_ARM_MOVW_ABS_NC 43 #define R_ARM_MOVT_ABS 44 +#define R_ARM_MOVW_PREL_NC 45 +#define R_ARM_MOVT_PREL 46 #define R_ARM_THM_CALL 10 #define R_ARM_THM_JUMP24 30 #define R_ARM_THM_MOVW_ABS_NC 47 #define R_ARM_THM_MOVT_ABS 48 +#define R_ARM_THM_MOVW_PREL_NC 49 +#define R_ARM_THM_MOVT_PREL 50 /* * These are used to set parameters in the core dumps. diff --git a/arch/arm/kernel/module.c b/arch/arm/kernel/module.c index e15444b25ca0..beac45e89ba6 100644 --- a/arch/arm/kernel/module.c +++ b/arch/arm/kernel/module.c @@ -185,14 +185,24 @@ apply_relocate(Elf32_Shdr *sechdrs, const char *strtab, unsigned int symindex, *(u32 *)loc |= offset & 0x7fffffff; break; + case R_ARM_REL32: + *(u32 *)loc += sym->st_value - loc; + break; + case R_ARM_MOVW_ABS_NC: case R_ARM_MOVT_ABS: + case R_ARM_MOVW_PREL_NC: + case R_ARM_MOVT_PREL: offset = tmp = __mem_to_opcode_arm(*(u32 *)loc); offset = ((offset & 0xf0000) >> 4) | (offset & 0xfff); offset = (offset ^ 0x8000) - 0x8000; offset += sym->st_value; - if (ELF32_R_TYPE(rel->r_info) == R_ARM_MOVT_ABS) + if (ELF32_R_TYPE(rel->r_info) == R_ARM_MOVT_PREL || + ELF32_R_TYPE(rel->r_info) == R_ARM_MOVW_PREL_NC) + offset -= loc; + if (ELF32_R_TYPE(rel->r_info) == R_ARM_MOVT_ABS || + ELF32_R_TYPE(rel->r_info) == R_ARM_MOVT_PREL) offset >>= 16; tmp &= 0xfff0f000; @@ -283,6 +293,8 @@ apply_relocate(Elf32_Shdr *sechdrs, const char *strtab, unsigned int symindex, case R_ARM_THM_MOVW_ABS_NC: case R_ARM_THM_MOVT_ABS: + case R_ARM_THM_MOVW_PREL_NC: + case R_ARM_THM_MOVT_PREL: upper = __mem_to_opcode_thumb16(*(u16 *)loc); lower = __mem_to_opcode_thumb16(*(u16 *)(loc + 2)); @@ -302,7 +314,11 @@ apply_relocate(Elf32_Shdr *sechdrs, const char *strtab, unsigned int symindex, offset = (offset ^ 0x8000) - 0x8000; offset += sym->st_value; - if (ELF32_R_TYPE(rel->r_info) == R_ARM_THM_MOVT_ABS) + if (ELF32_R_TYPE(rel->r_info) == R_ARM_THM_MOVT_PREL || + ELF32_R_TYPE(rel->r_info) == R_ARM_THM_MOVW_PREL_NC) + offset -= loc; + if (ELF32_R_TYPE(rel->r_info) == R_ARM_THM_MOVT_ABS || + ELF32_R_TYPE(rel->r_info) == R_ARM_THM_MOVT_PREL) offset >>= 16; upper = (u16)((upper & 0xfbf0) | -- cgit v1.2.3-59-g8ed1b From eae78e1a97201a81a851342ad9659b60f61a3951 Mon Sep 17 00:00:00 2001 From: Ard Biesheuvel Date: Sun, 20 Sep 2020 17:51:55 +0200 Subject: ARM: p2v: move patching code to separate assembler source file Move the phys2virt patching code into a separate .S file before doing some work on it. Suggested-by: Nicolas Pitre Reviewed-by: Linus Walleij Signed-off-by: Ard Biesheuvel --- arch/arm/kernel/Makefile | 1 + arch/arm/kernel/head.S | 138 ---------------------------------------- arch/arm/kernel/phys2virt.S | 151 ++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 152 insertions(+), 138 deletions(-) create mode 100644 arch/arm/kernel/phys2virt.S (limited to 'arch/arm') diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile index 89e5d864e923..9e465efcc8b6 100644 --- a/arch/arm/kernel/Makefile +++ b/arch/arm/kernel/Makefile @@ -92,6 +92,7 @@ obj-$(CONFIG_PARAVIRT) += paravirt.o head-y := head$(MMUEXT).o obj-$(CONFIG_DEBUG_LL) += debug.o obj-$(CONFIG_EARLY_PRINTK) += early_printk.o +obj-$(CONFIG_ARM_PATCH_PHYS_VIRT) += phys2virt.o # This is executed very early using a temporary stack when no memory allocator # nor global data is available. Everything has to be allocated on the stack. diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S index 98c1e68bdfcb..7e3f36809011 100644 --- a/arch/arm/kernel/head.S +++ b/arch/arm/kernel/head.S @@ -586,142 +586,4 @@ ENTRY(fixup_smp) ldmfd sp!, {r4 - r6, pc} ENDPROC(fixup_smp) -#ifdef __ARMEB__ -#define LOW_OFFSET 0x4 -#define HIGH_OFFSET 0x0 -#else -#define LOW_OFFSET 0x0 -#define HIGH_OFFSET 0x4 -#endif - -#ifdef CONFIG_ARM_PATCH_PHYS_VIRT - -/* __fixup_pv_table - patch the stub instructions with the delta between - * PHYS_OFFSET and PAGE_OFFSET, which is assumed to be 16MiB aligned and - * can be expressed by an immediate shifter operand. The stub instruction - * has a form of '(add|sub) rd, rn, #imm'. - */ - __HEAD -__fixup_pv_table: - adr r0, 1f - ldmia r0, {r3-r7} - mvn ip, #0 - subs r3, r0, r3 @ PHYS_OFFSET - PAGE_OFFSET - add r4, r4, r3 @ adjust table start address - add r5, r5, r3 @ adjust table end address - add r6, r6, r3 @ adjust __pv_phys_pfn_offset address - add r7, r7, r3 @ adjust __pv_offset address - mov r0, r8, lsr #PAGE_SHIFT @ convert to PFN - str r0, [r6] @ save computed PHYS_OFFSET to __pv_phys_pfn_offset - strcc ip, [r7, #HIGH_OFFSET] @ save to __pv_offset high bits - mov r6, r3, lsr #24 @ constant for add/sub instructions - teq r3, r6, lsl #24 @ must be 16MiB aligned -THUMB( it ne @ cross section branch ) - bne __error - str r3, [r7, #LOW_OFFSET] @ save to __pv_offset low bits - b __fixup_a_pv_table -ENDPROC(__fixup_pv_table) - - .align -1: .long . - .long __pv_table_begin - .long __pv_table_end -2: .long __pv_phys_pfn_offset - .long __pv_offset - - .text -__fixup_a_pv_table: - adr r0, 3f - ldr r6, [r0] - add r6, r6, r3 - ldr r0, [r6, #HIGH_OFFSET] @ pv_offset high word - ldr r6, [r6, #LOW_OFFSET] @ pv_offset low word - mov r6, r6, lsr #24 - cmn r0, #1 -#ifdef CONFIG_THUMB2_KERNEL - moveq r0, #0x200000 @ set bit 21, mov to mvn instruction - lsls r6, #24 - beq 2f - clz r7, r6 - lsr r6, #24 - lsl r6, r7 - bic r6, #0x0080 - lsrs r7, #1 - orrcs r6, #0x0080 - orr r6, r6, r7, lsl #12 - orr r6, #0x4000 - b 2f -1: add r7, r3 - ldrh ip, [r7, #2] -ARM_BE8(rev16 ip, ip) - tst ip, #0x4000 - and ip, #0x8f00 - orrne ip, r6 @ mask in offset bits 31-24 - orreq ip, r0 @ mask in offset bits 7-0 -ARM_BE8(rev16 ip, ip) - strh ip, [r7, #2] - bne 2f - ldrh ip, [r7] -ARM_BE8(rev16 ip, ip) - bic ip, #0x20 - orr ip, ip, r0, lsr #16 -ARM_BE8(rev16 ip, ip) - strh ip, [r7] -2: cmp r4, r5 - ldrcc r7, [r4], #4 @ use branch for delay slot - bcc 1b - bx lr -#else - moveq r0, #0x400000 @ set bit 22, mov to mvn instruction - b 2f -1: ldr ip, [r7, r3] -#ifdef CONFIG_CPU_ENDIAN_BE8 - @ in BE8, we load data in BE, but instructions still in LE - bic ip, ip, #0xff000000 - tst ip, #0x000f0000 @ check the rotation field - orrne ip, ip, r6, lsl #24 @ mask in offset bits 31-24 - biceq ip, ip, #0x00004000 @ clear bit 22 - orreq ip, ip, r0, ror #8 @ mask in offset bits 7-0 -#else - bic ip, ip, #0x000000ff - tst ip, #0xf00 @ check the rotation field - orrne ip, ip, r6 @ mask in offset bits 31-24 - biceq ip, ip, #0x400000 @ clear bit 22 - orreq ip, ip, r0 @ mask in offset bits 7-0 -#endif - str ip, [r7, r3] -2: cmp r4, r5 - ldrcc r7, [r4], #4 @ use branch for delay slot - bcc 1b - ret lr -#endif -ENDPROC(__fixup_a_pv_table) - - .align -3: .long __pv_offset - -ENTRY(fixup_pv_table) - stmfd sp!, {r4 - r7, lr} - mov r3, #0 @ no offset - mov r4, r0 @ r0 = table start - add r5, r0, r1 @ r1 = table size - bl __fixup_a_pv_table - ldmfd sp!, {r4 - r7, pc} -ENDPROC(fixup_pv_table) - - .data - .align 2 - .globl __pv_phys_pfn_offset - .type __pv_phys_pfn_offset, %object -__pv_phys_pfn_offset: - .word 0 - .size __pv_phys_pfn_offset, . -__pv_phys_pfn_offset - - .globl __pv_offset - .type __pv_offset, %object -__pv_offset: - .quad 0 - .size __pv_offset, . -__pv_offset -#endif - #include "head-common.S" diff --git a/arch/arm/kernel/phys2virt.S b/arch/arm/kernel/phys2virt.S new file mode 100644 index 000000000000..7c17fbfeeedd --- /dev/null +++ b/arch/arm/kernel/phys2virt.S @@ -0,0 +1,151 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 1994-2002 Russell King + * Copyright (c) 2003 ARM Limited + * All Rights Reserved + */ + +#include +#include +#include +#include + +#ifdef __ARMEB__ +#define LOW_OFFSET 0x4 +#define HIGH_OFFSET 0x0 +#else +#define LOW_OFFSET 0x0 +#define HIGH_OFFSET 0x4 +#endif + +/* + * __fixup_pv_table - patch the stub instructions with the delta between + * PHYS_OFFSET and PAGE_OFFSET, which is assumed to be + * 16MiB aligned. + * + * Called from head.S, which expects the following registers to be preserved: + * r1 = machine no, r2 = atags or dtb, + * r8 = phys_offset, r9 = cpuid, r10 = procinfo + */ + __HEAD +ENTRY(__fixup_pv_table) + adr r0, 1f + ldmia r0, {r3-r7} + mvn ip, #0 + subs r3, r0, r3 @ PHYS_OFFSET - PAGE_OFFSET + add r4, r4, r3 @ adjust table start address + add r5, r5, r3 @ adjust table end address + add r6, r6, r3 @ adjust __pv_phys_pfn_offset address + add r7, r7, r3 @ adjust __pv_offset address + mov r0, r8, lsr #PAGE_SHIFT @ convert to PFN + str r0, [r6] @ save computed PHYS_OFFSET to __pv_phys_pfn_offset + strcc ip, [r7, #HIGH_OFFSET] @ save to __pv_offset high bits + mov r6, r3, lsr #24 @ constant for add/sub instructions + teq r3, r6, lsl #24 @ must be 16MiB aligned + bne 0f + str r3, [r7, #LOW_OFFSET] @ save to __pv_offset low bits + b __fixup_a_pv_table +0: mov r0, r0 @ deadloop on error + b 0b +ENDPROC(__fixup_pv_table) + + .align +1: .long . + .long __pv_table_begin + .long __pv_table_end +2: .long __pv_phys_pfn_offset + .long __pv_offset + + .text +__fixup_a_pv_table: + adr r0, 3f + ldr r6, [r0] + add r6, r6, r3 + ldr r0, [r6, #HIGH_OFFSET] @ pv_offset high word + ldr r6, [r6, #LOW_OFFSET] @ pv_offset low word + mov r6, r6, lsr #24 + cmn r0, #1 +#ifdef CONFIG_THUMB2_KERNEL + moveq r0, #0x200000 @ set bit 21, mov to mvn instruction + lsls r6, #24 + beq 2f + clz r7, r6 + lsr r6, #24 + lsl r6, r7 + bic r6, #0x0080 + lsrs r7, #1 + orrcs r6, #0x0080 + orr r6, r6, r7, lsl #12 + orr r6, #0x4000 + b 2f +1: add r7, r3 + ldrh ip, [r7, #2] +ARM_BE8(rev16 ip, ip) + tst ip, #0x4000 + and ip, #0x8f00 + orrne ip, r6 @ mask in offset bits 31-24 + orreq ip, r0 @ mask in offset bits 7-0 +ARM_BE8(rev16 ip, ip) + strh ip, [r7, #2] + bne 2f + ldrh ip, [r7] +ARM_BE8(rev16 ip, ip) + bic ip, #0x20 + orr ip, ip, r0, lsr #16 +ARM_BE8(rev16 ip, ip) + strh ip, [r7] +2: cmp r4, r5 + ldrcc r7, [r4], #4 @ use branch for delay slot + bcc 1b + bx lr +#else + moveq r0, #0x400000 @ set bit 22, mov to mvn instruction + b 2f +1: ldr ip, [r7, r3] +#ifdef CONFIG_CPU_ENDIAN_BE8 + @ in BE8, we load data in BE, but instructions still in LE + bic ip, ip, #0xff000000 + tst ip, #0x000f0000 @ check the rotation field + orrne ip, ip, r6, lsl #24 @ mask in offset bits 31-24 + biceq ip, ip, #0x00004000 @ clear bit 22 + orreq ip, ip, r0, ror #8 @ mask in offset bits 7-0 +#else + bic ip, ip, #0x000000ff + tst ip, #0xf00 @ check the rotation field + orrne ip, ip, r6 @ mask in offset bits 31-24 + biceq ip, ip, #0x400000 @ clear bit 22 + orreq ip, ip, r0 @ mask in offset bits 7-0 +#endif + str ip, [r7, r3] +2: cmp r4, r5 + ldrcc r7, [r4], #4 @ use branch for delay slot + bcc 1b + ret lr +#endif +ENDPROC(__fixup_a_pv_table) + + .align +3: .long __pv_offset + +ENTRY(fixup_pv_table) + stmfd sp!, {r4 - r7, lr} + mov r3, #0 @ no offset + mov r4, r0 @ r0 = table start + add r5, r0, r1 @ r1 = table size + bl __fixup_a_pv_table + ldmfd sp!, {r4 - r7, pc} +ENDPROC(fixup_pv_table) + + .data + .align 2 + .globl __pv_phys_pfn_offset + .type __pv_phys_pfn_offset, %object +__pv_phys_pfn_offset: + .word 0 + .size __pv_phys_pfn_offset, . -__pv_phys_pfn_offset + + .globl __pv_offset + .type __pv_offset, %object +__pv_offset: + .quad 0 + .size __pv_offset, . -__pv_offset -- cgit v1.2.3-59-g8ed1b From 4b16421c3e955f440eb45546db6ce33d47f29c78 Mon Sep 17 00:00:00 2001 From: Ard Biesheuvel Date: Thu, 17 Sep 2020 21:29:36 +0300 Subject: ARM: p2v: factor out shared loop processing The ARM and Thumb2 versions of the p2v patching loop have some overlap at the end of the loop, so factor that out. As numeric labels are not required to be unique, and may therefore be ambiguous, use named local labels for the start and end of the loop instead. Acked-by: Nicolas Pitre Reviewed-by: Linus Walleij Signed-off-by: Ard Biesheuvel --- arch/arm/kernel/phys2virt.S | 24 +++++++++++------------- 1 file changed, 11 insertions(+), 13 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/kernel/phys2virt.S b/arch/arm/kernel/phys2virt.S index 7c17fbfeeedd..8fb1f7bcc720 100644 --- a/arch/arm/kernel/phys2virt.S +++ b/arch/arm/kernel/phys2virt.S @@ -68,7 +68,7 @@ __fixup_a_pv_table: #ifdef CONFIG_THUMB2_KERNEL moveq r0, #0x200000 @ set bit 21, mov to mvn instruction lsls r6, #24 - beq 2f + beq .Lnext clz r7, r6 lsr r6, #24 lsl r6, r7 @@ -77,8 +77,8 @@ __fixup_a_pv_table: orrcs r6, #0x0080 orr r6, r6, r7, lsl #12 orr r6, #0x4000 - b 2f -1: add r7, r3 + b .Lnext +.Lloop: add r7, r3 ldrh ip, [r7, #2] ARM_BE8(rev16 ip, ip) tst ip, #0x4000 @@ -87,21 +87,17 @@ ARM_BE8(rev16 ip, ip) orreq ip, r0 @ mask in offset bits 7-0 ARM_BE8(rev16 ip, ip) strh ip, [r7, #2] - bne 2f + bne .Lnext ldrh ip, [r7] ARM_BE8(rev16 ip, ip) bic ip, #0x20 orr ip, ip, r0, lsr #16 ARM_BE8(rev16 ip, ip) strh ip, [r7] -2: cmp r4, r5 - ldrcc r7, [r4], #4 @ use branch for delay slot - bcc 1b - bx lr #else moveq r0, #0x400000 @ set bit 22, mov to mvn instruction - b 2f -1: ldr ip, [r7, r3] + b .Lnext +.Lloop: ldr ip, [r7, r3] #ifdef CONFIG_CPU_ENDIAN_BE8 @ in BE8, we load data in BE, but instructions still in LE bic ip, ip, #0xff000000 @@ -117,11 +113,13 @@ ARM_BE8(rev16 ip, ip) orreq ip, ip, r0 @ mask in offset bits 7-0 #endif str ip, [r7, r3] -2: cmp r4, r5 +#endif + +.Lnext: + cmp r4, r5 ldrcc r7, [r4], #4 @ use branch for delay slot - bcc 1b + bcc .Lloop ret lr -#endif ENDPROC(__fixup_a_pv_table) .align -- cgit v1.2.3-59-g8ed1b From 7a94849e81b5c10e71f0a555300313c2789d9b0d Mon Sep 17 00:00:00 2001 From: Ard Biesheuvel Date: Thu, 17 Sep 2020 21:36:46 +0300 Subject: ARM: p2v: factor out BE8 handling The big and little endian versions of the ARM p2v patching routine only differ in the values of the constants, so factor those out into macros so that we only have one version of the logic sequence to maintain. Acked-by: Nicolas Pitre Reviewed-by: Linus Walleij Signed-off-by: Ard Biesheuvel --- arch/arm/kernel/phys2virt.S | 30 ++++++++++++++++-------------- 1 file changed, 16 insertions(+), 14 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/kernel/phys2virt.S b/arch/arm/kernel/phys2virt.S index 8fb1f7bcc720..5031e5a2e78b 100644 --- a/arch/arm/kernel/phys2virt.S +++ b/arch/arm/kernel/phys2virt.S @@ -95,23 +95,25 @@ ARM_BE8(rev16 ip, ip) ARM_BE8(rev16 ip, ip) strh ip, [r7] #else - moveq r0, #0x400000 @ set bit 22, mov to mvn instruction - b .Lnext -.Lloop: ldr ip, [r7, r3] #ifdef CONFIG_CPU_ENDIAN_BE8 - @ in BE8, we load data in BE, but instructions still in LE - bic ip, ip, #0xff000000 - tst ip, #0x000f0000 @ check the rotation field - orrne ip, ip, r6, lsl #24 @ mask in offset bits 31-24 - biceq ip, ip, #0x00004000 @ clear bit 22 - orreq ip, ip, r0, ror #8 @ mask in offset bits 7-0 +@ in BE8, we load data in BE, but instructions still in LE +#define PV_BIT22 0x00004000 +#define PV_IMM8_MASK 0xff000000 +#define PV_ROT_MASK 0x000f0000 #else - bic ip, ip, #0x000000ff - tst ip, #0xf00 @ check the rotation field - orrne ip, ip, r6 @ mask in offset bits 31-24 - biceq ip, ip, #0x400000 @ clear bit 22 - orreq ip, ip, r0 @ mask in offset bits 7-0 +#define PV_BIT22 0x00400000 +#define PV_IMM8_MASK 0x000000ff +#define PV_ROT_MASK 0xf00 #endif + + moveq r0, #0x400000 @ set bit 22, mov to mvn instruction + b .Lnext +.Lloop: ldr ip, [r7, r3] + bic ip, ip, #PV_IMM8_MASK + tst ip, #PV_ROT_MASK @ check the rotation field + orrne ip, ip, r6 ARM_BE8(, lsl #24) @ mask in offset bits 31-24 + biceq ip, ip, #PV_BIT22 @ clear bit 22 + orreq ip, ip, r0 ARM_BE8(, ror #8) @ mask in offset bits 7-0 (or bit 22) str ip, [r7, r3] #endif -- cgit v1.2.3-59-g8ed1b From 0869f3b9da38889faef2ccafcf675c713d4a3aa8 Mon Sep 17 00:00:00 2001 From: Ard Biesheuvel Date: Fri, 18 Sep 2020 10:00:24 +0300 Subject: ARM: p2v: drop redundant 'type' argument from __pv_stub We always pass the same value for 'type' so pull it into the __pv_stub macro itself. Acked-by: Nicolas Pitre Reviewed-by: Linus Walleij Signed-off-by: Ard Biesheuvel --- arch/arm/include/asm/memory.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h index 99035b5891ef..eb3c8e6e960a 100644 --- a/arch/arm/include/asm/memory.h +++ b/arch/arm/include/asm/memory.h @@ -183,14 +183,14 @@ extern const void *__pv_table_begin, *__pv_table_end; #define PHYS_OFFSET ((phys_addr_t)__pv_phys_pfn_offset << PAGE_SHIFT) #define PHYS_PFN_OFFSET (__pv_phys_pfn_offset) -#define __pv_stub(from,to,instr,type) \ +#define __pv_stub(from,to,instr) \ __asm__("@ __pv_stub\n" \ "1: " instr " %0, %1, %2\n" \ " .pushsection .pv_table,\"a\"\n" \ " .long 1b\n" \ " .popsection\n" \ : "=r" (to) \ - : "r" (from), "I" (type)) + : "r" (from), "I" (__PV_BITS_31_24)) #define __pv_stub_mov_hi(t) \ __asm__ volatile("@ __pv_stub_mov\n" \ @@ -217,7 +217,7 @@ static inline phys_addr_t __virt_to_phys_nodebug(unsigned long x) phys_addr_t t; if (sizeof(phys_addr_t) == 4) { - __pv_stub(x, t, "add", __PV_BITS_31_24); + __pv_stub(x, t, "add"); } else { __pv_stub_mov_hi(t); __pv_add_carry_stub(x, t); @@ -235,7 +235,7 @@ static inline unsigned long __phys_to_virt(phys_addr_t x) * assembler expression receives 32 bit argument * in place where 'r' 32 bit operand is expected. */ - __pv_stub((unsigned long) x, t, "sub", __PV_BITS_31_24); + __pv_stub((unsigned long) x, t, "sub"); return t; } -- cgit v1.2.3-59-g8ed1b From 2730e8eaa4f2baccc03296e0c5ee109c0673fe5f Mon Sep 17 00:00:00 2001 From: Ard Biesheuvel Date: Sun, 20 Sep 2020 18:23:35 +0200 Subject: ARM: p2v: use relative references in patch site arrays Free up a register in the p2v patching code by switching to relative references, which don't require keeping the phys-to-virt displacement live in a register. Acked-by: Nicolas Pitre Reviewed-by: Linus Walleij Signed-off-by: Ard Biesheuvel --- arch/arm/include/asm/memory.h | 6 +++--- arch/arm/kernel/phys2virt.S | 18 +++++++----------- 2 files changed, 10 insertions(+), 14 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h index eb3c8e6e960a..4121662dea5a 100644 --- a/arch/arm/include/asm/memory.h +++ b/arch/arm/include/asm/memory.h @@ -187,7 +187,7 @@ extern const void *__pv_table_begin, *__pv_table_end; __asm__("@ __pv_stub\n" \ "1: " instr " %0, %1, %2\n" \ " .pushsection .pv_table,\"a\"\n" \ - " .long 1b\n" \ + " .long 1b - .\n" \ " .popsection\n" \ : "=r" (to) \ : "r" (from), "I" (__PV_BITS_31_24)) @@ -196,7 +196,7 @@ extern const void *__pv_table_begin, *__pv_table_end; __asm__ volatile("@ __pv_stub_mov\n" \ "1: mov %R0, %1\n" \ " .pushsection .pv_table,\"a\"\n" \ - " .long 1b\n" \ + " .long 1b - .\n" \ " .popsection\n" \ : "=r" (t) \ : "I" (__PV_BITS_7_0)) @@ -206,7 +206,7 @@ extern const void *__pv_table_begin, *__pv_table_end; "1: adds %Q0, %1, %2\n" \ " adc %R0, %R0, #0\n" \ " .pushsection .pv_table,\"a\"\n" \ - " .long 1b\n" \ + " .long 1b - .\n" \ " .popsection\n" \ : "+r" (y) \ : "r" (x), "I" (__PV_BITS_31_24) \ diff --git a/arch/arm/kernel/phys2virt.S b/arch/arm/kernel/phys2virt.S index 5031e5a2e78b..8e4be15e1559 100644 --- a/arch/arm/kernel/phys2virt.S +++ b/arch/arm/kernel/phys2virt.S @@ -58,9 +58,7 @@ ENDPROC(__fixup_pv_table) .text __fixup_a_pv_table: - adr r0, 3f - ldr r6, [r0] - add r6, r6, r3 + adr_l r6, __pv_offset ldr r0, [r6, #HIGH_OFFSET] @ pv_offset high word ldr r6, [r6, #LOW_OFFSET] @ pv_offset low word mov r6, r6, lsr #24 @@ -78,7 +76,8 @@ __fixup_a_pv_table: orr r6, r6, r7, lsl #12 orr r6, #0x4000 b .Lnext -.Lloop: add r7, r3 +.Lloop: add r7, r4 + adds r4, #4 ldrh ip, [r7, #2] ARM_BE8(rev16 ip, ip) tst ip, #0x4000 @@ -108,28 +107,25 @@ ARM_BE8(rev16 ip, ip) moveq r0, #0x400000 @ set bit 22, mov to mvn instruction b .Lnext -.Lloop: ldr ip, [r7, r3] +.Lloop: ldr ip, [r7, r4] bic ip, ip, #PV_IMM8_MASK tst ip, #PV_ROT_MASK @ check the rotation field orrne ip, ip, r6 ARM_BE8(, lsl #24) @ mask in offset bits 31-24 biceq ip, ip, #PV_BIT22 @ clear bit 22 orreq ip, ip, r0 ARM_BE8(, ror #8) @ mask in offset bits 7-0 (or bit 22) - str ip, [r7, r3] + str ip, [r7, r4] + add r4, r4, #4 #endif .Lnext: cmp r4, r5 - ldrcc r7, [r4], #4 @ use branch for delay slot + ldrcc r7, [r4] @ use branch for delay slot bcc .Lloop ret lr ENDPROC(__fixup_a_pv_table) - .align -3: .long __pv_offset - ENTRY(fixup_pv_table) stmfd sp!, {r4 - r7, lr} - mov r3, #0 @ no offset mov r4, r0 @ r0 = table start add r5, r0, r1 @ r1 = table size bl __fixup_a_pv_table -- cgit v1.2.3-59-g8ed1b From 0e3db6c9d7f6fd0ee263325027e8d3fdac5a4c9e Mon Sep 17 00:00:00 2001 From: Ard Biesheuvel Date: Sun, 20 Sep 2020 19:19:32 +0200 Subject: ARM: p2v: simplify __fixup_pv_table() Declutter the code in __fixup_pv_table() by using the new adr_l/str_l macros to take PC relative references to external symbols, and by using the value of PHYS_OFFSET passed in r8 to calculate the p2v offset. Acked-by: Nicolas Pitre Reviewed-by: Linus Walleij Signed-off-by: Ard Biesheuvel --- arch/arm/kernel/phys2virt.S | 34 ++++++++++++++-------------------- 1 file changed, 14 insertions(+), 20 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/kernel/phys2virt.S b/arch/arm/kernel/phys2virt.S index 8e4be15e1559..be8fb0d89877 100644 --- a/arch/arm/kernel/phys2virt.S +++ b/arch/arm/kernel/phys2virt.S @@ -29,33 +29,27 @@ */ __HEAD ENTRY(__fixup_pv_table) - adr r0, 1f - ldmia r0, {r3-r7} - mvn ip, #0 - subs r3, r0, r3 @ PHYS_OFFSET - PAGE_OFFSET - add r4, r4, r3 @ adjust table start address - add r5, r5, r3 @ adjust table end address - add r6, r6, r3 @ adjust __pv_phys_pfn_offset address - add r7, r7, r3 @ adjust __pv_offset address mov r0, r8, lsr #PAGE_SHIFT @ convert to PFN - str r0, [r6] @ save computed PHYS_OFFSET to __pv_phys_pfn_offset - strcc ip, [r7, #HIGH_OFFSET] @ save to __pv_offset high bits - mov r6, r3, lsr #24 @ constant for add/sub instructions - teq r3, r6, lsl #24 @ must be 16MiB aligned + str_l r0, __pv_phys_pfn_offset, r3 + + adr_l r0, __pv_offset + subs r3, r8, #PAGE_OFFSET @ PHYS_OFFSET - PAGE_OFFSET + mvn ip, #0 + strcc ip, [r0, #HIGH_OFFSET] @ save to __pv_offset high bits + str r3, [r0, #LOW_OFFSET] @ save to __pv_offset low bits + + mov r0, r3, lsr #24 @ constant for add/sub instructions + teq r3, r0, lsl #24 @ must be 16MiB aligned bne 0f - str r3, [r7, #LOW_OFFSET] @ save to __pv_offset low bits + + adr_l r4, __pv_table_begin + adr_l r5, __pv_table_end b __fixup_a_pv_table + 0: mov r0, r0 @ deadloop on error b 0b ENDPROC(__fixup_pv_table) - .align -1: .long . - .long __pv_table_begin - .long __pv_table_end -2: .long __pv_phys_pfn_offset - .long __pv_offset - .text __fixup_a_pv_table: adr_l r6, __pv_offset -- cgit v1.2.3-59-g8ed1b From e8e00f5afb087912fb3edb225ee373aa6499bb79 Mon Sep 17 00:00:00 2001 From: Ard Biesheuvel Date: Sun, 20 Sep 2020 23:02:25 +0200 Subject: ARM: p2v: switch to MOVW for Thumb2 and ARM/LPAE In preparation for reducing the phys-to-virt minimum relative alignment from 16 MiB to 2 MiB, switch to patchable sequences involving MOVW instructions that can more easily be manipulated to carry a 12-bit immediate. Note that the non-LPAE ARM sequence is not updated: MOVW may not be supported on non-LPAE platforms, and the sequence itself can be updated more easily to apply the 12 bits of displacement. For Thumb2, which has many more versions of opcodes, switch to a sequence that can be patched by the same patching code for both versions. Note that the Thumb2 opcodes for MOVW and MVN are unambiguous, and have no rotation bits in their immediate fields, so there is no need to use placeholder constants in the asm blocks. While at it, drop the 'volatile' qualifiers from the asm blocks: the code does not have any side effects that are invisible to the compiler, so it is free to omit these sequences if the outputs are not used. Suggested-by: Russell King Acked-by: Nicolas Pitre Reviewed-by: Linus Walleij Signed-off-by: Ard Biesheuvel --- arch/arm/include/asm/memory.h | 44 +++++++++---- arch/arm/kernel/phys2virt.S | 147 +++++++++++++++++++++++++++++++++--------- 2 files changed, 148 insertions(+), 43 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h index 4121662dea5a..ccf55cef6ab9 100644 --- a/arch/arm/include/asm/memory.h +++ b/arch/arm/include/asm/memory.h @@ -183,6 +183,7 @@ extern const void *__pv_table_begin, *__pv_table_end; #define PHYS_OFFSET ((phys_addr_t)__pv_phys_pfn_offset << PAGE_SHIFT) #define PHYS_PFN_OFFSET (__pv_phys_pfn_offset) +#ifndef CONFIG_THUMB2_KERNEL #define __pv_stub(from,to,instr) \ __asm__("@ __pv_stub\n" \ "1: " instr " %0, %1, %2\n" \ @@ -192,25 +193,45 @@ extern const void *__pv_table_begin, *__pv_table_end; : "=r" (to) \ : "r" (from), "I" (__PV_BITS_31_24)) -#define __pv_stub_mov_hi(t) \ - __asm__ volatile("@ __pv_stub_mov\n" \ - "1: mov %R0, %1\n" \ +#define __pv_add_carry_stub(x, y) \ + __asm__("@ __pv_add_carry_stub\n" \ + "0: movw %R0, #0\n" \ + " adds %Q0, %1, %R0, lsl #24\n" \ + "1: mov %R0, %2\n" \ + " adc %R0, %R0, #0\n" \ " .pushsection .pv_table,\"a\"\n" \ - " .long 1b - .\n" \ + " .long 0b - ., 1b - .\n" \ " .popsection\n" \ - : "=r" (t) \ - : "I" (__PV_BITS_7_0)) + : "=&r" (y) \ + : "r" (x), "I" (__PV_BITS_7_0) \ + : "cc") + +#else +#define __pv_stub(from,to,instr) \ + __asm__("@ __pv_stub\n" \ + "0: movw %0, #0\n" \ + " lsl %0, #24\n" \ + " " instr " %0, %1, %0\n" \ + " .pushsection .pv_table,\"a\"\n" \ + " .long 0b - .\n" \ + " .popsection\n" \ + : "=&r" (to) \ + : "r" (from)) #define __pv_add_carry_stub(x, y) \ - __asm__ volatile("@ __pv_add_carry_stub\n" \ - "1: adds %Q0, %1, %2\n" \ + __asm__("@ __pv_add_carry_stub\n" \ + "0: movw %R0, #0\n" \ + " lsls %R0, #24\n" \ + " adds %Q0, %1, %R0\n" \ + "1: mvn %R0, #0\n" \ " adc %R0, %R0, #0\n" \ " .pushsection .pv_table,\"a\"\n" \ - " .long 1b - .\n" \ + " .long 0b - ., 1b - .\n" \ " .popsection\n" \ - : "+r" (y) \ - : "r" (x), "I" (__PV_BITS_31_24) \ + : "=&r" (y) \ + : "r" (x) \ : "cc") +#endif static inline phys_addr_t __virt_to_phys_nodebug(unsigned long x) { @@ -219,7 +240,6 @@ static inline phys_addr_t __virt_to_phys_nodebug(unsigned long x) if (sizeof(phys_addr_t) == 4) { __pv_stub(x, t, "add"); } else { - __pv_stub_mov_hi(t); __pv_add_carry_stub(x, t); } return t; diff --git a/arch/arm/kernel/phys2virt.S b/arch/arm/kernel/phys2virt.S index be8fb0d89877..a4e364689663 100644 --- a/arch/arm/kernel/phys2virt.S +++ b/arch/arm/kernel/phys2virt.S @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (C) 1994-2002 Russell King - * Copyright (c) 2003 ARM Limited + * Copyright (c) 2003, 2020 ARM Limited * All Rights Reserved */ @@ -58,55 +58,140 @@ __fixup_a_pv_table: mov r6, r6, lsr #24 cmn r0, #1 #ifdef CONFIG_THUMB2_KERNEL + @ + @ The Thumb-2 versions of the patchable sequences are + @ + @ phys-to-virt: movw , #offset<31:24> + @ lsl , #24 + @ sub , , + @ + @ virt-to-phys (non-LPAE): movw , #offset<31:24> + @ lsl , #24 + @ add , , + @ + @ virt-to-phys (LPAE): movw , #offset<31:24> + @ lsl , #24 + @ adds , , + @ mov , #offset<39:32> + @ adc , , #0 + @ + @ In the non-LPAE case, all patchable instructions are MOVW + @ instructions, where we need to patch in the offset into the + @ second halfword of the opcode (the 16-bit immediate is encoded + @ as imm4:i:imm3:imm8) + @ + @ 15 11 10 9 4 3 0 15 14 12 11 8 7 0 + @ +-----------+---+-------------+------++---+------+----+------+ + @ MOVW | 1 1 1 1 0 | i | 1 0 0 1 0 0 | imm4 || 0 | imm3 | Rd | imm8 | + @ +-----------+---+-------------+------++---+------+----+------+ + @ + @ In the LPAE case, we also need to patch in the high word of the + @ offset into the immediate field of the MOV instruction, or patch it + @ to a MVN instruction if the offset is negative. In this case, we + @ need to inspect the first halfword of the opcode, to check whether + @ it is MOVW or MOV/MVN, and to perform the MOV to MVN patching if + @ needed. The encoding of the immediate is rather complex for values + @ of i:imm3 != 0b0000, but fortunately, we never need more than 8 lower + @ order bits, which can be patched into imm8 directly (and i:imm3 + @ cleared) + @ + @ 15 11 10 9 5 0 15 14 12 11 8 7 0 + @ +-----------+---+---------------------++---+------+----+------+ + @ MOV | 1 1 1 1 0 | i | 0 0 0 1 0 0 1 1 1 1 || 0 | imm3 | Rd | imm8 | + @ MVN | 1 1 1 1 0 | i | 0 0 0 1 1 0 1 1 1 1 || 0 | imm3 | Rd | imm8 | + @ +-----------+---+---------------------++---+------+----+------+ + @ moveq r0, #0x200000 @ set bit 21, mov to mvn instruction - lsls r6, #24 - beq .Lnext - clz r7, r6 - lsr r6, #24 - lsl r6, r7 - bic r6, #0x0080 - lsrs r7, #1 - orrcs r6, #0x0080 - orr r6, r6, r7, lsl #12 - orr r6, #0x4000 b .Lnext .Lloop: add r7, r4 - adds r4, #4 - ldrh ip, [r7, #2] -ARM_BE8(rev16 ip, ip) - tst ip, #0x4000 - and ip, #0x8f00 - orrne ip, r6 @ mask in offset bits 31-24 - orreq ip, r0 @ mask in offset bits 7-0 -ARM_BE8(rev16 ip, ip) - strh ip, [r7, #2] - bne .Lnext + adds r4, #4 @ clears Z flag +#ifdef CONFIG_ARM_LPAE ldrh ip, [r7] ARM_BE8(rev16 ip, ip) - bic ip, #0x20 - orr ip, ip, r0, lsr #16 + tst ip, #0x200 @ MOVW has bit 9 set, MVN has it clear + bne 0f @ skip to MOVW handling (Z flag is clear) + bic ip, #0x20 @ clear bit 5 (MVN -> MOV) + orr ip, ip, r0, lsr #16 @ MOV -> MVN if offset < 0 ARM_BE8(rev16 ip, ip) strh ip, [r7] + @ Z flag is set +0: +#endif + ldrh ip, [r7, #2] +ARM_BE8(rev16 ip, ip) + and ip, #0xf00 @ clear everything except Rd field + orreq ip, r0 @ Z flag set -> MOV/MVN -> patch in high bits + orrne ip, r6 @ Z flag clear -> MOVW -> patch in low bits +ARM_BE8(rev16 ip, ip) + strh ip, [r7, #2] #else #ifdef CONFIG_CPU_ENDIAN_BE8 @ in BE8, we load data in BE, but instructions still in LE -#define PV_BIT22 0x00004000 +#define PV_BIT24 0x00000001 #define PV_IMM8_MASK 0xff000000 -#define PV_ROT_MASK 0x000f0000 #else -#define PV_BIT22 0x00400000 +#define PV_BIT24 0x01000000 #define PV_IMM8_MASK 0x000000ff -#define PV_ROT_MASK 0xf00 #endif + @ + @ The ARM versions of the patchable sequences are + @ + @ phys-to-virt: sub , , #offset<31:24>, lsl #24 + @ + @ virt-to-phys (non-LPAE): add , , #offset<31:24>, lsl #24 + @ + @ virt-to-phys (LPAE): movw , #offset<31:24> + @ adds , , , lsl #24 + @ mov , #offset<39:32> + @ adc , , #0 + @ + @ In the non-LPAE case, all patchable instructions are ADD or SUB + @ instructions, where we need to patch in the offset into the + @ immediate field of the opcode, which is emitted with the correct + @ rotation value. (The effective value of the immediate is imm12<7:0> + @ rotated right by [2 * imm12<11:8>] bits) + @ + @ 31 28 27 23 22 20 19 16 15 12 11 0 + @ +------+-----------------+------+------+-------+ + @ ADD | cond | 0 0 1 0 1 0 0 0 | Rn | Rd | imm12 | + @ SUB | cond | 0 0 1 0 0 1 0 0 | Rn | Rd | imm12 | + @ MOV | cond | 0 0 1 1 1 0 1 0 | Rn | Rd | imm12 | + @ MVN | cond | 0 0 1 1 1 1 1 0 | Rn | Rd | imm12 | + @ +------+-----------------+------+------+-------+ + @ + @ In the LPAE case, we use a MOVW instruction to carry the low offset + @ word, and patch in the high word of the offset into the immediate + @ field of the subsequent MOV instruction, or patch it to a MVN + @ instruction if the offset is negative. We can distinguish MOVW + @ instructions based on bits 23:22 of the opcode, and ADD/SUB can be + @ distinguished from MOV/MVN (all using the encodings above) using + @ bit 24. + @ + @ 31 28 27 23 22 20 19 16 15 12 11 0 + @ +------+-----------------+------+------+-------+ + @ MOVW | cond | 0 0 1 1 0 0 0 0 | imm4 | Rd | imm12 | + @ +------+-----------------+------+------+-------+ + @ moveq r0, #0x400000 @ set bit 22, mov to mvn instruction b .Lnext .Lloop: ldr ip, [r7, r4] +#ifdef CONFIG_ARM_LPAE + tst ip, #PV_BIT24 @ ADD/SUB have bit 24 clear + beq 1f +ARM_BE8(rev ip, ip) + tst ip, #0xc00000 @ MOVW has bits 23:22 clear + bic ip, ip, #0x400000 @ clear bit 22 + bfc ip, #0, #12 @ clear imm12 field of MOV[W] instruction + orreq ip, ip, r6 @ MOVW -> mask in offset bits 31-24 + orrne ip, ip, r0 @ MOV -> mask in offset bits 7-0 (or bit 22) +ARM_BE8(rev ip, ip) + b 2f +1: +#endif bic ip, ip, #PV_IMM8_MASK - tst ip, #PV_ROT_MASK @ check the rotation field - orrne ip, ip, r6 ARM_BE8(, lsl #24) @ mask in offset bits 31-24 - biceq ip, ip, #PV_BIT22 @ clear bit 22 - orreq ip, ip, r0 ARM_BE8(, ror #8) @ mask in offset bits 7-0 (or bit 22) + orr ip, ip, r6 ARM_BE8(, lsl #24) @ mask in offset bits 31-24 +2: str ip, [r7, r4] add r4, r4, #4 #endif -- cgit v1.2.3-59-g8ed1b From 9443076e4330a14ae2c6114307668b98a8293b77 Mon Sep 17 00:00:00 2001 From: Ard Biesheuvel Date: Fri, 18 Sep 2020 11:55:42 +0300 Subject: ARM: p2v: reduce p2v alignment requirement to 2 MiB The ARM kernel's linear map starts at PAGE_OFFSET, which maps to a physical address (PHYS_OFFSET) that is platform specific, and is discovered at boot. Since we don't want to slow down translations between physical and virtual addresses by keeping the offset in a variable in memory, we implement this by patching the code performing the translation, and putting the offset between PAGE_OFFSET and the start of physical RAM directly into the instruction opcodes. As we only patch up to 8 bits of offset, yielding 4 GiB >> 8 == 16 MiB of granularity, we have to round up PHYS_OFFSET to the next multiple if the start of physical RAM is not a multiple of 16 MiB. This wastes some physical RAM, since the memory that was skipped will now live below PAGE_OFFSET, making it inaccessible to the kernel. We can improve this by changing the patchable sequences and the patching logic to carry more bits of offset: 11 bits gives us 4 GiB >> 11 == 2 MiB of granularity, and so we will never waste more than that amount by rounding up the physical start of DRAM to the next multiple of 2 MiB. (Note that 2 MiB granularity guarantees that the linear mapping can be created efficiently, whereas less than 2 MiB may result in the linear mapping needing another level of page tables) This helps Zhen Lei's scenario, where the start of DRAM is known to be occupied. It also helps EFI boot, which relies on the firmware's page allocator to allocate space for the decompressed kernel as low as possible. And if the KASLR patches ever land for 32-bit, it will give us 3 more bits of randomization of the placement of the kernel inside the linear region. For the ARM code path, it simply comes down to using two add/sub instructions instead of one for the carryless version, and patching each of them with the correct immediate depending on the rotation field. For the LPAE calculation, which has to deal with a carry, it patches the MOVW instruction with up to 12 bits of offset (but we only need 11 bits anyway) For the Thumb2 code path, patching more than 11 bits of displacement would be somewhat cumbersome, but the 11 bits we need fit nicely into the second word of the u16[2] opcode, so we simply update the immediate assignment and the left shift to create an addend of the right magnitude. Suggested-by: Zhen Lei Acked-by: Nicolas Pitre Acked-by: Linus Walleij Signed-off-by: Ard Biesheuvel --- arch/arm/Kconfig | 2 +- arch/arm/include/asm/memory.h | 13 ++++++++----- arch/arm/kernel/phys2virt.S | 40 ++++++++++++++++++++++++++-------------- 3 files changed, 35 insertions(+), 20 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index fe2f17eb2b50..d8d62b8e72e4 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -243,7 +243,7 @@ config ARM_PATCH_PHYS_VIRT kernel in system memory. This can only be used with non-XIP MMU kernels where the base - of physical memory is at a 16MB boundary. + of physical memory is at a 2 MiB boundary. Only disable this option if you know that you do not require this feature (eg, building a kernel for a single machine) and diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h index ccf55cef6ab9..2611be35f26b 100644 --- a/arch/arm/include/asm/memory.h +++ b/arch/arm/include/asm/memory.h @@ -173,6 +173,7 @@ extern unsigned long vectors_base; * so that all we need to do is modify the 8-bit constant field. */ #define __PV_BITS_31_24 0x81000000 +#define __PV_BITS_23_16 0x810000 #define __PV_BITS_7_0 0x81 extern unsigned long __pv_phys_pfn_offset; @@ -187,16 +188,18 @@ extern const void *__pv_table_begin, *__pv_table_end; #define __pv_stub(from,to,instr) \ __asm__("@ __pv_stub\n" \ "1: " instr " %0, %1, %2\n" \ + "2: " instr " %0, %0, %3\n" \ " .pushsection .pv_table,\"a\"\n" \ - " .long 1b - .\n" \ + " .long 1b - ., 2b - .\n" \ " .popsection\n" \ : "=r" (to) \ - : "r" (from), "I" (__PV_BITS_31_24)) + : "r" (from), "I" (__PV_BITS_31_24), \ + "I"(__PV_BITS_23_16)) #define __pv_add_carry_stub(x, y) \ __asm__("@ __pv_add_carry_stub\n" \ "0: movw %R0, #0\n" \ - " adds %Q0, %1, %R0, lsl #24\n" \ + " adds %Q0, %1, %R0, lsl #20\n" \ "1: mov %R0, %2\n" \ " adc %R0, %R0, #0\n" \ " .pushsection .pv_table,\"a\"\n" \ @@ -210,7 +213,7 @@ extern const void *__pv_table_begin, *__pv_table_end; #define __pv_stub(from,to,instr) \ __asm__("@ __pv_stub\n" \ "0: movw %0, #0\n" \ - " lsl %0, #24\n" \ + " lsl %0, #21\n" \ " " instr " %0, %1, %0\n" \ " .pushsection .pv_table,\"a\"\n" \ " .long 0b - .\n" \ @@ -221,7 +224,7 @@ extern const void *__pv_table_begin, *__pv_table_end; #define __pv_add_carry_stub(x, y) \ __asm__("@ __pv_add_carry_stub\n" \ "0: movw %R0, #0\n" \ - " lsls %R0, #24\n" \ + " lsls %R0, #21\n" \ " adds %Q0, %1, %R0\n" \ "1: mvn %R0, #0\n" \ " adc %R0, %R0, #0\n" \ diff --git a/arch/arm/kernel/phys2virt.S b/arch/arm/kernel/phys2virt.S index a4e364689663..fb53db78fe78 100644 --- a/arch/arm/kernel/phys2virt.S +++ b/arch/arm/kernel/phys2virt.S @@ -21,7 +21,7 @@ /* * __fixup_pv_table - patch the stub instructions with the delta between * PHYS_OFFSET and PAGE_OFFSET, which is assumed to be - * 16MiB aligned. + * 2 MiB aligned. * * Called from head.S, which expects the following registers to be preserved: * r1 = machine no, r2 = atags or dtb, @@ -38,8 +38,8 @@ ENTRY(__fixup_pv_table) strcc ip, [r0, #HIGH_OFFSET] @ save to __pv_offset high bits str r3, [r0, #LOW_OFFSET] @ save to __pv_offset low bits - mov r0, r3, lsr #24 @ constant for add/sub instructions - teq r3, r0, lsl #24 @ must be 16MiB aligned + mov r0, r3, lsr #21 @ constant for add/sub instructions + teq r3, r0, lsl #21 @ must be 2 MiB aligned bne 0f adr_l r4, __pv_table_begin @@ -55,22 +55,21 @@ __fixup_a_pv_table: adr_l r6, __pv_offset ldr r0, [r6, #HIGH_OFFSET] @ pv_offset high word ldr r6, [r6, #LOW_OFFSET] @ pv_offset low word - mov r6, r6, lsr #24 cmn r0, #1 #ifdef CONFIG_THUMB2_KERNEL @ @ The Thumb-2 versions of the patchable sequences are @ - @ phys-to-virt: movw , #offset<31:24> - @ lsl , #24 + @ phys-to-virt: movw , #offset<31:21> + @ lsl , #21 @ sub , , @ - @ virt-to-phys (non-LPAE): movw , #offset<31:24> - @ lsl , #24 + @ virt-to-phys (non-LPAE): movw , #offset<31:21> + @ lsl , #21 @ add , , @ - @ virt-to-phys (LPAE): movw , #offset<31:24> - @ lsl , #24 + @ virt-to-phys (LPAE): movw , #offset<31:21> + @ lsl , #21 @ adds , , @ mov , #offset<39:32> @ adc , , #0 @@ -102,6 +101,9 @@ __fixup_a_pv_table: @ +-----------+---+---------------------++---+------+----+------+ @ moveq r0, #0x200000 @ set bit 21, mov to mvn instruction + lsrs r3, r6, #29 @ isolate top 3 bits of displacement + ubfx r6, r6, #21, #8 @ put bits 28:21 into the MOVW imm8 field + bfi r6, r3, #12, #3 @ put bits 31:29 into the MOVW imm3 field b .Lnext .Lloop: add r7, r4 adds r4, #4 @ clears Z flag @@ -129,20 +131,24 @@ ARM_BE8(rev16 ip, ip) @ in BE8, we load data in BE, but instructions still in LE #define PV_BIT24 0x00000001 #define PV_IMM8_MASK 0xff000000 +#define PV_IMMR_MSB 0x00080000 #else #define PV_BIT24 0x01000000 #define PV_IMM8_MASK 0x000000ff +#define PV_IMMR_MSB 0x00000800 #endif @ @ The ARM versions of the patchable sequences are @ @ phys-to-virt: sub , , #offset<31:24>, lsl #24 + @ sub , , #offset<23:16>, lsl #16 @ @ virt-to-phys (non-LPAE): add , , #offset<31:24>, lsl #24 + @ add , , #offset<23:16>, lsl #16 @ - @ virt-to-phys (LPAE): movw , #offset<31:24> - @ adds , , , lsl #24 + @ virt-to-phys (LPAE): movw , #offset<31:20> + @ adds , , , lsl #20 @ mov , #offset<39:32> @ adc , , #0 @ @@ -174,6 +180,9 @@ ARM_BE8(rev16 ip, ip) @ +------+-----------------+------+------+-------+ @ moveq r0, #0x400000 @ set bit 22, mov to mvn instruction + mov r3, r6, lsr #16 @ put offset bits 31-16 into r3 + mov r6, r6, lsr #24 @ put offset bits 31-24 into r6 + and r3, r3, #0xf0 @ only keep offset bits 23-20 in r3 b .Lnext .Lloop: ldr ip, [r7, r4] #ifdef CONFIG_ARM_LPAE @@ -183,14 +192,17 @@ ARM_BE8(rev ip, ip) tst ip, #0xc00000 @ MOVW has bits 23:22 clear bic ip, ip, #0x400000 @ clear bit 22 bfc ip, #0, #12 @ clear imm12 field of MOV[W] instruction - orreq ip, ip, r6 @ MOVW -> mask in offset bits 31-24 + orreq ip, ip, r6, lsl #4 @ MOVW -> mask in offset bits 31-24 + orreq ip, ip, r3, lsr #4 @ MOVW -> mask in offset bits 23-20 orrne ip, ip, r0 @ MOV -> mask in offset bits 7-0 (or bit 22) ARM_BE8(rev ip, ip) b 2f 1: #endif + tst ip, #PV_IMMR_MSB @ rotation value >= 16 ? bic ip, ip, #PV_IMM8_MASK - orr ip, ip, r6 ARM_BE8(, lsl #24) @ mask in offset bits 31-24 + orreq ip, ip, r6 ARM_BE8(, lsl #24) @ mask in offset bits 31-24 + orrne ip, ip, r3 ARM_BE8(, lsl #24) @ mask in offset bits 23-20 2: str ip, [r7, r4] add r4, r4, #4 -- cgit v1.2.3-59-g8ed1b From 67e3f828bd4bf5e4eb4214dc4eb227d8f1c8a877 Mon Sep 17 00:00:00 2001 From: Ard Biesheuvel Date: Mon, 14 Sep 2020 12:28:01 +0300 Subject: ARM: efistub: replace adrl pseudo-op with adr_l macro invocation The ARM 'adrl' pseudo instruction is a bit problematic, as it does not exist in Thumb mode, and it is not implemented by Clang either. Since the Thumb variant has a slightly bigger range, it is sometimes necessary to emit the 'adrl' variant in ARM mode where Thumb mode can use adr just fine. However, that still leaves the Clang issue, which does not appear to be supporting this any time soon. So let's switch to the adr_l macro, which works for both ARM and Thumb, and has unlimited range. Reviewed-by: Nicolas Pitre Signed-off-by: Ard Biesheuvel --- arch/arm/boot/compressed/head.S | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S index 2e04ec5b5446..5b591dacbaaf 100644 --- a/arch/arm/boot/compressed/head.S +++ b/arch/arm/boot/compressed/head.S @@ -1440,8 +1440,7 @@ ENTRY(efi_enter_kernel) mov r4, r0 @ preserve image base mov r8, r1 @ preserve DT pointer - ARM( adrl r0, call_cache_fn ) - THUMB( adr r0, call_cache_fn ) + adr_l r0, call_cache_fn adr r1, 0f @ clean the region of code we bl cache_clean_flush @ may run with the MMU off -- cgit v1.2.3-59-g8ed1b From 62c4a2e202b18e1d7176875b7e7af240f340596b Mon Sep 17 00:00:00 2001 From: Ard Biesheuvel Date: Mon, 14 Sep 2020 11:25:06 +0300 Subject: ARM: head-common.S: use PC-relative insn sequence for __proc_info Replace the open coded PC relative offset calculations with a pair of adr_l invocations. This removes some open coded arithmetic involving virtual addresses, avoids literal pools on v7+, and slightly reduces the footprint of the code. Reviewed-by: Nicolas Pitre Signed-off-by: Ard Biesheuvel --- arch/arm/kernel/head-common.S | 22 ++++++---------------- 1 file changed, 6 insertions(+), 16 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/kernel/head-common.S b/arch/arm/kernel/head-common.S index 4a3982812a40..9a5ab6c19568 100644 --- a/arch/arm/kernel/head-common.S +++ b/arch/arm/kernel/head-common.S @@ -170,11 +170,12 @@ ENDPROC(lookup_processor_type) * r9 = cpuid (preserved) */ __lookup_processor_type: - adr r3, __lookup_processor_type_data - ldmia r3, {r4 - r6} - sub r3, r3, r4 @ get offset between virt&phys - add r5, r5, r3 @ convert virt addresses to - add r6, r6, r3 @ physical address space + /* + * Look in for information about the __proc_info + * structure. + */ + adr_l r5, __proc_info_begin + adr_l r6, __proc_info_end 1: ldmia r5, {r3, r4} @ value, mask and r4, r4, r9 @ mask wanted bits teq r3, r4 @@ -186,17 +187,6 @@ __lookup_processor_type: 2: ret lr ENDPROC(__lookup_processor_type) -/* - * Look in for information about the __proc_info structure. - */ - .align 2 - .type __lookup_processor_type_data, %object -__lookup_processor_type_data: - .long . - .long __proc_info_begin - .long __proc_info_end - .size __lookup_processor_type_data, . - __lookup_processor_type_data - __error_lpae: #ifdef CONFIG_DEBUG_LL adr r0, str_lpae -- cgit v1.2.3-59-g8ed1b From 172c34c9ff0144c3e1d96a9b54d6fecfe5d17c3c Mon Sep 17 00:00:00 2001 From: Ard Biesheuvel Date: Mon, 14 Sep 2020 11:25:16 +0300 Subject: ARM: head-common.S: use PC-relative insn sequence for idmap creation Replace the open coded PC relative offset calculations involving __turn_mmu_on and __turn_mmu_on_end with a pair of adr_l invocations. This removes some open coded arithmetic involving virtual addresses, avoids literal pools on v7+, and slightly reduces the footprint of the code. Reviewed-by: Nicolas Pitre Signed-off-by: Ard Biesheuvel --- arch/arm/kernel/head.S | 12 ++---------- 1 file changed, 2 insertions(+), 10 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S index 7e3f36809011..f5a636fee9d0 100644 --- a/arch/arm/kernel/head.S +++ b/arch/arm/kernel/head.S @@ -224,11 +224,8 @@ __create_page_tables: * Create identity mapping to cater for __enable_mmu. * This identity mapping will be removed by paging_init(). */ - adr r0, __turn_mmu_on_loc - ldmia r0, {r3, r5, r6} - sub r0, r0, r3 @ virt->phys offset - add r5, r5, r0 @ phys __turn_mmu_on - add r6, r6, r0 @ phys __turn_mmu_on_end + adr_l r5, __turn_mmu_on @ _pa(__turn_mmu_on) + adr_l r6, __turn_mmu_on_end @ _pa(__turn_mmu_on_end) mov r5, r5, lsr #SECTION_SHIFT mov r6, r6, lsr #SECTION_SHIFT @@ -351,11 +348,6 @@ __create_page_tables: ret lr ENDPROC(__create_page_tables) .ltorg - .align -__turn_mmu_on_loc: - .long . - .long __turn_mmu_on - .long __turn_mmu_on_end #if defined(CONFIG_SMP) .text -- cgit v1.2.3-59-g8ed1b From 91580f0dbf24c6d616091526a900213bc7aa48fe Mon Sep 17 00:00:00 2001 From: Ard Biesheuvel Date: Mon, 14 Sep 2020 11:25:23 +0300 Subject: ARM: head.S: use PC-relative insn sequence for secondary_data Replace the open coded PC relative offset calculations with adr_l and ldr_l invocations. This removes some open coded arithmetic involving virtual addresses, avoids literal pools on v7+, and slightly reduces the footprint of the code. Note that it also removes a stale comment about the contents of r6. Reviewed-by: Nicolas Pitre Signed-off-by: Ard Biesheuvel --- arch/arm/kernel/head.S | 19 ++++--------------- 1 file changed, 4 insertions(+), 15 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S index f5a636fee9d0..478506b2d51f 100644 --- a/arch/arm/kernel/head.S +++ b/arch/arm/kernel/head.S @@ -383,10 +383,8 @@ ENTRY(secondary_startup) /* * Use the page tables supplied from __cpu_up. */ - adr r4, __secondary_data - ldmia r4, {r5, r7, r12} @ address to jump to after - sub lr, r4, r5 @ mmu has been enabled - add r3, r7, lr + adr_l r3, secondary_data + mov_l r12, __secondary_switched ldrd r4, r5, [r3, #0] @ get secondary_data.pgdir ARM_BE8(eor r4, r4, r5) @ Swap r5 and r4 in BE: ARM_BE8(eor r5, r4, r5) @ it can be done in 3 steps @@ -401,22 +399,13 @@ ARM_BE8(eor r4, r4, r5) @ without using a temp reg. ENDPROC(secondary_startup) ENDPROC(secondary_startup_arm) - /* - * r6 = &secondary_data - */ ENTRY(__secondary_switched) - ldr sp, [r7, #12] @ get secondary_data.stack + ldr_l r7, secondary_data + 12 @ get secondary_data.stack + mov sp, r7 mov fp, #0 b secondary_start_kernel ENDPROC(__secondary_switched) - .align - - .type __secondary_data, %object -__secondary_data: - .long . - .long secondary_data - .long __secondary_switched #endif /* defined(CONFIG_SMP) */ -- cgit v1.2.3-59-g8ed1b From 450abd38fe6c6313ce9bdd9dce81c1dd604f6fb0 Mon Sep 17 00:00:00 2001 From: Ard Biesheuvel Date: Mon, 14 Sep 2020 11:48:20 +0300 Subject: ARM: kernel: use relative references for UP/SMP alternatives Currently, the .alt.smp.init section contains the virtual addresses of the patch sites. Since patching may occur both before and after switching into virtual mode, this requires some manual handling of the address when applying the UP alternative. Let's simplify this by using relative offsets in the table entries: this allows us to simply add each entry's address to its contents, regardless of whether we are running in virtual mode or not. Reviewed-by: Nicolas Pitre Signed-off-by: Ard Biesheuvel --- arch/arm/include/asm/assembler.h | 4 ++-- arch/arm/include/asm/processor.h | 2 +- arch/arm/kernel/head.S | 10 +++++----- 3 files changed, 8 insertions(+), 8 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h index 72627c5fb3b2..6ed30421f697 100644 --- a/arch/arm/include/asm/assembler.h +++ b/arch/arm/include/asm/assembler.h @@ -259,7 +259,7 @@ */ #define ALT_UP(instr...) \ .pushsection ".alt.smp.init", "a" ;\ - .long 9998b ;\ + .long 9998b - . ;\ 9997: instr ;\ .if . - 9997b == 2 ;\ nop ;\ @@ -270,7 +270,7 @@ .popsection #define ALT_UP_B(label) \ .pushsection ".alt.smp.init", "a" ;\ - .long 9998b ;\ + .long 9998b - . ;\ W(b) . + (label - 9998b) ;\ .popsection #else diff --git a/arch/arm/include/asm/processor.h b/arch/arm/include/asm/processor.h index b9241051e5cb..9e6b97286307 100644 --- a/arch/arm/include/asm/processor.h +++ b/arch/arm/include/asm/processor.h @@ -96,7 +96,7 @@ unsigned long get_wchan(struct task_struct *p); #define __ALT_SMP_ASM(smp, up) \ "9998: " smp "\n" \ " .pushsection \".alt.smp.init\", \"a\"\n" \ - " .long 9998b\n" \ + " .long 9998b - .\n" \ " " up "\n" \ " .popsection\n" #else diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S index 478506b2d51f..cdc79fcee43e 100644 --- a/arch/arm/kernel/head.S +++ b/arch/arm/kernel/head.S @@ -546,14 +546,15 @@ smp_on_up: __do_fixup_smp_on_up: cmp r4, r5 reths lr - ldmia r4!, {r0, r6} - ARM( str r6, [r0, r3] ) - THUMB( add r0, r0, r3 ) + ldmia r4, {r0, r6} + ARM( str r6, [r0, r4] ) + THUMB( add r0, r0, r4 ) + add r4, r4, #8 #ifdef __ARMEB__ THUMB( mov r6, r6, ror #16 ) @ Convert word order for big-endian. #endif THUMB( strh r6, [r0], #2 ) @ For Thumb-2, store as two halfwords - THUMB( mov r6, r6, lsr #16 ) @ to be robust against misaligned r3. + THUMB( mov r6, r6, lsr #16 ) @ to be robust against misaligned r0. THUMB( strh r6, [r0] ) b __do_fixup_smp_on_up ENDPROC(__do_fixup_smp_on_up) @@ -562,7 +563,6 @@ ENTRY(fixup_smp) stmfd sp!, {r4 - r6, lr} mov r4, r0 add r5, r0, r1 - mov r3, #0 bl __do_fixup_smp_on_up ldmfd sp!, {r4 - r6, pc} ENDPROC(fixup_smp) -- cgit v1.2.3-59-g8ed1b From 59d2f2827dfdccf8911d5e51465136b52ba623c4 Mon Sep 17 00:00:00 2001 From: Ard Biesheuvel Date: Mon, 14 Sep 2020 11:25:29 +0300 Subject: ARM: head: use PC-relative insn sequence for __smp_alt Now that calling __do_fixup_smp_on_up() can be done without passing the physical-to-virtual offset in r3, we can replace the open coded PC relative offset calculations with a pair of adr_l invocations. This removes some open coded arithmetic involving virtual addresses, avoids literal pools on v7+, and slightly reduces the footprint of the code. Reviewed-by: Nicolas Pitre Signed-off-by: Ard Biesheuvel --- arch/arm/kernel/head.S | 12 ++---------- 1 file changed, 2 insertions(+), 10 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S index cdc79fcee43e..5e031a0bf9a9 100644 --- a/arch/arm/kernel/head.S +++ b/arch/arm/kernel/head.S @@ -520,19 +520,11 @@ ARM_BE8(rev r0, r0) @ byteswap if big endian retne lr __fixup_smp_on_up: - adr r0, 1f - ldmia r0, {r3 - r5} - sub r3, r0, r3 - add r4, r4, r3 - add r5, r5, r3 + adr_l r4, __smpalt_begin + adr_l r5, __smpalt_end b __do_fixup_smp_on_up ENDPROC(__fixup_smp) - .align -1: .word . - .word __smpalt_begin - .word __smpalt_end - .pushsection .data .align 2 .globl smp_on_up -- cgit v1.2.3-59-g8ed1b From d74d2b225018baa0e04e080ee9e80b21667ba3a2 Mon Sep 17 00:00:00 2001 From: Ard Biesheuvel Date: Mon, 14 Sep 2020 11:25:34 +0300 Subject: ARM: sleep.S: use PC-relative insn sequence for sleep_save_sp/mpidr_hash Replace the open coded PC relative offset calculations with adr_l and ldr_l invocations. This removes some open coded PC relative arithmetic, avoids literal pools on v7+, and slightly reduces the footprint of the code. Note that ALT_SMP() expects a single instruction so move the macro invocation after it. Reviewed-by: Nicolas Pitre Signed-off-by: Ard Biesheuvel --- arch/arm/kernel/sleep.S | 19 +++++-------------- 1 file changed, 5 insertions(+), 14 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/kernel/sleep.S b/arch/arm/kernel/sleep.S index 5dc8b80bb693..43077e11dafd 100644 --- a/arch/arm/kernel/sleep.S +++ b/arch/arm/kernel/sleep.S @@ -72,8 +72,9 @@ ENTRY(__cpu_suspend) ldr r3, =sleep_save_sp stmfd sp!, {r0, r1} @ save suspend func arg and pointer ldr r3, [r3, #SLEEP_SAVE_SP_VIRT] - ALT_SMP(ldr r0, =mpidr_hash) + ALT_SMP(W(nop)) @ don't use adr_l inside ALT_SMP() ALT_UP_B(1f) + adr_l r0, mpidr_hash /* This ldmia relies on the memory layout of the mpidr_hash struct */ ldmia r0, {r1, r6-r8} @ r1 = mpidr mask (r6,r7,r8) = l[0,1,2] shifts compute_mpidr_hash r0, r6, r7, r8, r2, r1 @@ -147,9 +148,8 @@ no_hyp: mov r1, #0 ALT_SMP(mrc p15, 0, r0, c0, c0, 5) ALT_UP_B(1f) - adr r2, mpidr_hash_ptr - ldr r3, [r2] - add r2, r2, r3 @ r2 = struct mpidr_hash phys address + adr_l r2, mpidr_hash @ r2 = struct mpidr_hash phys address + /* * This ldmia relies on the memory layout of the mpidr_hash * struct mpidr_hash. @@ -157,10 +157,7 @@ no_hyp: ldmia r2, { r3-r6 } @ r3 = mpidr mask (r4,r5,r6) = l[0,1,2] shifts compute_mpidr_hash r1, r4, r5, r6, r0, r3 1: - adr r0, _sleep_save_sp - ldr r2, [r0] - add r0, r0, r2 - ldr r0, [r0, #SLEEP_SAVE_SP_PHYS] + ldr_l r0, sleep_save_sp + SLEEP_SAVE_SP_PHYS ldr r0, [r0, r1, lsl #2] @ load phys pgd, stack, resume fn @@ -177,12 +174,6 @@ ENDPROC(cpu_resume_arm) ENDPROC(cpu_resume_no_hyp) #endif - .align 2 -_sleep_save_sp: - .long sleep_save_sp - . -mpidr_hash_ptr: - .long mpidr_hash - . @ mpidr_hash struct offset - .data .align 2 .type sleep_save_sp, #object -- cgit v1.2.3-59-g8ed1b From 3bcf906b194cebb6817cbb2f07b69e12aa5d7f51 Mon Sep 17 00:00:00 2001 From: Ard Biesheuvel Date: Mon, 14 Sep 2020 11:25:46 +0300 Subject: ARM: head.S: use PC relative insn sequence to calculate PHYS_OFFSET Replace the open coded arithmetic with a simple adr_l/sub pair. This removes some open coded arithmetic involving virtual addresses, avoids literal pools on v7+, and slightly reduces the footprint of the code. Reviewed-by: Nicolas Pitre Signed-off-by: Ard Biesheuvel --- arch/arm/kernel/head.S | 10 ++-------- 1 file changed, 2 insertions(+), 8 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S index 5e031a0bf9a9..ae0b08b47f52 100644 --- a/arch/arm/kernel/head.S +++ b/arch/arm/kernel/head.S @@ -103,10 +103,8 @@ ENTRY(stext) #endif #ifndef CONFIG_XIP_KERNEL - adr r3, 2f - ldmia r3, {r4, r8} - sub r4, r3, r4 @ (PHYS_OFFSET - PAGE_OFFSET) - add r8, r8, r4 @ PHYS_OFFSET + adr_l r8, _text @ __pa(_text) + sub r8, r8, #TEXT_OFFSET @ PHYS_OFFSET #else ldr r8, =PLAT_PHYS_OFFSET @ always constant in this case #endif @@ -158,10 +156,6 @@ ENTRY(stext) 1: b __enable_mmu ENDPROC(stext) .ltorg -#ifndef CONFIG_XIP_KERNEL -2: .long . - .long PAGE_OFFSET -#endif /* * Setup the initial page tables. We only setup the barest -- cgit v1.2.3-59-g8ed1b From aaac3733171fca948c4fb66b78257620e3885339 Mon Sep 17 00:00:00 2001 From: Ard Biesheuvel Date: Mon, 14 Sep 2020 11:25:52 +0300 Subject: ARM: kvm: replace open coded VA->PA calculations with adr_l call Replace the open coded calculations of the actual physical address of the KVM stub vector table with a single adr_l invocation. Reviewed-by: Nicolas Pitre Signed-off-by: Ard Biesheuvel --- arch/arm/boot/compressed/head.S | 15 ++------------- arch/arm/kernel/hyp-stub.S | 27 ++++++++++++--------------- 2 files changed, 14 insertions(+), 28 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S index 5b591dacbaaf..9905fb7560df 100644 --- a/arch/arm/boot/compressed/head.S +++ b/arch/arm/boot/compressed/head.S @@ -468,15 +468,10 @@ dtb_check_done: /* * Compute the address of the hyp vectors after relocation. - * This requires some arithmetic since we cannot directly - * reference __hyp_stub_vectors in a PC-relative way. * Call __hyp_set_vectors with the new address so that we * can HVC again after the copy. */ -0: adr r0, 0b - movw r1, #:lower16:__hyp_stub_vectors - 0b - movt r1, #:upper16:__hyp_stub_vectors - 0b - add r0, r0, r1 + adr_l r0, __hyp_stub_vectors sub r0, r0, r5 add r0, r0, r10 bl __hyp_set_vectors @@ -627,17 +622,11 @@ not_relocated: mov r0, #0 cmp r0, #HYP_MODE @ if not booted in HYP mode... bne __enter_kernel @ boot kernel directly - adr r12, .L__hyp_reentry_vectors_offset - ldr r0, [r12] - add r0, r0, r12 - + adr_l r0, __hyp_reentry_vectors bl __hyp_set_vectors __HVC(0) @ otherwise bounce to hyp mode b . @ should never be reached - - .align 2 -.L__hyp_reentry_vectors_offset: .long __hyp_reentry_vectors - . #else b __enter_kernel #endif diff --git a/arch/arm/kernel/hyp-stub.S b/arch/arm/kernel/hyp-stub.S index 26d8e03b1dd3..103d0bdb2b7e 100644 --- a/arch/arm/kernel/hyp-stub.S +++ b/arch/arm/kernel/hyp-stub.S @@ -24,41 +24,38 @@ ENTRY(__boot_cpu_mode) .text /* - * Save the primary CPU boot mode. Requires 3 scratch registers. + * Save the primary CPU boot mode. Requires 2 scratch registers. */ - .macro store_primary_cpu_mode reg1, reg2, reg3 + .macro store_primary_cpu_mode reg1, reg2 mrs \reg1, cpsr and \reg1, \reg1, #MODE_MASK - adr \reg2, .L__boot_cpu_mode_offset - ldr \reg3, [\reg2] - str \reg1, [\reg2, \reg3] + str_l \reg1, __boot_cpu_mode, \reg2 .endm /* * Compare the current mode with the one saved on the primary CPU. * If they don't match, record that fact. The Z bit indicates * if there's a match or not. - * Requires 3 additionnal scratch registers. + * Requires 2 additional scratch registers. */ - .macro compare_cpu_mode_with_primary mode, reg1, reg2, reg3 - adr \reg2, .L__boot_cpu_mode_offset - ldr \reg3, [\reg2] - ldr \reg1, [\reg2, \reg3] + .macro compare_cpu_mode_with_primary mode, reg1, reg2 + adr_l \reg2, __boot_cpu_mode + ldr \reg1, [\reg2] cmp \mode, \reg1 @ matches primary CPU boot mode? orrne \reg1, \reg1, #BOOT_CPU_MODE_MISMATCH - strne \reg1, [\reg2, \reg3] @ record what happened and give up + strne \reg1, [\reg2] @ record what happened and give up .endm #else /* ZIMAGE */ - .macro store_primary_cpu_mode reg1:req, reg2:req, reg3:req + .macro store_primary_cpu_mode reg1:req, reg2:req .endm /* * The zImage loader only runs on one CPU, so we don't bother with mult-CPU * consistency checking: */ - .macro compare_cpu_mode_with_primary mode, reg1, reg2, reg3 + .macro compare_cpu_mode_with_primary mode, reg1, reg2 cmp \mode, \mode .endm @@ -73,7 +70,7 @@ ENTRY(__boot_cpu_mode) */ @ Call this from the primary CPU ENTRY(__hyp_stub_install) - store_primary_cpu_mode r4, r5, r6 + store_primary_cpu_mode r4, r5 ENDPROC(__hyp_stub_install) @ fall through... @@ -87,7 +84,7 @@ ENTRY(__hyp_stub_install_secondary) * If the secondary has booted with a different mode, give up * immediately. */ - compare_cpu_mode_with_primary r4, r5, r6, r7 + compare_cpu_mode_with_primary r4, r5, r6 retne lr /* -- cgit v1.2.3-59-g8ed1b From 02e46262af5db410da5a27783833d68e2bdfb352 Mon Sep 17 00:00:00 2001 From: Alexander Dahl Date: Mon, 5 Oct 2020 22:34:43 +0200 Subject: ARM: dts: at91: smartkiz: Reference led node directly Do it the simple way like for the other kizbox boards. This will allow renaming the led controller node name later without breaking things. Signed-off-by: Alexander Dahl Signed-off-by: Alexandre Belloni Link: https://lore.kernel.org/r/20201005203451.9985-5-post@lespocky.de --- arch/arm/boot/dts/at91-smartkiz.dts | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/at91-smartkiz.dts b/arch/arm/boot/dts/at91-smartkiz.dts index 106f23ba4a3b..b76a6b5ac464 100644 --- a/arch/arm/boot/dts/at91-smartkiz.dts +++ b/arch/arm/boot/dts/at91-smartkiz.dts @@ -84,10 +84,8 @@ status = "okay"; }; -&leds { - blue { - status = "okay"; - }; +&led_blue { + status = "okay"; }; &adc0 { -- cgit v1.2.3-59-g8ed1b From 997ebd64df39f3916c37ca67a6eff58e79a13c73 Mon Sep 17 00:00:00 2001 From: Alexander Dahl Date: Mon, 5 Oct 2020 22:34:44 +0200 Subject: ARM: dts: at91: Fix schema warnings for pwm-leds The node names for devices using the pwm-leds driver follow a certain naming scheme (now). Parent node name is not enforced, but recommended by DT project. DTC arch/arm/boot/dts/at91-kizbox2-2.dt.yaml CHECK arch/arm/boot/dts/at91-kizbox2-2.dt.yaml /home/alex/build/linux/arch/arm/boot/dts/at91-kizbox2-2.dt.yaml: pwm_leds: 'blue', 'green', 'red' do not match any of the regexes: '^led(-[0-9a-f]+)?$', 'pinctrl-[0-9]+' From schema: /home/alex/src/linux/leds/Documentation/devicetree/bindings/leds/leds-pwm.yaml DTC arch/arm/boot/dts/at91-kizbox3-hs.dt.yaml CHECK arch/arm/boot/dts/at91-kizbox3-hs.dt.yaml /home/alex/build/linux/arch/arm/boot/dts/at91-kizbox3-hs.dt.yaml: pwm_leds: 'blue', 'green', 'red', 'white' do not match any of the regexes: '^led(-[0-9a-f]+)?$', 'pinctrl-[0-9]+' From schema: /home/alex/src/linux/leds/Documentation/devicetree/bindings/leds/leds-pwm.yaml (Warnings above are for armv7 only, armv5 would produce similar warnings.) Signed-off-by: Alexander Dahl Signed-off-by: Alexandre Belloni Link: https://lore.kernel.org/r/20201005203451.9985-6-post@lespocky.de --- arch/arm/boot/dts/at91-kizbox.dts | 10 +++++----- arch/arm/boot/dts/at91-kizbox2-common.dtsi | 8 ++++---- arch/arm/boot/dts/at91-kizbox3-hs.dts | 16 ++++++++-------- arch/arm/boot/dts/at91-kizbox3_common.dtsi | 10 +++++----- arch/arm/boot/dts/at91-kizboxmini-common.dtsi | 8 ++++---- arch/arm/boot/dts/at91sam9m10g45ek.dts | 10 +++++----- arch/arm/boot/dts/at91sam9rlek.dts | 10 +++++----- 7 files changed, 36 insertions(+), 36 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/at91-kizbox.dts b/arch/arm/boot/dts/at91-kizbox.dts index 7add151f6250..8b33fe5564fe 100644 --- a/arch/arm/boot/dts/at91-kizbox.dts +++ b/arch/arm/boot/dts/at91-kizbox.dts @@ -48,31 +48,31 @@ }; }; - pwm_leds { + led-controller { compatible = "pwm-leds"; - network_green { + led-1 { label = "pwm:green:network"; pwms = <&tcb_pwm 2 10000000 PWM_POLARITY_INVERTED>; max-brightness = <255>; linux,default-trigger = "default-on"; }; - network_red { + led-2 { label = "pwm:red:network"; pwms = <&tcb_pwm 4 10000000 PWM_POLARITY_INVERTED>; max-brightness = <255>; linux,default-trigger = "default-on"; }; - user_green { + led-3 { label = "pwm:green:user"; pwms = <&tcb_pwm 0 10000000 PWM_POLARITY_INVERTED>; max-brightness = <255>; linux,default-trigger = "default-on"; }; - user_red { + led-4 { label = "pwm:red:user"; pwms = <&tcb_pwm 1 10000000 PWM_POLARITY_INVERTED>; max-brightness = <255>; diff --git a/arch/arm/boot/dts/at91-kizbox2-common.dtsi b/arch/arm/boot/dts/at91-kizbox2-common.dtsi index 25f761065106..c08834ddf07b 100644 --- a/arch/arm/boot/dts/at91-kizbox2-common.dtsi +++ b/arch/arm/boot/dts/at91-kizbox2-common.dtsi @@ -58,24 +58,24 @@ }; }; - pwm_leds { + led-controller { compatible = "pwm-leds"; - blue { + led-1 { label = "pwm:blue:user"; pwms = <&pwm0 2 10000000 0>; max-brightness = <255>; linux,default-trigger = "none"; }; - green { + led-2 { label = "pwm:green:user"; pwms = <&pwm0 1 10000000 0>; max-brightness = <255>; linux,default-trigger = "default-on"; }; - red { + led-3 { label = "pwm:red:user"; pwms = <&pwm0 0 10000000 0>; max-brightness = <255>; diff --git a/arch/arm/boot/dts/at91-kizbox3-hs.dts b/arch/arm/boot/dts/at91-kizbox3-hs.dts index 0da1f0557eaf..2799b2a1f4d2 100644 --- a/arch/arm/boot/dts/at91-kizbox3-hs.dts +++ b/arch/arm/boot/dts/at91-kizbox3-hs.dts @@ -15,40 +15,40 @@ model = "Overkiz KIZBOX3-HS"; compatible = "overkiz,kizbox3-hs", "atmel,sama5d2", "atmel,sama5"; - pwm_leds { + led-controller-1 { status = "okay"; - red { + led-1 { status = "okay"; }; - green { + led-2 { status = "okay"; }; - blue { + led-3 { status = "okay"; }; - white { + led-4 { status = "okay"; }; }; - leds { + led-controller-2 { compatible = "gpio-leds"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_led_red &pinctrl_led_white>; status = "okay"; - red { + led-5 { label = "pio:red:user"; gpios = <&pioA PIN_PB1 GPIO_ACTIVE_HIGH>; default-state = "off"; }; - white { + led-6 { label = "pio:white:user"; gpios = <&pioA PIN_PB8 GPIO_ACTIVE_HIGH>; default-state = "off"; diff --git a/arch/arm/boot/dts/at91-kizbox3_common.dtsi b/arch/arm/boot/dts/at91-kizbox3_common.dtsi index 7c3076e245ef..9ce513dd514b 100644 --- a/arch/arm/boot/dts/at91-kizbox3_common.dtsi +++ b/arch/arm/boot/dts/at91-kizbox3_common.dtsi @@ -62,7 +62,7 @@ regulator-always-on; }; - pwm_leds { + led-controller-1 { compatible = "pwm-leds"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm0_pwm_h0 @@ -71,7 +71,7 @@ &pinctrl_pwm0_pwm_h3>; status = "disabled"; - red { + led-1 { label = "pwm:red:user"; pwms = <&pwm0 0 10000000 0>; max-brightness = <255>; @@ -79,7 +79,7 @@ status = "disabled"; }; - green { + led-2 { label = "pwm:green:user"; pwms = <&pwm0 1 10000000 0>; max-brightness = <255>; @@ -87,14 +87,14 @@ status = "disabled"; }; - blue { + led-3 { label = "pwm:blue:user"; pwms = <&pwm0 2 10000000 0>; max-brightness = <255>; status = "disabled"; }; - white { + led-4 { label = "pwm:white:user"; pwms = <&pwm0 3 10000000 0>; max-brightness = <255>; diff --git a/arch/arm/boot/dts/at91-kizboxmini-common.dtsi b/arch/arm/boot/dts/at91-kizboxmini-common.dtsi index d37724c10695..9c622892c692 100644 --- a/arch/arm/boot/dts/at91-kizboxmini-common.dtsi +++ b/arch/arm/boot/dts/at91-kizboxmini-common.dtsi @@ -54,10 +54,10 @@ }; }; - leds: pwm_leds { + leds: led-controller-1 { compatible = "pwm-leds"; - led_blue: pwm_blue { + led_blue: led-1 { label = "pwm:blue:user"; pwms = <&pwm0 2 10000000 0>; max-brightness = <255>; @@ -65,14 +65,14 @@ status = "disabled"; }; - led_green: pwm_green { + led_green: led-2 { label = "pwm:green:user"; pwms = <&pwm0 0 10000000 0>; max-brightness = <255>; linux,default-trigger = "default-on"; }; - led_red: pwm_red { + led_red: led-3 { label = "pwm:red:user"; pwms = <&pwm0 1 10000000 0>; max-brightness = <255>; diff --git a/arch/arm/boot/dts/at91sam9m10g45ek.dts b/arch/arm/boot/dts/at91sam9m10g45ek.dts index 9734667abbfc..b6256a20fbc7 100644 --- a/arch/arm/boot/dts/at91sam9m10g45ek.dts +++ b/arch/arm/boot/dts/at91sam9m10g45ek.dts @@ -315,27 +315,27 @@ }; }; - leds { + led-controller-1 { compatible = "gpio-leds"; - d8 { + led-1 { label = "d8"; gpios = <&pioD 30 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; }; - pwmleds { + led-controller-2 { compatible = "pwm-leds"; - d6 { + led-2 { label = "d6"; pwms = <&pwm0 3 5000 PWM_POLARITY_INVERTED>; max-brightness = <255>; linux,default-trigger = "nand-disk"; }; - d7 { + led-3 { label = "d7"; pwms = <&pwm0 1 5000 PWM_POLARITY_INVERTED>; max-brightness = <255>; diff --git a/arch/arm/boot/dts/at91sam9rlek.dts b/arch/arm/boot/dts/at91sam9rlek.dts index 1590862f16f2..62981b39c815 100644 --- a/arch/arm/boot/dts/at91sam9rlek.dts +++ b/arch/arm/boot/dts/at91sam9rlek.dts @@ -218,26 +218,26 @@ }; }; - pwmleds { + led-controller-1 { compatible = "pwm-leds"; - ds1 { + led-1 { label = "ds1"; pwms = <&pwm0 1 5000 PWM_POLARITY_INVERTED>; max-brightness = <255>; }; - ds2 { + led-2 { label = "ds2"; pwms = <&pwm0 2 5000 PWM_POLARITY_INVERTED>; max-brightness = <255>; }; }; - leds { + led-controller-2 { compatible = "gpio-leds"; - ds3 { + led-3 { label = "ds3"; gpios = <&pioD 14 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; -- cgit v1.2.3-59-g8ed1b From 132e900a47b89c45f760c82f0d0929903b96eb08 Mon Sep 17 00:00:00 2001 From: Marek Szyprowski Date: Tue, 27 Oct 2020 15:23:28 +0100 Subject: ARM: dts: exynos: Enable Bluetooth support for Trats board Add a node for the BCM4334 Bluetooth chip on the serial bus #0 on the Exynos4210-based Trats boards. Signed-off-by: Marek Szyprowski Link: https://lore.kernel.org/r/20201027142330.5121-1-m.szyprowski@samsung.com Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos4210-trats.dts | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/exynos4210-trats.dts b/arch/arm/boot/dts/exynos4210-trats.dts index a226bec56a45..eb6ca2a74cc0 100644 --- a/arch/arm/boot/dts/exynos4210-trats.dts +++ b/arch/arm/boot/dts/exynos4210-trats.dts @@ -462,6 +462,26 @@ }; }; +&pinctrl_1 { + bt_shutdown: bt-shutdown { + samsung,pins = "gpl1-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + bt_host_wakeup: bt-host-wakeup { + samsung,pins = "gpx2-6"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + bt_device_wakeup: bt-device-wakeup { + samsung,pins = "gpx3-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; +}; + &rtc { status = "okay"; clocks = <&clock CLK_RTC>, <&pmic_ap_clk>; @@ -512,6 +532,17 @@ &serial_0 { status = "okay"; + pinctrl-0 = <&uart0_data &uart0_fctl>; + pinctrl-names = "default"; + + bluetooth { + compatible = "brcm,bcm4330-bt"; + pinctrl-0 = <&bt_shutdown &bt_device_wakeup &bt_host_wakeup>; + pinctrl-names = "default"; + shutdown-gpios = <&gpl1 0 GPIO_ACTIVE_HIGH>; + device-wakeup-gpios = <&gpx3 1 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios = <&gpx2 6 GPIO_ACTIVE_HIGH>; + }; }; &serial_1 { -- cgit v1.2.3-59-g8ed1b From 4e77879298541bde7271f1e735933d07fa8ae8bf Mon Sep 17 00:00:00 2001 From: Marek Szyprowski Date: Tue, 27 Oct 2020 15:23:29 +0100 Subject: ARM: dts: exynos: Enable Bluetooth support for Universal C210 board Add a node for the BCM4330 Bluetooth chip on the serial bus #0 on the Exynos4210-based Universal C210 boards. Signed-off-by: Marek Szyprowski Link: https://lore.kernel.org/r/20201027142330.5121-2-m.szyprowski@samsung.com Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos4210-universal_c210.dts | 29 +++++++++++++++++++++++++ 1 file changed, 29 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/exynos4210-universal_c210.dts b/arch/arm/boot/dts/exynos4210-universal_c210.dts index 08284e8f3624..dd44ad2c6ad6 100644 --- a/arch/arm/boot/dts/exynos4210-universal_c210.dts +++ b/arch/arm/boot/dts/exynos4210-universal_c210.dts @@ -532,6 +532,24 @@ }; &pinctrl_1 { + bt_shutdown: bt-shutdown { + samsung,pins = "gpe1-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + bt_host_wakeup: bt-host-wakeup { + samsung,pins = "gpx2-6"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + bt_device_wakeup: bt-device-wakeup { + samsung,pins = "gpx3-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + lp3974_irq: lp3974-irq { samsung,pins = "gpx0-7", "gpx2-7"; samsung,pin-pud = ; @@ -608,6 +626,17 @@ status = "okay"; /delete-property/dmas; /delete-property/dma-names; + pinctrl-0 = <&uart0_data &uart0_fctl>; + pinctrl-names = "default"; + + bluetooth { + compatible = "brcm,bcm4330-bt"; + pinctrl-0 = <&bt_shutdown &bt_device_wakeup &bt_host_wakeup>; + pinctrl-names = "default"; + shutdown-gpios = <&gpe1 4 GPIO_ACTIVE_HIGH>; + device-wakeup-gpios = <&gpx3 1 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios = <&gpx2 6 GPIO_ACTIVE_HIGH>; + }; }; &serial_1 { -- cgit v1.2.3-59-g8ed1b From d35cdc833bf415d855261ebe2c4a6349f882b265 Mon Sep 17 00:00:00 2001 From: Marek Szyprowski Date: Tue, 27 Oct 2020 15:23:30 +0100 Subject: ARM: dts: exynos: Enable Bluetooth support for Midas board family Add a node for the BCM4334 Bluetooth chip on the serial bus #0 on the Exynos4412-based Midas board family. Signed-off-by: Marek Szyprowski Link: https://lore.kernel.org/r/20201027142330.5121-3-m.szyprowski@samsung.com Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos4412-midas.dtsi | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/exynos4412-midas.dtsi b/arch/arm/boot/dts/exynos4412-midas.dtsi index 7e7c243ff196..96287c6ff359 100644 --- a/arch/arm/boot/dts/exynos4412-midas.dtsi +++ b/arch/arm/boot/dts/exynos4412-midas.dtsi @@ -1109,6 +1109,21 @@ samsung,pin-pud = ; }; + bt_shutdown: bt-shutdown { + samsung,pins = "gpl0-6"; + samsung,pin-pud = ; + }; + + bt_host_wakeup: bt-host-wakeup { + samsung,pins = "gpx2-6"; + samsung,pin-pud = ; + }; + + bt_device_wakeup: bt-device-wakeup { + samsung,pins = "gpx3-1"; + samsung,pin-pud = ; + }; + max77686_irq: max77686-irq { samsung,pins = "gpx0-7"; samsung,pin-pud = ; @@ -1386,7 +1401,20 @@ }; &serial_0 { + pinctrl-0 = <&uart0_data &uart0_fctl>; + pinctrl-names = "default"; status = "okay"; + + bluetooth { + compatible = "brcm,bcm4330-bt"; + pinctrl-0 = <&bt_shutdown &bt_device_wakeup &bt_host_wakeup>; + pinctrl-names = "default"; + max-speed = <3000000>; + shutdown-gpios = <&gpl0 6 GPIO_ACTIVE_HIGH>; + device-wakeup-gpios = <&gpx3 1 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios = <&gpx2 6 GPIO_ACTIVE_HIGH>; + clocks = <&max77686 MAX77686_CLK_PMIC>; + }; }; &serial_1 { -- cgit v1.2.3-59-g8ed1b From 970f6cf2e91465c53dbbf9d80d755a7e8139fedb Mon Sep 17 00:00:00 2001 From: Marek Szyprowski Date: Tue, 27 Oct 2020 21:17:16 +0100 Subject: ARM: exynos: Simplify code in Exynos3250 CPU core restart path exynos_core_restart() is called by secondary CPU boot procedure, used by CPU hotplug and coupled CPU idle. Replace of_machine_is_compatible() call with a simple SoC revision check. of_machine_is_compatible() function performs a dozen of string comparisons during the full device tree walk, while soc_is_exynos3250() is a simple integer check on SoC revision variable. This change also fixes the following warning: ============================= WARNING: suspicious RCU usage 5.10.0-rc1-00001-g6f65599d1f4f-dirty #1800 Not tainted ----------------------------- ./include/trace/events/lock.h:37 suspicious rcu_dereference_check() usage! other info that might help us debug this: rcu_scheduler_active = 2, debug_locks = 1 RCU used illegally from extended quiescent state! no locks held by swapper/0/0. stack backtrace: CPU: 0 PID: 0 Comm: swapper/0 Not tainted 5.10.0-rc1-00001-g6f65599d1f4f-dirty #1800 Hardware name: Samsung Exynos (Flattened Device Tree) [] (unwind_backtrace) from [] (show_stack+0x10/0x14) [] (show_stack) from [] (dump_stack+0xb4/0xd4) [] (dump_stack) from [] (lock_acquire+0x418/0x584) [] (lock_acquire) from [] (_raw_spin_lock_irqsave+0x4c/0x60) [] (_raw_spin_lock_irqsave) from [] (of_device_is_compatible+0x1c/0x4c) [] (of_device_is_compatible) from [] (exynos_core_restart+0x14/0xb0) [] (exynos_core_restart) from [] (exynos_cpu0_enter_aftr+0x1d0/0x1dc) [] (exynos_cpu0_enter_aftr) from [] (exynos_enter_coupled_lowpower+0x44/0x74) [] (exynos_enter_coupled_lowpower) from [] (cpuidle_enter_state+0x178/0x660) [] (cpuidle_enter_state) from [] (cpuidle_enter_state_coupled+0x35c/0x378) [] (cpuidle_enter_state_coupled) from [] (cpuidle_enter+0x50/0x54) [] (cpuidle_enter) from [] (do_idle+0x224/0x2a4) [] (do_idle) from [] (cpu_startup_entry+0x18/0x1c) [] (cpu_startup_entry) from [] (start_kernel+0x640/0x67c) [] (start_kernel) from [<00000000>] (0x0) Signed-off-by: Marek Szyprowski Link: https://lore.kernel.org/r/20201027201716.15745-1-m.szyprowski@samsung.com Signed-off-by: Krzysztof Kozlowski --- arch/arm/mach-exynos/platsmp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c index d7fedbb2eefe..ea0be59f469a 100644 --- a/arch/arm/mach-exynos/platsmp.c +++ b/arch/arm/mach-exynos/platsmp.c @@ -215,7 +215,7 @@ void exynos_core_restart(u32 core_id) unsigned int timeout = 16; u32 val; - if (!of_machine_is_compatible("samsung,exynos3250")) + if (!soc_is_exynos3250()) return; while (timeout && !pmu_raw_readl(S5P_PMU_SPARE2)) { -- cgit v1.2.3-59-g8ed1b From fb533fc76d341ab73fc7e3cec0ab012bd2881ca7 Mon Sep 17 00:00:00 2001 From: Eugen Hristev Date: Fri, 16 Oct 2020 10:51:09 +0300 Subject: ARM: configs: at91: sama5: resync with media changes The media tree Kconfig has changed recently, and a lot of modules were built unintentionally, like the dvb frontends and encoders. Resync the defconfig to build the sama5 drivers and tested sensors. Signed-off-by: Eugen Hristev Signed-off-by: Alexandre Belloni Link: https://lore.kernel.org/r/20201016075109.287506-1-eugen.hristev@microchip.com --- arch/arm/configs/sama5_defconfig | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/configs/sama5_defconfig b/arch/arm/configs/sama5_defconfig index 037d3a718a60..2c8a621a8f1f 100644 --- a/arch/arm/configs/sama5_defconfig +++ b/arch/arm/configs/sama5_defconfig @@ -153,9 +153,18 @@ CONFIG_REGULATOR_ACT8945A=y CONFIG_REGULATOR_MCP16502=m CONFIG_REGULATOR_PWM=m CONFIG_MEDIA_SUPPORT=y +CONFIG_MEDIA_SUPPORT_FILTER=y +# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set CONFIG_MEDIA_CAMERA_SUPPORT=y +CONFIG_MEDIA_PLATFORM_SUPPORT=y CONFIG_V4L_PLATFORM_DRIVERS=y +CONFIG_VIDEO_ATMEL_ISC=y CONFIG_VIDEO_ATMEL_ISI=y +CONFIG_VIDEO_OV2640=m +CONFIG_VIDEO_OV5640=m +CONFIG_VIDEO_OV7670=m +CONFIG_VIDEO_OV7740=m +CONFIG_VIDEO_MT9V032=m CONFIG_DRM=y CONFIG_DRM_ATMEL_HLCDC=y CONFIG_DRM_PANEL_SIMPLE=y -- cgit v1.2.3-59-g8ed1b From c9dc33d13c813e20c6dcfd5a9f54122225ca46bb Mon Sep 17 00:00:00 2001 From: Bartosz Golaszewski Date: Mon, 26 Oct 2020 11:46:18 +0100 Subject: ARM: dts: at91: at91-sama5d27_som1: fix EEPROM compatible AT24 compatibles require a vendor prefix. Use the default "atmel". Signed-off-by: Bartosz Golaszewski Signed-off-by: Alexandre Belloni Link: https://lore.kernel.org/r/20201026104618.23415-1-brgl@bgdev.pl --- arch/arm/boot/dts/at91-sama5d27_som1.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/at91-sama5d27_som1.dtsi b/arch/arm/boot/dts/at91-sama5d27_som1.dtsi index b1f994c0ae79..1b1163858b1d 100644 --- a/arch/arm/boot/dts/at91-sama5d27_som1.dtsi +++ b/arch/arm/boot/dts/at91-sama5d27_som1.dtsi @@ -100,7 +100,7 @@ status = "okay"; at24@50 { - compatible = "24c02"; + compatible = "atmel,24c02"; reg = <0x50>; pagesize = <8>; }; -- cgit v1.2.3-59-g8ed1b From 157a5697f6f24aacf8017acd387e3fdc1f4c1950 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 27 Oct 2020 18:09:36 +0100 Subject: ARM: dts: exynos: adjust node names to DT spec in Exynos3250 boards The Devicetree specification expects device node names to have a generic name, representing the class of a device. Also the convention for node names is to use hyphens, not underscores. No functional changes. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20201027170947.132725-2-krzk@kernel.org --- arch/arm/boot/dts/exynos3250-artik5.dtsi | 2 +- arch/arm/boot/dts/exynos3250-monk.dts | 8 ++++---- arch/arm/boot/dts/exynos3250-rinato.dts | 8 ++++---- 3 files changed, 9 insertions(+), 9 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/exynos3250-artik5.dtsi b/arch/arm/boot/dts/exynos3250-artik5.dtsi index 12887b3924af..04290ec4583a 100644 --- a/arch/arm/boot/dts/exynos3250-artik5.dtsi +++ b/arch/arm/boot/dts/exynos3250-artik5.dtsi @@ -76,7 +76,7 @@ samsung,i2c-max-bus-freq = <100000>; status = "okay"; - s2mps14_pmic@66 { + pmic@66 { compatible = "samsung,s2mps14-pmic"; interrupt-parent = <&gpx3>; interrupts = <5 IRQ_TYPE_NONE>; diff --git a/arch/arm/boot/dts/exynos3250-monk.dts b/arch/arm/boot/dts/exynos3250-monk.dts index c1a68e612037..69451566945d 100644 --- a/arch/arm/boot/dts/exynos3250-monk.dts +++ b/arch/arm/boot/dts/exynos3250-monk.dts @@ -34,10 +34,10 @@ reg = <0x0205F000 0x1000>; }; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; - power_key { + power-key { gpios = <&gpx2 7 GPIO_ACTIVE_LOW>; linux,code = ; label = "power key"; @@ -62,7 +62,7 @@ #address-cells = <1>; #size-cells = <0>; - max77836: subpmic@25 { + max77836: pmic@25 { compatible = "maxim,max77836"; interrupt-parent = <&gpx1>; interrupts = <5 IRQ_TYPE_NONE>; @@ -197,7 +197,7 @@ samsung,i2c-max-bus-freq = <100000>; status = "okay"; - s2mps14_pmic@66 { + pmic@66 { compatible = "samsung,s2mps14-pmic"; interrupt-parent = <&gpx0>; interrupts = <7 IRQ_TYPE_NONE>; diff --git a/arch/arm/boot/dts/exynos3250-rinato.dts b/arch/arm/boot/dts/exynos3250-rinato.dts index b55afaaa691e..a26e3e582a7e 100644 --- a/arch/arm/boot/dts/exynos3250-rinato.dts +++ b/arch/arm/boot/dts/exynos3250-rinato.dts @@ -38,10 +38,10 @@ reg = <0x0205F000 0x1000>; }; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; - power_key { + power-key { gpios = <&gpx2 7 GPIO_ACTIVE_LOW>; linux,code = ; label = "power key"; @@ -62,7 +62,7 @@ #address-cells = <1>; #size-cells = <0>; - max77836: subpmic@25 { + max77836: pmic@25 { compatible = "maxim,max77836"; interrupt-parent = <&gpx1>; interrupts = <5 IRQ_TYPE_NONE>; @@ -267,7 +267,7 @@ samsung,i2c-max-bus-freq = <100000>; status = "okay"; - s2mps14_pmic@66 { + pmic@66 { compatible = "samsung,s2mps14-pmic"; interrupt-parent = <&gpx0>; interrupts = <7 IRQ_TYPE_NONE>; -- cgit v1.2.3-59-g8ed1b From d918633c8acbd42afb694a6d859f449f4bf9d3bf Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 27 Oct 2020 18:09:37 +0100 Subject: ARM: dts: exynos: adjust node names to DT spec in Exynos4210 boards The Devicetree specification expects device node names to have a generic name, representing the class of a device. Also the convention for node names is to use hyphens, not underscores. No functional changes. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20201027170947.132725-3-krzk@kernel.org --- arch/arm/boot/dts/exynos4210-i9100.dts | 6 +++--- arch/arm/boot/dts/exynos4210-origen.dts | 4 ++-- arch/arm/boot/dts/exynos4210-smdkv310.dts | 22 +++++++++++----------- arch/arm/boot/dts/exynos4210-trats.dts | 4 ++-- 4 files changed, 18 insertions(+), 18 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/exynos4210-i9100.dts b/arch/arm/boot/dts/exynos4210-i9100.dts index 5370ee477186..a0c3bab382ae 100644 --- a/arch/arm/boot/dts/exynos4210-i9100.dts +++ b/arch/arm/boot/dts/exynos4210-i9100.dts @@ -329,7 +329,7 @@ pinctrl-0 = <&i2c3_bus>; pinctrl-names = "default"; - mxt224-touchscreen@4a { + touchscreen@4a { compatible = "atmel,maxtouch"; reg = <0x4a>; @@ -348,7 +348,7 @@ pinctrl-0 = <&i2c5_bus>; pinctrl-names = "default"; - max8997_pmic@66 { + pmic@66 { compatible = "maxim,max8997-pmic"; reg = <0x66>; @@ -597,7 +597,7 @@ pinctrl-0 = <&i2c7_bus>; pinctrl-names = "default"; - ak8975@c { + magnetometer@c { compatible = "asahi-kasei,ak8975"; reg = <0x0c>; diff --git a/arch/arm/boot/dts/exynos4210-origen.dts b/arch/arm/boot/dts/exynos4210-origen.dts index 7d2cfbafefb2..1c5394152561 100644 --- a/arch/arm/boot/dts/exynos4210-origen.dts +++ b/arch/arm/boot/dts/exynos4210-origen.dts @@ -43,7 +43,7 @@ enable-active-high; }; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; up { @@ -171,7 +171,7 @@ pinctrl-0 = <&i2c0_bus>; pinctrl-names = "default"; - max8997_pmic@66 { + pmic@66 { compatible = "maxim,max8997-pmic"; reg = <0x66>; interrupt-parent = <&gpx0>; diff --git a/arch/arm/boot/dts/exynos4210-smdkv310.dts b/arch/arm/boot/dts/exynos4210-smdkv310.dts index c5609afa6101..d5797a67bf48 100644 --- a/arch/arm/boot/dts/exynos4210-smdkv310.dts +++ b/arch/arm/boot/dts/exynos4210-smdkv310.dts @@ -90,61 +90,61 @@ pinctrl-0 = <&keypad_rows &keypad_cols>; status = "okay"; - key_1 { + key-1 { keypad,row = <0>; keypad,column = <3>; linux,code = <2>; }; - key_2 { + key-2 { keypad,row = <0>; keypad,column = <4>; linux,code = <3>; }; - key_3 { + key-3 { keypad,row = <0>; keypad,column = <5>; linux,code = <4>; }; - key_4 { + key-4 { keypad,row = <0>; keypad,column = <6>; linux,code = <5>; }; - key_5 { + key-5 { keypad,row = <0>; keypad,column = <7>; linux,code = <6>; }; - key_a { + key-a { keypad,row = <1>; keypad,column = <3>; linux,code = <30>; }; - key_b { + key-b { keypad,row = <1>; keypad,column = <4>; linux,code = <48>; }; - key_c { + key-c { keypad,row = <1>; keypad,column = <5>; linux,code = <46>; }; - key_d { + key-d { keypad,row = <1>; keypad,column = <6>; linux,code = <32>; }; - key_e { + key-e { keypad,row = <1>; keypad,column = <7>; linux,code = <18>; @@ -200,7 +200,7 @@ cs-gpios = <&gpc1 2 GPIO_ACTIVE_HIGH>; status = "okay"; - w25x80@0 { + flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "w25x80"; diff --git a/arch/arm/boot/dts/exynos4210-trats.dts b/arch/arm/boot/dts/exynos4210-trats.dts index eb6ca2a74cc0..d2406c9146b8 100644 --- a/arch/arm/boot/dts/exynos4210-trats.dts +++ b/arch/arm/boot/dts/exynos4210-trats.dts @@ -263,7 +263,7 @@ pinctrl-names = "default"; status = "okay"; - mms114-touchscreen@48 { + touchscreen@48 { compatible = "melfas,mms114"; reg = <0x48>; interrupt-parent = <&gpx0>; @@ -283,7 +283,7 @@ pinctrl-names = "default"; status = "okay"; - max8997_pmic@66 { + pmic@66 { compatible = "maxim,max8997-pmic"; reg = <0x66>; -- cgit v1.2.3-59-g8ed1b From 43552e6d5a6109df05ea038f512a20b45ca5010c Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 27 Oct 2020 18:09:38 +0100 Subject: ARM: dts: exynos: override GPIO keys node by label in Exynos4412 Odroid family Using full paths to extend or override a device tree node is error prone. If there was a typo error, a new node will be created instead of extending the existing node. This will lead to run-time errors that could be hard to detect. A mistyped label on the other hand, will cause a dtc compile error (during build time). Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20201027170947.132725-4-krzk@kernel.org --- arch/arm/boot/dts/exynos4412-odroid-common.dtsi | 2 +- arch/arm/boot/dts/exynos4412-odroidx.dts | 24 ++++++++++++------------ 2 files changed, 13 insertions(+), 13 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi index ab291cec650a..4c77cd4044f2 100644 --- a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi +++ b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi @@ -22,7 +22,7 @@ reg = <0x0204F000 0x1000>; }; - gpio_keys { + gpio_keys: gpio-keys { compatible = "gpio-keys"; pinctrl-names = "default"; pinctrl-0 = <&gpio_power_key>; diff --git a/arch/arm/boot/dts/exynos4412-odroidx.dts b/arch/arm/boot/dts/exynos4412-odroidx.dts index 3ea2a0101e80..68fe88074d1d 100644 --- a/arch/arm/boot/dts/exynos4412-odroidx.dts +++ b/arch/arm/boot/dts/exynos4412-odroidx.dts @@ -36,18 +36,6 @@ }; }; - gpio_keys { - pinctrl-0 = <&gpio_power_key &gpio_home_key>; - - home_key { - gpios = <&gpx2 2 GPIO_ACTIVE_HIGH>; - linux,code = ; - label = "home key"; - debounce-interval = <10>; - wakeup-source; - }; - }; - regulator_p3v3 { compatible = "regulator-fixed"; regulator-name = "p3v3_en"; @@ -76,6 +64,18 @@ phy-names = "hsic0"; }; +&gpio_keys { + pinctrl-0 = <&gpio_power_key &gpio_home_key>; + + home-key { + gpios = <&gpx2 2 GPIO_ACTIVE_HIGH>; + linux,code = ; + label = "home key"; + debounce-interval = <10>; + wakeup-source; + }; +}; + &mshc_0 { vqmmc-supply = <&buck8_reg>; }; -- cgit v1.2.3-59-g8ed1b From 108463f568135255e1bd4847f66d41a2c1665920 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 27 Oct 2020 18:09:39 +0100 Subject: ARM: dts: exynos: adjust node names to DT spec in Exynos4412 boards The Devicetree specification expects device node names to have a generic name, representing the class of a device. Also the convention for node names is to use hyphens, not underscores. No functional changes. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20201027170947.132725-5-krzk@kernel.org --- arch/arm/boot/dts/exynos4412-galaxy-s3.dtsi | 8 ++++---- arch/arm/boot/dts/exynos4412-itop-elite.dts | 2 +- arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi | 2 +- arch/arm/boot/dts/exynos4412-midas.dtsi | 14 +++++++------- arch/arm/boot/dts/exynos4412-n710x.dts | 2 +- arch/arm/boot/dts/exynos4412-odroid-common.dtsi | 8 ++++---- arch/arm/boot/dts/exynos4412-odroidx.dts | 4 ++-- arch/arm/boot/dts/exynos4412-origen.dts | 14 +++++++------- arch/arm/boot/dts/exynos4412-smdk4412.dts | 20 ++++++++++---------- 9 files changed, 37 insertions(+), 37 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/exynos4412-galaxy-s3.dtsi b/arch/arm/boot/dts/exynos4412-galaxy-s3.dtsi index 89ed81fb348d..912c78e9ce8c 100644 --- a/arch/arm/boot/dts/exynos4412-galaxy-s3.dtsi +++ b/arch/arm/boot/dts/exynos4412-galaxy-s3.dtsi @@ -15,7 +15,7 @@ i2c10 = &i2c_cm36651; }; - aat1290 { + led-controller { compatible = "skyworks,aat1290"; flen-gpios = <&gpj1 1 GPIO_ACTIVE_HIGH>; enset-gpios = <&gpj1 2 GPIO_ACTIVE_HIGH>; @@ -60,7 +60,7 @@ #size-cells = <0>; status = "okay"; - ak8975@c { + magnetometer@c { compatible = "asahi-kasei,ak8975"; reg = <0x0c>; gpios = <&gpj0 7 GPIO_ACTIVE_HIGH>; @@ -75,7 +75,7 @@ #address-cells = <1>; #size-cells = <0>; - cm36651@18 { + light-sensor@18 { compatible = "capella,cm36651"; reg = <0x18>; interrupt-parent = <&gpx0>; @@ -133,7 +133,7 @@ }; &i2c_3 { - mms114-touchscreen@48 { + touchscreen@48 { compatible = "melfas,mms114"; reg = <0x48>; interrupt-parent = <&gpm2>; diff --git a/arch/arm/boot/dts/exynos4412-itop-elite.dts b/arch/arm/boot/dts/exynos4412-itop-elite.dts index f6d0a5f5d339..47431307cb3c 100644 --- a/arch/arm/boot/dts/exynos4412-itop-elite.dts +++ b/arch/arm/boot/dts/exynos4412-itop-elite.dts @@ -175,7 +175,7 @@ pinctrl-names = "default"; status = "okay"; - codec: wm8960@1a { + codec: audio-codec@1a { compatible = "wlf,wm8960"; reg = <0x1a>; clocks = <&pmu_system_controller 0>; diff --git a/arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi b/arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi index dfceb155b3a7..4583d342af39 100644 --- a/arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi +++ b/arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi @@ -134,7 +134,7 @@ pinctrl-names = "default"; status = "okay"; - s5m8767: s5m8767-pmic@66 { + s5m8767: pmic@66 { compatible = "samsung,s5m8767-pmic"; reg = <0x66>; diff --git a/arch/arm/boot/dts/exynos4412-midas.dtsi b/arch/arm/boot/dts/exynos4412-midas.dtsi index 96287c6ff359..1721705c280d 100644 --- a/arch/arm/boot/dts/exynos4412-midas.dtsi +++ b/arch/arm/boot/dts/exynos4412-midas.dtsi @@ -171,7 +171,7 @@ #size-cells = <0>; status = "okay"; - max77693@66 { + pmic@66 { compatible = "maxim,max77693"; interrupt-parent = <&gpx1>; interrupts = <5 IRQ_TYPE_EDGE_FALLING>; @@ -220,7 +220,7 @@ #size-cells = <0>; status = "okay"; - max77693-fuel-gauge@36 { + fuel-gauge@36 { compatible = "maxim,max17047"; interrupt-parent = <&gpx2>; interrupts = <3 IRQ_TYPE_EDGE_FALLING>; @@ -550,7 +550,7 @@ pinctrl-names = "default"; status = "okay"; - s5c73m3: s5c73m3@3c { + s5c73m3: image-sensor@3c { compatible = "samsung,s5c73m3"; reg = <0x3c>; xshutdown-gpios = <&gpf1 3 GPIO_ACTIVE_LOW>; /* ISP_RESET */ @@ -577,7 +577,7 @@ pinctrl-0 = <&fimc_is_i2c1>; pinctrl-names = "default"; - s5k6a3@10 { + image-sensor@10 { compatible = "samsung,s5k6a3"; reg = <0x10>; svdda-supply = <&cam_io_reg>; @@ -616,7 +616,7 @@ pinctrl-names = "default"; status = "okay"; - wm1811: wm1811@1a { + wm1811: audio-codec@1a { compatible = "wlf,wm1811"; reg = <0x1a>; clocks = <&pmu_system_controller 0>, @@ -665,7 +665,7 @@ pinctrl-names = "default"; status = "okay"; - max77686: max77686_pmic@9 { + max77686: pmic@9 { compatible = "maxim,max77686"; interrupt-parent = <&gpx0>; interrupts = <7 IRQ_TYPE_NONE>; @@ -1435,7 +1435,7 @@ cs-gpios = <&gpb 5 GPIO_ACTIVE_HIGH>; status = "okay"; - s5c73m3_spi: s5c73m3@0 { + s5c73m3_spi: image-sensor@0 { compatible = "samsung,s5c73m3"; spi-max-frequency = <50000000>; reg = <0>; diff --git a/arch/arm/boot/dts/exynos4412-n710x.dts b/arch/arm/boot/dts/exynos4412-n710x.dts index a47b7f35fc80..c49dbb7847b8 100644 --- a/arch/arm/boot/dts/exynos4412-n710x.dts +++ b/arch/arm/boot/dts/exynos4412-n710x.dts @@ -45,7 +45,7 @@ pinctrl-names = "default"; status = "okay"; - mms152-touchscreen@48 { + touchscreen@48 { compatible = "melfas,mms152"; reg = <0x48>; interrupt-parent = <&gpm2>; diff --git a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi index 4c77cd4044f2..1ca9d8b5f868 100644 --- a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi +++ b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi @@ -27,7 +27,7 @@ pinctrl-names = "default"; pinctrl-0 = <&gpio_power_key>; - power_key { + power-key { gpios = <&gpx1 3 GPIO_ACTIVE_LOW>; linux,code = ; label = "power key"; @@ -172,7 +172,7 @@ }; &pinctrl_1 { - gpio_power_key: power_key { + gpio_power_key: power-key { samsung,pins = "gpx1-3"; samsung,pin-pud = ; }; @@ -267,7 +267,7 @@ samsung,i2c-max-bus-freq = <400000>; status = "okay"; - usb3503: usb3503@8 { + usb3503: usb-hub@8 { compatible = "smsc,usb3503"; reg = <0x08>; @@ -493,7 +493,7 @@ &i2c_1 { status = "okay"; - max98090: max98090@10 { + max98090: audio-codec@10 { compatible = "maxim,max98090"; reg = <0x10>; interrupt-parent = <&gpx0>; diff --git a/arch/arm/boot/dts/exynos4412-odroidx.dts b/arch/arm/boot/dts/exynos4412-odroidx.dts index 68fe88074d1d..46381e9097f4 100644 --- a/arch/arm/boot/dts/exynos4412-odroidx.dts +++ b/arch/arm/boot/dts/exynos4412-odroidx.dts @@ -36,7 +36,7 @@ }; }; - regulator_p3v3 { + regulator-1 { compatible = "regulator-fixed"; regulator-name = "p3v3_en"; regulator-min-microvolt = <3300000>; @@ -81,7 +81,7 @@ }; &pinctrl_1 { - gpio_home_key: home_key { + gpio_home_key: home-key { samsung,pins = "gpx2-2"; samsung,pin-pud = ; }; diff --git a/arch/arm/boot/dts/exynos4412-origen.dts b/arch/arm/boot/dts/exynos4412-origen.dts index c2e793b69e7d..e1f6de53e20e 100644 --- a/arch/arm/boot/dts/exynos4412-origen.dts +++ b/arch/arm/boot/dts/exynos4412-origen.dts @@ -116,7 +116,7 @@ pinctrl-names = "default"; status = "okay"; - s5m8767_pmic@66 { + pmic@66 { compatible = "samsung,s5m8767-pmic"; reg = <0x66>; @@ -453,37 +453,37 @@ pinctrl-names = "default"; status = "okay"; - key_home { + key-home { keypad,row = <0>; keypad,column = <0>; linux,code = ; }; - key_down { + key-down { keypad,row = <0>; keypad,column = <1>; linux,code = ; }; - key_up { + key-up { keypad,row = <1>; keypad,column = <0>; linux,code = ; }; - key_menu { + key-menu { keypad,row = <1>; keypad,column = <1>; linux,code = ; }; - key_back { + key-back { keypad,row = <2>; keypad,column = <0>; linux,code = ; }; - key_enter { + key-enter { keypad,row = <2>; keypad,column = <1>; linux,code = ; diff --git a/arch/arm/boot/dts/exynos4412-smdk4412.dts b/arch/arm/boot/dts/exynos4412-smdk4412.dts index 49971203a8aa..cc99b955af0c 100644 --- a/arch/arm/boot/dts/exynos4412-smdk4412.dts +++ b/arch/arm/boot/dts/exynos4412-smdk4412.dts @@ -71,61 +71,61 @@ pinctrl-names = "default"; status = "okay"; - key_1 { + key-1 { keypad,row = <1>; keypad,column = <3>; linux,code = <2>; }; - key_2 { + key-2 { keypad,row = <1>; keypad,column = <4>; linux,code = <3>; }; - key_3 { + key-3 { keypad,row = <1>; keypad,column = <5>; linux,code = <4>; }; - key_4 { + key-4 { keypad,row = <1>; keypad,column = <6>; linux,code = <5>; }; - key_5 { + key-5 { keypad,row = <1>; keypad,column = <7>; linux,code = <6>; }; - key_A { + key-A { keypad,row = <2>; keypad,column = <6>; linux,code = <30>; }; - key_B { + key-B { keypad,row = <2>; keypad,column = <7>; linux,code = <48>; }; - key_C { + key-C { keypad,row = <0>; keypad,column = <5>; linux,code = <46>; }; - key_D { + key-D { keypad,row = <2>; keypad,column = <5>; linux,code = <32>; }; - key_E { + key-E { keypad,row = <0>; keypad,column = <7>; linux,code = <18>; -- cgit v1.2.3-59-g8ed1b From 2d29d03003017a7a556519d2fbcbbffcee0be319 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 27 Oct 2020 18:09:40 +0100 Subject: ARM: dts: exynos: remove redundant status=okay in Exynos4412 boards New nodes are enabled by default, so status=okay is not needed for them. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20201027170947.132725-6-krzk@kernel.org --- arch/arm/boot/dts/exynos4412-galaxy-s3.dtsi | 1 - arch/arm/boot/dts/exynos4412-midas.dtsi | 3 --- 2 files changed, 4 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/exynos4412-galaxy-s3.dtsi b/arch/arm/boot/dts/exynos4412-galaxy-s3.dtsi index 912c78e9ce8c..c14e37dc3a9b 100644 --- a/arch/arm/boot/dts/exynos4412-galaxy-s3.dtsi +++ b/arch/arm/boot/dts/exynos4412-galaxy-s3.dtsi @@ -58,7 +58,6 @@ i2c-gpio,delay-us = <2>; #address-cells = <1>; #size-cells = <0>; - status = "okay"; magnetometer@c { compatible = "asahi-kasei,ak8975"; diff --git a/arch/arm/boot/dts/exynos4412-midas.dtsi b/arch/arm/boot/dts/exynos4412-midas.dtsi index 1721705c280d..2be1db0b2387 100644 --- a/arch/arm/boot/dts/exynos4412-midas.dtsi +++ b/arch/arm/boot/dts/exynos4412-midas.dtsi @@ -169,7 +169,6 @@ i2c-gpio,delay-us = <2>; #address-cells = <1>; #size-cells = <0>; - status = "okay"; pmic@66 { compatible = "maxim,max77693"; @@ -218,7 +217,6 @@ i2c-gpio,delay-us = <2>; #address-cells = <1>; #size-cells = <0>; - status = "okay"; fuel-gauge@36 { compatible = "maxim,max17047"; @@ -262,7 +260,6 @@ pinctrl-0 = <&i2c_mhl_bus>; pinctrl-names = "default"; - status = "okay"; sii9234: hdmi-bridge@39 { compatible = "sil,sii9234"; -- cgit v1.2.3-59-g8ed1b From 5a1323023fb16c0b04efb24a4c85e5f2663172d8 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 27 Oct 2020 18:09:41 +0100 Subject: ARM: dts: exynos: adjust node names to DT spec in Exynos5250 boards The Devicetree specification expects device node names to have a generic name, representing the class of a device. Also the convention for node names is to use hyphens, not underscores. No functional changes. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20201027170947.132725-7-krzk@kernel.org --- arch/arm/boot/dts/exynos5250-arndale.dts | 6 +++--- arch/arm/boot/dts/exynos5250-smdk5250.dts | 4 ++-- arch/arm/boot/dts/exynos5250-snow-common.dtsi | 4 ++-- arch/arm/boot/dts/exynos5250-snow-rev5.dts | 2 +- arch/arm/boot/dts/exynos5250-snow.dts | 2 +- arch/arm/boot/dts/exynos5250-spring.dts | 2 +- 6 files changed, 10 insertions(+), 10 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts b/arch/arm/boot/dts/exynos5250-arndale.dts index 79546f11af26..a161f6237c7f 100644 --- a/arch/arm/boot/dts/exynos5250-arndale.dts +++ b/arch/arm/boot/dts/exynos5250-arndale.dts @@ -27,7 +27,7 @@ stdout-path = "serial2:115200n8"; }; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; menu { @@ -211,7 +211,7 @@ samsung,i2c-max-bus-freq = <20000>; samsung,i2c-slave-addr = <0x66>; - s5m8767_pmic@66 { + pmic@66 { compatible = "samsung,s5m8767-pmic"; reg = <0x66>; interrupt-parent = <&gpx3>; @@ -511,7 +511,7 @@ &i2c_3 { status = "okay"; - wm1811: codec@1a { + wm1811: audio-codec@1a { compatible = "wlf,wm1811"; reg = <0x1a>; clocks = <&i2s0 CLK_I2S_CDCLK>; diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts index 186790f39e4d..8b5a79a8720c 100644 --- a/arch/arm/boot/dts/exynos5250-smdk5250.dts +++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts @@ -290,7 +290,7 @@ reg = <0x51>; }; - wm8994: wm8994@1a { + wm8994: audio-codec@1a { compatible = "wlf,wm8994"; reg = <0x1a>; @@ -385,7 +385,7 @@ status = "okay"; cs-gpios = <&gpa2 5 GPIO_ACTIVE_HIGH>; - w25q80bw@0 { + flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "w25x80"; diff --git a/arch/arm/boot/dts/exynos5250-snow-common.dtsi b/arch/arm/boot/dts/exynos5250-snow-common.dtsi index c952a615148e..6635f6184051 100644 --- a/arch/arm/boot/dts/exynos5250-snow-common.dtsi +++ b/arch/arm/boot/dts/exynos5250-snow-common.dtsi @@ -217,7 +217,7 @@ }; }; - mmc3_pwrseq: mmc3_pwrseq { + mmc3_pwrseq: mmc3-pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&gpx0 2 GPIO_ACTIVE_LOW>, /* WIFI_RSTn */ <&gpx0 1 GPIO_ACTIVE_LOW>; /* WIFI_EN */ @@ -289,7 +289,7 @@ samsung,i2c-sda-delay = <100>; samsung,i2c-max-bus-freq = <378000>; - max77686: max77686@9 { + max77686: pmic@9 { compatible = "maxim,max77686"; interrupt-parent = <&gpx3>; interrupts = <2 IRQ_TYPE_NONE>; diff --git a/arch/arm/boot/dts/exynos5250-snow-rev5.dts b/arch/arm/boot/dts/exynos5250-snow-rev5.dts index 7cbfc6f1f4b8..0822b778c035 100644 --- a/arch/arm/boot/dts/exynos5250-snow-rev5.dts +++ b/arch/arm/boot/dts/exynos5250-snow-rev5.dts @@ -32,7 +32,7 @@ }; &i2c_7 { - max98090: codec@10 { + max98090: audio-codec@10 { compatible = "maxim,max98090"; reg = <0x10>; interrupts = <4 IRQ_TYPE_NONE>; diff --git a/arch/arm/boot/dts/exynos5250-snow.dts b/arch/arm/boot/dts/exynos5250-snow.dts index 75fdc5e6d423..9946dce54d74 100644 --- a/arch/arm/boot/dts/exynos5250-snow.dts +++ b/arch/arm/boot/dts/exynos5250-snow.dts @@ -30,7 +30,7 @@ }; &i2c_7 { - max98095: codec@11 { + max98095: audio-codec@11 { compatible = "maxim,max98095"; reg = <0x11>; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/exynos5250-spring.dts b/arch/arm/boot/dts/exynos5250-spring.dts index a92ade33779c..9d2baea62d0d 100644 --- a/arch/arm/boot/dts/exynos5250-spring.dts +++ b/arch/arm/boot/dts/exynos5250-spring.dts @@ -105,7 +105,7 @@ samsung,i2c-sda-delay = <100>; samsung,i2c-max-bus-freq = <378000>; - s5m8767-pmic@66 { + pmic@66 { compatible = "samsung,s5m8767-pmic"; reg = <0x66>; interrupt-parent = <&gpx3>; -- cgit v1.2.3-59-g8ed1b From e5fbceb07e3e8e81226b22326756649b127aa78c Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 27 Oct 2020 18:09:42 +0100 Subject: ARM: dts: exynos: adjust node names to DT spec in Odroid XU The Devicetree specification expects device node names to have a generic name, representing the class of a device. Also the convention for node names is to use hyphens, not underscores. No functional changes. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20201027170947.132725-8-krzk@kernel.org --- arch/arm/boot/dts/exynos5410-odroidxu.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/exynos5410-odroidxu.dts b/arch/arm/boot/dts/exynos5410-odroidxu.dts index dd300cea6a20..40cb0727aea1 100644 --- a/arch/arm/boot/dts/exynos5410-odroidxu.dts +++ b/arch/arm/boot/dts/exynos5410-odroidxu.dts @@ -500,7 +500,7 @@ &i2c_1 { status = "okay"; - max98090: max98090@10 { + max98090: audio-codec@10 { compatible = "maxim,max98090"; reg = <0x10>; interrupt-parent = <&gpj3>; -- cgit v1.2.3-59-g8ed1b From 77c91853a65f689cf4198644452fed151a83e8fd Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 27 Oct 2020 18:09:43 +0100 Subject: ARM: dts: exynos: adjust node names to DT spec in Exynos542x boards The Devicetree specification expects device node names to have a generic name, representing the class of a device. Also the convention for node names is to use hyphens, not underscores. No functional changes. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20201027170947.132725-9-krzk@kernel.org --- arch/arm/boot/dts/exynos5420-arndale-octa.dts | 4 ++-- arch/arm/boot/dts/exynos5420-peach-pit.dts | 6 +++--- arch/arm/boot/dts/exynos5420-smdk5420.dts | 2 +- arch/arm/boot/dts/exynos5422-odroid-core.dtsi | 2 +- arch/arm/boot/dts/exynos5422-odroidxu3-audio.dtsi | 2 +- arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi | 4 ++-- arch/arm/boot/dts/exynos5422-odroidxu3.dts | 8 ++++---- arch/arm/boot/dts/exynos5800-peach-pi.dts | 4 ++-- 8 files changed, 16 insertions(+), 16 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/exynos5420-arndale-octa.dts b/arch/arm/boot/dts/exynos5420-arndale-octa.dts index dd7f8385d81e..bf457d0c02eb 100644 --- a/arch/arm/boot/dts/exynos5420-arndale-octa.dts +++ b/arch/arm/boot/dts/exynos5420-arndale-octa.dts @@ -39,7 +39,7 @@ }; }; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; wakeup { @@ -344,7 +344,7 @@ &hsi2c_4 { status = "okay"; - s2mps11_pmic@66 { + pmic@66 { compatible = "samsung,s2mps11-pmic"; reg = <0x66>; diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts b/arch/arm/boot/dts/exynos5420-peach-pit.dts index 2bcbdf8a39bf..315b3dc9c017 100644 --- a/arch/arm/boot/dts/exynos5420-peach-pit.dts +++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts @@ -138,7 +138,7 @@ }; }; - mmc1_pwrseq: mmc1_pwrseq { + mmc1_pwrseq: mmc1-pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&gpx0 0 GPIO_ACTIVE_LOW>; /* WIFI_EN */ clocks = <&max77802 MAX77802_CLK_32K_CP>; @@ -205,7 +205,7 @@ status = "okay"; clock-frequency = <400000>; - max77802: max77802-pmic@9 { + max77802: pmic@9 { compatible = "maxim,max77802"; interrupt-parent = <&gpx3>; interrupts = <1 IRQ_TYPE_NONE>; @@ -615,7 +615,7 @@ status = "okay"; clock-frequency = <400000>; - max98090: codec@10 { + max98090: audio-codec@10 { compatible = "maxim,max98090"; reg = <0x10>; interrupts = <2 IRQ_TYPE_NONE>; diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts b/arch/arm/boot/dts/exynos5420-smdk5420.dts index 4e49d8095b29..d506da9fa661 100644 --- a/arch/arm/boot/dts/exynos5420-smdk5420.dts +++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts @@ -129,7 +129,7 @@ &hsi2c_4 { status = "okay"; - s2mps11_pmic@66 { + pmic@66 { compatible = "samsung,s2mps11-pmic"; reg = <0x66>; diff --git a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi index b1cf9414ce17..25fb6331c75e 100644 --- a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi +++ b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi @@ -503,7 +503,7 @@ &hsi2c_4 { status = "okay"; - s2mps11_pmic@66 { + pmic@66 { compatible = "samsung,s2mps11-pmic"; reg = <0x66>; samsung,s2mps11-acokb-ground; diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3-audio.dtsi b/arch/arm/boot/dts/exynos5422-odroidxu3-audio.dtsi index b5ec4f47eb3a..86b96f9706db 100644 --- a/arch/arm/boot/dts/exynos5422-odroidxu3-audio.dtsi +++ b/arch/arm/boot/dts/exynos5422-odroidxu3-audio.dtsi @@ -40,7 +40,7 @@ &hsi2c_5 { status = "okay"; - max98090: max98090@10 { + max98090: audio-codec@10 { compatible = "maxim,max98090"; reg = <0x10>; interrupt-parent = <&gpx3>; diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi index 5da2d81e3be2..e35af40a55cb 100644 --- a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi +++ b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi @@ -13,12 +13,12 @@ #include "exynos5422-odroid-core.dtsi" / { - gpio_keys { + gpio-keys { compatible = "gpio-keys"; pinctrl-names = "default"; pinctrl-0 = <&power_key>; - power_key { + power-key { /* * The power button (SW2) is connected to the PWRON * pin (active high) of the S2MPS11 PMIC, which acts diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3.dts b/arch/arm/boot/dts/exynos5422-odroidxu3.dts index db0bc17a667b..7c588407f931 100644 --- a/arch/arm/boot/dts/exynos5422-odroidxu3.dts +++ b/arch/arm/boot/dts/exynos5422-odroidxu3.dts @@ -21,28 +21,28 @@ status = "okay"; /* A15 cluster: VDD_ARM */ - ina231@40 { + power-sensor@40 { compatible = "ti,ina231"; reg = <0x40>; shunt-resistor = <10000>; }; /* memory: VDD_MEM */ - ina231@41 { + power-sensor@41 { compatible = "ti,ina231"; reg = <0x41>; shunt-resistor = <10000>; }; /* GPU: VDD_G3D */ - ina231@44 { + power-sensor@44 { compatible = "ti,ina231"; reg = <0x44>; shunt-resistor = <10000>; }; /* A7 cluster: VDD_KFC */ - ina231@45 { + power-sensor@45 { compatible = "ti,ina231"; reg = <0x45>; shunt-resistor = <10000>; diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts b/arch/arm/boot/dts/exynos5800-peach-pi.dts index 60ab0effe474..0ce3443d39a8 100644 --- a/arch/arm/boot/dts/exynos5800-peach-pi.dts +++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts @@ -138,7 +138,7 @@ }; }; - mmc1_pwrseq: mmc1_pwrseq { + mmc1_pwrseq: mmc1-pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&gpx0 0 GPIO_ACTIVE_LOW>; /* WIFI_EN */ clocks = <&max77802 MAX77802_CLK_32K_CP>; @@ -214,7 +214,7 @@ status = "okay"; clock-frequency = <400000>; - max77802: max77802-pmic@9 { + max77802: pmic@9 { compatible = "maxim,max77802"; interrupt-parent = <&gpx3>; interrupts = <1 IRQ_TYPE_NONE>; -- cgit v1.2.3-59-g8ed1b From b04544ac0d1f2a51e0f3234045343aa741d64e7b Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 27 Oct 2020 18:09:44 +0100 Subject: ARM: dts: s5pv210: adjust node names to DT spec The Devicetree specification expects device node names to have a generic name, representing the class of a device. Also the convention for node names is to use hyphens, not underscores. No functional changes. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20201027170947.132725-10-krzk@kernel.org --- arch/arm/boot/dts/s5pv210-aquila.dts | 12 ++++++------ arch/arm/boot/dts/s5pv210-aries.dtsi | 4 ++-- arch/arm/boot/dts/s5pv210-goni.dts | 14 +++++++------- arch/arm/boot/dts/s5pv210-smdkv210.dts | 20 ++++++++++---------- 4 files changed, 25 insertions(+), 25 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/s5pv210-aquila.dts b/arch/arm/boot/dts/s5pv210-aquila.dts index 8e57e5a1f0c5..6423348034b6 100644 --- a/arch/arm/boot/dts/s5pv210-aquila.dts +++ b/arch/arm/boot/dts/s5pv210-aquila.dts @@ -277,37 +277,37 @@ <&keypad_col0>, <&keypad_col1>, <&keypad_col2>; status = "okay"; - key_1 { + key-1 { keypad,row = <0>; keypad,column = <1>; linux,code = ; }; - key_2 { + key-2 { keypad,row = <0>; keypad,column = <2>; linux,code = ; }; - key_3 { + key-3 { keypad,row = <1>; keypad,column = <1>; linux,code = ; }; - key_4 { + key-4 { keypad,row = <1>; keypad,column = <2>; linux,code = ; }; - key_5 { + key-5 { keypad,row = <2>; keypad,column = <1>; linux,code = ; }; - key_6 { + key-6 { keypad,row = <2>; keypad,column = <2>; linux,code = ; diff --git a/arch/arm/boot/dts/s5pv210-aries.dtsi b/arch/arm/boot/dts/s5pv210-aries.dtsi index bd4450dbdcb6..91ecad85abfc 100644 --- a/arch/arm/boot/dts/s5pv210-aries.dtsi +++ b/arch/arm/boot/dts/s5pv210-aries.dtsi @@ -54,7 +54,7 @@ clock-frequency = <32768>; }; - bt_codec: bt_sco { + bt_codec: bt-sco { compatible = "linux,bt-sco"; #sound-dai-cells = <0>; }; @@ -113,7 +113,7 @@ pinctrl-names = "default"; pinctrl-0 = <&sound_i2c_pins>; - wm8994: wm8994@1a { + wm8994: audio-codec@1a { compatible = "wlf,wm8994"; reg = <0x1a>; diff --git a/arch/arm/boot/dts/s5pv210-goni.dts b/arch/arm/boot/dts/s5pv210-goni.dts index ad8d5d2fa32d..5c1e12d39747 100644 --- a/arch/arm/boot/dts/s5pv210-goni.dts +++ b/arch/arm/boot/dts/s5pv210-goni.dts @@ -259,37 +259,37 @@ <&keypad_col0>, <&keypad_col1>, <&keypad_col2>; status = "okay"; - key_1 { + key-1 { keypad,row = <0>; keypad,column = <1>; linux,code = ; }; - key_2 { + key-2 { keypad,row = <0>; keypad,column = <2>; linux,code = ; }; - key_3 { + key-3 { keypad,row = <1>; keypad,column = <1>; linux,code = ; }; - key_4 { + key-4 { keypad,row = <1>; keypad,column = <2>; linux,code = ; }; - key_5 { + key-5 { keypad,row = <2>; keypad,column = <1>; linux,code = ; }; - key_6 { + key-6 { keypad,row = <2>; keypad,column = <2>; linux,code = ; @@ -353,7 +353,7 @@ samsung,i2c-slave-addr = <0x10>; status = "okay"; - tsp@4a { + touchscreen@4a { compatible = "atmel,maxtouch"; reg = <0x4a>; interrupt-parent = <&gpj0>; diff --git a/arch/arm/boot/dts/s5pv210-smdkv210.dts b/arch/arm/boot/dts/s5pv210-smdkv210.dts index 7459e41e8ef1..fbae768d65e2 100644 --- a/arch/arm/boot/dts/s5pv210-smdkv210.dts +++ b/arch/arm/boot/dts/s5pv210-smdkv210.dts @@ -76,61 +76,61 @@ <&keypad_col6>, <&keypad_col7>; status = "okay"; - key_1 { + key-1 { keypad,row = <0>; keypad,column = <3>; linux,code = ; }; - key_2 { + key-2 { keypad,row = <0>; keypad,column = <4>; linux,code = ; }; - key_3 { + key-3 { keypad,row = <0>; keypad,column = <5>; linux,code = ; }; - key_4 { + key-4 { keypad,row = <0>; keypad,column = <6>; linux,code = ; }; - key_5 { + key-5 { keypad,row = <0 >; keypad,column = <7>; linux,code = ; }; - key_6 { + key-6 { keypad,row = <1>; keypad,column = <3>; linux,code = ; }; - key_7 { + key-7 { keypad,row = <1>; keypad,column = <4>; linux,code = ; }; - key_8 { + key-8 { keypad,row = <1>; keypad,column = <5>; linux,code = ; }; - key_9 { + key-9 { keypad,row = <1>; keypad,column = <6>; linux,code = ; }; - key_10 { + key-10 { keypad,row = <1>; keypad,column = <7>; linux,code = ; -- cgit v1.2.3-59-g8ed1b From 036f224ef8f447928bfd3085220c28e158a4e4d6 Mon Sep 17 00:00:00 2001 From: Eugen Hristev Date: Thu, 29 Oct 2020 14:12:23 +0200 Subject: ARM: configs: at91_dt: resync with media changes The media tree Kconfig has changed recently, and a lot of modules were built unintentionally, like the dvb frontends and encoders. Resync the defconfig to build the ISI drivers and tested sensors. Signed-off-by: Eugen Hristev Signed-off-by: Alexandre Belloni Link: https://lore.kernel.org/r/20201029121223.871531-1-eugen.hristev@microchip.com --- arch/arm/configs/at91_dt_defconfig | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/configs/at91_dt_defconfig b/arch/arm/configs/at91_dt_defconfig index 4a0ba2ae1a25..91f0f2c41841 100644 --- a/arch/arm/configs/at91_dt_defconfig +++ b/arch/arm/configs/at91_dt_defconfig @@ -124,9 +124,14 @@ CONFIG_MFD_ATMEL_HLCDC=y CONFIG_REGULATOR=y CONFIG_REGULATOR_FIXED_VOLTAGE=y CONFIG_MEDIA_SUPPORT=y +CONFIG_MEDIA_SUPPORT_FILTER=y +# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set CONFIG_MEDIA_CAMERA_SUPPORT=y +CONFIG_MEDIA_PLATFORM_SUPPORT=y CONFIG_V4L_PLATFORM_DRIVERS=y CONFIG_VIDEO_ATMEL_ISI=y +CONFIG_VIDEO_OV2640=m +CONFIG_VIDEO_MT9V032=m CONFIG_DRM=y CONFIG_DRM_ATMEL_HLCDC=y CONFIG_DRM_PANEL_SIMPLE=y -- cgit v1.2.3-59-g8ed1b From cec12cd8d1861ad9090d0b6c70e14a4b87b1e1b4 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 26 Sep 2020 18:23:01 +0200 Subject: ARM: dts: imx: align watchdog node name with dtschema The dtschema expects watchdog device node name to be "watchdog": arch/arm/boot/dts/imx31-bug.dt.yaml: wdog@53fdc000: $nodename:0: 'wdog@53fdc000' does not match '^watchdog(@.*|-[0-9a-f])?$' Signed-off-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx25.dtsi | 2 +- arch/arm/boot/dts/imx27.dtsi | 2 +- arch/arm/boot/dts/imx31.dtsi | 3 ++- arch/arm/boot/dts/imx35.dtsi | 2 +- arch/arm/boot/dts/imx50.dtsi | 2 +- arch/arm/boot/dts/imx51.dtsi | 4 ++-- arch/arm/boot/dts/imx53.dtsi | 4 ++-- 7 files changed, 10 insertions(+), 9 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx25.dtsi b/arch/arm/boot/dts/imx25.dtsi index 1ab19f1268f8..fdcca82c9986 100644 --- a/arch/arm/boot/dts/imx25.dtsi +++ b/arch/arm/boot/dts/imx25.dtsi @@ -525,7 +525,7 @@ fsl,sdma-ram-script-name = "imx/sdma/sdma-imx25.bin"; }; - wdog@53fdc000 { + watchdog@53fdc000 { compatible = "fsl,imx25-wdt", "fsl,imx21-wdt"; reg = <0x53fdc000 0x4000>; clocks = <&clks 126>; diff --git a/arch/arm/boot/dts/imx27.dtsi b/arch/arm/boot/dts/imx27.dtsi index 7bc132737a37..fd525c3b16fa 100644 --- a/arch/arm/boot/dts/imx27.dtsi +++ b/arch/arm/boot/dts/imx27.dtsi @@ -99,7 +99,7 @@ #dma-channels = <16>; }; - wdog: wdog@10002000 { + wdog: watchdog@10002000 { compatible = "fsl,imx27-wdt", "fsl,imx21-wdt"; reg = <0x10002000 0x1000>; interrupts = <27>; diff --git a/arch/arm/boot/dts/imx31.dtsi b/arch/arm/boot/dts/imx31.dtsi index 45333f7e10ea..948d2a543f8d 100644 --- a/arch/arm/boot/dts/imx31.dtsi +++ b/arch/arm/boot/dts/imx31.dtsi @@ -315,10 +315,11 @@ clock-names = "ref", "ipg"; }; - wdog: wdog@53fdc000 { + wdog: watchdog@53fdc000 { compatible = "fsl,imx31-wdt", "fsl,imx21-wdt"; reg = <0x53fdc000 0x4000>; clocks = <&clks 41>; + interrupts = <55>; }; pwm: pwm@53fe0000 { diff --git a/arch/arm/boot/dts/imx35.dtsi b/arch/arm/boot/dts/imx35.dtsi index aba16252faab..98ccc81ca6d9 100644 --- a/arch/arm/boot/dts/imx35.dtsi +++ b/arch/arm/boot/dts/imx35.dtsi @@ -294,7 +294,7 @@ fsl,sdma-ram-script-name = "imx/sdma/sdma-imx35.bin"; }; - wdog: wdog@53fdc000 { + wdog: watchdog@53fdc000 { compatible = "fsl,imx35-wdt", "fsl,imx21-wdt"; reg = <0x53fdc000 0x4000>; clocks = <&clks 74>; diff --git a/arch/arm/boot/dts/imx50.dtsi b/arch/arm/boot/dts/imx50.dtsi index b6b2e6af9b96..a969f335b240 100644 --- a/arch/arm/boot/dts/imx50.dtsi +++ b/arch/arm/boot/dts/imx50.dtsi @@ -267,7 +267,7 @@ <&iomuxc 20 140 11>; }; - wdog1: wdog@53f98000 { + wdog1: watchdog@53f98000 { compatible = "fsl,imx50-wdt", "fsl,imx21-wdt"; reg = <0x53f98000 0x4000>; interrupts = <58>; diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi index 985e1be03ad6..7ebb46ce9e36 100644 --- a/arch/arm/boot/dts/imx51.dtsi +++ b/arch/arm/boot/dts/imx51.dtsi @@ -370,14 +370,14 @@ status = "disabled"; }; - wdog1: wdog@73f98000 { + wdog1: watchdog@73f98000 { compatible = "fsl,imx51-wdt", "fsl,imx21-wdt"; reg = <0x73f98000 0x4000>; interrupts = <58>; clocks = <&clks IMX5_CLK_DUMMY>; }; - wdog2: wdog@73f9c000 { + wdog2: watchdog@73f9c000 { compatible = "fsl,imx51-wdt", "fsl,imx21-wdt"; reg = <0x73f9c000 0x4000>; interrupts = <59>; diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi index 500eeaa3a27c..000050aeeabe 100644 --- a/arch/arm/boot/dts/imx53.dtsi +++ b/arch/arm/boot/dts/imx53.dtsi @@ -427,14 +427,14 @@ status = "disabled"; }; - wdog1: wdog@53f98000 { + wdog1: watchdog@53f98000 { compatible = "fsl,imx53-wdt", "fsl,imx21-wdt"; reg = <0x53f98000 0x4000>; interrupts = <58>; clocks = <&clks IMX5_CLK_DUMMY>; }; - wdog2: wdog@53f9c000 { + wdog2: watchdog@53f9c000 { compatible = "fsl,imx53-wdt", "fsl,imx21-wdt"; reg = <0x53f9c000 0x4000>; interrupts = <59>; -- cgit v1.2.3-59-g8ed1b From a913e88ffb90800d531feba45025382aabf680bb Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 26 Sep 2020 18:23:02 +0200 Subject: ARM: dts: vf: align watchdog node name with dtschema The dtschema expects watchdog device node name to be "watchdog": arch/arm/boot/dts/vf500-colibri-eval-v3.dt.yaml: wdog@4003e000: $nodename:0: 'wdog@4003e000' does not match '^watchdog(@.*|-[0-9a-f])?$' Signed-off-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- arch/arm/boot/dts/vfxxx.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/vfxxx.dtsi b/arch/arm/boot/dts/vfxxx.dtsi index 2259d11af721..0c8d15fd9253 100644 --- a/arch/arm/boot/dts/vfxxx.dtsi +++ b/arch/arm/boot/dts/vfxxx.dtsi @@ -293,7 +293,7 @@ status = "disabled"; }; - wdoga5: wdog@4003e000 { + wdoga5: watchdog@4003e000 { compatible = "fsl,vf610-wdt", "fsl,imx21-wdt"; reg = <0x4003e000 0x1000>; interrupts = <20 IRQ_TYPE_LEVEL_HIGH>; -- cgit v1.2.3-59-g8ed1b From 2f4ac2d79eb4c09ee6dbda1d2fc2616f281094f9 Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Sun, 27 Sep 2020 15:03:13 +0800 Subject: ARM: imx: Add revision support for i.MX7ULP revision 2.2 On i.MX7ULP revision 2.2, the value is 3, so add support for this revision, otherwise, it will use default revision of 1.0 which is incorrect. Signed-off-by: Anson Huang Reviewed-by: Peng Fan Signed-off-by: Shawn Guo --- arch/arm/mach-imx/mach-imx7ulp.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/mach-imx/mach-imx7ulp.c b/arch/arm/mach-imx/mach-imx7ulp.c index 445256e6a4a0..f6032ea7de8b 100644 --- a/arch/arm/mach-imx/mach-imx7ulp.c +++ b/arch/arm/mach-imx/mach-imx7ulp.c @@ -45,6 +45,9 @@ static void __init imx7ulp_set_revision(void) case 2: imx_set_soc_revision(IMX_CHIP_REVISION_2_1); break; + case 3: + imx_set_soc_revision(IMX_CHIP_REVISION_2_2); + break; default: imx_set_soc_revision(IMX_CHIP_REVISION_1_0); break; -- cgit v1.2.3-59-g8ed1b From 5cad03883f1b96f4736027a5ee56a14e52cdfbc1 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 30 Sep 2020 21:01:39 +0200 Subject: ARM: dts: imx6dl-pico: fix board compatibles There are four flavors of TechNexion PICO-IMX6 boards. They have their own DTSes, even though in Dwarf, Nymph and Pi are exactly the same. They also have their own bindings so adjust the compatibles to match the bindings. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6dl-pico-dwarf.dts | 2 +- arch/arm/boot/dts/imx6dl-pico-hobbit.dts | 2 +- arch/arm/boot/dts/imx6dl-pico-nymph.dts | 2 +- arch/arm/boot/dts/imx6dl-pico-pi.dts | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx6dl-pico-dwarf.dts b/arch/arm/boot/dts/imx6dl-pico-dwarf.dts index 659a8e8714ea..d85b15a8c127 100644 --- a/arch/arm/boot/dts/imx6dl-pico-dwarf.dts +++ b/arch/arm/boot/dts/imx6dl-pico-dwarf.dts @@ -13,5 +13,5 @@ / { model = "TechNexion PICO-IMX6 DualLite/Solo Board and Dwarf baseboard"; - compatible = "technexion,imx6dl-pico", "fsl,imx6dl"; + compatible = "technexion,imx6dl-pico-dwarf", "fsl,imx6dl"; }; diff --git a/arch/arm/boot/dts/imx6dl-pico-hobbit.dts b/arch/arm/boot/dts/imx6dl-pico-hobbit.dts index d7403c5c4337..08fedcbcc91b 100644 --- a/arch/arm/boot/dts/imx6dl-pico-hobbit.dts +++ b/arch/arm/boot/dts/imx6dl-pico-hobbit.dts @@ -13,5 +13,5 @@ / { model = "TechNexion PICO-IMX6 DualLite/Solo Board and Hobbit baseboard"; - compatible = "technexion,imx6dl-pico", "fsl,imx6dl"; + compatible = "technexion,imx6dl-pico-hobbit", "fsl,imx6dl"; }; diff --git a/arch/arm/boot/dts/imx6dl-pico-nymph.dts b/arch/arm/boot/dts/imx6dl-pico-nymph.dts index b282dbf953aa..32ccfc5d41ce 100644 --- a/arch/arm/boot/dts/imx6dl-pico-nymph.dts +++ b/arch/arm/boot/dts/imx6dl-pico-nymph.dts @@ -13,5 +13,5 @@ / { model = "TechNexion PICO-IMX6 DualLite/Solo Board and Nymph baseboard"; - compatible = "technexion,imx6dl-pico", "fsl,imx6dl"; + compatible = "technexion,imx6dl-pico-nymph", "fsl,imx6dl"; }; diff --git a/arch/arm/boot/dts/imx6dl-pico-pi.dts b/arch/arm/boot/dts/imx6dl-pico-pi.dts index b7b1c07f96f3..4590e8ad9a91 100644 --- a/arch/arm/boot/dts/imx6dl-pico-pi.dts +++ b/arch/arm/boot/dts/imx6dl-pico-pi.dts @@ -13,5 +13,5 @@ / { model = "TechNexion PICO-IMX6 DualLite/Solo Board and PI baseboard"; - compatible = "technexion,imx6dl-pico", "fsl,imx6dl"; + compatible = "technexion,imx6dl-pico-pi", "fsl,imx6dl"; }; -- cgit v1.2.3-59-g8ed1b From 8fc8e8129e1aab1c7adfdb7c079eb0aa3d6f066b Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 30 Sep 2020 21:01:42 +0200 Subject: ARM: dts: imx6dl: add compatibles for Aristainetos boards The Aristainetos and Aristainetos2 boards have only SoC compatible. Cc: Heiko Schocher Signed-off-by: Krzysztof Kozlowski Reviewed-by: Heiko Schocher Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6dl-aristainetos2_4.dts | 2 +- arch/arm/boot/dts/imx6dl-aristainetos2_7.dts | 2 +- arch/arm/boot/dts/imx6dl-aristainetos_4.dts | 2 +- arch/arm/boot/dts/imx6dl-aristainetos_7.dts | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx6dl-aristainetos2_4.dts b/arch/arm/boot/dts/imx6dl-aristainetos2_4.dts index b16603f27dce..dfa6f64d43cc 100644 --- a/arch/arm/boot/dts/imx6dl-aristainetos2_4.dts +++ b/arch/arm/boot/dts/imx6dl-aristainetos2_4.dts @@ -46,7 +46,7 @@ / { model = "aristainetos2 i.MX6 Dual Lite Board 4"; - compatible = "fsl,imx6dl"; + compatible = "abb,aristainetos2-imx6dl-4", "fsl,imx6dl"; memory@10000000 { device_type = "memory"; diff --git a/arch/arm/boot/dts/imx6dl-aristainetos2_7.dts b/arch/arm/boot/dts/imx6dl-aristainetos2_7.dts index abb2a1b9ce08..5e15212eaf3a 100644 --- a/arch/arm/boot/dts/imx6dl-aristainetos2_7.dts +++ b/arch/arm/boot/dts/imx6dl-aristainetos2_7.dts @@ -46,7 +46,7 @@ / { model = "aristainetos2 i.MX6 Dual Lite Board 7"; - compatible = "fsl,imx6dl"; + compatible = "abb,aristainetos2-imx6dl-7", "fsl,imx6dl"; memory@10000000 { device_type = "memory"; diff --git a/arch/arm/boot/dts/imx6dl-aristainetos_4.dts b/arch/arm/boot/dts/imx6dl-aristainetos_4.dts index 5c7e85300695..cc861a43eb58 100644 --- a/arch/arm/boot/dts/imx6dl-aristainetos_4.dts +++ b/arch/arm/boot/dts/imx6dl-aristainetos_4.dts @@ -10,7 +10,7 @@ / { model = "aristainetos i.MX6 Dual Lite Board 4"; - compatible = "fsl,imx6dl"; + compatible = "abb,aristainetos-imx6dl-4", "fsl,imx6dl"; backlight { compatible = "pwm-backlight"; diff --git a/arch/arm/boot/dts/imx6dl-aristainetos_7.dts b/arch/arm/boot/dts/imx6dl-aristainetos_7.dts index 4d58cb4436d9..b6cb78870cd5 100644 --- a/arch/arm/boot/dts/imx6dl-aristainetos_7.dts +++ b/arch/arm/boot/dts/imx6dl-aristainetos_7.dts @@ -10,7 +10,7 @@ / { model = "aristainetos i.MX6 Dual Lite Board 7"; - compatible = "fsl,imx6dl"; + compatible = "abb,aristainetos-imx6dl-7", "fsl,imx6dl"; memory@10000000 { device_type = "memory"; -- cgit v1.2.3-59-g8ed1b From ef8b31051a85773fd4d5c3afb78d5f172affb256 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 1 Oct 2020 19:07:58 +0200 Subject: ARM: dts: imx6sl-warp: correct vendor in compatible to Revotics The WaRP board (Wearable Development Platform) was apparently made by Revolution Robotics, Inc (brand: Revotics), not by "Warp". Correct the vendor in compatible to reflect this. The compatibles were not documented in the bindings before. Link: https://revotics.com/warp Signed-off-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6sl-warp.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx6sl-warp.dts b/arch/arm/boot/dts/imx6sl-warp.dts index 408da704c459..9d7c8884892a 100644 --- a/arch/arm/boot/dts/imx6sl-warp.dts +++ b/arch/arm/boot/dts/imx6sl-warp.dts @@ -51,8 +51,8 @@ #include "imx6sl.dtsi" / { - model = "WaRP Board"; - compatible = "warp,imx6sl-warp", "fsl,imx6sl"; + model = "Revotics WaRP Board"; + compatible = "revotics,imx6sl-warp", "fsl,imx6sl"; memory@80000000 { device_type = "memory"; -- cgit v1.2.3-59-g8ed1b From a486d18c0a14649bc86052431b9f3eb88bcb0e15 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 1 Oct 2020 19:07:59 +0200 Subject: ARM: dts: imx7s-warp: correct vendor in compatible to Element14 The WaRP7 board (Wearable Development Platform) was apparently made by Element14, not by "Warp". Correct the vendor in compatible to reflect this. The compatibles were not documented in the bindings before. Link: https://www.element14.com/community/docs/DOC-79058 Signed-off-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx7s-warp.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx7s-warp.dts b/arch/arm/boot/dts/imx7s-warp.dts index d6b4888fa686..569bbd84e371 100644 --- a/arch/arm/boot/dts/imx7s-warp.dts +++ b/arch/arm/boot/dts/imx7s-warp.dts @@ -10,8 +10,8 @@ #include "imx7s.dtsi" / { - model = "Warp i.MX7 Board"; - compatible = "warp,imx7s-warp", "fsl,imx7s"; + model = "Element14 Warp i.MX7 Board"; + compatible = "element14,imx7s-warp", "fsl,imx7s"; memory@80000000 { device_type = "memory"; -- cgit v1.2.3-59-g8ed1b From 97f1dd5ba28f45f1fd41285dc713c7cf391f2cd7 Mon Sep 17 00:00:00 2001 From: Alexander Dahl Date: Mon, 5 Oct 2020 22:34:47 +0200 Subject: ARM: dts: imx: Fix schema warnings for pwm-leds The node names for devices using the pwm-leds driver follow a certain naming scheme (now). Parent node name is not enforced, but recommended by DT project. DTC arch/arm/boot/dts/imx53-ppd.dt.yaml CHECK arch/arm/boot/dts/imx53-ppd.dt.yaml arch/arm/boot/dts/imx53-ppd.dt.yaml: leds-brightness: 'alarm-brightness' does not match any of the regexes: '^led(-[0-9a-f]+)?$', 'pinctrl-[0-9]+' From schema: Documentation/devicetree/bindings/leds/leds-pwm.yaml DTC arch/arm/boot/dts/imx6dl-cubox-i.dt.yaml CHECK arch/arm/boot/dts/imx6dl-cubox-i.dt.yaml arch/arm/boot/dts/imx6dl-cubox-i.dt.yaml: pwmleds: 'front' does not match any of the regexes: '^led(-[0-9a-f]+)?$', 'pinctrl-[0-9]+' From schema: Documentation/devicetree/bindings/leds/leds-pwm.yaml DTC arch/arm/boot/dts/imx6dl-cubox-i-emmc-som-v15.dt.yaml CHECK arch/arm/boot/dts/imx6dl-cubox-i-emmc-som-v15.dt.yaml arch/arm/boot/dts/imx6dl-cubox-i-emmc-som-v15.dt.yaml: pwmleds: 'front' does not match any of the regexes: '^led(-[0-9a-f]+)?$', 'pinctrl-[0-9]+' From schema: Documentation/devicetree/bindings/leds/leds-pwm.yaml DTC arch/arm/boot/dts/imx6dl-cubox-i-som-v15.dt.yaml CHECK arch/arm/boot/dts/imx6dl-cubox-i-som-v15.dt.yaml arch/arm/boot/dts/imx6dl-cubox-i-som-v15.dt.yaml: pwmleds: 'front' does not match any of the regexes: '^led(-[0-9a-f]+)?$', 'pinctrl-[0-9]+' From schema: Documentation/devicetree/bindings/leds/leds-pwm.yaml DTC arch/arm/boot/dts/imx6sx-softing-vining-2000.dt.yaml CHECK arch/arm/boot/dts/imx6sx-softing-vining-2000.dt.yaml arch/arm/boot/dts/imx6sx-softing-vining-2000.dt.yaml: pwmleds: 'blue', 'green', 'red' do not match any of the regexes: '^led(-[0-9a-f]+)?$', 'pinctrl-[0-9]+' From schema: Documentation/devicetree/bindings/leds/leds-pwm.yaml Signed-off-by: Alexander Dahl Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx53-ppd.dts | 15 ++++++++------- arch/arm/boot/dts/imx6qdl-cubox-i.dtsi | 4 ++-- arch/arm/boot/dts/imx6sx-softing-vining-2000.dts | 8 ++++---- 3 files changed, 14 insertions(+), 13 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx53-ppd.dts b/arch/arm/boot/dts/imx53-ppd.dts index f7dcdf96e5c0..b480614efb30 100644 --- a/arch/arm/boot/dts/imx53-ppd.dts +++ b/arch/arm/boot/dts/imx53-ppd.dts @@ -176,36 +176,37 @@ power-supply = <®_3v3_lcd>; }; - leds-brightness { + led-controller-1 { compatible = "pwm-leds"; - alarm-brightness { + led-1 { + label = "alarm-brightness"; pwms = <&pwm1 0 100000>; max-brightness = <255>; }; }; - leds { + led-controller-2 { compatible = "gpio-leds"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_alarmled_pins>; - alarm1 { + led-2 { label = "alarm:red"; gpios = <&gpio7 3 GPIO_ACTIVE_HIGH>; }; - alarm2 { + led-3 { label = "alarm:yellow"; gpios = <&gpio7 7 GPIO_ACTIVE_HIGH>; }; - alarm3 { + led-4 { label = "alarm:blue"; gpios = <&gpio7 8 GPIO_ACTIVE_HIGH>; }; - alarm4 { + led-5 { label = "alarm:silenced"; gpios = <&gpio7 13 GPIO_ACTIVE_HIGH>; }; diff --git a/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi b/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi index 67042793b0ca..1e530d892b76 100644 --- a/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi +++ b/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi @@ -55,12 +55,12 @@ pinctrl-0 = <&pinctrl_cubox_i_ir>; }; - pwmleds { + led-controller { compatible = "pwm-leds"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_cubox_i_pwm1>; - front { + led-1 { active-low; label = "imx6:red:front"; max-brightness = <248>; diff --git a/arch/arm/boot/dts/imx6sx-softing-vining-2000.dts b/arch/arm/boot/dts/imx6sx-softing-vining-2000.dts index 5547916870c7..b9a1401e6c6d 100644 --- a/arch/arm/boot/dts/imx6sx-softing-vining-2000.dts +++ b/arch/arm/boot/dts/imx6sx-softing-vining-2000.dts @@ -40,22 +40,22 @@ regulator-max-microvolt = <3300000>; }; - pwmleds { + led-controller { compatible = "pwm-leds"; - red { + led-1 { label = "red"; max-brightness = <255>; pwms = <&pwm6 0 50000>; }; - green { + led-2 { label = "green"; max-brightness = <255>; pwms = <&pwm2 0 50000>; }; - blue { + led-3 { label = "blue"; max-brightness = <255>; pwms = <&pwm1 0 50000>; -- cgit v1.2.3-59-g8ed1b From 3e3f354bc383a052cde431d8f051efbf896f260b Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Thu, 24 Sep 2020 20:25:46 +0200 Subject: ARM: remove ebsa110 platform Russell said that he is no longer using this machine, and it seems that nobody else has in a long time, so it's time to say goodbye to it. As this is the last platform using CONFIG_ARCH_USES_GETTIMEOFFSET, there are some follow-up patches to remove that as well. Acked-by: Russell King Signed-off-by: Arnd Bergmann --- MAINTAINERS | 8 - arch/arm/Kconfig | 24 +- arch/arm/Kconfig.debug | 6 +- arch/arm/Makefile | 8 - arch/arm/configs/ebsa110_defconfig | 74 ---- arch/arm/kernel/Makefile | 6 +- arch/arm/mach-ebsa110/Makefile | 8 - arch/arm/mach-ebsa110/Makefile.boot | 5 - arch/arm/mach-ebsa110/core.c | 323 ----------------- arch/arm/mach-ebsa110/core.h | 38 -- arch/arm/mach-ebsa110/include/mach/entry-macro.S | 33 -- arch/arm/mach-ebsa110/include/mach/hardware.h | 21 -- arch/arm/mach-ebsa110/include/mach/io.h | 89 ----- arch/arm/mach-ebsa110/include/mach/irqs.h | 17 - arch/arm/mach-ebsa110/include/mach/memory.h | 22 -- arch/arm/mach-ebsa110/include/mach/uncompress.h | 41 --- arch/arm/mach-ebsa110/io.c | 440 ----------------------- arch/arm/mach-ebsa110/leds.c | 71 ---- drivers/watchdog/Kconfig | 2 +- 19 files changed, 7 insertions(+), 1229 deletions(-) delete mode 100644 arch/arm/configs/ebsa110_defconfig delete mode 100644 arch/arm/mach-ebsa110/Makefile delete mode 100644 arch/arm/mach-ebsa110/Makefile.boot delete mode 100644 arch/arm/mach-ebsa110/core.c delete mode 100644 arch/arm/mach-ebsa110/core.h delete mode 100644 arch/arm/mach-ebsa110/include/mach/entry-macro.S delete mode 100644 arch/arm/mach-ebsa110/include/mach/hardware.h delete mode 100644 arch/arm/mach-ebsa110/include/mach/io.h delete mode 100644 arch/arm/mach-ebsa110/include/mach/irqs.h delete mode 100644 arch/arm/mach-ebsa110/include/mach/memory.h delete mode 100644 arch/arm/mach-ebsa110/include/mach/uncompress.h delete mode 100644 arch/arm/mach-ebsa110/io.c delete mode 100644 arch/arm/mach-ebsa110/leds.c (limited to 'arch/arm') diff --git a/MAINTAINERS b/MAINTAINERS index e73636b75f29..12c6a9028ed2 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1789,14 +1789,6 @@ F: drivers/firmware/turris-mox-rwtm.c F: drivers/gpio/gpio-moxtet.c F: include/linux/moxtet.h -ARM/EBSA110 MACHINE SUPPORT -M: Russell King -L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) -S: Maintained -W: http://www.armlinux.org.uk/ -F: arch/arm/mach-ebsa110/ -F: drivers/net/ethernet/amd/am79c961a.* - ARM/ENERGY MICRO (SILICON LABS) EFM32 SUPPORT M: Uwe Kleine-König R: Pengutronix Kernel Team diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index fe2f17eb2b50..31391147315d 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -267,8 +267,7 @@ config PHYS_OFFSET hex "Physical address of main memory" if MMU depends on !ARM_PATCH_PHYS_VIRT default DRAM_BASE if !MMU - default 0x00000000 if ARCH_EBSA110 || \ - ARCH_FOOTBRIDGE + default 0x00000000 if ARCH_FOOTBRIDGE default 0x10000000 if ARCH_OMAP1 || ARCH_RPC default 0x20000000 if ARCH_S5PV210 default 0xc0000000 if ARCH_SA1100 @@ -342,20 +341,6 @@ config ARM_SINGLE_ARMV7M select SPARSE_IRQ select USE_OF -config ARCH_EBSA110 - bool "EBSA-110" - select ARCH_USES_GETTIMEOFFSET - select CPU_SA110 - select ISA - select NEED_MACH_IO_H - select NEED_MACH_MEMORY_H - select NO_IOPORT_MAP - help - This is an evaluation board for the StrongARM processor available - from Digital. It has limited hardware on-board, including an - Ethernet interface, two PCMCIA sockets, two serial ports and a - parallel port. - config ARCH_EP93XX bool "EP93xx-based" select ARCH_SPARSEMEM_ENABLE @@ -1371,7 +1356,6 @@ config ARCH_NR_GPIO config HZ_FIXED int - default 200 if ARCH_EBSA110 default 128 if SOC_AT91RM9200 default 0 @@ -1587,9 +1571,7 @@ config FORCE_MAX_ZONEORDER a value of 11 means that the largest free memory block is 2^10 pages. config ALIGNMENT_TRAP - bool - depends on CPU_CP15_MMU - default y if !ARCH_EBSA110 + def_bool CPU_CP15_MMU select HAVE_PROC_CPU if PROC_FS help ARM processors cannot fetch/store information which is not @@ -1784,7 +1766,7 @@ config CMDLINE string "Default kernel command string" default "" help - On some architectures (EBSA110 and CATS), there is currently no way + On some architectures (e.g. CATS), there is currently no way for the boot loader to pass arguments to the kernel. For these architectures, you should supply some command-line options at build time by entering them here. As a minimum, you should specify the diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug index 8986a91a6f31..4ff04201a8cc 100644 --- a/arch/arm/Kconfig.debug +++ b/arch/arm/Kconfig.debug @@ -1567,7 +1567,7 @@ config DEBUG_SIRFSOC_UART config DEBUG_UART_FLOW_CONTROL bool "Enable flow control (CTS) for the debug UART" depends on DEBUG_LL - default y if ARCH_EBSA110 || DEBUG_FOOTBRIDGE_COM1 || DEBUG_GEMINI || ARCH_RPC + default y if DEBUG_FOOTBRIDGE_COM1 || DEBUG_GEMINI || ARCH_RPC help Some UART ports are connected to terminals that will use modem control signals to indicate whether they are ready to receive text. @@ -1639,7 +1639,7 @@ config DEBUG_UART_PL01X # Compatibility options for 8250 config DEBUG_UART_8250 - def_bool ARCH_EBSA110 || ARCH_IOP32X || ARCH_IXP4XX || ARCH_RPC + def_bool ARCH_IOP32X || ARCH_IXP4XX || ARCH_RPC config DEBUG_UART_PHYS hex "Physical base address of debug UART" @@ -1743,7 +1743,6 @@ config DEBUG_UART_PHYS default 0xe8008000 if DEBUG_R7S72100_SCIF2 || DEBUG_R7S9210_SCIF2 default 0xe8009000 if DEBUG_R7S9210_SCIF4 default 0xf0000000 if DEBUG_DIGICOLOR_UA0 - default 0xf0000be0 if ARCH_EBSA110 default 0xf1012000 if DEBUG_MVEBU_UART0_ALTERNATE default 0xf1012100 if DEBUG_MVEBU_UART1_ALTERNATE default 0xf7fc9000 if DEBUG_BERLIN_UART @@ -1790,7 +1789,6 @@ config DEBUG_UART_VIRT default 0xc8821000 if DEBUG_RV1108_UART1 default 0xc8912000 if DEBUG_RV1108_UART0 default 0xe0010fe0 if ARCH_RPC - default 0xf0000be0 if ARCH_EBSA110 default 0xf0010000 if DEBUG_ASM9260_UART default 0xf0100000 if DEBUG_DIGICOLOR_UA0 default 0xf01fb000 if DEBUG_NOMADIK_UART diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 4d76eab2b22d..64999d94ed1b 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -172,7 +172,6 @@ machine-$(CONFIG_ARCH_CNS3XXX) += cns3xxx machine-$(CONFIG_ARCH_DAVINCI) += davinci machine-$(CONFIG_ARCH_DIGICOLOR) += digicolor machine-$(CONFIG_ARCH_DOVE) += dove -machine-$(CONFIG_ARCH_EBSA110) += ebsa110 machine-$(CONFIG_ARCH_EFM32) += efm32 machine-$(CONFIG_ARCH_EP93XX) += ep93xx machine-$(CONFIG_ARCH_EXYNOS) += exynos @@ -239,13 +238,6 @@ plat-$(CONFIG_PLAT_ORION) += orion plat-$(CONFIG_PLAT_PXA) += pxa plat-$(CONFIG_PLAT_VERSATILE) += versatile -ifeq ($(CONFIG_ARCH_EBSA110),y) -# This is what happens if you forget the IOCS16 line. -# PCMCIA cards stop working. -CFLAGS_3c589_cs.o :=-DISA_SIXTEEN_BIT_PERIPHERAL -export CFLAGS_3c589_cs.o -endif - # The byte offset of the kernel image in RAM from the start of RAM. TEXT_OFFSET := $(textofs-y) diff --git a/arch/arm/configs/ebsa110_defconfig b/arch/arm/configs/ebsa110_defconfig deleted file mode 100644 index 731a22a55f4e..000000000000 --- a/arch/arm/configs/ebsa110_defconfig +++ /dev/null @@ -1,74 +0,0 @@ -CONFIG_SYSVIPC=y -CONFIG_BSD_PROCESS_ACCT=y -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_EXPERT=y -CONFIG_MODULES=y -CONFIG_ARCH_EBSA110=y -CONFIG_PCCARD=m -CONFIG_I82365=m -CONFIG_LEDS=y -CONFIG_ZBOOT_ROM_TEXT=0x0 -CONFIG_ZBOOT_ROM_BSS=0x0 -CONFIG_CMDLINE="root=/dev/nfs rw mem=16M console=ttyS1,38400n8" -CONFIG_FPE_NWFPE=y -CONFIG_FPE_FASTFPE=y -CONFIG_BINFMT_AOUT=y -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_INET=y -CONFIG_IP_MULTICAST=y -CONFIG_IP_ADVANCED_ROUTER=y -CONFIG_IP_MULTIPLE_TABLES=y -CONFIG_IP_ROUTE_VERBOSE=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_BOOTP=y -CONFIG_SYN_COOKIES=y -CONFIG_IPV6=y -CONFIG_NETFILTER=y -CONFIG_IP_NF_IPTABLES=y -CONFIG_IP_NF_MATCH_ECN=y -CONFIG_IP_NF_MATCH_TTL=y -CONFIG_IP_NF_FILTER=y -CONFIG_IP_NF_TARGET_REJECT=y -CONFIG_IP_NF_TARGET_LOG=y -CONFIG_IP_NF_MANGLE=y -CONFIG_IP_NF_TARGET_ECN=y -CONFIG_IP6_NF_IPTABLES=y -CONFIG_IP6_NF_MATCH_FRAG=y -CONFIG_IP6_NF_MATCH_OPTS=y -CONFIG_IP6_NF_MATCH_HL=y -CONFIG_IP6_NF_MATCH_RT=y -CONFIG_IP6_NF_FILTER=y -CONFIG_IP6_NF_MANGLE=y -CONFIG_FW_LOADER=m -CONFIG_PARPORT=y -CONFIG_PARPORT_PC=y -CONFIG_PARPORT_PC_FIFO=y -CONFIG_PARPORT_1284=y -CONFIG_BLK_DEV_RAM=y -CONFIG_NETDEVICES=y -CONFIG_NET_ETHERNET=y -CONFIG_ARM_AM79C961A=y -CONFIG_NET_PCMCIA=y -CONFIG_PCMCIA_PCNET=m -CONFIG_PPP=m -CONFIG_PPP_ASYNC=m -CONFIG_PPP_DEFLATE=m -CONFIG_PPP_BSDCOMP=m -# CONFIG_INPUT is not set -# CONFIG_SERIO is not set -# CONFIG_VT is not set -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_8250_CS=m -CONFIG_PRINTER=m -CONFIG_WATCHDOG=y -CONFIG_SOFT_WATCHDOG=y -CONFIG_AUTOFS4_FS=y -CONFIG_MINIX_FS=y -CONFIG_NFS_FS=y -CONFIG_NFS_V3=y -CONFIG_ROOT_NFS=y -CONFIG_PARTITION_ADVANCED=y -# CONFIG_MSDOS_PARTITION is not set diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile index 89e5d864e923..09e67cb02b20 100644 --- a/arch/arm/kernel/Makefile +++ b/arch/arm/kernel/Makefile @@ -17,7 +17,7 @@ CFLAGS_REMOVE_return_address.o = -pg # Object file lists. obj-y := elf.o entry-common.o irq.o opcodes.o \ - process.o ptrace.o reboot.o \ + process.o ptrace.o reboot.o io.o \ setup.o signal.o sigreturn_codes.o \ stacktrace.o sys_arm.o time.o traps.o @@ -83,10 +83,6 @@ AFLAGS_iwmmxt.o := -Wa,-mcpu=iwmmxt obj-$(CONFIG_ARM_CPU_TOPOLOGY) += topology.o obj-$(CONFIG_VDSO) += vdso.o obj-$(CONFIG_EFI) += efi.o - -ifneq ($(CONFIG_ARCH_EBSA110),y) - obj-y += io.o -endif obj-$(CONFIG_PARAVIRT) += paravirt.o head-y := head$(MMUEXT).o diff --git a/arch/arm/mach-ebsa110/Makefile b/arch/arm/mach-ebsa110/Makefile deleted file mode 100644 index 296541315d25..000000000000 --- a/arch/arm/mach-ebsa110/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only -# -# Makefile for the linux kernel. -# - -# Object file lists. - -obj-y := core.o io.o leds.o diff --git a/arch/arm/mach-ebsa110/Makefile.boot b/arch/arm/mach-ebsa110/Makefile.boot deleted file mode 100644 index e7e98937c71b..000000000000 --- a/arch/arm/mach-ebsa110/Makefile.boot +++ /dev/null @@ -1,5 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only - zreladdr-y += 0x00008000 -params_phys-y := 0x00000400 -initrd_phys-y := 0x00800000 - diff --git a/arch/arm/mach-ebsa110/core.c b/arch/arm/mach-ebsa110/core.c deleted file mode 100644 index 5960e3dfd2bf..000000000000 --- a/arch/arm/mach-ebsa110/core.c +++ /dev/null @@ -1,323 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * linux/arch/arm/mach-ebsa110/core.c - * - * Copyright (C) 1998-2001 Russell King - * - * Extra MM routines for the EBSA-110 architecture - */ -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#include - -#include "core.h" - -static void ebsa110_mask_irq(struct irq_data *d) -{ - __raw_writeb(1 << d->irq, IRQ_MCLR); -} - -static void ebsa110_unmask_irq(struct irq_data *d) -{ - __raw_writeb(1 << d->irq, IRQ_MSET); -} - -static struct irq_chip ebsa110_irq_chip = { - .irq_ack = ebsa110_mask_irq, - .irq_mask = ebsa110_mask_irq, - .irq_unmask = ebsa110_unmask_irq, -}; - -static void __init ebsa110_init_irq(void) -{ - unsigned long flags; - unsigned int irq; - - local_irq_save(flags); - __raw_writeb(0xff, IRQ_MCLR); - __raw_writeb(0x55, IRQ_MSET); - __raw_writeb(0x00, IRQ_MSET); - if (__raw_readb(IRQ_MASK) != 0x55) - while (1); - __raw_writeb(0xff, IRQ_MCLR); /* clear all interrupt enables */ - local_irq_restore(flags); - - for (irq = 0; irq < NR_IRQS; irq++) { - irq_set_chip_and_handler(irq, &ebsa110_irq_chip, - handle_level_irq); - irq_clear_status_flags(irq, IRQ_NOREQUEST | IRQ_NOPROBE); - } -} - -static struct map_desc ebsa110_io_desc[] __initdata = { - /* - * sparse external-decode ISAIO space - */ - { /* IRQ_STAT/IRQ_MCLR */ - .virtual = (unsigned long)IRQ_STAT, - .pfn = __phys_to_pfn(TRICK4_PHYS), - .length = TRICK4_SIZE, - .type = MT_DEVICE - }, { /* IRQ_MASK/IRQ_MSET */ - .virtual = (unsigned long)IRQ_MASK, - .pfn = __phys_to_pfn(TRICK3_PHYS), - .length = TRICK3_SIZE, - .type = MT_DEVICE - }, { /* SOFT_BASE */ - .virtual = (unsigned long)SOFT_BASE, - .pfn = __phys_to_pfn(TRICK1_PHYS), - .length = TRICK1_SIZE, - .type = MT_DEVICE - }, { /* PIT_BASE */ - .virtual = (unsigned long)PIT_BASE, - .pfn = __phys_to_pfn(TRICK0_PHYS), - .length = TRICK0_SIZE, - .type = MT_DEVICE - }, - - /* - * self-decode ISAIO space - */ - { - .virtual = ISAIO_BASE, - .pfn = __phys_to_pfn(ISAIO_PHYS), - .length = ISAIO_SIZE, - .type = MT_DEVICE - }, { - .virtual = ISAMEM_BASE, - .pfn = __phys_to_pfn(ISAMEM_PHYS), - .length = ISAMEM_SIZE, - .type = MT_DEVICE - } -}; - -static void __init ebsa110_map_io(void) -{ - iotable_init(ebsa110_io_desc, ARRAY_SIZE(ebsa110_io_desc)); -} - -static void __iomem *ebsa110_ioremap_caller(phys_addr_t cookie, size_t size, - unsigned int flags, void *caller) -{ - return (void __iomem *)cookie; -} - -static void ebsa110_iounmap(volatile void __iomem *io_addr) -{} - -static void __init ebsa110_init_early(void) -{ - arch_ioremap_caller = ebsa110_ioremap_caller; - arch_iounmap = ebsa110_iounmap; -} - -#define PIT_CTRL (PIT_BASE + 0x0d) -#define PIT_T2 (PIT_BASE + 0x09) -#define PIT_T1 (PIT_BASE + 0x05) -#define PIT_T0 (PIT_BASE + 0x01) - -/* - * This is the rate at which your MCLK signal toggles (in Hz) - * This was measured on a 10 digit frequency counter sampling - * over 1 second. - */ -#define MCLK 47894000 - -/* - * This is the rate at which the PIT timers get clocked - */ -#define CLKBY7 (MCLK / 7) - -/* - * This is the counter value. We tick at 200Hz on this platform. - */ -#define COUNT ((CLKBY7 + (HZ / 2)) / HZ) - -/* - * Get the time offset from the system PIT. Note that if we have missed an - * interrupt, then the PIT counter will roll over (ie, be negative). - * This actually works out to be convenient. - */ -static u32 ebsa110_gettimeoffset(void) -{ - unsigned long offset, count; - - __raw_writeb(0x40, PIT_CTRL); - count = __raw_readb(PIT_T1); - count |= __raw_readb(PIT_T1) << 8; - - /* - * If count > COUNT, make the number negative. - */ - if (count > COUNT) - count |= 0xffff0000; - - offset = COUNT; - offset -= count; - - /* - * `offset' is in units of timer counts. Convert - * offset to units of microseconds. - */ - offset = offset * (1000000 / HZ) / COUNT; - - return offset * 1000; -} - -static irqreturn_t -ebsa110_timer_interrupt(int irq, void *dev_id) -{ - u32 count; - - /* latch and read timer 1 */ - __raw_writeb(0x40, PIT_CTRL); - count = __raw_readb(PIT_T1); - count |= __raw_readb(PIT_T1) << 8; - - count += COUNT; - - __raw_writeb(count & 0xff, PIT_T1); - __raw_writeb(count >> 8, PIT_T1); - - timer_tick(); - - return IRQ_HANDLED; -} - -/* - * Set up timer interrupt. - */ -void __init ebsa110_timer_init(void) -{ - int irq = IRQ_EBSA110_TIMER0; - - arch_gettimeoffset = ebsa110_gettimeoffset; - - /* - * Timer 1, mode 2, LSB/MSB - */ - __raw_writeb(0x70, PIT_CTRL); - __raw_writeb(COUNT & 0xff, PIT_T1); - __raw_writeb(COUNT >> 8, PIT_T1); - - if (request_irq(irq, ebsa110_timer_interrupt, IRQF_TIMER | IRQF_IRQPOLL, - "EBSA110 Timer Tick", NULL)) - pr_err("Failed to request irq %d (EBSA110 Timer Tick)\n", irq); -} - -static struct plat_serial8250_port serial_platform_data[] = { - { - .iobase = 0x3f8, - .irq = 1, - .uartclk = 1843200, - .regshift = 0, - .iotype = UPIO_PORT, - .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, - }, - { - .iobase = 0x2f8, - .irq = 2, - .uartclk = 1843200, - .regshift = 0, - .iotype = UPIO_PORT, - .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, - }, - { }, -}; - -static struct platform_device serial_device = { - .name = "serial8250", - .id = PLAT8250_DEV_PLATFORM, - .dev = { - .platform_data = serial_platform_data, - }, -}; - -static struct resource am79c961_resources[] = { - { - .start = 0x220, - .end = 0x238, - .flags = IORESOURCE_IO, - }, { - .start = IRQ_EBSA110_ETHERNET, - .end = IRQ_EBSA110_ETHERNET, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device am79c961_device = { - .name = "am79c961", - .id = -1, - .num_resources = ARRAY_SIZE(am79c961_resources), - .resource = am79c961_resources, -}; - -static struct platform_device *ebsa110_devices[] = { - &serial_device, - &am79c961_device, -}; - -/* - * EBSA110 idling methodology: - * - * We can not execute the "wait for interrupt" instruction since that - * will stop our MCLK signal (which provides the clock for the glue - * logic, and therefore the timer interrupt). - * - * Instead, we spin, polling the IRQ_STAT register for the occurrence - * of any interrupt with core clock down to the memory clock. - */ -static void ebsa110_idle(void) -{ - const char *irq_stat = (char *)0xff000000; - - /* disable clock switching */ - asm volatile ("mcr p15, 0, ip, c15, c2, 2" : : : "cc"); - - /* wait for an interrupt to occur */ - while (!*irq_stat); - - /* enable clock switching */ - asm volatile ("mcr p15, 0, ip, c15, c1, 2" : : : "cc"); -} - -static int __init ebsa110_init(void) -{ - arm_pm_idle = ebsa110_idle; - return platform_add_devices(ebsa110_devices, ARRAY_SIZE(ebsa110_devices)); -} - -arch_initcall(ebsa110_init); - -static void ebsa110_restart(enum reboot_mode mode, const char *cmd) -{ - soft_restart(0x80000000); -} - -MACHINE_START(EBSA110, "EBSA110") - /* Maintainer: Russell King */ - .atag_offset = 0x400, - .reserve_lp0 = 1, - .reserve_lp2 = 1, - .map_io = ebsa110_map_io, - .init_early = ebsa110_init_early, - .init_irq = ebsa110_init_irq, - .init_time = ebsa110_timer_init, - .restart = ebsa110_restart, -MACHINE_END diff --git a/arch/arm/mach-ebsa110/core.h b/arch/arm/mach-ebsa110/core.h deleted file mode 100644 index 47acc610b6b4..000000000000 --- a/arch/arm/mach-ebsa110/core.h +++ /dev/null @@ -1,38 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (C) 1996-2000 Russell King. - * - * This file contains the core hardware definitions of the EBSA-110. - */ -#ifndef CORE_H -#define CORE_H - -/* Physical addresses/sizes */ -#define ISAMEM_PHYS 0xe0000000 -#define ISAMEM_SIZE 0x10000000 - -#define ISAIO_PHYS 0xf0000000 -#define ISAIO_SIZE PGDIR_SIZE - -#define TRICK0_PHYS 0xf2000000 -#define TRICK0_SIZE PGDIR_SIZE -#define TRICK1_PHYS 0xf2400000 -#define TRICK1_SIZE PGDIR_SIZE -#define TRICK2_PHYS 0xf2800000 -#define TRICK3_PHYS 0xf2c00000 -#define TRICK3_SIZE PGDIR_SIZE -#define TRICK4_PHYS 0xf3000000 -#define TRICK4_SIZE PGDIR_SIZE -#define TRICK5_PHYS 0xf3400000 -#define TRICK6_PHYS 0xf3800000 -#define TRICK7_PHYS 0xf3c00000 - -/* Virtual addresses */ -#define PIT_BASE IOMEM(0xfc000000) /* trick 0 */ -#define SOFT_BASE IOMEM(0xfd000000) /* trick 1 */ -#define IRQ_MASK IOMEM(0xfe000000) /* trick 3 - read */ -#define IRQ_MSET IOMEM(0xfe000000) /* trick 3 - write */ -#define IRQ_STAT IOMEM(0xff000000) /* trick 4 - read */ -#define IRQ_MCLR IOMEM(0xff000000) /* trick 4 - write */ - -#endif diff --git a/arch/arm/mach-ebsa110/include/mach/entry-macro.S b/arch/arm/mach-ebsa110/include/mach/entry-macro.S deleted file mode 100644 index 14b110de78a9..000000000000 --- a/arch/arm/mach-ebsa110/include/mach/entry-macro.S +++ /dev/null @@ -1,33 +0,0 @@ -/* - * arch/arm/mach-ebsa110/include/mach/entry-macro.S - * - * Low-level IRQ helper macros for ebsa110 platform. - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - - - -#define IRQ_STAT 0xff000000 /* read */ - - .macro get_irqnr_preamble, base, tmp - mov \base, #IRQ_STAT - .endm - - .macro get_irqnr_and_base, irqnr, stat, base, tmp - ldrb \stat, [\base] @ get interrupts - mov \irqnr, #0 - tst \stat, #15 - addeq \irqnr, \irqnr, #4 - moveq \stat, \stat, lsr #4 - tst \stat, #3 - addeq \irqnr, \irqnr, #2 - moveq \stat, \stat, lsr #2 - tst \stat, #1 - addeq \irqnr, \irqnr, #1 - moveq \stat, \stat, lsr #1 - tst \stat, #1 @ bit 0 should be set - .endm - diff --git a/arch/arm/mach-ebsa110/include/mach/hardware.h b/arch/arm/mach-ebsa110/include/mach/hardware.h deleted file mode 100644 index 81f6967683f6..000000000000 --- a/arch/arm/mach-ebsa110/include/mach/hardware.h +++ /dev/null @@ -1,21 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * arch/arm/mach-ebsa110/include/mach/hardware.h - * - * Copyright (C) 1996-2000 Russell King. - * - * This file contains the hardware definitions of the EBSA-110. - */ -#ifndef __ASM_ARCH_HARDWARE_H -#define __ASM_ARCH_HARDWARE_H - -#define ISAMEM_BASE 0xe0000000 -#define ISAIO_BASE 0xf0000000 - -/* - * RAM definitions - */ -#define UNCACHEABLE_ADDR 0xff000000 /* IRQ_STAT */ - -#endif - diff --git a/arch/arm/mach-ebsa110/include/mach/io.h b/arch/arm/mach-ebsa110/include/mach/io.h deleted file mode 100644 index ad170886c9aa..000000000000 --- a/arch/arm/mach-ebsa110/include/mach/io.h +++ /dev/null @@ -1,89 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * arch/arm/mach-ebsa110/include/mach/io.h - * - * Copyright (C) 1997,1998 Russell King - * - * Modifications: - * 06-Dec-1997 RMK Created. - */ -#ifndef __ASM_ARM_ARCH_IO_H -#define __ASM_ARM_ARCH_IO_H - -u8 __inb8(unsigned int port); -void __outb8(u8 val, unsigned int port); - -u8 __inb16(unsigned int port); -void __outb16(u8 val, unsigned int port); - -u16 __inw(unsigned int port); -void __outw(u16 val, unsigned int port); - -u32 __inl(unsigned int port); -void __outl(u32 val, unsigned int port); - -u8 __readb(const volatile void __iomem *addr); -u16 __readw(const volatile void __iomem *addr); -u32 __readl(const volatile void __iomem *addr); - -void __writeb(u8 val, volatile void __iomem *addr); -void __writew(u16 val, volatile void __iomem *addr); -void __writel(u32 val, volatile void __iomem *addr); - -/* - * Argh, someone forgot the IOCS16 line. We therefore have to handle - * the byte stearing by selecting the correct byte IO functions here. - */ -#ifdef ISA_SIXTEEN_BIT_PERIPHERAL -#define inb(p) __inb16(p) -#define outb(v,p) __outb16(v,p) -#else -#define inb(p) __inb8(p) -#define outb(v,p) __outb8(v,p) -#endif - -#define inw(p) __inw(p) -#define outw(v,p) __outw(v,p) - -#define inl(p) __inl(p) -#define outl(v,p) __outl(v,p) - -#define readb(b) __readb(b) -#define readw(b) __readw(b) -#define readl(b) __readl(b) -#define readb_relaxed(addr) readb(addr) -#define readw_relaxed(addr) readw(addr) -#define readl_relaxed(addr) readl(addr) - -#define writeb(v,b) __writeb(v,b) -#define writew(v,b) __writew(v,b) -#define writel(v,b) __writel(v,b) - -#define insb insb -extern void insb(unsigned int port, void *buf, int sz); -#define insw insw -extern void insw(unsigned int port, void *buf, int sz); -#define insl insl -extern void insl(unsigned int port, void *buf, int sz); - -#define outsb outsb -extern void outsb(unsigned int port, const void *buf, int sz); -#define outsw outsw -extern void outsw(unsigned int port, const void *buf, int sz); -#define outsl outsl -extern void outsl(unsigned int port, const void *buf, int sz); - -/* can't support writesb atm */ -#define writesw writesw -extern void writesw(volatile void __iomem *addr, const void *data, int wordlen); -#define writesl writesl -extern void writesl(volatile void __iomem *addr, const void *data, int longlen); - -/* can't support readsb atm */ -#define readsw readsw -extern void readsw(const volatile void __iomem *addr, void *data, int wordlen); - -#define readsl readsl -extern void readsl(const volatile void __iomem *addr, void *data, int longlen); - -#endif diff --git a/arch/arm/mach-ebsa110/include/mach/irqs.h b/arch/arm/mach-ebsa110/include/mach/irqs.h deleted file mode 100644 index 29a8671fe849..000000000000 --- a/arch/arm/mach-ebsa110/include/mach/irqs.h +++ /dev/null @@ -1,17 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * arch/arm/mach-ebsa110/include/mach/irqs.h - * - * Copyright (C) 1996 Russell King - */ - -#define NR_IRQS 8 - -#define IRQ_EBSA110_PRINTER 0 -#define IRQ_EBSA110_COM1 1 -#define IRQ_EBSA110_COM2 2 -#define IRQ_EBSA110_ETHERNET 3 -#define IRQ_EBSA110_TIMER0 4 -#define IRQ_EBSA110_TIMER1 5 -#define IRQ_EBSA110_PCMCIA 6 -#define IRQ_EBSA110_IMMEDIATE 7 diff --git a/arch/arm/mach-ebsa110/include/mach/memory.h b/arch/arm/mach-ebsa110/include/mach/memory.h deleted file mode 100644 index f025f405de50..000000000000 --- a/arch/arm/mach-ebsa110/include/mach/memory.h +++ /dev/null @@ -1,22 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * arch/arm/mach-ebsa110/include/mach/memory.h - * - * Copyright (C) 1996-1999 Russell King. - * - * Changelog: - * 20-Oct-1996 RMK Created - * 31-Dec-1997 RMK Fixed definitions to reduce warnings - * 21-Mar-1999 RMK Renamed to memory.h - * RMK Moved TASK_SIZE and PAGE_OFFSET here - */ -#ifndef __ASM_ARCH_MEMORY_H -#define __ASM_ARCH_MEMORY_H - -/* - * Cache flushing area - SRAM - */ -#define FLUSH_BASE_PHYS 0x40000000 -#define FLUSH_BASE 0xdf000000 - -#endif diff --git a/arch/arm/mach-ebsa110/include/mach/uncompress.h b/arch/arm/mach-ebsa110/include/mach/uncompress.h deleted file mode 100644 index 3ec12efe98a6..000000000000 --- a/arch/arm/mach-ebsa110/include/mach/uncompress.h +++ /dev/null @@ -1,41 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * arch/arm/mach-ebsa110/include/mach/uncompress.h - * - * Copyright (C) 1996,1997,1998 Russell King - */ - -#include - -#define SERIAL_BASE ((unsigned char *)0xf0000be0) - -/* - * This does not append a newline - */ -static inline void putc(int c) -{ - unsigned char v, *base = SERIAL_BASE; - - do { - v = base[UART_LSR << 2]; - barrier(); - } while (!(v & UART_LSR_THRE)); - - base[UART_TX << 2] = c; -} - -static inline void flush(void) -{ - unsigned char v, *base = SERIAL_BASE; - - do { - v = base[UART_LSR << 2]; - barrier(); - } while ((v & (UART_LSR_TEMT|UART_LSR_THRE)) != - (UART_LSR_TEMT|UART_LSR_THRE)); -} - -/* - * nothing to do - */ -#define arch_decomp_setup() diff --git a/arch/arm/mach-ebsa110/io.c b/arch/arm/mach-ebsa110/io.c deleted file mode 100644 index 3c44dd3596ea..000000000000 --- a/arch/arm/mach-ebsa110/io.c +++ /dev/null @@ -1,440 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * linux/arch/arm/mach-ebsa110/isamem.c - * - * Copyright (C) 2001 Russell King - * - * Perform "ISA" memory and IO accesses. The EBSA110 has some "peculiarities" - * in the way it handles accesses to odd IO ports on 16-bit devices. These - * devices have their D0-D15 lines connected to the processors D0-D15 lines. - * Since they expect all byte IO operations to be performed on D0-D7, and the - * StrongARM expects to transfer the byte to these odd addresses on D8-D15, - * we must use a trick to get the required behaviour. - * - * The trick employed here is to use long word stores to odd address -1. The - * glue logic picks this up as a "trick" access, and asserts the LSB of the - * peripherals address bus, thereby accessing the odd IO port. Meanwhile, the - * StrongARM transfers its data on D0-D7 as expected. - * - * Things get more interesting on the pass-1 EBSA110 - the PCMCIA controller - * wiring was screwed in such a way that it had limited memory space access. - * Luckily, the work-around for this is not too horrible. See - * __isamem_convert_addr for the details. - */ -#include -#include -#include -#include - -#include -#include - -static void __iomem *__isamem_convert_addr(const volatile void __iomem *addr) -{ - u32 ret, a = (u32 __force) addr; - - /* - * The PCMCIA controller is wired up as follows: - * +---------+---------+---------+---------+---------+---------+ - * PCMCIA | 2 2 2 2 | 1 1 1 1 | 1 1 1 1 | 1 1 | | | - * | 3 2 1 0 | 9 8 7 6 | 5 4 3 2 | 1 0 9 8 | 7 6 5 4 | 3 2 1 0 | - * +---------+---------+---------+---------+---------+---------+ - * CPU | 2 2 2 2 | 2 1 1 1 | 1 1 1 1 | 1 1 1 | | | - * | 4 3 2 1 | 0 9 9 8 | 7 6 5 4 | 3 2 0 9 | 8 7 6 5 | 4 3 2 x | - * +---------+---------+---------+---------+---------+---------+ - * - * This means that we can access PCMCIA regions as follows: - * 0x*10000 -> 0x*1ffff - * 0x*70000 -> 0x*7ffff - * 0x*90000 -> 0x*9ffff - * 0x*f0000 -> 0x*fffff - */ - ret = (a & 0xf803fe) << 1; - ret |= (a & 0x03fc00) << 2; - - ret += 0xe8000000; - - if ((a & 0x20000) == (a & 0x40000) >> 1) - return (void __iomem *)ret; - - BUG(); - return NULL; -} - -/* - * read[bwl] and write[bwl] - */ -u8 __readb(const volatile void __iomem *addr) -{ - void __iomem *a = __isamem_convert_addr(addr); - u32 ret; - - if ((unsigned long)addr & 1) - ret = __raw_readl(a); - else - ret = __raw_readb(a); - return ret; -} - -u16 __readw(const volatile void __iomem *addr) -{ - void __iomem *a = __isamem_convert_addr(addr); - - if ((unsigned long)addr & 1) - BUG(); - - return __raw_readw(a); -} - -u32 __readl(const volatile void __iomem *addr) -{ - void __iomem *a = __isamem_convert_addr(addr); - u32 ret; - - if ((unsigned long)addr & 3) - BUG(); - - ret = __raw_readw(a); - ret |= __raw_readw(a + 4) << 16; - return ret; -} - -EXPORT_SYMBOL(__readb); -EXPORT_SYMBOL(__readw); -EXPORT_SYMBOL(__readl); - -void readsw(const volatile void __iomem *addr, void *data, int len) -{ - void __iomem *a = __isamem_convert_addr(addr); - - BUG_ON((unsigned long)addr & 1); - - __raw_readsw(a, data, len); -} -EXPORT_SYMBOL(readsw); - -void readsl(const volatile void __iomem *addr, void *data, int len) -{ - void __iomem *a = __isamem_convert_addr(addr); - - BUG_ON((unsigned long)addr & 3); - - __raw_readsl(a, data, len); -} -EXPORT_SYMBOL(readsl); - -void __writeb(u8 val, volatile void __iomem *addr) -{ - void __iomem *a = __isamem_convert_addr(addr); - - if ((unsigned long)addr & 1) - __raw_writel(val, a); - else - __raw_writeb(val, a); -} - -void __writew(u16 val, volatile void __iomem *addr) -{ - void __iomem *a = __isamem_convert_addr(addr); - - if ((unsigned long)addr & 1) - BUG(); - - __raw_writew(val, a); -} - -void __writel(u32 val, volatile void __iomem *addr) -{ - void __iomem *a = __isamem_convert_addr(addr); - - if ((unsigned long)addr & 3) - BUG(); - - __raw_writew(val, a); - __raw_writew(val >> 16, a + 4); -} - -EXPORT_SYMBOL(__writeb); -EXPORT_SYMBOL(__writew); -EXPORT_SYMBOL(__writel); - -void writesw(volatile void __iomem *addr, const void *data, int len) -{ - void __iomem *a = __isamem_convert_addr(addr); - - BUG_ON((unsigned long)addr & 1); - - __raw_writesw(a, data, len); -} -EXPORT_SYMBOL(writesw); - -void writesl(volatile void __iomem *addr, const void *data, int len) -{ - void __iomem *a = __isamem_convert_addr(addr); - - BUG_ON((unsigned long)addr & 3); - - __raw_writesl(a, data, len); -} -EXPORT_SYMBOL(writesl); - -/* - * The EBSA110 has a weird "ISA IO" region: - * - * Region 0 (addr = 0xf0000000 + io << 2) - * -------------------------------------------------------- - * Physical region IO region - * f0000fe0 - f0000ffc 3f8 - 3ff ttyS0 - * f0000e60 - f0000e64 398 - 399 - * f0000de0 - f0000dfc 378 - 37f lp0 - * f0000be0 - f0000bfc 2f8 - 2ff ttyS1 - * - * Region 1 (addr = 0xf0000000 + (io & ~1) << 1 + (io & 1)) - * -------------------------------------------------------- - * Physical region IO region - * f00014f1 a79 pnp write data - * f00007c0 - f00007c1 3e0 - 3e1 pcmcia - * f00004f1 279 pnp address - * f0000440 - f000046c 220 - 236 eth0 - * f0000405 203 pnp read data - */ -#define SUPERIO_PORT(p) \ - (((p) >> 3) == (0x3f8 >> 3) || \ - ((p) >> 3) == (0x2f8 >> 3) || \ - ((p) >> 3) == (0x378 >> 3)) - -/* - * We're addressing an 8 or 16-bit peripheral which tranfers - * odd addresses on the low ISA byte lane. - */ -u8 __inb8(unsigned int port) -{ - u32 ret; - - /* - * The SuperIO registers use sane addressing techniques... - */ - if (SUPERIO_PORT(port)) - ret = __raw_readb((void __iomem *)ISAIO_BASE + (port << 2)); - else { - void __iomem *a = (void __iomem *)ISAIO_BASE + ((port & ~1) << 1); - - /* - * Shame nothing else does - */ - if (port & 1) - ret = __raw_readl(a); - else - ret = __raw_readb(a); - } - return ret; -} - -/* - * We're addressing a 16-bit peripheral which transfers odd - * addresses on the high ISA byte lane. - */ -u8 __inb16(unsigned int port) -{ - unsigned int offset; - - /* - * The SuperIO registers use sane addressing techniques... - */ - if (SUPERIO_PORT(port)) - offset = port << 2; - else - offset = (port & ~1) << 1 | (port & 1); - - return __raw_readb((void __iomem *)ISAIO_BASE + offset); -} - -u16 __inw(unsigned int port) -{ - unsigned int offset; - - /* - * The SuperIO registers use sane addressing techniques... - */ - if (SUPERIO_PORT(port)) - offset = port << 2; - else { - offset = port << 1; - BUG_ON(port & 1); - } - return __raw_readw((void __iomem *)ISAIO_BASE + offset); -} - -/* - * Fake a 32-bit read with two 16-bit reads. Needed for 3c589. - */ -u32 __inl(unsigned int port) -{ - void __iomem *a; - - if (SUPERIO_PORT(port) || port & 3) - BUG(); - - a = (void __iomem *)ISAIO_BASE + ((port & ~1) << 1); - - return __raw_readw(a) | __raw_readw(a + 4) << 16; -} - -EXPORT_SYMBOL(__inb8); -EXPORT_SYMBOL(__inb16); -EXPORT_SYMBOL(__inw); -EXPORT_SYMBOL(__inl); - -void __outb8(u8 val, unsigned int port) -{ - /* - * The SuperIO registers use sane addressing techniques... - */ - if (SUPERIO_PORT(port)) - __raw_writeb(val, (void __iomem *)ISAIO_BASE + (port << 2)); - else { - void __iomem *a = (void __iomem *)ISAIO_BASE + ((port & ~1) << 1); - - /* - * Shame nothing else does - */ - if (port & 1) - __raw_writel(val, a); - else - __raw_writeb(val, a); - } -} - -void __outb16(u8 val, unsigned int port) -{ - unsigned int offset; - - /* - * The SuperIO registers use sane addressing techniques... - */ - if (SUPERIO_PORT(port)) - offset = port << 2; - else - offset = (port & ~1) << 1 | (port & 1); - - __raw_writeb(val, (void __iomem *)ISAIO_BASE + offset); -} - -void __outw(u16 val, unsigned int port) -{ - unsigned int offset; - - /* - * The SuperIO registers use sane addressing techniques... - */ - if (SUPERIO_PORT(port)) - offset = port << 2; - else { - offset = port << 1; - BUG_ON(port & 1); - } - __raw_writew(val, (void __iomem *)ISAIO_BASE + offset); -} - -void __outl(u32 val, unsigned int port) -{ - BUG(); -} - -EXPORT_SYMBOL(__outb8); -EXPORT_SYMBOL(__outb16); -EXPORT_SYMBOL(__outw); -EXPORT_SYMBOL(__outl); - -void outsb(unsigned int port, const void *from, int len) -{ - u32 off; - - if (SUPERIO_PORT(port)) - off = port << 2; - else { - off = (port & ~1) << 1; - if (port & 1) - BUG(); - } - - __raw_writesb((void __iomem *)ISAIO_BASE + off, from, len); -} - -void insb(unsigned int port, void *from, int len) -{ - u32 off; - - if (SUPERIO_PORT(port)) - off = port << 2; - else { - off = (port & ~1) << 1; - if (port & 1) - BUG(); - } - - __raw_readsb((void __iomem *)ISAIO_BASE + off, from, len); -} - -EXPORT_SYMBOL(outsb); -EXPORT_SYMBOL(insb); - -void outsw(unsigned int port, const void *from, int len) -{ - u32 off; - - if (SUPERIO_PORT(port)) - off = port << 2; - else { - off = (port & ~1) << 1; - if (port & 1) - BUG(); - } - - __raw_writesw((void __iomem *)ISAIO_BASE + off, from, len); -} - -void insw(unsigned int port, void *from, int len) -{ - u32 off; - - if (SUPERIO_PORT(port)) - off = port << 2; - else { - off = (port & ~1) << 1; - if (port & 1) - BUG(); - } - - __raw_readsw((void __iomem *)ISAIO_BASE + off, from, len); -} - -EXPORT_SYMBOL(outsw); -EXPORT_SYMBOL(insw); - -/* - * We implement these as 16-bit insw/outsw, mainly for - * 3c589 cards. - */ -void outsl(unsigned int port, const void *from, int len) -{ - u32 off = port << 1; - - if (SUPERIO_PORT(port) || port & 3) - BUG(); - - __raw_writesw((void __iomem *)ISAIO_BASE + off, from, len << 1); -} - -void insl(unsigned int port, void *from, int len) -{ - u32 off = port << 1; - - if (SUPERIO_PORT(port) || port & 3) - BUG(); - - __raw_readsw((void __iomem *)ISAIO_BASE + off, from, len << 1); -} - -EXPORT_SYMBOL(outsl); -EXPORT_SYMBOL(insl); diff --git a/arch/arm/mach-ebsa110/leds.c b/arch/arm/mach-ebsa110/leds.c deleted file mode 100644 index fd1474b66d31..000000000000 --- a/arch/arm/mach-ebsa110/leds.c +++ /dev/null @@ -1,71 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Driver for the LED found on the EBSA110 machine - * Based on Versatile and RealView machine LED code - * - * Author: Bryan Wu - */ -#include -#include -#include -#include -#include - -#include - -#include "core.h" - -#if defined(CONFIG_NEW_LEDS) && defined(CONFIG_LEDS_CLASS) -static void ebsa110_led_set(struct led_classdev *cdev, - enum led_brightness b) -{ - u8 reg = __raw_readb(SOFT_BASE); - - if (b != LED_OFF) - reg |= 0x80; - else - reg &= ~0x80; - - __raw_writeb(reg, SOFT_BASE); -} - -static enum led_brightness ebsa110_led_get(struct led_classdev *cdev) -{ - u8 reg = __raw_readb(SOFT_BASE); - - return (reg & 0x80) ? LED_FULL : LED_OFF; -} - -static int __init ebsa110_leds_init(void) -{ - - struct led_classdev *cdev; - int ret; - - if (!machine_is_ebsa110()) - return -ENODEV; - - cdev = kzalloc(sizeof(*cdev), GFP_KERNEL); - if (!cdev) - return -ENOMEM; - - cdev->name = "ebsa110:0"; - cdev->brightness_set = ebsa110_led_set; - cdev->brightness_get = ebsa110_led_get; - cdev->default_trigger = "heartbeat"; - - ret = led_classdev_register(NULL, cdev); - if (ret < 0) { - kfree(cdev); - return ret; - } - - return 0; -} - -/* - * Since we may have triggers on any subsystem, defer registration - * until after subsystem_init. - */ -fs_initcall(ebsa110_leds_init); -#endif diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index fd7968635e6d..f22e37337030 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -599,7 +599,7 @@ config K3_RTI_WATCHDOG config ORION_WATCHDOG tristate "Orion watchdog" - depends on ARCH_ORION5X || ARCH_DOVE || MACH_DOVE || ARCH_MVEBU || (COMPILE_TEST && !ARCH_EBSA110) + depends on ARCH_ORION5X || ARCH_DOVE || MACH_DOVE || ARCH_MVEBU || COMPILE_TEST depends on ARM select WATCHDOG_CORE help -- cgit v1.2.3-59-g8ed1b From 6239da297281e2ea6284ce28a92f97ab047aa365 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Thu, 24 Sep 2020 15:26:08 +0200 Subject: ARM: rpc: use legacy_timer_tick rpc is the only user of the timer_tick() function now, and can just call the newly added generic version instead. Reviewed-by: Linus Walleij Signed-off-by: Arnd Bergmann --- arch/arm/Kconfig | 1 + arch/arm/include/asm/mach/time.h | 2 -- arch/arm/kernel/time.c | 14 -------------- arch/arm/mach-rpc/time.c | 2 +- 4 files changed, 2 insertions(+), 17 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 31391147315d..a652686c3b32 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -452,6 +452,7 @@ config ARCH_RPC select HAVE_IDE select HAVE_PATA_PLATFORM select ISA_DMA_API + select LEGACY_TIMER_TICK select NEED_MACH_IO_H select NEED_MACH_MEMORY_H select NO_IOPORT_MAP diff --git a/arch/arm/include/asm/mach/time.h b/arch/arm/include/asm/mach/time.h index d75d39280db7..5f522916ec99 100644 --- a/arch/arm/include/asm/mach/time.h +++ b/arch/arm/include/asm/mach/time.h @@ -7,8 +7,6 @@ #ifndef __ASM_ARM_MACH_TIME_H #define __ASM_ARM_MACH_TIME_H -extern void timer_tick(void); - typedef void (*clock_access_fn)(struct timespec64 *); extern int register_persistent_clock(clock_access_fn read_persistent); diff --git a/arch/arm/kernel/time.c b/arch/arm/kernel/time.c index 09b149b09c43..b3836c94dc74 100644 --- a/arch/arm/kernel/time.c +++ b/arch/arm/kernel/time.c @@ -60,20 +60,6 @@ unsigned long profile_pc(struct pt_regs *regs) EXPORT_SYMBOL(profile_pc); #endif -#ifndef CONFIG_GENERIC_CLOCKEVENTS -/* - * Kernel system timer support. - */ -void timer_tick(void) -{ - profile_tick(CPU_PROFILING); - xtime_update(1); -#ifndef CONFIG_SMP - update_process_times(user_mode(get_irq_regs())); -#endif -} -#endif - static void dummy_clock_access(struct timespec64 *ts) { ts->tv_sec = 0; diff --git a/arch/arm/mach-rpc/time.c b/arch/arm/mach-rpc/time.c index da85cac761ba..9f8edcfe9357 100644 --- a/arch/arm/mach-rpc/time.c +++ b/arch/arm/mach-rpc/time.c @@ -81,7 +81,7 @@ static irqreturn_t ioc_timer_interrupt(int irq, void *dev_id) { ioc_time += RPC_LATCH; - timer_tick(); + legacy_timer_tick(1); return IRQ_HANDLED; } -- cgit v1.2.3-59-g8ed1b From 0774a6ed294b963dc76df2d8342ab86d030759ec Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Thu, 24 Sep 2020 11:32:40 +0200 Subject: timekeeping: default GENERIC_CLOCKEVENTS to enabled Almost all machines use GENERIC_CLOCKEVENTS, so it feels wrong to require each one to select that symbol manually. Instead, enable it whenever CONFIG_LEGACY_TIMER_TICK is disabled as a simplification. It should be possible to select both GENERIC_CLOCKEVENTS and LEGACY_TIMER_TICK from an architecture now and decide at runtime between the two. For the clockevents arch-support.txt file, this means that additional architectures are marked as TODO when they have at least one machine that still uses LEGACY_TIMER_TICK, rather than being marked 'ok' when at least one machine has been converted. This means that both m68k and arm (for riscpc) revert to TODO. At this point, we could just always enable CONFIG_GENERIC_CLOCKEVENTS rather than leaving it off when not needed. I built an m68k defconfig kernel (using gcc-10.1.0) and found that this would add around 5.5KB in kernel image size: text data bss dec hex filename 3861936 1092236 196656 5150828 4e986c obj-m68k/vmlinux-no-clockevent 3866201 1093832 196184 5156217 4ead79 obj-m68k/vmlinux-clockevent On Arm (MACH_RPC), that difference appears to be twice as large, around 11KB on top of an 6MB vmlinux. Reviewed-by: Geert Uytterhoeven Acked-by: Geert Uytterhoeven Tested-by: Geert Uytterhoeven Reviewed-by: Linus Walleij Signed-off-by: Arnd Bergmann --- Documentation/features/time/clockevents/arch-support.txt | 6 +++--- arch/alpha/Kconfig | 1 - arch/arc/Kconfig | 1 - arch/arm/Kconfig | 12 ------------ arch/arm64/Kconfig | 1 - arch/arm64/Kconfig.platforms | 1 - arch/c6x/Kconfig | 1 - arch/csky/Kconfig | 1 - arch/h8300/Kconfig | 1 - arch/hexagon/Kconfig | 1 - arch/m68k/Kconfig.cpu | 1 - arch/microblaze/Kconfig | 1 - arch/mips/Kconfig | 1 - arch/nds32/Kconfig | 1 - arch/nios2/Kconfig | 1 - arch/openrisc/Kconfig | 1 - arch/powerpc/Kconfig | 1 - arch/riscv/Kconfig | 1 - arch/s390/Kconfig | 1 - arch/sh/Kconfig | 1 - arch/sparc/Kconfig | 1 - arch/um/Kconfig | 1 - arch/x86/Kconfig | 1 - arch/xtensa/Kconfig | 1 - kernel/time/Kconfig | 2 +- 25 files changed, 4 insertions(+), 38 deletions(-) (limited to 'arch/arm') diff --git a/Documentation/features/time/clockevents/arch-support.txt b/Documentation/features/time/clockevents/arch-support.txt index 61a5c9d68c15..6863a3fbddad 100644 --- a/Documentation/features/time/clockevents/arch-support.txt +++ b/Documentation/features/time/clockevents/arch-support.txt @@ -1,6 +1,6 @@ # # Feature name: clockevents -# Kconfig: GENERIC_CLOCKEVENTS +# Kconfig: !LEGACY_TIMER_TICK # description: arch support generic clock events # ----------------------- @@ -8,14 +8,14 @@ ----------------------- | alpha: | ok | | arc: | ok | - | arm: | ok | + | arm: | TODO | | arm64: | ok | | c6x: | ok | | csky: | ok | | h8300: | ok | | hexagon: | ok | | ia64: | TODO | - | m68k: | ok | + | m68k: | TODO | | microblaze: | ok | | mips: | ok | | nds32: | ok | diff --git a/arch/alpha/Kconfig b/arch/alpha/Kconfig index d6e9fc7a7b19..f0a700946cac 100644 --- a/arch/alpha/Kconfig +++ b/arch/alpha/Kconfig @@ -27,7 +27,6 @@ config ALPHA select ARCH_WANT_IPC_PARSE_VERSION select ARCH_HAVE_NMI_SAFE_CMPXCHG select AUDIT_ARCH - select GENERIC_CLOCKEVENTS select GENERIC_CPU_VULNERABILITIES select GENERIC_SMP_IDLE_THREAD select GENERIC_STRNCPY_FROM_USER diff --git a/arch/arc/Kconfig b/arch/arc/Kconfig index 0a89cc9def65..061eb8e23739 100644 --- a/arch/arc/Kconfig +++ b/arch/arc/Kconfig @@ -19,7 +19,6 @@ config ARC select COMMON_CLK select DMA_DIRECT_REMAP select GENERIC_ATOMIC64 if !ISA_ARCV2 || !(ARC_HAS_LL64 && ARC_HAS_LLSC) - select GENERIC_CLOCKEVENTS select GENERIC_FIND_FIRST_BIT # for now, we don't need GENERIC_IRQ_PROBE, CONFIG_GENERIC_IRQ_CHIP select GENERIC_IRQ_SHOW diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index a652686c3b32..446c6c88e47f 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -321,7 +321,6 @@ config ARCH_MULTIPLATFORM select AUTO_ZRELADDR select TIMER_OF select COMMON_CLK - select GENERIC_CLOCKEVENTS select GENERIC_IRQ_MULTI_HANDLER select HAVE_PCI select PCI_DOMAINS_GENERIC if PCI @@ -336,7 +335,6 @@ config ARM_SINGLE_ARMV7M select TIMER_OF select COMMON_CLK select CPU_V7M - select GENERIC_CLOCKEVENTS select NO_IOPORT_MAP select SPARSE_IRQ select USE_OF @@ -351,7 +349,6 @@ config ARCH_EP93XX select CLKDEV_LOOKUP select CLKSRC_MMIO select CPU_ARM920T - select GENERIC_CLOCKEVENTS select GPIOLIB select HAVE_LEGACY_CLK help @@ -361,7 +358,6 @@ config ARCH_FOOTBRIDGE bool "FootBridge" select CPU_SA110 select FOOTBRIDGE - select GENERIC_CLOCKEVENTS select HAVE_IDE select NEED_MACH_IO_H if !MMU select NEED_MACH_MEMORY_H @@ -389,7 +385,6 @@ config ARCH_IXP4XX select ARCH_SUPPORTS_BIG_ENDIAN select CPU_XSCALE select DMABOUNCE if PCI - select GENERIC_CLOCKEVENTS select GENERIC_IRQ_MULTI_HANDLER select GPIO_IXP4XX select GPIOLIB @@ -405,7 +400,6 @@ config ARCH_IXP4XX config ARCH_DOVE bool "Marvell Dove" select CPU_PJ4 - select GENERIC_CLOCKEVENTS select GENERIC_IRQ_MULTI_HANDLER select GPIOLIB select HAVE_PCI @@ -429,7 +423,6 @@ config ARCH_PXA select CLKSRC_MMIO select TIMER_OF select CPU_XSCALE if !CPU_XSC3 - select GENERIC_CLOCKEVENTS select GENERIC_IRQ_MULTI_HANDLER select GPIO_PXA select GPIOLIB @@ -470,7 +463,6 @@ config ARCH_SA1100 select COMMON_CLK select CPU_FREQ select CPU_SA1100 - select GENERIC_CLOCKEVENTS select GENERIC_IRQ_MULTI_HANDLER select GPIOLIB select HAVE_IDE @@ -485,7 +477,6 @@ config ARCH_S3C24XX bool "Samsung S3C24XX SoCs" select ATAGS select CLKSRC_SAMSUNG_PWM - select GENERIC_CLOCKEVENTS select GPIO_SAMSUNG select GPIOLIB select GENERIC_IRQ_MULTI_HANDLER @@ -509,7 +500,6 @@ config ARCH_OMAP1 select ARCH_OMAP select CLKDEV_LOOKUP select CLKSRC_MMIO - select GENERIC_CLOCKEVENTS select GENERIC_IRQ_CHIP select GENERIC_IRQ_MULTI_HANDLER select GPIOLIB @@ -772,7 +762,6 @@ config ARCH_ACORN config PLAT_IOP bool - select GENERIC_CLOCKEVENTS config PLAT_ORION bool @@ -1163,7 +1152,6 @@ config HAVE_SMP config SMP bool "Symmetric Multi-Processing" depends on CPU_V6K || CPU_V7 - depends on GENERIC_CLOCKEVENTS depends on HAVE_SMP depends on MMU || ARM_MPU select IRQ_WORK diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index f858c352f72a..fee87e4104fd 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -101,7 +101,6 @@ config ARM64 select FRAME_POINTER select GENERIC_ALLOCATOR select GENERIC_ARCH_TOPOLOGY - select GENERIC_CLOCKEVENTS select GENERIC_CLOCKEVENTS_BROADCAST select GENERIC_CPU_AUTOPROBE select GENERIC_CPU_VULNERABILITIES diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index 6f2494dd6d60..748e6d8c3b94 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -256,7 +256,6 @@ config ARCH_TEGRA select ARM_GIC_PM select CLKSRC_MMIO select TIMER_OF - select GENERIC_CLOCKEVENTS select GPIOLIB select PINCTRL select PM diff --git a/arch/c6x/Kconfig b/arch/c6x/Kconfig index 48d66bf0465d..bdeeac28b1be 100644 --- a/arch/c6x/Kconfig +++ b/arch/c6x/Kconfig @@ -19,7 +19,6 @@ config C6X select IRQ_DOMAIN select OF select OF_EARLY_FLATTREE - select GENERIC_CLOCKEVENTS select MODULES_USE_ELF_RELA select MMU_GATHER_NO_RANGE if MMU select SET_FS diff --git a/arch/csky/Kconfig b/arch/csky/Kconfig index 268fad5f51cf..28fdf8303dff 100644 --- a/arch/csky/Kconfig +++ b/arch/csky/Kconfig @@ -28,7 +28,6 @@ config CSKY select GENERIC_LIB_UCMPDI2 select GENERIC_ALLOCATOR select GENERIC_ATOMIC64 - select GENERIC_CLOCKEVENTS select GENERIC_CPU_DEVICES select GENERIC_IRQ_CHIP select GENERIC_IRQ_PROBE diff --git a/arch/h8300/Kconfig b/arch/h8300/Kconfig index 7945de067e9f..3e3e0f16f7e0 100644 --- a/arch/h8300/Kconfig +++ b/arch/h8300/Kconfig @@ -12,7 +12,6 @@ config H8300 select FRAME_POINTER select GENERIC_CPU_DEVICES select MODULES_USE_ELF_RELA - select GENERIC_CLOCKEVENTS select COMMON_CLK select ARCH_WANT_FRAME_POINTERS select OF diff --git a/arch/hexagon/Kconfig b/arch/hexagon/Kconfig index f2afabbadd43..6e00c16a36b5 100644 --- a/arch/hexagon/Kconfig +++ b/arch/hexagon/Kconfig @@ -27,7 +27,6 @@ config HEXAGON select GENERIC_IOMAP select GENERIC_SMP_IDLE_THREAD select STACKTRACE_SUPPORT - select GENERIC_CLOCKEVENTS select GENERIC_CLOCKEVENTS_BROADCAST select MODULES_USE_ELF_RELA select GENERIC_CPU_DEVICES diff --git a/arch/m68k/Kconfig.cpu b/arch/m68k/Kconfig.cpu index 648054d4f860..ce09f993d858 100644 --- a/arch/m68k/Kconfig.cpu +++ b/arch/m68k/Kconfig.cpu @@ -318,7 +318,6 @@ config M54xx config COLDFIRE_PIT_TIMER bool - select GENERIC_CLOCKEVENTS config COLDFIRE_TIMERS bool diff --git a/arch/microblaze/Kconfig b/arch/microblaze/Kconfig index 33925ffed68f..2f0d3f431faf 100644 --- a/arch/microblaze/Kconfig +++ b/arch/microblaze/Kconfig @@ -17,7 +17,6 @@ config MICROBLAZE select COMMON_CLK select DMA_DIRECT_REMAP if MMU select GENERIC_ATOMIC64 - select GENERIC_CLOCKEVENTS select GENERIC_CPU_DEVICES select GENERIC_IDLE_POLL_SETUP select GENERIC_IRQ_PROBE diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 2000bb2b0220..077c4ae09550 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -21,7 +21,6 @@ config MIPS select CPU_NO_EFFICIENT_FFS if (TARGET_ISA_REV < 1) select CPU_PM if CPU_IDLE select GENERIC_ATOMIC64 if !64BIT - select GENERIC_CLOCKEVENTS select GENERIC_CMOS_UPDATE select GENERIC_CPU_AUTOPROBE select GENERIC_GETTIMEOFDAY diff --git a/arch/nds32/Kconfig b/arch/nds32/Kconfig index e8e541fd2267..62313902d75d 100644 --- a/arch/nds32/Kconfig +++ b/arch/nds32/Kconfig @@ -17,7 +17,6 @@ config NDS32 select DMA_DIRECT_REMAP select GENERIC_ATOMIC64 select GENERIC_CPU_DEVICES - select GENERIC_CLOCKEVENTS select GENERIC_IRQ_CHIP select GENERIC_IRQ_SHOW select GENERIC_IOREMAP diff --git a/arch/nios2/Kconfig b/arch/nios2/Kconfig index c7c6ba6bec9d..c24955c81c92 100644 --- a/arch/nios2/Kconfig +++ b/arch/nios2/Kconfig @@ -10,7 +10,6 @@ config NIOS2 select COMMON_CLK select TIMER_OF select GENERIC_ATOMIC64 - select GENERIC_CLOCKEVENTS select GENERIC_CPU_DEVICES select GENERIC_IRQ_PROBE select GENERIC_IRQ_SHOW diff --git a/arch/openrisc/Kconfig b/arch/openrisc/Kconfig index 6233c6293180..591acc5990dc 100644 --- a/arch/openrisc/Kconfig +++ b/arch/openrisc/Kconfig @@ -24,7 +24,6 @@ config OPENRISC select GENERIC_CPU_DEVICES select HAVE_UID16 select GENERIC_ATOMIC64 - select GENERIC_CLOCKEVENTS select GENERIC_CLOCKEVENTS_BROADCAST select GENERIC_STRNCPY_FROM_USER select GENERIC_STRNLEN_USER diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig index e9f13fe08492..57e2c75f76e9 100644 --- a/arch/powerpc/Kconfig +++ b/arch/powerpc/Kconfig @@ -163,7 +163,6 @@ config PPC select EDAC_ATOMIC_SCRUB select EDAC_SUPPORT select GENERIC_ATOMIC64 if PPC32 - select GENERIC_CLOCKEVENTS select GENERIC_CLOCKEVENTS_BROADCAST if SMP select GENERIC_CMOS_UPDATE select GENERIC_CPU_AUTOPROBE diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 44377fd7860e..3842bbb4fe62 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -37,7 +37,6 @@ config RISCV select EDAC_SUPPORT select GENERIC_ARCH_TOPOLOGY if SMP select GENERIC_ATOMIC64 if !64BIT - select GENERIC_CLOCKEVENTS select GENERIC_EARLY_IOREMAP select GENERIC_GETTIMEOFDAY if HAVE_GENERIC_VDSO select GENERIC_IOREMAP diff --git a/arch/s390/Kconfig b/arch/s390/Kconfig index 4a2a12be04c9..db246781844d 100644 --- a/arch/s390/Kconfig +++ b/arch/s390/Kconfig @@ -116,7 +116,6 @@ config S390 select CLONE_BACKWARDS2 select DMA_OPS if PCI select DYNAMIC_FTRACE if FUNCTION_TRACER - select GENERIC_CLOCKEVENTS select GENERIC_CPU_AUTOPROBE select GENERIC_CPU_VULNERABILITIES select GENERIC_FIND_FIRST_BIT diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig index 159da4ed578f..5fa580219a86 100644 --- a/arch/sh/Kconfig +++ b/arch/sh/Kconfig @@ -16,7 +16,6 @@ config SUPERH select CPU_NO_EFFICIENT_FFS select DMA_DECLARE_COHERENT select GENERIC_ATOMIC64 - select GENERIC_CLOCKEVENTS select GENERIC_CMOS_UPDATE if SH_SH03 || SH_DREAMCAST select GENERIC_IDLE_POLL_SETUP select GENERIC_IRQ_SHOW diff --git a/arch/sparc/Kconfig b/arch/sparc/Kconfig index a6ca135442f9..718c51cf2c6c 100644 --- a/arch/sparc/Kconfig +++ b/arch/sparc/Kconfig @@ -39,7 +39,6 @@ config SPARC select HAVE_EBPF_JIT if SPARC64 select HAVE_DEBUG_BUGVERBOSE select GENERIC_SMP_IDLE_THREAD - select GENERIC_CLOCKEVENTS select GENERIC_STRNCPY_FROM_USER select GENERIC_STRNLEN_USER select MODULES_USE_ELF_RELA diff --git a/arch/um/Kconfig b/arch/um/Kconfig index 4b799fad8b48..43333e36e0ba 100644 --- a/arch/um/Kconfig +++ b/arch/um/Kconfig @@ -17,7 +17,6 @@ config UML select NO_DMA select GENERIC_IRQ_SHOW select GENERIC_CPU_DEVICES - select GENERIC_CLOCKEVENTS select HAVE_GCC_PLUGINS select SET_FS select TTY # Needed for line.c diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index f6946b81f74a..0498d7596ccc 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -108,7 +108,6 @@ config X86 select DCACHE_WORD_ACCESS select EDAC_ATOMIC_SCRUB select EDAC_SUPPORT - select GENERIC_CLOCKEVENTS select GENERIC_CLOCKEVENTS_BROADCAST if X86_64 || (X86_32 && X86_LOCAL_APIC) select GENERIC_CLOCKEVENTS_MIN_ADJUST select GENERIC_CMOS_UPDATE diff --git a/arch/xtensa/Kconfig b/arch/xtensa/Kconfig index d0dfa50bd0bb..2611ba336af8 100644 --- a/arch/xtensa/Kconfig +++ b/arch/xtensa/Kconfig @@ -16,7 +16,6 @@ config XTENSA select COMMON_CLK select DMA_REMAP if MMU select GENERIC_ATOMIC64 - select GENERIC_CLOCKEVENTS select GENERIC_IRQ_SHOW select GENERIC_PCI_IOMAP select GENERIC_SCHED_CLOCK diff --git a/kernel/time/Kconfig b/kernel/time/Kconfig index c6867f29d279..9a41848b6ebb 100644 --- a/kernel/time/Kconfig +++ b/kernel/time/Kconfig @@ -28,7 +28,7 @@ config GENERIC_TIME_VSYSCALL # The generic clock events infrastructure config GENERIC_CLOCKEVENTS - bool + def_bool !LEGACY_TIMER_TICK # Architecture can handle broadcast in a driver-agnostic way config ARCH_HAS_TICK_BROADCAST -- cgit v1.2.3-59-g8ed1b From 73db215119963918afe446c6cec76e2d421aa33c Mon Sep 17 00:00:00 2001 From: Oleksij Rempel Date: Fri, 16 Oct 2020 09:51:58 +0200 Subject: ARM: dts: imx6/7: sync fsl,stop-mode with current flexcan driver After this patch we need 2 arguments less for the fsl,stop-mode property: | commit d9b081e3fc4bdc33e672dcb7bb256394909432fc | Author: Marc Kleine-Budde | Date: Sun Jun 14 21:09:20 2020 +0200 | | can: flexcan: remove ack_grp and ack_bit handling from driver | | Since commit: | | 048e3a34a2e7 can: flexcan: poll MCR_LPM_ACK instead of GPR ACK for stop mode acknowledgment | | the driver polls the IP core's internal bit MCR[LPM_ACK] as stop mode | acknowledge and not the acknowledgment on chip level. | | This means the 4th and 5th value of the property "fsl,stop-mode" isn't used | anymore. This patch removes the used "ack_gpr" and "ack_bit" from the driver. This patch removes the two last arguments, as they are not needed anymore. Signed-off-by: Oleksij Rempel Reviewed-by: Joakim Zhang Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl.dtsi | 4 ++-- arch/arm/boot/dts/imx6sx.dtsi | 4 ++-- arch/arm/boot/dts/imx6ul.dtsi | 4 ++-- arch/arm/boot/dts/imx7s.dtsi | 4 ++-- 4 files changed, 8 insertions(+), 8 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi index 7a8837cbe21b..bc98b63922b0 100644 --- a/arch/arm/boot/dts/imx6qdl.dtsi +++ b/arch/arm/boot/dts/imx6qdl.dtsi @@ -549,7 +549,7 @@ clocks = <&clks IMX6QDL_CLK_CAN1_IPG>, <&clks IMX6QDL_CLK_CAN1_SERIAL>; clock-names = "ipg", "per"; - fsl,stop-mode = <&gpr 0x34 28 0x10 17>; + fsl,stop-mode = <&gpr 0x34 28>; status = "disabled"; }; @@ -560,7 +560,7 @@ clocks = <&clks IMX6QDL_CLK_CAN2_IPG>, <&clks IMX6QDL_CLK_CAN2_SERIAL>; clock-names = "ipg", "per"; - fsl,stop-mode = <&gpr 0x34 29 0x10 18>; + fsl,stop-mode = <&gpr 0x34 29>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi index dfdca1804f9f..6c604c38c790 100644 --- a/arch/arm/boot/dts/imx6sx.dtsi +++ b/arch/arm/boot/dts/imx6sx.dtsi @@ -463,7 +463,7 @@ clocks = <&clks IMX6SX_CLK_CAN1_IPG>, <&clks IMX6SX_CLK_CAN1_SERIAL>; clock-names = "ipg", "per"; - fsl,stop-mode = <&gpr 0x10 1 0x10 17>; + fsl,stop-mode = <&gpr 0x10 1>; status = "disabled"; }; @@ -474,7 +474,7 @@ clocks = <&clks IMX6SX_CLK_CAN2_IPG>, <&clks IMX6SX_CLK_CAN2_SERIAL>; clock-names = "ipg", "per"; - fsl,stop-mode = <&gpr 0x10 2 0x10 18>; + fsl,stop-mode = <&gpr 0x10 2>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/imx6ul.dtsi b/arch/arm/boot/dts/imx6ul.dtsi index d7d9f3e46b92..713a4bb341db 100644 --- a/arch/arm/boot/dts/imx6ul.dtsi +++ b/arch/arm/boot/dts/imx6ul.dtsi @@ -430,7 +430,7 @@ clocks = <&clks IMX6UL_CLK_CAN1_IPG>, <&clks IMX6UL_CLK_CAN1_SERIAL>; clock-names = "ipg", "per"; - fsl,stop-mode = <&gpr 0x10 1 0x10 17>; + fsl,stop-mode = <&gpr 0x10 1>; status = "disabled"; }; @@ -441,7 +441,7 @@ clocks = <&clks IMX6UL_CLK_CAN2_IPG>, <&clks IMX6UL_CLK_CAN2_SERIAL>; clock-names = "ipg", "per"; - fsl,stop-mode = <&gpr 0x10 2 0x10 18>; + fsl,stop-mode = <&gpr 0x10 2>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi index 84d9cc13afb9..b58262acba11 100644 --- a/arch/arm/boot/dts/imx7s.dtsi +++ b/arch/arm/boot/dts/imx7s.dtsi @@ -971,7 +971,7 @@ clocks = <&clks IMX7D_CLK_DUMMY>, <&clks IMX7D_CAN1_ROOT_CLK>; clock-names = "ipg", "per"; - fsl,stop-mode = <&gpr 0x10 1 0x10 17>; + fsl,stop-mode = <&gpr 0x10 1>; status = "disabled"; }; @@ -982,7 +982,7 @@ clocks = <&clks IMX7D_CLK_DUMMY>, <&clks IMX7D_CAN2_ROOT_CLK>; clock-names = "ipg", "per"; - fsl,stop-mode = <&gpr 0x10 2 0x10 18>; + fsl,stop-mode = <&gpr 0x10 2>; status = "disabled"; }; -- cgit v1.2.3-59-g8ed1b From 5a76c474e8b940dc324eed4e10d486405c4110d7 Mon Sep 17 00:00:00 2001 From: Guillaume Tucker Date: Mon, 10 Aug 2020 13:22:08 +0100 Subject: ARM: exynos: clear prefetch bits in default l2c_aux_val Clear the L310_AUX_CTRL_DATA_PREFETCH and L310_AUX_CTRL_INSTR_PREFETCH bits in the l2c_aux_val defaults for Exynos since they can now be set using the standard l2c2x0 devicetree bindings. Signed-off-by: Guillaume Tucker Link: https://lore.kernel.org/r/e44b5226f3ad1551459830c678ed183762d8e458.1597061474.git.guillaume.tucker@collabora.com Signed-off-by: Krzysztof Kozlowski --- arch/arm/mach-exynos/exynos.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c index 700763e07083..a99d8eba4bb3 100644 --- a/arch/arm/mach-exynos/exynos.c +++ b/arch/arm/mach-exynos/exynos.c @@ -206,8 +206,8 @@ static void __init exynos_dt_fixup(void) } DT_MACHINE_START(EXYNOS_DT, "Samsung Exynos (Flattened Device Tree)") - .l2c_aux_val = 0x38400000, - .l2c_aux_mask = 0xc60fffff, + .l2c_aux_val = 0x08400000, + .l2c_aux_mask = 0xf60fffff, .smp = smp_ops(exynos_smp_ops), .map_io = exynos_init_io, .init_early = exynos_firmware_init, -- cgit v1.2.3-59-g8ed1b From 225c59b9235a421cdb219be5fbc13126a49714a6 Mon Sep 17 00:00:00 2001 From: Alexandru Stan Date: Wed, 21 Oct 2020 22:04:43 -0700 Subject: ARM: dts: rockchip: Remove 0 point from brightness-levels on rk3288-veyron The extra 0 only adds one point in the userspace visible range, so this change is almost a noop with the current driver behavior. We don't need the 0% point, userspace seems to handle this just fine because it uses the bl_power property to turn off the display. Furthermore after adding "backlight: pwm_bl: Fix interpolation" patch, the backlight interpolation will work a little differently. So we need to preemptively remove the 0-3 segment since otherwise we would have a 252 long interpolation that would slowly go between 0 and 3, looking really bad in userspace. So it's almost a noop/cleanup now, but it will be required in the future. Signed-off-by: Alexandru Stan Reviewed-by: Douglas Anderson Acked-by: Daniel Thompson Link: https://lore.kernel.org/r/20201021220404.v3.1.I96b8d872ec51171f19274e43e96cadc092881271@changeid Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3288-veyron-jaq.dts | 2 +- arch/arm/boot/dts/rk3288-veyron-minnie.dts | 2 +- arch/arm/boot/dts/rk3288-veyron-tiger.dts | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/rk3288-veyron-jaq.dts b/arch/arm/boot/dts/rk3288-veyron-jaq.dts index af77ab20586d..4a148cf1defc 100644 --- a/arch/arm/boot/dts/rk3288-veyron-jaq.dts +++ b/arch/arm/boot/dts/rk3288-veyron-jaq.dts @@ -20,7 +20,7 @@ &backlight { /* Jaq panel PWM must be >= 3%, so start non-zero brightness at 8 */ - brightness-levels = <0 8 255>; + brightness-levels = <8 255>; num-interpolated-steps = <247>; }; diff --git a/arch/arm/boot/dts/rk3288-veyron-minnie.dts b/arch/arm/boot/dts/rk3288-veyron-minnie.dts index f8b69e0a16a0..82fc6fba9999 100644 --- a/arch/arm/boot/dts/rk3288-veyron-minnie.dts +++ b/arch/arm/boot/dts/rk3288-veyron-minnie.dts @@ -39,7 +39,7 @@ &backlight { /* Minnie panel PWM must be >= 1%, so start non-zero brightness at 3 */ - brightness-levels = <0 3 255>; + brightness-levels = <3 255>; num-interpolated-steps = <252>; }; diff --git a/arch/arm/boot/dts/rk3288-veyron-tiger.dts b/arch/arm/boot/dts/rk3288-veyron-tiger.dts index 069f0c2c1fdf..52a84cbe7a90 100644 --- a/arch/arm/boot/dts/rk3288-veyron-tiger.dts +++ b/arch/arm/boot/dts/rk3288-veyron-tiger.dts @@ -23,7 +23,7 @@ &backlight { /* Tiger panel PWM must be >= 1%, so start non-zero brightness at 3 */ - brightness-levels = <0 3 255>; + brightness-levels = <3 255>; num-interpolated-steps = <252>; }; -- cgit v1.2.3-59-g8ed1b From 14f100c00f1e35e5890340d4c6a64bda5dff4320 Mon Sep 17 00:00:00 2001 From: Vijay Khemka Date: Thu, 13 Aug 2020 12:04:30 -0700 Subject: ARM: dts: aspeed: tiogapass: Remove vuart Removed vuart for facebook tiogapass platform as it uses uart2 and uart3 pin with aspeed uart routing feature. Signed-off-by: Vijay Khemka Reviewed-by: Joel Stanley Fixes: ffdbf494821d ("ARM: dts: aspeed: tiogapass: Enable VUART") Link: https://lore.kernel.org/r/20200813190431.3331026-1-vijaykhemka@fb.com Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts | 5 ----- 1 file changed, 5 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts b/arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts index 2d44d9ad4e40..e6ad821a8635 100644 --- a/arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts +++ b/arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts @@ -82,11 +82,6 @@ status = "okay"; }; -&vuart { - // VUART Host Console - status = "okay"; -}; - &uart1 { // Host Console status = "okay"; -- cgit v1.2.3-59-g8ed1b From 85f296433e6c417b27c4077ed3f9479596d9c623 Mon Sep 17 00:00:00 2001 From: Matteo Scordino Date: Fri, 30 Oct 2020 23:43:21 +0000 Subject: ARM: dts: sun8i: V3/S3: Add UART1 pin definitions to the V3/S3 dtsi The Allwinner V3 and S3 can use PG6/7 as RX/TX for UART1. Since no other functions are assigned to those pins, they are a convenient choice for a debugging or application UART. This is specific to V3/S3 as the V3s's non-BGA package did not have those pins. Signed-off-by: Matteo Scordino Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20201030234325.5865-3-matteo.scordino@gmail.com --- arch/arm/boot/dts/sun8i-v3.dtsi | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun8i-v3.dtsi b/arch/arm/boot/dts/sun8i-v3.dtsi index ca4672ed2e02..c279e13583ba 100644 --- a/arch/arm/boot/dts/sun8i-v3.dtsi +++ b/arch/arm/boot/dts/sun8i-v3.dtsi @@ -24,4 +24,9 @@ &pio { compatible = "allwinner,sun8i-v3-pinctrl"; + + uart1_pg_pins: uart1-pg-pins { + pins = "PG6", "PG7"; + function = "uart1"; + }; }; -- cgit v1.2.3-59-g8ed1b From 52a70e641a1fe6b0dc3ff46a8498d778ce6b99de Mon Sep 17 00:00:00 2001 From: Paul Kocialkowski Date: Sat, 31 Oct 2020 19:21:31 +0100 Subject: ARM: dts: sun8i-v3s: Add I2C1 PB pins description I2C1 can be exposed through PB pins in addition to PE pins on the V3s. Add the device-tree description for these pins. Signed-off-by: Paul Kocialkowski Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20201031182137.1879521-4-contact@paulk.fr --- arch/arm/boot/dts/sun8i-v3s.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi index 0c7341676921..7b2d684aeb97 100644 --- a/arch/arm/boot/dts/sun8i-v3s.dtsi +++ b/arch/arm/boot/dts/sun8i-v3s.dtsi @@ -347,6 +347,12 @@ function = "i2c0"; }; + /omit-if-no-ref/ + i2c1_pb_pins: i2c1-pb-pins { + pins = "PB8", "PB9"; + function = "i2c1"; + }; + /omit-if-no-ref/ i2c1_pe_pins: i2c1-pe-pins { pins = "PE21", "PE22"; -- cgit v1.2.3-59-g8ed1b From efc5dae95a8c272e7737a29fdaecc06d64320717 Mon Sep 17 00:00:00 2001 From: Konstantin Aladyshev Date: Tue, 27 Oct 2020 15:37:21 +0300 Subject: ARM: dts: aspeed: amd-ethanolx: Enable KCS channel 3 The KCS interface on the LPC channel 3 in the controller is used for the in-band BMC<->BIOS IPMI communication. 0xCA2 is a default host CPU LPC IO address for this interface. Signed-off-by: Konstantin Aladyshev Reviewed-by: Supreeth Venkatesh Reviewed-by: Joel Stanley Link: https://lore.kernel.org/r/20201027123722.2935-2-aladyshev22@gmail.com Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-amd-ethanolx.dts | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/aspeed-bmc-amd-ethanolx.dts b/arch/arm/boot/dts/aspeed-bmc-amd-ethanolx.dts index 89ddc3847222..2a86bda8afd8 100644 --- a/arch/arm/boot/dts/aspeed-bmc-amd-ethanolx.dts +++ b/arch/arm/boot/dts/aspeed-bmc-amd-ethanolx.dts @@ -147,6 +147,11 @@ aspeed,lpc-io-reg = <0x62>; }; +&kcs3 { + status = "okay"; + aspeed,lpc-io-reg = <0xCA2>; +}; + &kcs4 { status = "okay"; aspeed,lpc-io-reg = <0x97DE>; -- cgit v1.2.3-59-g8ed1b From f69456d3224aff06820dfc2460780046bb6544b0 Mon Sep 17 00:00:00 2001 From: Konstantin Aladyshev Date: Tue, 27 Oct 2020 15:37:22 +0300 Subject: ARM: dts: aspeed: amd-ethanolx: Enable devices for the iKVM functionality Enable the USB 2.0 Virtual Hub Controller and the Video Engine with it's reserved memory region for the implementation of the iKVM functionality in the BMC. Signed-off-by: Konstantin Aladyshev Reviewed-by: Supreeth Venkatesh Reviewed-by: Joel Stanley Link: https://lore.kernel.org/r/20201027123722.2935-3-aladyshev22@gmail.com Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-amd-ethanolx.dts | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/aspeed-bmc-amd-ethanolx.dts b/arch/arm/boot/dts/aspeed-bmc-amd-ethanolx.dts index 2a86bda8afd8..b93ed44eba0c 100644 --- a/arch/arm/boot/dts/aspeed-bmc-amd-ethanolx.dts +++ b/arch/arm/boot/dts/aspeed-bmc-amd-ethanolx.dts @@ -13,6 +13,21 @@ memory@80000000 { reg = <0x80000000 0x20000000>; }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + video_engine_memory: jpegbuffer { + size = <0x02000000>; /* 32M */ + alignment = <0x01000000>; + compatible = "shared-dma-pool"; + reusable; + }; + }; + + aliases { serial0 = &uart1; serial4 = &uart5; @@ -220,5 +235,12 @@ }; }; +&video { + status = "okay"; + memory-region = <&video_engine_memory>; +}; +&vhub { + status = "okay"; +}; -- cgit v1.2.3-59-g8ed1b From cd7c897821a0dd41b10b756601d5707f0096652b Mon Sep 17 00:00:00 2001 From: Marcus Cooper Date: Fri, 30 Oct 2020 15:46:48 +0100 Subject: arm: dts: sunxi: h3/h5: Add I2S2 node MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add H3/H5 I2S2 node connected to the HDMI interface. Signed-off-by: Jernej Skrabec Signed-off-by: Marcus Cooper Signed-off-by: Clément Péron Signed-off-by: Maxime Ripard Acked-by: Chen-Yu Tsai Link: https://lore.kernel.org/r/20201030144648.397824-16-peron.clem@gmail.com --- arch/arm/boot/dts/sunxi-h3-h5.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi index 22d533d18992..9be13378d4df 100644 --- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi +++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi @@ -662,6 +662,19 @@ status = "disabled"; }; + i2s2: i2s@1c22800 { + #sound-dai-cells = <0>; + compatible = "allwinner,sun8i-h3-i2s"; + reg = <0x01c22800 0x400>; + interrupts = ; + clocks = <&ccu CLK_BUS_I2S2>, <&ccu CLK_I2S2>; + clock-names = "apb", "mod"; + dmas = <&dma 27>; + resets = <&ccu RST_BUS_I2S2>; + dma-names = "tx"; + status = "disabled"; + }; + codec: codec@1c22c00 { #sound-dai-cells = <0>; compatible = "allwinner,sun8i-h3-codec"; -- cgit v1.2.3-59-g8ed1b From 5c8b3b8a182cbc1ccdfcdeea9b25dd2c12a8148f Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Sun, 1 Nov 2020 19:29:53 +0800 Subject: ARM: dts: imx: add usb alias Add usb alias for bootloader searching the controller in correct order. Signed-off-by: Peng Fan Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl.dtsi | 4 ++++ arch/arm/boot/dts/imx6sl.dtsi | 3 +++ arch/arm/boot/dts/imx6sll.dtsi | 2 ++ arch/arm/boot/dts/imx6sx.dtsi | 3 +++ arch/arm/boot/dts/imx6ul.dtsi | 2 ++ arch/arm/boot/dts/imx7d.dtsi | 6 ++++++ arch/arm/boot/dts/imx7s.dtsi | 2 ++ 7 files changed, 22 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi index bc98b63922b0..cb2a8ef9070c 100644 --- a/arch/arm/boot/dts/imx6qdl.dtsi +++ b/arch/arm/boot/dts/imx6qdl.dtsi @@ -45,6 +45,10 @@ spi1 = &ecspi2; spi2 = &ecspi3; spi3 = &ecspi4; + usb0 = &usbotg; + usb1 = &usbh1; + usb2 = &usbh2; + usb3 = &usbh3; usbphy0 = &usbphy1; usbphy1 = &usbphy2; }; diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi index 91a8c54d5e11..997b96c1c47b 100644 --- a/arch/arm/boot/dts/imx6sl.dtsi +++ b/arch/arm/boot/dts/imx6sl.dtsi @@ -39,6 +39,9 @@ spi1 = &ecspi2; spi2 = &ecspi3; spi3 = &ecspi4; + usb0 = &usbotg1; + usb1 = &usbotg2; + usb2 = &usbh; usbphy0 = &usbphy1; usbphy1 = &usbphy2; }; diff --git a/arch/arm/boot/dts/imx6sll.dtsi b/arch/arm/boot/dts/imx6sll.dtsi index 0b622201a1f3..04f8d637a501 100644 --- a/arch/arm/boot/dts/imx6sll.dtsi +++ b/arch/arm/boot/dts/imx6sll.dtsi @@ -36,6 +36,8 @@ spi1 = &ecspi2; spi3 = &ecspi3; spi4 = &ecspi4; + usb0 = &usbotg1; + usb1 = &usbotg2; usbphy0 = &usbphy1; usbphy1 = &usbphy2; }; diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi index 6c604c38c790..8516730778df 100644 --- a/arch/arm/boot/dts/imx6sx.dtsi +++ b/arch/arm/boot/dts/imx6sx.dtsi @@ -49,6 +49,9 @@ spi2 = &ecspi3; spi3 = &ecspi4; spi4 = &ecspi5; + usb0 = &usbotg1; + usb1 = &usbotg2; + usb2 = &usbh; usbphy0 = &usbphy1; usbphy1 = &usbphy2; }; diff --git a/arch/arm/boot/dts/imx6ul.dtsi b/arch/arm/boot/dts/imx6ul.dtsi index 713a4bb341db..ccbcbac80663 100644 --- a/arch/arm/boot/dts/imx6ul.dtsi +++ b/arch/arm/boot/dts/imx6ul.dtsi @@ -47,6 +47,8 @@ spi1 = &ecspi2; spi2 = &ecspi3; spi3 = &ecspi4; + usb0 = &usbotg1; + usb1 = &usbotg2; usbphy0 = &usbphy1; usbphy1 = &usbphy2; }; diff --git a/arch/arm/boot/dts/imx7d.dtsi b/arch/arm/boot/dts/imx7d.dtsi index cff875b80b60..b0bcfa9094a3 100644 --- a/arch/arm/boot/dts/imx7d.dtsi +++ b/arch/arm/boot/dts/imx7d.dtsi @@ -7,6 +7,12 @@ #include / { + aliases { + usb0 = &usbotg1; + usb1 = &usbotg2; + usb2 = &usbh; + }; + cpus { cpu0: cpu@0 { clock-frequency = <996000000>; diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi index b58262acba11..251007a7b836 100644 --- a/arch/arm/boot/dts/imx7s.dtsi +++ b/arch/arm/boot/dts/imx7s.dtsi @@ -47,6 +47,8 @@ spi1 = &ecspi2; spi2 = &ecspi3; spi3 = &ecspi4; + usb0 = &usbotg1; + usb1 = &usbh; }; cpus { -- cgit v1.2.3-59-g8ed1b From 895387231e54e83bd0779afdea125df4d79c91a4 Mon Sep 17 00:00:00 2001 From: Jonathan Neuschäfer Date: Sat, 31 Oct 2020 22:07:29 +0100 Subject: ARM: dts: imx50-kobo-aura: Add 'grp' suffix to pinctrl node names MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit i.MX pinctrl group nodes should have names that ends with 'grp'. Reported-by: Krzysztof Kozlowski Signed-off-by: Jonathan Neuschäfer Reviewed-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx50-kobo-aura.dts | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx50-kobo-aura.dts b/arch/arm/boot/dts/imx50-kobo-aura.dts index a0eaf869b913..53b3995d37e7 100644 --- a/arch/arm/boot/dts/imx50-kobo-aura.dts +++ b/arch/arm/boot/dts/imx50-kobo-aura.dts @@ -139,7 +139,7 @@ }; &iomuxc { - pinctrl_gpiokeys: gpiokeys { + pinctrl_gpiokeys: gpiokeysgrp { fsl,pins = < MX50_PAD_CSPI_MISO__GPIO4_10 0x0 MX50_PAD_SD2_D7__GPIO5_15 0x0 @@ -147,34 +147,34 @@ >; }; - pinctrl_i2c1: i2c1 { + pinctrl_i2c1: i2c1grp { fsl,pins = < MX50_PAD_I2C1_SCL__I2C1_SCL 0x400001fd MX50_PAD_I2C1_SDA__I2C1_SDA 0x400001fd >; }; - pinctrl_i2c2: i2c2 { + pinctrl_i2c2: i2c2grp { fsl,pins = < MX50_PAD_I2C2_SCL__I2C2_SCL 0x400001fd MX50_PAD_I2C2_SDA__I2C2_SDA 0x400001fd >; }; - pinctrl_i2c3: i2c3 { + pinctrl_i2c3: i2c3grp { fsl,pins = < MX50_PAD_I2C3_SCL__I2C3_SCL 0x400001fd MX50_PAD_I2C3_SDA__I2C3_SDA 0x400001fd >; }; - pinctrl_leds: leds { + pinctrl_leds: ledsgrp { fsl,pins = < MX50_PAD_PWM1__GPIO6_24 0x0 >; }; - pinctrl_sd1: sd1 { + pinctrl_sd1: sd1grp { fsl,pins = < MX50_PAD_SD1_CMD__ESDHC1_CMD 0x1e4 MX50_PAD_SD1_CLK__ESDHC1_CLK 0xd4 @@ -187,7 +187,7 @@ >; }; - pinctrl_sd2: sd2 { + pinctrl_sd2: sd2grp { fsl,pins = < MX50_PAD_SD2_CMD__ESDHC2_CMD 0x1e4 MX50_PAD_SD2_CLK__ESDHC2_CLK 0xd4 @@ -198,19 +198,19 @@ >; }; - pinctrl_sd2_reset: sd2-reset { + pinctrl_sd2_reset: sd2-resetgrp { fsl,pins = < MX50_PAD_ECSPI2_MOSI__GPIO4_17 0x0 >; }; - pinctrl_sd2_vmmc: sd2-vmmc { + pinctrl_sd2_vmmc: sd2-vmmcgrp { fsl,pins = < MX50_PAD_ECSPI1_SCLK__GPIO4_12 0x0 >; }; - pinctrl_sd3: sd3 { + pinctrl_sd3: sd3grp { fsl,pins = < MX50_PAD_SD3_CMD__ESDHC3_CMD 0x1e4 MX50_PAD_SD3_CLK__ESDHC3_CLK 0xd4 @@ -225,14 +225,14 @@ >; }; - pinctrl_uart2: uart2 { + pinctrl_uart2: uart2grp { fsl,pins = < MX50_PAD_UART2_TXD__UART2_TXD_MUX 0x1e4 MX50_PAD_UART2_RXD__UART2_RXD_MUX 0x1e4 >; }; - pinctrl_usbphy: usbphy { + pinctrl_usbphy: usbphygrp { fsl,pins = < MX50_PAD_ECSPI2_SS0__GPIO4_19 0x0 >; -- cgit v1.2.3-59-g8ed1b From 7604ce70b8f675582ae68064e125be4f5174dec0 Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Tue, 27 Oct 2020 10:25:02 +0100 Subject: USB: serial: keyspan_pda: clean up xircom/entrega support Drop the separate Kconfig symbol for Xircom / Entrega and always include support in the keyspan_pda driver. Note that all configs that enabled CONFIG_USB_SERIAL_XIRCOM also enable CONFIG_USB_SERIAL_KEYSPAN_PDA. Acked-by: Sebastian Andrzej Siewior Reviewed-by: Greg Kroah-Hartman Signed-off-by: Johan Hovold --- arch/arm/configs/badge4_defconfig | 1 - arch/arm/configs/corgi_defconfig | 1 - arch/arm/configs/pxa_defconfig | 1 - arch/arm/configs/spitz_defconfig | 1 - arch/mips/configs/mtx1_defconfig | 1 - arch/mips/configs/rm200_defconfig | 1 - arch/powerpc/configs/g5_defconfig | 1 - arch/powerpc/configs/ppc6xx_defconfig | 1 - drivers/usb/serial/Kconfig | 19 +++------- drivers/usb/serial/Makefile | 1 - drivers/usb/serial/keyspan_pda.c | 68 +++++------------------------------ 11 files changed, 13 insertions(+), 83 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/configs/badge4_defconfig b/arch/arm/configs/badge4_defconfig index ef484c4cfd1a..d9119da65f48 100644 --- a/arch/arm/configs/badge4_defconfig +++ b/arch/arm/configs/badge4_defconfig @@ -89,7 +89,6 @@ CONFIG_USB_SERIAL_KEYSPAN=m CONFIG_USB_SERIAL_MCT_U232=m CONFIG_USB_SERIAL_PL2303=m CONFIG_USB_SERIAL_CYBERJACK=m -CONFIG_USB_SERIAL_XIRCOM=m CONFIG_USB_SERIAL_OMNINET=m CONFIG_EXT2_FS=m CONFIG_EXT3_FS=m diff --git a/arch/arm/configs/corgi_defconfig b/arch/arm/configs/corgi_defconfig index 4fec2ec379ad..911e880f06ed 100644 --- a/arch/arm/configs/corgi_defconfig +++ b/arch/arm/configs/corgi_defconfig @@ -191,7 +191,6 @@ CONFIG_USB_SERIAL_PL2303=m CONFIG_USB_SERIAL_SAFE=m CONFIG_USB_SERIAL_TI=m CONFIG_USB_SERIAL_CYBERJACK=m -CONFIG_USB_SERIAL_XIRCOM=m CONFIG_USB_SERIAL_OMNINET=m CONFIG_USB_EMI62=m CONFIG_USB_EMI26=m diff --git a/arch/arm/configs/pxa_defconfig b/arch/arm/configs/pxa_defconfig index d7b9eaf4783c..8654ece13004 100644 --- a/arch/arm/configs/pxa_defconfig +++ b/arch/arm/configs/pxa_defconfig @@ -574,7 +574,6 @@ CONFIG_USB_SERIAL_PL2303=m CONFIG_USB_SERIAL_SAFE=m CONFIG_USB_SERIAL_TI=m CONFIG_USB_SERIAL_CYBERJACK=m -CONFIG_USB_SERIAL_XIRCOM=m CONFIG_USB_SERIAL_OMNINET=m CONFIG_USB_EMI62=m CONFIG_USB_EMI26=m diff --git a/arch/arm/configs/spitz_defconfig b/arch/arm/configs/spitz_defconfig index a1cdbfa064c5..8b2c14424927 100644 --- a/arch/arm/configs/spitz_defconfig +++ b/arch/arm/configs/spitz_defconfig @@ -185,7 +185,6 @@ CONFIG_USB_SERIAL_PL2303=m CONFIG_USB_SERIAL_SAFE=m CONFIG_USB_SERIAL_TI=m CONFIG_USB_SERIAL_CYBERJACK=m -CONFIG_USB_SERIAL_XIRCOM=m CONFIG_USB_SERIAL_OMNINET=m CONFIG_USB_EMI62=m CONFIG_USB_EMI26=m diff --git a/arch/mips/configs/mtx1_defconfig b/arch/mips/configs/mtx1_defconfig index 914af125a7fa..9750bcc38f05 100644 --- a/arch/mips/configs/mtx1_defconfig +++ b/arch/mips/configs/mtx1_defconfig @@ -565,7 +565,6 @@ CONFIG_USB_SERIAL_SAFE=m CONFIG_USB_SERIAL_SIERRAWIRELESS=m CONFIG_USB_SERIAL_TI=m CONFIG_USB_SERIAL_CYBERJACK=m -CONFIG_USB_SERIAL_XIRCOM=m CONFIG_USB_SERIAL_OPTION=m CONFIG_USB_SERIAL_OMNINET=m CONFIG_USB_EMI62=m diff --git a/arch/mips/configs/rm200_defconfig b/arch/mips/configs/rm200_defconfig index 30d7c3db884e..3dc2da2bee0d 100644 --- a/arch/mips/configs/rm200_defconfig +++ b/arch/mips/configs/rm200_defconfig @@ -311,7 +311,6 @@ CONFIG_USB_SERIAL_PL2303=m CONFIG_USB_SERIAL_SAFE=m CONFIG_USB_SERIAL_SAFE_PADDED=y CONFIG_USB_SERIAL_CYBERJACK=m -CONFIG_USB_SERIAL_XIRCOM=m CONFIG_USB_SERIAL_OMNINET=m CONFIG_USB_LEGOTOWER=m CONFIG_USB_LCD=m diff --git a/arch/powerpc/configs/g5_defconfig b/arch/powerpc/configs/g5_defconfig index 1c674c4c1d86..1de0dbf6cbba 100644 --- a/arch/powerpc/configs/g5_defconfig +++ b/arch/powerpc/configs/g5_defconfig @@ -194,7 +194,6 @@ CONFIG_USB_SERIAL_SAFE=m CONFIG_USB_SERIAL_SAFE_PADDED=y CONFIG_USB_SERIAL_TI=m CONFIG_USB_SERIAL_CYBERJACK=m -CONFIG_USB_SERIAL_XIRCOM=m CONFIG_USB_SERIAL_OMNINET=m CONFIG_USB_APPLEDISPLAY=m CONFIG_EXT2_FS=y diff --git a/arch/powerpc/configs/ppc6xx_defconfig b/arch/powerpc/configs/ppc6xx_defconfig index 66e9a0fd64ff..ac92cbe1f581 100644 --- a/arch/powerpc/configs/ppc6xx_defconfig +++ b/arch/powerpc/configs/ppc6xx_defconfig @@ -911,7 +911,6 @@ CONFIG_USB_SERIAL_SAFE_PADDED=y CONFIG_USB_SERIAL_SIERRAWIRELESS=m CONFIG_USB_SERIAL_TI=m CONFIG_USB_SERIAL_CYBERJACK=m -CONFIG_USB_SERIAL_XIRCOM=m CONFIG_USB_SERIAL_OPTION=m CONFIG_USB_SERIAL_OMNINET=m CONFIG_USB_SERIAL_DEBUG=m diff --git a/drivers/usb/serial/Kconfig b/drivers/usb/serial/Kconfig index 4007fa25a8ff..a21ff5ab6df9 100644 --- a/drivers/usb/serial/Kconfig +++ b/drivers/usb/serial/Kconfig @@ -298,12 +298,12 @@ config USB_SERIAL_IUU module will be called iuu_phoenix.o config USB_SERIAL_KEYSPAN_PDA - tristate "USB Keyspan PDA Single Port Serial Driver" + tristate "USB Keyspan PDA / Xircom Single Port Serial Driver" select USB_EZUSB_FX2 help - Say Y here if you want to use a Keyspan PDA single port USB to - serial converter device. This driver makes use of firmware - developed from scratch by Brian Warner. + Say Y here if you want to use a Keyspan PDA, Xircom or Entrega single + port USB to serial converter device. This driver makes use of + firmware developed from scratch by Brian Warner. To compile this driver as a module, choose M here: the module will be called keyspan_pda. @@ -538,17 +538,6 @@ config USB_SERIAL_CYBERJACK If unsure, say N. -config USB_SERIAL_XIRCOM - tristate "USB Xircom / Entrega Single Port Serial Driver" - select USB_EZUSB_FX2 - help - Say Y here if you want to use a Xircom or Entrega single port USB to - serial converter device. This driver makes use of firmware - developed from scratch by Brian Warner. - - To compile this driver as a module, choose M here: the - module will be called keyspan_pda. - config USB_SERIAL_WWAN tristate diff --git a/drivers/usb/serial/Makefile b/drivers/usb/serial/Makefile index 2d491e434f11..50c53aed787a 100644 --- a/drivers/usb/serial/Makefile +++ b/drivers/usb/serial/Makefile @@ -61,5 +61,4 @@ obj-$(CONFIG_USB_SERIAL_UPD78F0730) += upd78f0730.o obj-$(CONFIG_USB_SERIAL_VISOR) += visor.o obj-$(CONFIG_USB_SERIAL_WISHBONE) += wishbone-serial.o obj-$(CONFIG_USB_SERIAL_WHITEHEAT) += whiteheat.o -obj-$(CONFIG_USB_SERIAL_XIRCOM) += keyspan_pda.o obj-$(CONFIG_USB_SERIAL_XSENS_MT) += xsens_mt.o diff --git a/drivers/usb/serial/keyspan_pda.c b/drivers/usb/serial/keyspan_pda.c index aa19dd181e42..f102dbf83492 100644 --- a/drivers/usb/serial/keyspan_pda.c +++ b/drivers/usb/serial/keyspan_pda.c @@ -26,18 +26,6 @@ #include #include -/* make a simple define to handle if we are compiling keyspan_pda or xircom support */ -#if IS_ENABLED(CONFIG_USB_SERIAL_KEYSPAN_PDA) - #define KEYSPAN -#else - #undef KEYSPAN -#endif -#if IS_ENABLED(CONFIG_USB_SERIAL_XIRCOM) - #define XIRCOM -#else - #undef XIRCOM -#endif - #define DRIVER_AUTHOR "Brian Warner , Johan Hovold " #define DRIVER_DESC "USB Keyspan PDA Converter driver" @@ -64,18 +52,13 @@ static int keyspan_pda_write_start(struct usb_serial_port *port); #define ENTREGA_FAKE_ID 0x8093 static const struct usb_device_id id_table_combined[] = { -#ifdef KEYSPAN { USB_DEVICE(KEYSPAN_VENDOR_ID, KEYSPAN_PDA_FAKE_ID) }, -#endif -#ifdef XIRCOM { USB_DEVICE(XIRCOM_VENDOR_ID, XIRCOM_FAKE_ID) }, { USB_DEVICE(XIRCOM_VENDOR_ID, XIRCOM_FAKE_ID_2) }, { USB_DEVICE(ENTREGA_VENDOR_ID, ENTREGA_FAKE_ID) }, -#endif { USB_DEVICE(KEYSPAN_VENDOR_ID, KEYSPAN_PDA_ID) }, { } /* Terminating entry */ }; - MODULE_DEVICE_TABLE(usb, id_table_combined); static const struct usb_device_id id_table_std[] = { @@ -83,21 +66,13 @@ static const struct usb_device_id id_table_std[] = { { } /* Terminating entry */ }; -#ifdef KEYSPAN static const struct usb_device_id id_table_fake[] = { { USB_DEVICE(KEYSPAN_VENDOR_ID, KEYSPAN_PDA_FAKE_ID) }, - { } /* Terminating entry */ -}; -#endif - -#ifdef XIRCOM -static const struct usb_device_id id_table_fake_xircom[] = { { USB_DEVICE(XIRCOM_VENDOR_ID, XIRCOM_FAKE_ID) }, { USB_DEVICE(XIRCOM_VENDOR_ID, XIRCOM_FAKE_ID_2) }, { USB_DEVICE(ENTREGA_VENDOR_ID, ENTREGA_FAKE_ID) }, - { } + { } /* Terminating entry */ }; -#endif static int keyspan_pda_get_write_room(struct keyspan_pda_private *priv) { @@ -647,22 +622,21 @@ static void keyspan_pda_close(struct usb_serial_port *port) /* download the firmware to a "fake" device (pre-renumeration) */ static int keyspan_pda_fake_startup(struct usb_serial *serial) { + unsigned int vid = le16_to_cpu(serial->dev->descriptor.idVendor); const char *fw_name; /* download the firmware here ... */ ezusb_fx1_set_reset(serial->dev, 1); - if (0) { ; } -#ifdef KEYSPAN - else if (le16_to_cpu(serial->dev->descriptor.idVendor) == KEYSPAN_VENDOR_ID) + switch (vid) { + case KEYSPAN_VENDOR_ID: fw_name = "keyspan_pda/keyspan_pda.fw"; -#endif -#ifdef XIRCOM - else if ((le16_to_cpu(serial->dev->descriptor.idVendor) == XIRCOM_VENDOR_ID) || - (le16_to_cpu(serial->dev->descriptor.idVendor) == ENTREGA_VENDOR_ID)) + break; + case XIRCOM_VENDOR_ID: + case ENTREGA_VENDOR_ID: fw_name = "keyspan_pda/xircom_pgs.fw"; -#endif - else { + break; + default: dev_err(&serial->dev->dev, "%s: unknown vendor, aborting.\n", __func__); return -ENODEV; @@ -681,12 +655,8 @@ static int keyspan_pda_fake_startup(struct usb_serial *serial) return 1; } -#ifdef KEYSPAN MODULE_FIRMWARE("keyspan_pda/keyspan_pda.fw"); -#endif -#ifdef XIRCOM MODULE_FIRMWARE("keyspan_pda/xircom_pgs.fw"); -#endif static int keyspan_pda_port_probe(struct usb_serial_port *port) { @@ -716,7 +686,6 @@ static int keyspan_pda_port_remove(struct usb_serial_port *port) return 0; } -#ifdef KEYSPAN static struct usb_serial_driver keyspan_pda_fake_device = { .driver = { .owner = THIS_MODULE, @@ -727,20 +696,6 @@ static struct usb_serial_driver keyspan_pda_fake_device = { .num_ports = 1, .attach = keyspan_pda_fake_startup, }; -#endif - -#ifdef XIRCOM -static struct usb_serial_driver xircom_pgs_fake_device = { - .driver = { - .owner = THIS_MODULE, - .name = "xircom_no_firm", - }, - .description = "Xircom / Entrega PGS - (prerenumeration)", - .id_table = id_table_fake_xircom, - .num_ports = 1, - .attach = keyspan_pda_fake_startup, -}; -#endif static struct usb_serial_driver keyspan_pda_device = { .driver = { @@ -770,12 +725,7 @@ static struct usb_serial_driver keyspan_pda_device = { static struct usb_serial_driver * const serial_drivers[] = { &keyspan_pda_device, -#ifdef KEYSPAN &keyspan_pda_fake_device, -#endif -#ifdef XIRCOM - &xircom_pgs_fake_device, -#endif NULL }; -- cgit v1.2.3-59-g8ed1b From 007fda302d771d818347ce85043ae8681b87b6e0 Mon Sep 17 00:00:00 2001 From: Marek Szyprowski Date: Tue, 3 Nov 2020 15:02:14 +0100 Subject: ARM: dts: exynos: Enable DWC2 dual-role support on OdroidU3+ boards MicroUSB port on OdroidU3+ boards can operate both as peripheral or as host port. Till now it was configured as pheriperal only port, but it turned out that the DWC2 driver code already handles everything needed to support USB role-switch, so switch it to dual-role (OTG) mode. This has no effect on OdroidU3 (without 'plus') and OdroidX2, which doesn't have USB needed ID pin and VBUS wiring. Those will still operate correctly in pheriperal mode only. Signed-off-by: Marek Szyprowski Tested-by: Anand Moon Link: https://lore.kernel.org/r/20201103140214.21690-1-m.szyprowski@samsung.com Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos4412-odroid-common.dtsi | 1 - arch/arm/boot/dts/exynos4412-odroidu3.dts | 14 ++++++++++++++ arch/arm/boot/dts/exynos4412-odroidx.dts | 4 ++++ 3 files changed, 18 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi index 1ca9d8b5f868..4a67390426b6 100644 --- a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi +++ b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi @@ -256,7 +256,6 @@ }; &hsotg { - dr_mode = "peripheral"; status = "okay"; vusb_d-supply = <&ldo15_reg>; vusb_a-supply = <&ldo12_reg>; diff --git a/arch/arm/boot/dts/exynos4412-odroidu3.dts b/arch/arm/boot/dts/exynos4412-odroidu3.dts index b8549d846f86..3bc83d63de6b 100644 --- a/arch/arm/boot/dts/exynos4412-odroidu3.dts +++ b/arch/arm/boot/dts/exynos4412-odroidu3.dts @@ -21,6 +21,15 @@ reg = <0x40000000 0x7FF00000>; }; + vbus_otg_reg: regulator-1 { + compatible = "regulator-fixed"; + regulator-name = "VBUS_VDD_5.0V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpl2 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + leds { compatible = "gpio-leds"; led1 { @@ -105,6 +114,11 @@ phy-names = "hsic0", "hsic1"; }; +&hsotg { + dr_mode = "otg"; + vbus-supply = <&vbus_otg_reg>; +}; + &sound { model = "Odroid-U3"; samsung,audio-widgets = diff --git a/arch/arm/boot/dts/exynos4412-odroidx.dts b/arch/arm/boot/dts/exynos4412-odroidx.dts index 46381e9097f4..d6ee62bf336c 100644 --- a/arch/arm/boot/dts/exynos4412-odroidx.dts +++ b/arch/arm/boot/dts/exynos4412-odroidx.dts @@ -76,6 +76,10 @@ }; }; +&hsotg { + dr_mode = "peripheral"; +}; + &mshc_0 { vqmmc-supply = <&buck8_reg>; }; -- cgit v1.2.3-59-g8ed1b From 9ef3a2c5859e02afc67f71cd31ff5177771b48c1 Mon Sep 17 00:00:00 2001 From: Łukasz Stelmach Date: Tue, 3 Nov 2020 19:44:09 +0100 Subject: ARM: dts: exynos: Add Ethernet interface description for Odroid XU3 Lite MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add Ethernet interface description for Odroid XU3 Lite. Add an alias to enable bootloaders to find the Ethernet interface and assign a MAC address. Signed-off-by: Łukasz Stelmach Link: https://lore.kernel.org/r/20201103184412.18874-4-l.stelmach@samsung.com Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts b/arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts index 98feecad5489..62c5928aa994 100644 --- a/arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts +++ b/arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts @@ -16,6 +16,10 @@ / { model = "Hardkernel Odroid XU3 Lite"; compatible = "hardkernel,odroid-xu3-lite", "samsung,exynos5800", "samsung,exynos5"; + + aliases { + ethernet = ðernet; + }; }; &arm_a7_pmu { @@ -103,3 +107,21 @@ &usbdrd_dwc3_1 { dr_mode = "peripheral"; }; + +&usbhost2 { + #address-cells = <1>; + #size-cells = <0>; + + hub@1 { + compatible = "usb0424,9514"; + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + ethernet: usbether@1 { + compatible = "usb0424,ec00"; + reg = <1>; + local-mac-address = [00 00 00 00 00 00]; /* Filled in by a bootloader */ + }; + }; +}; -- cgit v1.2.3-59-g8ed1b From dff7ae5c50ebc69929973f948d87de6c661ef42d Mon Sep 17 00:00:00 2001 From: Łukasz Stelmach Date: Tue, 3 Nov 2020 19:44:10 +0100 Subject: ARM: dts: exynos: Add Ethernet interface description for Odroid XU MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add Ethernet interface description for Odroid XU. Add an alias to enable bootloaders to find the Ethernet interface and assign a MAC address. Signed-off-by: Łukasz Stelmach Link: https://lore.kernel.org/r/20201103184412.18874-5-l.stelmach@samsung.com Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos5410-odroidxu.dts | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/exynos5410-odroidxu.dts b/arch/arm/boot/dts/exynos5410-odroidxu.dts index 40cb0727aea1..949c0721cdb4 100644 --- a/arch/arm/boot/dts/exynos5410-odroidxu.dts +++ b/arch/arm/boot/dts/exynos5410-odroidxu.dts @@ -19,6 +19,10 @@ model = "Hardkernel Odroid XU"; compatible = "hardkernel,odroid-xu", "samsung,exynos5410", "samsung,exynos5"; + aliases { + ethernet = ðernet; + }; + memory@40000000 { device_type = "memory"; reg = <0x40000000 0x7ea00000>; @@ -665,3 +669,14 @@ vdd33-supply = <&ldo12_reg>; vdd10-supply = <&ldo15_reg>; }; + +&usbhost2 { + #address-cells = <1>; + #size-cells = <0>; + + ethernet: usbether@2 { + compatible = "usb0424,9730"; + reg = <2>; + local-mac-address = [00 00 00 00 00 00]; /* Filled in by a bootloader */ + }; +}; -- cgit v1.2.3-59-g8ed1b From 6eff260412bdf74ede126016f5e0026b7861db77 Mon Sep 17 00:00:00 2001 From: Łukasz Stelmach Date: Tue, 3 Nov 2020 19:44:11 +0100 Subject: ARM: dts: exynos: Add Ethernet interface description for Odroid U3 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add Ethernet interface description for Odroid U3. Add an alias to enable bootloaders to find the Ethernet interface and assign a MAC address. Signed-off-by: Łukasz Stelmach Link: https://lore.kernel.org/r/20201103184412.18874-6-l.stelmach@samsung.com Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos4412-odroidu3.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/exynos4412-odroidu3.dts b/arch/arm/boot/dts/exynos4412-odroidu3.dts index 3bc83d63de6b..efaf7533e84f 100644 --- a/arch/arm/boot/dts/exynos4412-odroidu3.dts +++ b/arch/arm/boot/dts/exynos4412-odroidu3.dts @@ -16,6 +16,10 @@ model = "Hardkernel ODROID-U3 board based on Exynos4412"; compatible = "hardkernel,odroid-u3", "samsung,exynos4412", "samsung,exynos4"; + aliases { + ethernet = ðernet; + }; + memory@40000000 { device_type = "memory"; reg = <0x40000000 0x7FF00000>; @@ -110,8 +114,16 @@ }; &ehci { + #address-cells = <1>; + #size-cells = <0>; phys = <&exynos_usbphy 2>, <&exynos_usbphy 3>; phy-names = "hsic0", "hsic1"; + + ethernet: usbether@2 { + compatible = "usb0424,9730"; + reg = <2>; + local-mac-address = [00 00 00 00 00 00]; /* Filled in by a bootloader */ + }; }; &hsotg { -- cgit v1.2.3-59-g8ed1b From d9e1af3a13947742cd8bf8007ba22d977a6b170e Mon Sep 17 00:00:00 2001 From: Łukasz Stelmach Date: Tue, 3 Nov 2020 19:44:12 +0100 Subject: ARM: dts: exynos: Add Ethernet interface description for Odroid X/X2 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add Ethernet interface description for Odroid X/X2. Add an alias to enable bootloaders to find the Ethernet interface and assign a MAC address. Signed-off-by: Łukasz Stelmach Link: https://lore.kernel.org/r/20201103184412.18874-7-l.stelmach@samsung.com Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos4412-odroidx.dts | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/exynos4412-odroidx.dts b/arch/arm/boot/dts/exynos4412-odroidx.dts index d6ee62bf336c..0e9d626e740a 100644 --- a/arch/arm/boot/dts/exynos4412-odroidx.dts +++ b/arch/arm/boot/dts/exynos4412-odroidx.dts @@ -15,6 +15,10 @@ model = "Hardkernel ODROID-X board based on Exynos4412"; compatible = "hardkernel,odroid-x", "samsung,exynos4412", "samsung,exynos4"; + aliases { + ethernet = ðernet; + }; + memory@40000000 { device_type = "memory"; reg = <0x40000000 0x3FF00000>; @@ -60,8 +64,30 @@ }; &ehci { + #address-cells = <1>; + #size-cells = <0>; phys = <&exynos_usbphy 2>; phy-names = "hsic0"; + + hub@2 { + compatible = "usb0424,3503"; + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + + hub@1 { + compatible = "usb0424,9514"; + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + ethernet: usbether@1 { + compatible = "usb0424,ec00"; + reg = <1>; + local-mac-address = [00 00 00 00 00 00]; /* Filled in by a bootloader */ + }; + }; + }; }; &gpio_keys { -- cgit v1.2.3-59-g8ed1b From 8902a6642771616901ea3f5341926602908eaf3a Mon Sep 17 00:00:00 2001 From: Łukasz Stelmach Date: Thu, 1 Oct 2020 15:52:54 +0200 Subject: ARM: dts: exynos: Add a placeholder for a MAC address MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add a placeholder for a MAC address. A bootloader may fill it to set the MAC address and override EEPROM settings. Signed-off-by: Łukasz Stelmach Link: https://lore.kernel.org/r/20201001135254.28178-1-l.stelmach@samsung.com Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos5422-odroidxu3.dts | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3.dts b/arch/arm/boot/dts/exynos5422-odroidxu3.dts index 7c588407f931..53aee3d56f6a 100644 --- a/arch/arm/boot/dts/exynos5422-odroidxu3.dts +++ b/arch/arm/boot/dts/exynos5422-odroidxu3.dts @@ -70,3 +70,21 @@ &usbdrd_dwc3_1 { dr_mode = "peripheral"; }; + +&usbhost2 { + #address-cells = <1>; + #size-cells = <0>; + + hub@1 { + compatible = "usb8087,0024"; + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + ethernet: usbether@1 { + compatible = "usb0c45,6310"; + reg = <1>; + local-mac-address = [00 00 00 00 00 00]; /* Filled in by a bootloader */ + }; + }; +}; -- cgit v1.2.3-59-g8ed1b From a2715fbdc6fc387e85211df917a4778761ec693d Mon Sep 17 00:00:00 2001 From: Horia Geantă Date: Wed, 28 Oct 2020 11:03:20 +0200 Subject: crypto: arm/aes-neonbs - fix usage of cbc(aes) fallback MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Loading the module deadlocks since: -local cbc(aes) implementation needs a fallback and -crypto API tries to find one but the request_module() resolves back to the same module Fix this by changing the module alias for cbc(aes) and using the NEED_FALLBACK flag when requesting for a fallback algorithm. Fixes: 00b99ad2bac2 ("crypto: arm/aes-neonbs - Use generic cbc encryption path") Signed-off-by: Horia Geantă Signed-off-by: Herbert Xu --- arch/arm/crypto/aes-neonbs-glue.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/crypto/aes-neonbs-glue.c b/arch/arm/crypto/aes-neonbs-glue.c index bda8bf17631e..f70af1d0514b 100644 --- a/arch/arm/crypto/aes-neonbs-glue.c +++ b/arch/arm/crypto/aes-neonbs-glue.c @@ -19,7 +19,7 @@ MODULE_AUTHOR("Ard Biesheuvel "); MODULE_LICENSE("GPL v2"); MODULE_ALIAS_CRYPTO("ecb(aes)"); -MODULE_ALIAS_CRYPTO("cbc(aes)"); +MODULE_ALIAS_CRYPTO("cbc(aes)-all"); MODULE_ALIAS_CRYPTO("ctr(aes)"); MODULE_ALIAS_CRYPTO("xts(aes)"); @@ -191,7 +191,8 @@ static int cbc_init(struct crypto_skcipher *tfm) struct aesbs_cbc_ctx *ctx = crypto_skcipher_ctx(tfm); unsigned int reqsize; - ctx->enc_tfm = crypto_alloc_skcipher("cbc(aes)", 0, CRYPTO_ALG_ASYNC); + ctx->enc_tfm = crypto_alloc_skcipher("cbc(aes)", 0, CRYPTO_ALG_ASYNC | + CRYPTO_ALG_NEED_FALLBACK); if (IS_ERR(ctx->enc_tfm)) return PTR_ERR(ctx->enc_tfm); @@ -441,7 +442,8 @@ static struct skcipher_alg aes_algs[] = { { .base.cra_blocksize = AES_BLOCK_SIZE, .base.cra_ctxsize = sizeof(struct aesbs_cbc_ctx), .base.cra_module = THIS_MODULE, - .base.cra_flags = CRYPTO_ALG_INTERNAL, + .base.cra_flags = CRYPTO_ALG_INTERNAL | + CRYPTO_ALG_NEED_FALLBACK, .min_keysize = AES_MIN_KEY_SIZE, .max_keysize = AES_MAX_KEY_SIZE, -- cgit v1.2.3-59-g8ed1b From 33958b22f3775ed8ac6594f89fff1ed150bed3fd Mon Sep 17 00:00:00 2001 From: Matteo Scordino Date: Thu, 5 Nov 2020 18:32:29 +0000 Subject: ARM: dts: sun8i: s3: Add dtsi for the Elimo Impetus SoM The Elimo Engineering Impetus is an Open Source Hardware System-on-Module based on the SoChip S3 SoC. It is meant for integration into carrier boards or, more generally, larger designs, and uses an M2 connector to facilitate that. Interfaces on the M.2/NGFF 42mm connector: WiFi IEEE 802. 11abgn (on-module Realtek) Bluetooth 4.2/BLE (on-module Realtek) RGB LCD Interface (on-module connector) MIPI Camera Interface (on-module connector) IEEE 802. 3u Ethernet MAC (external connecto) USB2.0 (Host, Device, OTG) (external connector) Audio Line In/Out (external connector) Signed-off-by: Matteo Scordino Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20201105183231.12952-2-matteo.scordino@gmail.com --- arch/arm/boot/dts/sun8i-s3-elimo-impetus.dtsi | 44 +++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) create mode 100644 arch/arm/boot/dts/sun8i-s3-elimo-impetus.dtsi (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun8i-s3-elimo-impetus.dtsi b/arch/arm/boot/dts/sun8i-s3-elimo-impetus.dtsi new file mode 100644 index 000000000000..24d507cdbcf9 --- /dev/null +++ b/arch/arm/boot/dts/sun8i-s3-elimo-impetus.dtsi @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2020 Matteo Scordino + */ + +/dts-v1/; +#include "sun8i-v3.dtsi" +#include "sunxi-common-regulators.dtsi" + +/ { + model = "Elimo Impetus SoM"; + compatible = "elimo,impetus", "sochip,s3", "allwinner,sun8i-v3"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&mmc0 { + broken-cd; + bus-width = <4>; + vmmc-supply = <®_vcc3v3>; + status = "okay"; +}; + +&uart0 { + pinctrl-0 = <&uart0_pb_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + +&usbphy { + usb0_id_det-gpio = <&pio 5 6 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; -- cgit v1.2.3-59-g8ed1b From da42b98d5c7d5a30d963633a964586cb68a5c886 Mon Sep 17 00:00:00 2001 From: Matteo Scordino Date: Thu, 5 Nov 2020 18:32:31 +0000 Subject: ARM: dts: sun8i: s3: Add dts for the Elimo Initium SBC The Elimo Engineering Initium is an Open Source Hardware Single Board Computer based on the Elimo Impetus SoM. It is meant as the first development platform for the Impetus, providing convenient access to the peripherals on the Impetus. It provides: USB-C power input UART-to-USB bridge on the USB-C connector, connected to UART1 USB-A connector for USB2.0 (Host, Device, OTG) Audio Line In/Out Pin header to access all signals on the M2 connector of the SoM Signed-off-by: Matteo Scordino Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20201105183231.12952-4-matteo.scordino@gmail.com --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/sun8i-s3-elimo-initium.dts | 29 ++++++++++++++++++++++++++++ 2 files changed, 30 insertions(+) create mode 100644 arch/arm/boot/dts/sun8i-s3-elimo-initium.dts (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 4f0adfead547..50e438ab8a00 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1208,6 +1208,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \ sun8i-r16-nintendo-super-nes-classic.dtb \ sun8i-r16-parrot.dtb \ sun8i-r40-bananapi-m2-ultra.dtb \ + sun8i-s3-elimo-initium.dtb \ sun8i-s3-lichee-zero-plus.dtb \ sun8i-s3-pinecube.dtb \ sun8i-t3-cqa3t-bv3.dtb \ diff --git a/arch/arm/boot/dts/sun8i-s3-elimo-initium.dts b/arch/arm/boot/dts/sun8i-s3-elimo-initium.dts new file mode 100644 index 000000000000..039677c2cc65 --- /dev/null +++ b/arch/arm/boot/dts/sun8i-s3-elimo-initium.dts @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2020 Matteo Scordino + */ + +/dts-v1/; +#include "sun8i-s3-elimo-impetus.dtsi" + +/ { + model = "Elimo Initium"; + compatible = "elimo,initium", "elimo,impetus", "sochip,s3", + "allwinner,sun8i-v3"; + + aliases { + serial1 = &uart1; + }; +}; + +&uart1 { + pinctrl-0 = <&uart1_pg_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&emac { + phy-handle = <&int_mii_phy>; + phy-mode = "mii"; + status = "okay"; +}; -- cgit v1.2.3-59-g8ed1b From 9340c293ebf0687d53a52c710a8e6fe80bfd6b6b Mon Sep 17 00:00:00 2001 From: Yu-Tung Chang Date: Mon, 2 Nov 2020 18:01:57 +0800 Subject: ARM: dts: sun8i: h3: Add initial NanoPi R1 support The NanoPi R1 is a complete open source board developed by FriendlyElec for makers, hobbyists, fans and etc. NanoPi R1 key features - Allwinner H3, Quad-core Cortex-A7@1.2GHz - 512MB/1GB DDR3 RAM - 8GB eMMC - microSD slot - 10/100/1000M Ethernet x 1 - 10/100 Ethernet x 1 - Wifi 802.11b/g/n - Bluetooth 4.0 - Serial Debug Port - 5V 2A DC power-supply Signed-off-by: Yu-Tung Chang Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20201102100157.85801-2-mtwget@gmail.com --- Documentation/devicetree/bindings/arm/sunxi.yaml | 5 + arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/sun8i-h3-nanopi-r1.dts | 169 +++++++++++++++++++++++ 3 files changed, 175 insertions(+) create mode 100644 arch/arm/boot/dts/sun8i-h3-nanopi-r1.dts (limited to 'arch/arm') diff --git a/Documentation/devicetree/bindings/arm/sunxi.yaml b/Documentation/devicetree/bindings/arm/sunxi.yaml index ef2ce3bd2bed..93e608aecae2 100644 --- a/Documentation/devicetree/bindings/arm/sunxi.yaml +++ b/Documentation/devicetree/bindings/arm/sunxi.yaml @@ -264,6 +264,11 @@ properties: - const: friendlyarm,nanopi-neo-plus2 - const: allwinner,sun50i-h5 + - description: FriendlyARM NanoPi R1 + items: + - const: friendlyarm,nanopi-r1 + - const: allwinner,sun8i-h3 + - description: FriendlyARM ZeroPi items: - const: friendlyarm,zeropi diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 50e438ab8a00..ad41489e591d 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1192,6 +1192,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \ sun8i-h3-nanopi-m1-plus.dtb \ sun8i-h3-nanopi-neo.dtb \ sun8i-h3-nanopi-neo-air.dtb \ + sun8i-h3-nanopi-r1.dtb \ sun8i-h3-orangepi-2.dtb \ sun8i-h3-orangepi-lite.dtb \ sun8i-h3-orangepi-one.dtb \ diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi-r1.dts b/arch/arm/boot/dts/sun8i-h3-nanopi-r1.dts new file mode 100644 index 000000000000..204a39f93f4e --- /dev/null +++ b/arch/arm/boot/dts/sun8i-h3-nanopi-r1.dts @@ -0,0 +1,169 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2019 Igor Pecovnik + * Copyright (C) 2020 Jayantajit Gogoi + * Copyright (C) 2020 Yu-Tung Chang +*/ + +#include "sun8i-h3-nanopi.dtsi" +#include + +/ { + model = "FriendlyARM NanoPi R1"; + compatible = "friendlyarm,nanopi-r1", "allwinner,sun8i-h3"; + + aliases { + serial1 = &uart1; + ethernet0 = &emac; + ethernet1 = &wifi; + }; + + reg_gmac_3v3: gmac-3v3 { + compatible = "regulator-fixed"; + regulator-name = "gmac-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <100000>; + enable-active-high; + gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; /* PD6 */ + }; + + reg_vdd_cpux: gpio-regulator { + compatible = "regulator-gpio"; + regulator-name = "vdd-cpux"; + regulator-type = "voltage"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1300000>; + regulator-ramp-delay = <50>; + gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */ + gpios-states = <0x1>; + states = <1100000 0x0 + 1300000 0x1>; + }; + + wifi_pwrseq: wifi_pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */ + clocks = <&rtc 1>; + clock-names = "ext_clock"; + }; + + leds { + led-2 { + function = LED_FUNCTION_WAN; + color = ; + gpios = <&pio 6 11 GPIO_ACTIVE_HIGH>; /* PG11 */ + }; + + led-3 { + function = LED_FUNCTION_LAN; + color = ; + gpios = <&pio 0 9 GPIO_ACTIVE_HIGH>; /* PA9 */ + }; + }; +}; + +&cpu0 { + cpu-supply = <®_vdd_cpux>; +}; + +&ehci1 { + status = "okay"; +}; + +&ehci2 { + status = "okay"; +}; + +&emac { + pinctrl-names = "default"; + pinctrl-0 = <&emac_rgmii_pins>; + phy-supply = <®_gmac_3v3>; + phy-handle = <&ext_rgmii_phy>; + phy-mode = "rgmii-id"; + status = "okay"; +}; + +&external_mdio { + ext_rgmii_phy: ethernet-phy@7 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <7>; + }; +}; + +&mmc1 { + vmmc-supply = <®_vcc3v3>; + vqmmc-supply = <®_vcc3v3>; + mmc-pwrseq = <&wifi_pwrseq>; + bus-width = <4>; + non-removable; + status = "okay"; + + wifi: wifi@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + interrupt-parent = <&pio>; + interrupts = <6 10 IRQ_TYPE_LEVEL_LOW>; /* PG10 / EINT10 */ + interrupt-names = "host-wake"; + }; +}; + +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_8bit_pins>; + vmmc-supply = <®_vcc3v3>; + vqmmc-supply = <®_vcc3v3>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&ohci2 { + status = "okay"; +}; + +®_usb0_vbus { + gpio = <&r_pio 0 2 GPIO_ACTIVE_HIGH>; /* PL2 */ + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins>, <&uart3_rts_cts_pins>; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + clocks = <&rtc 1>; + clock-names = "lpo"; + vbat-supply = <®_vcc3v3>; + vddio-supply = <®_vcc3v3>; + device-wakeup-gpios = <&pio 0 8 GPIO_ACTIVE_HIGH>; /* PA8 */ + host-wakeup-gpios = <&pio 0 7 GPIO_ACTIVE_HIGH>; /* PA7 */ + shutdown-gpios = <&pio 6 13 GPIO_ACTIVE_HIGH>; /* PG13 */ + }; +}; + +&usb_otg { + status = "okay"; + dr_mode = "otg"; +}; + +&usbphy { + usb0_id_det-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */ + usb0_vbus-supply = <®_usb0_vbus>; + status = "okay"; +}; -- cgit v1.2.3-59-g8ed1b From 6cbf13e3114c8477021295d338f800282ac0653a Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Wed, 4 Nov 2020 14:37:58 +0100 Subject: ARM: dts: ux500: Rename DSI controller nodes Rename the DSI controller nodes from "dsi-controller@" to "dsi@" so they match the naming convention in the YAML schema for DSI controllers. Signed-off-by: Linus Walleij Link: https://lore.kernel.org/r/20201104133758.1373298-1-linus.walleij@linaro.org Signed-off-by: Linus Walleij --- arch/arm/boot/dts/ste-ab8500.dtsi | 6 +++--- arch/arm/boot/dts/ste-ab8505.dtsi | 6 +++--- arch/arm/boot/dts/ste-dbx5x0.dtsi | 6 +++--- arch/arm/boot/dts/ste-href-stuib.dtsi | 2 +- arch/arm/boot/dts/ste-href-tvk1281618-r2.dtsi | 2 +- arch/arm/boot/dts/ste-href-tvk1281618-r3.dtsi | 2 +- arch/arm/boot/dts/ste-ux500-samsung-golden.dts | 2 +- arch/arm/boot/dts/ste-ux500-samsung-skomer.dts | 2 +- 8 files changed, 14 insertions(+), 14 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/ste-ab8500.dtsi b/arch/arm/boot/dts/ste-ab8500.dtsi index aab5719cc1a9..4c16736ea789 100644 --- a/arch/arm/boot/dts/ste-ab8500.dtsi +++ b/arch/arm/boot/dts/ste-ab8500.dtsi @@ -326,13 +326,13 @@ mcde@a0350000 { vana-supply = <&ab8500_ldo_ana_reg>; - dsi-controller@a0351000 { + dsi@a0351000 { vana-supply = <&ab8500_ldo_ana_reg>; }; - dsi-controller@a0352000 { + dsi@a0352000 { vana-supply = <&ab8500_ldo_ana_reg>; }; - dsi-controller@a0353000 { + dsi@a0353000 { vana-supply = <&ab8500_ldo_ana_reg>; }; }; diff --git a/arch/arm/boot/dts/ste-ab8505.dtsi b/arch/arm/boot/dts/ste-ab8505.dtsi index 67bc69e67b33..c72aa250bf6f 100644 --- a/arch/arm/boot/dts/ste-ab8505.dtsi +++ b/arch/arm/boot/dts/ste-ab8505.dtsi @@ -261,13 +261,13 @@ mcde@a0350000 { vana-supply = <&ab8500_ldo_ana_reg>; - dsi-controller@a0351000 { + dsi@a0351000 { vana-supply = <&ab8500_ldo_ana_reg>; }; - dsi-controller@a0352000 { + dsi@a0352000 { vana-supply = <&ab8500_ldo_ana_reg>; }; - dsi-controller@a0353000 { + dsi@a0353000 { vana-supply = <&ab8500_ldo_ana_reg>; }; }; diff --git a/arch/arm/boot/dts/ste-dbx5x0.dtsi b/arch/arm/boot/dts/ste-dbx5x0.dtsi index 05fd544b06c1..404b9c4a5fee 100644 --- a/arch/arm/boot/dts/ste-dbx5x0.dtsi +++ b/arch/arm/boot/dts/ste-dbx5x0.dtsi @@ -1097,7 +1097,7 @@ ranges; status = "disabled"; - dsi0: dsi-controller@a0351000 { + dsi0: dsi@a0351000 { compatible = "ste,mcde-dsi"; reg = <0xa0351000 0x1000>; clocks = <&prcmu_clk PRCMU_DSI0CLK>, <&prcmu_clk PRCMU_DSI0ESCCLK>; @@ -1105,7 +1105,7 @@ #address-cells = <1>; #size-cells = <0>; }; - dsi1: dsi-controller@a0352000 { + dsi1: dsi@a0352000 { compatible = "ste,mcde-dsi"; reg = <0xa0352000 0x1000>; clocks = <&prcmu_clk PRCMU_DSI1CLK>, <&prcmu_clk PRCMU_DSI1ESCCLK>; @@ -1113,7 +1113,7 @@ #address-cells = <1>; #size-cells = <0>; }; - dsi2: dsi-controller@a0353000 { + dsi2: dsi@a0353000 { compatible = "ste,mcde-dsi"; reg = <0xa0353000 0x1000>; /* This DSI port only has the Low Power / Energy Save clock */ diff --git a/arch/arm/boot/dts/ste-href-stuib.dtsi b/arch/arm/boot/dts/ste-href-stuib.dtsi index b8fd8f18ba16..e32d0c36feb8 100644 --- a/arch/arm/boot/dts/ste-href-stuib.dtsi +++ b/arch/arm/boot/dts/ste-href-stuib.dtsi @@ -199,7 +199,7 @@ mcde@a0350000 { status = "okay"; - dsi-controller@a0351000 { + dsi@a0351000 { panel { compatible = "samsung,s6d16d0"; reg = <0>; diff --git a/arch/arm/boot/dts/ste-href-tvk1281618-r2.dtsi b/arch/arm/boot/dts/ste-href-tvk1281618-r2.dtsi index de82b9db956f..e024520f4d47 100644 --- a/arch/arm/boot/dts/ste-href-tvk1281618-r2.dtsi +++ b/arch/arm/boot/dts/ste-href-tvk1281618-r2.dtsi @@ -66,7 +66,7 @@ mcde@a0350000 { status = "okay"; - dsi-controller@a0351000 { + dsi@a0351000 { panel { compatible = "samsung,s6d16d0"; reg = <0>; diff --git a/arch/arm/boot/dts/ste-href-tvk1281618-r3.dtsi b/arch/arm/boot/dts/ste-href-tvk1281618-r3.dtsi index 9f285c7cf914..cb3677f0a1cb 100644 --- a/arch/arm/boot/dts/ste-href-tvk1281618-r3.dtsi +++ b/arch/arm/boot/dts/ste-href-tvk1281618-r3.dtsi @@ -45,7 +45,7 @@ mcde@a0350000 { status = "okay"; - dsi-controller@a0351000 { + dsi@a0351000 { panel { compatible = "sony,acx424akp"; reg = <0>; diff --git a/arch/arm/boot/dts/ste-ux500-samsung-golden.dts b/arch/arm/boot/dts/ste-ux500-samsung-golden.dts index a1093cb37dc7..939360c05713 100644 --- a/arch/arm/boot/dts/ste-ux500-samsung-golden.dts +++ b/arch/arm/boot/dts/ste-ux500-samsung-golden.dts @@ -322,7 +322,7 @@ pinctrl-names = "default"; pinctrl-0 = <&dsi_default_mode>; - dsi-controller@a0351000 { + dsi@a0351000 { panel@0 { compatible = "samsung,s6e63m0"; reg = <0>; diff --git a/arch/arm/boot/dts/ste-ux500-samsung-skomer.dts b/arch/arm/boot/dts/ste-ux500-samsung-skomer.dts index 27722c42b61c..cbae23a1e8b6 100644 --- a/arch/arm/boot/dts/ste-ux500-samsung-skomer.dts +++ b/arch/arm/boot/dts/ste-ux500-samsung-skomer.dts @@ -393,7 +393,7 @@ pinctrl-names = "default"; pinctrl-0 = <&dsi_default_mode>; - dsi-controller@a0351000 { + dsi@a0351000 { panel { /* NT35510-based Hydis HVA40WV1 */ compatible = "hydis,hva40wv1", "novatek,nt35510"; -- cgit v1.2.3-59-g8ed1b From 2024b130b0c8b09d6086c495910faddbd9c6be02 Mon Sep 17 00:00:00 2001 From: Łukasz Stelmach Date: Tue, 3 Nov 2020 16:15:35 +0100 Subject: ARM: dts: exynos: Add Ethernet to Artik 5 board MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add node for ax88796c ethernet chip. Signed-off-by: Łukasz Stelmach Link: https://lore.kernel.org/r/20201103151536.26472-5-l.stelmach@samsung.com Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos3250-artik5-eval.dts | 29 ++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/exynos3250-artik5-eval.dts b/arch/arm/boot/dts/exynos3250-artik5-eval.dts index 20446a846a98..5461949d833e 100644 --- a/arch/arm/boot/dts/exynos3250-artik5-eval.dts +++ b/arch/arm/boot/dts/exynos3250-artik5-eval.dts @@ -37,3 +37,32 @@ &serial_2 { status = "okay"; }; + +&spi_0 { + status = "okay"; + cs-gpios = <&gpx3 4 GPIO_ACTIVE_LOW>, <0>; + + assigned-clocks = <&cmu CLK_MOUT_MPLL>, <&cmu CLK_DIV_MPLL_PRE>, + <&cmu CLK_MOUT_SPI0>, <&cmu CLK_DIV_SPI0>, + <&cmu CLK_DIV_SPI0_PRE>, <&cmu CLK_SCLK_SPI0>; + assigned-clock-parents = <&cmu CLK_FOUT_MPLL>, /* for: CLK_MOUT_MPLL */ + <&cmu CLK_MOUT_MPLL>, /* for: CLK_DIV_MPLL_PRE */ + <&cmu CLK_DIV_MPLL_PRE>, /* for: CLK_MOUT_SPI0 */ + <&cmu CLK_MOUT_SPI0>, /* for: CLK_DIV_SPI0 */ + <&cmu CLK_DIV_SPI0>, /* for: CLK_DIV_SPI0_PRE */ + <&cmu CLK_DIV_SPI0_PRE>; /* for: CLK_SCLK_SPI0 */ + + ethernet@0 { + compatible = "asix,ax88796c"; + reg = <0x0>; + local-mac-address = [00 00 00 00 00 00]; /* Filled in by a boot-loader */ + interrupt-parent = <&gpx2>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + spi-max-frequency = <40000000>; + reset-gpios = <&gpe0 2 GPIO_ACTIVE_LOW>; + + controller-data { + samsung,spi-feedback-delay = <2>; + }; + }; +}; -- cgit v1.2.3-59-g8ed1b From dfe21dcabac001e0a102c1aa3bbaee00041e9e0f Mon Sep 17 00:00:00 2001 From: Łukasz Stelmach Date: Tue, 3 Nov 2020 16:15:36 +0100 Subject: ARM: defconfig: Enable ax88796c driver for Exynos boards MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Enable ax88796c driver for the Ethernet chip on Exynos3250-based ARTIK5 boards in exynos and multi_v7 defconfigs. Signed-off-by: Łukasz Stelmach Link: https://lore.kernel.org/r/20201103151536.26472-6-l.stelmach@samsung.com Signed-off-by: Krzysztof Kozlowski --- arch/arm/configs/exynos_defconfig | 2 ++ arch/arm/configs/multi_v7_defconfig | 2 ++ 2 files changed, 4 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/configs/exynos_defconfig b/arch/arm/configs/exynos_defconfig index 8c1fd6408108..f0cef76a3ab9 100644 --- a/arch/arm/configs/exynos_defconfig +++ b/arch/arm/configs/exynos_defconfig @@ -107,6 +107,8 @@ CONFIG_MD=y CONFIG_BLK_DEV_DM=y CONFIG_DM_CRYPT=m CONFIG_NETDEVICES=y +CONFIG_NET_VENDOR_ASIX=y +CONFIG_SPI_AX88796C=y CONFIG_SMSC911X=y CONFIG_USB_RTL8150=m CONFIG_USB_RTL8152=y diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig index 138a9e8fe35d..6ab0945fb27c 100644 --- a/arch/arm/configs/multi_v7_defconfig +++ b/arch/arm/configs/multi_v7_defconfig @@ -243,6 +243,8 @@ CONFIG_SATA_HIGHBANK=y CONFIG_SATA_MV=y CONFIG_SATA_RCAR=y CONFIG_NETDEVICES=y +CONFIG_NET_VENDOR_ASIX=y +CONFIG_SPI_AX88796C=m CONFIG_VIRTIO_NET=y CONFIG_B53_SPI_DRIVER=m CONFIG_B53_MDIO_DRIVER=m -- cgit v1.2.3-59-g8ed1b From 2a15ba82fa6ca3f35502b3060f22118a938d2889 Mon Sep 17 00:00:00 2001 From: Thomas Gleixner Date: Tue, 3 Nov 2020 10:27:22 +0100 Subject: ARM: highmem: Switch to generic kmap atomic No reason having the same code in every architecture. Signed-off-by: Thomas Gleixner Cc: Russell King Cc: Arnd Bergmann Link: https://lore.kernel.org/r/20201103095857.582196476@linutronix.de --- arch/arm/Kconfig | 1 + arch/arm/include/asm/fixmap.h | 4 +- arch/arm/include/asm/highmem.h | 33 +++++++---- arch/arm/include/asm/kmap_types.h | 10 ---- arch/arm/mm/Makefile | 1 - arch/arm/mm/highmem.c | 121 -------------------------------------- 6 files changed, 26 insertions(+), 144 deletions(-) delete mode 100644 arch/arm/include/asm/kmap_types.h delete mode 100644 arch/arm/mm/highmem.c (limited to 'arch/arm') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index fe2f17eb2b50..46f890083607 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1498,6 +1498,7 @@ config HAVE_ARCH_PFN_VALID config HIGHMEM bool "High Memory Support" depends on MMU + select KMAP_LOCAL help The address space of ARM processors is only 4 Gigabytes large and it has to accommodate user address space, kernel address diff --git a/arch/arm/include/asm/fixmap.h b/arch/arm/include/asm/fixmap.h index fc56fc3e1931..c279a8a463a2 100644 --- a/arch/arm/include/asm/fixmap.h +++ b/arch/arm/include/asm/fixmap.h @@ -7,14 +7,14 @@ #define FIXADDR_TOP (FIXADDR_END - PAGE_SIZE) #include -#include +#include enum fixed_addresses { FIX_EARLYCON_MEM_BASE, __end_of_permanent_fixed_addresses, FIX_KMAP_BEGIN = __end_of_permanent_fixed_addresses, - FIX_KMAP_END = FIX_KMAP_BEGIN + (KM_TYPE_NR * NR_CPUS) - 1, + FIX_KMAP_END = FIX_KMAP_BEGIN + (KM_MAX_IDX * NR_CPUS) - 1, /* Support writing RO kernel text via kprobes, jump labels, etc. */ FIX_TEXT_POKE0, diff --git a/arch/arm/include/asm/highmem.h b/arch/arm/include/asm/highmem.h index 31811be38d78..a41de523d053 100644 --- a/arch/arm/include/asm/highmem.h +++ b/arch/arm/include/asm/highmem.h @@ -2,7 +2,7 @@ #ifndef _ASM_HIGHMEM_H #define _ASM_HIGHMEM_H -#include +#include #define PKMAP_BASE (PAGE_OFFSET - PMD_SIZE) #define LAST_PKMAP PTRS_PER_PTE @@ -46,19 +46,32 @@ extern pte_t *pkmap_page_table; #ifdef ARCH_NEEDS_KMAP_HIGH_GET extern void *kmap_high_get(struct page *page); -#else + +static inline void *arch_kmap_local_high_get(struct page *page) +{ + if (IS_ENABLED(CONFIG_DEBUG_HIGHMEM) && !cache_is_vivt()) + return NULL; + return kmap_high_get(page); +} +#define arch_kmap_local_high_get arch_kmap_local_high_get + +#else /* ARCH_NEEDS_KMAP_HIGH_GET */ static inline void *kmap_high_get(struct page *page) { return NULL; } -#endif +#endif /* !ARCH_NEEDS_KMAP_HIGH_GET */ -/* - * The following functions are already defined by - * when CONFIG_HIGHMEM is not set. - */ -#ifdef CONFIG_HIGHMEM -extern void *kmap_atomic_pfn(unsigned long pfn); -#endif +#define arch_kmap_local_post_map(vaddr, pteval) \ + local_flush_tlb_kernel_page(vaddr) + +#define arch_kmap_local_pre_unmap(vaddr) \ +do { \ + if (cache_is_vivt()) \ + __cpuc_flush_dcache_area((void *)vaddr, PAGE_SIZE); \ +} while (0) + +#define arch_kmap_local_post_unmap(vaddr) \ + local_flush_tlb_kernel_page(vaddr) #endif diff --git a/arch/arm/include/asm/kmap_types.h b/arch/arm/include/asm/kmap_types.h deleted file mode 100644 index 5590940ee43d..000000000000 --- a/arch/arm/include/asm/kmap_types.h +++ /dev/null @@ -1,10 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __ARM_KMAP_TYPES_H -#define __ARM_KMAP_TYPES_H - -/* - * This is the "bare minimum". AIO seems to require this. - */ -#define KM_TYPE_NR 16 - -#endif diff --git a/arch/arm/mm/Makefile b/arch/arm/mm/Makefile index 7cb1699fbfc4..c4ce477c5261 100644 --- a/arch/arm/mm/Makefile +++ b/arch/arm/mm/Makefile @@ -19,7 +19,6 @@ obj-$(CONFIG_MODULES) += proc-syms.o obj-$(CONFIG_DEBUG_VIRTUAL) += physaddr.o obj-$(CONFIG_ALIGNMENT_TRAP) += alignment.o -obj-$(CONFIG_HIGHMEM) += highmem.o obj-$(CONFIG_HUGETLB_PAGE) += hugetlbpage.o obj-$(CONFIG_ARM_PV_FIXUP) += pv-fixup-asm.o diff --git a/arch/arm/mm/highmem.c b/arch/arm/mm/highmem.c deleted file mode 100644 index 187fab227b50..000000000000 --- a/arch/arm/mm/highmem.c +++ /dev/null @@ -1,121 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * arch/arm/mm/highmem.c -- ARM highmem support - * - * Author: Nicolas Pitre - * Created: september 8, 2008 - * Copyright: Marvell Semiconductors Inc. - */ - -#include -#include -#include -#include -#include -#include -#include "mm.h" - -static inline void set_fixmap_pte(int idx, pte_t pte) -{ - unsigned long vaddr = __fix_to_virt(idx); - pte_t *ptep = virt_to_kpte(vaddr); - - set_pte_ext(ptep, pte, 0); - local_flush_tlb_kernel_page(vaddr); -} - -static inline pte_t get_fixmap_pte(unsigned long vaddr) -{ - pte_t *ptep = virt_to_kpte(vaddr); - - return *ptep; -} - -void *kmap_atomic_high_prot(struct page *page, pgprot_t prot) -{ - unsigned int idx; - unsigned long vaddr; - void *kmap; - int type; - -#ifdef CONFIG_DEBUG_HIGHMEM - /* - * There is no cache coherency issue when non VIVT, so force the - * dedicated kmap usage for better debugging purposes in that case. - */ - if (!cache_is_vivt()) - kmap = NULL; - else -#endif - kmap = kmap_high_get(page); - if (kmap) - return kmap; - - type = kmap_atomic_idx_push(); - - idx = FIX_KMAP_BEGIN + type + KM_TYPE_NR * smp_processor_id(); - vaddr = __fix_to_virt(idx); -#ifdef CONFIG_DEBUG_HIGHMEM - /* - * With debugging enabled, kunmap_atomic forces that entry to 0. - * Make sure it was indeed properly unmapped. - */ - BUG_ON(!pte_none(get_fixmap_pte(vaddr))); -#endif - /* - * When debugging is off, kunmap_atomic leaves the previous mapping - * in place, so the contained TLB flush ensures the TLB is updated - * with the new mapping. - */ - set_fixmap_pte(idx, mk_pte(page, prot)); - - return (void *)vaddr; -} -EXPORT_SYMBOL(kmap_atomic_high_prot); - -void kunmap_atomic_high(void *kvaddr) -{ - unsigned long vaddr = (unsigned long) kvaddr & PAGE_MASK; - int idx, type; - - if (kvaddr >= (void *)FIXADDR_START) { - type = kmap_atomic_idx(); - idx = FIX_KMAP_BEGIN + type + KM_TYPE_NR * smp_processor_id(); - - if (cache_is_vivt()) - __cpuc_flush_dcache_area((void *)vaddr, PAGE_SIZE); -#ifdef CONFIG_DEBUG_HIGHMEM - BUG_ON(vaddr != __fix_to_virt(idx)); - set_fixmap_pte(idx, __pte(0)); -#else - (void) idx; /* to kill a warning */ -#endif - kmap_atomic_idx_pop(); - } else if (vaddr >= PKMAP_ADDR(0) && vaddr < PKMAP_ADDR(LAST_PKMAP)) { - /* this address was obtained through kmap_high_get() */ - kunmap_high(pte_page(pkmap_page_table[PKMAP_NR(vaddr)])); - } -} -EXPORT_SYMBOL(kunmap_atomic_high); - -void *kmap_atomic_pfn(unsigned long pfn) -{ - unsigned long vaddr; - int idx, type; - struct page *page = pfn_to_page(pfn); - - preempt_disable(); - pagefault_disable(); - if (!PageHighMem(page)) - return page_address(page); - - type = kmap_atomic_idx_push(); - idx = FIX_KMAP_BEGIN + type + KM_TYPE_NR * smp_processor_id(); - vaddr = __fix_to_virt(idx); -#ifdef CONFIG_DEBUG_HIGHMEM - BUG_ON(!pte_none(get_fixmap_pte(vaddr))); -#endif - set_fixmap_pte(idx, pfn_pte(pfn, kmap_prot)); - - return (void *)vaddr; -} -- cgit v1.2.3-59-g8ed1b From c5f883d1a6f3f061eb5d1acbbe2f3cbbe985f6a3 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 3 Nov 2020 09:41:36 +0100 Subject: ARM: shmobile: defconfig: Refresh for v5.10-rc1 Refresh the defconfig for Renesas ARM systems: - Reorder SoC-specific config options (cfr. commit 6d5aded8d57fc032 ("soc: renesas: Sort driver description title")). Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20201103084136.1378875-1-geert+renesas@glider.be --- arch/arm/configs/shmobile_defconfig | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/configs/shmobile_defconfig b/arch/arm/configs/shmobile_defconfig index 4a161b3c35b9..01a6ebdf033a 100644 --- a/arch/arm/configs/shmobile_defconfig +++ b/arch/arm/configs/shmobile_defconfig @@ -179,22 +179,22 @@ CONFIG_STAGING=y CONFIG_STAGING_BOARD=y # CONFIG_IOMMU_SUPPORT is not set CONFIG_ARCH_EMEV2=y +CONFIG_ARCH_R8A7794=y +CONFIG_ARCH_R8A7779=y +CONFIG_ARCH_R8A7790=y +CONFIG_ARCH_R8A7778=y +CONFIG_ARCH_R8A7793=y +CONFIG_ARCH_R8A7791=y +CONFIG_ARCH_R8A7792=y +CONFIG_ARCH_R8A7740=y +CONFIG_ARCH_R8A73A4=y CONFIG_ARCH_R7S72100=y CONFIG_ARCH_R7S9210=y -CONFIG_ARCH_R8A73A4=y -CONFIG_ARCH_R8A7740=y +CONFIG_ARCH_R8A77470=y +CONFIG_ARCH_R8A7745=y CONFIG_ARCH_R8A7742=y CONFIG_ARCH_R8A7743=y CONFIG_ARCH_R8A7744=y -CONFIG_ARCH_R8A7745=y -CONFIG_ARCH_R8A77470=y -CONFIG_ARCH_R8A7778=y -CONFIG_ARCH_R8A7779=y -CONFIG_ARCH_R8A7790=y -CONFIG_ARCH_R8A7791=y -CONFIG_ARCH_R8A7792=y -CONFIG_ARCH_R8A7793=y -CONFIG_ARCH_R8A7794=y CONFIG_ARCH_R9A06G032=y CONFIG_ARCH_SH73A0=y CONFIG_IIO=y -- cgit v1.2.3-59-g8ed1b From f4d0fea16ad771f1f3c930251af90f8b33d9fa66 Mon Sep 17 00:00:00 2001 From: Yunus Bas Date: Thu, 29 Oct 2020 08:03:22 +0100 Subject: ARM: dts: imx6ul: segin: Add phyBOARD-Segin with eMMC phyCORE-i.MX6UL Add a PHYTEC phyBOARD-Segin full featured with phyCORE-i.MX 6UL with eMMC and following features: - i.MX 6UL - 512 MB RAM - eMMC - USB Host/OTG - 2x 100 Mbit/s Ethernet - RS232 - CAN Signed-off-by: Yunus Bas Signed-off-by: Stefan Riedmueller Signed-off-by: Shawn Guo --- arch/arm/boot/dts/Makefile | 1 + .../boot/dts/imx6ul-phytec-segin-ff-rdk-emmc.dts | 93 ++++++++++++++++++++++ 2 files changed, 94 insertions(+) create mode 100644 arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-emmc.dts (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index ce66ffd5a1bb..654692919a27 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -622,6 +622,7 @@ dtb-$(CONFIG_SOC_IMX6UL) += \ imx6ul-pico-dwarf.dtb \ imx6ul-pico-hobbit.dtb \ imx6ul-pico-pi.dtb \ + imx6ul-phytec-segin-ff-rdk-emmc.dtb \ imx6ul-phytec-segin-ff-rdk-nand.dtb \ imx6ul-tx6ul-0010.dtb \ imx6ul-tx6ul-0011.dtb \ diff --git a/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-emmc.dts b/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-emmc.dts new file mode 100644 index 000000000000..4a25122e0da2 --- /dev/null +++ b/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-emmc.dts @@ -0,0 +1,93 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright (C) 2020 PHYTEC Messtechnik GmbH + * Author: Yunus Bas + */ + +/dts-v1/; +#include "imx6ul.dtsi" +#include "imx6ul-phytec-phycore-som.dtsi" +#include "imx6ul-phytec-segin.dtsi" +#include "imx6ul-phytec-segin-peb-eval-01.dtsi" + +/ { + model = "PHYTEC phyBOARD-Segin i.MX6 UltraLite Full Featured with eMMC"; + compatible = "phytec,imx6ul-pbacd10-emmc", "phytec,imx6ul-pbacd10", + "phytec,imx6ul-pcl063","fsl,imx6ul"; +}; + +&adc1 { + status = "okay"; +}; + +&can1 { + status = "okay"; +}; + +&ecspi3 { + status = "okay"; +}; + +ðphy1 { + status = "okay"; +}; + +ðphy2 { + status = "okay"; +}; + +&fec1 { + status = "okay"; +}; + +&fec2 { + status = "okay"; +}; + +&i2c_rtc { + status = "okay"; +}; + +®_can1_en { + status = "okay"; +}; + +®_sound_1v8 { + status = "okay"; +}; + +®_sound_3v3 { + status = "okay"; +}; + +&sai2 { + status = "okay"; +}; + +&sound { + status = "okay"; +}; + +&tlv320 { + status = "okay"; +}; + +&uart5 { + status = "okay"; +}; + +&usbotg1 { + status = "okay"; +}; + +&usbotg2 { + status = "okay"; +}; + +&usdhc1 { + status = "okay"; +}; + +&usdhc2 { + status = "okay"; +}; -- cgit v1.2.3-59-g8ed1b From 6d4e1ff5281996efe6a2b9bc58cdcdd446bb52a4 Mon Sep 17 00:00:00 2001 From: Stefan Riedmueller Date: Thu, 29 Oct 2020 08:03:23 +0100 Subject: ARM: dts: imx6ul: phytec: Add support for optional PEB-AV-02 LCD adapter The PHYTEC PEB-AV-02 adapter adds the capability to connect a parallel LCD display to the phyBOARD-Segin full featured, either with capacitive or resistive touch. Signed-off-by: Stefan Riedmueller Signed-off-by: Shawn Guo --- .../boot/dts/imx6ul-phytec-segin-ff-rdk-emmc.dts | 1 + .../boot/dts/imx6ul-phytec-segin-ff-rdk-nand.dts | 1 + .../boot/dts/imx6ul-phytec-segin-peb-av-02.dtsi | 150 +++++++++++++++++++++ arch/arm/boot/dts/imx6ul-phytec-segin.dtsi | 43 ------ .../boot/dts/imx6ull-phytec-segin-ff-rdk-emmc.dts | 1 + .../boot/dts/imx6ull-phytec-segin-ff-rdk-nand.dts | 1 + .../boot/dts/imx6ull-phytec-segin-peb-av-02.dtsi | 26 ++++ arch/arm/boot/dts/imx6ull-phytec-segin.dtsi | 7 - 8 files changed, 180 insertions(+), 50 deletions(-) create mode 100644 arch/arm/boot/dts/imx6ul-phytec-segin-peb-av-02.dtsi create mode 100644 arch/arm/boot/dts/imx6ull-phytec-segin-peb-av-02.dtsi (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-emmc.dts b/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-emmc.dts index 4a25122e0da2..cfc744f8fcad 100644 --- a/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-emmc.dts +++ b/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-emmc.dts @@ -9,6 +9,7 @@ #include "imx6ul-phytec-phycore-som.dtsi" #include "imx6ul-phytec-segin.dtsi" #include "imx6ul-phytec-segin-peb-eval-01.dtsi" +#include "imx6ul-phytec-segin-peb-av-02.dtsi" / { model = "PHYTEC phyBOARD-Segin i.MX6 UltraLite Full Featured with eMMC"; diff --git a/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-nand.dts b/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-nand.dts index 699dfcbf9a60..bff98e676980 100644 --- a/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-nand.dts +++ b/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-nand.dts @@ -9,6 +9,7 @@ #include "imx6ul-phytec-phycore-som.dtsi" #include "imx6ul-phytec-segin.dtsi" #include "imx6ul-phytec-segin-peb-eval-01.dtsi" +#include "imx6ul-phytec-segin-peb-av-02.dtsi" / { model = "PHYTEC phyBOARD-Segin i.MX6 UltraLite Full Featured with NAND"; diff --git a/arch/arm/boot/dts/imx6ul-phytec-segin-peb-av-02.dtsi b/arch/arm/boot/dts/imx6ul-phytec-segin-peb-av-02.dtsi new file mode 100644 index 000000000000..b511c6dec427 --- /dev/null +++ b/arch/arm/boot/dts/imx6ul-phytec-segin-peb-av-02.dtsi @@ -0,0 +1,150 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright (C) 2016, 2020 PHYTEC Messtechnik + * Author: Christian Hemp + * Author: Stefan Riedmueller + */ + +/ { + backlight_lcd: backlight-lcd { + compatible = "pwm-backlight"; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <5>; + power-supply = <®_backlight_en>; + pwms = <&pwm3 0 5000000>; + status = "disabled"; + }; + + lcd_panel: lcd-panel { + compatible = "edt,etm0700g0edh6"; + backlight = <&backlight_lcd>; + status = "disabled"; + + port { + lcd_panel_in: endpoint { + remote-endpoint = <&lcdif_parallel_out>; + }; + }; + }; + + reg_backlight_en: regulator-backlight-en { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_backlight_en>; + regulator-name = "backlight-lcd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 18 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +&i2c1 { + edt_ft5406: touchscreen@38 { + compatible = "edt,edt-ft5406"; + reg = <0x38>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_edt_ft5406>; + interrupt-parent = <&gpio5>; + interrupts = <5 IRQ_TYPE_EDGE_FALLING>; + wakeup-source; + status = "disabled"; + }; + + stmpe: touchscreen@44 { + compatible = "st,stmpe811"; + reg = <0x44>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_stmpe>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio5>; + status = "disabled"; + + stmpe_touchscreen { + compatible = "st,stmpe-ts"; + st,sample-time = <4>; + st,mod-12b = <1>; + st,ref-sel = <0>; + st,adc-freq = <1>; + st,ave-ctrl = <1>; + st,touch-det-delay = <2>; + st,settling = <2>; + st,fraction-z = <7>; + st,i-drive = <1>; + touchscreen-inverted-x = <1>; + touchscreen-inverted-y = <1>; + }; + }; +}; + +&lcdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcdif_dat>; + status = "disabled"; + + port { + lcdif_parallel_out: endpoint { + remote-endpoint = <&lcd_panel_in>; + }; + }; +}; + +&pwm3 { + #pwm-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; + status = "disabled"; +}; + +&iomuxc { + pinctrl_edt_ft5406: edtft5406grp { + fsl,pins = < + MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x1b0b0 + >; + }; + + pinctrl_backlight_en: bachlightengrp { + fsl,pins = < + MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x1b0b0 + >; + }; + + pinctrl_lcdif_dat: lcdifdatgrp { + fsl,pins = < + MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x59 + MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x59 + MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x59 + MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x59 + MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x59 + MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x59 + MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x59 + MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x59 + MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x59 + MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x59 + MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x59 + MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x59 + MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x59 + MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x59 + MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x59 + MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x59 + MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x59 + MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x59 + MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x59 + MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x59 + MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x59 + MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x59 + >; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO04__PWM3_OUT 0x0b0b0 + >; + }; + + pinctrl_stmpe: stmpegrp { + fsl,pins = < + MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x17059 + >; + }; +}; diff --git a/arch/arm/boot/dts/imx6ul-phytec-segin.dtsi b/arch/arm/boot/dts/imx6ul-phytec-segin.dtsi index 7367279748f4..95e4080dd0a6 100644 --- a/arch/arm/boot/dts/imx6ul-phytec-segin.dtsi +++ b/arch/arm/boot/dts/imx6ul-phytec-segin.dtsi @@ -130,31 +130,6 @@ status = "disabled"; }; - stmpe: touchscreen@44 { - compatible = "st,stmpe811"; - reg = <0x44>; - interrupts = <3 IRQ_TYPE_LEVEL_LOW>; - interrupt-parent = <&gpio5>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_stmpe>; - status = "disabled"; - - stmpe_touchscreen { - compatible = "st,stmpe-ts"; - st,sample-time = <4>; - st,mod-12b = <1>; - st,ref-sel = <0>; - st,adc-freq = <1>; - st,ave-ctrl = <1>; - st,touch-det-delay = <2>; - st,settling = <2>; - st,fraction-z = <7>; - st,i-drive = <1>; - touchscreen-inverted-x = <1>; - touchscreen-inverted-y = <1>; - }; - }; - i2c_rtc: rtc@68 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_rtc_int>; @@ -176,12 +151,6 @@ }; }; -&pwm3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm3>; - status = "disabled"; -}; - &sai2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sai2>; @@ -267,12 +236,6 @@ >; }; - pinctrl_pwm3: pwm3grp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO04__PWM3_OUT 0x0b0b0 - >; - }; - pinctrl_rtc_int: rtcintgrp { fsl,pins = < MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x17059 @@ -289,12 +252,6 @@ >; }; - pinctrl_stmpe: stmpegrp { - fsl,pins = < - MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x17059 - >; - }; - pinctrl_uart5: uart5grp { fsl,pins = < MX6UL_PAD_UART5_TX_DATA__UART5_DCE_TX 0x1b0b1 diff --git a/arch/arm/boot/dts/imx6ull-phytec-segin-ff-rdk-emmc.dts b/arch/arm/boot/dts/imx6ull-phytec-segin-ff-rdk-emmc.dts index 9648d4ecaf58..8e2a4c5d7765 100644 --- a/arch/arm/boot/dts/imx6ull-phytec-segin-ff-rdk-emmc.dts +++ b/arch/arm/boot/dts/imx6ull-phytec-segin-ff-rdk-emmc.dts @@ -9,6 +9,7 @@ #include "imx6ull-phytec-phycore-som.dtsi" #include "imx6ull-phytec-segin.dtsi" #include "imx6ull-phytec-segin-peb-eval-01.dtsi" +#include "imx6ull-phytec-segin-peb-av-02.dtsi" / { model = "PHYTEC phyBOARD-Segin i.MX6 ULL Full Featured with eMMC"; diff --git a/arch/arm/boot/dts/imx6ull-phytec-segin-ff-rdk-nand.dts b/arch/arm/boot/dts/imx6ull-phytec-segin-ff-rdk-nand.dts index 656baf846453..c8d3eff9ed4b 100644 --- a/arch/arm/boot/dts/imx6ull-phytec-segin-ff-rdk-nand.dts +++ b/arch/arm/boot/dts/imx6ull-phytec-segin-ff-rdk-nand.dts @@ -9,6 +9,7 @@ #include "imx6ull-phytec-phycore-som.dtsi" #include "imx6ull-phytec-segin.dtsi" #include "imx6ull-phytec-segin-peb-eval-01.dtsi" +#include "imx6ull-phytec-segin-peb-av-02.dtsi" / { model = "PHYTEC phyBOARD-Segin i.MX6 ULL Full Featured with NAND"; diff --git a/arch/arm/boot/dts/imx6ull-phytec-segin-peb-av-02.dtsi b/arch/arm/boot/dts/imx6ull-phytec-segin-peb-av-02.dtsi new file mode 100644 index 000000000000..06bb7f327780 --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-phytec-segin-peb-av-02.dtsi @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright (C) 2018 PHYTEC Messtechnik GmbH + * Author: Stefan Riedmueller + */ + +#include "imx6ul-phytec-segin-peb-av-02.dtsi" + +&iomuxc { + /delete-node/ edtft5406grp; + /delete-node/ stmpegrp; +}; + +&iomuxc_snvs { + pinctrl_edt_ft5406: edtft5406grp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x1b0b0 + >; + }; + + pinctrl_stmpe: stmpegrp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x17059 + >; + }; +}; diff --git a/arch/arm/boot/dts/imx6ull-phytec-segin.dtsi b/arch/arm/boot/dts/imx6ull-phytec-segin.dtsi index c1595fc785f7..e287a0453b5f 100644 --- a/arch/arm/boot/dts/imx6ull-phytec-segin.dtsi +++ b/arch/arm/boot/dts/imx6ull-phytec-segin.dtsi @@ -14,7 +14,6 @@ &iomuxc { /delete-node/ flexcan1engrp; /delete-node/ rtcintgrp; - /delete-node/ stmpegrp; }; &iomuxc_snvs { @@ -29,10 +28,4 @@ MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x17059 >; }; - - pinctrl_stmpe: stmpegrp { - fsl,pins = < - MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x17059 - >; - }; }; -- cgit v1.2.3-59-g8ed1b From 93c0289c11b08467c0c998d35f050e6664bbf99c Mon Sep 17 00:00:00 2001 From: Stefan Riedmueller Date: Thu, 29 Oct 2020 08:03:24 +0100 Subject: ARM: dts: imx6ul: segin: peb-av-02: Mark stmpe touch as wakeup-source Mark the STMPE resistive touch controller as a wakeup-source. Signed-off-by: Stefan Riedmueller Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6ul-phytec-segin-peb-av-02.dtsi | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx6ul-phytec-segin-peb-av-02.dtsi b/arch/arm/boot/dts/imx6ul-phytec-segin-peb-av-02.dtsi index b511c6dec427..7cda6944501d 100644 --- a/arch/arm/boot/dts/imx6ul-phytec-segin-peb-av-02.dtsi +++ b/arch/arm/boot/dts/imx6ul-phytec-segin-peb-av-02.dtsi @@ -58,6 +58,7 @@ pinctrl-0 = <&pinctrl_stmpe>; interrupts = <3 IRQ_TYPE_LEVEL_LOW>; interrupt-parent = <&gpio5>; + wakeup-source; status = "disabled"; stmpe_touchscreen { -- cgit v1.2.3-59-g8ed1b From df0852c234d9a73ad2469cd0562ba212a422c374 Mon Sep 17 00:00:00 2001 From: Oleksij Rempel Date: Fri, 30 Oct 2020 15:00:29 +0100 Subject: ARM: dts: add Altesco I6P board Altesco (Altus-Escon-Company BV) I6P is a part of the diagnostic system for the vehicle inspection stations. Co-developed-by: David Jander Signed-off-by: David Jander Signed-off-by: Oleksij Rempel Signed-off-by: Shawn Guo --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/imx6dl-alti6p.dts | 564 ++++++++++++++++++++++++++++++++++++ 2 files changed, 565 insertions(+) create mode 100644 arch/arm/boot/dts/imx6dl-alti6p.dts (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 654692919a27..526e6c237a9c 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -414,6 +414,7 @@ dtb-$(CONFIG_SOC_IMX53) += \ imx53-usbarmory.dtb \ imx53-voipac-bsb.dtb dtb-$(CONFIG_SOC_IMX6Q) += \ + imx6dl-alti6p.dtb \ imx6dl-apf6dev.dtb \ imx6dl-aristainetos_4.dtb \ imx6dl-aristainetos_7.dtb \ diff --git a/arch/arm/boot/dts/imx6dl-alti6p.dts b/arch/arm/boot/dts/imx6dl-alti6p.dts new file mode 100644 index 000000000000..4329b372d8cb --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-alti6p.dts @@ -0,0 +1,564 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) 2016 Protonic Holland + * Copyright (c) 2020 Oleksij Rempel , Pengutronix + */ + +/dts-v1/; +#include +#include +#include +#include "imx6dl.dtsi" + +/ { + model = "Altesco I6P Board"; + compatible = "alt,alti6p", "fsl,imx6dl"; + + chosen { + stdout-path = &uart4; + }; + + clock_ksz8081: clock-ksz8081 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + }; + + i2c2-mux { + compatible = "i2c-mux"; + i2c-parent = <&i2c2>; + mux-controls = <&i2c_mux>; + #address-cells = <1>; + #size-cells = <0>; + + i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + i2c4-mux { + compatible = "i2c-mux"; + i2c-parent = <&i2c4>; + mux-controls = <&i2c_mux>; + #address-cells = <1>; + #size-cells = <0>; + + i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_leds>; + + led-debug0 { + function = LED_FUNCTION_STATUS; + gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + + led-debug1 { + function = LED_FUNCTION_SD; + gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "disk-activity"; + }; + }; + + i2c_mux: mux-controller { + compatible = "gpio-mux"; + #mux-control-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2cmux>; + + mux-gpios = <&gpio5 10 GPIO_ACTIVE_HIGH>, + <&gpio5 11 GPIO_ACTIVE_HIGH>; + }; + + reg_1v8: regulator-1v8 { + compatible = "regulator-fixed"; + regulator-name = "1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_5v0: regulator-5v0 { + compatible = "regulator-fixed"; + regulator-name = "5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_h1_vbus: regulator-h1-vbus { + compatible = "regulator-fixed"; + regulator-name = "h1-vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_otg_vbus: regulator-otg-vbus { + compatible = "regulator-fixed"; + regulator-name = "otg-vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "prti6q-sgtl5000"; + simple-audio-card,format = "i2s"; + simple-audio-card,widgets = + "Microphone", "Microphone Jack", + "Line", "Line In Jack", + "Headphone", "Headphone Jack", + "Speaker", "External Speaker"; + simple-audio-card,routing = + "MIC_IN", "Microphone Jack", + "LINE_IN", "Line In Jack", + "Headphone Jack", "HP_OUT", + "External Speaker", "LINE_OUT"; + + simple-audio-card,cpu { + sound-dai = <&ssi1>; + system-clock-frequency = <0>; + }; + + simple-audio-card,codec { + sound-dai = <&sgtl5000>; + bitclock-master; + frame-master; + }; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + status = "okay"; + + mux-ssi1 { + fsl,audmux-port = <0>; + fsl,port-config = < + IMX_AUDMUX_V2_PTCR_SYN 0 + IMX_AUDMUX_V2_PTCR_TFSEL(2) 0 + IMX_AUDMUX_V2_PTCR_TCSEL(2) 0 + IMX_AUDMUX_V2_PTCR_TFSDIR 0 + IMX_AUDMUX_V2_PTCR_TCLKDIR IMX_AUDMUX_V2_PDCR_RXDSEL(2) + >; + }; + + mux-pins3 { + fsl,audmux-port = <2>; + fsl,port-config = < + IMX_AUDMUX_V2_PTCR_SYN IMX_AUDMUX_V2_PDCR_RXDSEL(0) + 0 IMX_AUDMUX_V2_PDCR_TXRXEN + >; + }; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can1>; + xceiver-supply = <®_5v0>; + status = "okay"; +}; + +&ecspi1 { + cs-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <20000000>; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rmii"; + clocks = <&clks IMX6QDL_CLK_ENET>, + <&clks IMX6QDL_CLK_ENET>, + <&clock_ksz8081>; + clock-names = "ipg", "ahb", "ptp"; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + /* Microchip KSZ8081RNA PHY */ + rgmii_phy: ethernet-phy@0 { + reg = <0>; + interrupts-extended = <&gpio4 30 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpio4 26 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <300>; + }; + }; +}; + +&gpio1 { + gpio-line-names = + "", "SD1_CD", "", "USB_H1_OC", "", "", "", "", + "DEBUG_0", "DEBUG_1", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpio3 { + gpio-line-names = + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "ECSPI1_SS1", "", "USB_EXT1_OC", "USB_EXT1_PWR", "", + "", "", "", "", "", "", "", ""; +}; + +&gpio4 { + gpio-line-names = + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "ETH_RESET", "", "", "BUZZER", "ETH_INTRP", ""; +}; + +&gpio5 { + gpio-line-names = + "", "", "", "", "", "", "", "", + "", "", "I2C_EN13", "I2C_EN24", "", "", "", "", + "", "", "", "", "", "AUDIO_RESET", "", "", + "", "", "", "", "", "", "", ""; +}; + +&hdmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hdmi>; + ddc-i2c-bus = <&i2c1>; + status = "okay"; +}; + +/* DDC */ +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + sgtl5000: audio-codec@a { + compatible = "fsl,sgtl5000"; + reg = <0xa>; + #sound-dai-cells = <0>; + clocks = <&clks 201>; + VDDA-supply = <®_3v3>; + VDDIO-supply = <®_3v3>; + VDDD-supply = <®_1v8>; + }; + + /* additional i2c devices are added automatically by the boot loader */ +}; + +&i2c2 { + clock-frequency = <50000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + /* external interface, device are configured from user space */ +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + rtc@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + }; + + temperature-sensor@70 { + compatible = "ti,tmp103"; + reg = <0x70>; + }; +}; + +&i2c4 { + clock-frequency = <50000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4>; + status = "okay"; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&ssi1 { + #sound-dai-cells = <0>; + fsl,mode = "ac97-slave"; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + status = "okay"; +}; + +&usbh1 { + vbus-supply = <®_h1_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1>; + phy_type = "utmi"; + dr_mode = "host"; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + phy_type = "utmi"; + dr_mode = "host"; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; + no-1-8-v; + disable-wp; + cap-sd-highspeed; + no-mmc; + no-sdio; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + bus-width = <8>; + no-1-8-v; + non-removable; + no-sd; + no-sdio; + status = "okay"; +}; + +&iomuxc { + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0x030b0 + MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 + MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 + MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 + MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 + >; + }; + + pinctrl_can1: can1grp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b000 + MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x3008 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x1b000 + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x3008 + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x3008 + /* CS */ + MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x3008 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + /* MX6QDL_ENET_PINGRP4 */ + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0 + MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0 + MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0 + MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 + MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0 + MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0 + MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0 + + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x1b0b0 + /* Phy reset */ + MX6QDL_PAD_DISP0_DAT5__GPIO4_IO26 0x1b0b0 + /* nINTRP */ + MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30 0x1b0b0 + >; + }; + + pinctrl_hdmi: hdmigrp { + fsl,pins = < + /* NOTE: DDC is done via I2C2, so DON'T configure DDC + * pins for HDMI! + */ + MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x1f8b0 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001f8b1 + MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001f8b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX6QDL_PAD_NANDF_CS3__I2C4_SDA 0x4001f8b1 + MX6QDL_PAD_NANDF_WP_B__I2C4_SCL 0x4001f8b1 + >; + }; + + pinctrl_i2cmux: i2cmuxgrp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT16__GPIO5_IO10 0x1b0b0 + MX6QDL_PAD_DISP0_DAT17__GPIO5_IO11 0x1b0b0 + >; + }; + + pinctrl_leds: ledsgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0 + MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0x8 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbh1: usbh1grp { + fsl,pins = < + MX6QDL_PAD_GPIO_3__USB_H1_OC 0x1B058 + MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1B058 + + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x1b0b0 + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170f9 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100f9 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170f9 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170f9 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170f9 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170f9 + MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x1b0b0 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17099 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10099 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17099 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17099 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17099 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17099 + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17099 + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17099 + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17099 + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17099 + MX6QDL_PAD_SD3_RST__SD3_RESET 0x1b0b1 + >; + }; +}; -- cgit v1.2.3-59-g8ed1b From d1f1858f51be4d7900fe2bac6394c8dfc641f2c4 Mon Sep 17 00:00:00 2001 From: Oleksij Rempel Date: Mon, 2 Nov 2020 10:02:12 +0100 Subject: ARM: dts: add Van der Laan LANMCU board Van der Laan LANMCU is a module for the food storage rooms to control proper gas composition. Co-developed-by: Robin van der Gracht Signed-off-by: Robin van der Gracht Signed-off-by: Oleksij Rempel Reviewed-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/imx6dl-lanmcu.dts | 470 ++++++++++++++++++++++++++++++++++++ 2 files changed, 471 insertions(+) create mode 100644 arch/arm/boot/dts/imx6dl-lanmcu.dts (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 526e6c237a9c..d3275fe3095f 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -451,6 +451,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ imx6dl-icore.dtb \ imx6dl-icore-mipi.dtb \ imx6dl-icore-rqs.dtb \ + imx6dl-lanmcu.dtb \ imx6dl-mamoj.dtb \ imx6dl-nit6xlite.dtb \ imx6dl-nitrogen6x.dtb \ diff --git a/arch/arm/boot/dts/imx6dl-lanmcu.dts b/arch/arm/boot/dts/imx6dl-lanmcu.dts new file mode 100644 index 000000000000..6b6e6fcdea9c --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-lanmcu.dts @@ -0,0 +1,470 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2019 Protonic Holland + * Copyright (c) 2020 Oleksij Rempel , Pengutronix + */ + +/dts-v1/; +#include +#include +#include "imx6dl.dtsi" + +/ { + model = "Van der Laan LANMCU"; + compatible = "vdl,lanmcu", "fsl,imx6dl"; + + chosen { + stdout-path = &uart4; + }; + + clock_ksz8081: clock-ksz8081 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 5000000 0>; + brightness-levels = <0 1000>; + num-interpolated-steps = <20>; + default-brightness-level = <19>; + }; + + display { + compatible = "fsl,imx-parallel-display"; + pinctrl-0 = <&pinctrl_ipu1_disp>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + display_in: endpoint { + remote-endpoint = <&ipu1_di0_disp0>; + }; + }; + + port@1 { + reg = <1>; + + display_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_leds>; + + led-0 { + label = "debug0"; + function = LED_FUNCTION_STATUS; + gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + panel { + compatible = "edt,etm0700g0bdh6"; + backlight = <&backlight>; + + port { + panel_in: endpoint { + remote-endpoint = <&display_out>; + }; + }; + }; + + reg_otg_vbus: regulator-otg-vbus { + compatible = "regulator-fixed"; + regulator-name = "otg-vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + usdhc2_wifi_pwrseq: usdhc2-wifi-pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wifi_npd>; + reset-gpios = <&gpio6 10 GPIO_ACTIVE_LOW>; + }; + +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can1>; + status = "okay"; +}; + +&can2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can2>; + status = "okay"; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rmii"; + clocks = <&clks IMX6QDL_CLK_ENET>, + <&clks IMX6QDL_CLK_ENET>, + <&clock_ksz8081>; + clock-names = "ipg", "ahb", "ptp"; + phy-handle = <&rgmii_phy>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + /* Microchip KSZ8081RNA PHY */ + rgmii_phy: ethernet-phy@0 { + reg = <0>; + interrupts-extended = <&gpio5 23 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpio5 22 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <300>; + }; + }; +}; + +&gpio1 { + gpio-line-names = + "", "SD1_CD", "", "", "", "", "", "", + "DEBUG_0", "BL_PWM", "", "", "", "", "", "", + "", "", "", "", "", "", "", "ENET_LED_GREEN", + "", "", "", "", "", "", "", ""; +}; + +&gpio3 { + gpio-line-names = + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "TS_INT", "USB_OTG1_OC", "USB_OTG1_PWR", "", + "", "", "", "", "UART2_CTS", "", "UART3_CTS", ""; +}; + +&gpio5 { + gpio-line-names = + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "ENET_RST", "ENET_INT", + "", "", "I2C1_SDA", "I2C1_SCL", "", "", "", ""; +}; + +&gpio6 { + gpio-line-names = + "", "", "", "", "", "", "", "", + "", "", "WLAN_REG_ON", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpio7 { + gpio-line-names = + "", "", "", "", "", "", "", "", + "EMMC_RST", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + /* additional i2c devices are added automatically by the boot loader */ +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + touchscreen@38 { + compatible = "edt,edt-ft5406"; + reg = <0x38>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ts_edt>; + interrupts-extended = <&gpio3 20 IRQ_TYPE_EDGE_FALLING>; + + touchscreen-size-x = <1792>; + touchscreen-size-y = <1024>; + + touchscreen-fuzz-x = <0>; + touchscreen-fuzz-y = <0>; + + /* Touch screen calibration */ + threshold = <50>; + gain = <5>; + offset = <10>; + }; + + rtc@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + }; +}; + +&ipu1_di0_disp0 { + remote-endpoint = <&display_in>; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + linux,rs485-enabled-at-boot-time; + uart-has-rtscts; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + linux,rs485-enabled-at-boot-time; + uart-has-rtscts; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + phy_type = "utmi"; + dr_mode = "host"; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; + no-1-8-v; + disable-wp; + cap-sd-highspeed; + no-mmc; + no-sdio; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + no-1-8-v; + non-removable; + mmc-pwrseq = <&usdhc2_wifi_pwrseq>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + wifi@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + }; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + bus-width = <8>; + no-1-8-v; + non-removable; + no-sd; + no-sdio; + status = "okay"; +}; + +&iomuxc { + pinctrl_can1: can1grp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b000 + MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x3008 + >; + }; + + pinctrl_can2: can2grp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b000 + MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x3008 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + /* MX6QDL_ENET_PINGRP4 */ + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0 + MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0 + MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0 + MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 + MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0 + MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0 + MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0 + + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x1b0b0 + /* Phy reset */ + MX6QDL_PAD_CSI0_DAT4__GPIO5_IO22 0x1b0b0 + /* nINTRP */ + MX6QDL_PAD_CSI0_DAT5__GPIO5_IO23 0x1b0b0 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001f8b1 + MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001f8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_ipu1_disp: ipudisp1grp { + fsl,pins = < + /* DSE 0x30 => 25 Ohm, 0x20 => 37 Ohm, 0x10 => 75 Ohm */ + MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x30 + MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x30 + MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x30 + MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x30 + MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x30 + MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x30 + MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x30 + MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x30 + MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x30 + MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x30 + MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x30 + MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x30 + MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x30 + MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x30 + MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x30 + MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x30 + MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x30 + MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x30 + MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x30 + MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x30 + MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x30 + MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x30 + >; + }; + + pinctrl_leds: ledsgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX6QDL_PAD_GPIO_9__PWM1_OUT 0x8 + >; + }; + + pinctrl_ts_edt: ts1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x1b0b0 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_EIM_D26__UART2_RX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D27__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D28__UART2_CTS_B 0x130b1 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D30__UART3_CTS_B 0x130b1 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x1b0b0 + /* power enable, high active */ + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170f9 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100f9 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170f9 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170f9 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170f9 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170f9 + MX6QDL_PAD_GPIO_1__SD1_CD_B 0x1b0b0 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170b9 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100b9 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170b9 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170b9 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170b9 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17099 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10099 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17099 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17099 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17099 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17099 + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17099 + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17099 + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17099 + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17099 + MX6QDL_PAD_SD3_RST__SD3_RESET 0x1b0b1 + >; + }; + + pinctrl_wifi_npd: wifigrp { + fsl,pins = < + /* WL_REG_ON */ + MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x13069 + >; + }; +}; -- cgit v1.2.3-59-g8ed1b From 7544bfc0866f56326e47f8ec8b3f68c6db496125 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 3 Nov 2020 19:04:54 -0300 Subject: ARM: imx: imx7ulp: Add a comment explaining the B2 silicon version To help the users to understand the meaning of bits 31-28 of the JTAG_ID_REG register, add a comment explaining the value that is expected from a i.MX7ULP rev B2. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/mach-imx/mach-imx7ulp.c | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm') diff --git a/arch/arm/mach-imx/mach-imx7ulp.c b/arch/arm/mach-imx/mach-imx7ulp.c index f6032ea7de8b..a3c8dadec1c5 100644 --- a/arch/arm/mach-imx/mach-imx7ulp.c +++ b/arch/arm/mach-imx/mach-imx7ulp.c @@ -37,6 +37,7 @@ static void __init imx7ulp_set_revision(void) * bit[31:28] of JTAG_ID register defines revision as below from B0: * 0001 B0 * 0010 B1 + * 0011 B2 */ switch (revision >> 28) { case 1: -- cgit v1.2.3-59-g8ed1b From 53cc6bc69e536efe6c1cef98edfb7b3f0a14fabe Mon Sep 17 00:00:00 2001 From: Sven Van Asbroeck Date: Wed, 4 Nov 2020 11:54:18 -0500 Subject: ARM: imx: mach-imx6q: correctly identify i.MX6QP SoCs The i.MX6QP rev 1.1 SoC on my board is mis-identified by Linux: the log (incorrectly) shows "i.MX6Q rev 2.1". Correct this by assuming that every SoC that identifies as i.MX6Q with rev >= 2.0 is really an i.MX6QP. Signed-off-by: Sven Van Asbroeck Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/mach-imx/mach-imx6q.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c index 85c084a716ab..703998ebb52e 100644 --- a/arch/arm/mach-imx/mach-imx6q.c +++ b/arch/arm/mach-imx/mach-imx6q.c @@ -245,8 +245,13 @@ static void __init imx6q_axi_init(void) static void __init imx6q_init_machine(void) { - if (cpu_is_imx6q() && imx_get_soc_revision() == IMX_CHIP_REVISION_2_0) - imx_print_silicon_rev("i.MX6QP", IMX_CHIP_REVISION_1_0); + if (cpu_is_imx6q() && imx_get_soc_revision() >= IMX_CHIP_REVISION_2_0) + /* + * SoCs that identify as i.MX6Q >= rev 2.0 are really i.MX6QP. + * Quirk: i.MX6QP revision = i.MX6Q revision - (1, 0), + * e.g. i.MX6QP rev 1.1 identifies as i.MX6Q rev 2.1. + */ + imx_print_silicon_rev("i.MX6QP", imx_get_soc_revision() - 0x10); else imx_print_silicon_rev(cpu_is_imx6dl() ? "i.MX6DL" : "i.MX6Q", imx_get_soc_revision()); -- cgit v1.2.3-59-g8ed1b From df9dbaf2c415cd94ad520067a1eccfee62f00a33 Mon Sep 17 00:00:00 2001 From: "H. Nikolaus Schaller" Date: Sat, 3 Oct 2020 16:10:00 +0200 Subject: ARM: dts: pandaboard: fix pinmux for gpio user button of Pandaboard ES The pinmux control register offset passed to OMAP4_IOPAD is odd. Fixes: ab9a13665e7c ("ARM: dts: pandaboard: add gpio user button") Cc: stable@vger.kernel.org Signed-off-by: H. Nikolaus Schaller Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap4-panda-es.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/omap4-panda-es.dts b/arch/arm/boot/dts/omap4-panda-es.dts index cfa85aa3da08..6afa8fd7c412 100644 --- a/arch/arm/boot/dts/omap4-panda-es.dts +++ b/arch/arm/boot/dts/omap4-panda-es.dts @@ -46,7 +46,7 @@ button_pins: pinmux_button_pins { pinctrl-single,pins = < - OMAP4_IOPAD(0x11b, PIN_INPUT_PULLUP | MUX_MODE3) /* gpio_113 */ + OMAP4_IOPAD(0x0fc, PIN_INPUT_PULLUP | MUX_MODE3) /* gpio_113 */ >; }; }; -- cgit v1.2.3-59-g8ed1b From b86516452cfd94321900abe7c8ac843c146a8c53 Mon Sep 17 00:00:00 2001 From: "H. Nikolaus Schaller" Date: Sat, 3 Oct 2020 16:10:01 +0200 Subject: ARM: dts: pandaboard es: add bluetooth uart for HCI The wl271 bluetooth uart is connected to uart2. Setup a serdev uart child and separate bluetooth and uart2 pinmux from wl12xx pinmux to better group the pins and muxes. Signed-off-by: H. Nikolaus Schaller Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap4-panda-es.dts | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/omap4-panda-es.dts b/arch/arm/boot/dts/omap4-panda-es.dts index 6afa8fd7c412..7c6886cd738f 100644 --- a/arch/arm/boot/dts/omap4-panda-es.dts +++ b/arch/arm/boot/dts/omap4-panda-es.dts @@ -49,6 +49,22 @@ OMAP4_IOPAD(0x0fc, PIN_INPUT_PULLUP | MUX_MODE3) /* gpio_113 */ >; }; + + bt_pins: pinmux_bt_pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x06c, PIN_OUTPUT | MUX_MODE3) /* gpmc_a22.gpio_46 - BTEN */ + OMAP4_IOPAD(0x072, PIN_OUTPUT_PULLUP | MUX_MODE3) /* gpmc_a25.gpio_49 - BTWAKEUP */ + >; + }; + + uart2_pins: pinmux_uart2_pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x118, PIN_INPUT_PULLUP | MUX_MODE0) /* uart2_cts.uart2_cts - HCI */ + OMAP4_IOPAD(0x11a, PIN_OUTPUT | MUX_MODE0) /* uart2_rts.uart2_rts */ + OMAP4_IOPAD(0x11c, PIN_INPUT_PULLUP | MUX_MODE0) /* uart2_rx.uart2_rx */ + OMAP4_IOPAD(0x11e, PIN_OUTPUT | MUX_MODE0) /* uart2_tx.uart2_tx */ + >; + }; }; &led_wkgpio_pins { @@ -80,3 +96,19 @@ &gpio1_target { ti,no-reset-on-init; }; + +&wl12xx_gpio { + pinctrl-single,pins = < + OMAP4_IOPAD(0x066, PIN_OUTPUT | MUX_MODE3) /* gpmc_a19.gpio_43 */ + OMAP4_IOPAD(0x070, PIN_OUTPUT_PULLUP | MUX_MODE3) /* gpmc_a24.gpio_48 */ + >; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins &bt_pins>; + bluetooth: tiwi { + compatible = "ti,wl1271-st"; + enable-gpios = <&gpio2 14 GPIO_ACTIVE_HIGH>; /* GPIO_46 */ + }; +}; -- cgit v1.2.3-59-g8ed1b From 35f9a0d32effa3411798c68d7b46f2c7a4d41f9d Mon Sep 17 00:00:00 2001 From: Serge Semin Date: Tue, 20 Oct 2020 14:59:33 +0300 Subject: ARM: dts: am437x: Correct DWC USB3 compatible string Syonpsys IP cores are supposed to be defined with "snps" vendor-prefix. Use it instead of the deprecated "synopsys" one. Signed-off-by: Serge Semin Reviewed-by: Krzysztof Kozlowski Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am437x-l4.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/am437x-l4.dtsi b/arch/arm/boot/dts/am437x-l4.dtsi index c220dc3c4e0f..700c7650c845 100644 --- a/arch/arm/boot/dts/am437x-l4.dtsi +++ b/arch/arm/boot/dts/am437x-l4.dtsi @@ -2388,7 +2388,7 @@ ranges = <0 0 0x20000>; usb1: usb@10000 { - compatible = "synopsys,dwc3"; + compatible = "snps,dwc3"; reg = <0x10000 0x10000>; interrupts = , , @@ -2468,7 +2468,7 @@ ranges = <0 0 0x20000>; usb2: usb@10000 { - compatible = "synopsys,dwc3"; + compatible = "snps,dwc3"; reg = <0x10000 0x10000>; interrupts = , , -- cgit v1.2.3-59-g8ed1b From bdb65ec381f5503b257e41669f9998492b6083aa Mon Sep 17 00:00:00 2001 From: Serge Semin Date: Tue, 20 Oct 2020 14:59:52 +0300 Subject: ARM: dts: omap5: Harmonize DWC USB3 DT nodes name In accordance with the DWC USB3 bindings the corresponding node name is suppose to comply with the Generic USB HCD DT schema, which requires the USB nodes to have the name acceptable by the regexp: "^usb(@.*)?" . Make sure the "snps,dwc3"-compatible nodes are correctly named. Signed-off-by: Serge Semin Acked-by: Krzysztof Kozlowski Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap5-l4.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/omap5-l4.dtsi b/arch/arm/boot/dts/omap5-l4.dtsi index f3d3a16b7c64..887b3359dd5a 100644 --- a/arch/arm/boot/dts/omap5-l4.dtsi +++ b/arch/arm/boot/dts/omap5-l4.dtsi @@ -194,7 +194,7 @@ #size-cells = <1>; utmi-mode = <2>; ranges = <0 0 0x20000>; - dwc3: dwc3@10000 { + dwc3: usb@10000 { compatible = "snps,dwc3"; reg = <0x10000 0x10000>; interrupts = , -- cgit v1.2.3-59-g8ed1b From f487e6d6c5c6d1adb56d1752ca16b9d6c7c24068 Mon Sep 17 00:00:00 2001 From: Alexander Dahl Date: Mon, 5 Oct 2020 22:34:48 +0200 Subject: ARM: dts: omap: Fix schema warnings for pwm-leds The node names for devices using the pwm-leds driver follow a certain naming scheme (now). Parent node name is not enforced, but recommended by DT project. DTC arch/arm/boot/dts/omap3-beagle-xm.dt.yaml CHECK arch/arm/boot/dts/omap3-beagle-xm.dt.yaml /home/alex/build/linux/arch/arm/boot/dts/omap3-beagle-xm.dt.yaml: pwmleds: 'pmu_stat' does not match any of the regexes: '^led(-[0-9a-f]+)?$', 'pinctrl-[0-9]+' From schema: /home/alex/src/linux/leds/Documentation/devicetree/bindings/leds/leds-pwm.yaml DTC arch/arm/boot/dts/omap3-beagle-xm-ab.dt.yaml CHECK arch/arm/boot/dts/omap3-beagle-xm-ab.dt.yaml /home/alex/build/linux/arch/arm/boot/dts/omap3-beagle-xm-ab.dt.yaml: pwmleds: 'pmu_stat' does not match any of the regexes: '^led(-[0-9a-f]+)?$', 'pinctrl-[0-9]+' From schema: /home/alex/src/linux/leds/Documentation/devicetree/bindings/leds/leds-pwm.yaml DTC arch/arm/boot/dts/omap3-overo-alto35.dt.yaml CHECK arch/arm/boot/dts/omap3-overo-alto35.dt.yaml /home/alex/build/linux/arch/arm/boot/dts/omap3-overo-alto35.dt.yaml: pwmleds: 'overo' does not match any of the regexes: '^led(-[0-9a-f]+)?$', 'pinctrl-[0-9]+' From schema: /home/alex/src/linux/leds/Documentation/devicetree/bindings/leds/leds-pwm.yaml DTC arch/arm/boot/dts/omap3-overo-chestnut43.dt.yaml CHECK arch/arm/boot/dts/omap3-overo-chestnut43.dt.yaml /home/alex/build/linux/arch/arm/boot/dts/omap3-overo-chestnut43.dt.yaml: pwmleds: 'overo' does not match any of the regexes: '^led(-[0-9a-f]+)?$', 'pinctrl-[0-9]+' From schema: /home/alex/src/linux/leds/Documentation/devicetree/bindings/leds/leds-pwm.yaml DTC arch/arm/boot/dts/omap3-overo-gallop43.dt.yaml CHECK arch/arm/boot/dts/omap3-overo-gallop43.dt.yaml /home/alex/build/linux/arch/arm/boot/dts/omap3-overo-gallop43.dt.yaml: pwmleds: 'overo' does not match any of the regexes: '^led(-[0-9a-f]+)?$', 'pinctrl-[0-9]+' From schema: /home/alex/src/linux/leds/Documentation/devicetree/bindings/leds/leds-pwm.yaml DTC arch/arm/boot/dts/omap3-overo-palo35.dt.yaml CHECK arch/arm/boot/dts/omap3-overo-palo35.dt.yaml /home/alex/build/linux/arch/arm/boot/dts/omap3-overo-palo35.dt.yaml: pwmleds: 'overo' does not match any of the regexes: '^led(-[0-9a-f]+)?$', 'pinctrl-[0-9]+' From schema: /home/alex/src/linux/leds/Documentation/devicetree/bindings/leds/leds-pwm.yaml DTC arch/arm/boot/dts/omap3-overo-palo43.dt.yaml CHECK arch/arm/boot/dts/omap3-overo-palo43.dt.yaml /home/alex/build/linux/arch/arm/boot/dts/omap3-overo-palo43.dt.yaml: pwmleds: 'overo' does not match any of the regexes: '^led(-[0-9a-f]+)?$', 'pinctrl-[0-9]+' From schema: /home/alex/src/linux/leds/Documentation/devicetree/bindings/leds/leds-pwm.yaml DTC arch/arm/boot/dts/omap3-overo-storm-alto35.dt.yaml CHECK arch/arm/boot/dts/omap3-overo-storm-alto35.dt.yaml /home/alex/build/linux/arch/arm/boot/dts/omap3-overo-storm-alto35.dt.yaml: pwmleds: 'overo' does not match any of the regexes: '^led(-[0-9a-f]+)?$', 'pinctrl-[0-9]+' From schema: /home/alex/src/linux/leds/Documentation/devicetree/bindings/leds/leds-pwm.yaml DTC arch/arm/boot/dts/omap3-overo-storm-chestnut43.dt.yaml CHECK arch/arm/boot/dts/omap3-overo-storm-chestnut43.dt.yaml /home/alex/build/linux/arch/arm/boot/dts/omap3-overo-storm-chestnut43.dt.yaml: pwmleds: 'overo' does not match any of the regexes: '^led(-[0-9a-f]+)?$', 'pinctrl-[0-9]+' From schema: /home/alex/src/linux/leds/Documentation/devicetree/bindings/leds/leds-pwm.yaml DTC arch/arm/boot/dts/omap3-overo-storm-gallop43.dt.yaml CHECK arch/arm/boot/dts/omap3-overo-storm-gallop43.dt.yaml /home/alex/build/linux/arch/arm/boot/dts/omap3-overo-storm-gallop43.dt.yaml: pwmleds: 'overo' does not match any of the regexes: '^led(-[0-9a-f]+)?$', 'pinctrl-[0-9]+' From schema: /home/alex/src/linux/leds/Documentation/devicetree/bindings/leds/leds-pwm.yaml DTC arch/arm/boot/dts/omap3-overo-storm-palo35.dt.yaml CHECK arch/arm/boot/dts/omap3-overo-storm-palo35.dt.yaml /home/alex/build/linux/arch/arm/boot/dts/omap3-overo-storm-palo35.dt.yaml: pwmleds: 'overo' does not match any of the regexes: '^led(-[0-9a-f]+)?$', 'pinctrl-[0-9]+' From schema: /home/alex/src/linux/leds/Documentation/devicetree/bindings/leds/leds-pwm.yaml DTC arch/arm/boot/dts/omap3-overo-storm-palo43.dt.yaml CHECK arch/arm/boot/dts/omap3-overo-storm-palo43.dt.yaml /home/alex/build/linux/arch/arm/boot/dts/omap3-overo-storm-palo43.dt.yaml: pwmleds: 'overo' does not match any of the regexes: '^led(-[0-9a-f]+)?$', 'pinctrl-[0-9]+' From schema: /home/alex/src/linux/leds/Documentation/devicetree/bindings/leds/leds-pwm.yaml DTC arch/arm/boot/dts/omap3-overo-storm-summit.dt.yaml CHECK arch/arm/boot/dts/omap3-overo-storm-summit.dt.yaml /home/alex/build/linux/arch/arm/boot/dts/omap3-overo-storm-summit.dt.yaml: pwmleds: 'overo' does not match any of the regexes: '^led(-[0-9a-f]+)?$', 'pinctrl-[0-9]+' From schema: /home/alex/src/linux/leds/Documentation/devicetree/bindings/leds/leds-pwm.yaml DTC arch/arm/boot/dts/omap3-overo-storm-tobi.dt.yaml CHECK arch/arm/boot/dts/omap3-overo-storm-tobi.dt.yaml /home/alex/build/linux/arch/arm/boot/dts/omap3-overo-storm-tobi.dt.yaml: pwmleds: 'overo' does not match any of the regexes: '^led(-[0-9a-f]+)?$', 'pinctrl-[0-9]+' From schema: /home/alex/src/linux/leds/Documentation/devicetree/bindings/leds/leds-pwm.yaml DTC arch/arm/boot/dts/omap3-overo-storm-tobiduo.dt.yaml CHECK arch/arm/boot/dts/omap3-overo-storm-tobiduo.dt.yaml /home/alex/build/linux/arch/arm/boot/dts/omap3-overo-storm-tobiduo.dt.yaml: pwmleds: 'overo' does not match any of the regexes: '^led(-[0-9a-f]+)?$', 'pinctrl-[0-9]+' From schema: /home/alex/src/linux/leds/Documentation/devicetree/bindings/leds/leds-pwm.yaml DTC arch/arm/boot/dts/omap3-overo-summit.dt.yaml CHECK arch/arm/boot/dts/omap3-overo-summit.dt.yaml /home/alex/build/linux/arch/arm/boot/dts/omap3-overo-summit.dt.yaml: pwmleds: 'overo' does not match any of the regexes: '^led(-[0-9a-f]+)?$', 'pinctrl-[0-9]+' From schema: /home/alex/src/linux/leds/Documentation/devicetree/bindings/leds/leds-pwm.yaml DTC arch/arm/boot/dts/omap3-overo-tobi.dt.yaml CHECK arch/arm/boot/dts/omap3-overo-tobi.dt.yaml /home/alex/build/linux/arch/arm/boot/dts/omap3-overo-tobi.dt.yaml: pwmleds: 'overo' does not match any of the regexes: '^led(-[0-9a-f]+)?$', 'pinctrl-[0-9]+' From schema: /home/alex/src/linux/leds/Documentation/devicetree/bindings/leds/leds-pwm.yaml DTC arch/arm/boot/dts/omap3-overo-tobiduo.dt.yaml CHECK arch/arm/boot/dts/omap3-overo-tobiduo.dt.yaml /home/alex/build/linux/arch/arm/boot/dts/omap3-overo-tobiduo.dt.yaml: pwmleds: 'overo' does not match any of the regexes: '^led(-[0-9a-f]+)?$', 'pinctrl-[0-9]+' From schema: /home/alex/src/linux/leds/Documentation/devicetree/bindings/leds/leds-pwm.yaml DTC arch/arm/boot/dts/omap4-kc1.dt.yaml CHECK arch/arm/boot/dts/omap4-kc1.dt.yaml /home/alex/build/linux/arch/arm/boot/dts/omap4-kc1.dt.yaml: pwmleds: 'green', 'orange' do not match any of the regexes: '^led(-[0-9a-f]+)?$', 'pinctrl-[0-9]+' From schema: /home/alex/src/linux/leds/Documentation/devicetree/bindings/leds/leds-pwm.yaml DTC arch/arm/boot/dts/omap4-sdp.dt.yaml CHECK arch/arm/boot/dts/omap4-sdp.dt.yaml /home/alex/build/linux/arch/arm/boot/dts/omap4-sdp.dt.yaml: pwmleds: 'charging', 'kpad' do not match any of the regexes: '^led(-[0-9a-f]+)?$', 'pinctrl-[0-9]+' From schema: /home/alex/src/linux/leds/Documentation/devicetree/bindings/leds/leds-pwm.yaml DTC arch/arm/boot/dts/omap4-sdp-es23plus.dt.yaml CHECK arch/arm/boot/dts/omap4-sdp-es23plus.dt.yaml /home/alex/build/linux/arch/arm/boot/dts/omap4-sdp-es23plus.dt.yaml: pwmleds: 'charging', 'kpad' do not match any of the regexes: '^led(-[0-9a-f]+)?$', 'pinctrl-[0-9]+' From schema: /home/alex/src/linux/leds/Documentation/devicetree/bindings/leds/leds-pwm.yaml Signed-off-by: Alexander Dahl Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap3-beagle-xm.dts | 10 +++++----- arch/arm/boot/dts/omap3-overo-base.dtsi | 4 ++-- arch/arm/boot/dts/omap4-kc1.dts | 6 +++--- arch/arm/boot/dts/omap4-sdp.dts | 26 ++++++++++++++------------ 4 files changed, 24 insertions(+), 22 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/omap3-beagle-xm.dts b/arch/arm/boot/dts/omap3-beagle-xm.dts index 252507cf300b..a858ebfa1500 100644 --- a/arch/arm/boot/dts/omap3-beagle-xm.dts +++ b/arch/arm/boot/dts/omap3-beagle-xm.dts @@ -34,26 +34,26 @@ clock-frequency = <26000000>; }; - leds { + led-controller-1 { compatible = "gpio-leds"; - heartbeat { + led-1 { label = "beagleboard::usr0"; gpios = <&gpio5 22 GPIO_ACTIVE_HIGH>; /* 150 -> D6 LED */ linux,default-trigger = "heartbeat"; }; - mmc { + led-2 { label = "beagleboard::usr1"; gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>; /* 149 -> D7 LED */ linux,default-trigger = "mmc0"; }; }; - pwmleds { + led-controller-2 { compatible = "pwm-leds"; - pmu_stat { + led-3 { label = "beagleboard::pmu_stat"; pwms = <&twl_pwmled 1 7812500>; max-brightness = <127>; diff --git a/arch/arm/boot/dts/omap3-overo-base.dtsi b/arch/arm/boot/dts/omap3-overo-base.dtsi index 971d3e250515..006a6d97231c 100644 --- a/arch/arm/boot/dts/omap3-overo-base.dtsi +++ b/arch/arm/boot/dts/omap3-overo-base.dtsi @@ -14,10 +14,10 @@ reg = <0 0>; }; - pwmleds { + led-controller { compatible = "pwm-leds"; - overo { + led-1 { label = "overo:blue:COM"; pwms = <&twl_pwmled 1 7812500>; max-brightness = <127>; diff --git a/arch/arm/boot/dts/omap4-kc1.dts b/arch/arm/boot/dts/omap4-kc1.dts index 31d856b58f8a..e59d17b25a1d 100644 --- a/arch/arm/boot/dts/omap4-kc1.dts +++ b/arch/arm/boot/dts/omap4-kc1.dts @@ -15,16 +15,16 @@ reg = <0x80000000 0x20000000>; /* 512 MB */ }; - pwmleds { + led-controller { compatible = "pwm-leds"; - green { + led-1 { label = "green"; pwms = <&twl_pwm 0 7812500>; max-brightness = <127>; }; - orange { + led-2 { label = "orange"; pwms = <&twl_pwm 1 7812500>; max-brightness = <127>; diff --git a/arch/arm/boot/dts/omap4-sdp.dts b/arch/arm/boot/dts/omap4-sdp.dts index afb49a2d6963..9e976140f34a 100644 --- a/arch/arm/boot/dts/omap4-sdp.dts +++ b/arch/arm/boot/dts/omap4-sdp.dts @@ -45,58 +45,60 @@ regulator-boot-on; }; - leds { + led-controller-1 { compatible = "gpio-leds"; - debug0 { + + led-1 { label = "omap4:green:debug0"; gpios = <&gpio2 29 GPIO_ACTIVE_HIGH>; /* 61 */ }; - debug1 { + led-2 { label = "omap4:green:debug1"; gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>; /* 30 */ }; - debug2 { + led-3 { label = "omap4:green:debug2"; gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; /* 7 */ }; - debug3 { + led-4 { label = "omap4:green:debug3"; gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; /* 8 */ }; - debug4 { + led-5 { label = "omap4:green:debug4"; gpios = <&gpio2 18 GPIO_ACTIVE_HIGH>; /* 50 */ }; - user1 { + led-6 { label = "omap4:blue:user"; gpios = <&gpio6 9 GPIO_ACTIVE_HIGH>; /* 169 */ }; - user2 { + led-7 { label = "omap4:red:user"; gpios = <&gpio6 10 GPIO_ACTIVE_HIGH>; /* 170 */ }; - user3 { + led-8 { label = "omap4:green:user"; gpios = <&gpio5 11 GPIO_ACTIVE_HIGH>; /* 139 */ }; }; - pwmleds { + led-controller-2 { compatible = "pwm-leds"; - kpad { + + led-9 { label = "omap4::keypad"; pwms = <&twl_pwm 0 7812500>; max-brightness = <127>; }; - charging { + led-10 { label = "omap4:green:chrg"; pwms = <&twl_pwmled 0 7812500>; max-brightness = <255>; -- cgit v1.2.3-59-g8ed1b From 06607cfa0ffe2e8b2a3cb56fb1c2ef39ba0c22a3 Mon Sep 17 00:00:00 2001 From: Carl Philipp Klemm Date: Sun, 8 Nov 2020 19:49:56 +0100 Subject: ARM: dts: mapphone: separate out xt894 specific things Remove xt894 specific things from motorola-mapphone-common.dtsi and add them to omap4-droid4-xt894.dts and omap4-droid-bionic-xt875.dts as applicable. Signed-off-by: Carl Philipp Klemm [tony@atomide.com: shortened subject, wrapped description] Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/motorola-mapphone-common.dtsi | 141 +---------------------- arch/arm/boot/dts/omap4-droid-bionic-xt875.dts | 30 +++++ arch/arm/boot/dts/omap4-droid4-xt894.dts | 143 ++++++++++++++++++++++++ 3 files changed, 174 insertions(+), 140 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/motorola-mapphone-common.dtsi b/arch/arm/boot/dts/motorola-mapphone-common.dtsi index 1990239cc6af..0f020a2f0afc 100644 --- a/arch/arm/boot/dts/motorola-mapphone-common.dtsi +++ b/arch/arm/boot/dts/motorola-mapphone-common.dtsi @@ -113,32 +113,9 @@ enable-active-high; }; - gpio_keys { - compatible = "gpio-keys"; - - volume_down { - label = "Volume Down"; - gpios = <&gpio5 26 GPIO_ACTIVE_LOW>; /* gpio154 */ - linux,code = ; - linux,can-disable; - /* Value above 7.95ms for no GPIO hardware debounce */ - debounce-interval = <10>; - }; - - slider { - label = "Keypad Slide"; - gpios = <&gpio4 26 GPIO_ACTIVE_HIGH>; /* gpio122 */ - linux,input-type = ; - linux,code = ; - linux,can-disable; - /* Value above 7.95ms for no GPIO hardware debounce */ - debounce-interval = <10>; - }; - }; - soundcard { compatible = "audio-graph-card"; - label = "Droid 4 Audio"; + label = "Mapphone Audio"; widgets = "Speaker", "Earpiece", @@ -280,80 +257,6 @@ }; }; -&keypad { - keypad,num-rows = <8>; - keypad,num-columns = <8>; - linux,keymap = < - - /* Row 1 */ - MATRIX_KEY(0, 2, KEY_1) - MATRIX_KEY(0, 6, KEY_2) - MATRIX_KEY(2, 3, KEY_3) - MATRIX_KEY(0, 7, KEY_4) - MATRIX_KEY(0, 4, KEY_5) - MATRIX_KEY(5, 5, KEY_6) - MATRIX_KEY(0, 1, KEY_7) - MATRIX_KEY(0, 5, KEY_8) - MATRIX_KEY(0, 0, KEY_9) - MATRIX_KEY(1, 6, KEY_0) - - /* Row 2 */ - MATRIX_KEY(3, 4, KEY_APOSTROPHE) - MATRIX_KEY(7, 6, KEY_Q) - MATRIX_KEY(7, 7, KEY_W) - MATRIX_KEY(7, 2, KEY_E) - MATRIX_KEY(1, 0, KEY_R) - MATRIX_KEY(4, 4, KEY_T) - MATRIX_KEY(1, 2, KEY_Y) - MATRIX_KEY(6, 7, KEY_U) - MATRIX_KEY(2, 2, KEY_I) - MATRIX_KEY(5, 6, KEY_O) - MATRIX_KEY(3, 7, KEY_P) - MATRIX_KEY(6, 5, KEY_BACKSPACE) - - /* Row 3 */ - MATRIX_KEY(5, 4, KEY_TAB) - MATRIX_KEY(5, 7, KEY_A) - MATRIX_KEY(2, 7, KEY_S) - MATRIX_KEY(7, 0, KEY_D) - MATRIX_KEY(2, 6, KEY_F) - MATRIX_KEY(6, 2, KEY_G) - MATRIX_KEY(6, 6, KEY_H) - MATRIX_KEY(1, 4, KEY_J) - MATRIX_KEY(3, 1, KEY_K) - MATRIX_KEY(2, 1, KEY_L) - MATRIX_KEY(4, 6, KEY_ENTER) - - /* Row 4 */ - MATRIX_KEY(3, 6, KEY_LEFTSHIFT) /* KEY_CAPSLOCK */ - MATRIX_KEY(6, 1, KEY_Z) - MATRIX_KEY(7, 4, KEY_X) - MATRIX_KEY(5, 1, KEY_C) - MATRIX_KEY(1, 7, KEY_V) - MATRIX_KEY(2, 4, KEY_B) - MATRIX_KEY(4, 1, KEY_N) - MATRIX_KEY(1, 1, KEY_M) - MATRIX_KEY(3, 5, KEY_COMMA) - MATRIX_KEY(5, 2, KEY_DOT) - MATRIX_KEY(6, 3, KEY_UP) - MATRIX_KEY(7, 3, KEY_OK) - - /* Row 5 */ - MATRIX_KEY(2, 5, KEY_LEFTCTRL) /* KEY_LEFTSHIFT */ - MATRIX_KEY(4, 5, KEY_LEFTALT) /* SYM */ - MATRIX_KEY(6, 0, KEY_MINUS) - MATRIX_KEY(4, 7, KEY_EQUAL) - MATRIX_KEY(1, 5, KEY_SPACE) - MATRIX_KEY(3, 2, KEY_SLASH) - MATRIX_KEY(4, 3, KEY_LEFT) - MATRIX_KEY(5, 3, KEY_DOWN) - MATRIX_KEY(3, 3, KEY_RIGHT) - - /* Side buttons, KEY_VOLUMEDOWN and KEY_PWER are on CPCAP? */ - MATRIX_KEY(5, 0, KEY_VOLUMEUP) - >; -}; - &mmc1 { vmmc-supply = <&vwlan2>; bus-width = <4>; @@ -393,34 +296,6 @@ }; }; -&i2c1 { - led-controller@38 { - compatible = "ti,lm3532"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x38>; - - enable-gpios = <&gpio6 12 GPIO_ACTIVE_HIGH>; - - ramp-up-us = <1024>; - ramp-down-us = <8193>; - - backlight_led: led@0 { - reg = <0>; - led-sources = <2>; - ti,led-mode = <0>; - label = ":backlight"; - }; - - led@1 { - reg = <1>; - led-sources = <1>; - ti,led-mode = <0>; - label = ":kbd_backlight"; - }; - }; -}; - &i2c2 { touchscreen@4a { compatible = "atmel,maxtouch"; @@ -794,20 +669,6 @@ "0", "0", "-1"; }; - - lis3dh: accelerometer@18 { - compatible = "st,lis3dh-accel"; - reg = <0x18>; - - vdd-supply = <&vhvio>; - - interrupt-parent = <&gpio2>; - interrupts = <2 IRQ_TYPE_EDGE_BOTH>; /* gpio34 */ - - rotation-matrix = "0", "-1", "0", - "1", "0", "0", - "0", "0", "1"; - }; }; &mcbsp2 { diff --git a/arch/arm/boot/dts/omap4-droid-bionic-xt875.dts b/arch/arm/boot/dts/omap4-droid-bionic-xt875.dts index ba5c35b7027d..49b2a8d55356 100644 --- a/arch/arm/boot/dts/omap4-droid-bionic-xt875.dts +++ b/arch/arm/boot/dts/omap4-droid-bionic-xt875.dts @@ -7,3 +7,33 @@ model = "Motorola Droid Bionic XT875"; compatible = "motorola,droid-bionic", "ti,omap4430", "ti,omap4"; }; + +&keypad { + keypad,num-rows = <8>; + keypad,num-columns = <8>; + linux,keymap = < + MATRIX_KEY(5, 0, KEY_VOLUMEUP) + MATRIX_KEY(3, 0, KEY_VOLUMEDOWN) + >; +}; + +&i2c1 { + led-controller@38 { + compatible = "ti,lm3532"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x38>; + + enable-gpios = <&gpio6 12 GPIO_ACTIVE_HIGH>; + + ramp-up-us = <1024>; + ramp-down-us = <8193>; + + backlight_led: led@0 { + reg = <0>; + led-sources = <2>; + ti,led-mode = <0>; + label = ":backlight"; + }; + }; +}; diff --git a/arch/arm/boot/dts/omap4-droid4-xt894.dts b/arch/arm/boot/dts/omap4-droid4-xt894.dts index c0d2fd92aea3..3ea4c5b9fd31 100644 --- a/arch/arm/boot/dts/omap4-droid4-xt894.dts +++ b/arch/arm/boot/dts/omap4-droid4-xt894.dts @@ -3,7 +3,150 @@ #include "motorola-mapphone-common.dtsi" +/ { + gpio_keys { + compatible = "gpio-keys"; + + volume_down { + label = "Volume Down"; + gpios = <&gpio5 26 GPIO_ACTIVE_LOW>; /* gpio154 */ + linux,code = ; + linux,can-disable; + /* Value above 7.95ms for no GPIO hardware debounce */ + debounce-interval = <10>; + }; + + slider { + label = "Keypad Slide"; + gpios = <&gpio4 26 GPIO_ACTIVE_HIGH>; /* gpio122 */ + linux,input-type = ; + linux,code = ; + linux,can-disable; + /* Value above 7.95ms for no GPIO hardware debounce */ + debounce-interval = <10>; + }; + }; +}; + / { model = "Motorola Droid 4 XT894"; compatible = "motorola,droid4", "ti,omap4430", "ti,omap4"; }; + +&keypad { + keypad,num-rows = <8>; + keypad,num-columns = <8>; + linux,keymap = < + + /* Row 1 */ + MATRIX_KEY(0, 2, KEY_1) + MATRIX_KEY(0, 6, KEY_2) + MATRIX_KEY(2, 3, KEY_3) + MATRIX_KEY(0, 7, KEY_4) + MATRIX_KEY(0, 4, KEY_5) + MATRIX_KEY(5, 5, KEY_6) + MATRIX_KEY(0, 1, KEY_7) + MATRIX_KEY(0, 5, KEY_8) + MATRIX_KEY(0, 0, KEY_9) + MATRIX_KEY(1, 6, KEY_0) + + /* Row 2 */ + MATRIX_KEY(3, 4, KEY_APOSTROPHE) + MATRIX_KEY(7, 6, KEY_Q) + MATRIX_KEY(7, 7, KEY_W) + MATRIX_KEY(7, 2, KEY_E) + MATRIX_KEY(1, 0, KEY_R) + MATRIX_KEY(4, 4, KEY_T) + MATRIX_KEY(1, 2, KEY_Y) + MATRIX_KEY(6, 7, KEY_U) + MATRIX_KEY(2, 2, KEY_I) + MATRIX_KEY(5, 6, KEY_O) + MATRIX_KEY(3, 7, KEY_P) + MATRIX_KEY(6, 5, KEY_BACKSPACE) + + /* Row 3 */ + MATRIX_KEY(5, 4, KEY_TAB) + MATRIX_KEY(5, 7, KEY_A) + MATRIX_KEY(2, 7, KEY_S) + MATRIX_KEY(7, 0, KEY_D) + MATRIX_KEY(2, 6, KEY_F) + MATRIX_KEY(6, 2, KEY_G) + MATRIX_KEY(6, 6, KEY_H) + MATRIX_KEY(1, 4, KEY_J) + MATRIX_KEY(3, 1, KEY_K) + MATRIX_KEY(2, 1, KEY_L) + MATRIX_KEY(4, 6, KEY_ENTER) + + /* Row 4 */ + MATRIX_KEY(3, 6, KEY_LEFTSHIFT) /* KEY_CAPSLOCK */ + MATRIX_KEY(6, 1, KEY_Z) + MATRIX_KEY(7, 4, KEY_X) + MATRIX_KEY(5, 1, KEY_C) + MATRIX_KEY(1, 7, KEY_V) + MATRIX_KEY(2, 4, KEY_B) + MATRIX_KEY(4, 1, KEY_N) + MATRIX_KEY(1, 1, KEY_M) + MATRIX_KEY(3, 5, KEY_COMMA) + MATRIX_KEY(5, 2, KEY_DOT) + MATRIX_KEY(6, 3, KEY_UP) + MATRIX_KEY(7, 3, KEY_OK) + + /* Row 5 */ + MATRIX_KEY(2, 5, KEY_LEFTCTRL) /* KEY_LEFTSHIFT */ + MATRIX_KEY(4, 5, KEY_LEFTALT) /* SYM */ + MATRIX_KEY(6, 0, KEY_MINUS) + MATRIX_KEY(4, 7, KEY_EQUAL) + MATRIX_KEY(1, 5, KEY_SPACE) + MATRIX_KEY(3, 2, KEY_SLASH) + MATRIX_KEY(4, 3, KEY_LEFT) + MATRIX_KEY(5, 3, KEY_DOWN) + MATRIX_KEY(3, 3, KEY_RIGHT) + + /* Side buttons, KEY_VOLUMEDOWN and KEY_PWER are on CPCAP? */ + MATRIX_KEY(5, 0, KEY_VOLUMEUP) + >; +}; + +&i2c1 { + led-controller@38 { + compatible = "ti,lm3532"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x38>; + + enable-gpios = <&gpio6 12 GPIO_ACTIVE_HIGH>; + + ramp-up-us = <1024>; + ramp-down-us = <8193>; + + backlight_led: led@0 { + reg = <0>; + led-sources = <2>; + ti,led-mode = <0>; + label = ":backlight"; + }; + + led@1 { + reg = <1>; + led-sources = <1>; + ti,led-mode = <0>; + label = ":kbd_backlight"; + }; + }; +}; + +&i2c4 { + lis3dh: accelerometer@18 { + compatible = "st,lis3dh-accel"; + reg = <0x18>; + + vdd-supply = <&vhvio>; + + interrupt-parent = <&gpio2>; + interrupts = <2 IRQ_TYPE_EDGE_BOTH>; /* gpio34 */ + + rotation-matrix = "0", "-1", "0", + "1", "0", "0", + "0", "0", "1"; + }; +}; -- cgit v1.2.3-59-g8ed1b From 5a7b624037625adcfd247299aa6f9d9257c97371 Mon Sep 17 00:00:00 2001 From: Carl Philipp Klemm Date: Sun, 8 Nov 2020 19:43:39 +0100 Subject: ARM: dts: xt875: add section for kionix kxtf9 Add section for kionix kxtf9. Signed-off-by: Carl Philipp Klemm [tony@atomide.com: removed extra header from description] Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap4-droid-bionic-xt875.dts | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/omap4-droid-bionic-xt875.dts b/arch/arm/boot/dts/omap4-droid-bionic-xt875.dts index 49b2a8d55356..ccf03a743678 100644 --- a/arch/arm/boot/dts/omap4-droid-bionic-xt875.dts +++ b/arch/arm/boot/dts/omap4-droid-bionic-xt875.dts @@ -37,3 +37,19 @@ }; }; }; + +&i2c4 { + kxtf9: accelerometer@f { + compatible = "kionix,kxtf9"; + reg = <0x0f>; + + vdd-supply = <&vhvio>; + + interrupt-parent = <&gpio2>; + interrupts = <2 IRQ_TYPE_EDGE_RISING>; + + rotation-matrix = "0", "-1", "0", + "1", "0", "0", + "0", "0", "1"; + }; +}; -- cgit v1.2.3-59-g8ed1b From 5334df3a4bc50f422684291d045aa2c821d7ff0b Mon Sep 17 00:00:00 2001 From: Sylwester Nawrocki Date: Wed, 4 Nov 2020 11:36:55 +0100 Subject: ARM: dts: exynos: Add interconnect properties to Exynos4412 bus nodes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This patch adds the following properties for Exynos4412 interconnect bus nodes: - interconnects: to declare connections between nodes in order to guarantee PM QoS requirements between nodes, - #interconnect-cells: required by the interconnect framework, - samsung,data-clk-ratio: which allows to specify minimum data clock frequency corresponding to requested bandwidth for each bus. Note that #interconnect-cells is always zero and node IDs are not hardcoded anywhere. Signed-off-by: Artur Świgoń Signed-off-by: Sylwester Nawrocki Tested-by: Chanwoo Choi Reviewed-by: Chanwoo Choi Link: https://lore.kernel.org/r/20201104103657.18007-6-s.nawrocki@samsung.com Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos4412.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/exynos4412.dtsi b/arch/arm/boot/dts/exynos4412.dtsi index fa8e8d6bc4d5..05e215621e7b 100644 --- a/arch/arm/boot/dts/exynos4412.dtsi +++ b/arch/arm/boot/dts/exynos4412.dtsi @@ -383,6 +383,8 @@ clocks = <&clock CLK_DIV_DMC>; clock-names = "bus"; operating-points-v2 = <&bus_dmc_opp_table>; + samsung,data-clock-ratio = <4>; + #interconnect-cells = <0>; status = "disabled"; }; @@ -450,6 +452,8 @@ clocks = <&clock CLK_DIV_GDL>; clock-names = "bus"; operating-points-v2 = <&bus_leftbus_opp_table>; + interconnects = <&bus_dmc>; + #interconnect-cells = <0>; status = "disabled"; }; @@ -466,6 +470,8 @@ clocks = <&clock CLK_ACLK160>; clock-names = "bus"; operating-points-v2 = <&bus_display_opp_table>; + interconnects = <&bus_leftbus &bus_dmc>; + #interconnect-cells = <0>; status = "disabled"; }; -- cgit v1.2.3-59-g8ed1b From 246c1a37f5ff897edec750b6d9325860143cefde Mon Sep 17 00:00:00 2001 From: Artur Świgoń Date: Wed, 4 Nov 2020 11:36:56 +0100 Subject: ARM: dts: exynos: Add interconnects to Exynos4412 mixer MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This patch adds an 'interconnects' property to Exynos4412 DTS in order to declare the interconnect path used by the mixer. Please note that the 'interconnect-names' property is not needed when there is only one path in 'interconnects', in which case calling of_icc_get() with a NULL name simply returns the right path. Signed-off-by: Artur Świgoń Signed-off-by: Sylwester Nawrocki Tested-by: Chanwoo Choi Reviewed-by: Chanwoo Choi Link: https://lore.kernel.org/r/20201104103657.18007-7-s.nawrocki@samsung.com Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos4412.dtsi | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/exynos4412.dtsi b/arch/arm/boot/dts/exynos4412.dtsi index 05e215621e7b..bcb87c5dca88 100644 --- a/arch/arm/boot/dts/exynos4412.dtsi +++ b/arch/arm/boot/dts/exynos4412.dtsi @@ -773,6 +773,7 @@ clock-names = "mixer", "hdmi", "sclk_hdmi", "vp"; clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>, <&clock CLK_VP>; + interconnects = <&bus_display &bus_dmc>; }; &pmu { -- cgit v1.2.3-59-g8ed1b From b357e6aa41011c003b18637024243bf37a3c7369 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 5 Nov 2020 19:41:08 +0100 Subject: ARM: dts: exynos: use hyphens in Exynos3250 node names Use hyphens instead of underscores in the Exynos3250 node names which is expected by naming convention, multiple dtschema files and pointed out by dtc W=2 builds. Use also generic "ppmu" node name for PPMU nodes to match Devicetree specification. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20201105184506.215648-1-krzk@kernel.org --- arch/arm/boot/dts/exynos3250.dtsi | 48 +++++++++++++++++++-------------------- 1 file changed, 24 insertions(+), 24 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi index 75ed82600ec8..c5390ca5a87d 100644 --- a/arch/arm/boot/dts/exynos3250.dtsi +++ b/arch/arm/boot/dts/exynos3250.dtsi @@ -691,25 +691,25 @@ status = "disabled"; }; - ppmu_dmc0: ppmu_dmc0@106a0000 { + ppmu_dmc0: ppmu@106a0000 { compatible = "samsung,exynos-ppmu"; reg = <0x106a0000 0x2000>; status = "disabled"; }; - ppmu_dmc1: ppmu_dmc1@106b0000 { + ppmu_dmc1: ppmu@106b0000 { compatible = "samsung,exynos-ppmu"; reg = <0x106b0000 0x2000>; status = "disabled"; }; - ppmu_cpu: ppmu_cpu@106c0000 { + ppmu_cpu: ppmu@106c0000 { compatible = "samsung,exynos-ppmu"; reg = <0x106c0000 0x2000>; status = "disabled"; }; - ppmu_rightbus: ppmu_rightbus@112a0000 { + ppmu_rightbus: ppmu@112a0000 { compatible = "samsung,exynos-ppmu"; reg = <0x112a0000 0x2000>; clocks = <&cmu CLK_PPMURIGHT>; @@ -717,7 +717,7 @@ status = "disabled"; }; - ppmu_leftbus: ppmu_leftbus0@116a0000 { + ppmu_leftbus: ppmu@116a0000 { compatible = "samsung,exynos-ppmu"; reg = <0x116a0000 0x2000>; clocks = <&cmu CLK_PPMULEFT>; @@ -725,7 +725,7 @@ status = "disabled"; }; - ppmu_camif: ppmu_camif@11ac0000 { + ppmu_camif: ppmu@11ac0000 { compatible = "samsung,exynos-ppmu"; reg = <0x11ac0000 0x2000>; clocks = <&cmu CLK_PPMUCAMIF>; @@ -733,7 +733,7 @@ status = "disabled"; }; - ppmu_lcd0: ppmu_lcd0@11e40000 { + ppmu_lcd0: ppmu@11e40000 { compatible = "samsung,exynos-ppmu"; reg = <0x11e40000 0x2000>; clocks = <&cmu CLK_PPMULCD0>; @@ -741,7 +741,7 @@ status = "disabled"; }; - ppmu_fsys: ppmu_fsys@12630000 { + ppmu_fsys: ppmu@12630000 { compatible = "samsung,exynos-ppmu"; reg = <0x12630000 0x2000>; clocks = <&cmu CLK_PPMUFILE>; @@ -749,7 +749,7 @@ status = "disabled"; }; - ppmu_g3d: ppmu_g3d@13220000 { + ppmu_g3d: ppmu@13220000 { compatible = "samsung,exynos-ppmu"; reg = <0x13220000 0x2000>; clocks = <&cmu CLK_PPMUG3D>; @@ -757,7 +757,7 @@ status = "disabled"; }; - ppmu_mfc: ppmu_mfc@13660000 { + ppmu_mfc: ppmu@13660000 { compatible = "samsung,exynos-ppmu"; reg = <0x13660000 0x2000>; clocks = <&cmu CLK_PPMUMFC_L>; @@ -765,7 +765,7 @@ status = "disabled"; }; - bus_dmc: bus_dmc { + bus_dmc: bus-dmc { compatible = "samsung,exynos-bus"; clocks = <&cmu_dmc CLK_DIV_DMC>; clock-names = "bus"; @@ -773,7 +773,7 @@ status = "disabled"; }; - bus_dmc_opp_table: opp_table1 { + bus_dmc_opp_table: opp-table1 { compatible = "operating-points-v2"; opp-50000000 { @@ -798,7 +798,7 @@ }; }; - bus_leftbus: bus_leftbus { + bus_leftbus: bus-leftbus { compatible = "samsung,exynos-bus"; clocks = <&cmu CLK_DIV_GDL>; clock-names = "bus"; @@ -806,7 +806,7 @@ status = "disabled"; }; - bus_rightbus: bus_rightbus { + bus_rightbus: bus-rightbus { compatible = "samsung,exynos-bus"; clocks = <&cmu CLK_DIV_GDR>; clock-names = "bus"; @@ -814,7 +814,7 @@ status = "disabled"; }; - bus_lcd0: bus_lcd0 { + bus_lcd0: bus-lcd0 { compatible = "samsung,exynos-bus"; clocks = <&cmu CLK_DIV_ACLK_160>; clock-names = "bus"; @@ -822,7 +822,7 @@ status = "disabled"; }; - bus_fsys: bus_fsys { + bus_fsys: bus-fsys { compatible = "samsung,exynos-bus"; clocks = <&cmu CLK_DIV_ACLK_200>; clock-names = "bus"; @@ -830,7 +830,7 @@ status = "disabled"; }; - bus_mcuisp: bus_mcuisp { + bus_mcuisp: bus-mcuisp { compatible = "samsung,exynos-bus"; clocks = <&cmu CLK_DIV_ACLK_400_MCUISP>; clock-names = "bus"; @@ -838,7 +838,7 @@ status = "disabled"; }; - bus_isp: bus_isp { + bus_isp: bus-isp { compatible = "samsung,exynos-bus"; clocks = <&cmu CLK_DIV_ACLK_266>; clock-names = "bus"; @@ -846,7 +846,7 @@ status = "disabled"; }; - bus_peril: bus_peril { + bus_peril: bus-peril { compatible = "samsung,exynos-bus"; clocks = <&cmu CLK_DIV_ACLK_100>; clock-names = "bus"; @@ -854,7 +854,7 @@ status = "disabled"; }; - bus_mfc: bus_mfc { + bus_mfc: bus-mfc { compatible = "samsung,exynos-bus"; clocks = <&cmu CLK_SCLK_MFC>; clock-names = "bus"; @@ -862,7 +862,7 @@ status = "disabled"; }; - bus_leftbus_opp_table: opp_table2 { + bus_leftbus_opp_table: opp-table2 { compatible = "operating-points-v2"; opp-50000000 { @@ -887,7 +887,7 @@ }; }; - bus_mcuisp_opp_table: opp_table3 { + bus_mcuisp_opp_table: opp-table3 { compatible = "operating-points-v2"; opp-50000000 { @@ -907,7 +907,7 @@ }; }; - bus_isp_opp_table: opp_table4 { + bus_isp_opp_table: opp-table4 { compatible = "operating-points-v2"; opp-50000000 { @@ -927,7 +927,7 @@ }; }; - bus_peril_opp_table: opp_table5 { + bus_peril_opp_table: opp-table5 { compatible = "operating-points-v2"; opp-50000000 { -- cgit v1.2.3-59-g8ed1b From 1c6831b472f2e31c42eff579f35a5dd2b5da5435 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 5 Nov 2020 19:45:02 +0100 Subject: ARM: dts: exynos: use hyphens in Exynos4 node names Use hyphens instead of underscores in the Exynos4210 and Exynos4412 node names which is expected by naming convention, multiple dtschema files and pointed out by dtc W=2 builds. Use also generic "ppmu" node name for PPMU nodes to match Devicetree specification. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20201105184506.215648-2-krzk@kernel.org --- arch/arm/boot/dts/exynos4.dtsi | 26 +++++++++++++------------- arch/arm/boot/dts/exynos4210.dtsi | 36 ++++++++++++++++++------------------ arch/arm/boot/dts/exynos4412.dtsi | 18 +++++++++--------- 3 files changed, 40 insertions(+), 40 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi index a1e54449f33f..eab77a66ae8f 100644 --- a/arch/arm/boot/dts/exynos4.dtsi +++ b/arch/arm/boot/dts/exynos4.dtsi @@ -782,7 +782,7 @@ status = "disabled"; }; - ppmu_dmc0: ppmu_dmc0@106a0000 { + ppmu_dmc0: ppmu@106a0000 { compatible = "samsung,exynos-ppmu"; reg = <0x106a0000 0x2000>; clocks = <&clock CLK_PPMUDMC0>; @@ -790,7 +790,7 @@ status = "disabled"; }; - ppmu_dmc1: ppmu_dmc1@106b0000 { + ppmu_dmc1: ppmu@106b0000 { compatible = "samsung,exynos-ppmu"; reg = <0x106b0000 0x2000>; clocks = <&clock CLK_PPMUDMC1>; @@ -798,7 +798,7 @@ status = "disabled"; }; - ppmu_cpu: ppmu_cpu@106c0000 { + ppmu_cpu: ppmu@106c0000 { compatible = "samsung,exynos-ppmu"; reg = <0x106c0000 0x2000>; clocks = <&clock CLK_PPMUCPU>; @@ -806,7 +806,7 @@ status = "disabled"; }; - ppmu_rightbus: ppmu_rightbus@112a0000 { + ppmu_rightbus: ppmu@112a0000 { compatible = "samsung,exynos-ppmu"; reg = <0x112a0000 0x2000>; clocks = <&clock CLK_PPMURIGHT>; @@ -814,7 +814,7 @@ status = "disabled"; }; - ppmu_leftbus: ppmu_leftbus0@116a0000 { + ppmu_leftbus: ppmu@116a0000 { compatible = "samsung,exynos-ppmu"; reg = <0x116a0000 0x2000>; clocks = <&clock CLK_PPMULEFT>; @@ -822,7 +822,7 @@ status = "disabled"; }; - ppmu_camif: ppmu_camif@11ac0000 { + ppmu_camif: ppmu@11ac0000 { compatible = "samsung,exynos-ppmu"; reg = <0x11ac0000 0x2000>; clocks = <&clock CLK_PPMUCAMIF>; @@ -830,7 +830,7 @@ status = "disabled"; }; - ppmu_lcd0: ppmu_lcd0@11e40000 { + ppmu_lcd0: ppmu@11e40000 { compatible = "samsung,exynos-ppmu"; reg = <0x11e40000 0x2000>; clocks = <&clock CLK_PPMULCD0>; @@ -838,13 +838,13 @@ status = "disabled"; }; - ppmu_fsys: ppmu_g3d@12630000 { + ppmu_fsys: ppmu@12630000 { compatible = "samsung,exynos-ppmu"; reg = <0x12630000 0x2000>; status = "disabled"; }; - ppmu_image: ppmu_image@12aa0000 { + ppmu_image: ppmu@12aa0000 { compatible = "samsung,exynos-ppmu"; reg = <0x12aa0000 0x2000>; clocks = <&clock CLK_PPMUIMAGE>; @@ -852,7 +852,7 @@ status = "disabled"; }; - ppmu_tv: ppmu_tv@12e40000 { + ppmu_tv: ppmu@12e40000 { compatible = "samsung,exynos-ppmu"; reg = <0x12e40000 0x2000>; clocks = <&clock CLK_PPMUTV>; @@ -860,7 +860,7 @@ status = "disabled"; }; - ppmu_g3d: ppmu_g3d@13220000 { + ppmu_g3d: ppmu@13220000 { compatible = "samsung,exynos-ppmu"; reg = <0x13220000 0x2000>; clocks = <&clock CLK_PPMUG3D>; @@ -868,7 +868,7 @@ status = "disabled"; }; - ppmu_mfc_left: ppmu_mfc_left@13660000 { + ppmu_mfc_left: ppmu@13660000 { compatible = "samsung,exynos-ppmu"; reg = <0x13660000 0x2000>; clocks = <&clock CLK_PPMUMFC_L>; @@ -876,7 +876,7 @@ status = "disabled"; }; - ppmu_mfc_right: ppmu_mfc_right@13670000 { + ppmu_mfc_right: ppmu@13670000 { compatible = "samsung,exynos-ppmu"; reg = <0x13670000 0x2000>; clocks = <&clock CLK_PPMUMFC_R>; diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi index fddc661ded28..70baad9b11f0 100644 --- a/arch/arm/boot/dts/exynos4210.dtsi +++ b/arch/arm/boot/dts/exynos4210.dtsi @@ -168,13 +168,13 @@ iommus = <&sysmmu_g2d>; }; - ppmu_acp: ppmu_acp@10ae0000 { + ppmu_acp: ppmu@10ae0000 { compatible = "samsung,exynos-ppmu"; reg = <0x10ae0000 0x2000>; status = "disabled"; }; - ppmu_lcd1: ppmu_lcd1@12240000 { + ppmu_lcd1: ppmu@12240000 { compatible = "samsung,exynos-ppmu"; reg = <0x12240000 0x2000>; clocks = <&clock CLK_PPMULCD1>; @@ -204,7 +204,7 @@ #iommu-cells = <0>; }; - bus_dmc: bus_dmc { + bus_dmc: bus-dmc { compatible = "samsung,exynos-bus"; clocks = <&clock CLK_DIV_DMC>; clock-names = "bus"; @@ -212,7 +212,7 @@ status = "disabled"; }; - bus_acp: bus_acp { + bus_acp: bus-acp { compatible = "samsung,exynos-bus"; clocks = <&clock CLK_DIV_ACP>; clock-names = "bus"; @@ -220,7 +220,7 @@ status = "disabled"; }; - bus_peri: bus_peri { + bus_peri: bus-peri { compatible = "samsung,exynos-bus"; clocks = <&clock CLK_ACLK100>; clock-names = "bus"; @@ -228,7 +228,7 @@ status = "disabled"; }; - bus_fsys: bus_fsys { + bus_fsys: bus-fsys { compatible = "samsung,exynos-bus"; clocks = <&clock CLK_ACLK133>; clock-names = "bus"; @@ -236,7 +236,7 @@ status = "disabled"; }; - bus_display: bus_display { + bus_display: bus-display { compatible = "samsung,exynos-bus"; clocks = <&clock CLK_ACLK160>; clock-names = "bus"; @@ -244,7 +244,7 @@ status = "disabled"; }; - bus_lcd0: bus_lcd0 { + bus_lcd0: bus-lcd0 { compatible = "samsung,exynos-bus"; clocks = <&clock CLK_ACLK200>; clock-names = "bus"; @@ -252,7 +252,7 @@ status = "disabled"; }; - bus_leftbus: bus_leftbus { + bus_leftbus: bus-leftbus { compatible = "samsung,exynos-bus"; clocks = <&clock CLK_DIV_GDL>; clock-names = "bus"; @@ -260,7 +260,7 @@ status = "disabled"; }; - bus_rightbus: bus_rightbus { + bus_rightbus: bus-rightbus { compatible = "samsung,exynos-bus"; clocks = <&clock CLK_DIV_GDR>; clock-names = "bus"; @@ -268,7 +268,7 @@ status = "disabled"; }; - bus_mfc: bus_mfc { + bus_mfc: bus-mfc { compatible = "samsung,exynos-bus"; clocks = <&clock CLK_SCLK_MFC>; clock-names = "bus"; @@ -276,7 +276,7 @@ status = "disabled"; }; - bus_dmc_opp_table: opp_table1 { + bus_dmc_opp_table: opp-table1 { compatible = "operating-points-v2"; opp-shared; @@ -295,7 +295,7 @@ }; }; - bus_acp_opp_table: opp_table2 { + bus_acp_opp_table: opp-table2 { compatible = "operating-points-v2"; opp-shared; @@ -310,7 +310,7 @@ }; }; - bus_peri_opp_table: opp_table3 { + bus_peri_opp_table: opp-table3 { compatible = "operating-points-v2"; opp-shared; @@ -322,7 +322,7 @@ }; }; - bus_fsys_opp_table: opp_table4 { + bus_fsys_opp_table: opp-table4 { compatible = "operating-points-v2"; opp-shared; @@ -334,7 +334,7 @@ }; }; - bus_display_opp_table: opp_table5 { + bus_display_opp_table: opp-table5 { compatible = "operating-points-v2"; opp-shared; @@ -349,7 +349,7 @@ }; }; - bus_leftbus_opp_table: opp_table6 { + bus_leftbus_opp_table: opp-table6 { compatible = "operating-points-v2"; opp-shared; @@ -463,7 +463,7 @@ "ppmmu3"; operating-points-v2 = <&gpu_opp_table>; - gpu_opp_table: opp_table { + gpu_opp_table: opp-table { compatible = "operating-points-v2"; opp-160000000 { diff --git a/arch/arm/boot/dts/exynos4412.dtsi b/arch/arm/boot/dts/exynos4412.dtsi index bcb87c5dca88..96a4b01bd71b 100644 --- a/arch/arm/boot/dts/exynos4412.dtsi +++ b/arch/arm/boot/dts/exynos4412.dtsi @@ -378,7 +378,7 @@ #iommu-cells = <0>; }; - bus_dmc: bus_dmc { + bus_dmc: bus-dmc { compatible = "samsung,exynos-bus"; clocks = <&clock CLK_DIV_DMC>; clock-names = "bus"; @@ -388,7 +388,7 @@ status = "disabled"; }; - bus_acp: bus_acp { + bus_acp: bus-acp { compatible = "samsung,exynos-bus"; clocks = <&clock CLK_DIV_ACP>; clock-names = "bus"; @@ -396,7 +396,7 @@ status = "disabled"; }; - bus_c2c: bus_c2c { + bus_c2c: bus-c2c { compatible = "samsung,exynos-bus"; clocks = <&clock CLK_DIV_C2C>; clock-names = "bus"; @@ -447,7 +447,7 @@ }; }; - bus_leftbus: bus_leftbus { + bus_leftbus: bus-leftbus { compatible = "samsung,exynos-bus"; clocks = <&clock CLK_DIV_GDL>; clock-names = "bus"; @@ -457,7 +457,7 @@ status = "disabled"; }; - bus_rightbus: bus_rightbus { + bus_rightbus: bus-rightbus { compatible = "samsung,exynos-bus"; clocks = <&clock CLK_DIV_GDR>; clock-names = "bus"; @@ -465,7 +465,7 @@ status = "disabled"; }; - bus_display: bus_display { + bus_display: bus-display { compatible = "samsung,exynos-bus"; clocks = <&clock CLK_ACLK160>; clock-names = "bus"; @@ -475,7 +475,7 @@ status = "disabled"; }; - bus_fsys: bus_fsys { + bus_fsys: bus-fsys { compatible = "samsung,exynos-bus"; clocks = <&clock CLK_ACLK133>; clock-names = "bus"; @@ -483,7 +483,7 @@ status = "disabled"; }; - bus_peri: bus_peri { + bus_peri: bus-peri { compatible = "samsung,exynos-bus"; clocks = <&clock CLK_ACLK100>; clock-names = "bus"; @@ -491,7 +491,7 @@ status = "disabled"; }; - bus_mfc: bus_mfc { + bus_mfc: bus-mfc { compatible = "samsung,exynos-bus"; clocks = <&clock CLK_SCLK_MFC>; clock-names = "bus"; -- cgit v1.2.3-59-g8ed1b From 32f9abc326ee21d8fe01c9979d493c7a92dedd59 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 5 Nov 2020 19:45:03 +0100 Subject: ARM: dts: exynos: use generic name for max77693 motor in Midas Use a generic name for the max77693 motor driver in Exynos4412 Midas boards to align with Devicetree specification naming convention. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20201105184506.215648-3-krzk@kernel.org --- arch/arm/boot/dts/exynos4412-midas.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/exynos4412-midas.dtsi b/arch/arm/boot/dts/exynos4412-midas.dtsi index 2be1db0b2387..111c32bae02c 100644 --- a/arch/arm/boot/dts/exynos4412-midas.dtsi +++ b/arch/arm/boot/dts/exynos4412-midas.dtsi @@ -192,7 +192,7 @@ }; }; - max77693_haptic { + motor-driver { compatible = "maxim,max77693-haptic"; haptic-supply = <&ldo26_reg>; pwms = <&pwm 0 38022 0>; -- cgit v1.2.3-59-g8ed1b From 9b846ba7c1d237476267bc2e05d4920691651ca2 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 5 Nov 2020 19:45:04 +0100 Subject: ARM: dts: exynos: use hyphens in Exynos5 node names Use hyphens instead of underscores in the Exynos5250 and Exynos542x node names which is expected by naming convention, multiple dtschema files and pointed out by dtc W=2 builds. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20201105184506.215648-4-krzk@kernel.org --- arch/arm/boot/dts/exynos5250.dtsi | 2 +- arch/arm/boot/dts/exynos5420.dtsi | 36 +++++++++++++-------------- arch/arm/boot/dts/exynos5422-odroid-core.dtsi | 32 ++++++++++++------------ 3 files changed, 35 insertions(+), 35 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi index 84677332a5a2..1be1841c374f 100644 --- a/arch/arm/boot/dts/exynos5250.dtsi +++ b/arch/arm/boot/dts/exynos5250.dtsi @@ -70,7 +70,7 @@ }; }; - cpu0_opp_table: opp_table0 { + cpu0_opp_table: opp-table0 { compatible = "operating-points-v2"; opp-shared; diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index 23a8fd5c8a6e..e23e8ffb093f 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -42,7 +42,7 @@ * by exynos5420-cpus.dtsi or exynos5422-cpus.dtsi. */ - cluster_a15_opp_table: opp_table0 { + cluster_a15_opp_table: opp-table0 { compatible = "operating-points-v2"; opp-shared; @@ -108,7 +108,7 @@ }; }; - cluster_a7_opp_table: opp_table1 { + cluster_a7_opp_table: opp-table1 { compatible = "operating-points-v2"; opp-shared; @@ -1077,112 +1077,112 @@ #iommu-cells = <0>; }; - bus_wcore: bus_wcore { + bus_wcore: bus-wcore { compatible = "samsung,exynos-bus"; clocks = <&clock CLK_DOUT_ACLK400_WCORE>; clock-names = "bus"; status = "disabled"; }; - bus_noc: bus_noc { + bus_noc: bus-noc { compatible = "samsung,exynos-bus"; clocks = <&clock CLK_DOUT_ACLK100_NOC>; clock-names = "bus"; status = "disabled"; }; - bus_fsys_apb: bus_fsys_apb { + bus_fsys_apb: bus-fsys-apb { compatible = "samsung,exynos-bus"; clocks = <&clock CLK_DOUT_PCLK200_FSYS>; clock-names = "bus"; status = "disabled"; }; - bus_fsys: bus_fsys { + bus_fsys: bus-fsys { compatible = "samsung,exynos-bus"; clocks = <&clock CLK_DOUT_ACLK200_FSYS>; clock-names = "bus"; status = "disabled"; }; - bus_fsys2: bus_fsys2 { + bus_fsys2: bus-fsys2 { compatible = "samsung,exynos-bus"; clocks = <&clock CLK_DOUT_ACLK200_FSYS2>; clock-names = "bus"; status = "disabled"; }; - bus_mfc: bus_mfc { + bus_mfc: bus-mfc { compatible = "samsung,exynos-bus"; clocks = <&clock CLK_DOUT_ACLK333>; clock-names = "bus"; status = "disabled"; }; - bus_gen: bus_gen { + bus_gen: bus-gen { compatible = "samsung,exynos-bus"; clocks = <&clock CLK_DOUT_ACLK266>; clock-names = "bus"; status = "disabled"; }; - bus_peri: bus_peri { + bus_peri: bus-peri { compatible = "samsung,exynos-bus"; clocks = <&clock CLK_DOUT_ACLK66>; clock-names = "bus"; status = "disabled"; }; - bus_g2d: bus_g2d { + bus_g2d: bus-g2d { compatible = "samsung,exynos-bus"; clocks = <&clock CLK_DOUT_ACLK333_G2D>; clock-names = "bus"; status = "disabled"; }; - bus_g2d_acp: bus_g2d_acp { + bus_g2d_acp: bus-g2d-acp { compatible = "samsung,exynos-bus"; clocks = <&clock CLK_DOUT_ACLK266_G2D>; clock-names = "bus"; status = "disabled"; }; - bus_jpeg: bus_jpeg { + bus_jpeg: bus-jpeg { compatible = "samsung,exynos-bus"; clocks = <&clock CLK_DOUT_ACLK300_JPEG>; clock-names = "bus"; status = "disabled"; }; - bus_jpeg_apb: bus_jpeg_apb { + bus_jpeg_apb: bus-jpeg-apb { compatible = "samsung,exynos-bus"; clocks = <&clock CLK_DOUT_ACLK166>; clock-names = "bus"; status = "disabled"; }; - bus_disp1_fimd: bus_disp1_fimd { + bus_disp1_fimd: bus-disp1-fimd { compatible = "samsung,exynos-bus"; clocks = <&clock CLK_DOUT_ACLK300_DISP1>; clock-names = "bus"; status = "disabled"; }; - bus_disp1: bus_disp1 { + bus_disp1: bus-disp1 { compatible = "samsung,exynos-bus"; clocks = <&clock CLK_DOUT_ACLK400_DISP1>; clock-names = "bus"; status = "disabled"; }; - bus_gscl_scaler: bus_gscl_scaler { + bus_gscl_scaler: bus-gscl-scaler { compatible = "samsung,exynos-bus"; clocks = <&clock CLK_DOUT_ACLK300_GSCL>; clock-names = "bus"; status = "disabled"; }; - bus_mscl: bus_mscl { + bus_mscl: bus-mscl { compatible = "samsung,exynos-bus"; clocks = <&clock CLK_DOUT_ACLK400_MSCL>; clock-names = "bus"; diff --git a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi index 25fb6331c75e..d0df560eb0db 100644 --- a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi +++ b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi @@ -35,7 +35,7 @@ }; }; - bus_wcore_opp_table: opp_table2 { + bus_wcore_opp_table: opp-table2 { compatible = "operating-points-v2"; /* derived from 532MHz MPLL */ @@ -61,7 +61,7 @@ }; }; - bus_noc_opp_table: opp_table3 { + bus_noc_opp_table: opp-table3 { compatible = "operating-points-v2"; /* derived from 666MHz CPLL */ @@ -79,7 +79,7 @@ }; }; - bus_fsys_apb_opp_table: opp_table4 { + bus_fsys_apb_opp_table: opp-table4 { compatible = "operating-points-v2"; /* derived from 666MHz CPLL */ @@ -91,7 +91,7 @@ }; }; - bus_fsys2_opp_table: opp_table5 { + bus_fsys2_opp_table: opp-table5 { compatible = "operating-points-v2"; /* derived from 600MHz DPLL */ @@ -106,7 +106,7 @@ }; }; - bus_mfc_opp_table: opp_table6 { + bus_mfc_opp_table: opp-table6 { compatible = "operating-points-v2"; /* derived from 666MHz CPLL */ @@ -127,7 +127,7 @@ }; }; - bus_gen_opp_table: opp_table7 { + bus_gen_opp_table: opp-table7 { compatible = "operating-points-v2"; /* derived from 532MHz MPLL */ @@ -145,7 +145,7 @@ }; }; - bus_peri_opp_table: opp_table8 { + bus_peri_opp_table: opp-table8 { compatible = "operating-points-v2"; /* derived from 666MHz CPLL */ @@ -154,7 +154,7 @@ }; }; - bus_g2d_opp_table: opp_table9 { + bus_g2d_opp_table: opp-table9 { compatible = "operating-points-v2"; /* derived from 666MHz CPLL */ @@ -175,7 +175,7 @@ }; }; - bus_g2d_acp_opp_table: opp_table10 { + bus_g2d_acp_opp_table: opp-table10 { compatible = "operating-points-v2"; /* derived from 532MHz MPLL */ @@ -193,7 +193,7 @@ }; }; - bus_jpeg_opp_table: opp_table11 { + bus_jpeg_opp_table: opp-table11 { compatible = "operating-points-v2"; /* derived from 600MHz DPLL */ @@ -211,7 +211,7 @@ }; }; - bus_jpeg_apb_opp_table: opp_table12 { + bus_jpeg_apb_opp_table: opp-table12 { compatible = "operating-points-v2"; /* derived from 666MHz CPLL */ @@ -229,7 +229,7 @@ }; }; - bus_disp1_fimd_opp_table: opp_table13 { + bus_disp1_fimd_opp_table: opp-table13 { compatible = "operating-points-v2"; /* derived from 600MHz DPLL */ @@ -241,7 +241,7 @@ }; }; - bus_disp1_opp_table: opp_table14 { + bus_disp1_opp_table: opp-table14 { compatible = "operating-points-v2"; /* derived from 600MHz DPLL */ @@ -256,7 +256,7 @@ }; }; - bus_gscl_opp_table: opp_table15 { + bus_gscl_opp_table: opp-table15 { compatible = "operating-points-v2"; /* derived from 600MHz DPLL */ @@ -271,7 +271,7 @@ }; }; - bus_mscl_opp_table: opp_table16 { + bus_mscl_opp_table: opp-table16 { compatible = "operating-points-v2"; /* derived from 666MHz CPLL */ @@ -292,7 +292,7 @@ }; }; - dmc_opp_table: opp_table17 { + dmc_opp_table: opp-table17 { compatible = "operating-points-v2"; opp00 { -- cgit v1.2.3-59-g8ed1b From 73f882a0f3a833d589c1a0b6b83045567244e71e Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 5 Nov 2020 19:45:05 +0100 Subject: ARM: dts: exynos: use hyphens in MFC reserved memory node names Use hyphens instead of underscores in the MFC reserved memory node names which is expected by naming convention, multiple dtschema files and pointed out by dtc W=2 builds. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20201105184506.215648-5-krzk@kernel.org --- arch/arm/boot/dts/exynos-mfc-reserved-memory.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/exynos-mfc-reserved-memory.dtsi b/arch/arm/boot/dts/exynos-mfc-reserved-memory.dtsi index 1dbf3bbff8d3..597ade3e252f 100644 --- a/arch/arm/boot/dts/exynos-mfc-reserved-memory.dtsi +++ b/arch/arm/boot/dts/exynos-mfc-reserved-memory.dtsi @@ -11,14 +11,14 @@ #size-cells = <1>; ranges; - mfc_left: region_mfc_left { + mfc_left: region-mfc-left { compatible = "shared-dma-pool"; no-map; size = <0x2400000>; alignment = <0x100000>; }; - mfc_right: region_mfc_right { + mfc_right: region-mfc-right { compatible = "shared-dma-pool"; no-map; size = <0x800000>; -- cgit v1.2.3-59-g8ed1b From e77ce5ec8b9d63bd980ca8a2ab9c28222cacb3ba Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Wed, 11 Nov 2020 01:25:13 +0100 Subject: ARM: dts: ux500: skomer: Pull down SDI2 FBCLK The feedback clock on SDI2 needs to be pulled down on this machine. Link: https://lore.kernel.org/r/20201111002513.2271351-1-linus.walleij@linaro.org Signed-off-by: Linus Walleij --- arch/arm/boot/dts/ste-ux500-samsung-skomer.dts | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/ste-ux500-samsung-skomer.dts b/arch/arm/boot/dts/ste-ux500-samsung-skomer.dts index cbae23a1e8b6..b50634c81b44 100644 --- a/arch/arm/boot/dts/ste-ux500-samsung-skomer.dts +++ b/arch/arm/boot/dts/ste-ux500-samsung-skomer.dts @@ -433,6 +433,16 @@ }; }; + /* The unused FBCLK needs to be pulled down on this machine */ + sdi2 { + mc2_a_1_default { + default_cfg2 { + pins = "GPIO130_C8"; /* FBCLK */ + ste,config = <&in_pd>; + }; + }; + }; + mcde { dsi_default_mode: dsi_default { default_mux1 { -- cgit v1.2.3-59-g8ed1b From c74da5cf007c49873a502eb7f4554fefb23f3f33 Mon Sep 17 00:00:00 2001 From: Konstantin Aladyshev Date: Wed, 11 Nov 2020 16:21:33 +0300 Subject: ARM: dts: aspeed: amd-ethanolx: Add GPIO line names Add GPIO line names for AMD EthanolX customer reference board. It populates AST2500 GPIO lines (A0-A7 to AC0-AC7) with AMD EthanolX designated names. Signed-off-by: Konstantin Aladyshev Reviewed-by: Supreeth Venkatesh Link: https://lore.kernel.org/r/20201111132133.1253-1-aladyshev22@gmail.com Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-amd-ethanolx.dts | 44 +++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/aspeed-bmc-amd-ethanolx.dts b/arch/arm/boot/dts/aspeed-bmc-amd-ethanolx.dts index b93ed44eba0c..96ff0aea64e5 100644 --- a/arch/arm/boot/dts/aspeed-bmc-amd-ethanolx.dts +++ b/arch/arm/boot/dts/aspeed-bmc-amd-ethanolx.dts @@ -97,6 +97,50 @@ &pinctrl_adc4_default>; }; +&gpio { + status = "okay"; + gpio-line-names = + /*A0-A7*/ "","","FAULT_LED","CHASSIS_ID_LED","","","","", + /*B0-B7*/ "","","","","","","","", + /*C0-C7*/ "CHASSIS_ID_BTN","INTRUDER","AC_LOSS","","","","","", + /*D0-D7*/ "HDT_DBREQ","LOCAL_SPI_ROM_SEL","FPGA_SPI_ROM_SEL","JTAG_MUX_S", + "JTAG_MUX_OE","HDT_SEL","ASERT_WARM_RST_BTN","FPGA_RSVD", + /*E0-E7*/ "","","MON_P0_PWR_BTN","MON_P0_RST_BTN","MON_P0_NMI_BTN", + "MON_P0_PWR_GOOD","MON_PWROK","MON_RESET", + /*F0-F7*/ "MON_P0_PROCHOT","MON_P1_PROCHOT","MON_P0_THERMTRIP", + "MON_P1_THERMTRIP","P0_PRESENT","P1_PRESENT","MON_ATX_PWR_OK","", + /*G0-G7*/ "BRD_REV_ID_3","BRD_REV_ID_2","BRD_REV_ID_1","BRD_REV_ID_0", + "P0_APML_ALERT","P1_APML_ALERT","FPGA ALERT","", + /*H0-H7*/ "BRD_ID_0","BRD_ID_1","BRD_ID_2","BRD_ID_3", + "PCIE_DISCONNECTED","USB_DISCONNECTED","SPARE_0","SPARE_1", + /*I0-I7*/ "","","","","","","","", + /*J0-J7*/ "","","","","","","","", + /*K0-K7*/ "","","","","","","","", + /*L0-L7*/ "","","","","","","","", + /*M0-M7*/ "ASSERT_PWR_BTN","ASSERT_RST_BTN","ASSERT_NMI_BTN", + "ASSERT_LOCAL_LOCK","ASSERT_P0_PROCHOT","ASSERT_P1_PROCHOT", + "ASSERT_CLR_CMOS","ASSERT_BMC_READY", + /*N0-N7*/ "","","","","","","","", + /*O0-O7*/ "","","","","","","","", + /*P0-P7*/ "P0_VDD_CORE_RUN_VRHOT","P0_VDD_SOC_RUN_VRHOT", + "P0_VDD_MEM_ABCD_SUS_VRHOT","P0_VDD_MEM_EFGH_SUS_VRHOT", + "P1_VDD_CORE_RUN_VRHOT","P1_VDD_SOC_RUN_VRHOT", + "P1_VDD_MEM_ABCD_SUS_VRHOT","P1_VDD_MEM_EFGH_SUS_VRHOT", + /*Q0-Q7*/ "","","","","","","","", + /*R0-R7*/ "","","","","","","","", + /*S0-S7*/ "","","","","","","","", + /*T0-T7*/ "","","","","","","","", + /*U0-U7*/ "","","","","","","","", + /*V0-V7*/ "","","","","","","","", + /*W0-W7*/ "","","","","","","","", + /*X0-X7*/ "","","","","","","","", + /*Y0-Y7*/ "","","","","","","","", + /*Z0-Z7*/ "","","","","","","","", + /*AA0-AA7*/ "","SENSOR THERM","","","","","","", + /*AB0-AB7*/ "","","","","","","","", + /*AC0-AC7*/ "","","","","","","",""; +}; + //APML for P0 &i2c0 { status = "okay"; -- cgit v1.2.3-59-g8ed1b From 1ca5f2430c4f9d85b98b8d6e5d93f8d4802faf8e Mon Sep 17 00:00:00 2001 From: Vivek Unune Date: Wed, 14 Oct 2020 15:27:27 -0400 Subject: ARM: dts: BCM5301X: Linksys EA9500 add port 5 and port 7 Add ports 5 and 7 which are connected to gmac cores 1 & 2. These will be disabled for now. Signed-off-by: Vivek Unune Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm47094-linksys-panamera.dts | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/bcm47094-linksys-panamera.dts b/arch/arm/boot/dts/bcm47094-linksys-panamera.dts index 0faae8950375..5d5930edfb9d 100644 --- a/arch/arm/boot/dts/bcm47094-linksys-panamera.dts +++ b/arch/arm/boot/dts/bcm47094-linksys-panamera.dts @@ -242,6 +242,30 @@ label = "wan"; }; + port@5 { + reg = <5>; + ethernet = <&gmac0>; + label = "cpu"; + status = "disabled"; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + port@7 { + reg = <7>; + ethernet = <&gmac1>; + label = "cpu"; + status = "disabled"; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + port@8 { reg = <8>; ethernet = <&gmac2>; -- cgit v1.2.3-59-g8ed1b From 74abbfe99f43eb7466d26d9e48fbeb46b8f3d804 Mon Sep 17 00:00:00 2001 From: Serge Semin Date: Tue, 20 Oct 2020 14:59:37 +0300 Subject: ARM: dts: BCM5301X: Harmonize EHCI/OHCI DT nodes name In accordance with the Generic EHCI/OHCI bindings the corresponding node name is suppose to comply with the Generic USB HCD DT schema, which requires the USB nodes to have the name acceptable by the regexp: "^usb(@.*)?" . Make sure the "generic-ehci" and "generic-ohci"-compatible nodes are correctly named. Signed-off-by: Serge Semin Acked-by: Florian Fainelli Acked-by: Krzysztof Kozlowski Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm5301x.dtsi | 4 ++-- arch/arm/boot/dts/bcm53573.dtsi | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/bcm5301x.dtsi b/arch/arm/boot/dts/bcm5301x.dtsi index ac3a99cf2079..3ec6673f6c1e 100644 --- a/arch/arm/boot/dts/bcm5301x.dtsi +++ b/arch/arm/boot/dts/bcm5301x.dtsi @@ -265,7 +265,7 @@ interrupt-parent = <&gic>; - ehci: ehci@21000 { + ehci: usb@21000 { #usb-cells = <0>; compatible = "generic-ehci"; @@ -287,7 +287,7 @@ }; }; - ohci: ohci@22000 { + ohci: usb@22000 { #usb-cells = <0>; compatible = "generic-ohci"; diff --git a/arch/arm/boot/dts/bcm53573.dtsi b/arch/arm/boot/dts/bcm53573.dtsi index 4af8e3293cff..51546fccc616 100644 --- a/arch/arm/boot/dts/bcm53573.dtsi +++ b/arch/arm/boot/dts/bcm53573.dtsi @@ -135,7 +135,7 @@ #address-cells = <1>; #size-cells = <1>; - ehci: ehci@4000 { + ehci: usb@4000 { compatible = "generic-ehci"; reg = <0x4000 0x1000>; interrupt-parent = <&gic>; @@ -155,7 +155,7 @@ }; }; - ohci: ohci@d000 { + ohci: usb@d000 { #usb-cells = <0>; compatible = "generic-ohci"; -- cgit v1.2.3-59-g8ed1b From 4b650a20bdb5f9558007dd3055a17a1644a91c3e Mon Sep 17 00:00:00 2001 From: Serge Semin Date: Tue, 20 Oct 2020 14:59:46 +0300 Subject: ARM: dts: BCM5310X: Harmonize xHCI DT nodes name In accordance with the Generic xHCI bindings the corresponding node name is suppose to comply with the Generic USB HCD DT schema, which requires the USB nodes to have the name acceptable by the regexp: "^usb(@.*)?" . Make sure the "generic-xhci"-compatible nodes are correctly named. Signed-off-by: Serge Semin Acked-by: Krzysztof Kozlowski Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm5301x.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/bcm5301x.dtsi b/arch/arm/boot/dts/bcm5301x.dtsi index 3ec6673f6c1e..fcfaad4ffcb3 100644 --- a/arch/arm/boot/dts/bcm5301x.dtsi +++ b/arch/arm/boot/dts/bcm5301x.dtsi @@ -318,7 +318,7 @@ interrupt-parent = <&gic>; - xhci: xhci@23000 { + xhci: usb@23000 { #usb-cells = <0>; compatible = "generic-xhci"; -- cgit v1.2.3-59-g8ed1b From bd9a01e28e5d1632528e531480b42d6e2c861d88 Mon Sep 17 00:00:00 2001 From: Vivek Unune Date: Sun, 1 Nov 2020 15:08:03 -0500 Subject: ARM: dts: BCM5301X: Linksys EA9500 add fixed partitions This router has dual paritions to store trx firmware image and dual partitions for nvram. The second one in each of these cases acts as a backup store. When tested with OpenWrt, the default partition parser causes two issues: 1. It labels both nvram partitions as nvram. In factory, second one is labeled devinfo. 2. It parses second trx image and tries to create second 'linux' partition and fails with - cannot create duplicate 'linux' partition The following patch works around both of these issues. Signed-off-by: Vivek Unune Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm47094-linksys-panamera.dts | 41 +++++++++++++++++++++++++ 1 file changed, 41 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/bcm47094-linksys-panamera.dts b/arch/arm/boot/dts/bcm47094-linksys-panamera.dts index 5d5930edfb9d..507af23e227f 100644 --- a/arch/arm/boot/dts/bcm47094-linksys-panamera.dts +++ b/arch/arm/boot/dts/bcm47094-linksys-panamera.dts @@ -292,3 +292,44 @@ &usb3_phy { status = "okay"; }; + +&nandcs { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "boot"; + reg = <0x0000000 0x0080000>; + read-only; + }; + + partition@80000 { + label = "nvram"; + reg = <0x080000 0x0100000>; + }; + + partition@180000{ + label = "devinfo"; + reg = <0x0180000 0x080000>; + }; + + partition@200000 { + label = "firmware"; + reg = <0x0200000 0x01D00000>; + compatible = "brcm,trx"; + }; + + partition@1F00000 { + label = "failsafe"; + reg = <0x01F00000 0x01D00000>; + read-only; + }; + + partition@5200000 { + label = "system"; + reg = <0x05200000 0x02E00000>; + }; + }; +}; -- cgit v1.2.3-59-g8ed1b From 2f34ae32f5e74096540cd7ce95bfd467cb74b21a Mon Sep 17 00:00:00 2001 From: Vivek Unune Date: Wed, 4 Nov 2020 15:29:51 -0500 Subject: ARM: dts: BCM5301X: Use corretc pinctrl compatible for 4709x MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit BCM47094 version of pinmux uses different compatible and supports MDIO pinmux pins. Hence, use the correct compatible string and defines the MDIO pins group. Signed-off-by: Vivek Unune Acked-by: Rafał Miłecki Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm47094.dtsi | 9 +++++++++ arch/arm/boot/dts/bcm5301x.dtsi | 2 +- 2 files changed, 10 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/bcm47094.dtsi b/arch/arm/boot/dts/bcm47094.dtsi index cdc5ff593adb..747ca030435f 100644 --- a/arch/arm/boot/dts/bcm47094.dtsi +++ b/arch/arm/boot/dts/bcm47094.dtsi @@ -8,6 +8,15 @@ / { }; +&pinctrl { + compatible = "brcm,bcm4709-pinmux"; + + pinmux_mdio: mdio { + groups = "mdio_grp"; + function = "mdio"; + }; +}; + &usb3_phy { compatible = "brcm,ns-bx-usb3-phy"; }; diff --git a/arch/arm/boot/dts/bcm5301x.dtsi b/arch/arm/boot/dts/bcm5301x.dtsi index fcfaad4ffcb3..bcb32fc698ab 100644 --- a/arch/arm/boot/dts/bcm5301x.dtsi +++ b/arch/arm/boot/dts/bcm5301x.dtsi @@ -428,7 +428,7 @@ #address-cells = <1>; #size-cells = <1>; - pin-controller@1c0 { + pinctrl: pin-controller@1c0 { compatible = "brcm,bcm4708-pinmux"; reg = <0x1c0 0x24>; reg-names = "cru_gpio_control"; -- cgit v1.2.3-59-g8ed1b From c862059875cffc013ee27bf9759ac288224e7a14 Mon Sep 17 00:00:00 2001 From: Vivek Unune Date: Wed, 4 Nov 2020 15:29:52 -0500 Subject: ARM: dts: BCM5301X: Linksys EA9500 make use of pinctrl Now that we have a pin controller, use that instead of manuplating the mdio/mdc pins directly. i.e. we no longer require the mdio-mii-mux Signed-off-by: Vivek Unune Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm47094-linksys-panamera.dts | 26 ++++--------------------- 1 file changed, 4 insertions(+), 22 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/bcm47094-linksys-panamera.dts b/arch/arm/boot/dts/bcm47094-linksys-panamera.dts index 507af23e227f..3bb3fe5bfbf8 100644 --- a/arch/arm/boot/dts/bcm47094-linksys-panamera.dts +++ b/arch/arm/boot/dts/bcm47094-linksys-panamera.dts @@ -123,33 +123,13 @@ }; }; - mdio-bus-mux { - #address-cells = <1>; - #size-cells = <0>; + mdio-bus-mux@18003000 { /* BIT(9) = 1 => external mdio */ - mdio_ext: mdio@200 { + mdio@200 { reg = <0x200>; #address-cells = <1>; #size-cells = <0>; - }; - }; - - mdio-mii-mux { - compatible = "mdio-mux-mmioreg"; - mdio-parent-bus = <&mdio_ext>; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x1800c1c0 0x4>; - - /* BIT(6) = mdc, BIT(7) = mdio */ - mux-mask = <0xc0>; - - mdio-mii@0 { - /* Enable MII function */ - reg = <0x0>; - #address-cells = <1>; - #size-cells = <0>; switch@0 { compatible = "brcm,bcm53125"; @@ -159,6 +139,8 @@ reset-names = "robo_reset"; reg = <0>; dsa,member = <1 0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinmux_mdio>; ports { #address-cells = <1>; -- cgit v1.2.3-59-g8ed1b From 776461b1795b4dc4084894cf53399044aafa1d21 Mon Sep 17 00:00:00 2001 From: Rafał Miłecki Date: Wed, 11 Nov 2020 15:55:38 +0100 Subject: ARM: dts: BCM5301X: Move CRU devices to the CRU node MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Clocks and thermal blocks are part of the CRU ("Clock and Reset Unit" or "Central Resource Unit"). Signed-off-by: Rafał Miłecki Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm5301x.dtsi | 51 +++++++++++++++++++++-------------------- 1 file changed, 26 insertions(+), 25 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/bcm5301x.dtsi b/arch/arm/boot/dts/bcm5301x.dtsi index bcb32fc698ab..90c09c48721b 100644 --- a/arch/arm/boot/dts/bcm5301x.dtsi +++ b/arch/arm/boot/dts/bcm5301x.dtsi @@ -428,6 +428,26 @@ #address-cells = <1>; #size-cells = <1>; + lcpll0: lcpll0@100 { + #clock-cells = <1>; + compatible = "brcm,nsp-lcpll0"; + reg = <0x100 0x14>; + clocks = <&osc>; + clock-output-names = "lcpll0", "pcie_phy", + "sdio", "ddr_phy"; + }; + + genpll: genpll@140 { + #clock-cells = <1>; + compatible = "brcm,nsp-genpll"; + reg = <0x140 0x24>; + clocks = <&osc>; + clock-output-names = "genpll", "phy", + "ethernetclk", + "usbclk", "iprocfast", + "sata1", "sata2"; + }; + pinctrl: pin-controller@1c0 { compatible = "brcm,bcm4708-pinmux"; reg = <0x1c0 0x24>; @@ -454,32 +474,13 @@ function = "uart1"; }; }; - }; - }; - - lcpll0: lcpll0@1800c100 { - #clock-cells = <1>; - compatible = "brcm,nsp-lcpll0"; - reg = <0x1800c100 0x14>; - clocks = <&osc>; - clock-output-names = "lcpll0", "pcie_phy", "sdio", - "ddr_phy"; - }; - genpll: genpll@1800c140 { - #clock-cells = <1>; - compatible = "brcm,nsp-genpll"; - reg = <0x1800c140 0x24>; - clocks = <&osc>; - clock-output-names = "genpll", "phy", "ethernetclk", - "usbclk", "iprocfast", "sata1", - "sata2"; - }; - - thermal: thermal@1800c2c0 { - compatible = "brcm,ns-thermal"; - reg = <0x1800c2c0 0x10>; - #thermal-sensor-cells = <0>; + thermal: thermal@2c0 { + compatible = "brcm,ns-thermal"; + reg = <0x2c0 0x10>; + #thermal-sensor-cells = <0>; + }; + }; }; srab: srab@18007000 { -- cgit v1.2.3-59-g8ed1b From 800b92ef92f3be6f635c31a411802afd29914dd8 Mon Sep 17 00:00:00 2001 From: Tao Ren Date: Wed, 11 Nov 2020 15:23:27 -0800 Subject: ARM: dts: aspeed: Common dtsi for Facebook AST2400 Network BMCs This common descirption is included by all Facebook AST2400 Network BMC platforms to minimize duplicated device entries across Facebook Network BMC device trees. Signed-off-by: Tao Ren Reviewed-by: Patrick Williams Reviewed-by: Joel Stanley Link: https://lore.kernel.org/r/20201111232330.30843-2-rentao.bupt@gmail.com Signed-off-by: Joel Stanley --- .../boot/dts/ast2400-facebook-netbmc-common.dtsi | 117 +++++++++++++++++++++ 1 file changed, 117 insertions(+) create mode 100644 arch/arm/boot/dts/ast2400-facebook-netbmc-common.dtsi (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/ast2400-facebook-netbmc-common.dtsi b/arch/arm/boot/dts/ast2400-facebook-netbmc-common.dtsi new file mode 100644 index 000000000000..73a5503be78c --- /dev/null +++ b/arch/arm/boot/dts/ast2400-facebook-netbmc-common.dtsi @@ -0,0 +1,117 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright (c) 2020 Facebook Inc. +/dts-v1/; + +#include "aspeed-g4.dtsi" + +/ { + aliases { + /* + * Override the default uart aliases to avoid breaking + * the legacy applications. + */ + serial0 = &uart5; + serial1 = &uart1; + serial2 = &uart3; + serial3 = &uart4; + }; + + memory@40000000 { + reg = <0x40000000 0x20000000>; + }; +}; + +&wdt1 { + status = "okay"; + aspeed,reset-type = "system"; +}; + +&fmc { + status = "okay"; + flash@0 { + status = "okay"; + m25p,fast-read; + label = "spi0.0"; +#include "facebook-bmc-flash-layout.dtsi" + }; +}; + +&uart1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd1_default + &pinctrl_rxd1_default>; +}; + +&uart3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd3_default + &pinctrl_rxd3_default>; +}; + +&uart4 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd4_default + &pinctrl_rxd4_default + &pinctrl_ndts4_default>; +}; + +&uart5 { + status = "okay"; +}; + +&mac1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>; +}; + +&i2c0 { + status = "okay"; +}; + +&i2c1 { + status = "okay"; +}; + +&i2c2 { + status = "okay"; +}; + +&i2c3 { + status = "okay"; +}; + +&i2c4 { + status = "okay"; +}; + +&i2c5 { + status = "okay"; +}; + +&i2c6 { + status = "okay"; +}; + +&i2c7 { + status = "okay"; +}; + +&i2c8 { + status = "okay"; +}; + +&i2c11 { + status = "okay"; +}; + +&i2c12 { + status = "okay"; +}; + +&vhub { + status = "okay"; +}; -- cgit v1.2.3-59-g8ed1b From e4c1633325fa4dca3b39c260881f9f6b55ca1031 Mon Sep 17 00:00:00 2001 From: Tao Ren Date: Wed, 11 Nov 2020 15:23:28 -0800 Subject: ARM: dts: aspeed: wedge40: Use common dtsi Simplify the Wedge40 device tree by using the common dtsi. Signed-off-by: Tao Ren Reviewed-by: Patrick Williams Reviewed-by: Joel Stanley Link: https://lore.kernel.org/r/20201111232330.30843-3-rentao.bupt@gmail.com Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-facebook-wedge40.dts | 112 +--------------------- 1 file changed, 1 insertion(+), 111 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-wedge40.dts b/arch/arm/boot/dts/aspeed-bmc-facebook-wedge40.dts index 8c426ba2f8ab..2dcfeae3c92a 100644 --- a/arch/arm/boot/dts/aspeed-bmc-facebook-wedge40.dts +++ b/arch/arm/boot/dts/aspeed-bmc-facebook-wedge40.dts @@ -2,137 +2,27 @@ // Copyright (c) 2018 Facebook Inc. /dts-v1/; -#include "aspeed-g4.dtsi" +#include "ast2400-facebook-netbmc-common.dtsi" / { model = "Facebook Wedge 40 BMC"; compatible = "facebook,wedge40-bmc", "aspeed,ast2400"; - aliases { - /* - * Override the default uart aliases to avoid breaking - * the legacy applications. - */ - serial0 = &uart5; - serial1 = &uart1; - serial2 = &uart3; - serial3 = &uart4; - }; - chosen { stdout-path = &uart3; bootargs = "console=ttyS2,9600n8 root=/dev/ram rw"; }; - memory@40000000 { - reg = <0x40000000 0x20000000>; - }; - ast-adc-hwmon { compatible = "iio-hwmon"; io-channels = <&adc 5>, <&adc 6>, <&adc 7>, <&adc 8>, <&adc 9>; }; }; -&wdt1 { - status = "okay"; - aspeed,reset-type = "system"; -}; - &wdt2 { status = "disabled"; }; -&fmc { - status = "okay"; - flash@0 { - status = "okay"; - m25p,fast-read; - label = "spi0.0"; -#include "facebook-bmc-flash-layout.dtsi" - }; -}; - -&uart1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_txd1_default - &pinctrl_rxd1_default>; -}; - -&uart3 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_txd3_default - &pinctrl_rxd3_default>; -}; - -&uart4 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_txd4_default - &pinctrl_rxd4_default - &pinctrl_ndts4_default>; -}; - -&uart5 { - status = "okay"; -}; - -&mac1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>; -}; - -&i2c0 { - status = "okay"; -}; - -&i2c1 { - status = "okay"; -}; - -&i2c2 { - status = "okay"; -}; - -&i2c3 { - status = "okay"; -}; - -&i2c4 { - status = "okay"; -}; - -&i2c5 { - status = "okay"; -}; - -&i2c6 { - status = "okay"; -}; - -&i2c7 { - status = "okay"; -}; - -&i2c8 { - status = "okay"; -}; - -&i2c11 { - status = "okay"; -}; - -&i2c12 { - status = "okay"; -}; - -&vhub { - status = "okay"; -}; - &adc { status = "okay"; }; -- cgit v1.2.3-59-g8ed1b From 41376fb94c6a825674de3de27c6ee3af17065834 Mon Sep 17 00:00:00 2001 From: Tao Ren Date: Wed, 11 Nov 2020 15:23:29 -0800 Subject: ARM: dts: aspeed: wedge100: Use common dtsi Simplify the Wedge100 device tree by using the common dtsi. In addition this enables the second firmware flash, and turns on the "i2c-mux-idle-disconnect" flag for I2C switch 7-0070. Signed-off-by: Tao Ren Reviewed-by: Patrick Williams Reviewed-by: Joel Stanley Link: https://lore.kernel.org/r/20201111232330.30843-4-rentao.bupt@gmail.com Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-facebook-wedge100.dts | 120 +++------------------ 1 file changed, 15 insertions(+), 105 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-wedge100.dts b/arch/arm/boot/dts/aspeed-bmc-facebook-wedge100.dts index 322587b7b67d..39c6be91d53f 100644 --- a/arch/arm/boot/dts/aspeed-bmc-facebook-wedge100.dts +++ b/arch/arm/boot/dts/aspeed-bmc-facebook-wedge100.dts @@ -2,36 +2,16 @@ // Copyright (c) 2018 Facebook Inc. /dts-v1/; -#include "aspeed-g4.dtsi" +#include "ast2400-facebook-netbmc-common.dtsi" / { model = "Facebook Wedge 100 BMC"; compatible = "facebook,wedge100-bmc", "aspeed,ast2400"; - aliases { - /* - * Override the default uart aliases to avoid breaking - * the legacy applications. - */ - serial0 = &uart5; - serial1 = &uart1; - serial2 = &uart3; - serial3 = &uart4; - }; - chosen { stdout-path = &uart3; bootargs = "console=ttyS2,9600n8 root=/dev/ram rw"; }; - - memory@40000000 { - reg = <0x40000000 0x20000000>; - }; -}; - -&wdt1 { - status = "okay"; - aspeed,reset-type = "system"; }; &wdt2 { @@ -40,108 +20,38 @@ }; &fmc { - status = "okay"; - flash@0 { + flash@1 { status = "okay"; m25p,fast-read; - label = "fmc0"; -#include "facebook-bmc-flash-layout.dtsi" + label = "spi0.1"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + flash1@0 { + reg = <0x0 0x2000000>; + label = "flash1"; + }; + }; }; }; -&uart1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_txd1_default - &pinctrl_rxd1_default>; -}; - -&uart3 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_txd3_default - &pinctrl_rxd3_default>; -}; - -&uart4 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_txd4_default - &pinctrl_rxd4_default>; -}; - -&uart5 { - status = "okay"; -}; - -&mac1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>; -}; - -&i2c0 { - status = "okay"; -}; - -&i2c1 { - status = "okay"; -}; - -&i2c2 { - status = "okay"; -}; - -&i2c3 { - status = "okay"; -}; - -&i2c4 { - status = "okay"; -}; - -&i2c5 { - status = "okay"; -}; - -&i2c6 { - status = "okay"; -}; - &i2c7 { - status = "okay"; - i2c-switch@70 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x70>; + i2c-mux-idle-disconnect; }; }; -&i2c8 { - status = "okay"; -}; - &i2c9 { status = "okay"; }; -&i2c10 { - status = "okay"; -}; - -&i2c11 { - status = "okay"; -}; - -&i2c12 { - status = "okay"; -}; - -&i2c13 { - status = "okay"; -}; &vhub { status = "okay"; -- cgit v1.2.3-59-g8ed1b From 71b802d2d518d2bdbdc0fa5b661fc1d37b9b50d3 Mon Sep 17 00:00:00 2001 From: Tao Ren Date: Wed, 11 Nov 2020 15:23:30 -0800 Subject: ARM: dts: aspeed: Add Facebook Galaxy100 (AST2400) BMC Add initial version of device tree for Facebook Galaxy100 (AST2400) BMC. Signed-off-by: Tao Ren Reviewed-by: Patrick Williams Reviewed-by: Joel Stanley Link: https://lore.kernel.org/r/20201111232330.30843-5-rentao.bupt@gmail.com Signed-off-by: Joel Stanley --- arch/arm/boot/dts/Makefile | 1 + .../arm/boot/dts/aspeed-bmc-facebook-galaxy100.dts | 57 ++++++++++++++++++++++ 2 files changed, 58 insertions(+) create mode 100644 arch/arm/boot/dts/aspeed-bmc-facebook-galaxy100.dts (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 21477ef5c5c9..1917cd47204a 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1383,6 +1383,7 @@ dtb-$(CONFIG_ARCH_ASPEED) += \ aspeed-bmc-arm-stardragon4800-rep2.dtb \ aspeed-bmc-bytedance-g220a.dtb \ aspeed-bmc-facebook-cmm.dtb \ + aspeed-bmc-facebook-galaxy100.dtb \ aspeed-bmc-facebook-minipack.dtb \ aspeed-bmc-facebook-tiogapass.dtb \ aspeed-bmc-facebook-wedge40.dtb \ diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-galaxy100.dts b/arch/arm/boot/dts/aspeed-bmc-facebook-galaxy100.dts new file mode 100644 index 000000000000..dcf213472749 --- /dev/null +++ b/arch/arm/boot/dts/aspeed-bmc-facebook-galaxy100.dts @@ -0,0 +1,57 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright (c) 2020 Facebook Inc. +/dts-v1/; + +#include "ast2400-facebook-netbmc-common.dtsi" + +/ { + model = "Facebook Galaxy 100 BMC"; + compatible = "facebook,galaxy100-bmc", "aspeed,ast2400"; + + chosen { + stdout-path = &uart5; + bootargs = "console=ttyS0,9600n8 root=/dev/ram rw"; + }; + + ast-adc-hwmon { + compatible = "iio-hwmon"; + io-channels = <&adc 3>, <&adc 4>, <&adc 8>, <&adc 9>; + }; +}; + +&wdt2 { + status = "okay"; + aspeed,reset-type = "system"; +}; + +&fmc { + flash@1 { + status = "okay"; + m25p,fast-read; + label = "spi0.1"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + flash1@0 { + reg = <0x0 0x2000000>; + label = "flash1"; + }; + }; + }; +}; + + +&i2c9 { + status = "okay"; +}; + +&vhub { + status = "okay"; +}; + +&adc { + status = "okay"; +}; -- cgit v1.2.3-59-g8ed1b From 735e8d93dc2b107f7891a9c2b1c4cfbea1fcbbbc Mon Sep 17 00:00:00 2001 From: Fangrui Song Date: Fri, 6 Nov 2020 21:46:11 +0100 Subject: ARM: 9022/1: Change arch/arm/lib/mem*.S to use WEAK instead of .weak Commit d6d51a96c7d6 ("ARM: 9014/2: Replace string mem* functions for KASan") add .weak directives to memcpy/memmove/memset to avoid collision with KASAN interceptors. This does not work with LLVM's integrated assembler (the assembly snippet `.weak memcpy ... .globl memcpy` produces a STB_GLOBAL memcpy while GNU as produces a STB_WEAK memcpy). LLVM 12 (since https://reviews.llvm.org/D90108) will error on such an overridden symbol binding. Use the appropriate WEAK macro instead. Link: https://github.com/ClangBuiltLinux/linux/issues/1190 -- Fixes: d6d51a96c7d6 ("ARM: 9014/2: Replace string mem* functions for KASan") Reported-by: Nick Desaulniers Signed-off-by: Fangrui Song Reviewed-by: Nick Desaulniers Tested-by: Nick Desaulniers Signed-off-by: Russell King --- arch/arm/lib/memcpy.S | 3 +-- arch/arm/lib/memmove.S | 3 +-- arch/arm/lib/memset.S | 3 +-- 3 files changed, 3 insertions(+), 6 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/lib/memcpy.S b/arch/arm/lib/memcpy.S index ad4625d16e11..e4caf48c089f 100644 --- a/arch/arm/lib/memcpy.S +++ b/arch/arm/lib/memcpy.S @@ -58,10 +58,9 @@ /* Prototype: void *memcpy(void *dest, const void *src, size_t n); */ -.weak memcpy ENTRY(__memcpy) ENTRY(mmiocpy) -ENTRY(memcpy) +WEAK(memcpy) #include "copy_template.S" diff --git a/arch/arm/lib/memmove.S b/arch/arm/lib/memmove.S index fd123ea5a5a4..6fecc12a1f51 100644 --- a/arch/arm/lib/memmove.S +++ b/arch/arm/lib/memmove.S @@ -24,9 +24,8 @@ * occurring in the opposite direction. */ -.weak memmove ENTRY(__memmove) -ENTRY(memmove) +WEAK(memmove) UNWIND( .fnstart ) subs ip, r0, r1 diff --git a/arch/arm/lib/memset.S b/arch/arm/lib/memset.S index 0e7ff0423f50..9817cb258c1a 100644 --- a/arch/arm/lib/memset.S +++ b/arch/arm/lib/memset.S @@ -13,10 +13,9 @@ .text .align 5 -.weak memset ENTRY(__memset) ENTRY(mmioset) -ENTRY(memset) +WEAK(memset) UNWIND( .fnstart ) ands r3, r0, #3 @ 1 unaligned? mov ip, r0 @ preserve r0 as return value -- cgit v1.2.3-59-g8ed1b From df8eda0f1f58e2419875046f57c27c4d72378575 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 10 Nov 2020 16:59:30 +0100 Subject: ARM: 9023/1: Spelling s/mmeory/memory/ Fix a misspelling of the word "memory". Signed-off-by: Geert Uytterhoeven Signed-off-by: Russell King --- arch/arm/kernel/setup.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c index d32f7652a5bf..f9de7658d9b3 100644 --- a/arch/arm/kernel/setup.c +++ b/arch/arm/kernel/setup.c @@ -1136,7 +1136,7 @@ void __init setup_arch(char **cmdline_p) efi_init(); /* * Make sure the calculation for lowmem/highmem is set appropriately - * before reserving/allocating any mmeory + * before reserving/allocating any memory */ adjust_lowmem_bounds(); arm_memblock_init(mdesc); -- cgit v1.2.3-59-g8ed1b From 730b5764ea8526e48bdb85a24ed96d62de435940 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 10 Nov 2020 16:58:41 +0100 Subject: ARM: 9024/1: Drop useless cast of "u64" to "long long" As "u64" is equivalent to "unsigned long long", there is no need to cast a "u64" parameter for printing it using the "0x%08llx" format specifier. Signed-off-by: Geert Uytterhoeven Signed-off-by: Russell King --- arch/arm/kernel/setup.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c index f9de7658d9b3..1a5edf562e85 100644 --- a/arch/arm/kernel/setup.c +++ b/arch/arm/kernel/setup.c @@ -765,7 +765,7 @@ int __init arm_add_memory(u64 start, u64 size) #ifndef CONFIG_PHYS_ADDR_T_64BIT if (aligned_start > ULONG_MAX) { pr_crit("Ignoring memory at 0x%08llx outside 32-bit physical address space\n", - (long long)start); + start); return -EINVAL; } -- cgit v1.2.3-59-g8ed1b From 32d59773da38cd83e497a70eb9754d4bbae3aeae Mon Sep 17 00:00:00 2001 From: Jens Axboe Date: Fri, 9 Oct 2020 16:00:49 -0600 Subject: arm: add support for TIF_NOTIFY_SIGNAL Wire up TIF_NOTIFY_SIGNAL handling for arm. Cc: linux-arm-kernel@lists.infradead.org Acked-by: Russell King Signed-off-by: Jens Axboe --- arch/arm/include/asm/thread_info.h | 7 ++++++- arch/arm/kernel/entry-common.S | 6 +++--- arch/arm/kernel/entry-v7m.S | 2 +- arch/arm/kernel/signal.c | 2 +- 4 files changed, 11 insertions(+), 6 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/include/asm/thread_info.h b/arch/arm/include/asm/thread_info.h index 536b6b979f63..eb7ce2747eb0 100644 --- a/arch/arm/include/asm/thread_info.h +++ b/arch/arm/include/asm/thread_info.h @@ -126,6 +126,8 @@ extern int vfp_restore_user_hwstate(struct user_vfp *, * thread information flags: * TIF_USEDFPU - FPU was used by this task this quantum (SMP) * TIF_POLLING_NRFLAG - true if poll_idle() is polling TIF_NEED_RESCHED + * + * Any bit in the range of 0..15 will cause do_work_pending() to be invoked. */ #define TIF_SIGPENDING 0 /* signal pending */ #define TIF_NEED_RESCHED 1 /* rescheduling necessary */ @@ -135,6 +137,7 @@ extern int vfp_restore_user_hwstate(struct user_vfp *, #define TIF_SYSCALL_AUDIT 5 /* syscall auditing active */ #define TIF_SYSCALL_TRACEPOINT 6 /* syscall tracepoint instrumentation */ #define TIF_SECCOMP 7 /* seccomp syscall filtering active */ +#define TIF_NOTIFY_SIGNAL 8 /* signal notifications exist */ #define TIF_USING_IWMMXT 17 #define TIF_MEMDIE 18 /* is terminating due to OOM killer */ @@ -148,6 +151,7 @@ extern int vfp_restore_user_hwstate(struct user_vfp *, #define _TIF_SYSCALL_AUDIT (1 << TIF_SYSCALL_AUDIT) #define _TIF_SYSCALL_TRACEPOINT (1 << TIF_SYSCALL_TRACEPOINT) #define _TIF_SECCOMP (1 << TIF_SECCOMP) +#define _TIF_NOTIFY_SIGNAL (1 << TIF_NOTIFY_SIGNAL) #define _TIF_USING_IWMMXT (1 << TIF_USING_IWMMXT) /* Checks for any syscall work in entry-common.S */ @@ -158,7 +162,8 @@ extern int vfp_restore_user_hwstate(struct user_vfp *, * Change these and you break ASM code in entry-common.S */ #define _TIF_WORK_MASK (_TIF_NEED_RESCHED | _TIF_SIGPENDING | \ - _TIF_NOTIFY_RESUME | _TIF_UPROBE) + _TIF_NOTIFY_RESUME | _TIF_UPROBE | \ + _TIF_NOTIFY_SIGNAL) #endif /* __KERNEL__ */ #endif /* __ASM_ARM_THREAD_INFO_H */ diff --git a/arch/arm/kernel/entry-common.S b/arch/arm/kernel/entry-common.S index 271cb8a1eba1..77d16390a524 100644 --- a/arch/arm/kernel/entry-common.S +++ b/arch/arm/kernel/entry-common.S @@ -53,7 +53,7 @@ __ret_fast_syscall: cmp r2, #TASK_SIZE blne addr_limit_check_failed ldr r1, [tsk, #TI_FLAGS] @ re-check for syscall tracing - tst r1, #_TIF_SYSCALL_WORK | _TIF_WORK_MASK + movs r1, r1, lsl #16 bne fast_work_pending @@ -90,7 +90,7 @@ __ret_fast_syscall: cmp r2, #TASK_SIZE blne addr_limit_check_failed ldr r1, [tsk, #TI_FLAGS] @ re-check for syscall tracing - tst r1, #_TIF_SYSCALL_WORK | _TIF_WORK_MASK + movs r1, r1, lsl #16 beq no_work_pending UNWIND(.fnend ) ENDPROC(ret_fast_syscall) @@ -131,7 +131,7 @@ ENTRY(ret_to_user_from_irq) cmp r2, #TASK_SIZE blne addr_limit_check_failed ldr r1, [tsk, #TI_FLAGS] - tst r1, #_TIF_WORK_MASK + movs r1, r1, lsl #16 bne slow_work_pending no_work_pending: asm_trace_hardirqs_on save = 0 diff --git a/arch/arm/kernel/entry-v7m.S b/arch/arm/kernel/entry-v7m.S index de1f20624be1..d0e898608d30 100644 --- a/arch/arm/kernel/entry-v7m.S +++ b/arch/arm/kernel/entry-v7m.S @@ -59,7 +59,7 @@ __irq_entry: get_thread_info tsk ldr r2, [tsk, #TI_FLAGS] - tst r2, #_TIF_WORK_MASK + movs r2, r2, lsl #16 beq 2f @ no work pending mov r0, #V7M_SCB_ICSR_PENDSVSET str r0, [r1, V7M_SCB_ICSR] @ raise PendSV diff --git a/arch/arm/kernel/signal.c b/arch/arm/kernel/signal.c index 585edbfccf6d..9d2e916121be 100644 --- a/arch/arm/kernel/signal.c +++ b/arch/arm/kernel/signal.c @@ -655,7 +655,7 @@ do_work_pending(struct pt_regs *regs, unsigned int thread_flags, int syscall) if (unlikely(!user_mode(regs))) return 0; local_irq_enable(); - if (thread_flags & _TIF_SIGPENDING) { + if (thread_flags & (_TIF_SIGPENDING | _TIF_NOTIFY_SIGNAL)) { int restart = do_signal(regs, syscall); if (unlikely(restart)) { /* -- cgit v1.2.3-59-g8ed1b From 86cd97ec4b943af35562a74688bc4e909b32c3d1 Mon Sep 17 00:00:00 2001 From: Ard Biesheuvel Date: Tue, 3 Nov 2020 17:28:09 +0100 Subject: crypto: arm/chacha-neon - optimize for non-block size multiples The current NEON based ChaCha implementation for ARM is optimized for multiples of 4x the ChaCha block size (64 bytes). This makes sense for block encryption, but given that ChaCha is also often used in the context of networking, it makes sense to consider arbitrary length inputs as well. For example, WireGuard typically uses 1420 byte packets, and performing ChaCha encryption involves 5 invocations of chacha_4block_xor_neon() and 3 invocations of chacha_block_xor_neon(), where the last one also involves a memcpy() using a buffer on the stack to process the final chunk of 1420 % 64 == 12 bytes. Let's optimize for this case as well, by letting chacha_4block_xor_neon() deal with any input size between 64 and 256 bytes, using NEON permutation instructions and overlapping loads and stores. This way, the 140 byte tail of a 1420 byte input buffer can simply be processed in one go. This results in the following performance improvements for 1420 byte blocks, without significant impact on power-of-2 input sizes. (Note that Raspberry Pi is widely used in combination with a 32-bit kernel, even though the core is 64-bit capable) Cortex-A8 (BeagleBone) : 7% Cortex-A15 (Calxeda Midway) : 21% Cortex-A53 (Raspberry Pi 3) : 3% Cortex-A72 (Raspberry Pi 4) : 19% Cc: Eric Biggers Cc: "Jason A . Donenfeld" Signed-off-by: Ard Biesheuvel Signed-off-by: Herbert Xu --- arch/arm/crypto/chacha-glue.c | 34 ++++++------- arch/arm/crypto/chacha-neon-core.S | 97 +++++++++++++++++++++++++++++++++++--- 2 files changed, 107 insertions(+), 24 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/crypto/chacha-glue.c b/arch/arm/crypto/chacha-glue.c index 59da6c0b63b6..7b5cf8430c6d 100644 --- a/arch/arm/crypto/chacha-glue.c +++ b/arch/arm/crypto/chacha-glue.c @@ -23,7 +23,7 @@ asmlinkage void chacha_block_xor_neon(const u32 *state, u8 *dst, const u8 *src, int nrounds); asmlinkage void chacha_4block_xor_neon(const u32 *state, u8 *dst, const u8 *src, - int nrounds); + int nrounds, unsigned int nbytes); asmlinkage void hchacha_block_arm(const u32 *state, u32 *out, int nrounds); asmlinkage void hchacha_block_neon(const u32 *state, u32 *out, int nrounds); @@ -42,24 +42,24 @@ static void chacha_doneon(u32 *state, u8 *dst, const u8 *src, { u8 buf[CHACHA_BLOCK_SIZE]; - while (bytes >= CHACHA_BLOCK_SIZE * 4) { - chacha_4block_xor_neon(state, dst, src, nrounds); - bytes -= CHACHA_BLOCK_SIZE * 4; - src += CHACHA_BLOCK_SIZE * 4; - dst += CHACHA_BLOCK_SIZE * 4; - state[12] += 4; - } - while (bytes >= CHACHA_BLOCK_SIZE) { - chacha_block_xor_neon(state, dst, src, nrounds); - bytes -= CHACHA_BLOCK_SIZE; - src += CHACHA_BLOCK_SIZE; - dst += CHACHA_BLOCK_SIZE; - state[12]++; + while (bytes > CHACHA_BLOCK_SIZE) { + unsigned int l = min(bytes, CHACHA_BLOCK_SIZE * 4U); + + chacha_4block_xor_neon(state, dst, src, nrounds, l); + bytes -= l; + src += l; + dst += l; + state[12] += DIV_ROUND_UP(l, CHACHA_BLOCK_SIZE); } if (bytes) { - memcpy(buf, src, bytes); - chacha_block_xor_neon(state, buf, buf, nrounds); - memcpy(dst, buf, bytes); + const u8 *s = src; + u8 *d = dst; + + if (bytes != CHACHA_BLOCK_SIZE) + s = d = memcpy(buf, src, bytes); + chacha_block_xor_neon(state, d, s, nrounds); + if (d != dst) + memcpy(dst, buf, bytes); } } diff --git a/arch/arm/crypto/chacha-neon-core.S b/arch/arm/crypto/chacha-neon-core.S index eb22926d4912..13d12f672656 100644 --- a/arch/arm/crypto/chacha-neon-core.S +++ b/arch/arm/crypto/chacha-neon-core.S @@ -47,6 +47,7 @@ */ #include +#include .text .fpu neon @@ -205,7 +206,7 @@ ENDPROC(hchacha_block_neon) .align 5 ENTRY(chacha_4block_xor_neon) - push {r4-r5} + push {r4, lr} mov r4, sp // preserve the stack pointer sub ip, sp, #0x20 // allocate a 32 byte buffer bic ip, ip, #0x1f // aligned to 32 bytes @@ -229,10 +230,10 @@ ENTRY(chacha_4block_xor_neon) vld1.32 {q0-q1}, [r0] vld1.32 {q2-q3}, [ip] - adr r5, .Lctrinc + adr lr, .Lctrinc vdup.32 q15, d7[1] vdup.32 q14, d7[0] - vld1.32 {q4}, [r5, :128] + vld1.32 {q4}, [lr, :128] vdup.32 q13, d6[1] vdup.32 q12, d6[0] vdup.32 q11, d5[1] @@ -455,7 +456,7 @@ ENTRY(chacha_4block_xor_neon) // Re-interleave the words in the first two rows of each block (x0..7). // Also add the counter values 0-3 to x12[0-3]. - vld1.32 {q8}, [r5, :128] // load counter values 0-3 + vld1.32 {q8}, [lr, :128] // load counter values 0-3 vzip.32 q0, q1 // => (0 1 0 1) (0 1 0 1) vzip.32 q2, q3 // => (2 3 2 3) (2 3 2 3) vzip.32 q4, q5 // => (4 5 4 5) (4 5 4 5) @@ -493,6 +494,8 @@ ENTRY(chacha_4block_xor_neon) // Re-interleave the words in the last two rows of each block (x8..15). vld1.32 {q8-q9}, [sp, :256] + mov sp, r4 // restore original stack pointer + ldr r4, [r4, #8] // load number of bytes vzip.32 q12, q13 // => (12 13 12 13) (12 13 12 13) vzip.32 q14, q15 // => (14 15 14 15) (14 15 14 15) vzip.32 q8, q9 // => (8 9 8 9) (8 9 8 9) @@ -520,41 +523,121 @@ ENTRY(chacha_4block_xor_neon) // XOR the rest of the data with the keystream vld1.8 {q0-q1}, [r2]! + subs r4, r4, #96 veor q0, q0, q8 veor q1, q1, q12 + ble .Lle96 vst1.8 {q0-q1}, [r1]! vld1.8 {q0-q1}, [r2]! + subs r4, r4, #32 veor q0, q0, q2 veor q1, q1, q6 + ble .Lle128 vst1.8 {q0-q1}, [r1]! vld1.8 {q0-q1}, [r2]! + subs r4, r4, #32 veor q0, q0, q10 veor q1, q1, q14 + ble .Lle160 vst1.8 {q0-q1}, [r1]! vld1.8 {q0-q1}, [r2]! + subs r4, r4, #32 veor q0, q0, q4 veor q1, q1, q5 + ble .Lle192 vst1.8 {q0-q1}, [r1]! vld1.8 {q0-q1}, [r2]! + subs r4, r4, #32 veor q0, q0, q9 veor q1, q1, q13 + ble .Lle224 vst1.8 {q0-q1}, [r1]! vld1.8 {q0-q1}, [r2]! + subs r4, r4, #32 veor q0, q0, q3 veor q1, q1, q7 + blt .Llt256 +.Lout: vst1.8 {q0-q1}, [r1]! vld1.8 {q0-q1}, [r2] - mov sp, r4 // restore original stack pointer veor q0, q0, q11 veor q1, q1, q15 vst1.8 {q0-q1}, [r1] - pop {r4-r5} - bx lr + pop {r4, pc} + +.Lle192: + vmov q4, q9 + vmov q5, q13 + +.Lle160: + // nothing to do + +.Lfinalblock: + // Process the final block if processing less than 4 full blocks. + // Entered with 32 bytes of ChaCha cipher stream in q4-q5, and the + // previous 32 byte output block that still needs to be written at + // [r1] in q0-q1. + beq .Lfullblock + +.Lpartialblock: + adr lr, .Lpermute + 32 + add r2, r2, r4 + add lr, lr, r4 + add r4, r4, r1 + + vld1.8 {q2-q3}, [lr] + vld1.8 {q6-q7}, [r2] + + add r4, r4, #32 + + vtbl.8 d4, {q4-q5}, d4 + vtbl.8 d5, {q4-q5}, d5 + vtbl.8 d6, {q4-q5}, d6 + vtbl.8 d7, {q4-q5}, d7 + + veor q6, q6, q2 + veor q7, q7, q3 + + vst1.8 {q6-q7}, [r4] // overlapping stores + vst1.8 {q0-q1}, [r1] + pop {r4, pc} + +.Lfullblock: + vmov q11, q4 + vmov q15, q5 + b .Lout +.Lle96: + vmov q4, q2 + vmov q5, q6 + b .Lfinalblock +.Lle128: + vmov q4, q10 + vmov q5, q14 + b .Lfinalblock +.Lle224: + vmov q4, q3 + vmov q5, q7 + b .Lfinalblock +.Llt256: + vmov q4, q11 + vmov q5, q15 + b .Lpartialblock ENDPROC(chacha_4block_xor_neon) + + .align L1_CACHE_SHIFT +.Lpermute: + .byte 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07 + .byte 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f + .byte 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17 + .byte 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f + .byte 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07 + .byte 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f + .byte 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17 + .byte 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f -- cgit v1.2.3-59-g8ed1b From 632ddf978565378e7efb9ea77c0ba239ea66bfdc Mon Sep 17 00:00:00 2001 From: Rafał Miłecki Date: Fri, 13 Nov 2020 11:09:19 +0100 Subject: ARM: dts: BCM5301X: Disable USB 3 PHY on devices without USB 3 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit It seems pointless to have it enabled. Signed-off-by: Rafał Miłecki Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm4708-luxul-xap-1510.dts | 4 ---- arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts | 4 ---- arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts | 4 ---- arch/arm/boot/dts/bcm47081-luxul-xap-1410.dts | 4 ---- arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts | 4 ---- arch/arm/boot/dts/bcm47081-tplink-archer-c5-v2.dts | 4 ---- 6 files changed, 24 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/bcm4708-luxul-xap-1510.dts b/arch/arm/boot/dts/bcm4708-luxul-xap-1510.dts index 810fc32f1895..7f07b78c1ac3 100644 --- a/arch/arm/boot/dts/bcm4708-luxul-xap-1510.dts +++ b/arch/arm/boot/dts/bcm4708-luxul-xap-1510.dts @@ -57,10 +57,6 @@ status = "okay"; }; -&usb3_phy { - status = "okay"; -}; - &srab { status = "okay"; diff --git a/arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts b/arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts index 7604b4480bb1..548faa0c44c8 100644 --- a/arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts +++ b/arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts @@ -64,10 +64,6 @@ status = "okay"; }; -&usb3_phy { - status = "okay"; -}; - &srab { status = "okay"; diff --git a/arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts b/arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts index 4dcec6865469..2f2d2b0a6893 100644 --- a/arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts +++ b/arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts @@ -117,7 +117,3 @@ }; }; }; - -&usb3_phy { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/bcm47081-luxul-xap-1410.dts b/arch/arm/boot/dts/bcm47081-luxul-xap-1410.dts index 1ec655809e57..944e81cab338 100644 --- a/arch/arm/boot/dts/bcm47081-luxul-xap-1410.dts +++ b/arch/arm/boot/dts/bcm47081-luxul-xap-1410.dts @@ -57,10 +57,6 @@ status = "okay"; }; -&usb3_phy { - status = "okay"; -}; - &srab { status = "okay"; diff --git a/arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts b/arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts index 04bfd58127fc..d1ae7dc10775 100644 --- a/arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts +++ b/arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts @@ -105,10 +105,6 @@ status = "okay"; }; -&usb3_phy { - status = "okay"; -}; - &srab { status = "okay"; diff --git a/arch/arm/boot/dts/bcm47081-tplink-archer-c5-v2.dts b/arch/arm/boot/dts/bcm47081-tplink-archer-c5-v2.dts index 01c390ed48ea..12e34a0439b4 100644 --- a/arch/arm/boot/dts/bcm47081-tplink-archer-c5-v2.dts +++ b/arch/arm/boot/dts/bcm47081-tplink-archer-c5-v2.dts @@ -126,7 +126,3 @@ &usb2 { vcc-gpio = <&chipcommon 9 GPIO_ACTIVE_HIGH>; }; - -&usb3_phy { - status = "okay"; -}; -- cgit v1.2.3-59-g8ed1b From b2ab5e8697ef6591aeeda23be49e096705dbbda3 Mon Sep 17 00:00:00 2001 From: Rafał Miłecki Date: Fri, 13 Nov 2020 10:50:12 +0100 Subject: ARM: dts: BCM5301X: Enable USB 3 PHY on Luxul XWR-3150 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This device has a functional USB 3 port so PHY is required. Signed-off-by: Rafał Miłecki Reported-by: kernel test robot Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm47094-luxul-xwr-3150-v1.dts | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/bcm47094-luxul-xwr-3150-v1.dts b/arch/arm/boot/dts/bcm47094-luxul-xwr-3150-v1.dts index 4d5c5aa7dc42..a361aa8627d3 100644 --- a/arch/arm/boot/dts/bcm47094-luxul-xwr-3150-v1.dts +++ b/arch/arm/boot/dts/bcm47094-luxul-xwr-3150-v1.dts @@ -71,6 +71,10 @@ vcc-gpio = <&chipcommon 18 GPIO_ACTIVE_HIGH>; }; +&usb3_phy { + status = "okay"; +}; + &spi_nor { status = "okay"; }; -- cgit v1.2.3-59-g8ed1b From f949d414fc1a9dfdfc878134629052135bd527db Mon Sep 17 00:00:00 2001 From: Łukasz Stelmach Date: Tue, 3 Nov 2020 19:44:07 +0100 Subject: ARM: dts: exynos: Fix Ethernet interface description on Odroid XU3 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Assign appropriate compatible properties matching real USB vendor and product ID. Signed-off-by: Łukasz Stelmach Link: https://lore.kernel.org/r/20201103184412.18874-2-l.stelmach@samsung.com Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos5422-odroidxu3.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3.dts b/arch/arm/boot/dts/exynos5422-odroidxu3.dts index 53aee3d56f6a..cdd3a5fef216 100644 --- a/arch/arm/boot/dts/exynos5422-odroidxu3.dts +++ b/arch/arm/boot/dts/exynos5422-odroidxu3.dts @@ -76,13 +76,13 @@ #size-cells = <0>; hub@1 { - compatible = "usb8087,0024"; + compatible = "usb0424,9514"; reg = <1>; #address-cells = <1>; #size-cells = <0>; ethernet: usbether@1 { - compatible = "usb0c45,6310"; + compatible = "usb0424,ec00"; reg = <1>; local-mac-address = [00 00 00 00 00 00]; /* Filled in by a bootloader */ }; -- cgit v1.2.3-59-g8ed1b From c0f5d3873bc806f32584558fc1c8c593758c2967 Mon Sep 17 00:00:00 2001 From: Łukasz Stelmach Date: Tue, 3 Nov 2020 19:44:08 +0100 Subject: ARM: dts: exynos: Add an alias for the Ethernet interface on Odroid XU3 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add an alias to enable bootloaders to find the Ethernet interface and assign a MAC address. Signed-off-by: Łukasz Stelmach Link: https://lore.kernel.org/r/20201103184412.18874-3-l.stelmach@samsung.com Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos5422-odroidxu3.dts | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3.dts b/arch/arm/boot/dts/exynos5422-odroidxu3.dts index cdd3a5fef216..cecaeb69e623 100644 --- a/arch/arm/boot/dts/exynos5422-odroidxu3.dts +++ b/arch/arm/boot/dts/exynos5422-odroidxu3.dts @@ -15,6 +15,10 @@ / { model = "Hardkernel Odroid XU3"; compatible = "hardkernel,odroid-xu3", "samsung,exynos5800", "samsung,exynos5"; + + aliases { + ethernet = ðernet; + }; }; &i2c_0 { -- cgit v1.2.3-59-g8ed1b From 7f415677420ff97dd7792eab02dd00e25fcd1f15 Mon Sep 17 00:00:00 2001 From: Jonathan Cameron Date: Sun, 15 Nov 2020 19:29:45 +0000 Subject: ARM: dts: Cygnus: Drop incorrect io-channel-ranges property. This property applies to consumers of io-channels. In this case we have a provider so the property is not used. Recent changes to dt-schema result int his being reported as an error as a dependency is enforced between this property and io-channels. Signed-off-by: Jonathan Cameron Cc: Florian Fainelli Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm-cygnus.dtsi | 1 - 1 file changed, 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/bcm-cygnus.dtsi b/arch/arm/boot/dts/bcm-cygnus.dtsi index dacaef2c14ca..0025c88f660c 100644 --- a/arch/arm/boot/dts/bcm-cygnus.dtsi +++ b/arch/arm/boot/dts/bcm-cygnus.dtsi @@ -591,7 +591,6 @@ adc: adc@180a6000 { compatible = "brcm,iproc-static-adc"; #io-channel-cells = <1>; - io-channel-ranges; adc-syscon = <&ts_adc_syscon>; clocks = <&asiu_clks BCM_CYGNUS_ASIU_ADC_CLK>; clock-names = "tsc_clk"; -- cgit v1.2.3-59-g8ed1b From c9f6aa9d1f50fa1b6429bfa9cb50648379b1c710 Mon Sep 17 00:00:00 2001 From: Tao Ren Date: Mon, 9 Nov 2020 23:21:59 -0800 Subject: ARM: dts: aspeed: wedge400: Fix FMC flash0 layout Update "data0" partition's size from 8MB to 4MB to fix "partition data0 extends beyond the end of device" warning at bootup time. Signed-off-by: Tao Ren Reviewed-by: Joel Stanley Link: https://lore.kernel.org/r/20201110072159.7941-1-rentao.bupt@gmail.com Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-facebook-wedge400.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-wedge400.dts b/arch/arm/boot/dts/aspeed-bmc-facebook-wedge400.dts index ad1fcad3676c..63a3dd548f30 100644 --- a/arch/arm/boot/dts/aspeed-bmc-facebook-wedge400.dts +++ b/arch/arm/boot/dts/aspeed-bmc-facebook-wedge400.dts @@ -124,8 +124,8 @@ * "data0" partition (4MB) is reserved for persistent * data store. */ - data0@3800000 { - reg = <0x7c00000 0x800000>; + data0@7c00000 { + reg = <0x7c00000 0x400000>; label = "data0"; }; -- cgit v1.2.3-59-g8ed1b From 2e7cd913eafcdfa008565d91e9d1f253f89f7c3b Mon Sep 17 00:00:00 2001 From: Tao Ren Date: Mon, 9 Nov 2020 23:24:46 -0800 Subject: ARM: dts: aspeed: minipack: Fixup I2C tree Create all the i2c switches in device tree and use aliases to assign child channels with consistent bus numbers. Besides, "i2c-mux-idle-disconnect" is set for all the i2c switches to avoid potential conflicts when multiple devices (beind the switches) use the same device address. Signed-off-by: Tao Ren Reviewed-by: Joel Stanley Link: https://lore.kernel.org/r/20201110072446.8218-1-rentao.bupt@gmail.com Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-facebook-minipack.dts | 888 +++++++++++++++++++++ 1 file changed, 888 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-minipack.dts b/arch/arm/boot/dts/aspeed-bmc-facebook-minipack.dts index c34741dbd268..9eb23e874f19 100644 --- a/arch/arm/boot/dts/aspeed-bmc-facebook-minipack.dts +++ b/arch/arm/boot/dts/aspeed-bmc-facebook-minipack.dts @@ -70,6 +70,162 @@ i2c45 = &imux45; i2c46 = &imux46; i2c47 = &imux47; + + /* + * I2C Switch 24-0071 (channel #0 of 8-0070): 8 channels for + * connecting to left PDB (Power Distribution Board). + */ + i2c48 = &imux48; + i2c49 = &imux49; + i2c50 = &imux50; + i2c51 = &imux51; + i2c52 = &imux52; + i2c53 = &imux53; + i2c54 = &imux54; + i2c55 = &imux55; + + /* + * I2C Switch 25-0072 (channel #1 of 8-0070): 8 channels for + * connecting to right PDB (Power Distribution Board). + */ + i2c56 = &imux56; + i2c57 = &imux57; + i2c58 = &imux58; + i2c59 = &imux59; + i2c60 = &imux60; + i2c61 = &imux61; + i2c62 = &imux62; + i2c63 = &imux63; + + /* + * I2C Switch 26-0076 (channel #2 of 8-0070): 8 channels for + * connecting to top FCM (Fan Control Module). + */ + i2c64 = &imux64; + i2c65 = &imux65; + i2c66 = &imux66; + i2c67 = &imux67; + i2c68 = &imux68; + i2c69 = &imux69; + i2c70 = &imux70; + i2c71 = &imux71; + + /* + * I2C Switch 27-0076 (channel #3 of 8-0070): 8 channels for + * connecting to bottom FCM (Fan Control Module). + */ + i2c72 = &imux72; + i2c73 = &imux73; + i2c74 = &imux74; + i2c75 = &imux75; + i2c76 = &imux76; + i2c77 = &imux77; + i2c78 = &imux78; + i2c79 = &imux79; + + /* + * I2C Switch 40-0073 (channel #0 of 11-0070): connecting + * to PIM (Port Interface Module) #1 (1-based). + */ + i2c80 = &imux80; + i2c81 = &imux81; + i2c82 = &imux82; + i2c83 = &imux83; + i2c84 = &imux84; + i2c85 = &imux85; + i2c86 = &imux86; + i2c87 = &imux87; + + /* + * I2C Switch 41-0073 (channel #1 of 11-0070): connecting + * to PIM (Port Interface Module) #2 (1-based). + */ + i2c88 = &imux88; + i2c89 = &imux89; + i2c90 = &imux90; + i2c91 = &imux91; + i2c92 = &imux92; + i2c93 = &imux93; + i2c94 = &imux94; + i2c95 = &imux95; + + /* + * I2C Switch 42-0073 (channel #2 of 11-0070): connecting + * to PIM (Port Interface Module) #3 (1-based). + */ + i2c96 = &imux96; + i2c97 = &imux97; + i2c98 = &imux98; + i2c99 = &imux99; + i2c100 = &imux100; + i2c101 = &imux101; + i2c102 = &imux102; + i2c103 = &imux103; + + /* + * I2C Switch 43-0073 (channel #3 of 11-0070): connecting + * to PIM (Port Interface Module) #4 (1-based). + */ + i2c104 = &imux104; + i2c105 = &imux105; + i2c106 = &imux106; + i2c107 = &imux107; + i2c108 = &imux108; + i2c109 = &imux109; + i2c110 = &imux110; + i2c111 = &imux111; + + /* + * I2C Switch 44-0073 (channel #4 of 11-0070): connecting + * to PIM (Port Interface Module) #5 (1-based). + */ + i2c112 = &imux112; + i2c113 = &imux113; + i2c114 = &imux114; + i2c115 = &imux115; + i2c116 = &imux116; + i2c117 = &imux117; + i2c118 = &imux118; + i2c119 = &imux119; + + /* + * I2C Switch 45-0073 (channel #5 of 11-0070): connecting + * to PIM (Port Interface Module) #6 (1-based). + */ + i2c120 = &imux120; + i2c121 = &imux121; + i2c122 = &imux122; + i2c123 = &imux123; + i2c124 = &imux124; + i2c125 = &imux125; + i2c126 = &imux126; + i2c127 = &imux127; + + /* + * I2C Switch 46-0073 (channel #6 of 11-0070): connecting + * to PIM (Port Interface Module) #7 (1-based). + */ + i2c128 = &imux128; + i2c129 = &imux129; + i2c130 = &imux130; + i2c131 = &imux131; + i2c132 = &imux132; + i2c133 = &imux133; + i2c134 = &imux134; + i2c135 = &imux135; + + /* + * I2C Switch 47-0073 (channel #7 of 11-0070): connecting + * to PIM (Port Interface Module) #8 (1-based). + */ + i2c136 = &imux136; + i2c137 = &imux137; + i2c138 = &imux138; + i2c139 = &imux139; + i2c140 = &imux140; + i2c141 = &imux141; + i2c142 = &imux142; + i2c143 = &imux143; }; chosen { @@ -184,11 +340,16 @@ &i2c2 { status = "okay"; + /* + * I2C Switch 2-0070 is connecting to SCM (System Controller + * Module). + */ i2c-switch@70 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x70>; + i2c-mux-idle-disconnect; imux16: i2c@0 { #address-cells = <1>; @@ -269,29 +430,270 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x70>; + i2c-mux-idle-disconnect; + /* + * I2C Switch 8-0070 channel #0: connecting to left PDB + * (Power Distribution Board). + */ imux24: i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; + + i2c-switch@71 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x71>; + i2c-mux-idle-disconnect; + + imux48: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + imux49: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + imux50: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + imux51: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + + imux52: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + + imux53: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + + imux54: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + + imux55: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + }; }; + /* + * I2C Switch 8-0070 channel #1: connecting to right PDB + * (Power Distribution Board). + */ imux25: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; + + i2c-switch@72 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x72>; + i2c-mux-idle-disconnect; + + imux56: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + imux57: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + imux58: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + imux59: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + + imux60: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + + imux61: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + + imux62: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + + imux63: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + }; }; + /* + * I2C Switch 8-0070 channel #2: connecting to top FCM + * (Fan Control Module). + */ imux26: i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; + + i2c-switch@76 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x76>; + i2c-mux-idle-disconnect; + + imux64: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + imux65: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + imux66: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + imux67: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + + imux68: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + + imux69: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + + imux70: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + + imux71: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + }; }; + /* + * I2C Switch 8-0070 channel #3: connecting to bottom + * FCM (Fan Control Module). + */ imux27: i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; + + i2c-switch@76 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x76>; + i2c-mux-idle-disconnect; + + imux72: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + imux73: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + imux74: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + imux75: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + + imux76: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + + imux77: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + + imux78: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + + imux79: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + }; }; imux28: i2c@4 { @@ -323,11 +725,16 @@ &i2c9 { status = "okay"; + /* + * I2C Switch 9-0070 is connecting to MAC/PHY EEPROMs on SMB + * (Switch Main Board). + */ i2c-switch@70 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x70>; + i2c-mux-idle-disconnect; imux32: i2c@0 { #address-cells = <1>; @@ -391,53 +798,534 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x70>; + i2c-mux-idle-disconnect; + /* + * I2C Switch 11-0070 channel #0: connecting to PIM + * (Port Interface Module) #1 (1-based). + */ imux40: i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; + + i2c-switch@73 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x73>; + i2c-mux-idle-disconnect; + + imux80: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + imux81: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + imux82: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + imux83: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + + imux84: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + + imux85: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + + imux86: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + + imux87: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + }; }; + /* + * I2C Switch 11-0070 channel #1: connecting to PIM + * (Port Interface Module) #2 (1-based). + */ imux41: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; + + i2c-switch@73 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x73>; + i2c-mux-idle-disconnect; + + imux88: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + imux89: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + imux90: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + imux91: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + + imux92: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + + imux93: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + + imux94: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + + imux95: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + }; }; + /* + * I2C Switch 11-0070 channel #2: connecting to PIM + * (Port Interface Module) #3 (1-based). + */ imux42: i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; + + i2c-switch@73 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x73>; + i2c-mux-idle-disconnect; + + imux96: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + imux97: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + imux98: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + imux99: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + + imux100: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + + imux101: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + + imux102: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + + imux103: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + }; }; + /* + * I2C Switch 11-0070 channel #3: connecting to PIM + * (Port Interface Module) #4 (1-based). + */ imux43: i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; + + i2c-switch@73 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x73>; + i2c-mux-idle-disconnect; + + imux104: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + imux105: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + imux106: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + imux107: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + + imux108: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + + imux109: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + + imux110: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + + imux111: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + }; }; + /* + * I2C Switch 11-0070 channel #4: connecting to PIM + * (Port Interface Module) #5 (1-based). + */ imux44: i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; + + i2c-switch@73 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x73>; + i2c-mux-idle-disconnect; + + imux112: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + imux113: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + imux114: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + imux115: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + + imux116: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + + imux117: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + + imux118: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + + imux119: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + }; }; + /* + * I2C Switch 11-0070 channel #5: connecting to PIM + * (Port Interface Module) #6 (1-based). + */ imux45: i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; + + i2c-switch@73 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x73>; + i2c-mux-idle-disconnect; + + imux120: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + imux121: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + imux122: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + imux123: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + + imux124: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + + imux125: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + + imux126: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + + imux127: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + }; }; + /* + * I2C Switch 11-0070 channel #6: connecting to PIM + * (Port Interface Module) #7 (1-based). + */ imux46: i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; + + i2c-switch@73 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x73>; + i2c-mux-idle-disconnect; + + imux128: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + imux129: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + imux130: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + imux131: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + + imux132: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + + imux133: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + + imux134: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + + imux135: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + }; }; + /* + * I2C Switch 11-0070 channel #7: connecting to PIM + * (Port Interface Module) #8 (1-based). + */ imux47: i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; + + i2c-switch@73 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x73>; + i2c-mux-idle-disconnect; + + imux136: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + imux137: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + imux138: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + imux139: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + + imux140: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + + imux141: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + + imux142: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + + imux143: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + }; }; }; }; -- cgit v1.2.3-59-g8ed1b From 6ff286225d75a1bcb61cf0ff714757a579305beb Mon Sep 17 00:00:00 2001 From: Paul Fertser Date: Wed, 30 Sep 2020 22:25:07 +0300 Subject: arm: dts: aspeed: tiogapass: Enable second MAC Tioga Pass reference design includes Intel I210 Ethernet controller connected to the BMC with NC/SI. MAC readout is not supported. Signed-off-by: Paul Fertser Reviewed-by: Vijay Khemka Tested-by: Vijay Khemka Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts b/arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts index e6ad821a8635..cd18641d5c23 100644 --- a/arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts +++ b/arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts @@ -191,6 +191,14 @@ use-ncsi; }; +&mac1 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rmii2_default>; + use-ncsi; +}; + &adc { status = "okay"; }; -- cgit v1.2.3-59-g8ed1b From 1186a522c302e01f1737b28e353bac137c47aca8 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 10 Nov 2020 19:50:34 +0100 Subject: ARM: dts: imx6q-pico: fix board compatibles There are four flavors of TechNexion PICO-IMX6 boards. They have their own DTSes, even though in Dwarf, Nymph and Pi are exactly the same. They also have their own bindings so adjust the compatibles to match the bindings. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6q-pico-dwarf.dts | 2 +- arch/arm/boot/dts/imx6q-pico-hobbit.dts | 2 +- arch/arm/boot/dts/imx6q-pico-nymph.dts | 2 +- arch/arm/boot/dts/imx6q-pico-pi.dts | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx6q-pico-dwarf.dts b/arch/arm/boot/dts/imx6q-pico-dwarf.dts index 618d2743e1e9..479a63ed42af 100644 --- a/arch/arm/boot/dts/imx6q-pico-dwarf.dts +++ b/arch/arm/boot/dts/imx6q-pico-dwarf.dts @@ -13,5 +13,5 @@ / { model = "TechNexion PICO-IMX6 Quad Board and Dwarf baseboard"; - compatible = "technexion,imx6q-pico", "fsl,imx6q"; + compatible = "technexion,imx6q-pico-dwarf", "fsl,imx6q"; }; diff --git a/arch/arm/boot/dts/imx6q-pico-hobbit.dts b/arch/arm/boot/dts/imx6q-pico-hobbit.dts index 7a666507b456..b767131068f5 100644 --- a/arch/arm/boot/dts/imx6q-pico-hobbit.dts +++ b/arch/arm/boot/dts/imx6q-pico-hobbit.dts @@ -13,5 +13,5 @@ / { model = "TechNexion PICO-IMX6 Quad Board and Hobbit baseboard"; - compatible = "technexion,imx6q-pico", "fsl,imx6q"; + compatible = "technexion,imx6q-pico-hobbit", "fsl,imx6q"; }; diff --git a/arch/arm/boot/dts/imx6q-pico-nymph.dts b/arch/arm/boot/dts/imx6q-pico-nymph.dts index fe5a7becc9e5..e8ad4c12b263 100644 --- a/arch/arm/boot/dts/imx6q-pico-nymph.dts +++ b/arch/arm/boot/dts/imx6q-pico-nymph.dts @@ -13,5 +13,5 @@ / { model = "TechNexion PICO-IMX6 Quad Board and Nymph baseboard"; - compatible = "technexion,imx6q-pico", "fsl,imx6q"; + compatible = "technexion,imx6q-pico-nymph", "fsl,imx6q"; }; diff --git a/arch/arm/boot/dts/imx6q-pico-pi.dts b/arch/arm/boot/dts/imx6q-pico-pi.dts index 9413f0a68f54..cc2394ddad6c 100644 --- a/arch/arm/boot/dts/imx6q-pico-pi.dts +++ b/arch/arm/boot/dts/imx6q-pico-pi.dts @@ -13,5 +13,5 @@ / { model = "TechNexion PICO-IMX6 Quad Board and PI baseboard"; - compatible = "technexion,imx6q-pico", "fsl,imx6q"; + compatible = "technexion,imx6q-pico-pi", "fsl,imx6q"; }; -- cgit v1.2.3-59-g8ed1b From 21658d51cf1ea88c04652a3852a190bb905cd91e Mon Sep 17 00:00:00 2001 From: Marc Kleine-Budde Date: Wed, 11 Nov 2020 14:05:05 +0100 Subject: ARM: dts: imx: Change flexcan node name to "can" Change i.MX SoCs nand node name from "flexcan" to "can" to be compliant with yaml schema, it requires the nodename to be "can". This fixes the following error found by dtbs_check: arch/arm/boot/dts/imx6dl-apf6dev.dt.yaml: flexcan@2090000: $nodename:0: 'flexcan@2090000' does not match '^can(@.*)?$' From schema: Documentation/devicetree/bindings/net/can/fsl,flexcan.yaml Cc: Shawn Guo Cc: devicetree@vger.kernel.org Signed-off-by: Marc Kleine-Budde Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl.dtsi | 4 ++-- arch/arm/boot/dts/imx6ul.dtsi | 4 ++-- arch/arm/boot/dts/vfxxx.dtsi | 4 ++-- 3 files changed, 6 insertions(+), 6 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi index cb2a8ef9070c..6f59a99cbe82 100644 --- a/arch/arm/boot/dts/imx6qdl.dtsi +++ b/arch/arm/boot/dts/imx6qdl.dtsi @@ -546,7 +546,7 @@ status = "disabled"; }; - can1: flexcan@2090000 { + can1: can@2090000 { compatible = "fsl,imx6q-flexcan"; reg = <0x02090000 0x4000>; interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>; @@ -557,7 +557,7 @@ status = "disabled"; }; - can2: flexcan@2094000 { + can2: can@2094000 { compatible = "fsl,imx6q-flexcan"; reg = <0x02094000 0x4000>; interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>; diff --git a/arch/arm/boot/dts/imx6ul.dtsi b/arch/arm/boot/dts/imx6ul.dtsi index ccbcbac80663..9d3411cc597b 100644 --- a/arch/arm/boot/dts/imx6ul.dtsi +++ b/arch/arm/boot/dts/imx6ul.dtsi @@ -425,7 +425,7 @@ status = "disabled"; }; - can1: flexcan@2090000 { + can1: can@2090000 { compatible = "fsl,imx6ul-flexcan", "fsl,imx6q-flexcan"; reg = <0x02090000 0x4000>; interrupts = ; @@ -436,7 +436,7 @@ status = "disabled"; }; - can2: flexcan@2094000 { + can2: can@2094000 { compatible = "fsl,imx6ul-flexcan", "fsl,imx6q-flexcan"; reg = <0x02094000 0x4000>; interrupts = ; diff --git a/arch/arm/boot/dts/vfxxx.dtsi b/arch/arm/boot/dts/vfxxx.dtsi index 0c8d15fd9253..d53f9c9db8bf 100644 --- a/arch/arm/boot/dts/vfxxx.dtsi +++ b/arch/arm/boot/dts/vfxxx.dtsi @@ -95,7 +95,7 @@ status = "disabled"; }; - can0: flexcan@40020000 { + can0: can@40020000 { compatible = "fsl,vf610-flexcan"; reg = <0x40020000 0x4000>; interrupts = <58 IRQ_TYPE_LEVEL_HIGH>; @@ -681,7 +681,7 @@ status = "disabled"; }; - can1: flexcan@400d4000 { + can1: can@400d4000 { compatible = "fsl,vf610-flexcan"; reg = <0x400d4000 0x4000>; interrupts = <59 IRQ_TYPE_LEVEL_HIGH>; -- cgit v1.2.3-59-g8ed1b From b9639a8b5ef1fa90fc0152db15588a9fe601c4b0 Mon Sep 17 00:00:00 2001 From: Jonathan Neuschäfer Date: Fri, 13 Nov 2020 00:30:54 +0100 Subject: ARM: dts: imx50-kobo-aura: Enable eKTF2132 touchscreen MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The Kobo Aura has an eKTF2132 touchscreen controller. Although the vendor kernel toggles a reset pin (GPIO5-12) during the startup sequence, the touchscreen works without it. Signed-off-by: Jonathan Neuschäfer Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx50-kobo-aura.dts | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx50-kobo-aura.dts b/arch/arm/boot/dts/imx50-kobo-aura.dts index 53b3995d37e7..97cfd970fe74 100644 --- a/arch/arm/boot/dts/imx50-kobo-aura.dts +++ b/arch/arm/boot/dts/imx50-kobo-aura.dts @@ -6,6 +6,7 @@ /dts-v1/; #include "imx50.dtsi" #include +#include / { model = "Kobo Aura (N514)"; @@ -119,7 +120,14 @@ pinctrl-0 = <&pinctrl_i2c1>; status = "okay"; - /* TODO: ektf2132 touch controller at 0x15 */ + touchscreen@15 { + reg = <0x15>; + compatible = "elan,ektf2132"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ts>; + power-gpios = <&gpio4 9 GPIO_ACTIVE_HIGH>; + interrupts-extended = <&gpio5 13 IRQ_TYPE_EDGE_FALLING>; + }; }; &i2c2 { @@ -225,6 +233,13 @@ >; }; + pinctrl_ts: tsgrp { + fsl,pins = < + MX50_PAD_CSPI_MOSI__GPIO4_9 0x0 + MX50_PAD_SD2_D5__GPIO5_13 0x0 + >; + }; + pinctrl_uart2: uart2grp { fsl,pins = < MX50_PAD_UART2_TXD__UART2_TXD_MUX 0x1e4 -- cgit v1.2.3-59-g8ed1b From a82820fcd079e38309403f595f005a8cc318a13c Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Fri, 11 Sep 2020 07:31:57 -0500 Subject: ARM: omap2plus_defconfig: Enable OMAP3_THERMAL With the additional power management options enabled, this patch enables OMAP3_THERMAL by default. Signed-off-by: Adam Ford Signed-off-by: Tony Lindgren --- arch/arm/configs/omap2plus_defconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm') diff --git a/arch/arm/configs/omap2plus_defconfig b/arch/arm/configs/omap2plus_defconfig index 34793aabdb65..4bdaa9dd41fe 100644 --- a/arch/arm/configs/omap2plus_defconfig +++ b/arch/arm/configs/omap2plus_defconfig @@ -314,6 +314,7 @@ CONFIG_THERMAL_GOV_FAIR_SHARE=y CONFIG_THERMAL_GOV_USER_SPACE=y CONFIG_CPU_THERMAL=y CONFIG_TI_THERMAL=y +CONFIG_OMAP3_THERMAL=y CONFIG_OMAP4_THERMAL=y CONFIG_OMAP5_THERMAL=y CONFIG_DRA752_THERMAL=y -- cgit v1.2.3-59-g8ed1b From a6b2a18060f6b351752fa748a904f46b94edec00 Mon Sep 17 00:00:00 2001 From: Carl Philipp Klemm Date: Sun, 8 Nov 2020 19:53:20 +0100 Subject: ARM: omap2plus_defconfig: add CONFIG_AK8975=m and CONFIG_KXCJK1013=m ARM: omap2plus_defconfig: add CONFIG_AK8975=m and CONFIG_KXCJK1013=m to support motorola xt894's magnetometer and motorola xt875's accelerometer respectivly Signed-off-by: Carl Philipp Klemm [tony@atomide.com: shortened subject a bit] Signed-off-by: Tony Lindgren --- arch/arm/configs/omap2plus_defconfig | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/configs/omap2plus_defconfig b/arch/arm/configs/omap2plus_defconfig index 4bdaa9dd41fe..2ab9024cb6e3 100644 --- a/arch/arm/configs/omap2plus_defconfig +++ b/arch/arm/configs/omap2plus_defconfig @@ -525,6 +525,8 @@ CONFIG_TI_AM335X_ADC=m CONFIG_TWL4030_MADC=m CONFIG_SENSORS_ISL29028=m CONFIG_BMP280=m +CONFIG_KXCJK1013=m +CONFIG_AK8975=m CONFIG_PWM=y CONFIG_PWM_OMAP_DMTIMER=m CONFIG_PWM_TIECAP=m -- cgit v1.2.3-59-g8ed1b From 9261c5b2f51996e7d4e10089f73ea472ae9e996f Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Mon, 16 Nov 2020 12:57:13 +0200 Subject: ARM: OMAP2+: Check for inited flag If we have no hwmods configured and omap_hwmod_init() is not called, we don't want to call omap_hwmod_setup_all() as it will fail with checks for configured MPU at least. Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/omap_hwmod.c | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c index 15b29a179c8a..2310cd56e99b 100644 --- a/arch/arm/mach-omap2/omap_hwmod.c +++ b/arch/arm/mach-omap2/omap_hwmod.c @@ -627,6 +627,9 @@ static struct clockdomain *_get_clkdm(struct omap_hwmod *oh) { struct clk_hw_omap *clk; + if (!oh) + return NULL; + if (oh->clkdm) { return oh->clkdm; } else if (oh->_clk) { @@ -3677,6 +3680,9 @@ static void __init omap_hwmod_setup_earlycon_flags(void) */ static int __init omap_hwmod_setup_all(void) { + if (!inited) + return 0; + _ensure_mpu_hwmod_is_setup(NULL); omap_hwmod_for_each(_init, NULL); -- cgit v1.2.3-59-g8ed1b From ae5f70f707889dfd056905d9ea69e3f72dace213 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Mon, 16 Nov 2020 12:57:13 +0200 Subject: ARM: OMAP2+: Probe PRCM first to probe l4_wkup with simple-pm-bus In preparation for probing the interconnects with simple-pm-bus to make use of genpd, we need to probe the always-on PRCM first for the clocks needed by l4_wkup instance. Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/pdata-quirks.c | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/mach-omap2/pdata-quirks.c b/arch/arm/mach-omap2/pdata-quirks.c index 2a4fe3e68b82..6c925056b800 100644 --- a/arch/arm/mach-omap2/pdata-quirks.c +++ b/arch/arm/mach-omap2/pdata-quirks.c @@ -580,6 +580,8 @@ static void pdata_quirks_check(struct pdata_init *quirks) void __init pdata_quirks_init(const struct of_device_id *omap_dt_match_table) { + struct device_node *np; + /* * We still need this for omap2420 and omap3 PM to work, others are * using drivers/misc/sram.c already. @@ -591,6 +593,15 @@ void __init pdata_quirks_init(const struct of_device_id *omap_dt_match_table) if (of_machine_is_compatible("ti,omap3")) omap3_mcbsp_init(); pdata_quirks_check(auxdata_quirks); + + /* Populate always-on PRCM in l4_wkup to probe l4_wkup */ + np = of_find_node_by_name(NULL, "prcm"); + if (!np) + np = of_find_node_by_name(NULL, "prm"); + if (np) + of_platform_populate(np, omap_dt_match_table, + omap_auxdata_lookup, NULL); + of_platform_populate(NULL, omap_dt_match_table, omap_auxdata_lookup, NULL); pdata_quirks_check(pdata_quirks); -- cgit v1.2.3-59-g8ed1b From 1041b2d0ca22e3e57f9f8393c28134419c92eb5c Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Mon, 16 Nov 2020 12:57:13 +0200 Subject: ARM: dts: am33xx: add remaining PRM instances Add remaining PRM instances for the am33xx SoC. Additionally, enable the genpd support for them. Signed-off-by: Tero Kristo [tony@atomide.com: fixed a typo for #power-domain-cells] Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am33xx.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi index 4c2298024137..8214feae0173 100644 --- a/arch/arm/boot/dts/am33xx.dtsi +++ b/arch/arm/boot/dts/am33xx.dtsi @@ -601,12 +601,20 @@ compatible = "ti,am3-prm-inst", "ti,omap-prm-inst"; reg = <0xc00 0x100>; #reset-cells = <1>; + #power-domain-cells = <0>; }; prm_wkup: prm@d00 { compatible = "ti,am3-prm-inst", "ti,omap-prm-inst"; reg = <0xd00 0x100>; #reset-cells = <1>; + #power-domain-cells = <0>; + }; + + prm_mpu: prm@e00 { + compatible = "ti,am3-prm-inst", "ti,omap-prm-inst"; + reg = <0xe00 0x100>; + #power-domain-cells = <0>; }; prm_device: prm@f00 { @@ -615,12 +623,24 @@ #reset-cells = <1>; }; + prm_rtc: prm@1000 { + compatible = "ti,am3-prm-inst", "ti,omap-prm-inst"; + reg = <0x1000 0x100>; + #power-domain-cells = <0>; + }; + prm_gfx: prm@1100 { compatible = "ti,am3-prm-inst", "ti,omap-prm-inst"; reg = <0x1100 0x100>; #power-domain-cells = <0>; #reset-cells = <1>; }; + + prm_cefuse: prm@1200 { + compatible = "ti,am3-prm-inst", "ti,omap-prm-inst"; + reg = <0x1200 0x100>; + #power-domain-cells = <0>; + }; }; /* Preferred always-on timer for clocksource */ -- cgit v1.2.3-59-g8ed1b From b7427dc49fcc8dfa95502f8c8e009738d4906d4e Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Mon, 16 Nov 2020 12:57:13 +0200 Subject: ARM: dts: Configure also interconnect clocks for am4 system timer We now manage clocksource and clockevent clocks directly with timer-ti-dm-systimer. In order to use genpd with prm_omap, GENPD_FLAG_PM_CLK and simple-pm-bus, we need to keep the system timer related interconnect clocks enabled until clocksource suspend is done. Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am33xx.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi index 8214feae0173..c777a865b5d2 100644 --- a/arch/arm/boot/dts/am33xx.dtsi +++ b/arch/arm/boot/dts/am33xx.dtsi @@ -645,6 +645,9 @@ /* Preferred always-on timer for clocksource */ &timer1_target { + clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_TIMER1_CLKCTRL 0>, + <&l4_wkup_clkctrl AM3_L4_WKUP_L4_WKUP_CLKCTRL 0>; + clock-names = "fck", "ick"; ti,no-reset-on-init; ti,no-idle; timer@0 { @@ -655,6 +658,9 @@ /* Preferred timer for clockevent */ &timer2_target { + clocks = <&l4ls_clkctrl AM3_L4LS_TIMER2_CLKCTRL 0>, + <&l4ls_clkctrl AM3_L4LS_L4_LS_CLKCTRL 0>; + clock-names = "fck", "ick"; ti,no-reset-on-init; ti,no-idle; timer@0 { -- cgit v1.2.3-59-g8ed1b From 6bcc5f9989402e30347e72e22ec0bc22844c5824 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Mon, 16 Nov 2020 12:57:13 +0200 Subject: ARM: OMAP2+: Drop legacy platform data for am3 control module We can now probe devices with ti-sysc interconnect driver and dts data. Let's drop the related platform data and custom ti,hwmods dts property. To drop the legacy platform data for am3 control module, we need to configure the missing functional clock and tag the module to not idle as platform data also had it configured with HWMOD_INIT_NO_IDLE. Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am33xx-l4.dtsi | 3 +++ arch/arm/mach-omap2/omap_hwmod_33xx_data.c | 24 ------------------------ 2 files changed, 3 insertions(+), 24 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/am33xx-l4.dtsi b/arch/arm/boot/dts/am33xx-l4.dtsi index ea20e4bdf040..4e39ac4321c4 100644 --- a/arch/arm/boot/dts/am33xx-l4.dtsi +++ b/arch/arm/boot/dts/am33xx-l4.dtsi @@ -274,6 +274,9 @@ compatible = "ti,sysc-omap4", "ti,sysc"; reg = <0x10000 0x4>; reg-names = "rev"; + clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_CONTROL_CLKCTRL 0>; + clock-names = "fck"; + ti,no-idle; #address-cells = <1>; #size-cells = <1>; ranges = <0x00000000 0x00010000 0x00010000>, diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c index b232f6ca6fe3..8d890df54f7c 100644 --- a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c @@ -182,21 +182,6 @@ static struct omap_hwmod am33xx_debugss_hwmod = { .opt_clks_cnt = ARRAY_SIZE(debugss_opt_clks), }; -static struct omap_hwmod am33xx_control_hwmod = { - .name = "control", - .class = &am33xx_control_hwmod_class, - .clkdm_name = "l4_wkup_clkdm", - .flags = HWMOD_INIT_NO_IDLE, - .main_clk = "dpll_core_m4_div2_ck", - .prcm = { - .omap4 = { - .clkctrl_offs = AM33XX_CM_WKUP_CONTROL_CLKCTRL_OFFSET, - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - - /* * Interfaces */ @@ -257,14 +242,6 @@ static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex1 = { .user = OCP_USER_MPU, }; -/* l4 wkup -> control */ -static struct omap_hwmod_ocp_if am33xx_l4_wkup__control = { - .master = &am33xx_l4_wkup_hwmod, - .slave = &am33xx_control_hwmod, - .clk = "dpll_core_m4_div2_ck", - .user = OCP_USER_MPU, -}; - static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = { &am33xx_l3_main__emif, &am33xx_mpu__l3_main, @@ -278,7 +255,6 @@ static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = { &am33xx_wkup_m3__l4_wkup, &am33xx_l3_main__debugss, &am33xx_l4_wkup__wkup_m3, - &am33xx_l4_wkup__control, &am33xx_l4_wkup__smartreflex0, &am33xx_l4_wkup__smartreflex1, &am33xx_l3_s__gpmc, -- cgit v1.2.3-59-g8ed1b From bfbad30690195996774ed2ddc8a55fb32cce0de0 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Mon, 16 Nov 2020 12:57:13 +0200 Subject: ARM: dts: Configure RTC powerdomain for am3 For genpd we need the RTC powerdomain configured. Cc: Dave Gerlach Cc: Suman Anna Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am33xx-l4.dtsi | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/am33xx-l4.dtsi b/arch/arm/boot/dts/am33xx-l4.dtsi index 4e39ac4321c4..ddfb27d38dff 100644 --- a/arch/arm/boot/dts/am33xx-l4.dtsi +++ b/arch/arm/boot/dts/am33xx-l4.dtsi @@ -436,6 +436,7 @@ , ; /* Domains (P, C): rtc_pwrdm, l4_rtc_clkdm */ + power-domains = <&prm_rtc>; clocks = <&l4_rtc_clkctrl AM3_L4_RTC_RTC_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; -- cgit v1.2.3-59-g8ed1b From b2304c5b0cf347b688694ac63a2bc434709beed2 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Mon, 16 Nov 2020 12:57:13 +0200 Subject: ARM: dts: Configure interconnect target module for am3 wkup_m3 We can now probe devices with device tree only configuration using ti-sysc interconnect target module driver. Note that we no longer need ti,no-reset-on-init as the rstctrl resets are properly handled by the reset driver and claimed by the RTC driver. And we need to squash together the module ranges for driver compability. Cc: Dave Gerlach Cc: Suman Anna Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am33xx-l4.dtsi | 23 ++++++++++++++--------- arch/arm/boot/dts/am33xx.dtsi | 8 -------- 2 files changed, 14 insertions(+), 17 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/am33xx-l4.dtsi b/arch/arm/boot/dts/am33xx-l4.dtsi index ddfb27d38dff..7fa2312b13e8 100644 --- a/arch/arm/boot/dts/am33xx-l4.dtsi +++ b/arch/arm/boot/dts/am33xx-l4.dtsi @@ -32,20 +32,25 @@ target-module@0 { /* 0x44d00000, ap 4 28.0 */ compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "wkup_m3"; reg = <0x0 0x4>; reg-names = "rev"; + clocks = <&l4_wkup_aon_clkctrl AM3_L4_WKUP_AON_WKUP_M3_CLKCTRL 0>; + clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; - ranges = <0x0 0x0 0x4000>; - status = "disabled"; - }; + ranges = <0x00000000 0x00000000 0x4000>, + <0x00080000 0x00080000 0x2000>; - target-module@80000 { /* 0x44d80000, ap 6 10.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x80000 0x2000>; + wkup_m3: cpu@0 { + compatible = "ti,am3352-wkup-m3"; + reg = <0x00000000 0x4000>, + <0x00080000 0x2000>; + reg-names = "umem", "dmem"; + resets = <&prm_wkup 3>; + reset-names = "rstctrl"; + ti,pm-firmware = "am335x-pm-firmware.elf"; + }; }; }; diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi index c777a865b5d2..fe9cdd2c0996 100644 --- a/arch/arm/boot/dts/am33xx.dtsi +++ b/arch/arm/boot/dts/am33xx.dtsi @@ -180,14 +180,6 @@ ti,hwmods = "l3_main"; l4_wkup: interconnect@44c00000 { - wkup_m3: wkup_m3@100000 { - compatible = "ti,am3352-wkup-m3"; - reg = <0x100000 0x4000>, - <0x180000 0x2000>; - reg-names = "umem", "dmem"; - ti,hwmods = "wkup_m3"; - ti,pm-firmware = "am335x-pm-firmware.elf"; - }; }; l4_per: interconnect@48000000 { }; -- cgit v1.2.3-59-g8ed1b From 3856e86f86d6793fcf1e30fbc2976a61ca816737 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Mon, 16 Nov 2020 12:57:13 +0200 Subject: ARM: OMAP2+: Drop legacy platform data for am3 wkup_m3 We can now probe devices with ti-sysc interconnect driver and dts data. Let's drop the related platform data and custom ti,hwmods dts property. As we're just dropping data, and the early platform data init is based on the custom ti,hwmods property, we want to drop both the platform data and ti,hwmods property in a single patch. Cc: Dave Gerlach Cc: Suman Anna Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am33xx-l4.dtsi | 1 - arch/arm/mach-omap2/omap_hwmod_33xx_data.c | 43 ------------------------------ 2 files changed, 44 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/am33xx-l4.dtsi b/arch/arm/boot/dts/am33xx-l4.dtsi index 7fa2312b13e8..3d8d260eb4f7 100644 --- a/arch/arm/boot/dts/am33xx-l4.dtsi +++ b/arch/arm/boot/dts/am33xx-l4.dtsi @@ -32,7 +32,6 @@ target-module@0 { /* 0x44d00000, ap 4 28.0 */ compatible = "ti,sysc-omap4", "ti,sysc"; - ti,hwmods = "wkup_m3"; reg = <0x0 0x4>; reg-names = "rev"; clocks = <&l4_wkup_aon_clkctrl AM3_L4_WKUP_AON_WKUP_M3_CLKCTRL 0>; diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c index 8d890df54f7c..0961275230d1 100644 --- a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c @@ -57,31 +57,6 @@ static struct omap_hwmod am33xx_l4_hs_hwmod = { }, }; -static struct omap_hwmod_rst_info am33xx_wkup_m3_resets[] = { - { .name = "wkup_m3", .rst_shift = 3, .st_shift = 5 }, -}; - -/* wkup_m3 */ -static struct omap_hwmod am33xx_wkup_m3_hwmod = { - .name = "wkup_m3", - .class = &am33xx_wkup_m3_hwmod_class, - .clkdm_name = "l4_wkup_aon_clkdm", - /* Keep hardreset asserted */ - .flags = HWMOD_INIT_NO_RESET | HWMOD_NO_IDLEST, - .main_clk = "dpll_core_m4_div2_ck", - .prcm = { - .omap4 = { - .clkctrl_offs = AM33XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET, - .rstctrl_offs = AM33XX_RM_WKUP_RSTCTRL_OFFSET, - .rstst_offs = AM33XX_RM_WKUP_RSTST_OFFSET, - .modulemode = MODULEMODE_SWCTRL, - }, - }, - .rst_lines = am33xx_wkup_m3_resets, - .rst_lines_cnt = ARRAY_SIZE(am33xx_wkup_m3_resets), -}; - - /* * Modules omap_hwmod structures * @@ -202,22 +177,6 @@ static struct omap_hwmod_ocp_if am33xx_l3_main__l4_hs = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; -/* wkup m3 -> l4 wkup */ -static struct omap_hwmod_ocp_if am33xx_wkup_m3__l4_wkup = { - .master = &am33xx_wkup_m3_hwmod, - .slave = &am33xx_l4_wkup_hwmod, - .clk = "dpll_core_m4_div2_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4 wkup -> wkup m3 */ -static struct omap_hwmod_ocp_if am33xx_l4_wkup__wkup_m3 = { - .master = &am33xx_l4_wkup_hwmod, - .slave = &am33xx_wkup_m3_hwmod, - .clk = "dpll_core_m4_div2_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - /* l3_main -> debugss */ static struct omap_hwmod_ocp_if am33xx_l3_main__debugss = { .master = &am33xx_l3_main_hwmod, @@ -252,9 +211,7 @@ static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = { &am33xx_l3_main__l3_s, &am33xx_l3_main__l3_instr, &am33xx_l3_s__l3_main, - &am33xx_wkup_m3__l4_wkup, &am33xx_l3_main__debugss, - &am33xx_l4_wkup__wkup_m3, &am33xx_l4_wkup__smartreflex0, &am33xx_l4_wkup__smartreflex1, &am33xx_l3_s__gpmc, -- cgit v1.2.3-59-g8ed1b From df7f2f95042850bfd890afec41e0dbe3de8ae1bd Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Mon, 16 Nov 2020 12:57:13 +0200 Subject: ARM: OMAP2+: Drop legacy platform data for am3 and am4 gpmc We can now probe devices with ti-sysc interconnect driver and dts data. Let's drop the related platform data and custom ti,hwmods dts property. As we're just dropping data, and the early platform data init is based on the custom ti,hwmods property, we want to drop both the platform data and ti,hwmods property in a single patch. Cc: Roger Quadros Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am335x-nano.dts | 1 - arch/arm/boot/dts/am33xx.dtsi | 48 ++++++++++++++------- arch/arm/boot/dts/am4372.dtsi | 49 +++++++++++++++------- .../mach-omap2/omap_hwmod_33xx_43xx_common_data.h | 2 - .../omap_hwmod_33xx_43xx_interconnect_data.c | 8 ---- .../mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c | 33 --------------- arch/arm/mach-omap2/omap_hwmod_33xx_data.c | 1 - arch/arm/mach-omap2/omap_hwmod_43xx_data.c | 1 - 8 files changed, 65 insertions(+), 78 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/am335x-nano.dts b/arch/arm/boot/dts/am335x-nano.dts index 0946fbf1b1fb..0dbc72d726c9 100644 --- a/arch/arm/boot/dts/am335x-nano.dts +++ b/arch/arm/boot/dts/am335x-nano.dts @@ -238,7 +238,6 @@ &gpmc { compatible = "ti,am3352-gpmc"; - ti,hwmods = "gpmc"; status = "okay"; gpmc,num-waitpins = <2>; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi index fe9cdd2c0996..d055002d48d7 100644 --- a/arch/arm/boot/dts/am33xx.dtsi +++ b/arch/arm/boot/dts/am33xx.dtsi @@ -480,23 +480,39 @@ ti,no-idle; }; - gpmc: gpmc@50000000 { - compatible = "ti,am3352-gpmc"; - ti,hwmods = "gpmc"; - ti,no-idle-on-init; - reg = <0x50000000 0x2000>; - interrupts = <100>; - dmas = <&edma 52 0>; - dma-names = "rxtx"; - gpmc,num-cs = <7>; - gpmc,num-waitpins = <2>; - #address-cells = <2>; + target-module@50000000 { + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x50000000 4>, + <0x50000010 4>, + <0x50000014 4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-sidle = , + , + ; + ti,syss-mask = <1>; + clocks = <&l3s_clkctrl AM3_L3S_GPMC_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; #size-cells = <1>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-controller; - #gpio-cells = <2>; - status = "disabled"; + ranges = <0x50000000 0x50000000 0x00001000>, /* regs */ + <0x00000000 0x00000000 0x40000000>; /* data */ + + gpmc: gpmc@50000000 { + compatible = "ti,am3352-gpmc"; + reg = <0x50000000 0x2000>; + interrupts = <100>; + dmas = <&edma 52 0>; + dma-names = "rxtx"; + gpmc,num-cs = <7>; + gpmc,num-waitpins = <2>; + #address-cells = <2>; + #size-cells = <1>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + status = "disabled"; + }; }; sham_target: target-module@53100000 { diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi index 878406b120be..8844526577dd 100644 --- a/arch/arm/boot/dts/am4372.dtsi +++ b/arch/arm/boot/dts/am4372.dtsi @@ -434,24 +434,41 @@ ranges = <0x0 0x54400000 0x80000>; }; - gpmc: gpmc@50000000 { - compatible = "ti,am3352-gpmc"; - ti,hwmods = "gpmc"; - dmas = <&edma 52 0>; - dma-names = "rxtx"; - clocks = <&l3s_gclk>; + target-module@50000000 { + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x50000000 4>, + <0x50000010 4>, + <0x50000014 4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-sidle = , + , + ; + ti,syss-mask = <1>; + clocks = <&l3s_clkctrl AM4_L3S_GPMC_CLKCTRL 0>; clock-names = "fck"; - reg = <0x50000000 0x2000>; - interrupts = ; - gpmc,num-cs = <7>; - gpmc,num-waitpins = <2>; - #address-cells = <2>; + #address-cells = <1>; #size-cells = <1>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-controller; - #gpio-cells = <2>; - status = "disabled"; + ranges = <0x50000000 0x50000000 0x00001000>, /* regs */ + <0x00000000 0x00000000 0x40000000>; /* data */ + + gpmc: gpmc@50000000 { + compatible = "ti,am3352-gpmc"; + dmas = <&edma 52 0>; + dma-names = "rxtx"; + clocks = <&l3s_gclk>; + clock-names = "fck"; + reg = <0x50000000 0x2000>; + interrupts = ; + gpmc,num-cs = <7>; + gpmc,num-waitpins = <2>; + #address-cells = <2>; + #size-cells = <1>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + status = "disabled"; + }; }; target-module@47900000 { diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_common_data.h b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_common_data.h index e29841072287..9aae558f6e9f 100644 --- a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_common_data.h +++ b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_common_data.h @@ -26,7 +26,6 @@ extern struct omap_hwmod_ocp_if am33xx_mpu__prcm; extern struct omap_hwmod_ocp_if am33xx_l3_s__l3_main; extern struct omap_hwmod_ocp_if am33xx_gfx__l3_main; extern struct omap_hwmod_ocp_if am33xx_l3_main__gfx; -extern struct omap_hwmod_ocp_if am33xx_l3_s__gpmc; extern struct omap_hwmod_ocp_if am33xx_l4_ls__timer2; extern struct omap_hwmod_ocp_if am33xx_l3_main__ocmc; @@ -41,7 +40,6 @@ extern struct omap_hwmod am33xx_prcm_hwmod; extern struct omap_hwmod am33xx_ocmcram_hwmod; extern struct omap_hwmod am33xx_smartreflex0_hwmod; extern struct omap_hwmod am33xx_smartreflex1_hwmod; -extern struct omap_hwmod am33xx_gpmc_hwmod; extern struct omap_hwmod_class am33xx_emif_hwmod_class; extern struct omap_hwmod_class am33xx_l4_hwmod_class; diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_interconnect_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_interconnect_data.c index ab5146bfe941..32741de0ed71 100644 --- a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_interconnect_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_interconnect_data.c @@ -74,14 +74,6 @@ struct omap_hwmod_ocp_if am33xx_l3_s__l3_main = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; -/* l3s cfg -> gpmc */ -struct omap_hwmod_ocp_if am33xx_l3_s__gpmc = { - .master = &am33xx_l3_s_hwmod, - .slave = &am33xx_gpmc_hwmod, - .clk = "l3s_gclk", - .user = OCP_USER_MPU, -}; - /* l3 main -> ocmc */ struct omap_hwmod_ocp_if am33xx_l3_main__ocmc = { .master = &am33xx_l3_main_hwmod, diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c index bcc120ed610a..a8a72a5474c6 100644 --- a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c @@ -218,44 +218,12 @@ struct omap_hwmod_class am33xx_control_hwmod_class = { .name = "control", }; - -/* gpmc */ -static struct omap_hwmod_class_sysconfig gpmc_sysc = { - .rev_offs = 0x0, - .sysc_offs = 0x10, - .syss_offs = 0x14, - .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE | - SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), - .sysc_fields = &omap_hwmod_sysc_type1, -}; - -static struct omap_hwmod_class am33xx_gpmc_hwmod_class = { - .name = "gpmc", - .sysc = &gpmc_sysc, -}; - -struct omap_hwmod am33xx_gpmc_hwmod = { - .name = "gpmc", - .class = &am33xx_gpmc_hwmod_class, - .clkdm_name = "l3s_clkdm", - /* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */ - .flags = DEBUG_OMAP_GPMC_HWMOD_FLAGS, - .main_clk = "l3s_gclk", - .prcm = { - .omap4 = { - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - static void omap_hwmod_am33xx_clkctrl(void) { CLKCTRL(am33xx_smartreflex0_hwmod, AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET); CLKCTRL(am33xx_smartreflex1_hwmod, AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET); - CLKCTRL(am33xx_gpmc_hwmod, AM33XX_CM_PER_GPMC_CLKCTRL_OFFSET); CLKCTRL(am33xx_l4_ls_hwmod, AM33XX_CM_PER_L4LS_CLKCTRL_OFFSET); CLKCTRL(am33xx_l4_wkup_hwmod, AM33XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET); CLKCTRL(am33xx_l3_main_hwmod, AM33XX_CM_PER_L3_CLKCTRL_OFFSET); @@ -275,7 +243,6 @@ static void omap_hwmod_am43xx_clkctrl(void) AM43XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET); CLKCTRL(am33xx_smartreflex1_hwmod, AM43XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET); - CLKCTRL(am33xx_gpmc_hwmod, AM43XX_CM_PER_GPMC_CLKCTRL_OFFSET); CLKCTRL(am33xx_l4_ls_hwmod, AM43XX_CM_PER_L4LS_CLKCTRL_OFFSET); CLKCTRL(am33xx_l4_wkup_hwmod, AM43XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET); CLKCTRL(am33xx_l3_main_hwmod, AM43XX_CM_PER_L3_CLKCTRL_OFFSET); diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c index 0961275230d1..7ef7fdb55381 100644 --- a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c @@ -214,7 +214,6 @@ static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = { &am33xx_l3_main__debugss, &am33xx_l4_wkup__smartreflex0, &am33xx_l4_wkup__smartreflex1, - &am33xx_l3_s__gpmc, &am33xx_l3_main__ocmc, NULL, }; diff --git a/arch/arm/mach-omap2/omap_hwmod_43xx_data.c b/arch/arm/mach-omap2/omap_hwmod_43xx_data.c index b97cb745bbbc..6ccdf57041b1 100644 --- a/arch/arm/mach-omap2/omap_hwmod_43xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_43xx_data.c @@ -150,7 +150,6 @@ static struct omap_hwmod_ocp_if *am43xx_hwmod_ocp_ifs[] __initdata = { &am43xx_l4_wkup__control, &am43xx_l4_wkup__smartreflex0, &am43xx_l4_wkup__smartreflex1, - &am33xx_l3_s__gpmc, &am33xx_l3_main__ocmc, NULL, }; -- cgit v1.2.3-59-g8ed1b From e990ebae4c27bc5bd06bbfefffa9564dc4f2417a Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Mon, 16 Nov 2020 12:57:13 +0200 Subject: ARM: OMAP2+: Drop legacy platform data for am3 debugss We can now probe devices with ti-sysc interconnect driver and dts data. Let's drop the related platform data and custom ti,hwmods dts property. Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am33xx.dtsi | 19 +++++++++++---- arch/arm/mach-omap2/omap_hwmod_33xx_data.c | 37 ------------------------------ 2 files changed, 14 insertions(+), 42 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi index d055002d48d7..87e591c18b32 100644 --- a/arch/arm/boot/dts/am33xx.dtsi +++ b/arch/arm/boot/dts/am33xx.dtsi @@ -144,11 +144,20 @@ }; }; - pmu@4b000000 { - compatible = "arm,cortex-a8-pmu"; - interrupts = <3>; - reg = <0x4b000000 0x1000000>; - ti,hwmods = "debugss"; + target-module@4b000000 { + compatible = "ti,sysc-omap4-simple", "ti,sysc"; + clocks = <&l3_aon_clkctrl AM3_L3_AON_DEBUGSS_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x4b000000 0x1000000>; + + pmu@0 { + compatible = "arm,cortex-a8-pmu"; + interrupts = <3>; + reg = <0 0x1000000>; + ti,hwmods = "debugss"; + }; }; /* diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c index 7ef7fdb55381..a8e5ccad3fd7 100644 --- a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c @@ -129,34 +129,6 @@ static struct omap_hwmod am33xx_ocpwp_hwmod = { }; #endif -/* - * 'debugss' class - * debug sub system - */ -static struct omap_hwmod_opt_clk debugss_opt_clks[] = { - { .role = "dbg_sysclk", .clk = "dbg_sysclk_ck" }, - { .role = "dbg_clka", .clk = "dbg_clka_ck" }, -}; - -static struct omap_hwmod_class am33xx_debugss_hwmod_class = { - .name = "debugss", -}; - -static struct omap_hwmod am33xx_debugss_hwmod = { - .name = "debugss", - .class = &am33xx_debugss_hwmod_class, - .clkdm_name = "l3_aon_clkdm", - .main_clk = "trace_clk_div_ck", - .prcm = { - .omap4 = { - .clkctrl_offs = AM33XX_CM_WKUP_DEBUGSS_CLKCTRL_OFFSET, - .modulemode = MODULEMODE_SWCTRL, - }, - }, - .opt_clks = debugss_opt_clks, - .opt_clks_cnt = ARRAY_SIZE(debugss_opt_clks), -}; - /* * Interfaces */ @@ -177,14 +149,6 @@ static struct omap_hwmod_ocp_if am33xx_l3_main__l4_hs = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; -/* l3_main -> debugss */ -static struct omap_hwmod_ocp_if am33xx_l3_main__debugss = { - .master = &am33xx_l3_main_hwmod, - .slave = &am33xx_debugss_hwmod, - .clk = "dpll_core_m4_ck", - .user = OCP_USER_MPU, -}; - /* l4 wkup -> smartreflex0 */ static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex0 = { .master = &am33xx_l4_wkup_hwmod, @@ -211,7 +175,6 @@ static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = { &am33xx_l3_main__l3_s, &am33xx_l3_main__l3_instr, &am33xx_l3_s__l3_main, - &am33xx_l3_main__debugss, &am33xx_l4_wkup__smartreflex0, &am33xx_l4_wkup__smartreflex1, &am33xx_l3_main__ocmc, -- cgit v1.2.3-59-g8ed1b From 966c5e9f149fa1b1ee57b440fef3cd5405dfdd41 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Mon, 16 Nov 2020 12:57:13 +0200 Subject: ARM: OMAP2+: Drop legacy platform data for am3 emif We can now probe devices with ti-sysc interconnect driver and dts data. Let's drop the related platform data and custom ti,hwmods dts property. Cc: Dave Gerlach Cc: Suman Anna Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am33xx.dtsi | 24 +++++++++++++++++------- arch/arm/mach-omap2/omap_hwmod_33xx_data.c | 24 ------------------------ 2 files changed, 17 insertions(+), 31 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi index 87e591c18b32..f220d5624785 100644 --- a/arch/arm/boot/dts/am33xx.dtsi +++ b/arch/arm/boot/dts/am33xx.dtsi @@ -479,14 +479,24 @@ }; }; - emif: emif@4c000000 { - compatible = "ti,emif-am3352"; - reg = <0x4c000000 0x1000000>; - ti,hwmods = "emif"; - interrupts = <101>; - sram = <&pm_sram_code - &pm_sram_data>; + target-module@4c000000 { + compatible = "ti,sysc-omap4-simple", "ti,sysc"; + reg = <0x4c000000 0x4>; + reg-names = "rev"; + clocks = <&l3_clkctrl AM3_L3_EMIF_CLKCTRL 0>; + clock-names = "fck"; ti,no-idle; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x4c000000 0x1000000>; + + emif: emif@0 { + compatible = "ti,emif-am3352"; + reg = <0 0x1000000>; + interrupts = <101>; + sram = <&pm_sram_code + &pm_sram_data>; + }; }; target-module@50000000 { diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c index a8e5ccad3fd7..b64daae7b9db 100644 --- a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c @@ -27,21 +27,6 @@ * IP blocks */ -/* emif */ -static struct omap_hwmod am33xx_emif_hwmod = { - .name = "emif", - .class = &am33xx_emif_hwmod_class, - .clkdm_name = "l3_clkdm", - .flags = HWMOD_INIT_NO_IDLE, - .main_clk = "dpll_ddr_m2_div2_ck", - .prcm = { - .omap4 = { - .clkctrl_offs = AM33XX_CM_PER_EMIF_CLKCTRL_OFFSET, - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - /* l4_hs */ static struct omap_hwmod am33xx_l4_hs_hwmod = { .name = "l4_hs", @@ -133,14 +118,6 @@ static struct omap_hwmod am33xx_ocpwp_hwmod = { * Interfaces */ -/* l3 main -> emif */ -static struct omap_hwmod_ocp_if am33xx_l3_main__emif = { - .master = &am33xx_l3_main_hwmod, - .slave = &am33xx_emif_hwmod, - .clk = "dpll_core_m4_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - /* l3 main -> l4 hs */ static struct omap_hwmod_ocp_if am33xx_l3_main__l4_hs = { .master = &am33xx_l3_main_hwmod, @@ -166,7 +143,6 @@ static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex1 = { }; static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = { - &am33xx_l3_main__emif, &am33xx_mpu__l3_main, &am33xx_mpu__prcm, &am33xx_l3_s__l4_ls, -- cgit v1.2.3-59-g8ed1b From 2e5395684b213fd128f0e9fb0fa3d70cf5bfd4b1 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Mon, 16 Nov 2020 12:57:13 +0200 Subject: ARM: OMAP2+: Drop legacy platform data for am3 ocmcram We can now probe devices with ti-sysc interconnect driver and dts data. Let's drop the related platform data and custom ti,hwmods dts property. Note that we need to use "ti,no-idle" here. Cc: Dave Gerlach Cc: Suman Anna Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am33xx.dtsi | 36 ++++++++++++++-------- .../mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c | 1 - arch/arm/mach-omap2/omap_hwmod_33xx_data.c | 1 - 3 files changed, 23 insertions(+), 15 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi index f220d5624785..1d1cc858f46f 100644 --- a/arch/arm/boot/dts/am33xx.dtsi +++ b/arch/arm/boot/dts/am33xx.dtsi @@ -459,23 +459,33 @@ }; }; - ocmcram: sram@40300000 { - compatible = "mmio-sram"; - reg = <0x40300000 0x10000>; /* 64k */ - ranges = <0x0 0x40300000 0x10000>; + target-module@40300000 { + compatible = "ti,sysc-omap4-simple", "ti,sysc"; + clocks = <&l3_clkctrl AM3_L3_OCMCRAM_CLKCTRL 0>; + clock-names = "fck"; + ti,no-idle; #address-cells = <1>; #size-cells = <1>; + ranges = <0 0x40300000 0x10000>; - pm_sram_code: pm-code-sram@0 { - compatible = "ti,sram"; - reg = <0x0 0x1000>; - protect-exec; - }; + ocmcram: sram@0 { + compatible = "mmio-sram"; + reg = <0 0x10000>; /* 64k */ + ranges = <0 0 0x10000>; + #address-cells = <1>; + #size-cells = <1>; - pm_sram_data: pm-data-sram@1000 { - compatible = "ti,sram"; - reg = <0x1000 0x1000>; - pool; + pm_sram_code: pm-code-sram@0 { + compatible = "ti,sram"; + reg = <0x0 0x1000>; + protect-exec; + }; + + pm_sram_data: pm-data-sram@1000 { + compatible = "ti,sram"; + reg = <0x1000 0x1000>; + pool; + }; }; }; diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c index a8a72a5474c6..3efcba4ea0e5 100644 --- a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c @@ -229,7 +229,6 @@ static void omap_hwmod_am33xx_clkctrl(void) CLKCTRL(am33xx_l3_main_hwmod, AM33XX_CM_PER_L3_CLKCTRL_OFFSET); CLKCTRL(am33xx_mpu_hwmod , AM33XX_CM_MPU_MPU_CLKCTRL_OFFSET); CLKCTRL(am33xx_l3_instr_hwmod , AM33XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET); - CLKCTRL(am33xx_ocmcram_hwmod , AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET); } void omap_hwmod_am33xx_reg(void) diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c index b64daae7b9db..6c4b7d366b92 100644 --- a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c @@ -153,7 +153,6 @@ static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = { &am33xx_l3_s__l3_main, &am33xx_l4_wkup__smartreflex0, &am33xx_l4_wkup__smartreflex1, - &am33xx_l3_main__ocmc, NULL, }; -- cgit v1.2.3-59-g8ed1b From 675755705f08fb30164f2022fe30ee3b18d52bd4 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Mon, 16 Nov 2020 12:57:13 +0200 Subject: ARM: OMAP2+: Drop legacy platform data for am3 instr We can now probe devices with ti-sysc interconnect driver and dts data. Let's drop the related platform data and custom ti,hwmods dts property. Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am33xx.dtsi | 20 ++++++++++++++------ .../mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c | 1 - arch/arm/mach-omap2/omap_hwmod_33xx_data.c | 1 - 3 files changed, 14 insertions(+), 8 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi index 1d1cc858f46f..c540ba4e7f09 100644 --- a/arch/arm/boot/dts/am33xx.dtsi +++ b/arch/arm/boot/dts/am33xx.dtsi @@ -146,17 +146,25 @@ target-module@4b000000 { compatible = "ti,sysc-omap4-simple", "ti,sysc"; - clocks = <&l3_aon_clkctrl AM3_L3_AON_DEBUGSS_CLKCTRL 0>; + clocks = <&l3_clkctrl AM3_L3_L3_INSTR_CLKCTRL 0>; clock-names = "fck"; + ti,no-idle; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x4b000000 0x1000000>; - pmu@0 { - compatible = "arm,cortex-a8-pmu"; - interrupts = <3>; - reg = <0 0x1000000>; - ti,hwmods = "debugss"; + target-module@140000 { + compatible = "ti,sysc-omap4-simple", "ti,sysc"; + clocks = <&l3_aon_clkctrl AM3_L3_AON_DEBUGSS_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x140000 0xec0000>; + + pmu@0 { + compatible = "arm,cortex-a8-pmu"; + interrupts = <3>; + }; }; }; diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c index 3efcba4ea0e5..f0abdcc2f9e1 100644 --- a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c @@ -246,7 +246,6 @@ static void omap_hwmod_am43xx_clkctrl(void) CLKCTRL(am33xx_l4_wkup_hwmod, AM43XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET); CLKCTRL(am33xx_l3_main_hwmod, AM43XX_CM_PER_L3_CLKCTRL_OFFSET); CLKCTRL(am33xx_mpu_hwmod , AM43XX_CM_MPU_MPU_CLKCTRL_OFFSET); - CLKCTRL(am33xx_l3_instr_hwmod , AM43XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET); CLKCTRL(am33xx_ocmcram_hwmod , AM43XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET); } diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c index 6c4b7d366b92..5fd9b2560c98 100644 --- a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c @@ -149,7 +149,6 @@ static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = { &am33xx_l3_s__l4_wkup, &am33xx_l3_main__l4_hs, &am33xx_l3_main__l3_s, - &am33xx_l3_main__l3_instr, &am33xx_l3_s__l3_main, &am33xx_l4_wkup__smartreflex0, &am33xx_l4_wkup__smartreflex1, -- cgit v1.2.3-59-g8ed1b From b0625afe305253d0831af9289b37c906c18a781b Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Mon, 16 Nov 2020 12:57:13 +0200 Subject: ARM: OMAP2+: Drop legacy platform data for am3 mpuss We can now probe devices with ti-sysc interconnect driver and dts data. Let's drop the related platform data and custom ti,hwmods dts property. As we're just dropping data, and the early platform data init is based on the custom ti,hwmods property, we want to drop both the platform data and ti,hwmods property in a single patch. Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am33xx-l4.dtsi | 18 ++++++++++++++++++ arch/arm/boot/dts/am33xx.dtsi | 6 ------ .../arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c | 1 - arch/arm/mach-omap2/omap_hwmod_33xx_data.c | 2 -- 4 files changed, 18 insertions(+), 9 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/am33xx-l4.dtsi b/arch/arm/boot/dts/am33xx-l4.dtsi index 3d8d260eb4f7..5aef965b847f 100644 --- a/arch/arm/boot/dts/am33xx-l4.dtsi +++ b/arch/arm/boot/dts/am33xx-l4.dtsi @@ -1861,6 +1861,24 @@ compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; + ranges = <0x00000000 0x00200000 0x010000>; + + target-module@0 { + compatible = "ti,sysc-omap4-simple", "ti,sysc"; + power-domains = <&prm_mpu>; + clocks = <&mpu_clkctrl AM3_MPU_MPU_CLKCTRL 0>; + clock-names = "fck"; + ti,no-idle; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x10000>; + + mpu@0 { + compatible = "ti,omap3-mpu"; + pm-sram = <&pm_sram_code + &pm_sram_data>; + }; + }; }; segment@300000 { /* 0x48300000 */ diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi index c540ba4e7f09..bcdbc5bdc79a 100644 --- a/arch/arm/boot/dts/am33xx.dtsi +++ b/arch/arm/boot/dts/am33xx.dtsi @@ -174,12 +174,6 @@ */ soc { compatible = "ti,omap-infra"; - mpu { - compatible = "ti,omap3-mpu"; - ti,hwmods = "mpu"; - pm-sram = <&pm_sram_code - &pm_sram_data>; - }; }; /* diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c index f0abdcc2f9e1..a58d79a619c8 100644 --- a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c @@ -227,7 +227,6 @@ static void omap_hwmod_am33xx_clkctrl(void) CLKCTRL(am33xx_l4_ls_hwmod, AM33XX_CM_PER_L4LS_CLKCTRL_OFFSET); CLKCTRL(am33xx_l4_wkup_hwmod, AM33XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET); CLKCTRL(am33xx_l3_main_hwmod, AM33XX_CM_PER_L3_CLKCTRL_OFFSET); - CLKCTRL(am33xx_mpu_hwmod , AM33XX_CM_MPU_MPU_CLKCTRL_OFFSET); CLKCTRL(am33xx_l3_instr_hwmod , AM33XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET); } diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c index 5fd9b2560c98..ddc3b8d503fa 100644 --- a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c @@ -143,8 +143,6 @@ static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex1 = { }; static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = { - &am33xx_mpu__l3_main, - &am33xx_mpu__prcm, &am33xx_l3_s__l4_ls, &am33xx_l3_s__l4_wkup, &am33xx_l3_main__l4_hs, -- cgit v1.2.3-59-g8ed1b From 5a230524f87926f24d637fe62fd689f7f86f5036 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Mon, 16 Nov 2020 12:57:13 +0200 Subject: ARM: dts: Use simple-pm-bus for genpd for am3 l4_wkup We can now enable simple-pm-bus to use genpd. Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am33xx-l4.dtsi | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/am33xx-l4.dtsi b/arch/arm/boot/dts/am33xx-l4.dtsi index 5aef965b847f..9b1ac81281c6 100644 --- a/arch/arm/boot/dts/am33xx-l4.dtsi +++ b/arch/arm/boot/dts/am33xx-l4.dtsi @@ -1,5 +1,8 @@ &l4_wkup { /* 0x44c00000 */ - compatible = "ti,am33xx-l4-wkup", "simple-bus"; + compatible = "ti,am33xx-l4-wkup", "simple-pm-bus"; + power-domains = <&prm_wkup>; + clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_L4_WKUP_CLKCTRL 0>; + clock-names = "fck"; reg = <0x44c00000 0x800>, <0x44c00800 0x800>, <0x44c01000 0x400>, @@ -12,7 +15,7 @@ <0x00200000 0x44e00000 0x100000>; /* segment 2 */ segment@0 { /* 0x44c00000 */ - compatible = "simple-bus"; + compatible = "simple-pm-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ @@ -22,7 +25,7 @@ }; segment@100000 { /* 0x44d00000 */ - compatible = "simple-bus"; + compatible = "simple-pm-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x00000000 0x00100000 0x004000>, /* ap 4 */ @@ -54,7 +57,7 @@ }; segment@200000 { /* 0x44e00000 */ - compatible = "simple-bus"; + compatible = "simple-pm-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x00000000 0x00200000 0x002000>, /* ap 8 */ -- cgit v1.2.3-59-g8ed1b From ac1c14f51a8216764d6bb446def98092c7c95f1a Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Mon, 16 Nov 2020 12:57:13 +0200 Subject: ARM: dts: Use simple-pm-bus for genpd for am3 l4_fast We can now enable simple-pm-bus to use genpd. Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am33xx-l4.dtsi | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/am33xx-l4.dtsi b/arch/arm/boot/dts/am33xx-l4.dtsi index 9b1ac81281c6..38981411dc1b 100644 --- a/arch/arm/boot/dts/am33xx-l4.dtsi +++ b/arch/arm/boot/dts/am33xx-l4.dtsi @@ -669,7 +669,10 @@ }; &l4_fast { /* 0x4a000000 */ - compatible = "ti,am33xx-l4-fast", "simple-bus"; + compatible = "ti,am33xx-l4-fast", "simple-pm-bus"; + power-domains = <&prm_per>; + clocks = <&l4hs_clkctrl AM3_L4HS_L4_HS_CLKCTRL 0>; + clock-names = "fck"; reg = <0x4a000000 0x800>, <0x4a000800 0x800>, <0x4a001000 0x400>; @@ -679,7 +682,7 @@ ranges = <0x00000000 0x4a000000 0x1000000>; /* segment 0 */ segment@0 { /* 0x4a000000 */ - compatible = "simple-bus"; + compatible = "simple-pm-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ -- cgit v1.2.3-59-g8ed1b From 25ddbb2b88cf3e82a11cb3f661afec5e34d23eb5 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Mon, 16 Nov 2020 12:57:13 +0200 Subject: ARM: dts: Use simple-pm-bus for genpd for am3 l4_per We can now enable simple-pm-bus to use genpd. Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am33xx-l4.dtsi | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/am33xx-l4.dtsi b/arch/arm/boot/dts/am33xx-l4.dtsi index 38981411dc1b..78b5e88f869d 100644 --- a/arch/arm/boot/dts/am33xx-l4.dtsi +++ b/arch/arm/boot/dts/am33xx-l4.dtsi @@ -851,7 +851,10 @@ }; &l4_per { /* 0x48000000 */ - compatible = "ti,am33xx-l4-per", "simple-bus"; + compatible = "ti,am33xx-l4-per", "simple-pm-bus"; + power-domains = <&prm_per>; + clocks = <&l4ls_clkctrl AM3_L4LS_L4_LS_CLKCTRL 0>; + clock-names = "fck"; reg = <0x48000000 0x800>, <0x48000800 0x800>, <0x48001000 0x400>, @@ -869,7 +872,7 @@ <0x46400000 0x46400000 0x400000>; /* l3 data port */ segment@0 { /* 0x48000000 */ - compatible = "simple-bus"; + compatible = "simple-pm-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ @@ -1480,7 +1483,7 @@ }; segment@100000 { /* 0x48100000 */ - compatible = "simple-bus"; + compatible = "simple-pm-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0008c000 0x0018c000 0x001000>, /* ap 42 */ @@ -1864,7 +1867,7 @@ }; segment@200000 { /* 0x48200000 */ - compatible = "simple-bus"; + compatible = "simple-pm-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x00000000 0x00200000 0x010000>; @@ -1888,7 +1891,7 @@ }; segment@300000 { /* 0x48300000 */ - compatible = "simple-bus"; + compatible = "simple-pm-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x00000000 0x00300000 0x001000>, /* ap 66 */ -- cgit v1.2.3-59-g8ed1b From 472931c641dfa5f8cdb4f2a637e4afdf78dba63c Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Mon, 16 Nov 2020 12:57:13 +0200 Subject: ARM: dts: Use simple-pm-bus for genpd for am3 l3 We can now enable simple-pm-bus to use genpd. Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am33xx.dtsi | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi index bcdbc5bdc79a..5b213a1e68bb 100644 --- a/arch/arm/boot/dts/am33xx.dtsi +++ b/arch/arm/boot/dts/am33xx.dtsi @@ -184,11 +184,13 @@ * the whole bus hierarchy. */ ocp: ocp { - compatible = "simple-bus"; + compatible = "simple-pm-bus"; + power-domains = <&prm_per>; + clocks = <&l3_clkctrl AM3_L3_L3_MAIN_CLKCTRL 0>; + clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges; - ti,hwmods = "l3_main"; l4_wkup: interconnect@44c00000 { }; -- cgit v1.2.3-59-g8ed1b From 68fc5990b8be229274964a22547c7e078342bad1 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Mon, 16 Nov 2020 12:57:13 +0200 Subject: ARM: OMAP2+: Drop legacy remaining legacy platform data for am3 We can now drop the remaining legacy platform data as we are probing devices with device tree data. Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/Makefile | 1 - arch/arm/mach-omap2/io.c | 2 - arch/arm/mach-omap2/omap_hwmod_33xx_data.c | 161 ----------------------------- 3 files changed, 164 deletions(-) delete mode 100644 arch/arm/mach-omap2/omap_hwmod_33xx_data.c (limited to 'arch/arm') diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index 732e614c56b2..23644741840d 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -205,7 +205,6 @@ obj-$(CONFIG_SOC_OMAP2430) += omap_hwmod_2xxx_interconnect_data.o obj-$(CONFIG_SOC_OMAP2430) += omap_hwmod_2430_data.o obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_2xxx_3xxx_ipblock_data.o obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_3xxx_data.o -obj-$(CONFIG_SOC_AM33XX) += omap_hwmod_33xx_data.o obj-$(CONFIG_SOC_AM33XX) += omap_hwmod_33xx_43xx_interconnect_data.o obj-$(CONFIG_SOC_AM33XX) += omap_hwmod_33xx_43xx_ipblock_data.o obj-$(CONFIG_SOC_AM43XX) += omap_hwmod_43xx_data.o diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c index 27608d1026cb..a868b91ce90a 100644 --- a/arch/arm/mach-omap2/io.c +++ b/arch/arm/mach-omap2/io.c @@ -567,8 +567,6 @@ void __init am33xx_init_early(void) omap2_prcm_base_init(); am33xx_powerdomains_init(); am33xx_clockdomains_init(); - am33xx_hwmod_init(); - omap_hwmod_init_postsetup(); omap_clk_soc_init = am33xx_dt_clk_init; omap_secure_init(); } diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c deleted file mode 100644 index ddc3b8d503fa..000000000000 --- a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c +++ /dev/null @@ -1,161 +0,0 @@ -/* - * omap_hwmod_33xx_data.c: Hardware modules present on the AM33XX chips - * - * Copyright (C) {2012} Texas Instruments Incorporated - https://www.ti.com/ - * - * This file is automatically generated from the AM33XX hardware databases. - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation version 2. - * - * This program is distributed "as is" WITHOUT ANY WARRANTY of any - * kind, whether express or implied; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "omap_hwmod.h" -#include "omap_hwmod_common_data.h" - -#include "control.h" -#include "cm33xx.h" -#include "prm33xx.h" -#include "prm-regbits-33xx.h" -#include "omap_hwmod_33xx_43xx_common_data.h" - -/* - * IP blocks - */ - -/* l4_hs */ -static struct omap_hwmod am33xx_l4_hs_hwmod = { - .name = "l4_hs", - .class = &am33xx_l4_hwmod_class, - .clkdm_name = "l4hs_clkdm", - .flags = HWMOD_INIT_NO_IDLE, - .main_clk = "l4hs_gclk", - .prcm = { - .omap4 = { - .clkctrl_offs = AM33XX_CM_PER_L4HS_CLKCTRL_OFFSET, - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - -/* - * Modules omap_hwmod structures - * - * The following IPs are excluded for the moment because: - * - They do not need an explicit SW control using omap_hwmod API. - * - They still need to be validated with the driver - * properly adapted to omap_hwmod / omap_device - * - * - cEFUSE (doesn't fall under any ocp_if) - * - clkdiv32k - * - ocp watch point - */ -#if 0 -/* - * 'cefuse' class - */ -static struct omap_hwmod_class am33xx_cefuse_hwmod_class = { - .name = "cefuse", -}; - -static struct omap_hwmod am33xx_cefuse_hwmod = { - .name = "cefuse", - .class = &am33xx_cefuse_hwmod_class, - .clkdm_name = "l4_cefuse_clkdm", - .main_clk = "cefuse_fck", - .prcm = { - .omap4 = { - .clkctrl_offs = AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET, - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - -/* - * 'clkdiv32k' class - */ -static struct omap_hwmod_class am33xx_clkdiv32k_hwmod_class = { - .name = "clkdiv32k", -}; - -static struct omap_hwmod am33xx_clkdiv32k_hwmod = { - .name = "clkdiv32k", - .class = &am33xx_clkdiv32k_hwmod_class, - .clkdm_name = "clk_24mhz_clkdm", - .main_clk = "clkdiv32k_ick", - .prcm = { - .omap4 = { - .clkctrl_offs = AM33XX_CM_PER_CLKDIV32K_CLKCTRL_OFFSET, - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - -/* ocpwp */ -static struct omap_hwmod_class am33xx_ocpwp_hwmod_class = { - .name = "ocpwp", -}; - -static struct omap_hwmod am33xx_ocpwp_hwmod = { - .name = "ocpwp", - .class = &am33xx_ocpwp_hwmod_class, - .clkdm_name = "l4ls_clkdm", - .main_clk = "l4ls_gclk", - .prcm = { - .omap4 = { - .clkctrl_offs = AM33XX_CM_PER_OCPWP_CLKCTRL_OFFSET, - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; -#endif - -/* - * Interfaces - */ - -/* l3 main -> l4 hs */ -static struct omap_hwmod_ocp_if am33xx_l3_main__l4_hs = { - .master = &am33xx_l3_main_hwmod, - .slave = &am33xx_l4_hs_hwmod, - .clk = "l3s_gclk", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4 wkup -> smartreflex0 */ -static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex0 = { - .master = &am33xx_l4_wkup_hwmod, - .slave = &am33xx_smartreflex0_hwmod, - .clk = "dpll_core_m4_div2_ck", - .user = OCP_USER_MPU, -}; - -/* l4 wkup -> smartreflex1 */ -static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex1 = { - .master = &am33xx_l4_wkup_hwmod, - .slave = &am33xx_smartreflex1_hwmod, - .clk = "dpll_core_m4_div2_ck", - .user = OCP_USER_MPU, -}; - -static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = { - &am33xx_l3_s__l4_ls, - &am33xx_l3_s__l4_wkup, - &am33xx_l3_main__l4_hs, - &am33xx_l3_main__l3_s, - &am33xx_l3_s__l3_main, - &am33xx_l4_wkup__smartreflex0, - &am33xx_l4_wkup__smartreflex1, - NULL, -}; - -int __init am33xx_hwmod_init(void) -{ - omap_hwmod_am33xx_reg(); - omap_hwmod_init(); - return omap_hwmod_register_links(am33xx_hwmod_ocp_ifs); -} -- cgit v1.2.3-59-g8ed1b From 133ad7ab7005dc951fb66d3de9e29a8259fe9744 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Mon, 16 Nov 2020 12:57:13 +0200 Subject: ARM: OMAP2+: Build hwmod related code as needed If we have only am3 selected, there's no need to build the hwmod related code as we are probing devices with device tree data. Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/Kconfig | 9 +++++++++ arch/arm/mach-omap2/Makefile | 13 ++++++------- arch/arm/mach-omap2/pdata-quirks.c | 12 +++++++----- 3 files changed, 22 insertions(+), 12 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index 3f62a0c9450d..c7ef2e242f30 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig @@ -2,11 +2,15 @@ menu "TI OMAP/AM/DM/DRA Family" depends on ARCH_MULTI_V6 || ARCH_MULTI_V7 +config OMAP_HWMOD + bool + config ARCH_OMAP2 bool "TI OMAP2" depends on ARCH_MULTI_V6 select ARCH_OMAP2PLUS select CPU_V6 + select OMAP_HWMOD select SOC_HAS_OMAP2_SDRC config ARCH_OMAP3 @@ -14,6 +18,7 @@ config ARCH_OMAP3 depends on ARCH_MULTI_V7 select ARCH_OMAP2PLUS select ARM_CPU_SUSPEND if PM + select OMAP_HWMOD select OMAP_INTERCONNECT select PM_OPP if PM select PM if CPU_IDLE @@ -30,6 +35,7 @@ config ARCH_OMAP4 select ARM_GIC select HAVE_ARM_SCU if SMP select HAVE_ARM_TWD if SMP + select OMAP_HWMOD select OMAP_INTERCONNECT select OMAP_INTERCONNECT_BARRIER select PL310_ERRATA_588369 if CACHE_L2X0 @@ -49,6 +55,7 @@ config SOC_OMAP5 select HAVE_ARM_SCU if SMP select HAVE_ARM_ARCH_TIMER select ARM_ERRATA_798181 if SMP + select OMAP_HWMOD select OMAP_INTERCONNECT select OMAP_INTERCONNECT_BARRIER select PM_OPP if PM @@ -71,6 +78,7 @@ config SOC_AM43XX select HAVE_ARM_TWD select ARM_ERRATA_754322 select ARM_ERRATA_775420 + select OMAP_HWMOD select OMAP_INTERCONNECT select ARM_CPU_SUSPEND if PM @@ -84,6 +92,7 @@ config SOC_DRA7XX select HAVE_ARM_ARCH_TIMER select IRQ_CROSSBAR select ARM_ERRATA_798181 if SMP + select OMAP_HWMOD select OMAP_INTERCONNECT select OMAP_INTERCONNECT_BARRIER select PM_OPP if PM diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index 23644741840d..efd409ddceb5 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -8,18 +8,20 @@ ccflags-y := -I$(srctree)/$(src)/include \ # Common support obj-y := id.o io.o control.o devices.o fb.o pm.o \ - common.o dma.o wd_timer.o display.o i2c.o hdq1w.o omap_hwmod.o \ - omap_device.o omap-headsmp.o sram.o + common.o dma.o omap-headsmp.o sram.o hwmod-common = omap_hwmod.o omap_hwmod_reset.o \ - omap_hwmod_common_data.o + omap_hwmod_common_data.o \ + omap_hwmod_common_ipblock_data.o \ + omap_device.o display.o hdq1w.o \ + i2c.o wd_timer.o clock-common = clock.o secure-common = omap-smc.o omap-secure.o obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(hwmod-common) obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(hwmod-common) $(secure-common) obj-$(CONFIG_ARCH_OMAP4) += $(hwmod-common) $(secure-common) -obj-$(CONFIG_SOC_AM33XX) += $(hwmod-common) $(secure-common) +obj-$(CONFIG_SOC_AM33XX) += $(secure-common) obj-$(CONFIG_SOC_OMAP5) += $(hwmod-common) $(secure-common) obj-$(CONFIG_SOC_AM43XX) += $(hwmod-common) $(secure-common) obj-$(CONFIG_SOC_DRA7XX) += $(hwmod-common) $(secure-common) @@ -194,7 +196,6 @@ obj-$(CONFIG_SOC_OMAP2420) += opp2420_data.o obj-$(CONFIG_SOC_OMAP2430) += opp2430_data.o # hwmod data -obj-y += omap_hwmod_common_ipblock_data.o obj-$(CONFIG_SOC_OMAP2420) += omap_hwmod_2xxx_ipblock_data.o obj-$(CONFIG_SOC_OMAP2420) += omap_hwmod_2xxx_3xxx_ipblock_data.o obj-$(CONFIG_SOC_OMAP2420) += omap_hwmod_2xxx_interconnect_data.o @@ -205,8 +206,6 @@ obj-$(CONFIG_SOC_OMAP2430) += omap_hwmod_2xxx_interconnect_data.o obj-$(CONFIG_SOC_OMAP2430) += omap_hwmod_2430_data.o obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_2xxx_3xxx_ipblock_data.o obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_3xxx_data.o -obj-$(CONFIG_SOC_AM33XX) += omap_hwmod_33xx_43xx_interconnect_data.o -obj-$(CONFIG_SOC_AM33XX) += omap_hwmod_33xx_43xx_ipblock_data.o obj-$(CONFIG_SOC_AM43XX) += omap_hwmod_43xx_data.o obj-$(CONFIG_SOC_AM43XX) += omap_hwmod_33xx_43xx_interconnect_data.o obj-$(CONFIG_SOC_AM43XX) += omap_hwmod_33xx_43xx_ipblock_data.o diff --git a/arch/arm/mach-omap2/pdata-quirks.c b/arch/arm/mach-omap2/pdata-quirks.c index 6c925056b800..e707d29a5a12 100644 --- a/arch/arm/mach-omap2/pdata-quirks.c +++ b/arch/arm/mach-omap2/pdata-quirks.c @@ -94,6 +94,7 @@ static void __init hsmmc2_internal_input_clk(void) omap_ctrl_writel(reg, OMAP343X_CONTROL_DEVCONF1); } +#ifdef CONFIG_OMAP_HWMOD static struct iommu_platform_data omap3_iommu_pdata = { .reset_name = "mmu", .assert_reset = omap_device_assert_hardreset, @@ -106,6 +107,7 @@ static struct iommu_platform_data omap3_iommu_isp_pdata = { .device_enable = omap_device_enable, .device_idle = omap_device_idle, }; +#endif static int omap3_sbc_t3730_twl_callback(struct device *dev, unsigned gpio, @@ -272,7 +274,7 @@ static void __init omap3_pandora_legacy_init(void) } #endif /* CONFIG_ARCH_OMAP3 */ -#if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX) +#if defined(CONFIG_SOC_AM43XX) static struct wkup_m3_platform_data wkup_m3_data = { .reset_name = "wkup_m3", .assert_reset = omap_device_assert_hardreset, @@ -370,6 +372,7 @@ static void ti_sysc_clkdm_allow_idle(struct device *dev, clkdm_allow_idle(cookie->clkdm); } +#ifdef CONFIG_OMAP_HWMOD static int ti_sysc_enable_module(struct device *dev, const struct ti_sysc_cookie *cookie) { @@ -396,6 +399,7 @@ static int ti_sysc_shutdown_module(struct device *dev, return omap_hwmod_shutdown(cookie->data); } +#endif /* CONFIG_OMAP_HWMOD */ static bool ti_sysc_soc_type_gp(void) { @@ -410,10 +414,12 @@ static struct ti_sysc_platform_data ti_sysc_pdata = { .init_clockdomain = ti_sysc_clkdm_init, .clkdm_deny_idle = ti_sysc_clkdm_deny_idle, .clkdm_allow_idle = ti_sysc_clkdm_allow_idle, +#ifdef CONFIG_OMAP_HWMOD .init_module = omap_hwmod_init_module, .enable_module = ti_sysc_enable_module, .idle_module = ti_sysc_idle_module, .shutdown_module = ti_sysc_shutdown_module, +#endif }; static struct pcs_pdata pcs_pdata; @@ -501,10 +507,6 @@ static struct of_dev_auxdata omap_auxdata_lookup[] = { OF_DEV_AUXDATA("ti,omap3-mcbsp", 0x49024000, "49024000.mcbsp", &mcbsp_pdata), #endif #endif -#ifdef CONFIG_SOC_AM33XX - OF_DEV_AUXDATA("ti,am3352-wkup-m3", 0x44d00000, "44d00000.wkup_m3", - &wkup_m3_data), -#endif #ifdef CONFIG_SOC_AM43XX OF_DEV_AUXDATA("ti,am4372-wkup-m3", 0x44d00000, "44d00000.wkup_m3", &wkup_m3_data), -- cgit v1.2.3-59-g8ed1b From 50896b745187b0a9ffca5bcf832424ce7501b2b5 Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Mon, 16 Nov 2020 12:57:13 +0200 Subject: ARM: dts: am43xx: add remaining PRM instances Add remaining PRM instances for the am43xx SoC. Additionally enable the genpd support for them. Signed-off-by: Tero Kristo Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am4372.dtsi | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi index 8844526577dd..7fef5d6d5dce 100644 --- a/arch/arm/boot/dts/am4372.dtsi +++ b/arch/arm/boot/dts/am4372.dtsi @@ -548,6 +548,12 @@ #include "am43xx-clocks.dtsi" &prcm { + prm_mpu: prm@300 { + compatible = "ti,am4-prm-inst", "ti,omap-prm-inst"; + reg = <0x300 0x100>; + #power-domain-cells = <0>; + }; + prm_gfx: prm@400 { compatible = "ti,am4-prm-inst", "ti,omap-prm-inst"; reg = <0x400 0x100>; @@ -555,16 +561,36 @@ #reset-cells = <1>; }; + prm_rtc: prm@500 { + compatible = "ti,am4-prm-inst", "ti,omap-prm-inst"; + reg = <0x500 0x100>; + #power-domain-cells = <0>; + }; + + prm_tamper: prm@600 { + compatible = "ti,am4-prm-inst", "ti,omap-prm-inst"; + reg = <0x600 0x100>; + #power-domain-cells = <0>; + }; + + prm_cefuse: prm@700 { + compatible = "ti,am4-prm-inst", "ti,omap-prm-inst"; + reg = <0x700 0x100>; + #power-domain-cells = <0>; + }; + prm_per: prm@800 { compatible = "ti,am4-prm-inst", "ti,omap-prm-inst"; reg = <0x800 0x100>; #reset-cells = <1>; + #power-domain-cells = <0>; }; prm_wkup: prm@2000 { compatible = "ti,am4-prm-inst", "ti,omap-prm-inst"; reg = <0x2000 0x100>; #reset-cells = <1>; + #power-domain-cells = <0>; }; prm_device: prm@4000 { -- cgit v1.2.3-59-g8ed1b From 00cb24bec0abcf177613abbfc32d7710ac8d6544 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Mon, 16 Nov 2020 12:57:13 +0200 Subject: ARM: dts: Configure also interconnect clocks for am4 system timer We now manage clocksource and clockevent clocks directly with timer-ti-dm-systimer. In order to use genpd with prm_omap, GENPD_FLAG_PM_CLK and simple-pm-bus, we need to keep the system timer related interconnect clocks enabled until clocksource suspend is done. Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am4372.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi index 7fef5d6d5dce..43e7d3ea2d93 100644 --- a/arch/arm/boot/dts/am4372.dtsi +++ b/arch/arm/boot/dts/am4372.dtsi @@ -604,6 +604,9 @@ &timer1_target { ti,no-reset-on-init; ti,no-idle; + clocks = <&l4_wkup_clkctrl AM4_L4_WKUP_TIMER1_CLKCTRL 0>, + <&l4_wkup_clkctrl AM4_L4_WKUP_L4_WKUP_CLKCTRL 0>; + clock-names = "fck", "ick"; timer@0 { assigned-clocks = <&timer1_fck>; assigned-clock-parents = <&sys_clkin_ck>; @@ -614,6 +617,9 @@ &timer2_target { ti,no-reset-on-init; ti,no-idle; + clocks = <&l4ls_clkctrl AM4_L4LS_TIMER2_CLKCTRL 0>, + <&l4ls_clkctrl AM4_L4LS_L4_LS_CLKCTRL 0>; + clock-names = "fck", "ick"; timer@0 { assigned-clocks = <&timer2_fck>; assigned-clock-parents = <&sys_clkin_ck>; -- cgit v1.2.3-59-g8ed1b From 2b999ae15b64643e7c6b79982cc4a8e2dd6db797 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Mon, 16 Nov 2020 12:57:13 +0200 Subject: ARM: OMAP2+: Drop legacy platform data for am4 control module We can now probe devices with ti-sysc interconnect driver and dts data. Let's drop the related platform data and custom ti,hwmods dts property. To drop the legacy platform data for am3 control module, we need to configure the missing functional clock and tag the module to not idle as platform data also had it configured with HWMOD_INIT_NO_IDLE. Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am437x-l4.dtsi | 3 +++ .../mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c | 7 ------- arch/arm/mach-omap2/omap_hwmod_43xx_data.c | 22 ---------------------- 3 files changed, 3 insertions(+), 29 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/am437x-l4.dtsi b/arch/arm/boot/dts/am437x-l4.dtsi index c220dc3c4e0f..be16ffc870bd 100644 --- a/arch/arm/boot/dts/am437x-l4.dtsi +++ b/arch/arm/boot/dts/am437x-l4.dtsi @@ -265,6 +265,9 @@ compatible = "ti,sysc-omap4", "ti,sysc"; reg = <0x10000 0x4>; reg-names = "rev"; + clocks = <&l4_wkup_clkctrl AM4_L4_WKUP_CONTROL_CLKCTRL 0>; + clock-names = "fck"; + ti,no-idle; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x10000 0x10000>; diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c index a58d79a619c8..7ce6ebb68002 100644 --- a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c @@ -211,13 +211,6 @@ struct omap_hwmod am33xx_smartreflex1_hwmod = { }, }; -/* - * 'control' module class - */ -struct omap_hwmod_class am33xx_control_hwmod_class = { - .name = "control", -}; - static void omap_hwmod_am33xx_clkctrl(void) { CLKCTRL(am33xx_smartreflex0_hwmod, diff --git a/arch/arm/mach-omap2/omap_hwmod_43xx_data.c b/arch/arm/mach-omap2/omap_hwmod_43xx_data.c index 6ccdf57041b1..0bc0dc2dccea 100644 --- a/arch/arm/mach-omap2/omap_hwmod_43xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_43xx_data.c @@ -71,20 +71,6 @@ static struct omap_hwmod am43xx_wkup_m3_hwmod = { .rst_lines_cnt = ARRAY_SIZE(am33xx_wkup_m3_resets), }; -static struct omap_hwmod am43xx_control_hwmod = { - .name = "control", - .class = &am33xx_control_hwmod_class, - .clkdm_name = "l4_wkup_clkdm", - .flags = HWMOD_INIT_NO_IDLE, - .main_clk = "sys_clkin_ck", - .prcm = { - .omap4 = { - .clkctrl_offs = AM43XX_CM_WKUP_CONTROL_CLKCTRL_OFFSET, - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - /* Interfaces */ static struct omap_hwmod_ocp_if am43xx_l3_main__emif = { .master = &am33xx_l3_main_hwmod, @@ -128,13 +114,6 @@ static struct omap_hwmod_ocp_if am43xx_l4_wkup__smartreflex1 = { .user = OCP_USER_MPU, }; -static struct omap_hwmod_ocp_if am43xx_l4_wkup__control = { - .master = &am33xx_l4_wkup_hwmod, - .slave = &am43xx_control_hwmod, - .clk = "sys_clkin_ck", - .user = OCP_USER_MPU, -}; - static struct omap_hwmod_ocp_if *am43xx_hwmod_ocp_ifs[] __initdata = { &am33xx_mpu__l3_main, &am33xx_mpu__prcm, @@ -147,7 +126,6 @@ static struct omap_hwmod_ocp_if *am43xx_hwmod_ocp_ifs[] __initdata = { &am43xx_l3_main__emif, &am43xx_wkup_m3__l4_wkup, &am43xx_l4_wkup__wkup_m3, - &am43xx_l4_wkup__control, &am43xx_l4_wkup__smartreflex0, &am43xx_l4_wkup__smartreflex1, &am33xx_l3_main__ocmc, -- cgit v1.2.3-59-g8ed1b From d8fecb36f42da03f40fe15bf7900ccd32a8122e2 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Mon, 16 Nov 2020 12:57:13 +0200 Subject: ARM: dts: Configure RTC powerdomain for am4 For genpd we need the RTC powerdomain configured. Cc: Dave Gerlach Cc: Suman Anna Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am437x-l4.dtsi | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/am437x-l4.dtsi b/arch/arm/boot/dts/am437x-l4.dtsi index be16ffc870bd..e6ef7d6190a1 100644 --- a/arch/arm/boot/dts/am437x-l4.dtsi +++ b/arch/arm/boot/dts/am437x-l4.dtsi @@ -422,6 +422,7 @@ , ; /* Domains (P, C): rtc_pwrdm, l4_rtc_clkdm */ + power-domains = <&prm_rtc>; clocks = <&l4_rtc_clkctrl AM4_L4_RTC_RTC_CLKCTRL 0>; clock-names = "fck"; #address-cells = <1>; -- cgit v1.2.3-59-g8ed1b From 302502efaf8fa0f553634b736723e1f9aedbda10 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Mon, 16 Nov 2020 12:57:13 +0200 Subject: ARM: dts: Configure interconnect target module for am4 wkup_m3 We can now probe devices with device tree only configuration using ti-sysc interconnect target module driver. Note that we no longer need ti,no-reset-on-init as the rstctrl resets are properly handled by the reset driver and claimed by the RTC driver. And we need to squash together the module ranges for driver compability. Cc: Dave Gerlach Cc: Suman Anna Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am4372.dtsi | 8 -------- arch/arm/boot/dts/am437x-l4.dtsi | 27 +++++++++++++++++---------- 2 files changed, 17 insertions(+), 18 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi index 43e7d3ea2d93..5da4414011fd 100644 --- a/arch/arm/boot/dts/am4372.dtsi +++ b/arch/arm/boot/dts/am4372.dtsi @@ -173,14 +173,6 @@ ; l4_wkup: interconnect@44c00000 { - wkup_m3: wkup_m3@100000 { - compatible = "ti,am4372-wkup-m3"; - reg = <0x100000 0x4000>, - <0x180000 0x2000>; - reg-names = "umem", "dmem"; - ti,hwmods = "wkup_m3"; - ti,pm-firmware = "am335x-pm-firmware.elf"; - }; }; l4_per: interconnect@48000000 { }; diff --git a/arch/arm/boot/dts/am437x-l4.dtsi b/arch/arm/boot/dts/am437x-l4.dtsi index e6ef7d6190a1..e944bc7ce48b 100644 --- a/arch/arm/boot/dts/am437x-l4.dtsi +++ b/arch/arm/boot/dts/am437x-l4.dtsi @@ -32,19 +32,26 @@ <0x000f0000 0x001f0000 0x010000>; /* ap 8 */ target-module@0 { /* 0x44d00000, ap 4 28.0 */ - compatible = "ti,sysc"; - status = "disabled"; + compatible = "ti,sysc-omap4", "ti,sysc"; + ti,hwmods = "wkup_m3"; + reg = <0x0 0x4>; + reg-names = "rev"; + clocks = <&l4_wkup_aon_clkctrl AM4_L4_WKUP_AON_WKUP_M3_CLKCTRL 0>; + clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; - ranges = <0x0 0x0 0x4000>; - }; + ranges = <0x00000000 0x00000000 0x4000>, + <0x00080000 0x00080000 0x2000>; - target-module@80000 { /* 0x44d80000, ap 6 10.0 */ - compatible = "ti,sysc"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x80000 0x2000>; + wkup_m3: cpu@0 { + compatible = "ti,am4372-wkup-m3"; + reg = <0x00000000 0x4000>, + <0x00080000 0x2000>; + reg-names = "umem", "dmem"; + resets = <&prm_wkup 3>; + reset-names = "rstctrl"; + ti,pm-firmware = "am335x-pm-firmware.elf"; + }; }; target-module@f0000 { /* 0x44df0000, ap 8 58.0 */ -- cgit v1.2.3-59-g8ed1b From f7ddc2c9746984524c44a85e1b11eaa221593089 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Mon, 16 Nov 2020 12:57:13 +0200 Subject: ARM: OMAP2+: Drop legacy platform data for am4 wkup_m3 We can now probe devices with ti-sysc interconnect driver and dts data. Let's drop the related platform data and custom ti,hwmods dts property. As we're just dropping data, and the early platform data init is based on the custom ti,hwmods property, we want to drop both the platform data and ti,hwmods property in a single patch. Cc: Dave Gerlach Cc: Suman Anna Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am437x-l4.dtsi | 1 - .../mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c | 8 ----- arch/arm/mach-omap2/omap_hwmod_43xx_data.c | 39 ---------------------- 3 files changed, 48 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/am437x-l4.dtsi b/arch/arm/boot/dts/am437x-l4.dtsi index e944bc7ce48b..2b0e458150f7 100644 --- a/arch/arm/boot/dts/am437x-l4.dtsi +++ b/arch/arm/boot/dts/am437x-l4.dtsi @@ -33,7 +33,6 @@ target-module@0 { /* 0x44d00000, ap 4 28.0 */ compatible = "ti,sysc-omap4", "ti,sysc"; - ti,hwmods = "wkup_m3"; reg = <0x0 0x4>; reg-names = "rev"; clocks = <&l4_wkup_aon_clkctrl AM4_L4_WKUP_AON_WKUP_M3_CLKCTRL 0>; diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c index 7ce6ebb68002..0bdd8cd8f154 100644 --- a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c @@ -124,14 +124,6 @@ struct omap_hwmod am33xx_mpu_hwmod = { }, }; -/* - * 'wakeup m3' class - * Wakeup controller sub-system under wakeup domain - */ -struct omap_hwmod_class am33xx_wkup_m3_hwmod_class = { - .name = "wkup_m3", -}; - /* * 'prcm' class * power and reset manager (whole prcm infrastructure) diff --git a/arch/arm/mach-omap2/omap_hwmod_43xx_data.c b/arch/arm/mach-omap2/omap_hwmod_43xx_data.c index 0bc0dc2dccea..07bc9462339a 100644 --- a/arch/arm/mach-omap2/omap_hwmod_43xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_43xx_data.c @@ -48,29 +48,6 @@ static struct omap_hwmod am43xx_l4_hs_hwmod = { }, }; -static struct omap_hwmod_rst_info am33xx_wkup_m3_resets[] = { - { .name = "wkup_m3", .rst_shift = 3, .st_shift = 5 }, -}; - -static struct omap_hwmod am43xx_wkup_m3_hwmod = { - .name = "wkup_m3", - .class = &am33xx_wkup_m3_hwmod_class, - .clkdm_name = "l4_wkup_aon_clkdm", - /* Keep hardreset asserted */ - .flags = HWMOD_INIT_NO_RESET | HWMOD_NO_IDLEST, - .main_clk = "sys_clkin_ck", - .prcm = { - .omap4 = { - .clkctrl_offs = AM43XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET, - .rstctrl_offs = AM43XX_RM_WKUP_RSTCTRL_OFFSET, - .rstst_offs = AM43XX_RM_WKUP_RSTST_OFFSET, - .modulemode = MODULEMODE_SWCTRL, - }, - }, - .rst_lines = am33xx_wkup_m3_resets, - .rst_lines_cnt = ARRAY_SIZE(am33xx_wkup_m3_resets), -}; - /* Interfaces */ static struct omap_hwmod_ocp_if am43xx_l3_main__emif = { .master = &am33xx_l3_main_hwmod, @@ -86,20 +63,6 @@ static struct omap_hwmod_ocp_if am43xx_l3_main__l4_hs = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; -static struct omap_hwmod_ocp_if am43xx_wkup_m3__l4_wkup = { - .master = &am43xx_wkup_m3_hwmod, - .slave = &am33xx_l4_wkup_hwmod, - .clk = "sys_clkin_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -static struct omap_hwmod_ocp_if am43xx_l4_wkup__wkup_m3 = { - .master = &am33xx_l4_wkup_hwmod, - .slave = &am43xx_wkup_m3_hwmod, - .clk = "sys_clkin_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - static struct omap_hwmod_ocp_if am43xx_l4_wkup__smartreflex0 = { .master = &am33xx_l4_wkup_hwmod, .slave = &am33xx_smartreflex0_hwmod, @@ -124,8 +87,6 @@ static struct omap_hwmod_ocp_if *am43xx_hwmod_ocp_ifs[] __initdata = { &am33xx_l3_main__l3_instr, &am33xx_l3_s__l3_main, &am43xx_l3_main__emif, - &am43xx_wkup_m3__l4_wkup, - &am43xx_l4_wkup__wkup_m3, &am43xx_l4_wkup__smartreflex0, &am43xx_l4_wkup__smartreflex1, &am33xx_l3_main__ocmc, -- cgit v1.2.3-59-g8ed1b From 04af40fc7433555d31d73b698f0fb292b0bf9d7c Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Mon, 16 Nov 2020 12:57:13 +0200 Subject: ARM: OMAP2+: Drop legacy platform data for am4 emif We can now probe devices with ti-sysc interconnect driver and dts data. Let's drop the related platform data and custom ti,hwmods dts property. Cc: Dave Gerlach Cc: Suman Anna Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am4372.dtsi | 24 +++++++++++++++------- .../mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c | 15 -------------- arch/arm/mach-omap2/omap_hwmod_43xx_data.c | 21 ------------------- 3 files changed, 17 insertions(+), 43 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi index 5da4414011fd..204556144ce7 100644 --- a/arch/arm/boot/dts/am4372.dtsi +++ b/arch/arm/boot/dts/am4372.dtsi @@ -179,14 +179,24 @@ l4_fast: interconnect@4a000000 { }; - emif: emif@4c000000 { - compatible = "ti,emif-am4372"; - reg = <0x4c000000 0x1000000>; - ti,hwmods = "emif"; - interrupts = ; + target-module@4c000000 { + compatible = "ti,sysc-omap4-simple", "ti,sysc"; + reg = <0x4c000000 0x4>; + reg-names = "rev"; + clocks = <&emif_clkctrl AM4_EMIF_EMIF_CLKCTRL 0>; + clock-names = "fck"; ti,no-idle; - sram = <&pm_sram_code - &pm_sram_data>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x4c000000 0x1000000>; + + emif: emif@0 { + compatible = "ti,emif-am4372"; + reg = <0 0x1000000>; + interrupts = ; + sram = <&pm_sram_code + &pm_sram_data>; + }; }; target-module@49000000 { diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c index 0bdd8cd8f154..f72fb6c8cc9b 100644 --- a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c @@ -139,21 +139,6 @@ struct omap_hwmod am33xx_prcm_hwmod = { .clkdm_name = "l4_wkup_clkdm", }; -/* - * 'emif' class - * instance(s): emif - */ -static struct omap_hwmod_class_sysconfig am33xx_emif_sysc = { - .rev_offs = 0x0000, -}; - -struct omap_hwmod_class am33xx_emif_hwmod_class = { - .name = "emif", - .sysc = &am33xx_emif_sysc, -}; - - - /* ocmcram */ static struct omap_hwmod_class am33xx_ocmcram_hwmod_class = { .name = "ocmcram", diff --git a/arch/arm/mach-omap2/omap_hwmod_43xx_data.c b/arch/arm/mach-omap2/omap_hwmod_43xx_data.c index 07bc9462339a..a17f2b0b6583 100644 --- a/arch/arm/mach-omap2/omap_hwmod_43xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_43xx_data.c @@ -20,20 +20,6 @@ #include "omap_hwmod_common_data.h" /* IP blocks */ -static struct omap_hwmod am43xx_emif_hwmod = { - .name = "emif", - .class = &am33xx_emif_hwmod_class, - .clkdm_name = "emif_clkdm", - .flags = HWMOD_INIT_NO_IDLE, - .main_clk = "dpll_ddr_m2_ck", - .prcm = { - .omap4 = { - .clkctrl_offs = AM43XX_CM_PER_EMIF_CLKCTRL_OFFSET, - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - static struct omap_hwmod am43xx_l4_hs_hwmod = { .name = "l4_hs", .class = &am33xx_l4_hwmod_class, @@ -49,12 +35,6 @@ static struct omap_hwmod am43xx_l4_hs_hwmod = { }; /* Interfaces */ -static struct omap_hwmod_ocp_if am43xx_l3_main__emif = { - .master = &am33xx_l3_main_hwmod, - .slave = &am43xx_emif_hwmod, - .clk = "dpll_core_m4_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; static struct omap_hwmod_ocp_if am43xx_l3_main__l4_hs = { .master = &am33xx_l3_main_hwmod, @@ -86,7 +66,6 @@ static struct omap_hwmod_ocp_if *am43xx_hwmod_ocp_ifs[] __initdata = { &am33xx_l3_main__l3_s, &am33xx_l3_main__l3_instr, &am33xx_l3_s__l3_main, - &am43xx_l3_main__emif, &am43xx_l4_wkup__smartreflex0, &am43xx_l4_wkup__smartreflex1, &am33xx_l3_main__ocmc, -- cgit v1.2.3-59-g8ed1b From ffbf46a3624cad94ee087a5d486b423e43f6bc1f Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Mon, 16 Nov 2020 12:57:13 +0200 Subject: ARM: OMAP2+: Drop legacy platform data for am4 ocmcram We can now probe devices with ti-sysc interconnect driver and dts data. Let's drop the related platform data and custom ti,hwmods dts property. Note that we need to use "ti,no-idle" here. Cc: Dave Gerlach Cc: Suman Anna Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am4372.dtsi | 36 ++++++++++++++-------- .../omap_hwmod_33xx_43xx_interconnect_data.c | 7 ----- .../mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c | 19 ------------ arch/arm/mach-omap2/omap_hwmod_43xx_data.c | 1 - 4 files changed, 23 insertions(+), 40 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi index 204556144ce7..ab70722e866f 100644 --- a/arch/arm/boot/dts/am4372.dtsi +++ b/arch/arm/boot/dts/am4372.dtsi @@ -503,23 +503,33 @@ }; }; - ocmcram: sram@40300000 { - compatible = "mmio-sram"; - reg = <0x40300000 0x40000>; /* 256k */ - ranges = <0x0 0x40300000 0x40000>; + target-module@40300000 { + compatible = "ti,sysc-omap4-simple", "ti,sysc"; + clocks = <&l3_clkctrl AM4_L3_OCMCRAM_CLKCTRL 0>; + clock-names = "fck"; + ti,no-idle; #address-cells = <1>; #size-cells = <1>; + ranges = <0 0x40300000 0x40000>; - pm_sram_code: pm-code-sram@0 { - compatible = "ti,sram"; - reg = <0x0 0x1000>; - protect-exec; - }; + ocmcram: sram@0 { + compatible = "mmio-sram"; + reg = <0 0x40000>; /* 256k */ + ranges = <0 0 0x40000>; + #address-cells = <1>; + #size-cells = <1>; - pm_sram_data: pm-data-sram@1000 { - compatible = "ti,sram"; - reg = <0x1000 0x1000>; - pool; + pm_sram_code: pm-code-sram@0 { + compatible = "ti,sram"; + reg = <0x0 0x1000>; + protect-exec; + }; + + pm_sram_data: pm-data-sram@1000 { + compatible = "ti,sram"; + reg = <0x1000 0x1000>; + pool; + }; }; }; diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_interconnect_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_interconnect_data.c index 32741de0ed71..6b8837378fa9 100644 --- a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_interconnect_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_interconnect_data.c @@ -73,10 +73,3 @@ struct omap_hwmod_ocp_if am33xx_l3_s__l3_main = { .clk = "l3s_gclk", .user = OCP_USER_MPU | OCP_USER_SDMA, }; - -/* l3 main -> ocmc */ -struct omap_hwmod_ocp_if am33xx_l3_main__ocmc = { - .master = &am33xx_l3_main_hwmod, - .slave = &am33xx_ocmcram_hwmod, - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c index f72fb6c8cc9b..670c1934f8d4 100644 --- a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c @@ -139,24 +139,6 @@ struct omap_hwmod am33xx_prcm_hwmod = { .clkdm_name = "l4_wkup_clkdm", }; -/* ocmcram */ -static struct omap_hwmod_class am33xx_ocmcram_hwmod_class = { - .name = "ocmcram", -}; - -struct omap_hwmod am33xx_ocmcram_hwmod = { - .name = "ocmcram", - .class = &am33xx_ocmcram_hwmod_class, - .clkdm_name = "l3_clkdm", - .flags = HWMOD_INIT_NO_IDLE, - .main_clk = "l3_gclk", - .prcm = { - .omap4 = { - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - /* 'smartreflex' class */ static struct omap_hwmod_class am33xx_smartreflex_hwmod_class = { .name = "smartreflex", @@ -215,7 +197,6 @@ static void omap_hwmod_am43xx_clkctrl(void) CLKCTRL(am33xx_l4_wkup_hwmod, AM43XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET); CLKCTRL(am33xx_l3_main_hwmod, AM43XX_CM_PER_L3_CLKCTRL_OFFSET); CLKCTRL(am33xx_mpu_hwmod , AM43XX_CM_MPU_MPU_CLKCTRL_OFFSET); - CLKCTRL(am33xx_ocmcram_hwmod , AM43XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET); } void omap_hwmod_am43xx_reg(void) diff --git a/arch/arm/mach-omap2/omap_hwmod_43xx_data.c b/arch/arm/mach-omap2/omap_hwmod_43xx_data.c index a17f2b0b6583..9bae22d217b9 100644 --- a/arch/arm/mach-omap2/omap_hwmod_43xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_43xx_data.c @@ -68,7 +68,6 @@ static struct omap_hwmod_ocp_if *am43xx_hwmod_ocp_ifs[] __initdata = { &am33xx_l3_s__l3_main, &am43xx_l4_wkup__smartreflex0, &am43xx_l4_wkup__smartreflex1, - &am33xx_l3_main__ocmc, NULL, }; -- cgit v1.2.3-59-g8ed1b From 98e6c0ae1444b97ba1ad2078847d50cb324a070e Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Mon, 16 Nov 2020 12:57:13 +0200 Subject: ARM: OMAP2+: Drop legacy platform data for am4 mpuss We can now probe devices with ti-sysc interconnect driver and dts data. Let's drop the related platform data and custom ti,hwmods dts property. Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am4372.dtsi | 6 ------ arch/arm/boot/dts/am437x-l4.dtsi | 18 ++++++++++++++++++ .../mach-omap2/omap_hwmod_33xx_43xx_common_data.h | 3 --- .../omap_hwmod_33xx_43xx_interconnect_data.c | 16 ---------------- .../mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c | 21 --------------------- arch/arm/mach-omap2/omap_hwmod_43xx_data.c | 2 -- 6 files changed, 18 insertions(+), 48 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi index ab70722e866f..0e0805688882 100644 --- a/arch/arm/boot/dts/am4372.dtsi +++ b/arch/arm/boot/dts/am4372.dtsi @@ -107,12 +107,6 @@ soc { compatible = "ti,omap-infra"; - mpu { - compatible = "ti,omap4-mpu"; - ti,hwmods = "mpu"; - pm-sram = <&pm_sram_code - &pm_sram_data>; - }; }; gic: interrupt-controller@48241000 { diff --git a/arch/arm/boot/dts/am437x-l4.dtsi b/arch/arm/boot/dts/am437x-l4.dtsi index 2b0e458150f7..30c029a7b839 100644 --- a/arch/arm/boot/dts/am437x-l4.dtsi +++ b/arch/arm/boot/dts/am437x-l4.dtsi @@ -1631,6 +1631,24 @@ compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; + ranges = <0x00000000 0x00200000 0x010000>; + + target-module@0 { + compatible = "ti,sysc-omap4-simple", "ti,sysc"; + power-domains = <&prm_mpu>; + clocks = <&mpu_clkctrl AM4_MPU_MPU_CLKCTRL 0>; + clock-names = "fck"; + ti,no-idle; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x10000>; + + mpu@0 { + compatible = "ti,omap4-mpu"; + pm-sram = <&pm_sram_code + &pm_sram_data>; + }; + }; }; segment@300000 { /* 0x48300000 */ diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_common_data.h b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_common_data.h index 9aae558f6e9f..795e9c58c54a 100644 --- a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_common_data.h +++ b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_common_data.h @@ -17,12 +17,10 @@ #ifndef __ARCH_ARM_MACH_OMAP2_OMAP_HWMOD_33XX_43XX_COMMON_DATA_H #define __ARCH_ARM_MACH_OMAP2_OMAP_HWMOD_33XX_43XX_COMMON_DATA_H -extern struct omap_hwmod_ocp_if am33xx_mpu__l3_main; extern struct omap_hwmod_ocp_if am33xx_l3_main__l3_s; extern struct omap_hwmod_ocp_if am33xx_l3_s__l4_ls; extern struct omap_hwmod_ocp_if am33xx_l3_s__l4_wkup; extern struct omap_hwmod_ocp_if am33xx_l3_main__l3_instr; -extern struct omap_hwmod_ocp_if am33xx_mpu__prcm; extern struct omap_hwmod_ocp_if am33xx_l3_s__l3_main; extern struct omap_hwmod_ocp_if am33xx_gfx__l3_main; extern struct omap_hwmod_ocp_if am33xx_l3_main__gfx; @@ -34,7 +32,6 @@ extern struct omap_hwmod am33xx_l3_s_hwmod; extern struct omap_hwmod am33xx_l3_instr_hwmod; extern struct omap_hwmod am33xx_l4_ls_hwmod; extern struct omap_hwmod am33xx_l4_wkup_hwmod; -extern struct omap_hwmod am33xx_mpu_hwmod; extern struct omap_hwmod am33xx_gfx_hwmod; extern struct omap_hwmod am33xx_prcm_hwmod; extern struct omap_hwmod am33xx_ocmcram_hwmod; diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_interconnect_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_interconnect_data.c index 6b8837378fa9..f447e5476fea 100644 --- a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_interconnect_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_interconnect_data.c @@ -18,14 +18,6 @@ #include "omap_hwmod.h" #include "omap_hwmod_33xx_43xx_common_data.h" -/* mpu -> l3 main */ -struct omap_hwmod_ocp_if am33xx_mpu__l3_main = { - .master = &am33xx_mpu_hwmod, - .slave = &am33xx_l3_main_hwmod, - .clk = "dpll_mpu_m2_ck", - .user = OCP_USER_MPU, -}; - /* l3 main -> l3 s */ struct omap_hwmod_ocp_if am33xx_l3_main__l3_s = { .master = &am33xx_l3_main_hwmod, @@ -58,14 +50,6 @@ struct omap_hwmod_ocp_if am33xx_l3_main__l3_instr = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; -/* mpu -> prcm */ -struct omap_hwmod_ocp_if am33xx_mpu__prcm = { - .master = &am33xx_mpu_hwmod, - .slave = &am33xx_prcm_hwmod, - .clk = "dpll_mpu_m2_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - /* l3 s -> l3 main*/ struct omap_hwmod_ocp_if am33xx_l3_s__l3_main = { .master = &am33xx_l3_s_hwmod, diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c index 670c1934f8d4..0399055fce25 100644 --- a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c @@ -104,26 +104,6 @@ struct omap_hwmod am33xx_l4_wkup_hwmod = { }, }; -/* - * 'mpu' class - */ -static struct omap_hwmod_class am33xx_mpu_hwmod_class = { - .name = "mpu", -}; - -struct omap_hwmod am33xx_mpu_hwmod = { - .name = "mpu", - .class = &am33xx_mpu_hwmod_class, - .clkdm_name = "mpu_clkdm", - .flags = HWMOD_INIT_NO_IDLE, - .main_clk = "dpll_mpu_m2_ck", - .prcm = { - .omap4 = { - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - /* * 'prcm' class * power and reset manager (whole prcm infrastructure) @@ -196,7 +176,6 @@ static void omap_hwmod_am43xx_clkctrl(void) CLKCTRL(am33xx_l4_ls_hwmod, AM43XX_CM_PER_L4LS_CLKCTRL_OFFSET); CLKCTRL(am33xx_l4_wkup_hwmod, AM43XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET); CLKCTRL(am33xx_l3_main_hwmod, AM43XX_CM_PER_L3_CLKCTRL_OFFSET); - CLKCTRL(am33xx_mpu_hwmod , AM43XX_CM_MPU_MPU_CLKCTRL_OFFSET); } void omap_hwmod_am43xx_reg(void) diff --git a/arch/arm/mach-omap2/omap_hwmod_43xx_data.c b/arch/arm/mach-omap2/omap_hwmod_43xx_data.c index 9bae22d217b9..b288d113efcf 100644 --- a/arch/arm/mach-omap2/omap_hwmod_43xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_43xx_data.c @@ -58,8 +58,6 @@ static struct omap_hwmod_ocp_if am43xx_l4_wkup__smartreflex1 = { }; static struct omap_hwmod_ocp_if *am43xx_hwmod_ocp_ifs[] __initdata = { - &am33xx_mpu__l3_main, - &am33xx_mpu__prcm, &am33xx_l3_s__l4_ls, &am33xx_l3_s__l4_wkup, &am43xx_l3_main__l4_hs, -- cgit v1.2.3-59-g8ed1b From 209ca3e8add0fb3331f5ccdf29bdb1a82b10533c Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Mon, 16 Nov 2020 12:57:13 +0200 Subject: ARM: dts: Use simple-pm-bus for genpd for am4 l4_wkup We can now enable simple-pm-bus to use genpd. Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am437x-l4.dtsi | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/am437x-l4.dtsi b/arch/arm/boot/dts/am437x-l4.dtsi index 30c029a7b839..f07a7adfeea9 100644 --- a/arch/arm/boot/dts/am437x-l4.dtsi +++ b/arch/arm/boot/dts/am437x-l4.dtsi @@ -1,5 +1,8 @@ &l4_wkup { /* 0x44c00000 */ - compatible = "ti,am4-l4-wkup", "simple-bus"; + compatible = "ti,am4-l4-wkup", "simple-pm-bus"; + power-domains = <&prm_wkup>; + clocks = <&l4_wkup_clkctrl AM4_L4_WKUP_L4_WKUP_CLKCTRL 0>; + clock-names = "fck"; reg = <0x44c00000 0x800>, <0x44c00800 0x800>, <0x44c01000 0x400>, @@ -12,7 +15,7 @@ <0x00200000 0x44e00000 0x100000>; /* segment 2 */ segment@0 { /* 0x44c00000 */ - compatible = "simple-bus"; + compatible = "simple-pm-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ @@ -22,7 +25,7 @@ }; segment@100000 { /* 0x44d00000 */ - compatible = "simple-bus"; + compatible = "simple-pm-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x00000000 0x00100000 0x004000>, /* ap 4 */ @@ -81,7 +84,7 @@ }; segment@200000 { /* 0x44e00000 */ - compatible = "simple-bus"; + compatible = "simple-pm-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x00000000 0x00200000 0x001000>, /* ap 9 */ -- cgit v1.2.3-59-g8ed1b From 3de94f076cda64b1081ecc3ec4b706ff3222e63c Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Mon, 16 Nov 2020 12:57:13 +0200 Subject: ARM: dts: Use simple-pm-bus for genpd for am4 l4_fast We can now enable simple-pm-bus to use genpd. Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am437x-l4.dtsi | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/am437x-l4.dtsi b/arch/arm/boot/dts/am437x-l4.dtsi index f07a7adfeea9..ab962fc1dcbf 100644 --- a/arch/arm/boot/dts/am437x-l4.dtsi +++ b/arch/arm/boot/dts/am437x-l4.dtsi @@ -492,7 +492,10 @@ }; &l4_fast { /* 0x4a000000 */ - compatible = "ti,am4-l4-fast", "simple-bus"; + compatible = "ti,am4-l4-fast", "simple-pm-bus"; + power-domains = <&prm_per>; + clocks = <&l3_clkctrl AM4_L3_L4_HS_CLKCTRL 0>; + clock-names = "fck"; reg = <0x4a000000 0x800>, <0x4a000800 0x800>, <0x4a001000 0x400>; @@ -502,7 +505,7 @@ ranges = <0x00000000 0x4a000000 0x1000000>; /* segment 0 */ segment@0 { /* 0x4a000000 */ - compatible = "simple-bus"; + compatible = "simple-pm-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ -- cgit v1.2.3-59-g8ed1b From 2e4da7eab473585c1a041b3e2e106ea99a684747 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Mon, 16 Nov 2020 12:57:13 +0200 Subject: ARM: dts: Use simple-pm-bus for genpd for am4 l4_per We can now enable simple-pm-bus to use genpd. Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am437x-l4.dtsi | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/am437x-l4.dtsi b/arch/arm/boot/dts/am437x-l4.dtsi index ab962fc1dcbf..dfbededcb2c4 100644 --- a/arch/arm/boot/dts/am437x-l4.dtsi +++ b/arch/arm/boot/dts/am437x-l4.dtsi @@ -610,7 +610,10 @@ }; &l4_per { /* 0x48000000 */ - compatible = "ti,am4-l4-per", "simple-bus"; + compatible = "ti,am4-l4-per", "simple-pm-bus"; + power-domains = <&prm_per>; + clocks = <&l4ls_clkctrl AM4_L4LS_L4_LS_CLKCTRL 0>; + clock-names = "fck"; reg = <0x48000000 0x800>, <0x48000800 0x800>, <0x48001000 0x400>, @@ -628,7 +631,7 @@ <0x46400000 0x46400000 0x400000>; /* l3 data port */ segment@0 { /* 0x48000000 */ - compatible = "simple-bus"; + compatible = "simple-pm-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ @@ -1203,7 +1206,7 @@ }; segment@100000 { /* 0x48100000 */ - compatible = "simple-bus"; + compatible = "simple-pm-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0008c000 0x0018c000 0x001000>, /* ap 34 */ @@ -1634,7 +1637,7 @@ }; segment@200000 { /* 0x48200000 */ - compatible = "simple-bus"; + compatible = "simple-pm-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x00000000 0x00200000 0x010000>; @@ -1658,7 +1661,7 @@ }; segment@300000 { /* 0x48300000 */ - compatible = "simple-bus"; + compatible = "simple-pm-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x00000000 0x00300000 0x001000>, /* ap 56 */ -- cgit v1.2.3-59-g8ed1b From 994b86e8fd017d06fb3c333fbd6c25aa3c9edfca Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Mon, 16 Nov 2020 12:57:13 +0200 Subject: ARM: dts: Move am4 l3 noc to a separate node In preparation for probing l3 with simple-pm-bus and genpd, we must move l3 noc to a separate node to prevent omap_l3_noc.c driver from claiming the whole l3 instance before simple-pm-bus has a chance to probe. Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am4372.dtsi | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi index 0e0805688882..75fe295aefa9 100644 --- a/arch/arm/boot/dts/am4372.dtsi +++ b/arch/arm/boot/dts/am4372.dtsi @@ -161,10 +161,14 @@ ranges; ti,hwmods = "l3_main"; ti,no-idle; - reg = <0x44000000 0x400000 - 0x44800000 0x400000>; - interrupts = , - ; + + l3-noc@44000000 { + compatible = "ti,am4372-l3-noc"; + reg = <0x44000000 0x400000>, + <0x44800000 0x400000>; + interrupts = , + ; + }; l4_wkup: interconnect@44c00000 { }; -- cgit v1.2.3-59-g8ed1b From 4cf6a21411b7a29b6e46f9e3fb2118edb3b602d2 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Mon, 16 Nov 2020 12:57:13 +0200 Subject: ARM: dts: Use simple-pm-bus for genpd for am4 l3 We can now enable simple-pm-bus to use genpd. Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am4372.dtsi | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi index 75fe295aefa9..57a85a6c34a2 100644 --- a/arch/arm/boot/dts/am4372.dtsi +++ b/arch/arm/boot/dts/am4372.dtsi @@ -155,11 +155,13 @@ }; ocp@44000000 { - compatible = "ti,am4372-l3-noc", "simple-bus"; + compatible = "simple-pm-bus"; + power-domains = <&prm_per>; + clocks = <&l3_clkctrl AM4_L3_L3_MAIN_CLKCTRL 0>; + clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges; - ti,hwmods = "l3_main"; ti,no-idle; l3-noc@44000000 { -- cgit v1.2.3-59-g8ed1b From df6c2ec872a62cf81dff86ef62818dea89cc9d98 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Mon, 16 Nov 2020 12:57:13 +0200 Subject: ARM: OMAP2+: Drop legacy remaining legacy platform data for am4 We can now drop the remaining legacy platform data as we are probing devices with device tree data. Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/Kconfig | 1 - arch/arm/mach-omap2/Makefile | 5 +- arch/arm/mach-omap2/io.c | 1 - .../mach-omap2/omap_hwmod_33xx_43xx_common_data.h | 52 ------ .../omap_hwmod_33xx_43xx_interconnect_data.c | 59 ------- .../mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c | 184 --------------------- arch/arm/mach-omap2/omap_hwmod_43xx_data.c | 81 --------- 7 files changed, 1 insertion(+), 382 deletions(-) delete mode 100644 arch/arm/mach-omap2/omap_hwmod_33xx_43xx_common_data.h delete mode 100644 arch/arm/mach-omap2/omap_hwmod_33xx_43xx_interconnect_data.c delete mode 100644 arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c delete mode 100644 arch/arm/mach-omap2/omap_hwmod_43xx_data.c (limited to 'arch/arm') diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index c7ef2e242f30..0c876c0e4d2a 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig @@ -78,7 +78,6 @@ config SOC_AM43XX select HAVE_ARM_TWD select ARM_ERRATA_754322 select ARM_ERRATA_775420 - select OMAP_HWMOD select OMAP_INTERCONNECT select ARM_CPU_SUSPEND if PM diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index efd409ddceb5..9bcfb34a2206 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -23,7 +23,7 @@ obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(hwmod-common) $(secure-common) obj-$(CONFIG_ARCH_OMAP4) += $(hwmod-common) $(secure-common) obj-$(CONFIG_SOC_AM33XX) += $(secure-common) obj-$(CONFIG_SOC_OMAP5) += $(hwmod-common) $(secure-common) -obj-$(CONFIG_SOC_AM43XX) += $(hwmod-common) $(secure-common) +obj-$(CONFIG_SOC_AM43XX) += $(secure-common) obj-$(CONFIG_SOC_DRA7XX) += $(hwmod-common) $(secure-common) ifneq ($(CONFIG_SND_SOC_OMAP_MCBSP),) @@ -206,9 +206,6 @@ obj-$(CONFIG_SOC_OMAP2430) += omap_hwmod_2xxx_interconnect_data.o obj-$(CONFIG_SOC_OMAP2430) += omap_hwmod_2430_data.o obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_2xxx_3xxx_ipblock_data.o obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_3xxx_data.o -obj-$(CONFIG_SOC_AM43XX) += omap_hwmod_43xx_data.o -obj-$(CONFIG_SOC_AM43XX) += omap_hwmod_33xx_43xx_interconnect_data.o -obj-$(CONFIG_SOC_AM43XX) += omap_hwmod_33xx_43xx_ipblock_data.o obj-$(CONFIG_SOC_TI81XX) += omap_hwmod_81xx_data.o obj-$(CONFIG_ARCH_OMAP4) += omap_hwmod_44xx_data.o obj-$(CONFIG_SOC_OMAP5) += omap_hwmod_54xx_data.o diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c index a868b91ce90a..6cd99e868556 100644 --- a/arch/arm/mach-omap2/io.c +++ b/arch/arm/mach-omap2/io.c @@ -588,7 +588,6 @@ void __init am43xx_init_early(void) omap2_prcm_base_init(); am43xx_powerdomains_init(); am43xx_clockdomains_init(); - am43xx_hwmod_init(); omap_hwmod_init_postsetup(); omap_l2_cache_init(); omap_clk_soc_init = am43xx_dt_clk_init; diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_common_data.h b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_common_data.h deleted file mode 100644 index 795e9c58c54a..000000000000 --- a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_common_data.h +++ /dev/null @@ -1,52 +0,0 @@ -/* - * - * Copyright (C) 2013 Texas Instruments Incorporated - * - * Data common for AM335x and AM43x - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation version 2. - * - * This program is distributed "as is" WITHOUT ANY WARRANTY of any - * kind, whether express or implied; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __ARCH_ARM_MACH_OMAP2_OMAP_HWMOD_33XX_43XX_COMMON_DATA_H -#define __ARCH_ARM_MACH_OMAP2_OMAP_HWMOD_33XX_43XX_COMMON_DATA_H - -extern struct omap_hwmod_ocp_if am33xx_l3_main__l3_s; -extern struct omap_hwmod_ocp_if am33xx_l3_s__l4_ls; -extern struct omap_hwmod_ocp_if am33xx_l3_s__l4_wkup; -extern struct omap_hwmod_ocp_if am33xx_l3_main__l3_instr; -extern struct omap_hwmod_ocp_if am33xx_l3_s__l3_main; -extern struct omap_hwmod_ocp_if am33xx_gfx__l3_main; -extern struct omap_hwmod_ocp_if am33xx_l3_main__gfx; -extern struct omap_hwmod_ocp_if am33xx_l4_ls__timer2; -extern struct omap_hwmod_ocp_if am33xx_l3_main__ocmc; - -extern struct omap_hwmod am33xx_l3_main_hwmod; -extern struct omap_hwmod am33xx_l3_s_hwmod; -extern struct omap_hwmod am33xx_l3_instr_hwmod; -extern struct omap_hwmod am33xx_l4_ls_hwmod; -extern struct omap_hwmod am33xx_l4_wkup_hwmod; -extern struct omap_hwmod am33xx_gfx_hwmod; -extern struct omap_hwmod am33xx_prcm_hwmod; -extern struct omap_hwmod am33xx_ocmcram_hwmod; -extern struct omap_hwmod am33xx_smartreflex0_hwmod; -extern struct omap_hwmod am33xx_smartreflex1_hwmod; - -extern struct omap_hwmod_class am33xx_emif_hwmod_class; -extern struct omap_hwmod_class am33xx_l4_hwmod_class; -extern struct omap_hwmod_class am33xx_wkup_m3_hwmod_class; -extern struct omap_hwmod_class am33xx_control_hwmod_class; -extern struct omap_hwmod_class am33xx_timer_hwmod_class; -extern struct omap_hwmod_class am33xx_ehrpwm_hwmod_class; -extern struct omap_hwmod_class am33xx_spi_hwmod_class; - -void omap_hwmod_am33xx_reg(void); -void omap_hwmod_am43xx_reg(void); - -#endif diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_interconnect_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_interconnect_data.c deleted file mode 100644 index f447e5476fea..000000000000 --- a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_interconnect_data.c +++ /dev/null @@ -1,59 +0,0 @@ -/* - * - * Copyright (C) 2013 Texas Instruments Incorporated - * - * Interconnects common for AM335x and AM43x - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation version 2. - * - * This program is distributed "as is" WITHOUT ANY WARRANTY of any - * kind, whether express or implied; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include "omap_hwmod.h" -#include "omap_hwmod_33xx_43xx_common_data.h" - -/* l3 main -> l3 s */ -struct omap_hwmod_ocp_if am33xx_l3_main__l3_s = { - .master = &am33xx_l3_main_hwmod, - .slave = &am33xx_l3_s_hwmod, - .clk = "l3s_gclk", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l3 s -> l4 per/ls */ -struct omap_hwmod_ocp_if am33xx_l3_s__l4_ls = { - .master = &am33xx_l3_s_hwmod, - .slave = &am33xx_l4_ls_hwmod, - .clk = "l3s_gclk", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l3 s -> l4 wkup */ -struct omap_hwmod_ocp_if am33xx_l3_s__l4_wkup = { - .master = &am33xx_l3_s_hwmod, - .slave = &am33xx_l4_wkup_hwmod, - .clk = "l3s_gclk", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l3 main -> l3 instr */ -struct omap_hwmod_ocp_if am33xx_l3_main__l3_instr = { - .master = &am33xx_l3_main_hwmod, - .slave = &am33xx_l3_instr_hwmod, - .clk = "l3s_gclk", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l3 s -> l3 main*/ -struct omap_hwmod_ocp_if am33xx_l3_s__l3_main = { - .master = &am33xx_l3_s_hwmod, - .slave = &am33xx_l3_main_hwmod, - .clk = "l3s_gclk", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c deleted file mode 100644 index 0399055fce25..000000000000 --- a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c +++ /dev/null @@ -1,184 +0,0 @@ -/* - * - * Copyright (C) 2013 Texas Instruments Incorporated - * - * Hwmod common for AM335x and AM43x - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation version 2. - * - * This program is distributed "as is" WITHOUT ANY WARRANTY of any - * kind, whether express or implied; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include - -#include "omap_hwmod.h" -#include "cm33xx.h" -#include "prm33xx.h" -#include "omap_hwmod_33xx_43xx_common_data.h" -#include "prcm43xx.h" -#include "common.h" - -#define CLKCTRL(oh, clkctrl) ((oh).prcm.omap4.clkctrl_offs = (clkctrl)) -#define RSTCTRL(oh, rstctrl) ((oh).prcm.omap4.rstctrl_offs = (rstctrl)) -#define RSTST(oh, rstst) ((oh).prcm.omap4.rstst_offs = (rstst)) - -/* - * 'l3' class - * instance(s): l3_main, l3_s, l3_instr - */ -static struct omap_hwmod_class am33xx_l3_hwmod_class = { - .name = "l3", -}; - -struct omap_hwmod am33xx_l3_main_hwmod = { - .name = "l3_main", - .class = &am33xx_l3_hwmod_class, - .clkdm_name = "l3_clkdm", - .flags = HWMOD_INIT_NO_IDLE, - .main_clk = "l3_gclk", - .prcm = { - .omap4 = { - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - -/* l3_s */ -struct omap_hwmod am33xx_l3_s_hwmod = { - .name = "l3_s", - .class = &am33xx_l3_hwmod_class, - .clkdm_name = "l3s_clkdm", -}; - -/* l3_instr */ -struct omap_hwmod am33xx_l3_instr_hwmod = { - .name = "l3_instr", - .class = &am33xx_l3_hwmod_class, - .clkdm_name = "l3_clkdm", - .flags = HWMOD_INIT_NO_IDLE, - .main_clk = "l3_gclk", - .prcm = { - .omap4 = { - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - -/* - * 'l4' class - * instance(s): l4_ls, l4_hs, l4_wkup, l4_fw - */ -struct omap_hwmod_class am33xx_l4_hwmod_class = { - .name = "l4", -}; - -/* l4_ls */ -struct omap_hwmod am33xx_l4_ls_hwmod = { - .name = "l4_ls", - .class = &am33xx_l4_hwmod_class, - .clkdm_name = "l4ls_clkdm", - .flags = HWMOD_INIT_NO_IDLE, - .main_clk = "l4ls_gclk", - .prcm = { - .omap4 = { - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - -/* l4_wkup */ -struct omap_hwmod am33xx_l4_wkup_hwmod = { - .name = "l4_wkup", - .class = &am33xx_l4_hwmod_class, - .clkdm_name = "l4_wkup_clkdm", - .flags = HWMOD_INIT_NO_IDLE, - .prcm = { - .omap4 = { - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - -/* - * 'prcm' class - * power and reset manager (whole prcm infrastructure) - */ -static struct omap_hwmod_class am33xx_prcm_hwmod_class = { - .name = "prcm", -}; - -/* prcm */ -struct omap_hwmod am33xx_prcm_hwmod = { - .name = "prcm", - .class = &am33xx_prcm_hwmod_class, - .clkdm_name = "l4_wkup_clkdm", -}; - -/* 'smartreflex' class */ -static struct omap_hwmod_class am33xx_smartreflex_hwmod_class = { - .name = "smartreflex", -}; - -/* smartreflex0 */ -struct omap_hwmod am33xx_smartreflex0_hwmod = { - .name = "smartreflex0", - .class = &am33xx_smartreflex_hwmod_class, - .clkdm_name = "l4_wkup_clkdm", - .main_clk = "smartreflex0_fck", - .prcm = { - .omap4 = { - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - -/* smartreflex1 */ -struct omap_hwmod am33xx_smartreflex1_hwmod = { - .name = "smartreflex1", - .class = &am33xx_smartreflex_hwmod_class, - .clkdm_name = "l4_wkup_clkdm", - .main_clk = "smartreflex1_fck", - .prcm = { - .omap4 = { - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - -static void omap_hwmod_am33xx_clkctrl(void) -{ - CLKCTRL(am33xx_smartreflex0_hwmod, - AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET); - CLKCTRL(am33xx_smartreflex1_hwmod, - AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET); - CLKCTRL(am33xx_l4_ls_hwmod, AM33XX_CM_PER_L4LS_CLKCTRL_OFFSET); - CLKCTRL(am33xx_l4_wkup_hwmod, AM33XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET); - CLKCTRL(am33xx_l3_main_hwmod, AM33XX_CM_PER_L3_CLKCTRL_OFFSET); - CLKCTRL(am33xx_l3_instr_hwmod , AM33XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET); -} - -void omap_hwmod_am33xx_reg(void) -{ - omap_hwmod_am33xx_clkctrl(); -} - -static void omap_hwmod_am43xx_clkctrl(void) -{ - CLKCTRL(am33xx_smartreflex0_hwmod, - AM43XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET); - CLKCTRL(am33xx_smartreflex1_hwmod, - AM43XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET); - CLKCTRL(am33xx_l4_ls_hwmod, AM43XX_CM_PER_L4LS_CLKCTRL_OFFSET); - CLKCTRL(am33xx_l4_wkup_hwmod, AM43XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET); - CLKCTRL(am33xx_l3_main_hwmod, AM43XX_CM_PER_L3_CLKCTRL_OFFSET); -} - -void omap_hwmod_am43xx_reg(void) -{ - omap_hwmod_am43xx_clkctrl(); -} diff --git a/arch/arm/mach-omap2/omap_hwmod_43xx_data.c b/arch/arm/mach-omap2/omap_hwmod_43xx_data.c deleted file mode 100644 index b288d113efcf..000000000000 --- a/arch/arm/mach-omap2/omap_hwmod_43xx_data.c +++ /dev/null @@ -1,81 +0,0 @@ -/* - * Copyright (C) 2013 Texas Instruments Incorporated - * - * Hwmod present only in AM43x and those that differ other than register - * offsets as compared to AM335x. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation version 2. - * - * This program is distributed "as is" WITHOUT ANY WARRANTY of any - * kind, whether express or implied; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "omap_hwmod.h" -#include "omap_hwmod_33xx_43xx_common_data.h" -#include "prcm43xx.h" -#include "omap_hwmod_common_data.h" - -/* IP blocks */ -static struct omap_hwmod am43xx_l4_hs_hwmod = { - .name = "l4_hs", - .class = &am33xx_l4_hwmod_class, - .clkdm_name = "l3_clkdm", - .flags = HWMOD_INIT_NO_IDLE, - .main_clk = "l4hs_gclk", - .prcm = { - .omap4 = { - .clkctrl_offs = AM43XX_CM_PER_L4HS_CLKCTRL_OFFSET, - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - -/* Interfaces */ - -static struct omap_hwmod_ocp_if am43xx_l3_main__l4_hs = { - .master = &am33xx_l3_main_hwmod, - .slave = &am43xx_l4_hs_hwmod, - .clk = "l3s_gclk", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -static struct omap_hwmod_ocp_if am43xx_l4_wkup__smartreflex0 = { - .master = &am33xx_l4_wkup_hwmod, - .slave = &am33xx_smartreflex0_hwmod, - .clk = "sys_clkin_ck", - .user = OCP_USER_MPU, -}; - -static struct omap_hwmod_ocp_if am43xx_l4_wkup__smartreflex1 = { - .master = &am33xx_l4_wkup_hwmod, - .slave = &am33xx_smartreflex1_hwmod, - .clk = "sys_clkin_ck", - .user = OCP_USER_MPU, -}; - -static struct omap_hwmod_ocp_if *am43xx_hwmod_ocp_ifs[] __initdata = { - &am33xx_l3_s__l4_ls, - &am33xx_l3_s__l4_wkup, - &am43xx_l3_main__l4_hs, - &am33xx_l3_main__l3_s, - &am33xx_l3_main__l3_instr, - &am33xx_l3_s__l3_main, - &am43xx_l4_wkup__smartreflex0, - &am43xx_l4_wkup__smartreflex1, - NULL, -}; - -int __init am43xx_hwmod_init(void) -{ - int ret; - - omap_hwmod_am43xx_reg(); - omap_hwmod_init(); - ret = omap_hwmod_register_links(am43xx_hwmod_ocp_ifs); - - return ret; -} -- cgit v1.2.3-59-g8ed1b From be5cd39a5e2cfa9cd78ccd00e7886029e21ceaf1 Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Mon, 7 Sep 2020 12:52:46 +0300 Subject: ARM: dts: dra7: add second SHA instance DRA7 SoC has two SHA instances, add the missing second one under the main dts file. Signed-off-by: Tero Kristo Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/dra7.dtsi | 34 ++++++++++++++++++++++++++++++++-- 1 file changed, 32 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index 4e1bbc0198eb..6ba6a1b50e00 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -932,7 +932,7 @@ }; }; - sham_target: target-module@4b101000 { + sham1_target: target-module@4b101000 { compatible = "ti,sysc-omap3-sham", "ti,sysc"; reg = <0x4b101100 0x4>, <0x4b101110 0x4>, @@ -951,7 +951,7 @@ #size-cells = <1>; ranges = <0x0 0x4b101000 0x1000>; - sham: sham@0 { + sham1: sham@0 { compatible = "ti,omap5-sham"; reg = <0 0x300>; interrupts = ; @@ -962,6 +962,36 @@ }; }; + sham2_target: target-module@42701000 { + compatible = "ti,sysc-omap3-sham", "ti,sysc"; + reg = <0x42701100 0x4>, + <0x42701110 0x4>, + <0x42701114 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */ + clocks = <&l4sec_clkctrl DRA7_L4SEC_SHAM2_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x42701000 0x1000>; + + sham2: sham@0 { + compatible = "ti,omap5-sham"; + reg = <0 0x300>; + interrupts = ; + dmas = <&edma_xbar 165 0>; + dma-names = "rx"; + clocks = <&l3_iclk_div>; + clock-names = "fck"; + }; + }; + opp_supply_mpu: opp-supply@4a003b20 { compatible = "ti,omap5-opp-supply"; reg = <0x4a003b20 0xc>; -- cgit v1.2.3-59-g8ed1b From 02564e1ad77e5fe1bbae87ed8490dc503c6f9570 Mon Sep 17 00:00:00 2001 From: David Lechner Date: Mon, 12 Oct 2020 16:12:27 -0500 Subject: ARM: dts: am33xx: Add nodes for eQEP This adds new nodes for the Texas Instruments Enhanced Quadrature Encoder Pulse (eQEP) module in the PWM subsystem on AM33XX. Signed-off-by: David Lechner Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am33xx-l4.dtsi | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/am33xx-l4.dtsi b/arch/arm/boot/dts/am33xx-l4.dtsi index ea20e4bdf040..cb164dfec56d 100644 --- a/arch/arm/boot/dts/am33xx-l4.dtsi +++ b/arch/arm/boot/dts/am33xx-l4.dtsi @@ -1923,6 +1923,15 @@ status = "disabled"; }; + eqep0: counter@180 { + compatible = "ti,am3352-eqep"; + reg = <0x180 0x80>; + clocks = <&l4ls_gclk>; + clock-names = "sysclkout"; + interrupts = <79>; + status = "disabled"; + }; + ehrpwm0: pwm@200 { compatible = "ti,am3352-ehrpwm", "ti,am33xx-ehrpwm"; @@ -1975,6 +1984,15 @@ status = "disabled"; }; + eqep1: counter@180 { + compatible = "ti,am3352-eqep"; + reg = <0x180 0x80>; + clocks = <&l4ls_gclk>; + clock-names = "sysclkout"; + interrupts = <88>; + status = "disabled"; + }; + ehrpwm1: pwm@200 { compatible = "ti,am3352-ehrpwm", "ti,am33xx-ehrpwm"; @@ -2027,6 +2045,15 @@ status = "disabled"; }; + eqep2: counter@180 { + compatible = "ti,am3352-eqep"; + reg = <0x180 0x80>; + clocks = <&l4ls_gclk>; + clock-names = "sysclkout"; + interrupts = <89>; + status = "disabled"; + }; + ehrpwm2: pwm@200 { compatible = "ti,am3352-ehrpwm", "ti,am33xx-ehrpwm"; -- cgit v1.2.3-59-g8ed1b From 672081b5dd94a4f81e545c79c96e3a1dfdffd2f1 Mon Sep 17 00:00:00 2001 From: David Lechner Date: Mon, 12 Oct 2020 16:12:28 -0500 Subject: ARM: dts: am335x-boneblue: Enable eQEP This enables the Enhanced Quadrature Encoder Pulse (eQEP) module for connectors E1, E2 and E3 on BeagleBone Blue. Signed-off-by: David Lechner Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am335x-boneblue.dts | 54 +++++++++++++++++++++++++++++++++++ 1 file changed, 54 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/am335x-boneblue.dts b/arch/arm/boot/dts/am335x-boneblue.dts index c696d57cf364..69acaf4ea0f3 100644 --- a/arch/arm/boot/dts/am335x-boneblue.dts +++ b/arch/arm/boot/dts/am335x-boneblue.dts @@ -241,6 +241,30 @@ AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_OUTPUT, MUX_MODE7) /* (M16) gmii1_rxd0.gpio2[21] */ >; }; + + /* E1 */ + eqep0_pins: pinmux_eqep0_pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_MCASP0_AXR0, PIN_INPUT, MUX_MODE1) /* (B12) mcasp0_aclkr.eQEP0A_in */ + AM33XX_PADCONF(AM335X_PIN_MCASP0_FSR, PIN_INPUT, MUX_MODE1) /* (C13) mcasp0_fsr.eQEP0B_in */ + >; + }; + + /* E2 */ + eqep1_pins: pinmux_eqep1_pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_INPUT, MUX_MODE2) /* (V2) lcd_data12.eQEP1A_in */ + AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_INPUT, MUX_MODE2) /* (V3) lcd_data13.eQEP1B_in */ + >; + }; + + /* E3 */ + eqep2_pins: pinmux_eqep2_pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_INPUT, MUX_MODE4) /* (T12) gpmc_ad12.eQEP2A_in */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT, MUX_MODE4) /* (R12) gpmc_ad13.eQEP2B_in */ + >; + }; }; &uart0 { @@ -419,3 +443,33 @@ line-name = "LS_BUF_EN"; }; }; + +&epwmss0 { + status = "okay"; +}; + +&eqep0 { + pinctrl-names = "default"; + pinctrl-0 = <&eqep0_pins>; + status = "okay"; +}; + +&epwmss1 { + status = "okay"; +}; + +&eqep1 { + pinctrl-names = "default"; + pinctrl-0 = <&eqep1_pins>; + status = "okay"; +}; + +&epwmss2 { + status = "okay"; +}; + +&eqep2 { + pinctrl-names = "default"; + pinctrl-0 = <&eqep2_pins>; + status = "okay"; +}; -- cgit v1.2.3-59-g8ed1b From d7356a7ab125c3a4fee521b7530f3122bc842ac4 Mon Sep 17 00:00:00 2001 From: Alexander Shiyan Date: Wed, 11 Nov 2020 18:59:10 +0300 Subject: ARM: dts: am335x: Fix comments for AM335X_PIN_GPMC_WPN pin in GPIO mode According to AM335x datasheet pin AM335X_PIN_GPMC_WPN in MODE7 works as GPIO0[31]. Signed-off-by: Alexander Shiyan Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am335x-baltos.dtsi | 2 +- arch/arm/boot/dts/am335x-cm-t335.dts | 2 +- arch/arm/boot/dts/am335x-evm.dts | 2 +- arch/arm/boot/dts/am335x-igep0033.dtsi | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/am335x-baltos.dtsi b/arch/arm/boot/dts/am335x-baltos.dtsi index b7f64c7ba83d..3ea286180382 100644 --- a/arch/arm/boot/dts/am335x-baltos.dtsi +++ b/arch/arm/boot/dts/am335x-baltos.dtsi @@ -168,7 +168,7 @@ AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */ AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLUP, MUX_MODE7) /* gpmc_wpn.gpio0_30 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLUP, MUX_MODE7) /* gpmc_wpn.gpio0_31 */ AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT, MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */ AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_OUTPUT, MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */ AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_OUTPUT, MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */ diff --git a/arch/arm/boot/dts/am335x-cm-t335.dts b/arch/arm/boot/dts/am335x-cm-t335.dts index c6fe9db660e2..36d963db4026 100644 --- a/arch/arm/boot/dts/am335x-cm-t335.dts +++ b/arch/arm/boot/dts/am335x-cm-t335.dts @@ -122,7 +122,7 @@ AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE0) - /* gpmc_wpn.gpio0_30 */ + /* gpmc_wpn.gpio0_31 */ AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLUP, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_OUTPUT, MUX_MODE0) diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts index 12dffccd1ffd..7c6f2c11f0e1 100644 --- a/arch/arm/boot/dts/am335x-evm.dts +++ b/arch/arm/boot/dts/am335x-evm.dts @@ -229,7 +229,7 @@ AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLUP, MUX_MODE7) /* gpmc_wpn.gpio0_30 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLUP, MUX_MODE7) /* gpmc_wpn.gpio0_31 */ AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_OUTPUT, MUX_MODE0) diff --git a/arch/arm/boot/dts/am335x-igep0033.dtsi b/arch/arm/boot/dts/am335x-igep0033.dtsi index c9f354fc984a..7ec23d47a429 100644 --- a/arch/arm/boot/dts/am335x-igep0033.dtsi +++ b/arch/arm/boot/dts/am335x-igep0033.dtsi @@ -70,7 +70,7 @@ AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLUP, MUX_MODE7) /* gpmc_wpn.gpio0_30 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLUP, MUX_MODE7) /* gpmc_wpn.gpio0_31 */ AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_OUTPUT, MUX_MODE0) -- cgit v1.2.3-59-g8ed1b From 38c212c90bf172547dc7df7c11fcaacef2c78696 Mon Sep 17 00:00:00 2001 From: Corentin Labbe Date: Thu, 12 Nov 2020 20:26:52 +0000 Subject: ARM: configs: sunxi: enable Realtek PHY Lot of sunxi boards has a Realtek PHY, so let's enable it. Signed-off-by: Corentin Labbe Signed-off-by: Maxime Ripard Acked-by: Jernej Skrabec Link: https://lore.kernel.org/r/20201112202652.27676-1-clabbe@baylibre.com --- arch/arm/configs/sunxi_defconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm') diff --git a/arch/arm/configs/sunxi_defconfig b/arch/arm/configs/sunxi_defconfig index 244126172fd6..05f7f4ed8ded 100644 --- a/arch/arm/configs/sunxi_defconfig +++ b/arch/arm/configs/sunxi_defconfig @@ -51,6 +51,7 @@ CONFIG_STMMAC_ETH=y # CONFIG_NET_VENDOR_VIA is not set # CONFIG_NET_VENDOR_WIZNET is not set CONFIG_MICREL_PHY=y +CONFIG_REALTEK_PHY=y # CONFIG_WLAN is not set CONFIG_INPUT_EVDEV=y CONFIG_KEYBOARD_SUN4I_LRADC=y -- cgit v1.2.3-59-g8ed1b From f9135aaf2767500dee419c03640f7a3784b56559 Mon Sep 17 00:00:00 2001 From: Martin Jücker Date: Fri, 13 Nov 2020 22:25:26 +0100 Subject: ARM: exynos: extend cpuidle support to P4 Note boards MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The P4 Note family supports cpuidle, so allow it to make use of this feature. Signed-off-by: Martin Jücker Link: https://lore.kernel.org/r/20201113212525.13455-6-martin.juecker@gmail.com Signed-off-by: Krzysztof Kozlowski --- arch/arm/mach-exynos/exynos.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c index a99d8eba4bb3..25b01da4771b 100644 --- a/arch/arm/mach-exynos/exynos.c +++ b/arch/arm/mach-exynos/exynos.c @@ -177,7 +177,8 @@ static void __init exynos_dt_machine_init(void) if (of_machine_is_compatible("samsung,exynos4210") || (of_machine_is_compatible("samsung,exynos4412") && (of_machine_is_compatible("samsung,trats2") || - of_machine_is_compatible("samsung,midas"))) || + of_machine_is_compatible("samsung,midas") || + of_machine_is_compatible("samsung,p4note"))) || of_machine_is_compatible("samsung,exynos3250") || of_machine_is_compatible("samsung,exynos5250")) platform_device_register(&exynos_cpuidle); -- cgit v1.2.3-59-g8ed1b From d8f0ddc8387757957c4f696e67b3332695f6525e Mon Sep 17 00:00:00 2001 From: Martin Jücker Date: Fri, 13 Nov 2020 22:25:24 +0100 Subject: ARM: defconfig: add STMPE ADC driver for P4 Note MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Enable the STMPE ADC driver for the P4 Note device family in exynos and multi_v7 defconfigs. Signed-off-by: Martin Jücker Link: https://lore.kernel.org/r/20201113212525.13455-4-martin.juecker@gmail.com Signed-off-by: Krzysztof Kozlowski --- arch/arm/configs/exynos_defconfig | 3 +++ arch/arm/configs/multi_v7_defconfig | 2 ++ 2 files changed, 5 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/configs/exynos_defconfig b/arch/arm/configs/exynos_defconfig index f0cef76a3ab9..ee71bcd247a0 100644 --- a/arch/arm/configs/exynos_defconfig +++ b/arch/arm/configs/exynos_defconfig @@ -177,6 +177,8 @@ CONFIG_MFD_MAX77693=y CONFIG_MFD_MAX8997=y CONFIG_MFD_MAX8998=y CONFIG_MFD_SEC_CORE=y +CONFIG_MFD_STMPE=y +CONFIG_STMPE_I2C=y CONFIG_MFD_TPS65090=y CONFIG_REGULATOR=y CONFIG_REGULATOR_FIXED_VOLTAGE=y @@ -322,6 +324,7 @@ CONFIG_EXTCON_MAX77693=y CONFIG_EXTCON_MAX8997=y CONFIG_IIO=y CONFIG_EXYNOS_ADC=y +CONFIG_STMPE_ADC=y CONFIG_CM36651=y CONFIG_AK8975=y CONFIG_PWM=y diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig index 6ab0945fb27c..a33a0b8eda20 100644 --- a/arch/arm/configs/multi_v7_defconfig +++ b/arch/arm/configs/multi_v7_defconfig @@ -558,6 +558,7 @@ CONFIG_MFD_RK808=y CONFIG_MFD_RN5T618=y CONFIG_MFD_SEC_CORE=y CONFIG_MFD_STMPE=y +CONFIG_STMPE_I2C=y CONFIG_MFD_PALMAS=y CONFIG_MFD_TPS65090=y CONFIG_MFD_TPS65217=y @@ -1026,6 +1027,7 @@ CONFIG_AT91_SAMA5D2_ADC=m CONFIG_BERLIN2_ADC=m CONFIG_CPCAP_ADC=m CONFIG_EXYNOS_ADC=m +CONFIG_STMPE_ADC=m CONFIG_MESON_SARADC=m CONFIG_ROCKCHIP_SARADC=m CONFIG_STM32_ADC_CORE=m -- cgit v1.2.3-59-g8ed1b From 7e8af057bd9b3d76bd343794e71c20e8dd462372 Mon Sep 17 00:00:00 2001 From: Martin Jücker Date: Fri, 13 Nov 2020 22:25:25 +0100 Subject: ARM: exynos_defconfig: compile Atmel MXT touchscreeen as module MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The Atmel MXT touchscreen can load firmware and settings from the /lib/firmware directory, it makes sense to have it as a module to have more control over the loading process. Signed-off-by: Martin Jücker Link: https://lore.kernel.org/r/20201113212525.13455-5-martin.juecker@gmail.com Signed-off-by: Krzysztof Kozlowski --- arch/arm/configs/exynos_defconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/configs/exynos_defconfig b/arch/arm/configs/exynos_defconfig index ee71bcd247a0..513f56b3c059 100644 --- a/arch/arm/configs/exynos_defconfig +++ b/arch/arm/configs/exynos_defconfig @@ -127,7 +127,7 @@ CONFIG_KEYBOARD_CROS_EC=y # CONFIG_MOUSE_PS2 is not set CONFIG_MOUSE_CYAPA=y CONFIG_INPUT_TOUCHSCREEN=y -CONFIG_TOUCHSCREEN_ATMEL_MXT=y +CONFIG_TOUCHSCREEN_ATMEL_MXT=m CONFIG_TOUCHSCREEN_MMS114=y CONFIG_INPUT_MISC=y CONFIG_INPUT_MAX77693_HAPTIC=y -- cgit v1.2.3-59-g8ed1b From f48b5050c301f7235ef61d8cbbbf0410a5e0245f Mon Sep 17 00:00:00 2001 From: Martin Jücker Date: Fri, 13 Nov 2020 22:25:23 +0100 Subject: ARM: dts: exynos: add Samsung's Exynos4412-based P4 Note boards MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The P4 Note family contains a couple of variants of the Galaxy Note 10.1 tablet with mainly different modems. The GT-N8010/GT-N8013 is the WiFi only version. Signed-off-by: Martin Jücker Link: https://lore.kernel.org/r/20201113212525.13455-3-martin.juecker@gmail.com Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/exynos4412-p4note-n8010.dts | 17 + arch/arm/boot/dts/exynos4412-p4note.dtsi | 1132 +++++++++++++++++++++++++ 3 files changed, 1150 insertions(+) create mode 100644 arch/arm/boot/dts/exynos4412-p4note-n8010.dts create mode 100644 arch/arm/boot/dts/exynos4412-p4note.dtsi (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index ce66ffd5a1bb..55ffee2b20f8 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -197,6 +197,7 @@ dtb-$(CONFIG_ARCH_EXYNOS4) += \ exynos4412-odroidx.dtb \ exynos4412-odroidx2.dtb \ exynos4412-origen.dtb \ + exynos4412-p4note-n8010.dtb \ exynos4412-smdk4412.dtb \ exynos4412-tiny4412.dtb \ exynos4412-trats2.dtb diff --git a/arch/arm/boot/dts/exynos4412-p4note-n8010.dts b/arch/arm/boot/dts/exynos4412-p4note-n8010.dts new file mode 100644 index 000000000000..9f559425bd2c --- /dev/null +++ b/arch/arm/boot/dts/exynos4412-p4note-n8010.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Samsung's Galaxy Note 10.1 - N801x (wifi only version) + * + * Copyright (c) 2013 Samsung Electronics Co., Ltd. + * http://www.samsung.com + */ + +/dts-v1/; +#include "exynos4412-p4note.dtsi" + +/ { + model = "Samsung Galaxy Note 10.1 (GT-N8010/N8013) based on Exynos4412"; + compatible = "samsung,n8010", "samsung,p4note", "samsung,exynos4412", "samsung,exynos4"; + + /* this is the base variant without any kind of modem */ +}; diff --git a/arch/arm/boot/dts/exynos4412-p4note.dtsi b/arch/arm/boot/dts/exynos4412-p4note.dtsi new file mode 100644 index 000000000000..0f8d4164a977 --- /dev/null +++ b/arch/arm/boot/dts/exynos4412-p4note.dtsi @@ -0,0 +1,1132 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Samsung's Exynos4412 based p4note device family base DT. + * Based on exynos4412-midas.dtsi. + * + * Copyright (c) 2013 Samsung Electronics Co., Ltd. + * http://www.samsung.com + */ + +/dts-v1/; +#include "exynos4412.dtsi" +#include "exynos4412-ppmu-common.dtsi" + +#include +#include +#include +#include +#include + +/ { + compatible = "samsung,p4note", "samsung,exynos4412", "samsung,exynos4"; + + memory@40000000 { + device_type = "memory"; + reg = <0x40000000 0x80000000>; + }; + + chosen { + stdout-path = &serial_2; + }; + + firmware@204f000 { + compatible = "samsung,secure-firmware"; + reg = <0x0204F000 0x1000>; + }; + + fixed-rate-clocks { + xxti { + compatible = "samsung,clock-xxti"; + clock-frequency = <0>; + }; + + xusbxti { + compatible = "samsung,clock-xusbxti"; + clock-frequency = <24000000>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&gpio_keys>; + + key-down { + gpios = <&gpx2 2 GPIO_ACTIVE_LOW>; + linux,code = ; + label = "volume down"; + debounce-interval = <10>; + }; + + key-up { + gpios = <&gpx3 3 GPIO_ACTIVE_LOW>; + linux,code = ; + label = "volume up"; + debounce-interval = <10>; + }; + + key-power { + gpios = <&gpx2 7 GPIO_ACTIVE_LOW>; + linux,code = ; + label = "power"; + debounce-interval = <10>; + wakeup-source; + }; + }; + + voltage-regulator-1 { + compatible = "regulator-fixed"; + regulator-name = "TSP_LDO1"; + pinctrl-names = "default"; + pinctrl-0 = <&tsp_reg_gpio_1>; + gpios = <&gpm4 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + voltage-regulator-2 { + compatible = "regulator-fixed"; + regulator-name = "TSP_LDO2"; + pinctrl-names = "default"; + pinctrl-0 = <&tsp_reg_gpio_2>; + gpios = <&gpb 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + voltage-regulator-3 { + compatible = "regulator-fixed"; + regulator-name = "TSP_LDO3"; + pinctrl-names = "default"; + pinctrl-0 = <&tsp_reg_gpio_3>; + gpios = <&gpb 7 GPIO_ACTIVE_HIGH>; + startup-delay-us = <20000>; + enable-active-high; + regulator-always-on; + }; + + wlan_pwrseq: sdhci3-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpm3 5 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&wifi_reset>; + pinctrl-names = "default"; + clocks = <&max77686 MAX77686_CLK_PMIC>; + clock-names = "ext_clock"; + }; + + i2c-gpio-1 { + compatible = "i2c-gpio"; + sda-gpios = <&gpy2 4 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpy2 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + i2c-gpio,delay-us = <2>; + #address-cells = <1>; + #size-cells = <0>; + + magnetometer@c { + compatible = "asahi-kasei,ak8975"; + reg = <0x0c>; + pinctrl-0 = <&ak8975_irq>; + pinctrl-names = "default"; + interrupt-parent = <&gpm4>; + interrupts = <7 IRQ_TYPE_EDGE_RISING>; + }; + }; + + i2c-gpio-2 { + compatible = "i2c-gpio"; + sda-gpios = <&gpy0 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpy0 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + i2c-gpio,delay-us = <2>; + #address-cells = <1>; + #size-cells = <0>; + + fuel-gauge@36 { + compatible = "maxim,max17042"; + reg = <0x36>; + pinctrl-0 = <&fuel_alert_irq>; + pinctrl-names = "default"; + interrupt-parent = <&gpx2>; + interrupts = <3 IRQ_TYPE_EDGE_FALLING>; + maxim,rsns-microohm = <10000>; + maxim,over-heat-temp = <600>; + maxim,over-volt = <4300>; + }; + }; + + i2c-gpio-3 { + compatible = "i2c-gpio"; + sda-gpios = <&gpm4 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpm4 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + i2c-gpio,delay-us = <5>; + #address-cells = <1>; + #size-cells = <0>; + + adc@41 { + compatible = "st,stmpe811"; + reg = <0x41>; + pinctrl-0 = <&stmpe_adc_irq>; + pinctrl-names = "default"; + interrupt-parent = <&gpx0>; + interrupts = <1 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + irq-trigger = <0x1>; + st,adc-freq = <3>; + st,mod-12b = <1>; + st,ref-sel = <0>; + st,sample-time = <3>; + + stmpe_adc { + compatible = "st,stmpe-adc"; + #io-channel-cells = <1>; + st,norequest-mask = <0x2F>; + }; + }; + }; +}; + +&adc { + vdd-supply = <&ldo3_reg>; + /* not verified */ + status = "okay"; +}; + +&bus_dmc { + devfreq-events = <&ppmu_dmc0_3>, <&ppmu_dmc1_3>; + vdd-supply = <&buck1_reg>; + status = "okay"; +}; + +&bus_acp { + devfreq = <&bus_dmc>; + status = "okay"; +}; + +&bus_c2c { + devfreq = <&bus_dmc>; + status = "okay"; +}; + +&bus_leftbus { + devfreq-events = <&ppmu_leftbus_3>, <&ppmu_rightbus_3>; + vdd-supply = <&buck3_reg>; + status = "okay"; +}; + +&bus_rightbus { + devfreq = <&bus_leftbus>; + status = "okay"; +}; + +&bus_display { + devfreq = <&bus_leftbus>; + status = "okay"; +}; + +&bus_fsys { + devfreq = <&bus_leftbus>; + status = "okay"; +}; + +&bus_peri { + devfreq = <&bus_leftbus>; + status = "okay"; +}; + +&bus_mfc { + devfreq = <&bus_leftbus>; + status = "okay"; +}; + +&cpu0 { + cpu0-supply = <&buck2_reg>; +}; + +&cpu_thermal { + cooling-maps { + map0 { + /* Corresponds to 800MHz at freq_table */ + cooling-device = <&cpu0 7 7>, <&cpu1 7 7>, + <&cpu2 7 7>, <&cpu3 7 7>; + }; + map1 { + /* Corresponds to 200MHz at freq_table */ + cooling-device = <&cpu0 13 13>, <&cpu1 13 13>, + <&cpu2 13 13>, <&cpu3 13 13>; + }; + }; +}; + +&exynos_usbphy { + status = "okay"; +}; + +&fimd { + pinctrl-0 = <&lcd_clk &lcd_data24 &pwm1_out>; + pinctrl-names = "default"; + status = "okay"; + + display-timings { + timing0 { + clock-frequency = <66666666>; + hactive = <1280>; + vactive = <800>; + hfront-porch = <18>; + hback-porch = <36>; + hsync-len = <16>; + vback-porch = <16>; + vfront-porch = <4>; + vsync-len = <3>; + hsync-active = <1>; + }; + }; +}; + +&gpu { + mali-supply = <&buck4_reg>; + status = "okay"; +}; + +&hsotg { + vusb_a-supply = <&ldo12_reg>; + dr_mode = "peripheral"; + status = "okay"; +}; + +&i2c_3 { + samsung,i2c-sda-delay = <100>; + samsung,i2c-slave-addr = <0x10>; + samsung,i2c-max-bus-freq = <400000>; + pinctrl-0 = <&i2c3_bus>; + pinctrl-names = "default"; + status = "okay"; + + touchscreen@4a { + compatible = "atmel,maxtouch"; + reg = <0x4a>; + pinctrl-0 = <&tsp_rst &tsp_irq>; + pinctrl-names = "default"; + interrupt-parent = <&gpm2>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpm0 4 GPIO_ACTIVE_HIGH>; + }; +}; + +&i2c_7 { + samsung,i2c-sda-delay = <100>; + samsung,i2c-slave-addr = <0x10>; + samsung,i2c-max-bus-freq = <400000>; + pinctrl-0 = <&i2c7_bus>; + pinctrl-names = "default"; + status = "okay"; + + max77686: pmic@9 { + compatible = "maxim,max77686"; + interrupt-parent = <&gpx0>; + interrupts = <7 IRQ_TYPE_NONE>; + pinctrl-0 = <&max77686_irq>; + pinctrl-names = "default"; + reg = <0x09>; + #clock-cells = <1>; + + voltage-regulators { + ldo1_reg: LDO1 { + regulator-name = "ldo1"; + regulator-always-on; + }; + + ldo2_reg: LDO2 { + regulator-name = "ldo2"; + regulator-always-on; + }; + + /* WM8994 audio */ + ldo3_reg: LDO3 { + regulator-name = "VCC_1.8V_AP"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + ldo4_reg: LDO4 { + regulator-name = "ldo4"; + regulator-always-on; + }; + + ldo5_reg: LDO5 { + regulator-name = "VCC_1.8V_IO"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo6_reg: LDO6 { + regulator-name = "ldo6"; + regulator-always-on; + }; + + ldo7_reg: LDO7 { + regulator-name = "ldo7"; + regulator-always-on; + }; + + /* CSI IP block */ + ldo8_reg: LDO8 { + regulator-name = "VMIPI_1.0V"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + /* IR LED on/off */ + ldo9_reg: LDO9 { + regulator-name = "VLED_IC_1.9V"; + regulator-min-microvolt = <1950000>; + regulator-max-microvolt = <1950000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + /* CSI IP block */ + ldo10_reg: LDO10 { + regulator-name = "VMIPI_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + ldo11_reg: LDO11 { + regulator-name = "VABB1_1.9V"; + regulator-min-microvolt = <1950000>; + regulator-max-microvolt = <1950000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + /* USB OTG */ + ldo12_reg: LDO12 { + regulator-name = "VUOTG_3.0V"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + /* not connected */ + ldo13_reg: LDO13 { + regulator-name = "ldo13"; + }; + + ldo14_reg: LDO14 { + regulator-name = "VABB2_1.9V"; + regulator-min-microvolt = <1950000>; + regulator-max-microvolt = <1950000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo15_reg: LDO15 { + regulator-name = "ldo15"; + regulator-always-on; + }; + + ldo16_reg: LDO16 { + regulator-name = "ldo16"; + regulator-always-on; + }; + + /* not connected */ + ldo17_reg: LDO17 { + regulator-name = "ldo17"; + }; + + /* Camera ISX012 */ + ldo18_reg: LDO18 { + regulator-name = "CAM_IO_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + /* Camera S5K6A3 */ + ldo19_reg: LDO19 { + regulator-name = "VT_CORE_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + /* not connected */ + ldo20_reg: LDO20 { + regulator-name = "ldo20"; + }; + + /* MMC2 */ + ldo21_reg: LDO21 { + regulator-name = "VTF_2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + maxim,ena-gpios = <&gpy2 0 GPIO_ACTIVE_HIGH>; + }; + + /* not connected */ + ldo22_reg: LDO22 { + regulator-name = "ldo22"; + }; + + /* ADC */ + ldo23_reg: LDO23 { + regulator-name = "VDD_ADC_3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + /* Camera S5K6A3 */ + ldo24_reg: LDO24 { + regulator-name = "CAM_A2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo25_reg: LDO25 { + regulator-name = "VLED_3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + /* Camera ISX012 */ + ldo26_reg: LDO26 { + regulator-name = "3MP_AF_2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + buck1_reg: BUCK1 { + regulator-name = "VDD_MIF"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1050000>; + regulator-always-on; + regulator-boot-on; + }; + + buck2_reg: BUCK2 { + regulator-name = "VDD_ARM"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + }; + + buck3_reg: BUCK3 { + regulator-name = "VDD_INT"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + regulator-boot-on; + }; + + buck4_reg: BUCK4 { + regulator-name = "VDD_G3D"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1075000>; + regulator-boot-on; + }; + + buck5_reg: BUCK5 { + regulator-name = "buck5"; + regulator-always-on; + }; + + buck6_reg: BUCK6 { + regulator-name = "buck6"; + regulator-always-on; + }; + + buck7_reg: BUCK7 { + regulator-name = "buck7"; + regulator-always-on; + }; + + /* not connected */ + buck8_reg: BUCK8 { + regulator-name = "buck8"; + }; + + buck9_reg: BUCK9 { + regulator-name = "3MP_CORE_1.2V"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&mshc_0 { + broken-cd; + non-removable; + card-detect-delay = <200>; + clock-frequency = <400000000>; + samsung,dw-mshc-ciu-div = <0>; + samsung,dw-mshc-sdr-timing = <2 3>; + samsung,dw-mshc-ddr-timing = <1 2>; + pinctrl-0 = <&sd4_clk &sd4_cmd &sd4_bus4 &sd4_bus8>; + pinctrl-names = "default"; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + status = "okay"; +}; + +&pinctrl_0 { + pinctrl-names = "default"; + pinctrl-0 = <&sleep0>; + + tsp_reg_gpio_2: tsp-reg-gpio-2 { + samsung,pins = "gpb-5"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + tsp_reg_gpio_3: tsp-reg-gpio-3 { + samsung,pins = "gpb-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + sleep0: sleep-states { + PIN_SLP(gpa0-0, INPUT, NONE); + PIN_SLP(gpa0-1, OUT0, NONE); + PIN_SLP(gpa0-2, INPUT, NONE); + PIN_SLP(gpa0-3, INPUT, UP); + PIN_SLP(gpa0-4, INPUT, NONE); + PIN_SLP(gpa0-5, INPUT, DOWN); + PIN_SLP(gpa0-6, INPUT, DOWN); + PIN_SLP(gpa0-7, INPUT, UP); + + PIN_SLP(gpa1-0, INPUT, DOWN); + PIN_SLP(gpa1-1, INPUT, DOWN); + PIN_SLP(gpa1-2, INPUT, DOWN); + PIN_SLP(gpa1-3, INPUT, DOWN); + PIN_SLP(gpa1-4, INPUT, DOWN); + PIN_SLP(gpa1-5, INPUT, DOWN); + + PIN_SLP(gpb-0, INPUT, NONE); + PIN_SLP(gpb-1, INPUT, NONE); + PIN_SLP(gpb-2, INPUT, NONE); + PIN_SLP(gpb-3, INPUT, NONE); + PIN_SLP(gpb-4, INPUT, DOWN); + PIN_SLP(gpb-5, INPUT, DOWN); + PIN_SLP(gpb-6, INPUT, DOWN); + PIN_SLP(gpb-7, INPUT, DOWN); + + PIN_SLP(gpc0-0, INPUT, DOWN); + PIN_SLP(gpc0-1, INPUT, DOWN); + PIN_SLP(gpc0-2, INPUT, DOWN); + PIN_SLP(gpc0-3, INPUT, DOWN); + PIN_SLP(gpc0-4, INPUT, DOWN); + + PIN_SLP(gpc1-0, INPUT, UP); + PIN_SLP(gpc1-1, PREV, NONE); + PIN_SLP(gpc1-2, INPUT, UP); + PIN_SLP(gpc1-3, INPUT, UP); + PIN_SLP(gpc1-4, INPUT, UP); + + PIN_SLP(gpd0-0, INPUT, DOWN); + PIN_SLP(gpd0-1, OUT0, NONE); + PIN_SLP(gpd0-2, INPUT, NONE); + PIN_SLP(gpd0-3, INPUT, NONE); + + PIN_SLP(gpd1-0, INPUT, DOWN); + PIN_SLP(gpd1-1, INPUT, DOWN); + PIN_SLP(gpd1-2, INPUT, NONE); + PIN_SLP(gpd1-3, INPUT, NONE); + + PIN_SLP(gpf0-0, OUT0, NONE); + PIN_SLP(gpf0-1, OUT0, NONE); + PIN_SLP(gpf0-2, OUT0, NONE); + PIN_SLP(gpf0-3, OUT0, NONE); + PIN_SLP(gpf0-4, OUT0, NONE); + PIN_SLP(gpf0-5, OUT0, NONE); + PIN_SLP(gpf0-6, OUT0, NONE); + PIN_SLP(gpf0-7, OUT0, NONE); + + PIN_SLP(gpf1-0, OUT0, NONE); + PIN_SLP(gpf1-1, OUT0, NONE); + PIN_SLP(gpf1-2, OUT0, NONE); + PIN_SLP(gpf1-3, OUT0, NONE); + PIN_SLP(gpf1-4, OUT0, NONE); + PIN_SLP(gpf1-5, OUT0, NONE); + PIN_SLP(gpf1-6, OUT0, NONE); + PIN_SLP(gpf1-7, OUT0, NONE); + + PIN_SLP(gpf2-0, OUT0, NONE); + PIN_SLP(gpf2-1, OUT0, NONE); + PIN_SLP(gpf2-2, OUT0, NONE); + PIN_SLP(gpf2-3, OUT0, NONE); + PIN_SLP(gpf2-4, OUT0, NONE); + PIN_SLP(gpf2-5, OUT0, NONE); + PIN_SLP(gpf2-6, OUT0, NONE); + PIN_SLP(gpf2-7, OUT0, NONE); + + PIN_SLP(gpf3-0, OUT0, NONE); + PIN_SLP(gpf3-1, OUT0, NONE); + PIN_SLP(gpf3-2, OUT0, NONE); + PIN_SLP(gpf3-3, OUT0, NONE); + PIN_SLP(gpf3-4, OUT0, NONE); + PIN_SLP(gpf3-5, OUT0, NONE); + + PIN_SLP(gpj0-0, INPUT, DOWN); + PIN_SLP(gpj0-1, INPUT, DOWN); + PIN_SLP(gpj0-2, INPUT, DOWN); + PIN_SLP(gpj0-3, PREV, NONE); + PIN_SLP(gpj0-4, PREV, NONE); + PIN_SLP(gpj0-5, OUT0, NONE); + PIN_SLP(gpj0-6, OUT0, NONE); + PIN_SLP(gpj0-7, OUT0, NONE); + + PIN_SLP(gpj1-0, OUT0, NONE); + PIN_SLP(gpj1-1, INPUT, DOWN); + PIN_SLP(gpj1-2, PREV, NONE); + PIN_SLP(gpj1-3, OUT0, NONE); + }; +}; + +&pinctrl_1 { + pinctrl-names = "default"; + pinctrl-0 = <&sleep1>; + + sd3_wifi: sd3-wifi { + samsung,pins = "gpk3-3", "gpk3-4", "gpk3-5", "gpk3-6"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + bt_shutdown: bt-shutdown { + samsung,pins = "gpl0-6"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + uart_sel: uart-sel { + samsung,pins = "gpl2-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-val = <1>; + /* 0 = CP, 1 = AP (serial output) */ + }; + + tsp_rst: tsp-rst { + samsung,pins = "gpm0-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + tsp_irq: tsp-irq { + samsung,pins = "gpm2-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + wifi_reset: wifi-reset { + samsung,pins = "gpm3-5"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + tsp_reg_gpio_1: tsp-reg-gpio-1 { + samsung,pins = "gpm4-5"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + ak8975_irq: ak8975-irq { + samsung,pins = "gpm4-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + stmpe_adc_irq: stmpe-adc-irq { + samsung,pins = "gpx0-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + max77686_irq: max77686-irq { + samsung,pins = "gpx0-7"; + samsung,pin-pud = ; + }; + + gpio_keys: gpio-keys { + samsung,pins = "gpx2-2", "gpx2-7", "gpx3-3"; + samsung,pin-pud = ; + }; + + fuel_alert_irq: fuel-alert-irq { + samsung,pins = "gpx2-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + wifi_host_wake: wifi-host-wake { + samsung,pins = "gpx2-5"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + bt_host_wakeup: bt-host-wakeup { + samsung,pins = "gpx2-6"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + bt_device_wakeup: bt-device-wakeup { + samsung,pins = "gpx3-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + sdhci2_cd: sdhci2-cd { + samsung,pins = "gpx3-4"; + samsung,pin-pud = ; + }; + + sleep1: sleep-states { + PIN_SLP(gpk0-0, PREV, NONE); + PIN_SLP(gpk0-1, PREV, NONE); + PIN_SLP(gpk0-2, PREV, NONE); + PIN_SLP(gpk0-3, PREV, NONE); + PIN_SLP(gpk0-4, PREV, NONE); + PIN_SLP(gpk0-5, PREV, NONE); + PIN_SLP(gpk0-6, PREV, NONE); + + PIN_SLP(gpk1-0, INPUT, DOWN); + PIN_SLP(gpk1-1, INPUT, DOWN); + PIN_SLP(gpk1-2, INPUT, DOWN); + PIN_SLP(gpk1-3, PREV, NONE); + PIN_SLP(gpk1-4, PREV, NONE); + PIN_SLP(gpk1-5, PREV, NONE); + PIN_SLP(gpk1-6, PREV, NONE); + + PIN_SLP(gpk2-0, INPUT, DOWN); + PIN_SLP(gpk2-1, INPUT, DOWN); + PIN_SLP(gpk2-2, INPUT, DOWN); + PIN_SLP(gpk2-3, INPUT, DOWN); + PIN_SLP(gpk2-4, INPUT, DOWN); + PIN_SLP(gpk2-5, INPUT, DOWN); + PIN_SLP(gpk2-6, INPUT, DOWN); + + PIN_SLP(gpk3-0, OUT0, NONE); + PIN_SLP(gpk3-1, INPUT, NONE); + PIN_SLP(gpk3-2, INPUT, DOWN); + PIN_SLP(gpk3-3, INPUT, NONE); + PIN_SLP(gpk3-4, INPUT, NONE); + PIN_SLP(gpk3-5, INPUT, NONE); + PIN_SLP(gpk3-6, INPUT, NONE); + + PIN_SLP(gpl0-0, OUT0, NONE); + PIN_SLP(gpl0-1, INPUT, NONE); + PIN_SLP(gpl0-2, INPUT, NONE); + PIN_SLP(gpl0-3, INPUT, DOWN); + PIN_SLP(gpl0-4, PREV, NONE); + PIN_SLP(gpl0-6, PREV, NONE); + + PIN_SLP(gpl1-0, OUT0, NONE); + PIN_SLP(gpl1-1, OUT0, NONE); + + PIN_SLP(gpl2-0, INPUT, DOWN); + PIN_SLP(gpl2-1, INPUT, DOWN); + PIN_SLP(gpl2-2, INPUT, DOWN); + PIN_SLP(gpl2-3, INPUT, DOWN); + PIN_SLP(gpl2-4, OUT0, NONE); + PIN_SLP(gpl2-5, INPUT, DOWN); + PIN_SLP(gpl2-6, PREV, NONE); + PIN_SLP(gpl2-7, PREV, NONE); + + PIN_SLP(gpm0-0, PREV, NONE); + PIN_SLP(gpm0-1, OUT0, NONE); + PIN_SLP(gpm0-2, INPUT, DOWN); + PIN_SLP(gpm0-3, INPUT, NONE); + PIN_SLP(gpm0-4, OUT0, NONE); + PIN_SLP(gpm0-5, OUT0, NONE); + PIN_SLP(gpm0-6, INPUT, DOWN); + PIN_SLP(gpm0-7, OUT0, NONE); + + PIN_SLP(gpm1-0, INPUT, NONE); + PIN_SLP(gpm1-1, INPUT, NONE); + PIN_SLP(gpm1-2, INPUT, NONE); + PIN_SLP(gpm1-3, INPUT, NONE); + PIN_SLP(gpm1-4, INPUT, NONE); + PIN_SLP(gpm1-5, INPUT, NONE); + PIN_SLP(gpm1-6, INPUT, DOWN); + + PIN_SLP(gpm2-0, INPUT, NONE); + PIN_SLP(gpm2-1, INPUT, NONE); + PIN_SLP(gpm2-2, OUT0, NONE); + PIN_SLP(gpm2-3, OUT0, DOWN); + PIN_SLP(gpm2-4, INPUT, DOWN); + + PIN_SLP(gpm3-0, PREV, NONE); + PIN_SLP(gpm3-1, PREV, NONE); + PIN_SLP(gpm3-2, PREV, NONE); + PIN_SLP(gpm3-3, OUT1, NONE); + PIN_SLP(gpm3-4, OUT0, DOWN); + PIN_SLP(gpm3-5, PREV, NONE); + PIN_SLP(gpm3-6, PREV, NONE); + PIN_SLP(gpm3-7, OUT0, NONE); + + PIN_SLP(gpm4-0, INPUT, NONE); + PIN_SLP(gpm4-1, INPUT, NONE); + PIN_SLP(gpm4-2, INPUT, DOWN); + PIN_SLP(gpm4-3, INPUT, DOWN); + PIN_SLP(gpm4-4, PREV, NONE); + PIN_SLP(gpm4-5, OUT0, NONE); + PIN_SLP(gpm4-6, OUT0, NONE); + PIN_SLP(gpm4-7, INPUT, DOWN); + + PIN_SLP(gpy0-0, INPUT, DOWN); + PIN_SLP(gpy0-1, INPUT, DOWN); + PIN_SLP(gpy0-2, INPUT, NONE); + PIN_SLP(gpy0-3, INPUT, NONE); + PIN_SLP(gpy0-4, INPUT, NONE); + PIN_SLP(gpy0-5, INPUT, NONE); + + PIN_SLP(gpy1-0, INPUT, DOWN); + PIN_SLP(gpy1-1, INPUT, DOWN); + PIN_SLP(gpy1-2, INPUT, DOWN); + PIN_SLP(gpy1-3, INPUT, DOWN); + + PIN_SLP(gpy2-0, PREV, NONE); + PIN_SLP(gpy2-1, INPUT, DOWN); + PIN_SLP(gpy2-2, INPUT, NONE); + PIN_SLP(gpy2-3, INPUT, NONE); + PIN_SLP(gpy2-4, INPUT, NONE); + PIN_SLP(gpy2-5, INPUT, NONE); + + PIN_SLP(gpy3-0, INPUT, DOWN); + PIN_SLP(gpy3-1, INPUT, DOWN); + PIN_SLP(gpy3-2, INPUT, DOWN); + PIN_SLP(gpy3-3, INPUT, DOWN); + PIN_SLP(gpy3-4, INPUT, DOWN); + PIN_SLP(gpy3-5, INPUT, DOWN); + PIN_SLP(gpy3-6, INPUT, DOWN); + PIN_SLP(gpy3-7, INPUT, DOWN); + + PIN_SLP(gpy4-0, INPUT, DOWN); + PIN_SLP(gpy4-1, INPUT, DOWN); + PIN_SLP(gpy4-2, INPUT, DOWN); + PIN_SLP(gpy4-3, INPUT, DOWN); + PIN_SLP(gpy4-4, INPUT, DOWN); + PIN_SLP(gpy4-5, INPUT, DOWN); + PIN_SLP(gpy4-6, INPUT, DOWN); + PIN_SLP(gpy4-7, INPUT, DOWN); + + PIN_SLP(gpy5-0, INPUT, DOWN); + PIN_SLP(gpy5-1, INPUT, DOWN); + PIN_SLP(gpy5-2, INPUT, DOWN); + PIN_SLP(gpy5-3, INPUT, DOWN); + PIN_SLP(gpy5-4, INPUT, DOWN); + PIN_SLP(gpy5-5, INPUT, DOWN); + PIN_SLP(gpy5-6, INPUT, DOWN); + PIN_SLP(gpy5-7, INPUT, DOWN); + + PIN_SLP(gpy6-0, INPUT, DOWN); + PIN_SLP(gpy6-1, INPUT, DOWN); + PIN_SLP(gpy6-2, INPUT, DOWN); + PIN_SLP(gpy6-3, INPUT, DOWN); + PIN_SLP(gpy6-4, INPUT, DOWN); + PIN_SLP(gpy6-5, INPUT, DOWN); + PIN_SLP(gpy6-6, INPUT, DOWN); + PIN_SLP(gpy6-7, INPUT, DOWN); + }; +}; + +&pinctrl_2 { + pinctrl-names = "default"; + pinctrl-0 = <&sleep2>; + + sleep2: sleep-states { + PIN_SLP(gpz-0, INPUT, DOWN); + PIN_SLP(gpz-1, INPUT, DOWN); + PIN_SLP(gpz-2, INPUT, DOWN); + PIN_SLP(gpz-3, INPUT, DOWN); + PIN_SLP(gpz-4, INPUT, DOWN); + PIN_SLP(gpz-5, INPUT, DOWN); + PIN_SLP(gpz-6, INPUT, DOWN); + }; +}; + +&pinctrl_3 { + pinctrl-names = "default"; + pinctrl-0 = <&sleep3>; + + sleep3: sleep-states { + PIN_SLP(gpv0-0, INPUT, DOWN); + PIN_SLP(gpv0-1, INPUT, DOWN); + PIN_SLP(gpv0-2, INPUT, DOWN); + PIN_SLP(gpv0-3, INPUT, DOWN); + PIN_SLP(gpv0-4, INPUT, DOWN); + PIN_SLP(gpv0-5, INPUT, DOWN); + PIN_SLP(gpv0-6, INPUT, DOWN); + PIN_SLP(gpv0-7, INPUT, DOWN); + + PIN_SLP(gpv1-0, INPUT, DOWN); + PIN_SLP(gpv1-1, INPUT, DOWN); + PIN_SLP(gpv1-2, INPUT, DOWN); + PIN_SLP(gpv1-3, INPUT, DOWN); + PIN_SLP(gpv1-4, INPUT, DOWN); + PIN_SLP(gpv1-5, INPUT, DOWN); + PIN_SLP(gpv1-6, INPUT, DOWN); + PIN_SLP(gpv1-7, INPUT, DOWN); + + PIN_SLP(gpv2-0, INPUT, DOWN); + PIN_SLP(gpv2-1, INPUT, DOWN); + PIN_SLP(gpv2-2, INPUT, DOWN); + PIN_SLP(gpv2-3, INPUT, DOWN); + PIN_SLP(gpv2-4, INPUT, DOWN); + PIN_SLP(gpv2-5, INPUT, DOWN); + PIN_SLP(gpv2-6, INPUT, DOWN); + PIN_SLP(gpv2-7, INPUT, DOWN); + + PIN_SLP(gpv3-0, INPUT, DOWN); + PIN_SLP(gpv3-1, INPUT, DOWN); + PIN_SLP(gpv3-2, INPUT, DOWN); + PIN_SLP(gpv3-3, INPUT, DOWN); + PIN_SLP(gpv3-4, INPUT, DOWN); + PIN_SLP(gpv3-5, INPUT, DOWN); + PIN_SLP(gpv3-6, INPUT, DOWN); + PIN_SLP(gpv3-7, INPUT, DOWN); + + PIN_SLP(gpv4-0, INPUT, DOWN); + PIN_SLP(gpv4-1, INPUT, DOWN); + }; +}; + +&pmu_system_controller { + assigned-clocks = <&pmu_system_controller 0>; + assigned-clock-parents = <&clock CLK_XUSBXTI>; +}; + +&rtc { + clocks = <&clock CLK_RTC>, <&max77686 MAX77686_CLK_AP>; + clock-names = "rtc", "rtc_src"; + status = "okay"; +}; + +&sdhci_2 { + bus-width = <4>; + cd-gpios = <&gpx3 4 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4 &sdhci2_cd>; + pinctrl-names = "default"; + vmmc-supply = <&ldo21_reg>; + status = "okay"; +}; + +&sdhci_3 { + #address-cells = <1>; + #size-cells = <0>; + non-removable; + bus-width = <4>; + mmc-pwrseq = <&wlan_pwrseq>; + + pinctrl-names = "default"; + pinctrl-0 = <&sd3_clk &sd3_cmd &sd3_wifi>; + status = "okay"; + + wifi@1 { + compatible = "brcm,bcm4329-fmac"; + reg = <0x1>; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake>; + interrupt-parent = <&gpx2>; + interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "host-wake"; + }; +}; + +&serial_0 { + pinctrl-0 = <&uart0_data &uart0_fctl>; + pinctrl-names = "default"; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm4330-bt"; + pinctrl-0 = <&bt_shutdown &bt_device_wakeup &bt_host_wakeup>; + pinctrl-names = "default"; + + max-speed = <2000000>; + shutdown-gpios = <&gpl0 6 GPIO_ACTIVE_HIGH>; + device-wakeup-gpios = <&gpx3 1 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios = <&gpx2 6 GPIO_ACTIVE_HIGH>; + clocks = <&max77686 MAX77686_CLK_PMIC>; + clock-names = "lpo"; + }; +}; + +&serial_2 { + pinctrl-0 = <&uart_sel>; + pinctrl-names = "default"; + status = "okay"; +}; + +&tmu { + status = "okay"; +}; -- cgit v1.2.3-59-g8ed1b From 3e50523fe6f4b0ade2e8e0a1428e23b7503fb85c Mon Sep 17 00:00:00 2001 From: Tomer Maimon Date: Tue, 29 Sep 2020 16:18:03 +0300 Subject: ARM: dts: nuvoton: Modify clock parameters Modify NPCM7xx device tree clock parameter to clock constants that define at include/dt-bindings/clock/nuvoton,npcm7xx-clock.h file. Signed-off-by: Tomer Maimon Reviewed-by: Joel Stanley Link: https://lore.kernel.org/r/20200929131807.15378-2-tmaimon77@gmail.com Signed-off-by: Joel Stanley --- arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi | 19 ++++++++++--------- arch/arm/boot/dts/nuvoton-npcm750.dtsi | 6 +++--- 2 files changed, 13 insertions(+), 12 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi b/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi index d2d0761295a4..16a28c5c4131 100644 --- a/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi +++ b/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi @@ -3,6 +3,7 @@ // Copyright 2018 Google, Inc. #include +#include / { #address-cells = <1>; @@ -80,7 +81,7 @@ interrupts = ; cache-unified; cache-level = <2>; - clocks = <&clk 10>; + clocks = <&clk NPCM7XX_CLK_AXI>; arm,shared-override; }; @@ -120,7 +121,7 @@ compatible = "nuvoton,npcm750-timer"; interrupts = ; reg = <0x8000 0x50>; - clocks = <&clk 5>; + clocks = <&clk NPCM7XX_CLK_TIMER>; }; watchdog0: watchdog@801C { @@ -128,7 +129,7 @@ interrupts = ; reg = <0x801C 0x4>; status = "disabled"; - clocks = <&clk 5>; + clocks = <&clk NPCM7XX_CLK_TIMER>; }; watchdog1: watchdog@901C { @@ -136,7 +137,7 @@ interrupts = ; reg = <0x901C 0x4>; status = "disabled"; - clocks = <&clk 5>; + clocks = <&clk NPCM7XX_CLK_TIMER>; }; watchdog2: watchdog@a01C { @@ -144,13 +145,13 @@ interrupts = ; reg = <0xa01C 0x4>; status = "disabled"; - clocks = <&clk 5>; + clocks = <&clk NPCM7XX_CLK_TIMER>; }; serial0: serial@1000 { compatible = "nuvoton,npcm750-uart"; reg = <0x1000 0x1000>; - clocks = <&clk 6>; + clocks = <&clk NPCM7XX_CLK_UART>; interrupts = ; reg-shift = <2>; status = "disabled"; @@ -159,7 +160,7 @@ serial1: serial@2000 { compatible = "nuvoton,npcm750-uart"; reg = <0x2000 0x1000>; - clocks = <&clk 6>; + clocks = <&clk NPCM7XX_CLK_UART>; interrupts = ; reg-shift = <2>; status = "disabled"; @@ -168,7 +169,7 @@ serial2: serial@3000 { compatible = "nuvoton,npcm750-uart"; reg = <0x3000 0x1000>; - clocks = <&clk 6>; + clocks = <&clk NPCM7XX_CLK_UART>; interrupts = ; reg-shift = <2>; status = "disabled"; @@ -177,7 +178,7 @@ serial3: serial@4000 { compatible = "nuvoton,npcm750-uart"; reg = <0x4000 0x1000>; - clocks = <&clk 6>; + clocks = <&clk NPCM7XX_CLK_UART>; interrupts = ; reg-shift = <2>; status = "disabled"; diff --git a/arch/arm/boot/dts/nuvoton-npcm750.dtsi b/arch/arm/boot/dts/nuvoton-npcm750.dtsi index 6ac340533587..a37bb2294b8f 100644 --- a/arch/arm/boot/dts/nuvoton-npcm750.dtsi +++ b/arch/arm/boot/dts/nuvoton-npcm750.dtsi @@ -17,7 +17,7 @@ cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a9"; - clocks = <&clk 0>; + clocks = <&clk NPCM7XX_CLK_CPU>; clock-names = "clk_cpu"; reg = <0>; next-level-cache = <&l2>; @@ -26,7 +26,7 @@ cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a9"; - clocks = <&clk 0>; + clocks = <&clk NPCM7XX_CLK_CPU>; clock-names = "clk_cpu"; reg = <1>; next-level-cache = <&l2>; @@ -38,7 +38,7 @@ reg = <0x3fe600 0x20>; interrupts = ; - clocks = <&clk 5>; + clocks = <&clk NPCM7XX_CLK_AHB>; }; }; }; -- cgit v1.2.3-59-g8ed1b From 7a28a9957ce7b4ed5cc30560034f54039cd56ed8 Mon Sep 17 00:00:00 2001 From: Tomer Maimon Date: Tue, 29 Sep 2020 16:18:04 +0300 Subject: ARM: dts: nuvoton: Modify timer register size Modify NPCM7xx device tree timer register size from 0x50 to 0x1C to control only the timer registers and not other hw modules. Signed-off-by: Tomer Maimon Reviewed-by: Joel Stanley Link: https://lore.kernel.org/r/20200929131807.15378-3-tmaimon77@gmail.com Signed-off-by: Joel Stanley --- arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi b/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi index 16a28c5c4131..72e364054e72 100644 --- a/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi +++ b/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi @@ -120,7 +120,7 @@ timer0: timer@8000 { compatible = "nuvoton,npcm750-timer"; interrupts = ; - reg = <0x8000 0x50>; + reg = <0x8000 0x1C>; clocks = <&clk NPCM7XX_CLK_TIMER>; }; -- cgit v1.2.3-59-g8ed1b From 0153c82b12233012b219b03f911aa242f5fe1e2c Mon Sep 17 00:00:00 2001 From: Tomer Maimon Date: Tue, 29 Sep 2020 16:18:05 +0300 Subject: ARM: dts: nuvoton: Add pinctrl and GPIO node Add pin controller and GPIO node to NPCM7XX device tree. Signed-off-by: Tomer Maimon Reviewed-by: Joel Stanley Link: https://lore.kernel.org/r/20200929131807.15378-4-tmaimon77@gmail.com Signed-off-by: Joel Stanley --- arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi | 564 ++++++++++++++++++++++++++ 1 file changed, 564 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi b/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi index 72e364054e72..7755a3de7c53 100644 --- a/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi +++ b/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi @@ -185,4 +185,568 @@ }; }; }; + + pinctrl: pinctrl@f0800000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "nuvoton,npcm750-pinctrl", "syscon", "simple-mfd"; + ranges = <0 0xf0010000 0x8000>; + gpio0: gpio@f0010000 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x0 0x80>; + interrupts = ; + gpio-ranges = <&pinctrl 0 0 32>; + }; + gpio1: gpio@f0011000 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x1000 0x80>; + interrupts = ; + gpio-ranges = <&pinctrl 0 32 32>; + }; + gpio2: gpio@f0012000 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x2000 0x80>; + interrupts = ; + gpio-ranges = <&pinctrl 0 64 32>; + }; + gpio3: gpio@f0013000 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x3000 0x80>; + interrupts = ; + gpio-ranges = <&pinctrl 0 96 32>; + }; + gpio4: gpio@f0014000 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x4000 0x80>; + interrupts = ; + gpio-ranges = <&pinctrl 0 128 32>; + }; + gpio5: gpio@f0015000 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x5000 0x80>; + interrupts = ; + gpio-ranges = <&pinctrl 0 160 32>; + }; + gpio6: gpio@f0016000 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x6000 0x80>; + interrupts = ; + gpio-ranges = <&pinctrl 0 192 32>; + }; + gpio7: gpio@f0017000 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x7000 0x80>; + interrupts = ; + gpio-ranges = <&pinctrl 0 224 32>; + }; + + iox1_pins: iox1-pins { + groups = "iox1"; + function = "iox1"; + }; + iox2_pins: iox2-pins { + groups = "iox2"; + function = "iox2"; + }; + smb1d_pins: smb1d-pins { + groups = "smb1d"; + function = "smb1d"; + }; + smb2d_pins: smb2d-pins { + groups = "smb2d"; + function = "smb2d"; + }; + lkgpo1_pins: lkgpo1-pins { + groups = "lkgpo1"; + function = "lkgpo1"; + }; + lkgpo2_pins: lkgpo2-pins { + groups = "lkgpo2"; + function = "lkgpo2"; + }; + ioxh_pins: ioxh-pins { + groups = "ioxh"; + function = "ioxh"; + }; + gspi_pins: gspi-pins { + groups = "gspi"; + function = "gspi"; + }; + smb5b_pins: smb5b-pins { + groups = "smb5b"; + function = "smb5b"; + }; + smb5c_pins: smb5c-pins { + groups = "smb5c"; + function = "smb5c"; + }; + lkgpo0_pins: lkgpo0-pins { + groups = "lkgpo0"; + function = "lkgpo0"; + }; + pspi2_pins: pspi2-pins { + groups = "pspi2"; + function = "pspi2"; + }; + smb4den_pins: smb4den-pins { + groups = "smb4den"; + function = "smb4den"; + }; + smb4b_pins: smb4b-pins { + groups = "smb4b"; + function = "smb4b"; + }; + smb4c_pins: smb4c-pins { + groups = "smb4c"; + function = "smb4c"; + }; + smb15_pins: smb15-pins { + groups = "smb15"; + function = "smb15"; + }; + smb4d_pins: smb4d-pins { + groups = "smb4d"; + function = "smb4d"; + }; + smb14_pins: smb14-pins { + groups = "smb14"; + function = "smb14"; + }; + smb5_pins: smb5-pins { + groups = "smb5"; + function = "smb5"; + }; + smb4_pins: smb4-pins { + groups = "smb4"; + function = "smb4"; + }; + smb3_pins: smb3-pins { + groups = "smb3"; + function = "smb3"; + }; + spi0cs1_pins: spi0cs1-pins { + groups = "spi0cs1"; + function = "spi0cs1"; + }; + spi0cs2_pins: spi0cs2-pins { + groups = "spi0cs2"; + function = "spi0cs2"; + }; + spi0cs3_pins: spi0cs3-pins { + groups = "spi0cs3"; + function = "spi0cs3"; + }; + smb3c_pins: smb3c-pins { + groups = "smb3c"; + function = "smb3c"; + }; + smb3b_pins: smb3b-pins { + groups = "smb3b"; + function = "smb3b"; + }; + bmcuart0a_pins: bmcuart0a-pins { + groups = "bmcuart0a"; + function = "bmcuart0a"; + }; + uart1_pins: uart1-pins { + groups = "uart1"; + function = "uart1"; + }; + jtag2_pins: jtag2-pins { + groups = "jtag2"; + function = "jtag2"; + }; + bmcuart1_pins: bmcuart1-pins { + groups = "bmcuart1"; + function = "bmcuart1"; + }; + uart2_pins: uart2-pins { + groups = "uart2"; + function = "uart2"; + }; + bmcuart0b_pins: bmcuart0b-pins { + groups = "bmcuart0b"; + function = "bmcuart0b"; + }; + r1err_pins: r1err-pins { + groups = "r1err"; + function = "r1err"; + }; + r1md_pins: r1md-pins { + groups = "r1md"; + function = "r1md"; + }; + smb3d_pins: smb3d-pins { + groups = "smb3d"; + function = "smb3d"; + }; + fanin0_pins: fanin0-pins { + groups = "fanin0"; + function = "fanin0"; + }; + fanin1_pins: fanin1-pins { + groups = "fanin1"; + function = "fanin1"; + }; + fanin2_pins: fanin2-pins { + groups = "fanin2"; + function = "fanin2"; + }; + fanin3_pins: fanin3-pins { + groups = "fanin3"; + function = "fanin3"; + }; + fanin4_pins: fanin4-pins { + groups = "fanin4"; + function = "fanin4"; + }; + fanin5_pins: fanin5-pins { + groups = "fanin5"; + function = "fanin5"; + }; + fanin6_pins: fanin6-pins { + groups = "fanin6"; + function = "fanin6"; + }; + fanin7_pins: fanin7-pins { + groups = "fanin7"; + function = "fanin7"; + }; + fanin8_pins: fanin8-pins { + groups = "fanin8"; + function = "fanin8"; + }; + fanin9_pins: fanin9-pins { + groups = "fanin9"; + function = "fanin9"; + }; + fanin10_pins: fanin10-pins { + groups = "fanin10"; + function = "fanin10"; + }; + fanin11_pins: fanin11-pins { + groups = "fanin11"; + function = "fanin11"; + }; + fanin12_pins: fanin12-pins { + groups = "fanin12"; + function = "fanin12"; + }; + fanin13_pins: fanin13-pins { + groups = "fanin13"; + function = "fanin13"; + }; + fanin14_pins: fanin14-pins { + groups = "fanin14"; + function = "fanin14"; + }; + fanin15_pins: fanin15-pins { + groups = "fanin15"; + function = "fanin15"; + }; + pwm0_pins: pwm0-pins { + groups = "pwm0"; + function = "pwm0"; + }; + pwm1_pins: pwm1-pins { + groups = "pwm1"; + function = "pwm1"; + }; + pwm2_pins: pwm2-pins { + groups = "pwm2"; + function = "pwm2"; + }; + pwm3_pins: pwm3-pins { + groups = "pwm3"; + function = "pwm3"; + }; + r2_pins: r2-pins { + groups = "r2"; + function = "r2"; + }; + r2err_pins: r2err-pins { + groups = "r2err"; + function = "r2err"; + }; + r2md_pins: r2md-pins { + groups = "r2md"; + function = "r2md"; + }; + ga20kbc_pins: ga20kbc-pins { + groups = "ga20kbc"; + function = "ga20kbc"; + }; + smb5d_pins: smb5d-pins { + groups = "smb5d"; + function = "smb5d"; + }; + lpc_pins: lpc-pins { + groups = "lpc"; + function = "lpc"; + }; + espi_pins: espi-pins { + groups = "espi"; + function = "espi"; + }; + rg1_pins: rg1-pins { + groups = "rg1"; + function = "rg1"; + }; + rg1mdio_pins: rg1mdio-pins { + groups = "rg1mdio"; + function = "rg1mdio"; + }; + rg2_pins: rg2-pins { + groups = "rg2"; + function = "rg2"; + }; + ddr_pins: ddr-pins { + groups = "ddr"; + function = "ddr"; + }; + smb0_pins: smb0-pins { + groups = "smb0"; + function = "smb0"; + }; + smb1_pins: smb1-pins { + groups = "smb1"; + function = "smb1"; + }; + smb2_pins: smb2-pins { + groups = "smb2"; + function = "smb2"; + }; + smb2c_pins: smb2c-pins { + groups = "smb2c"; + function = "smb2c"; + }; + smb2b_pins: smb2b-pins { + groups = "smb2b"; + function = "smb2b"; + }; + smb1c_pins: smb1c-pins { + groups = "smb1c"; + function = "smb1c"; + }; + smb1b_pins: smb1b-pins { + groups = "smb1b"; + function = "smb1b"; + }; + smb8_pins: smb8-pins { + groups = "smb8"; + function = "smb8"; + }; + smb9_pins: smb9-pins { + groups = "smb9"; + function = "smb9"; + }; + smb10_pins: smb10-pins { + groups = "smb10"; + function = "smb10"; + }; + smb11_pins: smb11-pins { + groups = "smb11"; + function = "smb11"; + }; + sd1_pins: sd1-pins { + groups = "sd1"; + function = "sd1"; + }; + sd1pwr_pins: sd1pwr-pins { + groups = "sd1pwr"; + function = "sd1pwr"; + }; + pwm4_pins: pwm4-pins { + groups = "pwm4"; + function = "pwm4"; + }; + pwm5_pins: pwm5-pins { + groups = "pwm5"; + function = "pwm5"; + }; + pwm6_pins: pwm6-pins { + groups = "pwm6"; + function = "pwm6"; + }; + pwm7_pins: pwm7-pins { + groups = "pwm7"; + function = "pwm7"; + }; + mmc8_pins: mmc8-pins { + groups = "mmc8"; + function = "mmc8"; + }; + mmc_pins: mmc-pins { + groups = "mmc"; + function = "mmc"; + }; + mmcwp_pins: mmcwp-pins { + groups = "mmcwp"; + function = "mmcwp"; + }; + mmccd_pins: mmccd-pins { + groups = "mmccd"; + function = "mmccd"; + }; + mmcrst_pins: mmcrst-pins { + groups = "mmcrst"; + function = "mmcrst"; + }; + clkout_pins: clkout-pins { + groups = "clkout"; + function = "clkout"; + }; + serirq_pins: serirq-pins { + groups = "serirq"; + function = "serirq"; + }; + lpcclk_pins: lpcclk-pins { + groups = "lpcclk"; + function = "lpcclk"; + }; + scipme_pins: scipme-pins { + groups = "scipme"; + function = "scipme"; + }; + sci_pins: sci-pins { + groups = "sci"; + function = "sci"; + }; + smb6_pins: smb6-pins { + groups = "smb6"; + function = "smb6"; + }; + smb7_pins: smb7-pins { + groups = "smb7"; + function = "smb7"; + }; + pspi1_pins: pspi1-pins { + groups = "pspi1"; + function = "pspi1"; + }; + faninx_pins: faninx-pins { + groups = "faninx"; + function = "faninx"; + }; + r1_pins: r1-pins { + groups = "r1"; + function = "r1"; + }; + spi3_pins: spi3-pins { + groups = "spi3"; + function = "spi3"; + }; + spi3cs1_pins: spi3cs1-pins { + groups = "spi3cs1"; + function = "spi3cs1"; + }; + spi3quad_pins: spi3quad-pins { + groups = "spi3quad"; + function = "spi3quad"; + }; + spi3cs2_pins: spi3cs2-pins { + groups = "spi3cs2"; + function = "spi3cs2"; + }; + spi3cs3_pins: spi3cs3-pins { + groups = "spi3cs3"; + function = "spi3cs3"; + }; + nprd_smi_pins: nprd-smi-pins { + groups = "nprd_smi"; + function = "nprd_smi"; + }; + smb0b_pins: smb0b-pins { + groups = "smb0b"; + function = "smb0b"; + }; + smb0c_pins: smb0c-pins { + groups = "smb0c"; + function = "smb0c"; + }; + smb0den_pins: smb0den-pins { + groups = "smb0den"; + function = "smb0den"; + }; + smb0d_pins: smb0d-pins { + groups = "smb0d"; + function = "smb0d"; + }; + ddc_pins: ddc-pins { + groups = "ddc"; + function = "ddc"; + }; + rg2mdio_pins: rg2mdio-pins { + groups = "rg2mdio"; + function = "rg2mdio"; + }; + wdog1_pins: wdog1-pins { + groups = "wdog1"; + function = "wdog1"; + }; + wdog2_pins: wdog2-pins { + groups = "wdog2"; + function = "wdog2"; + }; + smb12_pins: smb12-pins { + groups = "smb12"; + function = "smb12"; + }; + smb13_pins: smb13-pins { + groups = "smb13"; + function = "smb13"; + }; + spix_pins: spix-pins { + groups = "spix"; + function = "spix"; + }; + spixcs1_pins: spixcs1-pins { + groups = "spixcs1"; + function = "spixcs1"; + }; + clkreq_pins: clkreq-pins { + groups = "clkreq"; + function = "clkreq"; + }; + hgpio0_pins: hgpio0-pins { + groups = "hgpio0"; + function = "hgpio0"; + }; + hgpio1_pins: hgpio1-pins { + groups = "hgpio1"; + function = "hgpio1"; + }; + hgpio2_pins: hgpio2-pins { + groups = "hgpio2"; + function = "hgpio2"; + }; + hgpio3_pins: hgpio3-pins { + groups = "hgpio3"; + function = "hgpio3"; + }; + hgpio4_pins: hgpio4-pins { + groups = "hgpio4"; + function = "hgpio4"; + }; + hgpio5_pins: hgpio5-pins { + groups = "hgpio5"; + function = "hgpio5"; + }; + hgpio6_pins: hgpio6-pins { + groups = "hgpio6"; + function = "hgpio6"; + }; + hgpio7_pins: hgpio7-pins { + groups = "hgpio7"; + function = "hgpio7"; + }; + }; }; -- cgit v1.2.3-59-g8ed1b From 77c72b33f0b3bfc1609d7ad8d20980ba7854e955 Mon Sep 17 00:00:00 2001 From: Tomer Maimon Date: Tue, 29 Sep 2020 16:18:06 +0300 Subject: ARM: dts: nuvoton: Add new device nodes Add the following new device nodes to NPCM7XX: - NPCM7xx PWM and FAN. - NPCM7xx EHCI USB. - NPCM7xx KCS. - NPCM Reset. - NPCM Peripheral SPI. - NPCM FIU SPI. - NPCM HWRNG. - NPCM I2C. - STMicro STMMAC. Signed-off-by: Tomer Maimon Reviewed-by: Joel Stanley Link: https://lore.kernel.org/r/20200929131807.15378-5-tmaimon77@gmail.com Signed-off-by: Joel Stanley --- arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi | 382 +++++++++++++++++++++++++- arch/arm/boot/dts/nuvoton-npcm750.dtsi | 18 ++ 2 files changed, 394 insertions(+), 6 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi b/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi index 7755a3de7c53..3696980a3da1 100644 --- a/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi +++ b/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi @@ -4,6 +4,7 @@ #include #include +#include / { #address-cells = <1>; @@ -64,12 +65,6 @@ interrupt-parent = <&gic>; ranges = <0x0 0xf0000000 0x00900000>; - gcr: gcr@800000 { - compatible = "nuvoton,npcm750-gcr", "syscon", - "simple-mfd"; - reg = <0x800000 0x1000>; - }; - scu: scu@3fe000 { compatible = "arm,cortex-a9-scu"; reg = <0x3fe000 0x1000>; @@ -92,6 +87,16 @@ reg = <0x3ff000 0x1000>, <0x3fe100 0x100>; }; + + gcr: gcr@800000 { + compatible = "nuvoton,npcm750-gcr", "syscon", "simple-mfd"; + reg = <0x800000 0x1000>; + }; + + rst: rst@801000 { + compatible = "nuvoton,npcm750-rst", "syscon", "simple-mfd"; + reg = <0x801000 0x6C>; + }; }; ahb { @@ -101,6 +106,12 @@ interrupt-parent = <&gic>; ranges; + rstc: rstc@f0801000 { + compatible = "nuvoton,npcm750-reset"; + reg = <0xf0801000 0x70>; + #reset-cells = <2>; + }; + clk: clock-controller@f0801000 { compatible = "nuvoton,npcm750-clk", "syscon"; #clock-cells = <1>; @@ -110,6 +121,63 @@ clocks = <&clk_refclk>, <&clk_sysbypck>, <&clk_mcbypck>; }; + gmac0: eth@f0802000 { + device_type = "network"; + compatible = "snps,dwmac"; + reg = <0xf0802000 0x2000>; + interrupts = ; + interrupt-names = "macirq"; + ethernet = <0>; + clocks = <&clk_rg1refck>, <&clk NPCM7XX_CLK_AHB>; + clock-names = "stmmaceth", "clk_gmac"; + pinctrl-names = "default"; + pinctrl-0 = <&rg1_pins + &rg1mdio_pins>; + status = "disabled"; + }; + + ehci1: usb@f0806000 { + compatible = "nuvoton,npcm750-ehci"; + reg = <0xf0806000 0x1000>; + interrupts = ; + status = "disabled"; + }; + + fiu0: spi@fb000000 { + compatible = "nuvoton,npcm750-fiu"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xfb000000 0x1000>; + reg-names = "control", "memory"; + clocks = <&clk NPCM7XX_CLK_SPI0>; + clock-names = "clk_spi0"; + status = "disabled"; + }; + + fiu3: spi@c0000000 { + compatible = "nuvoton,npcm750-fiu"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xc0000000 0x1000>; + reg-names = "control", "memory"; + clocks = <&clk NPCM7XX_CLK_SPI3>; + clock-names = "clk_spi3"; + pinctrl-names = "default"; + pinctrl-0 = <&spi3_pins>; + status = "disabled"; + }; + + fiux: spi@fb001000 { + compatible = "nuvoton,npcm750-fiu"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xfb001000 0x1000>; + reg-names = "control", "memory"; + clocks = <&clk NPCM7XX_CLK_SPIX>; + clock-names = "clk_spix"; + status = "disabled"; + }; + apb { #address-cells = <1>; #size-cells = <1>; @@ -117,6 +185,68 @@ interrupt-parent = <&gic>; ranges = <0x0 0xf0000000 0x00300000>; + lpc_kcs: lpc_kcs@7000 { + compatible = "nuvoton,npcm750-lpc-kcs", "simple-mfd", "syscon"; + reg = <0x7000 0x40>; + reg-io-width = <1>; + + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x7000 0x40>; + + kcs1: kcs1@0 { + compatible = "nuvoton,npcm750-kcs-bmc"; + reg = <0x0 0x40>; + interrupts = ; + kcs_chan = <1>; + status = "disabled"; + }; + + kcs2: kcs2@0 { + compatible = "nuvoton,npcm750-kcs-bmc"; + reg = <0x0 0x40>; + interrupts = ; + kcs_chan = <2>; + status = "disabled"; + }; + + kcs3: kcs3@0 { + compatible = "nuvoton,npcm750-kcs-bmc"; + reg = <0x0 0x40>; + interrupts = ; + kcs_chan = <3>; + status = "disabled"; + }; + }; + + spi0: spi@200000 { + compatible = "nuvoton,npcm750-pspi"; + reg = <0x200000 0x1000>; + pinctrl-names = "default"; + pinctrl-0 = <&pspi1_pins>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&clk NPCM7XX_CLK_APB5>; + clock-names = "clk_apb5"; + resets = <&rstc NPCM7XX_RESET_IPSRST2 NPCM7XX_RESET_PSPI1>; + status = "disabled"; + }; + + spi1: spi@201000 { + compatible = "nuvoton,npcm750-pspi"; + reg = <0x201000 0x1000>; + pinctrl-names = "default"; + pinctrl-0 = <&pspi2_pins>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&clk NPCM7XX_CLK_APB5>; + clock-names = "clk_apb5"; + resets = <&rstc NPCM7XX_RESET_IPSRST2 NPCM7XX_RESET_PSPI2>; + status = "disabled"; + }; + timer0: timer@8000 { compatible = "nuvoton,npcm750-timer"; interrupts = ; @@ -183,6 +313,246 @@ reg-shift = <2>; status = "disabled"; }; + + rng: rng@b000 { + compatible = "nuvoton,npcm750-rng"; + reg = <0xb000 0x8>; + status = "disabled"; + }; + + adc: adc@c000 { + compatible = "nuvoton,npcm750-adc"; + reg = <0xc000 0x8>; + interrupts = ; + clocks = <&clk NPCM7XX_CLK_ADC>; + resets = <&rstc NPCM7XX_RESET_IPSRST1 NPCM7XX_RESET_ADC>; + status = "disabled"; + }; + + pwm_fan: pwm-fan-controller@103000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nuvoton,npcm750-pwm-fan"; + reg = <0x103000 0x2000>, <0x180000 0x8000>; + reg-names = "pwm", "fan"; + clocks = <&clk NPCM7XX_CLK_APB3>, + <&clk NPCM7XX_CLK_APB4>; + clock-names = "pwm","fan"; + interrupts = , + , + , + , + , + , + , + ; + pinctrl-names = "default"; + pinctrl-0 = <&pwm0_pins &pwm1_pins + &pwm2_pins &pwm3_pins + &pwm4_pins &pwm5_pins + &pwm6_pins &pwm7_pins + &fanin0_pins &fanin1_pins + &fanin2_pins &fanin3_pins + &fanin4_pins &fanin5_pins + &fanin6_pins &fanin7_pins + &fanin8_pins &fanin9_pins + &fanin10_pins &fanin11_pins + &fanin12_pins &fanin13_pins + &fanin14_pins &fanin15_pins>; + status = "disabled"; + }; + + i2c0: i2c@80000 { + reg = <0x80000 0x1000>; + compatible = "nuvoton,npcm750-i2c"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clk NPCM7XX_CLK_APB2>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&smb0_pins>; + status = "disabled"; + }; + + i2c1: i2c@81000 { + reg = <0x81000 0x1000>; + compatible = "nuvoton,npcm750-i2c"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clk NPCM7XX_CLK_APB2>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&smb1_pins>; + status = "disabled"; + }; + + i2c2: i2c@82000 { + reg = <0x82000 0x1000>; + compatible = "nuvoton,npcm750-i2c"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clk NPCM7XX_CLK_APB2>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&smb2_pins>; + status = "disabled"; + }; + + i2c3: i2c@83000 { + reg = <0x83000 0x1000>; + compatible = "nuvoton,npcm750-i2c"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clk NPCM7XX_CLK_APB2>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&smb3_pins>; + status = "disabled"; + }; + + i2c4: i2c@84000 { + reg = <0x84000 0x1000>; + compatible = "nuvoton,npcm750-i2c"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clk NPCM7XX_CLK_APB2>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&smb4_pins>; + status = "disabled"; + }; + + i2c5: i2c@85000 { + reg = <0x85000 0x1000>; + compatible = "nuvoton,npcm750-i2c"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clk NPCM7XX_CLK_APB2>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&smb5_pins>; + status = "disabled"; + }; + + i2c6: i2c@86000 { + reg = <0x86000 0x1000>; + compatible = "nuvoton,npcm750-i2c"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clk NPCM7XX_CLK_APB2>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&smb6_pins>; + status = "disabled"; + }; + + i2c7: i2c@87000 { + reg = <0x87000 0x1000>; + compatible = "nuvoton,npcm750-i2c"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clk NPCM7XX_CLK_APB2>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&smb7_pins>; + status = "disabled"; + }; + + i2c8: i2c@88000 { + reg = <0x88000 0x1000>; + compatible = "nuvoton,npcm750-i2c"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clk NPCM7XX_CLK_APB2>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&smb8_pins>; + status = "disabled"; + }; + + i2c9: i2c@89000 { + reg = <0x89000 0x1000>; + compatible = "nuvoton,npcm750-i2c"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clk NPCM7XX_CLK_APB2>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&smb9_pins>; + status = "disabled"; + }; + + i2c10: i2c@8a000 { + reg = <0x8a000 0x1000>; + compatible = "nuvoton,npcm750-i2c"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clk NPCM7XX_CLK_APB2>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&smb10_pins>; + status = "disabled"; + }; + + i2c11: i2c@8b000 { + reg = <0x8b000 0x1000>; + compatible = "nuvoton,npcm750-i2c"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clk NPCM7XX_CLK_APB2>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&smb11_pins>; + status = "disabled"; + }; + + i2c12: i2c@8c000 { + reg = <0x8c000 0x1000>; + compatible = "nuvoton,npcm750-i2c"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clk NPCM7XX_CLK_APB2>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&smb12_pins>; + status = "disabled"; + }; + + i2c13: i2c@8d000 { + reg = <0x8d000 0x1000>; + compatible = "nuvoton,npcm750-i2c"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clk NPCM7XX_CLK_APB2>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&smb13_pins>; + status = "disabled"; + }; + + i2c14: i2c@8e000 { + reg = <0x8e000 0x1000>; + compatible = "nuvoton,npcm750-i2c"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clk NPCM7XX_CLK_APB2>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&smb14_pins>; + status = "disabled"; + }; + + i2c15: i2c@8f000 { + reg = <0x8f000 0x1000>; + compatible = "nuvoton,npcm750-i2c"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clk NPCM7XX_CLK_APB2>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&smb15_pins>; + status = "disabled"; + }; }; }; diff --git a/arch/arm/boot/dts/nuvoton-npcm750.dtsi b/arch/arm/boot/dts/nuvoton-npcm750.dtsi index a37bb2294b8f..13eee0fe5642 100644 --- a/arch/arm/boot/dts/nuvoton-npcm750.dtsi +++ b/arch/arm/boot/dts/nuvoton-npcm750.dtsi @@ -32,6 +32,7 @@ next-level-cache = <&l2>; }; }; + soc { timer@3fe600 { compatible = "arm,cortex-a9-twd-timer"; @@ -41,4 +42,21 @@ clocks = <&clk NPCM7XX_CLK_AHB>; }; }; + + ahb { + gmac1: eth@f0804000 { + device_type = "network"; + compatible = "snps,dwmac"; + reg = <0xf0804000 0x2000>; + interrupts = ; + interrupt-names = "macirq"; + ethernet = <1>; + clocks = <&clk_rg2refck>, <&clk NPCM7XX_CLK_AHB>; + clock-names = "stmmaceth", "clk_gmac"; + pinctrl-names = "default"; + pinctrl-0 = <&rg2_pins + &rg2mdio_pins>; + status = "disabled"; + }; + }; }; -- cgit v1.2.3-59-g8ed1b From e42b650f828d275840ab6403289249b8029e99e6 Mon Sep 17 00:00:00 2001 From: Tomer Maimon Date: Tue, 29 Sep 2020 16:18:07 +0300 Subject: ARM: dts: nuvoton: Add new device nodes to NPCM750 EVB Add the following new device nodes to NPCM750 evolution board device tree: - NPCM7xx Pin controller and GPIO - NPCM7xx PWM and FAN - NPCM7xx EHCI USB - NPCM7xx KCS - NPCM Reset - NPCM Peripheral SPI - NPCM FIU SPI - NPCM HWRNG - NPCM I2C - STMicro STMMAC Signed-off-by: Tomer Maimon Reviewed-by: Joel Stanley Link: https://lore.kernel.org/r/20200929131807.15378-6-tmaimon77@gmail.com Signed-off-by: Joel Stanley --- arch/arm/boot/dts/nuvoton-npcm750-evb.dts | 367 +++++++++++++++++++++- arch/arm/boot/dts/nuvoton-npcm750-pincfg-evb.dtsi | 157 +++++++++ 2 files changed, 523 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/nuvoton-npcm750-pincfg-evb.dtsi (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/nuvoton-npcm750-evb.dts b/arch/arm/boot/dts/nuvoton-npcm750-evb.dts index 15f744f1beea..9f13d08f5804 100644 --- a/arch/arm/boot/dts/nuvoton-npcm750-evb.dts +++ b/arch/arm/boot/dts/nuvoton-npcm750-evb.dts @@ -4,24 +4,161 @@ /dts-v1/; #include "nuvoton-npcm750.dtsi" +#include "dt-bindings/gpio/gpio.h" +#include "nuvoton-npcm750-pincfg-evb.dtsi" / { model = "Nuvoton npcm750 Development Board (Device Tree)"; compatible = "nuvoton,npcm750"; + aliases { + ethernet2 = &gmac0; + ethernet3 = &gmac1; + serial0 = &serial0; + serial1 = &serial1; + serial2 = &serial2; + serial3 = &serial3; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c5; + i2c6 = &i2c6; + i2c7 = &i2c7; + i2c8 = &i2c8; + i2c9 = &i2c9; + i2c10 = &i2c10; + i2c11 = &i2c11; + i2c12 = &i2c12; + i2c13 = &i2c13; + i2c14 = &i2c14; + i2c15 = &i2c15; + spi0 = &spi0; + spi1 = &spi1; + fiu0 = &fiu0; + fiu1 = &fiu3; + fiu2 = &fiux; + }; + chosen { stdout-path = &serial3; }; memory { - reg = <0 0x40000000>; + device_type = "memory"; + reg = <0x0 0x20000000>; + }; +}; + +&gmac0 { + phy-mode = "rgmii-id"; + status = "okay"; +}; + +&gmac1 { + phy-mode = "rgmii-id"; + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&fiu0 { + status = "okay"; + spi-nor@0 { + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + spi-rx-bus-width = <2>; + reg = <0>; + spi-max-frequency = <5000000>; + partitions@80000000 { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + bbuboot1@0 { + label = "bb-uboot-1"; + reg = <0x0000000 0x80000>; + read-only; + }; + bbuboot2@80000 { + label = "bb-uboot-2"; + reg = <0x0080000 0x80000>; + read-only; + }; + envparam@100000 { + label = "env-param"; + reg = <0x0100000 0x40000>; + read-only; + }; + spare@140000 { + label = "spare"; + reg = <0x0140000 0xC0000>; + }; + kernel@200000 { + label = "kernel"; + reg = <0x0200000 0x400000>; + }; + rootfs@600000 { + label = "rootfs"; + reg = <0x0600000 0x700000>; + }; + spare1@D00000 { + label = "spare1"; + reg = <0x0D00000 0x200000>; + }; + spare2@0F00000 { + label = "spare2"; + reg = <0x0F00000 0x200000>; + }; + spare3@1100000 { + label = "spare3"; + reg = <0x1100000 0x200000>; + }; + spare4@1300000 { + label = "spare4"; + reg = <0x1300000 0x0>; + }; + }; + }; +}; + +&fiu3 { + pinctrl-0 = <&spi3_pins>, <&spi3quad_pins>; + status = "okay"; + spi-nor@0 { + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + spi-rx-bus-width = <2>; + reg = <0>; + spi-max-frequency = <5000000>; + partitions@A0000000 { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + system1@0 { + label = "spi3-system1"; + reg = <0x0 0x0>; + }; + }; }; }; +&fiux { + spix-mode; +}; + &watchdog1 { status = "okay"; }; +&rng { + status = "okay"; +}; + &serial0 { status = "okay"; }; @@ -37,3 +174,231 @@ &serial3 { status = "okay"; }; + +&adc { + status = "okay"; +}; + +&lpc_kcs { + kcs1: kcs1@0 { + status = "okay"; + }; + + kcs2: kcs2@0 { + status = "okay"; + }; + + kcs3: kcs3@0 { + status = "okay"; + }; +}; + +/* lm75 on SVB */ +&i2c0 { + clock-frequency = <100000>; + status = "okay"; + lm75@48 { + compatible = "lm75"; + reg = <0x48>; + status = "okay"; + }; +}; + +/* lm75 on EB */ +&i2c1 { + clock-frequency = <100000>; + status = "okay"; + lm75@48 { + compatible = "lm75"; + reg = <0x48>; + status = "okay"; + }; +}; + +/* tmp100 on EB */ +&i2c2 { + clock-frequency = <100000>; + status = "okay"; + tmp100@48 { + compatible = "tmp100"; + reg = <0x48>; + status = "okay"; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + status = "okay"; +}; + +&i2c5 { + clock-frequency = <100000>; + status = "okay"; +}; + +/* tmp100 on SVB */ +&i2c6 { + clock-frequency = <100000>; + status = "okay"; + tmp100@48 { + compatible = "tmp100"; + reg = <0x48>; + status = "okay"; + }; +}; + +&i2c7 { + clock-frequency = <100000>; + status = "okay"; +}; + +&i2c8 { + clock-frequency = <100000>; + status = "okay"; +}; + +&i2c9 { + clock-frequency = <100000>; + status = "okay"; +}; + +&i2c10 { + clock-frequency = <100000>; + status = "okay"; +}; + +&i2c11 { + clock-frequency = <100000>; + status = "okay"; +}; + +&i2c14 { + clock-frequency = <100000>; + status = "okay"; +}; + +&pwm_fan { + status = "okay"; + fan@0 { + reg = <0x00>; + fan-tach-ch = /bits/ 8 <0x00 0x01>; + cooling-levels = <127 255>; + }; + fan@1 { + reg = <0x01>; + fan-tach-ch = /bits/ 8 <0x02 0x03>; + cooling-levels = /bits/ 8 <127 255>; + }; + fan@2 { + reg = <0x02>; + fan-tach-ch = /bits/ 8 <0x04 0x05>; + cooling-levels = /bits/ 8 <127 255>; + }; + fan@3 { + reg = <0x03>; + fan-tach-ch = /bits/ 8 <0x06 0x07>; + cooling-levels = /bits/ 8 <127 255>; + }; + fan@4 { + reg = <0x04>; + fan-tach-ch = /bits/ 8 <0x08 0x09>; + cooling-levels = /bits/ 8 <127 255>; + }; + fan@5 { + reg = <0x05>; + fan-tach-ch = /bits/ 8 <0x0A 0x0B>; + cooling-levels = /bits/ 8 <127 255>; + }; + fan@6 { + reg = <0x06>; + fan-tach-ch = /bits/ 8 <0x0C 0x0D>; + cooling-levels = /bits/ 8 <127 255>; + }; + fan@7 { + reg = <0x07>; + fan-tach-ch = /bits/ 8 <0x0E 0x0F>; + cooling-levels = /bits/ 8 <127 255>; + }; +}; + +&spi0 { + cs-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>; + status = "okay"; + Flash@0 { + compatible = "winbond,w25q128", + "jedec,spi-nor"; + reg = <0x0>; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <5000000>; + partition@0 { + label = "spi0_spare1"; + reg = <0x0000000 0x800000>; + }; + partition@1 { + label = "spi0_spare2"; + reg = <0x800000 0x0>; + }; + }; +}; + +&spi1 { + cs-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>; + status = "okay"; + Flash@0 { + compatible = "winbond,w25q128fw", + "jedec,spi-nor"; + reg = <0x0>; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <5000000>; + partition@0 { + label = "spi1_spare1"; + reg = <0x0000000 0x800000>; + }; + partition@1 { + label = "spi1_spare2"; + reg = <0x800000 0x0>; + }; + }; +}; + +&pinctrl { + pinctrl-names = "default"; + pinctrl-0 = < &iox1_pins + &pin8_input + &pin9_output_high + &pin10_input + &pin11_output_high + &pin16_input + &pin24_output_high + &pin25_output_low + &pin32_output_high + &jtag2_pins + &pin61_output_high + &pin62_output_high + &pin63_output_high + &lpc_pins + &pin160_input + &pin162_input + &pin168_input + &pin169_input + &pin170_input + &pin187_output_high + &pin190_input + &pin191_output_high + &pin192_output_high + &pin197_output_low + &ddc_pins + &pin218_input + &pin219_output_low + &pin220_output_low + &pin221_output_high + &pin222_input + &pin223_output_low + &spix_pins + &pin228_output_low + &pin231_output_high + &pin255_input>; +}; + diff --git a/arch/arm/boot/dts/nuvoton-npcm750-pincfg-evb.dtsi b/arch/arm/boot/dts/nuvoton-npcm750-pincfg-evb.dtsi new file mode 100644 index 000000000000..3b3806274adf --- /dev/null +++ b/arch/arm/boot/dts/nuvoton-npcm750-pincfg-evb.dtsi @@ -0,0 +1,157 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2018 Nuvoton Technology + +/ { + pinctrl: pinctrl@f0800000 { + pin8_input: pin8-input { + pins = "GPIO8/LKGPO1"; + bias-disable; + input-enable; + }; + pin9_output_high: pin9-output-high { + pins = "GPIO9/LKGPO2"; + bias-disable; + output-high; + }; + pin10_input: pin10-input { + pins = "GPIO10/IOXHLD"; + bias-disable; + input-enable; + }; + pin11_output_high: pin11-output-high { + pins = "GPIO11/IOXHCK"; + bias-disable; + output-high; + }; + pin16_input: pin16-input { + pins = "GPIO16/LKGPO0"; + bias-disable; + input-enable; + }; + pin24_output_high: pin24-output-high { + pins = "GPIO24/IOXHDO"; + bias-disable; + output-high; + }; + pin25_output_low: pin25-output-low { + pins = "GPIO25/IOXHDI"; + bias-disable; + output-low; + }; + pin32_output_high: pin32-output-high { + pins = "GPIO32/nSPI0CS1"; + bias-disable; + output-high; + }; + pin61_output_high: pin61-output-high { + pins = "GPO61/nDTR1_BOUT1/STRAP6"; + bias-disable; + output-high; + }; + pin62_output_high: pin62-output-high { + pins = "GPO62/nRTST1/STRAP5"; + bias-disable; + output-high; + }; + pin63_output_high: pin63-output-high { + pins = "GPO63/TXD1/STRAP4"; + bias-disable; + output-high; + }; + pin160_input: pin160-input { + pins = "GPIO160/CLKOUT/RNGOSCOUT"; + bias-disable; + input-enable; + }; + pin162_input: pin162-input { + pins = "GPIO162/SERIRQ"; + bias-disable; + input-enable; + }; + pin168_input: pin168-input { + pins = "GPIO168/nCLKRUN/nESPIALERT"; + bias-disable; + input-enable; + }; + pin169_input: pin169-input { + pins = "GPIO169/nSCIPME"; + bias-disable; + input-enable; + }; + pin170_input: pin170-input { + pins = "GPIO170/nSMI"; + bias-disable; + input-enable; + }; + pin187_output_high: pin187-output-high { + pins = "GPIO187/nSPI3CS1"; + bias-disable; + output-high; + }; + pin190_input: pin190-input { + pins = "GPIO190/nPRD_SMI"; + bias-disable; + input-enable; + }; + pin191_output_high: pin191-output-high { + pins = "GPIO191"; + bias-disable; + output-high; + }; + pin192_output_high: pin192-output-high { + pins = "GPIO192"; + bias-disable; + output-high; + }; + pin197_output_low: pin197-output-low { + pins = "GPIO197/SMB0DEN"; + bias-disable; + output-low; + }; + pin218_input: pin218-input { + pins = "GPIO218/nWDO1"; + bias-disable; + input-enable; + }; + pin219_output_low: pin219-output-low { + pins = "GPIO219/nWDO2"; + bias-disable; + output-low; + }; + pin220_output_low: pin220-output-low { + pins = "GPIO220/SMB12SCL"; + bias-disable; + output-low; + }; + pin221_output_high: pin221-output-high { + pins = "GPIO221/SMB12SDA"; + bias-disable; + output-high; + }; + pin222_input: pin222-input { + pins = "GPIO222/SMB13SCL"; + bias-disable; + input-enable; + }; + pin223_output_low: pin223-output-low { + pins = "GPIO223/SMB13SDA"; + bias-disable; + output-low; + }; + pin228_output_low: pin228-output-low { + pins = "GPIO228/nSPIXCS1"; + bias-disable; + output-low; + }; + pin231_output_high: pin231-output-high { + pins = "GPIO230/SPIXD3"; + bias-disable; + output-high; + }; + pin255_input: pin255-input { + pins = "GPI255/DACOSEL"; + bias-disable; + input-enable; + }; + }; +}; -- cgit v1.2.3-59-g8ed1b From 3e1f79e4311248c8b20f3bc988f898b11aa1a887 Mon Sep 17 00:00:00 2001 From: Hugues Fruchet Date: Thu, 8 Oct 2020 11:09:42 +0200 Subject: ARM: dts: stm32: fix DCMI DMA features on stm32mp15 family Enable FIFO mode with half-full threshold. Signed-off-by: Hugues Fruchet Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp151.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/stm32mp151.dtsi b/arch/arm/boot/dts/stm32mp151.dtsi index 84757901cd8d..00361d9f0187 100644 --- a/arch/arm/boot/dts/stm32mp151.dtsi +++ b/arch/arm/boot/dts/stm32mp151.dtsi @@ -1098,7 +1098,7 @@ resets = <&rcc CAMITF_R>; clocks = <&rcc DCMI>; clock-names = "mclk"; - dmas = <&dmamux1 75 0x400 0x0d>; + dmas = <&dmamux1 75 0x400 0x01>; dma-names = "tx"; status = "disabled"; }; -- cgit v1.2.3-59-g8ed1b From 516728273ddfbf51b3d0fcaac05d26e299a7b456 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 8 Oct 2020 21:36:18 +0200 Subject: ARM: dts: stm32: Connect PHY IRQ line on DH STM32MP1 SoM On the production DHCOM STM32MP15xx SoM, the PHY IRQ line is connected to the PI11 pin. Describe it in the DT as well, so the PHY IRQ can be used e.g. to detect cable insertion and removal. Signed-off-by: Marek Vasut Cc: Alexandre Torgue Cc: Maxime Coquelin Cc: Patrice Chotard Cc: Patrick Delaunay Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi index f796a6150313..e257459c34dc 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi @@ -127,6 +127,8 @@ phy0: ethernet-phy@1 { reg = <1>; + interrupt-parent = <&gpioi>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; }; }; }; -- cgit v1.2.3-59-g8ed1b From b0c0c8b400d5047dd0fce13d73cf63f33716641a Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 8 Oct 2020 21:37:59 +0200 Subject: ARM: dts: stm32: Add alternate pinmux for FMC EBI bus Add another mux option for FMC EBI bus, this is used on DHCOM SoM for the second ethernet and on the PDK2 devkit for SRAM. Signed-off-by: Marek Vasut Cc: Alexandre Torgue Cc: Maxime Coquelin Cc: Patrice Chotard Cc: Patrick Delaunay Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp15-pinctrl.dtsi | 55 ++++++++++++++++++++++++++++++++ 1 file changed, 55 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi index d84686e00370..9dbefa77b03e 100644 --- a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi @@ -349,6 +349,61 @@ }; }; + fmc_pins_b: fmc-1 { + pins { + pinmux = , /* FMC_NOE */ + , /* FMC_NWE */ + , /* FMC_NL */ + , /* FMC_D0 */ + , /* FMC_D1 */ + , /* FMC_D2 */ + , /* FMC_D3 */ + , /* FMC_D4 */ + , /* FMC_D5 */ + , /* FMC_D6 */ + , /* FMC_D7 */ + , /* FMC_D8 */ + , /* FMC_D9 */ + , /* FMC_D10 */ + , /* FMC_D11 */ + , /* FMC_D12 */ + , /* FMC_D13 */ + , /* FMC_D14 */ + , /* FMC_D15 */ + , /* FMC_NE2_FMC_NCE */ + ; /* FMC_NE4 */ + bias-disable; + drive-push-pull; + slew-rate = <3>; + }; + }; + + fmc_sleep_pins_b: fmc-sleep-1 { + pins { + pinmux = , /* FMC_NOE */ + , /* FMC_NWE */ + , /* FMC_NL */ + , /* FMC_D0 */ + , /* FMC_D1 */ + , /* FMC_D2 */ + , /* FMC_D3 */ + , /* FMC_D4 */ + , /* FMC_D5 */ + , /* FMC_D6 */ + , /* FMC_D7 */ + , /* FMC_D8 */ + , /* FMC_D9 */ + , /* FMC_D10 */ + , /* FMC_D11 */ + , /* FMC_D12 */ + , /* FMC_D13 */ + , /* FMC_D14 */ + , /* FMC_D15 */ + , /* FMC_NE2_FMC_NCE */ + ; /* FMC_NE4 */ + }; + }; + i2c1_pins_a: i2c1-0 { pins { pinmux = , /* I2C1_SCL */ -- cgit v1.2.3-59-g8ed1b From b5269b6664515b4de6fd06e22ca9773530c6fc57 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 8 Oct 2020 21:38:00 +0200 Subject: ARM: dts: stm32: Add KS8851 on FMC2 to STM32MP1 DHCOM Add bindings for the KS8851 ethernet present on the STM32MP1 DHCOM SoM. Signed-off-by: Marek Vasut Cc: Alexandre Torgue Cc: Maxime Coquelin Cc: Patrice Chotard Cc: Patrick Delaunay Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi | 35 ++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi index e257459c34dc..ac46ab363e1b 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi @@ -11,6 +11,7 @@ / { aliases { ethernet0 = ðernet0; + ethernet1 = &ksz8851; }; memory@c0000000 { @@ -133,6 +134,40 @@ }; }; +&fmc { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&fmc_pins_b>; + pinctrl-1 = <&fmc_sleep_pins_b>; + status = "okay"; + + ksz8851: ks8851mll@1,0 { + compatible = "micrel,ks8851-mll"; + reg = <1 0x0 0x2>, <1 0x2 0x20000>; + interrupt-parent = <&gpioc>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + bank-width = <2>; + + /* Timing values are in nS */ + st,fmc2-ebi-cs-mux-enable; + st,fmc2-ebi-cs-transaction-type = <4>; + st,fmc2-ebi-cs-buswidth = <16>; + st,fmc2-ebi-cs-address-setup-ns = <5>; + st,fmc2-ebi-cs-address-hold-ns = <5>; + st,fmc2-ebi-cs-bus-turnaround-ns = <5>; + st,fmc2-ebi-cs-data-setup-ns = <45>; + st,fmc2-ebi-cs-data-hold-ns = <1>; + st,fmc2-ebi-cs-write-address-setup-ns = <5>; + st,fmc2-ebi-cs-write-address-hold-ns = <5>; + st,fmc2-ebi-cs-write-bus-turnaround-ns = <5>; + st,fmc2-ebi-cs-write-data-setup-ns = <45>; + st,fmc2-ebi-cs-write-data-hold-ns = <1>; + }; +}; + +&gpioc { + status = "okay"; +}; + &i2c4 { pinctrl-names = "default"; pinctrl-0 = <&i2c4_pins_a>; -- cgit v1.2.3-59-g8ed1b From fd6a1e60a0496be1c903a7fd47482c67cdd5ccd7 Mon Sep 17 00:00:00 2001 From: Eddie James Date: Wed, 28 Oct 2020 13:56:47 -0500 Subject: ARM: dts: aspeed: rainier: Add 4U device-tree Add a device-tree for the Rainier 4U system. Change the model name on the existing Rainier device-tree to 2U, and remove the two extra power supplies that are only present on the 4U system. Also add labels to the fan nodes for use in the 4U device-tree. Signed-off-by: Eddie James Reviewed-by: Andrew Jeffery Link: https://lore.kernel.org/r/20201028185647.14565-1-eajames@linux.ibm.com Signed-off-by: Joel Stanley --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/aspeed-bmc-ibm-rainier-4u.dts | 37 +++++++++++++++++++++++++ arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts | 20 ++++--------- 3 files changed, 43 insertions(+), 15 deletions(-) create mode 100644 arch/arm/boot/dts/aspeed-bmc-ibm-rainier-4u.dts (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 1917cd47204a..ec35977193f1 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1392,6 +1392,7 @@ dtb-$(CONFIG_ARCH_ASPEED) += \ aspeed-bmc-facebook-yamp.dtb \ aspeed-bmc-facebook-yosemitev2.dtb \ aspeed-bmc-ibm-rainier.dtb \ + aspeed-bmc-ibm-rainier-4u.dtb \ aspeed-bmc-intel-s2600wf.dtb \ aspeed-bmc-inspur-fp5280g2.dtb \ aspeed-bmc-lenovo-hr630.dtb \ diff --git a/arch/arm/boot/dts/aspeed-bmc-ibm-rainier-4u.dts b/arch/arm/boot/dts/aspeed-bmc-ibm-rainier-4u.dts new file mode 100644 index 000000000000..291f7d6c9979 --- /dev/null +++ b/arch/arm/boot/dts/aspeed-bmc-ibm-rainier-4u.dts @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +// Copyright 2020 IBM Corp. +/dts-v1/; + +#include "aspeed-bmc-ibm-rainier.dts" + +/ { + model = "Rainier 4U"; +}; + +&i2c3 { + power-supply@6a { + compatible = "ibm,cffps"; + reg = <0x6a>; + }; + + power-supply@6b { + compatible = "ibm,cffps"; + reg = <0x6b>; + }; +}; + +&fan0 { + tach-pulses = <4>; +}; + +&fan1 { + tach-pulses = <4>; +}; + +&fan2 { + tach-pulses = <4>; +}; + +&fan3 { + tach-pulses = <4>; +}; diff --git a/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts b/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts index 21ae880c7530..ac649fde802e 100644 --- a/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts +++ b/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts @@ -8,7 +8,7 @@ #include / { - model = "Rainier"; + model = "Rainier 2U"; compatible = "ibm,rainier-bmc", "aspeed,ast2600"; aliases { @@ -594,16 +594,6 @@ compatible = "ibm,cffps"; reg = <0x69>; }; - - power-supply@6a { - compatible = "ibm,cffps"; - reg = <0x6a>; - }; - - power-supply@6b { - compatible = "ibm,cffps"; - reg = <0x6b>; - }; }; &i2c4 { @@ -723,25 +713,25 @@ #address-cells = <1>; #size-cells = <0>; - fan@0 { + fan0: fan@0 { compatible = "pmbus-fan"; reg = <0>; tach-pulses = <2>; }; - fan@1 { + fan1: fan@1 { compatible = "pmbus-fan"; reg = <1>; tach-pulses = <2>; }; - fan@2 { + fan2: fan@2 { compatible = "pmbus-fan"; reg = <2>; tach-pulses = <2>; }; - fan@3 { + fan3: fan@3 { compatible = "pmbus-fan"; reg = <3>; tach-pulses = <2>; -- cgit v1.2.3-59-g8ed1b From e73840f316cbf9df00893c0ef9f734196087403d Mon Sep 17 00:00:00 2001 From: Jonathan Cameron Date: Sun, 15 Nov 2020 19:29:46 +0000 Subject: ARM: dts: exynos: Drop incorrect use of io-channel-ranges This property is only relevant to consumers of io-channels, not providers. All these dtsi files have it alongside #io-channel-cells which indicates they are providers of io-channels, not consumers. Note that dt-schema will now flag this up due to a dependency between this property and io-channels. Signed-off-by: Jonathan Cameron Link: https://lore.kernel.org/r/20201115192951.1073632-5-jic23@kernel.org Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos3250.dtsi | 1 - arch/arm/boot/dts/exynos4412.dtsi | 1 - arch/arm/boot/dts/exynos5250.dtsi | 1 - arch/arm/boot/dts/exynos54xx.dtsi | 1 - 4 files changed, 4 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi index c5390ca5a87d..77ab7193b903 100644 --- a/arch/arm/boot/dts/exynos3250.dtsi +++ b/arch/arm/boot/dts/exynos3250.dtsi @@ -439,7 +439,6 @@ clock-names = "adc", "sclk"; clocks = <&cmu CLK_TSADC>, <&cmu CLK_SCLK_TSADC>; #io-channel-cells = <1>; - io-channel-ranges; samsung,syscon-phandle = <&pmu_system_controller>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/exynos4412.dtsi b/arch/arm/boot/dts/exynos4412.dtsi index 96a4b01bd71b..a142fe84010b 100644 --- a/arch/arm/boot/dts/exynos4412.dtsi +++ b/arch/arm/boot/dts/exynos4412.dtsi @@ -274,7 +274,6 @@ clocks = <&clock CLK_TSADC>; clock-names = "adc"; #io-channel-cells = <1>; - io-channel-ranges; samsung,syscon-phandle = <&pmu_system_controller>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi index 1be1841c374f..2ea2caaca4e2 100644 --- a/arch/arm/boot/dts/exynos5250.dtsi +++ b/arch/arm/boot/dts/exynos5250.dtsi @@ -844,7 +844,6 @@ clocks = <&clock CLK_ADC>; clock-names = "adc"; #io-channel-cells = <1>; - io-channel-ranges; samsung,syscon-phandle = <&pmu_system_controller>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/exynos54xx.dtsi b/arch/arm/boot/dts/exynos54xx.dtsi index 339243d19a80..fe9d34c23374 100644 --- a/arch/arm/boot/dts/exynos54xx.dtsi +++ b/arch/arm/boot/dts/exynos54xx.dtsi @@ -101,7 +101,6 @@ reg = <0x12d10000 0x100>; interrupts = ; #io-channel-cells = <1>; - io-channel-ranges; status = "disabled"; }; -- cgit v1.2.3-59-g8ed1b From 43379417e31cadc7afba5ca549eaa1043f089ce5 Mon Sep 17 00:00:00 2001 From: Jonathan Cameron Date: Sun, 15 Nov 2020 19:29:47 +0000 Subject: ARM: dts: s5pv210: Drop incorrect use of io-channel-ranges property This property is relevant to consumers of io-channels. Here it is used by a provider. dt-schema will now report and error as this property must be in the same node as io-channels and it is not here. Signed-off-by: Jonathan Cameron Link: https://lore.kernel.org/r/20201115192951.1073632-6-jic23@kernel.org Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/s5pv210.dtsi | 1 - 1 file changed, 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/s5pv210.dtsi b/arch/arm/boot/dts/s5pv210.dtsi index 2871351ab907..353ba7b09a0c 100644 --- a/arch/arm/boot/dts/s5pv210.dtsi +++ b/arch/arm/boot/dts/s5pv210.dtsi @@ -149,7 +149,6 @@ clocks = <&clocks CLK_TSADC>; clock-names = "adc"; #io-channel-cells = <1>; - io-channel-ranges; status = "disabled"; }; -- cgit v1.2.3-59-g8ed1b From 0f8159371c225a7b019b612a5c101e8b839c6c46 Mon Sep 17 00:00:00 2001 From: Jonathan Cameron Date: Sun, 15 Nov 2020 19:29:49 +0000 Subject: ARM: dts: s5pv210: Drop unneeded io-channel-ranges property in Aries This property is only useful if a node has children as it allows them to then use io-channel properties in the parent. Here there are no children. This is harmless, but we are planning to shortly drop this property as it is rarely used correctly and there is little reason it would ever be needed as we can just provide the io-channels property to any child nodes that need it. Signed-off-by: Jonathan Cameron Link: https://lore.kernel.org/r/20201115192951.1073632-8-jic23@kernel.org Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/s5pv210-aries.dtsi | 1 - 1 file changed, 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/s5pv210-aries.dtsi b/arch/arm/boot/dts/s5pv210-aries.dtsi index 91ecad85abfc..97cb7ff2f75f 100644 --- a/arch/arm/boot/dts/s5pv210-aries.dtsi +++ b/arch/arm/boot/dts/s5pv210-aries.dtsi @@ -589,7 +589,6 @@ io-channels = <&adc 9>; shunt-resistor-micro-ohms = <47000000>; /* 47 ohms */ #io-channel-cells = <0>; - io-channel-ranges; }; }; -- cgit v1.2.3-59-g8ed1b From f73659192b0bdf7bad826587b3530cef43cc048d Mon Sep 17 00:00:00 2001 From: Xie He Date: Sat, 14 Nov 2020 07:09:21 -0800 Subject: net: wan: Delete the DLCI / SDLA drivers The DLCI driver (dlci.c) implements the Frame Relay protocol. However, we already have another newer and better implementation of Frame Relay provided by the HDLC_FR driver (hdlc_fr.c). The DLCI driver's implementation of Frame Relay is used by only one hardware driver in the kernel - the SDLA driver (sdla.c). The SDLA driver provides Frame Relay support for the Sangoma S50x devices. However, the vendor provides their own driver (along with their own multi-WAN-protocol implementations including Frame Relay), called WANPIPE. I believe most users of the hardware would use the vendor-provided WANPIPE driver instead. (The WANPIPE driver was even once in the kernel, but was deleted in commit 8db60bcf3021 ("[WAN]: Remove broken and unmaintained Sangoma drivers.") because the vendor no longer updated the in-kernel WANPIPE driver.) Cc: Mike McLagan Signed-off-by: Xie He Link: https://lore.kernel.org/r/20201114150921.685594-1-xie.he.0141@gmail.com Signed-off-by: Jakub Kicinski --- CREDITS | 9 - Documentation/networking/framerelay.rst | 44 - MAINTAINERS | 6 - arch/arm/configs/ixp4xx_defconfig | 1 - arch/mips/configs/gpr_defconfig | 1 - arch/mips/configs/mtx1_defconfig | 1 - drivers/net/wan/Kconfig | 45 - drivers/net/wan/Makefile | 2 - drivers/net/wan/dlci.c | 541 ---------- drivers/net/wan/sdla.c | 1655 ------------------------------- include/linux/if_frad.h | 92 -- include/linux/sdla.h | 240 ----- include/uapi/linux/if_frad.h | 123 --- include/uapi/linux/sdla.h | 117 --- net/socket.c | 25 - 15 files changed, 2902 deletions(-) delete mode 100644 Documentation/networking/framerelay.rst delete mode 100644 drivers/net/wan/dlci.c delete mode 100644 drivers/net/wan/sdla.c delete mode 100644 include/linux/if_frad.h delete mode 100644 include/linux/sdla.h delete mode 100644 include/uapi/linux/if_frad.h delete mode 100644 include/uapi/linux/sdla.h (limited to 'arch/arm') diff --git a/CREDITS b/CREDITS index 8592e45e3932..67421adb747c 100644 --- a/CREDITS +++ b/CREDITS @@ -2499,15 +2499,6 @@ W: http://www.rdrop.com/users/paulmck/ D: RCU and variants D: rcutorture module -N: Mike McLagan -E: mike.mclagan@linux.org -W: http://www.invlogic.com/~mmclagan -D: DLCI/FRAD drivers for Sangoma SDLAs -S: Innovative Logic Corp -S: Post Office Box 1068 -S: Laurel, Maryland 20732 -S: USA - N: Bradley McLean E: brad@bradpc.gaylord.com D: Device driver hacker diff --git a/Documentation/networking/framerelay.rst b/Documentation/networking/framerelay.rst deleted file mode 100644 index 6d904399ec6d..000000000000 --- a/Documentation/networking/framerelay.rst +++ /dev/null @@ -1,44 +0,0 @@ -.. SPDX-License-Identifier: GPL-2.0 - -================ -Frame Relay (FR) -================ - -Frame Relay (FR) support for linux is built into a two tiered system of device -drivers. The upper layer implements RFC1490 FR specification, and uses the -Data Link Connection Identifier (DLCI) as its hardware address. Usually these -are assigned by your network supplier, they give you the number/numbers of -the Virtual Connections (VC) assigned to you. - -Each DLCI is a point-to-point link between your machine and a remote one. -As such, a separate device is needed to accommodate the routing. Within the -net-tools archives is 'dlcicfg'. This program will communicate with the -base "DLCI" device, and create new net devices named 'dlci00', 'dlci01'... -The configuration script will ask you how many DLCIs you need, as well as -how many DLCIs you want to assign to each Frame Relay Access Device (FRAD). - -The DLCI uses a number of function calls to communicate with the FRAD, all -of which are stored in the FRAD's private data area. assoc/deassoc, -activate/deactivate and dlci_config. The DLCI supplies a receive function -to the FRAD to accept incoming packets. - -With this initial offering, only 1 FRAD driver is available. With many thanks -to Sangoma Technologies, David Mandelstam & Gene Kozin, the S502A, S502E & -S508 are supported. This driver is currently set up for only FR, but as -Sangoma makes more firmware modules available, it can be updated to provide -them as well. - -Configuration of the FRAD makes use of another net-tools program, 'fradcfg'. -This program makes use of a configuration file (which dlcicfg can also read) -to specify the types of boards to be configured as FRADs, as well as perform -any board specific configuration. The Sangoma module of fradcfg loads the -FR firmware into the card, sets the irq/port/memory information, and provides -an initial configuration. - -Additional FRAD device drivers can be added as hardware is available. - -At this time, the dlcicfg and fradcfg programs have not been incorporated into -the net-tools distribution. They can be found at ftp.invlogic.com, in -/pub/linux. Note that with OS/2 FTPD, you end up in /pub by default, so just -use 'cd linux'. v0.10 is for use on pre-2.0.3 and earlier, v0.15 is for -pre-2.0.4 and later. diff --git a/MAINTAINERS b/MAINTAINERS index af9f6a3ab100..3341959af0c7 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -6905,12 +6905,6 @@ S: Maintained W: http://floatingpoint.sourceforge.net/emulator/index.html F: arch/x86/math-emu/ -FRAME RELAY DLCI/FRAD (Sangoma drivers too) -L: netdev@vger.kernel.org -S: Orphan -F: drivers/net/wan/dlci.c -F: drivers/net/wan/sdla.c - FRAMEBUFFER LAYER M: Bartlomiej Zolnierkiewicz L: dri-devel@lists.freedesktop.org diff --git a/arch/arm/configs/ixp4xx_defconfig b/arch/arm/configs/ixp4xx_defconfig index 27e7c0714b96..0d6edeb27659 100644 --- a/arch/arm/configs/ixp4xx_defconfig +++ b/arch/arm/configs/ixp4xx_defconfig @@ -141,7 +141,6 @@ CONFIG_HDLC_CISCO=m CONFIG_HDLC_FR=m CONFIG_HDLC_PPP=m CONFIG_HDLC_X25=m -CONFIG_DLCI=m CONFIG_WAN_ROUTER_DRIVERS=m CONFIG_ATM_TCP=m # CONFIG_INPUT_KEYBOARD is not set diff --git a/arch/mips/configs/gpr_defconfig b/arch/mips/configs/gpr_defconfig index 599d5604aabe..8a921c8ac233 100644 --- a/arch/mips/configs/gpr_defconfig +++ b/arch/mips/configs/gpr_defconfig @@ -228,7 +228,6 @@ CONFIG_FARSYNC=m CONFIG_DSCC4=m CONFIG_DSCC4_PCISYNC=y CONFIG_DSCC4_PCI_RST=y -CONFIG_DLCI=m CONFIG_LAPBETHER=m # CONFIG_INPUT_KEYBOARD is not set # CONFIG_INPUT_MOUSE is not set diff --git a/arch/mips/configs/mtx1_defconfig b/arch/mips/configs/mtx1_defconfig index dc69b054181c..30dacce94198 100644 --- a/arch/mips/configs/mtx1_defconfig +++ b/arch/mips/configs/mtx1_defconfig @@ -378,7 +378,6 @@ CONFIG_FARSYNC=m CONFIG_DSCC4=m CONFIG_DSCC4_PCISYNC=y CONFIG_DSCC4_PCI_RST=y -CONFIG_DLCI=m CONFIG_LAPBETHER=m # CONFIG_KEYBOARD_ATKBD is not set CONFIG_KEYBOARD_GPIO=y diff --git a/drivers/net/wan/Kconfig b/drivers/net/wan/Kconfig index 2cf98a732a26..4029fde71a9e 100644 --- a/drivers/net/wan/Kconfig +++ b/drivers/net/wan/Kconfig @@ -321,51 +321,6 @@ config IXP4XX_HSS Say Y here if you want to use built-in HSS ports on IXP4xx processor. -config DLCI - tristate "Frame Relay DLCI support" - help - Support for the Frame Relay protocol. - - Frame Relay is a fast low-cost way to connect to a remote Internet - access provider or to form a private wide area network. The one - physical line from your box to the local "switch" (i.e. the entry - point to the Frame Relay network, usually at the phone company) can - carry several logical point-to-point connections to other computers - connected to the Frame Relay network. For a general explanation of - the protocol, check out . - - To use frame relay, you need supporting hardware (called FRAD) and - certain programs from the net-tools package as explained in - . - - To compile this driver as a module, choose M here: the - module will be called dlci. - -config DLCI_MAX - int "Max DLCI per device" - depends on DLCI - default "8" - help - How many logical point-to-point frame relay connections (the - identifiers of which are called DCLIs) should be handled by each - of your hardware frame relay access devices. - - Go with the default. - -config SDLA - tristate "SDLA (Sangoma S502/S508) support" - depends on DLCI && ISA - help - Driver for the Sangoma S502A, S502E, and S508 Frame Relay Access - Devices. - - These are multi-protocol cards, but only Frame Relay is supported - by the driver at this time. Please read - . - - To compile this driver as a module, choose M here: the - module will be called sdla. - # X.25 network drivers config LAPBETHER tristate "LAPB over Ethernet driver" diff --git a/drivers/net/wan/Makefile b/drivers/net/wan/Makefile index 5b9dc85eae34..081666c36ca2 100644 --- a/drivers/net/wan/Makefile +++ b/drivers/net/wan/Makefile @@ -21,8 +21,6 @@ obj-$(CONFIG_FARSYNC) += farsync.o obj-$(CONFIG_LANMEDIA) += lmc/ -obj-$(CONFIG_DLCI) += dlci.o -obj-$(CONFIG_SDLA) += sdla.o obj-$(CONFIG_LAPBETHER) += lapbether.o obj-$(CONFIG_SBNI) += sbni.o obj-$(CONFIG_N2) += n2.o diff --git a/drivers/net/wan/dlci.c b/drivers/net/wan/dlci.c deleted file mode 100644 index 3ca4daf63389..000000000000 --- a/drivers/net/wan/dlci.c +++ /dev/null @@ -1,541 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * DLCI Implementation of Frame Relay protocol for Linux, according to - * RFC 1490. This generic device provides en/decapsulation for an - * underlying hardware driver. Routes & IPs are assigned to these - * interfaces. Requires 'dlcicfg' program to create usable - * interfaces, the initial one, 'dlci' is for IOCTL use only. - * - * Version: @(#)dlci.c 0.35 4 Jan 1997 - * - * Author: Mike McLagan - * - * Changes: - * - * 0.15 Mike Mclagan Packet freeing, bug in kmalloc call - * DLCI_RET handling - * 0.20 Mike McLagan More conservative on which packets - * are returned for retry and which are - * are dropped. If DLCI_RET_DROP is - * returned from the FRAD, the packet is - * sent back to Linux for re-transmission - * 0.25 Mike McLagan Converted to use SIOC IOCTL calls - * 0.30 Jim Freeman Fixed to allow IPX traffic - * 0.35 Michael Elizabeth Fixed incorrect memcpy_fromfs - */ - -#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -#include -#include -#include - -static const char version[] = "DLCI driver v0.35, 4 Jan 1997, mike.mclagan@linux.org"; - -static LIST_HEAD(dlci_devs); - -static void dlci_setup(struct net_device *); - -/* - * these encapsulate the RFC 1490 requirements as well as - * deal with packet transmission and reception, working with - * the upper network layers - */ - -static int dlci_header(struct sk_buff *skb, struct net_device *dev, - unsigned short type, const void *daddr, - const void *saddr, unsigned len) -{ - struct frhdr hdr; - unsigned int hlen; - char *dest; - - hdr.control = FRAD_I_UI; - switch (type) - { - case ETH_P_IP: - hdr.IP_NLPID = FRAD_P_IP; - hlen = sizeof(hdr.control) + sizeof(hdr.IP_NLPID); - break; - - /* feel free to add other types, if necessary */ - - default: - hdr.pad = FRAD_P_PADDING; - hdr.NLPID = FRAD_P_SNAP; - memset(hdr.OUI, 0, sizeof(hdr.OUI)); - hdr.PID = htons(type); - hlen = sizeof(hdr); - break; - } - - dest = skb_push(skb, hlen); - if (!dest) - return 0; - - memcpy(dest, &hdr, hlen); - - return hlen; -} - -static void dlci_receive(struct sk_buff *skb, struct net_device *dev) -{ - struct frhdr *hdr; - int process, header; - - if (!pskb_may_pull(skb, sizeof(*hdr))) { - netdev_notice(dev, "invalid data no header\n"); - dev->stats.rx_errors++; - kfree_skb(skb); - return; - } - - hdr = (struct frhdr *) skb->data; - process = 0; - header = 0; - skb->dev = dev; - - if (hdr->control != FRAD_I_UI) - { - netdev_notice(dev, "Invalid header flag 0x%02X\n", - hdr->control); - dev->stats.rx_errors++; - } - else - switch (hdr->IP_NLPID) - { - case FRAD_P_PADDING: - if (hdr->NLPID != FRAD_P_SNAP) - { - netdev_notice(dev, "Unsupported NLPID 0x%02X\n", - hdr->NLPID); - dev->stats.rx_errors++; - break; - } - - if (hdr->OUI[0] + hdr->OUI[1] + hdr->OUI[2] != 0) - { - netdev_notice(dev, "Unsupported organizationally unique identifier 0x%02X-%02X-%02X\n", - hdr->OUI[0], - hdr->OUI[1], - hdr->OUI[2]); - dev->stats.rx_errors++; - break; - } - - /* at this point, it's an EtherType frame */ - header = sizeof(struct frhdr); - /* Already in network order ! */ - skb->protocol = hdr->PID; - process = 1; - break; - - case FRAD_P_IP: - header = sizeof(hdr->control) + sizeof(hdr->IP_NLPID); - skb->protocol = htons(ETH_P_IP); - process = 1; - break; - - case FRAD_P_SNAP: - case FRAD_P_Q933: - case FRAD_P_CLNP: - netdev_notice(dev, "Unsupported NLPID 0x%02X\n", - hdr->pad); - dev->stats.rx_errors++; - break; - - default: - netdev_notice(dev, "Invalid pad byte 0x%02X\n", - hdr->pad); - dev->stats.rx_errors++; - break; - } - - if (process) - { - /* we've set up the protocol, so discard the header */ - skb_reset_mac_header(skb); - skb_pull(skb, header); - dev->stats.rx_bytes += skb->len; - netif_rx(skb); - dev->stats.rx_packets++; - } - else - dev_kfree_skb(skb); -} - -static netdev_tx_t dlci_transmit(struct sk_buff *skb, struct net_device *dev) -{ - struct dlci_local *dlp = netdev_priv(dev); - - if (skb) { - struct netdev_queue *txq = skb_get_tx_queue(dev, skb); - netdev_start_xmit(skb, dlp->slave, txq, false); - } - return NETDEV_TX_OK; -} - -static int dlci_config(struct net_device *dev, struct dlci_conf __user *conf, int get) -{ - struct dlci_conf config; - struct dlci_local *dlp; - struct frad_local *flp; - int err; - - dlp = netdev_priv(dev); - - flp = netdev_priv(dlp->slave); - - if (!get) - { - if (copy_from_user(&config, conf, sizeof(struct dlci_conf))) - return -EFAULT; - if (config.flags & ~DLCI_VALID_FLAGS) - return -EINVAL; - memcpy(&dlp->config, &config, sizeof(struct dlci_conf)); - dlp->configured = 1; - } - - err = (*flp->dlci_conf)(dlp->slave, dev, get); - if (err) - return err; - - if (get) - { - if (copy_to_user(conf, &dlp->config, sizeof(struct dlci_conf))) - return -EFAULT; - } - - return 0; -} - -static int dlci_dev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) -{ - struct dlci_local *dlp; - - if (!capable(CAP_NET_ADMIN)) - return -EPERM; - - dlp = netdev_priv(dev); - - switch (cmd) - { - case DLCI_GET_SLAVE: - if (!*(short *)(dev->dev_addr)) - return -EINVAL; - - strncpy(ifr->ifr_slave, dlp->slave->name, sizeof(ifr->ifr_slave)); - break; - - case DLCI_GET_CONF: - case DLCI_SET_CONF: - if (!*(short *)(dev->dev_addr)) - return -EINVAL; - - return dlci_config(dev, ifr->ifr_data, cmd == DLCI_GET_CONF); - - default: - return -EOPNOTSUPP; - } - return 0; -} - -static int dlci_change_mtu(struct net_device *dev, int new_mtu) -{ - struct dlci_local *dlp = netdev_priv(dev); - - return dev_set_mtu(dlp->slave, new_mtu); -} - -static int dlci_open(struct net_device *dev) -{ - struct dlci_local *dlp; - struct frad_local *flp; - int err; - - dlp = netdev_priv(dev); - - if (!*(short *)(dev->dev_addr)) - return -EINVAL; - - if (!netif_running(dlp->slave)) - return -ENOTCONN; - - flp = netdev_priv(dlp->slave); - err = (*flp->activate)(dlp->slave, dev); - if (err) - return err; - - netif_start_queue(dev); - - return 0; -} - -static int dlci_close(struct net_device *dev) -{ - struct dlci_local *dlp; - struct frad_local *flp; - - netif_stop_queue(dev); - - dlp = netdev_priv(dev); - - flp = netdev_priv(dlp->slave); - (*flp->deactivate)(dlp->slave, dev); - - return 0; -} - -static int dlci_add(struct dlci_add *dlci) -{ - struct net_device *master, *slave; - struct dlci_local *dlp; - struct frad_local *flp; - int err = -EINVAL; - - - /* validate slave device */ - slave = dev_get_by_name(&init_net, dlci->devname); - if (!slave) - return -ENODEV; - - if (slave->type != ARPHRD_FRAD || netdev_priv(slave) == NULL) - goto err1; - - /* create device name */ - master = alloc_netdev(sizeof(struct dlci_local), "dlci%d", - NET_NAME_UNKNOWN, dlci_setup); - if (!master) { - err = -ENOMEM; - goto err1; - } - - /* make sure same slave not already registered */ - rtnl_lock(); - list_for_each_entry(dlp, &dlci_devs, list) { - if (dlp->slave == slave) { - err = -EBUSY; - goto err2; - } - } - - *(short *)(master->dev_addr) = dlci->dlci; - - dlp = netdev_priv(master); - dlp->slave = slave; - dlp->master = master; - - flp = netdev_priv(slave); - err = (*flp->assoc)(slave, master); - if (err < 0) - goto err2; - - err = register_netdevice(master); - if (err < 0) - goto err2; - - strcpy(dlci->devname, master->name); - - list_add(&dlp->list, &dlci_devs); - rtnl_unlock(); - - return 0; - - err2: - rtnl_unlock(); - free_netdev(master); - err1: - dev_put(slave); - return err; -} - -static int dlci_del(struct dlci_add *dlci) -{ - struct dlci_local *dlp; - struct frad_local *flp; - struct net_device *master, *slave; - int err; - bool found = false; - - rtnl_lock(); - - /* validate slave device */ - master = __dev_get_by_name(&init_net, dlci->devname); - if (!master) { - err = -ENODEV; - goto out; - } - - list_for_each_entry(dlp, &dlci_devs, list) { - if (dlp->master == master) { - found = true; - break; - } - } - if (!found) { - err = -ENODEV; - goto out; - } - - if (netif_running(master)) { - err = -EBUSY; - goto out; - } - - dlp = netdev_priv(master); - slave = dlp->slave; - flp = netdev_priv(slave); - - err = (*flp->deassoc)(slave, master); - if (!err) { - list_del(&dlp->list); - - unregister_netdevice(master); - - dev_put(slave); - } -out: - rtnl_unlock(); - return err; -} - -static int dlci_ioctl(unsigned int cmd, void __user *arg) -{ - struct dlci_add add; - int err; - - if (!capable(CAP_NET_ADMIN)) - return -EPERM; - - if (copy_from_user(&add, arg, sizeof(struct dlci_add))) - return -EFAULT; - - switch (cmd) - { - case SIOCADDDLCI: - err = dlci_add(&add); - - if (!err) - if (copy_to_user(arg, &add, sizeof(struct dlci_add))) - return -EFAULT; - break; - - case SIOCDELDLCI: - err = dlci_del(&add); - break; - - default: - err = -EINVAL; - } - - return err; -} - -static const struct header_ops dlci_header_ops = { - .create = dlci_header, -}; - -static const struct net_device_ops dlci_netdev_ops = { - .ndo_open = dlci_open, - .ndo_stop = dlci_close, - .ndo_do_ioctl = dlci_dev_ioctl, - .ndo_start_xmit = dlci_transmit, - .ndo_change_mtu = dlci_change_mtu, -}; - -static void dlci_setup(struct net_device *dev) -{ - struct dlci_local *dlp = netdev_priv(dev); - - dev->flags = 0; - dev->header_ops = &dlci_header_ops; - dev->netdev_ops = &dlci_netdev_ops; - dev->needs_free_netdev = true; - - dlp->receive = dlci_receive; - - dev->type = ARPHRD_DLCI; - dev->hard_header_len = sizeof(struct frhdr); - dev->addr_len = sizeof(short); - -} - -/* if slave is unregistering, then cleanup master */ -static int dlci_dev_event(struct notifier_block *unused, - unsigned long event, void *ptr) -{ - struct net_device *dev = netdev_notifier_info_to_dev(ptr); - - if (dev_net(dev) != &init_net) - return NOTIFY_DONE; - - if (event == NETDEV_UNREGISTER) { - struct dlci_local *dlp; - - list_for_each_entry(dlp, &dlci_devs, list) { - if (dlp->slave == dev) { - list_del(&dlp->list); - unregister_netdevice(dlp->master); - dev_put(dlp->slave); - break; - } - } - } - return NOTIFY_DONE; -} - -static struct notifier_block dlci_notifier = { - .notifier_call = dlci_dev_event, -}; - -static int __init init_dlci(void) -{ - dlci_ioctl_set(dlci_ioctl); - register_netdevice_notifier(&dlci_notifier); - - printk("%s.\n", version); - - return 0; -} - -static void __exit dlci_exit(void) -{ - struct dlci_local *dlp, *nxt; - - dlci_ioctl_set(NULL); - unregister_netdevice_notifier(&dlci_notifier); - - rtnl_lock(); - list_for_each_entry_safe(dlp, nxt, &dlci_devs, list) { - unregister_netdevice(dlp->master); - dev_put(dlp->slave); - } - rtnl_unlock(); -} - -module_init(init_dlci); -module_exit(dlci_exit); - -MODULE_AUTHOR("Mike McLagan"); -MODULE_DESCRIPTION("Frame Relay DLCI layer"); -MODULE_LICENSE("GPL"); diff --git a/drivers/net/wan/sdla.c b/drivers/net/wan/sdla.c deleted file mode 100644 index bc2c1c7fb1a4..000000000000 --- a/drivers/net/wan/sdla.c +++ /dev/null @@ -1,1655 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * SDLA An implementation of a driver for the Sangoma S502/S508 series - * multi-protocol PC interface card. Initial offering is with - * the DLCI driver, providing Frame Relay support for linux. - * - * Global definitions for the Frame relay interface. - * - * Version: @(#)sdla.c 0.30 12 Sep 1996 - * - * Credits: Sangoma Technologies, for the use of 2 cards for an extended - * period of time. - * David Mandelstam for getting me started on - * this project, and incentive to complete it. - * Gene Kozen <74604.152@compuserve.com> for providing me with - * important information about the cards. - * - * Author: Mike McLagan - * - * Changes: - * 0.15 Mike McLagan Improved error handling, packet dropping - * 0.20 Mike McLagan New transmit/receive flags for config - * If in FR mode, don't accept packets from - * non DLCI devices. - * 0.25 Mike McLagan Fixed problem with rejecting packets - * from non DLCI devices. - * 0.30 Mike McLagan Fixed kernel panic when used with modified - * ifconfig - */ - -#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -static const char* version = "SDLA driver v0.30, 12 Sep 1996, mike.mclagan@linux.org"; - -static unsigned int valid_port[] = { 0x250, 0x270, 0x280, 0x300, 0x350, 0x360, 0x380, 0x390}; - -static unsigned int valid_mem[] = { - 0xA0000, 0xA2000, 0xA4000, 0xA6000, 0xA8000, 0xAA000, 0xAC000, 0xAE000, - 0xB0000, 0xB2000, 0xB4000, 0xB6000, 0xB8000, 0xBA000, 0xBC000, 0xBE000, - 0xC0000, 0xC2000, 0xC4000, 0xC6000, 0xC8000, 0xCA000, 0xCC000, 0xCE000, - 0xD0000, 0xD2000, 0xD4000, 0xD6000, 0xD8000, 0xDA000, 0xDC000, 0xDE000, - 0xE0000, 0xE2000, 0xE4000, 0xE6000, 0xE8000, 0xEA000, 0xEC000, 0xEE000}; - -static DEFINE_SPINLOCK(sdla_lock); - -/********************************************************* - * - * these are the core routines that access the card itself - * - *********************************************************/ - -#define SDLA_WINDOW(dev,addr) outb((((addr) >> 13) & 0x1F), (dev)->base_addr + SDLA_REG_Z80_WINDOW) - -static void __sdla_read(struct net_device *dev, int addr, void *buf, short len) -{ - char *temp; - const void *base; - int offset, bytes; - - temp = buf; - while(len) - { - offset = addr & SDLA_ADDR_MASK; - bytes = offset + len > SDLA_WINDOW_SIZE ? SDLA_WINDOW_SIZE - offset : len; - base = (const void *) (dev->mem_start + offset); - - SDLA_WINDOW(dev, addr); - memcpy(temp, base, bytes); - - addr += bytes; - temp += bytes; - len -= bytes; - } -} - -static void sdla_read(struct net_device *dev, int addr, void *buf, short len) -{ - unsigned long flags; - spin_lock_irqsave(&sdla_lock, flags); - __sdla_read(dev, addr, buf, len); - spin_unlock_irqrestore(&sdla_lock, flags); -} - -static void __sdla_write(struct net_device *dev, int addr, - const void *buf, short len) -{ - const char *temp; - void *base; - int offset, bytes; - - temp = buf; - while(len) - { - offset = addr & SDLA_ADDR_MASK; - bytes = offset + len > SDLA_WINDOW_SIZE ? SDLA_WINDOW_SIZE - offset : len; - base = (void *) (dev->mem_start + offset); - - SDLA_WINDOW(dev, addr); - memcpy(base, temp, bytes); - - addr += bytes; - temp += bytes; - len -= bytes; - } -} - -static void sdla_write(struct net_device *dev, int addr, - const void *buf, short len) -{ - unsigned long flags; - - spin_lock_irqsave(&sdla_lock, flags); - __sdla_write(dev, addr, buf, len); - spin_unlock_irqrestore(&sdla_lock, flags); -} - - -static void sdla_clear(struct net_device *dev) -{ - unsigned long flags; - char *base; - int len, addr, bytes; - - len = 65536; - addr = 0; - bytes = SDLA_WINDOW_SIZE; - base = (void *) dev->mem_start; - - spin_lock_irqsave(&sdla_lock, flags); - while(len) - { - SDLA_WINDOW(dev, addr); - memset(base, 0, bytes); - - addr += bytes; - len -= bytes; - } - spin_unlock_irqrestore(&sdla_lock, flags); - -} - -static char sdla_byte(struct net_device *dev, int addr) -{ - unsigned long flags; - char byte, *temp; - - temp = (void *) (dev->mem_start + (addr & SDLA_ADDR_MASK)); - - spin_lock_irqsave(&sdla_lock, flags); - SDLA_WINDOW(dev, addr); - byte = *temp; - spin_unlock_irqrestore(&sdla_lock, flags); - - return byte; -} - -static void sdla_stop(struct net_device *dev) -{ - struct frad_local *flp; - - flp = netdev_priv(dev); - switch(flp->type) - { - case SDLA_S502A: - outb(SDLA_S502A_HALT, dev->base_addr + SDLA_REG_CONTROL); - flp->state = SDLA_HALT; - break; - case SDLA_S502E: - outb(SDLA_HALT, dev->base_addr + SDLA_REG_Z80_CONTROL); - outb(SDLA_S502E_ENABLE, dev->base_addr + SDLA_REG_CONTROL); - flp->state = SDLA_S502E_ENABLE; - break; - case SDLA_S507: - flp->state &= ~SDLA_CPUEN; - outb(flp->state, dev->base_addr + SDLA_REG_CONTROL); - break; - case SDLA_S508: - flp->state &= ~SDLA_CPUEN; - outb(flp->state, dev->base_addr + SDLA_REG_CONTROL); - break; - } -} - -static void sdla_start(struct net_device *dev) -{ - struct frad_local *flp; - - flp = netdev_priv(dev); - switch(flp->type) - { - case SDLA_S502A: - outb(SDLA_S502A_NMI, dev->base_addr + SDLA_REG_CONTROL); - outb(SDLA_S502A_START, dev->base_addr + SDLA_REG_CONTROL); - flp->state = SDLA_S502A_START; - break; - case SDLA_S502E: - outb(SDLA_S502E_CPUEN, dev->base_addr + SDLA_REG_Z80_CONTROL); - outb(0x00, dev->base_addr + SDLA_REG_CONTROL); - flp->state = 0; - break; - case SDLA_S507: - flp->state |= SDLA_CPUEN; - outb(flp->state, dev->base_addr + SDLA_REG_CONTROL); - break; - case SDLA_S508: - flp->state |= SDLA_CPUEN; - outb(flp->state, dev->base_addr + SDLA_REG_CONTROL); - break; - } -} - -/**************************************************** - * - * this is used for the S502A/E cards to determine - * the speed of the onboard CPU. Calibration is - * necessary for the Frame Relay code uploaded - * later. Incorrect results cause timing problems - * with link checks & status messages - * - ***************************************************/ - -static int sdla_z80_poll(struct net_device *dev, int z80_addr, int jiffs, char resp1, char resp2) -{ - unsigned long start, done, now; - char resp, *temp; - - start = now = jiffies; - done = jiffies + jiffs; - - temp = (void *)dev->mem_start; - temp += z80_addr & SDLA_ADDR_MASK; - - resp = ~resp1; - while (time_before(jiffies, done) && (resp != resp1) && (!resp2 || (resp != resp2))) - { - if (jiffies != now) - { - SDLA_WINDOW(dev, z80_addr); - now = jiffies; - resp = *temp; - } - } - return time_before(jiffies, done) ? jiffies - start : -1; -} - -/* constants for Z80 CPU speed */ -#define Z80_READY '1' /* Z80 is ready to begin */ -#define LOADER_READY '2' /* driver is ready to begin */ -#define Z80_SCC_OK '3' /* SCC is on board */ -#define Z80_SCC_BAD '4' /* SCC was not found */ - -static int sdla_cpuspeed(struct net_device *dev, struct ifreq *ifr) -{ - int jiffs; - char data; - - sdla_start(dev); - if (sdla_z80_poll(dev, 0, 3*HZ, Z80_READY, 0) < 0) - return -EIO; - - data = LOADER_READY; - sdla_write(dev, 0, &data, 1); - - if ((jiffs = sdla_z80_poll(dev, 0, 8*HZ, Z80_SCC_OK, Z80_SCC_BAD)) < 0) - return -EIO; - - sdla_stop(dev); - sdla_read(dev, 0, &data, 1); - - if (data == Z80_SCC_BAD) - { - printk("%s: SCC bad\n", dev->name); - return -EIO; - } - - if (data != Z80_SCC_OK) - return -EINVAL; - - if (jiffs < 165) - ifr->ifr_mtu = SDLA_CPU_16M; - else if (jiffs < 220) - ifr->ifr_mtu = SDLA_CPU_10M; - else if (jiffs < 258) - ifr->ifr_mtu = SDLA_CPU_8M; - else if (jiffs < 357) - ifr->ifr_mtu = SDLA_CPU_7M; - else if (jiffs < 467) - ifr->ifr_mtu = SDLA_CPU_5M; - else - ifr->ifr_mtu = SDLA_CPU_3M; - - return 0; -} - -/************************************************ - * - * Direct interaction with the Frame Relay code - * starts here. - * - ************************************************/ - -struct _dlci_stat -{ - short dlci; - char flags; -} __packed; - -struct _frad_stat -{ - char flags; - struct _dlci_stat dlcis[SDLA_MAX_DLCI]; -}; - -static void sdla_errors(struct net_device *dev, int cmd, int dlci, int ret, int len, void *data) -{ - struct _dlci_stat *pstatus; - short *pdlci; - int i; - char *state, line[30]; - - switch (ret) - { - case SDLA_RET_MODEM: - state = data; - if (*state & SDLA_MODEM_DCD_LOW) - netdev_info(dev, "Modem DCD unexpectedly low!\n"); - if (*state & SDLA_MODEM_CTS_LOW) - netdev_info(dev, "Modem CTS unexpectedly low!\n"); - /* I should probably do something about this! */ - break; - - case SDLA_RET_CHANNEL_OFF: - netdev_info(dev, "Channel became inoperative!\n"); - /* same here */ - break; - - case SDLA_RET_CHANNEL_ON: - netdev_info(dev, "Channel became operative!\n"); - /* same here */ - break; - - case SDLA_RET_DLCI_STATUS: - netdev_info(dev, "Status change reported by Access Node\n"); - len /= sizeof(struct _dlci_stat); - for(pstatus = data, i=0;i < len;i++,pstatus++) - { - if (pstatus->flags & SDLA_DLCI_NEW) - state = "new"; - else if (pstatus->flags & SDLA_DLCI_DELETED) - state = "deleted"; - else if (pstatus->flags & SDLA_DLCI_ACTIVE) - state = "active"; - else - { - sprintf(line, "unknown status: %02X", pstatus->flags); - state = line; - } - netdev_info(dev, "DLCI %i: %s\n", - pstatus->dlci, state); - /* same here */ - } - break; - - case SDLA_RET_DLCI_UNKNOWN: - netdev_info(dev, "Received unknown DLCIs:"); - len /= sizeof(short); - for(pdlci = data,i=0;i < len;i++,pdlci++) - pr_cont(" %i", *pdlci); - pr_cont("\n"); - break; - - case SDLA_RET_TIMEOUT: - netdev_err(dev, "Command timed out!\n"); - break; - - case SDLA_RET_BUF_OVERSIZE: - netdev_info(dev, "Bc/CIR overflow, acceptable size is %i\n", - len); - break; - - case SDLA_RET_BUF_TOO_BIG: - netdev_info(dev, "Buffer size over specified max of %i\n", - len); - break; - - case SDLA_RET_CHANNEL_INACTIVE: - case SDLA_RET_DLCI_INACTIVE: - case SDLA_RET_CIR_OVERFLOW: - case SDLA_RET_NO_BUFS: - if (cmd == SDLA_INFORMATION_WRITE) - break; - fallthrough; - - default: - netdev_dbg(dev, "Cmd 0x%02X generated return code 0x%02X\n", - cmd, ret); - /* Further processing could be done here */ - break; - } -} - -static int sdla_cmd(struct net_device *dev, int cmd, short dlci, short flags, - void *inbuf, short inlen, void *outbuf, short *outlen) -{ - static struct _frad_stat status; - struct frad_local *flp; - struct sdla_cmd *cmd_buf; - unsigned long pflags; - unsigned long jiffs; - int ret, waiting, len; - long window; - - flp = netdev_priv(dev); - window = flp->type == SDLA_S508 ? SDLA_508_CMD_BUF : SDLA_502_CMD_BUF; - cmd_buf = (struct sdla_cmd *)(dev->mem_start + (window & SDLA_ADDR_MASK)); - ret = 0; - len = 0; - jiffs = jiffies + HZ; /* 1 second is plenty */ - - spin_lock_irqsave(&sdla_lock, pflags); - SDLA_WINDOW(dev, window); - cmd_buf->cmd = cmd; - cmd_buf->dlci = dlci; - cmd_buf->flags = flags; - - if (inbuf) - memcpy(cmd_buf->data, inbuf, inlen); - - cmd_buf->length = inlen; - - cmd_buf->opp_flag = 1; - spin_unlock_irqrestore(&sdla_lock, pflags); - - waiting = 1; - len = 0; - while (waiting && time_before_eq(jiffies, jiffs)) - { - if (waiting++ % 3) - { - spin_lock_irqsave(&sdla_lock, pflags); - SDLA_WINDOW(dev, window); - waiting = ((volatile int)(cmd_buf->opp_flag)); - spin_unlock_irqrestore(&sdla_lock, pflags); - } - } - - if (!waiting) - { - - spin_lock_irqsave(&sdla_lock, pflags); - SDLA_WINDOW(dev, window); - ret = cmd_buf->retval; - len = cmd_buf->length; - if (outbuf && outlen) - { - *outlen = *outlen >= len ? len : *outlen; - - if (*outlen) - memcpy(outbuf, cmd_buf->data, *outlen); - } - - /* This is a local copy that's used for error handling */ - if (ret) - memcpy(&status, cmd_buf->data, len > sizeof(status) ? sizeof(status) : len); - - spin_unlock_irqrestore(&sdla_lock, pflags); - } - else - ret = SDLA_RET_TIMEOUT; - - if (ret != SDLA_RET_OK) - sdla_errors(dev, cmd, dlci, ret, len, &status); - - return ret; -} - -/*********************************************** - * - * these functions are called by the DLCI driver - * - ***********************************************/ - -static int sdla_reconfig(struct net_device *dev); - -static int sdla_activate(struct net_device *slave, struct net_device *master) -{ - struct frad_local *flp; - int i; - - flp = netdev_priv(slave); - - for(i=0;imaster[i] == master) - break; - - if (i == CONFIG_DLCI_MAX) - return -ENODEV; - - flp->dlci[i] = abs(flp->dlci[i]); - - if (netif_running(slave) && (flp->config.station == FRAD_STATION_NODE)) - sdla_cmd(slave, SDLA_ACTIVATE_DLCI, 0, 0, &flp->dlci[i], sizeof(short), NULL, NULL); - - return 0; -} - -static int sdla_deactivate(struct net_device *slave, struct net_device *master) -{ - struct frad_local *flp; - int i; - - flp = netdev_priv(slave); - - for(i=0;imaster[i] == master) - break; - - if (i == CONFIG_DLCI_MAX) - return -ENODEV; - - flp->dlci[i] = -abs(flp->dlci[i]); - - if (netif_running(slave) && (flp->config.station == FRAD_STATION_NODE)) - sdla_cmd(slave, SDLA_DEACTIVATE_DLCI, 0, 0, &flp->dlci[i], sizeof(short), NULL, NULL); - - return 0; -} - -static int sdla_assoc(struct net_device *slave, struct net_device *master) -{ - struct frad_local *flp; - int i; - - if (master->type != ARPHRD_DLCI) - return -EINVAL; - - flp = netdev_priv(slave); - - for(i=0;imaster[i]) - break; - if (abs(flp->dlci[i]) == *(short *)(master->dev_addr)) - return -EADDRINUSE; - } - - if (i == CONFIG_DLCI_MAX) - return -EMLINK; /* #### Alan: Comments on this ?? */ - - - flp->master[i] = master; - flp->dlci[i] = -*(short *)(master->dev_addr); - master->mtu = slave->mtu; - - if (netif_running(slave)) { - if (flp->config.station == FRAD_STATION_CPE) - sdla_reconfig(slave); - else - sdla_cmd(slave, SDLA_ADD_DLCI, 0, 0, master->dev_addr, sizeof(short), NULL, NULL); - } - - return 0; -} - -static int sdla_deassoc(struct net_device *slave, struct net_device *master) -{ - struct frad_local *flp; - int i; - - flp = netdev_priv(slave); - - for(i=0;imaster[i] == master) - break; - - if (i == CONFIG_DLCI_MAX) - return -ENODEV; - - flp->master[i] = NULL; - flp->dlci[i] = 0; - - - if (netif_running(slave)) { - if (flp->config.station == FRAD_STATION_CPE) - sdla_reconfig(slave); - else - sdla_cmd(slave, SDLA_DELETE_DLCI, 0, 0, master->dev_addr, sizeof(short), NULL, NULL); - } - - return 0; -} - -static int sdla_dlci_conf(struct net_device *slave, struct net_device *master, int get) -{ - struct frad_local *flp; - struct dlci_local *dlp; - int i; - short len, ret; - - flp = netdev_priv(slave); - - for(i=0;imaster[i] == master) - break; - - if (i == CONFIG_DLCI_MAX) - return -ENODEV; - - dlp = netdev_priv(master); - - ret = SDLA_RET_OK; - len = sizeof(struct dlci_conf); - if (netif_running(slave)) { - if (get) - ret = sdla_cmd(slave, SDLA_READ_DLCI_CONFIGURATION, abs(flp->dlci[i]), 0, - NULL, 0, &dlp->config, &len); - else - ret = sdla_cmd(slave, SDLA_SET_DLCI_CONFIGURATION, abs(flp->dlci[i]), 0, - &dlp->config, sizeof(struct dlci_conf) - 4 * sizeof(short), NULL, NULL); - } - - return ret == SDLA_RET_OK ? 0 : -EIO; -} - -/************************** - * - * now for the Linux driver - * - **************************/ - -/* NOTE: the DLCI driver deals with freeing the SKB!! */ -static netdev_tx_t sdla_transmit(struct sk_buff *skb, - struct net_device *dev) -{ - struct frad_local *flp; - int ret, addr, accept, i; - short size; - unsigned long flags; - struct buf_entry *pbuf; - - flp = netdev_priv(dev); - ret = 0; - accept = 1; - - netif_stop_queue(dev); - - /* - * stupid GateD insists on setting up the multicast router thru us - * and we're ill equipped to handle a non Frame Relay packet at this - * time! - */ - - accept = 1; - switch (dev->type) - { - case ARPHRD_FRAD: - if (skb->dev->type != ARPHRD_DLCI) - { - netdev_warn(dev, "Non DLCI device, type %i, tried to send on FRAD module\n", - skb->dev->type); - accept = 0; - } - break; - default: - netdev_warn(dev, "unknown firmware type 0x%04X\n", - dev->type); - accept = 0; - break; - } - if (accept) - { - /* this is frame specific, but till there's a PPP module, it's the default */ - switch (flp->type) - { - case SDLA_S502A: - case SDLA_S502E: - ret = sdla_cmd(dev, SDLA_INFORMATION_WRITE, *(short *)(skb->dev->dev_addr), 0, skb->data, skb->len, NULL, NULL); - break; - case SDLA_S508: - size = sizeof(addr); - ret = sdla_cmd(dev, SDLA_INFORMATION_WRITE, *(short *)(skb->dev->dev_addr), 0, NULL, skb->len, &addr, &size); - if (ret == SDLA_RET_OK) - { - - spin_lock_irqsave(&sdla_lock, flags); - SDLA_WINDOW(dev, addr); - pbuf = (void *)(dev->mem_start + (addr & SDLA_ADDR_MASK)); - __sdla_write(dev, pbuf->buf_addr, skb->data, skb->len); - SDLA_WINDOW(dev, addr); - pbuf->opp_flag = 1; - spin_unlock_irqrestore(&sdla_lock, flags); - } - break; - } - - switch (ret) - { - case SDLA_RET_OK: - dev->stats.tx_packets++; - break; - - case SDLA_RET_CIR_OVERFLOW: - case SDLA_RET_BUF_OVERSIZE: - case SDLA_RET_NO_BUFS: - dev->stats.tx_dropped++; - break; - - default: - dev->stats.tx_errors++; - break; - } - } - netif_wake_queue(dev); - for(i=0;imaster[i]!=NULL) - netif_wake_queue(flp->master[i]); - } - - dev_kfree_skb(skb); - return NETDEV_TX_OK; -} - -static void sdla_receive(struct net_device *dev) -{ - struct net_device *master; - struct frad_local *flp; - struct dlci_local *dlp; - struct sk_buff *skb; - - struct sdla_cmd *cmd; - struct buf_info *pbufi; - struct buf_entry *pbuf; - - unsigned long flags; - int i=0, received, success, addr, buf_base, buf_top; - short dlci, len, len2, split; - - flp = netdev_priv(dev); - success = 1; - received = addr = buf_top = buf_base = 0; - len = dlci = 0; - skb = NULL; - master = NULL; - cmd = NULL; - pbufi = NULL; - pbuf = NULL; - - spin_lock_irqsave(&sdla_lock, flags); - - switch (flp->type) - { - case SDLA_S502A: - case SDLA_S502E: - cmd = (void *) (dev->mem_start + (SDLA_502_RCV_BUF & SDLA_ADDR_MASK)); - SDLA_WINDOW(dev, SDLA_502_RCV_BUF); - success = cmd->opp_flag; - if (!success) - break; - - dlci = cmd->dlci; - len = cmd->length; - break; - - case SDLA_S508: - pbufi = (void *) (dev->mem_start + (SDLA_508_RXBUF_INFO & SDLA_ADDR_MASK)); - SDLA_WINDOW(dev, SDLA_508_RXBUF_INFO); - pbuf = (void *) (dev->mem_start + ((pbufi->rse_base + flp->buffer * sizeof(struct buf_entry)) & SDLA_ADDR_MASK)); - success = pbuf->opp_flag; - if (!success) - break; - - buf_top = pbufi->buf_top; - buf_base = pbufi->buf_base; - dlci = pbuf->dlci; - len = pbuf->length; - addr = pbuf->buf_addr; - break; - } - - /* common code, find the DLCI and get the SKB */ - if (success) - { - for (i=0;idlci[i] == dlci) - break; - - if (i == CONFIG_DLCI_MAX) - { - netdev_notice(dev, "Received packet from invalid DLCI %i, ignoring\n", - dlci); - dev->stats.rx_errors++; - success = 0; - } - } - - if (success) - { - master = flp->master[i]; - skb = dev_alloc_skb(len + sizeof(struct frhdr)); - if (skb == NULL) - { - netdev_notice(dev, "Memory squeeze, dropping packet\n"); - dev->stats.rx_dropped++; - success = 0; - } - else - skb_reserve(skb, sizeof(struct frhdr)); - } - - /* pick up the data */ - switch (flp->type) - { - case SDLA_S502A: - case SDLA_S502E: - if (success) - __sdla_read(dev, SDLA_502_RCV_BUF + SDLA_502_DATA_OFS, skb_put(skb,len), len); - - SDLA_WINDOW(dev, SDLA_502_RCV_BUF); - cmd->opp_flag = 0; - break; - - case SDLA_S508: - if (success) - { - /* is this buffer split off the end of the internal ring buffer */ - split = addr + len > buf_top + 1 ? len - (buf_top - addr + 1) : 0; - len2 = len - split; - - __sdla_read(dev, addr, skb_put(skb, len2), len2); - if (split) - __sdla_read(dev, buf_base, skb_put(skb, split), split); - } - - /* increment the buffer we're looking at */ - SDLA_WINDOW(dev, SDLA_508_RXBUF_INFO); - flp->buffer = (flp->buffer + 1) % pbufi->rse_num; - pbuf->opp_flag = 0; - break; - } - - if (success) - { - dev->stats.rx_packets++; - dlp = netdev_priv(master); - (*dlp->receive)(skb, master); - } - - spin_unlock_irqrestore(&sdla_lock, flags); -} - -static irqreturn_t sdla_isr(int dummy, void *dev_id) -{ - struct net_device *dev; - struct frad_local *flp; - char byte; - - dev = dev_id; - - flp = netdev_priv(dev); - - if (!flp->initialized) - { - netdev_warn(dev, "irq %d for uninitialized device\n", dev->irq); - return IRQ_NONE; - } - - byte = sdla_byte(dev, flp->type == SDLA_S508 ? SDLA_508_IRQ_INTERFACE : SDLA_502_IRQ_INTERFACE); - switch (byte) - { - case SDLA_INTR_RX: - sdla_receive(dev); - break; - - /* the command will get an error return, which is processed above */ - case SDLA_INTR_MODEM: - case SDLA_INTR_STATUS: - sdla_cmd(dev, SDLA_READ_DLC_STATUS, 0, 0, NULL, 0, NULL, NULL); - break; - - case SDLA_INTR_TX: - case SDLA_INTR_COMPLETE: - case SDLA_INTR_TIMER: - netdev_warn(dev, "invalid irq flag 0x%02X\n", byte); - break; - } - - /* the S502E requires a manual acknowledgement of the interrupt */ - if (flp->type == SDLA_S502E) - { - flp->state &= ~SDLA_S502E_INTACK; - outb(flp->state, dev->base_addr + SDLA_REG_CONTROL); - flp->state |= SDLA_S502E_INTACK; - outb(flp->state, dev->base_addr + SDLA_REG_CONTROL); - } - - /* this clears the byte, informing the Z80 we're done */ - byte = 0; - sdla_write(dev, flp->type == SDLA_S508 ? SDLA_508_IRQ_INTERFACE : SDLA_502_IRQ_INTERFACE, &byte, sizeof(byte)); - return IRQ_HANDLED; -} - -static void sdla_poll(struct timer_list *t) -{ - struct frad_local *flp = from_timer(flp, t, timer); - struct net_device *dev = flp->dev; - - if (sdla_byte(dev, SDLA_502_RCV_BUF)) - sdla_receive(dev); - - flp->timer.expires = 1; - add_timer(&flp->timer); -} - -static int sdla_close(struct net_device *dev) -{ - struct frad_local *flp; - struct intr_info intr; - int len, i; - short dlcis[CONFIG_DLCI_MAX]; - - flp = netdev_priv(dev); - - len = 0; - for(i=0;idlci[i]) - dlcis[len++] = abs(flp->dlci[i]); - len *= 2; - - if (flp->config.station == FRAD_STATION_NODE) - { - for(i=0;idlci[i] > 0) - sdla_cmd(dev, SDLA_DEACTIVATE_DLCI, 0, 0, dlcis, len, NULL, NULL); - sdla_cmd(dev, SDLA_DELETE_DLCI, 0, 0, &flp->dlci[i], sizeof(flp->dlci[i]), NULL, NULL); - } - - memset(&intr, 0, sizeof(intr)); - /* let's start up the reception */ - switch(flp->type) - { - case SDLA_S502A: - del_timer(&flp->timer); - break; - - case SDLA_S502E: - sdla_cmd(dev, SDLA_SET_IRQ_TRIGGER, 0, 0, &intr, sizeof(char) + sizeof(short), NULL, NULL); - flp->state &= ~SDLA_S502E_INTACK; - outb(flp->state, dev->base_addr + SDLA_REG_CONTROL); - break; - - case SDLA_S507: - break; - - case SDLA_S508: - sdla_cmd(dev, SDLA_SET_IRQ_TRIGGER, 0, 0, &intr, sizeof(struct intr_info), NULL, NULL); - flp->state &= ~SDLA_S508_INTEN; - outb(flp->state, dev->base_addr + SDLA_REG_CONTROL); - break; - } - - sdla_cmd(dev, SDLA_DISABLE_COMMUNICATIONS, 0, 0, NULL, 0, NULL, NULL); - - netif_stop_queue(dev); - - return 0; -} - -struct conf_data { - struct frad_conf config; - short dlci[CONFIG_DLCI_MAX]; -}; - -static int sdla_open(struct net_device *dev) -{ - struct frad_local *flp; - struct dlci_local *dlp; - struct conf_data data; - struct intr_info intr; - int len, i; - char byte; - - flp = netdev_priv(dev); - - if (!flp->initialized) - return -EPERM; - - if (!flp->configured) - return -EPERM; - - /* time to send in the configuration */ - len = 0; - for(i=0;idlci[i]) - data.dlci[len++] = abs(flp->dlci[i]); - len *= 2; - - memcpy(&data.config, &flp->config, sizeof(struct frad_conf)); - len += sizeof(struct frad_conf); - - sdla_cmd(dev, SDLA_DISABLE_COMMUNICATIONS, 0, 0, NULL, 0, NULL, NULL); - sdla_cmd(dev, SDLA_SET_DLCI_CONFIGURATION, 0, 0, &data, len, NULL, NULL); - - if (flp->type == SDLA_S508) - flp->buffer = 0; - - sdla_cmd(dev, SDLA_ENABLE_COMMUNICATIONS, 0, 0, NULL, 0, NULL, NULL); - - /* let's start up the reception */ - memset(&intr, 0, sizeof(intr)); - switch(flp->type) - { - case SDLA_S502A: - flp->timer.expires = 1; - add_timer(&flp->timer); - break; - - case SDLA_S502E: - flp->state |= SDLA_S502E_ENABLE; - outb(flp->state, dev->base_addr + SDLA_REG_CONTROL); - flp->state |= SDLA_S502E_INTACK; - outb(flp->state, dev->base_addr + SDLA_REG_CONTROL); - byte = 0; - sdla_write(dev, SDLA_502_IRQ_INTERFACE, &byte, sizeof(byte)); - intr.flags = SDLA_INTR_RX | SDLA_INTR_STATUS | SDLA_INTR_MODEM; - sdla_cmd(dev, SDLA_SET_IRQ_TRIGGER, 0, 0, &intr, sizeof(char) + sizeof(short), NULL, NULL); - break; - - case SDLA_S507: - break; - - case SDLA_S508: - flp->state |= SDLA_S508_INTEN; - outb(flp->state, dev->base_addr + SDLA_REG_CONTROL); - byte = 0; - sdla_write(dev, SDLA_508_IRQ_INTERFACE, &byte, sizeof(byte)); - intr.flags = SDLA_INTR_RX | SDLA_INTR_STATUS | SDLA_INTR_MODEM; - intr.irq = dev->irq; - sdla_cmd(dev, SDLA_SET_IRQ_TRIGGER, 0, 0, &intr, sizeof(struct intr_info), NULL, NULL); - break; - } - - if (flp->config.station == FRAD_STATION_CPE) - { - byte = SDLA_ICS_STATUS_ENQ; - sdla_cmd(dev, SDLA_ISSUE_IN_CHANNEL_SIGNAL, 0, 0, &byte, sizeof(byte), NULL, NULL); - } - else - { - sdla_cmd(dev, SDLA_ADD_DLCI, 0, 0, data.dlci, len - sizeof(struct frad_conf), NULL, NULL); - for(i=0;idlci[i] > 0) - sdla_cmd(dev, SDLA_ACTIVATE_DLCI, 0, 0, &flp->dlci[i], 2*sizeof(flp->dlci[i]), NULL, NULL); - } - - /* configure any specific DLCI settings */ - for(i=0;idlci[i]) - { - dlp = netdev_priv(flp->master[i]); - if (dlp->configured) - sdla_cmd(dev, SDLA_SET_DLCI_CONFIGURATION, abs(flp->dlci[i]), 0, &dlp->config, sizeof(struct dlci_conf), NULL, NULL); - } - - netif_start_queue(dev); - - return 0; -} - -static int sdla_config(struct net_device *dev, struct frad_conf __user *conf, int get) -{ - struct frad_local *flp; - struct conf_data data; - int i; - short size; - - if (dev->type == 0xFFFF) - return -EUNATCH; - - flp = netdev_priv(dev); - - if (!get) - { - if (netif_running(dev)) - return -EBUSY; - - if(copy_from_user(&data.config, conf, sizeof(struct frad_conf))) - return -EFAULT; - - if (data.config.station & ~FRAD_STATION_NODE) - return -EINVAL; - - if (data.config.flags & ~FRAD_VALID_FLAGS) - return -EINVAL; - - if ((data.config.kbaud < 0) || - ((data.config.kbaud > 128) && (flp->type != SDLA_S508))) - return -EINVAL; - - if (data.config.clocking & ~(FRAD_CLOCK_INT | SDLA_S508_PORT_RS232)) - return -EINVAL; - - if ((data.config.mtu < 0) || (data.config.mtu > SDLA_MAX_MTU)) - return -EINVAL; - - if ((data.config.T391 < 5) || (data.config.T391 > 30)) - return -EINVAL; - - if ((data.config.T392 < 5) || (data.config.T392 > 30)) - return -EINVAL; - - if ((data.config.N391 < 1) || (data.config.N391 > 255)) - return -EINVAL; - - if ((data.config.N392 < 1) || (data.config.N392 > 10)) - return -EINVAL; - - if ((data.config.N393 < 1) || (data.config.N393 > 10)) - return -EINVAL; - - memcpy(&flp->config, &data.config, sizeof(struct frad_conf)); - flp->config.flags |= SDLA_DIRECT_RECV; - - if (flp->type == SDLA_S508) - flp->config.flags |= SDLA_TX70_RX30; - - if (dev->mtu != flp->config.mtu) - { - /* this is required to change the MTU */ - dev->mtu = flp->config.mtu; - for(i=0;imaster[i]) - flp->master[i]->mtu = flp->config.mtu; - } - - flp->config.mtu += sizeof(struct frhdr); - - /* off to the races! */ - if (!flp->configured) - sdla_start(dev); - - flp->configured = 1; - } - else - { - /* no sense reading if the CPU isn't started */ - if (netif_running(dev)) - { - size = sizeof(data); - if (sdla_cmd(dev, SDLA_READ_DLCI_CONFIGURATION, 0, 0, NULL, 0, &data, &size) != SDLA_RET_OK) - return -EIO; - } - else - if (flp->configured) - memcpy(&data.config, &flp->config, sizeof(struct frad_conf)); - else - memset(&data.config, 0, sizeof(struct frad_conf)); - - memcpy(&flp->config, &data.config, sizeof(struct frad_conf)); - data.config.flags &= FRAD_VALID_FLAGS; - data.config.mtu -= data.config.mtu > sizeof(struct frhdr) ? sizeof(struct frhdr) : data.config.mtu; - return copy_to_user(conf, &data.config, sizeof(struct frad_conf))?-EFAULT:0; - } - - return 0; -} - -static int sdla_xfer(struct net_device *dev, struct sdla_mem __user *info, int read) -{ - struct sdla_mem mem; - char *temp; - - if(copy_from_user(&mem, info, sizeof(mem))) - return -EFAULT; - - if (read) - { - temp = kzalloc(mem.len, GFP_KERNEL); - if (!temp) - return -ENOMEM; - sdla_read(dev, mem.addr, temp, mem.len); - if(copy_to_user(mem.data, temp, mem.len)) - { - kfree(temp); - return -EFAULT; - } - kfree(temp); - } - else - { - temp = memdup_user(mem.data, mem.len); - if (IS_ERR(temp)) - return PTR_ERR(temp); - sdla_write(dev, mem.addr, temp, mem.len); - kfree(temp); - } - return 0; -} - -static int sdla_reconfig(struct net_device *dev) -{ - struct frad_local *flp; - struct conf_data data; - int i, len; - - flp = netdev_priv(dev); - - len = 0; - for(i=0;idlci[i]) - data.dlci[len++] = flp->dlci[i]; - len *= 2; - - memcpy(&data, &flp->config, sizeof(struct frad_conf)); - len += sizeof(struct frad_conf); - - sdla_cmd(dev, SDLA_DISABLE_COMMUNICATIONS, 0, 0, NULL, 0, NULL, NULL); - sdla_cmd(dev, SDLA_SET_DLCI_CONFIGURATION, 0, 0, &data, len, NULL, NULL); - sdla_cmd(dev, SDLA_ENABLE_COMMUNICATIONS, 0, 0, NULL, 0, NULL, NULL); - - return 0; -} - -static int sdla_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) -{ - struct frad_local *flp; - - if(!capable(CAP_NET_ADMIN)) - return -EPERM; - - flp = netdev_priv(dev); - - if (!flp->initialized) - return -EINVAL; - - switch (cmd) - { - case FRAD_GET_CONF: - case FRAD_SET_CONF: - return sdla_config(dev, ifr->ifr_data, cmd == FRAD_GET_CONF); - - case SDLA_IDENTIFY: - ifr->ifr_flags = flp->type; - break; - - case SDLA_CPUSPEED: - return sdla_cpuspeed(dev, ifr); - -/* ========================================================== -NOTE: This is rather a useless action right now, as the - current driver does not support protocols other than - FR. However, Sangoma has modules for a number of - other protocols in the works. -============================================================*/ - case SDLA_PROTOCOL: - if (flp->configured) - return -EALREADY; - - switch (ifr->ifr_flags) - { - case ARPHRD_FRAD: - dev->type = ifr->ifr_flags; - break; - default: - return -ENOPROTOOPT; - } - break; - - case SDLA_CLEARMEM: - sdla_clear(dev); - break; - - case SDLA_WRITEMEM: - case SDLA_READMEM: - if(!capable(CAP_SYS_RAWIO)) - return -EPERM; - return sdla_xfer(dev, ifr->ifr_data, cmd == SDLA_READMEM); - - case SDLA_START: - sdla_start(dev); - break; - - case SDLA_STOP: - sdla_stop(dev); - break; - - default: - return -EOPNOTSUPP; - } - return 0; -} - -static int sdla_change_mtu(struct net_device *dev, int new_mtu) -{ - if (netif_running(dev)) - return -EBUSY; - - /* for now, you can't change the MTU! */ - return -EOPNOTSUPP; -} - -static int sdla_set_config(struct net_device *dev, struct ifmap *map) -{ - struct frad_local *flp; - int i; - char byte; - unsigned base; - int err = -EINVAL; - - flp = netdev_priv(dev); - - if (flp->initialized) - return -EINVAL; - - for(i=0; i < ARRAY_SIZE(valid_port); i++) - if (valid_port[i] == map->base_addr) - break; - - if (i == ARRAY_SIZE(valid_port)) - return -EINVAL; - - if (!request_region(map->base_addr, SDLA_IO_EXTENTS, dev->name)){ - pr_warn("io-port 0x%04lx in use\n", dev->base_addr); - return -EINVAL; - } - base = map->base_addr; - - /* test for card types, S502A, S502E, S507, S508 */ - /* these tests shut down the card completely, so clear the state */ - flp->type = SDLA_UNKNOWN; - flp->state = 0; - - for(i=1;itype = SDLA_S502E; - goto got_type; - } - } - } - - for(byte=inb(base),i=0;itype = SDLA_S507; - goto got_type; - } - } - } - - outb(SDLA_HALT, base + SDLA_REG_CONTROL); - if ((inb(base + SDLA_S508_STS) & 0x3F) == 0x00) { - outb(SDLA_S508_INTEN, base + SDLA_REG_CONTROL); - if ((inb(base + SDLA_S508_STS) & 0x3F) == 0x10) { - outb(SDLA_HALT, base + SDLA_REG_CONTROL); - flp->type = SDLA_S508; - goto got_type; - } - } - - outb(SDLA_S502A_HALT, base + SDLA_REG_CONTROL); - if (inb(base + SDLA_S502_STS) == 0x40) { - outb(SDLA_S502A_START, base + SDLA_REG_CONTROL); - if (inb(base + SDLA_S502_STS) == 0x40) { - outb(SDLA_S502A_INTEN, base + SDLA_REG_CONTROL); - if (inb(base + SDLA_S502_STS) == 0x44) { - outb(SDLA_S502A_START, base + SDLA_REG_CONTROL); - flp->type = SDLA_S502A; - goto got_type; - } - } - } - - netdev_notice(dev, "Unknown card type\n"); - err = -ENODEV; - goto fail; - -got_type: - switch(base) { - case 0x270: - case 0x280: - case 0x380: - case 0x390: - if (flp->type != SDLA_S508 && flp->type != SDLA_S507) - goto fail; - } - - switch (map->irq) { - case 2: - if (flp->type != SDLA_S502E) - goto fail; - break; - - case 10: - case 11: - case 12: - case 15: - case 4: - if (flp->type != SDLA_S508 && flp->type != SDLA_S507) - goto fail; - break; - case 3: - case 5: - case 7: - if (flp->type == SDLA_S502A) - goto fail; - break; - - default: - goto fail; - } - - err = -EAGAIN; - if (request_irq(dev->irq, sdla_isr, 0, dev->name, dev)) - goto fail; - - if (flp->type == SDLA_S507) { - switch(dev->irq) { - case 3: - flp->state = SDLA_S507_IRQ3; - break; - case 4: - flp->state = SDLA_S507_IRQ4; - break; - case 5: - flp->state = SDLA_S507_IRQ5; - break; - case 7: - flp->state = SDLA_S507_IRQ7; - break; - case 10: - flp->state = SDLA_S507_IRQ10; - break; - case 11: - flp->state = SDLA_S507_IRQ11; - break; - case 12: - flp->state = SDLA_S507_IRQ12; - break; - case 15: - flp->state = SDLA_S507_IRQ15; - break; - } - } - - for(i=0; i < ARRAY_SIZE(valid_mem); i++) - if (valid_mem[i] == map->mem_start) - break; - - err = -EINVAL; - if (i == ARRAY_SIZE(valid_mem)) - goto fail2; - - if (flp->type == SDLA_S502A && (map->mem_start & 0xF000) >> 12 == 0x0E) - goto fail2; - - if (flp->type != SDLA_S507 && map->mem_start >> 16 == 0x0B) - goto fail2; - - if (flp->type == SDLA_S507 && map->mem_start >> 16 == 0x0D) - goto fail2; - - byte = flp->type != SDLA_S508 ? SDLA_8K_WINDOW : 0; - byte |= (map->mem_start & 0xF000) >> (12 + (flp->type == SDLA_S508 ? 1 : 0)); - switch(flp->type) { - case SDLA_S502A: - case SDLA_S502E: - switch (map->mem_start >> 16) { - case 0x0A: - byte |= SDLA_S502_SEG_A; - break; - case 0x0C: - byte |= SDLA_S502_SEG_C; - break; - case 0x0D: - byte |= SDLA_S502_SEG_D; - break; - case 0x0E: - byte |= SDLA_S502_SEG_E; - break; - } - break; - case SDLA_S507: - switch (map->mem_start >> 16) { - case 0x0A: - byte |= SDLA_S507_SEG_A; - break; - case 0x0B: - byte |= SDLA_S507_SEG_B; - break; - case 0x0C: - byte |= SDLA_S507_SEG_C; - break; - case 0x0E: - byte |= SDLA_S507_SEG_E; - break; - } - break; - case SDLA_S508: - switch (map->mem_start >> 16) { - case 0x0A: - byte |= SDLA_S508_SEG_A; - break; - case 0x0C: - byte |= SDLA_S508_SEG_C; - break; - case 0x0D: - byte |= SDLA_S508_SEG_D; - break; - case 0x0E: - byte |= SDLA_S508_SEG_E; - break; - } - break; - } - - /* set the memory bits, and enable access */ - outb(byte, base + SDLA_REG_PC_WINDOW); - - switch(flp->type) - { - case SDLA_S502E: - flp->state = SDLA_S502E_ENABLE; - break; - case SDLA_S507: - flp->state |= SDLA_MEMEN; - break; - case SDLA_S508: - flp->state = SDLA_MEMEN; - break; - } - outb(flp->state, base + SDLA_REG_CONTROL); - - dev->irq = map->irq; - dev->base_addr = base; - dev->mem_start = map->mem_start; - dev->mem_end = dev->mem_start + 0x2000; - flp->initialized = 1; - return 0; - -fail2: - free_irq(map->irq, dev); -fail: - release_region(base, SDLA_IO_EXTENTS); - return err; -} - -static const struct net_device_ops sdla_netdev_ops = { - .ndo_open = sdla_open, - .ndo_stop = sdla_close, - .ndo_do_ioctl = sdla_ioctl, - .ndo_set_config = sdla_set_config, - .ndo_start_xmit = sdla_transmit, - .ndo_change_mtu = sdla_change_mtu, -}; - -static void setup_sdla(struct net_device *dev) -{ - struct frad_local *flp = netdev_priv(dev); - - netdev_boot_setup_check(dev); - - dev->netdev_ops = &sdla_netdev_ops; - dev->flags = 0; - dev->type = 0xFFFF; - dev->hard_header_len = 0; - dev->addr_len = 0; - dev->mtu = SDLA_MAX_MTU; - - flp->activate = sdla_activate; - flp->deactivate = sdla_deactivate; - flp->assoc = sdla_assoc; - flp->deassoc = sdla_deassoc; - flp->dlci_conf = sdla_dlci_conf; - flp->dev = dev; - - timer_setup(&flp->timer, sdla_poll, 0); - flp->timer.expires = 1; -} - -static struct net_device *sdla; - -static int __init init_sdla(void) -{ - int err; - - printk("%s.\n", version); - - sdla = alloc_netdev(sizeof(struct frad_local), "sdla0", - NET_NAME_UNKNOWN, setup_sdla); - if (!sdla) - return -ENOMEM; - - err = register_netdev(sdla); - if (err) - free_netdev(sdla); - - return err; -} - -static void __exit exit_sdla(void) -{ - struct frad_local *flp = netdev_priv(sdla); - - unregister_netdev(sdla); - if (flp->initialized) { - free_irq(sdla->irq, sdla); - release_region(sdla->base_addr, SDLA_IO_EXTENTS); - } - del_timer_sync(&flp->timer); - free_netdev(sdla); -} - -MODULE_LICENSE("GPL"); - -module_init(init_sdla); -module_exit(exit_sdla); diff --git a/include/linux/if_frad.h b/include/linux/if_frad.h deleted file mode 100644 index 52224de798aa..000000000000 --- a/include/linux/if_frad.h +++ /dev/null @@ -1,92 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * DLCI/FRAD Definitions for Frame Relay Access Devices. DLCI devices are - * created for each DLCI associated with a FRAD. The FRAD driver - * is not truly a network device, but the lower level device - * handler. This allows other FRAD manufacturers to use the DLCI - * code, including its RFC1490 encapsulation alongside the current - * implementation for the Sangoma cards. - * - * Version: @(#)if_ifrad.h 0.15 31 Mar 96 - * - * Author: Mike McLagan - * - * Changes: - * 0.15 Mike McLagan changed structure defs (packed) - * re-arranged flags - * added DLCI_RET vars - */ -#ifndef _FRAD_H_ -#define _FRAD_H_ - -#include - - -#if defined(CONFIG_DLCI) || defined(CONFIG_DLCI_MODULE) - -/* these are the fields of an RFC 1490 header */ -struct frhdr -{ - unsigned char control; - - /* for IP packets, this can be the NLPID */ - unsigned char pad; - - unsigned char NLPID; - unsigned char OUI[3]; - __be16 PID; - -#define IP_NLPID pad -} __packed; - -/* see RFC 1490 for the definition of the following */ -#define FRAD_I_UI 0x03 - -#define FRAD_P_PADDING 0x00 -#define FRAD_P_Q933 0x08 -#define FRAD_P_SNAP 0x80 -#define FRAD_P_CLNP 0x81 -#define FRAD_P_IP 0xCC - -struct dlci_local -{ - struct net_device *master; - struct net_device *slave; - struct dlci_conf config; - int configured; - struct list_head list; - - /* callback function */ - void (*receive)(struct sk_buff *skb, struct net_device *); -}; - -struct frad_local -{ - /* devices which this FRAD is slaved to */ - struct net_device *master[CONFIG_DLCI_MAX]; - short dlci[CONFIG_DLCI_MAX]; - - struct frad_conf config; - int configured; /* has this device been configured */ - int initialized; /* mem_start, port, irq set ? */ - - /* callback functions */ - int (*activate)(struct net_device *, struct net_device *); - int (*deactivate)(struct net_device *, struct net_device *); - int (*assoc)(struct net_device *, struct net_device *); - int (*deassoc)(struct net_device *, struct net_device *); - int (*dlci_conf)(struct net_device *, struct net_device *, int get); - - /* fields that are used by the Sangoma SDLA cards */ - struct timer_list timer; - struct net_device *dev; - int type; /* adapter type */ - int state; /* state of the S502/8 control latch */ - int buffer; /* current buffer for S508 firmware */ -}; - -#endif /* CONFIG_DLCI || CONFIG_DLCI_MODULE */ - -extern void dlci_ioctl_set(int (*hook)(unsigned int, void __user *)); - -#endif diff --git a/include/linux/sdla.h b/include/linux/sdla.h deleted file mode 100644 index 00e8b3b614f0..000000000000 --- a/include/linux/sdla.h +++ /dev/null @@ -1,240 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * INET An implementation of the TCP/IP protocol suite for the LINUX - * operating system. INET is implemented using the BSD Socket - * interface as the means of communication with the user level. - * - * Global definitions for the Frame relay interface. - * - * Version: @(#)if_ifrad.h 0.20 13 Apr 96 - * - * Author: Mike McLagan - * - * Changes: - * 0.15 Mike McLagan Structure packing - * - * 0.20 Mike McLagan New flags for S508 buffer handling - */ -#ifndef SDLA_H -#define SDLA_H - -#include - - -/* important Z80 window addresses */ -#define SDLA_CONTROL_WND 0xE000 - -#define SDLA_502_CMD_BUF 0xEF60 -#define SDLA_502_RCV_BUF 0xA900 -#define SDLA_502_TXN_AVAIL 0xFFF1 -#define SDLA_502_RCV_AVAIL 0xFFF2 -#define SDLA_502_EVENT_FLAGS 0xFFF3 -#define SDLA_502_MDM_STATUS 0xFFF4 -#define SDLA_502_IRQ_INTERFACE 0xFFFD -#define SDLA_502_IRQ_PERMISSION 0xFFFE -#define SDLA_502_DATA_OFS 0x0010 - -#define SDLA_508_CMD_BUF 0xE000 -#define SDLA_508_TXBUF_INFO 0xF100 -#define SDLA_508_RXBUF_INFO 0xF120 -#define SDLA_508_EVENT_FLAGS 0xF003 -#define SDLA_508_MDM_STATUS 0xF004 -#define SDLA_508_IRQ_INTERFACE 0xF010 -#define SDLA_508_IRQ_PERMISSION 0xF011 -#define SDLA_508_TSE_OFFSET 0xF012 - -/* Event flags */ -#define SDLA_EVENT_STATUS 0x01 -#define SDLA_EVENT_DLCI_STATUS 0x02 -#define SDLA_EVENT_BAD_DLCI 0x04 -#define SDLA_EVENT_LINK_DOWN 0x40 - -/* IRQ Trigger flags */ -#define SDLA_INTR_RX 0x01 -#define SDLA_INTR_TX 0x02 -#define SDLA_INTR_MODEM 0x04 -#define SDLA_INTR_COMPLETE 0x08 -#define SDLA_INTR_STATUS 0x10 -#define SDLA_INTR_TIMER 0x20 - -/* DLCI status bits */ -#define SDLA_DLCI_DELETED 0x01 -#define SDLA_DLCI_ACTIVE 0x02 -#define SDLA_DLCI_WAITING 0x04 -#define SDLA_DLCI_NEW 0x08 -#define SDLA_DLCI_INCLUDED 0x40 - -/* valid command codes */ -#define SDLA_INFORMATION_WRITE 0x01 -#define SDLA_INFORMATION_READ 0x02 -#define SDLA_ISSUE_IN_CHANNEL_SIGNAL 0x03 -#define SDLA_SET_DLCI_CONFIGURATION 0x10 -#define SDLA_READ_DLCI_CONFIGURATION 0x11 -#define SDLA_DISABLE_COMMUNICATIONS 0x12 -#define SDLA_ENABLE_COMMUNICATIONS 0x13 -#define SDLA_READ_DLC_STATUS 0x14 -#define SDLA_READ_DLC_STATISTICS 0x15 -#define SDLA_FLUSH_DLC_STATISTICS 0x16 -#define SDLA_LIST_ACTIVE_DLCI 0x17 -#define SDLA_FLUSH_INFORMATION_BUFFERS 0x18 -#define SDLA_ADD_DLCI 0x20 -#define SDLA_DELETE_DLCI 0x21 -#define SDLA_ACTIVATE_DLCI 0x22 -#define SDLA_DEACTIVATE_DLCI 0x23 -#define SDLA_READ_MODEM_STATUS 0x30 -#define SDLA_SET_MODEM_STATUS 0x31 -#define SDLA_READ_COMMS_ERR_STATS 0x32 -#define SDLA_FLUSH_COMMS_ERR_STATS 0x33 -#define SDLA_READ_CODE_VERSION 0x40 -#define SDLA_SET_IRQ_TRIGGER 0x50 -#define SDLA_GET_IRQ_TRIGGER 0x51 - -/* In channel signal types */ -#define SDLA_ICS_LINK_VERIFY 0x02 -#define SDLA_ICS_STATUS_ENQ 0x03 - -/* modem status flags */ -#define SDLA_MODEM_DTR_HIGH 0x01 -#define SDLA_MODEM_RTS_HIGH 0x02 -#define SDLA_MODEM_DCD_HIGH 0x08 -#define SDLA_MODEM_CTS_HIGH 0x20 - -/* used for RET_MODEM interpretation */ -#define SDLA_MODEM_DCD_LOW 0x01 -#define SDLA_MODEM_CTS_LOW 0x02 - -/* return codes */ -#define SDLA_RET_OK 0x00 -#define SDLA_RET_COMMUNICATIONS 0x01 -#define SDLA_RET_CHANNEL_INACTIVE 0x02 -#define SDLA_RET_DLCI_INACTIVE 0x03 -#define SDLA_RET_DLCI_CONFIG 0x04 -#define SDLA_RET_BUF_TOO_BIG 0x05 -#define SDLA_RET_NO_DATA 0x05 -#define SDLA_RET_BUF_OVERSIZE 0x06 -#define SDLA_RET_CIR_OVERFLOW 0x07 -#define SDLA_RET_NO_BUFS 0x08 -#define SDLA_RET_TIMEOUT 0x0A -#define SDLA_RET_MODEM 0x10 -#define SDLA_RET_CHANNEL_OFF 0x11 -#define SDLA_RET_CHANNEL_ON 0x12 -#define SDLA_RET_DLCI_STATUS 0x13 -#define SDLA_RET_DLCI_UNKNOWN 0x14 -#define SDLA_RET_COMMAND_INVALID 0x1F - -/* Configuration flags */ -#define SDLA_DIRECT_RECV 0x0080 -#define SDLA_TX_NO_EXCEPT 0x0020 -#define SDLA_NO_ICF_MSGS 0x1000 -#define SDLA_TX50_RX50 0x0000 -#define SDLA_TX70_RX30 0x2000 -#define SDLA_TX30_RX70 0x4000 - -/* IRQ selection flags */ -#define SDLA_IRQ_RECEIVE 0x01 -#define SDLA_IRQ_TRANSMIT 0x02 -#define SDLA_IRQ_MODEM_STAT 0x04 -#define SDLA_IRQ_COMMAND 0x08 -#define SDLA_IRQ_CHANNEL 0x10 -#define SDLA_IRQ_TIMER 0x20 - -/* definitions for PC memory mapping */ -#define SDLA_8K_WINDOW 0x01 -#define SDLA_S502_SEG_A 0x10 -#define SDLA_S502_SEG_C 0x20 -#define SDLA_S502_SEG_D 0x00 -#define SDLA_S502_SEG_E 0x30 -#define SDLA_S507_SEG_A 0x00 -#define SDLA_S507_SEG_B 0x40 -#define SDLA_S507_SEG_C 0x80 -#define SDLA_S507_SEG_E 0xC0 -#define SDLA_S508_SEG_A 0x00 -#define SDLA_S508_SEG_C 0x10 -#define SDLA_S508_SEG_D 0x08 -#define SDLA_S508_SEG_E 0x18 - -/* SDLA adapter port constants */ -#define SDLA_IO_EXTENTS 0x04 - -#define SDLA_REG_CONTROL 0x00 -#define SDLA_REG_PC_WINDOW 0x01 /* offset for PC window select latch */ -#define SDLA_REG_Z80_WINDOW 0x02 /* offset for Z80 window select latch */ -#define SDLA_REG_Z80_CONTROL 0x03 /* offset for Z80 control latch */ - -#define SDLA_S502_STS 0x00 /* status reg for 502, 502E, 507 */ -#define SDLA_S508_GNRL 0x00 /* general purp. reg for 508 */ -#define SDLA_S508_STS 0x01 /* status reg for 508 */ -#define SDLA_S508_IDR 0x02 /* ID reg for 508 */ - -/* control register flags */ -#define SDLA_S502A_START 0x00 /* start the CPU */ -#define SDLA_S502A_INTREQ 0x02 -#define SDLA_S502A_INTEN 0x04 -#define SDLA_S502A_HALT 0x08 /* halt the CPU */ -#define SDLA_S502A_NMI 0x10 /* issue an NMI to the CPU */ - -#define SDLA_S502E_CPUEN 0x01 -#define SDLA_S502E_ENABLE 0x02 -#define SDLA_S502E_INTACK 0x04 - -#define SDLA_S507_ENABLE 0x01 -#define SDLA_S507_IRQ3 0x00 -#define SDLA_S507_IRQ4 0x20 -#define SDLA_S507_IRQ5 0x40 -#define SDLA_S507_IRQ7 0x60 -#define SDLA_S507_IRQ10 0x80 -#define SDLA_S507_IRQ11 0xA0 -#define SDLA_S507_IRQ12 0xC0 -#define SDLA_S507_IRQ15 0xE0 - -#define SDLA_HALT 0x00 -#define SDLA_CPUEN 0x02 -#define SDLA_MEMEN 0x04 -#define SDLA_S507_EPROMWR 0x08 -#define SDLA_S507_EPROMCLK 0x10 -#define SDLA_S508_INTRQ 0x08 -#define SDLA_S508_INTEN 0x10 - -struct sdla_cmd { - char opp_flag; - char cmd; - short length; - char retval; - short dlci; - char flags; - short rxlost_int; - long rxlost_app; - char reserve[2]; - char data[SDLA_MAX_DATA]; /* transfer data buffer */ -} __attribute__((packed)); - -struct intr_info { - char flags; - short txlen; - char irq; - char flags2; - short timeout; -} __attribute__((packed)); - -/* found in the 508's control window at RXBUF_INFO */ -struct buf_info { - unsigned short rse_num; - unsigned long rse_base; - unsigned long rse_next; - unsigned long buf_base; - unsigned short reserved; - unsigned long buf_top; -} __attribute__((packed)); - -/* structure pointed to by rse_base in RXBUF_INFO struct */ -struct buf_entry { - char opp_flag; - short length; - short dlci; - char flags; - short timestamp; - short reserved[2]; - long buf_addr; -} __attribute__((packed)); - -#endif diff --git a/include/uapi/linux/if_frad.h b/include/uapi/linux/if_frad.h deleted file mode 100644 index 3c6ee85f6262..000000000000 --- a/include/uapi/linux/if_frad.h +++ /dev/null @@ -1,123 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */ -/* - * DLCI/FRAD Definitions for Frame Relay Access Devices. DLCI devices are - * created for each DLCI associated with a FRAD. The FRAD driver - * is not truly a network device, but the lower level device - * handler. This allows other FRAD manufacturers to use the DLCI - * code, including its RFC1490 encapsulation alongside the current - * implementation for the Sangoma cards. - * - * Version: @(#)if_ifrad.h 0.15 31 Mar 96 - * - * Author: Mike McLagan - * - * Changes: - * 0.15 Mike McLagan changed structure defs (packed) - * re-arranged flags - * added DLCI_RET vars - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - */ - -#ifndef _UAPI_FRAD_H_ -#define _UAPI_FRAD_H_ - -#include - -/* Structures and constants associated with the DLCI device driver */ - -struct dlci_add -{ - char devname[IFNAMSIZ]; - short dlci; -}; - -#define DLCI_GET_CONF (SIOCDEVPRIVATE + 2) -#define DLCI_SET_CONF (SIOCDEVPRIVATE + 3) - -/* - * These are related to the Sangoma SDLA and should remain in order. - * Code within the SDLA module is based on the specifics of this - * structure. Change at your own peril. - */ -struct dlci_conf { - short flags; - short CIR_fwd; - short Bc_fwd; - short Be_fwd; - short CIR_bwd; - short Bc_bwd; - short Be_bwd; - -/* these are part of the status read */ - short Tc_fwd; - short Tc_bwd; - short Tf_max; - short Tb_max; - -/* add any new fields here above is a mirror of sdla_dlci_conf */ -}; - -#define DLCI_GET_SLAVE (SIOCDEVPRIVATE + 4) - -/* configuration flags for DLCI */ -#define DLCI_IGNORE_CIR_OUT 0x0001 -#define DLCI_ACCOUNT_CIR_IN 0x0002 -#define DLCI_BUFFER_IF 0x0008 - -#define DLCI_VALID_FLAGS 0x000B - -/* defines for the actual Frame Relay hardware */ -#define FRAD_GET_CONF (SIOCDEVPRIVATE) -#define FRAD_SET_CONF (SIOCDEVPRIVATE + 1) - -#define FRAD_LAST_IOCTL FRAD_SET_CONF - -/* - * Based on the setup for the Sangoma SDLA. If changes are - * necessary to this structure, a routine will need to be - * added to that module to copy fields. - */ -struct frad_conf -{ - short station; - short flags; - short kbaud; - short clocking; - short mtu; - short T391; - short T392; - short N391; - short N392; - short N393; - short CIR_fwd; - short Bc_fwd; - short Be_fwd; - short CIR_bwd; - short Bc_bwd; - short Be_bwd; - -/* Add new fields here, above is a mirror of the sdla_conf */ - -}; - -#define FRAD_STATION_CPE 0x0000 -#define FRAD_STATION_NODE 0x0001 - -#define FRAD_TX_IGNORE_CIR 0x0001 -#define FRAD_RX_ACCOUNT_CIR 0x0002 -#define FRAD_DROP_ABORTED 0x0004 -#define FRAD_BUFFERIF 0x0008 -#define FRAD_STATS 0x0010 -#define FRAD_MCI 0x0100 -#define FRAD_AUTODLCI 0x8000 -#define FRAD_VALID_FLAGS 0x811F - -#define FRAD_CLOCK_INT 0x0001 -#define FRAD_CLOCK_EXT 0x0000 - - -#endif /* _UAPI_FRAD_H_ */ diff --git a/include/uapi/linux/sdla.h b/include/uapi/linux/sdla.h deleted file mode 100644 index 1e3735be6511..000000000000 --- a/include/uapi/linux/sdla.h +++ /dev/null @@ -1,117 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */ -/* - * INET An implementation of the TCP/IP protocol suite for the LINUX - * operating system. INET is implemented using the BSD Socket - * interface as the means of communication with the user level. - * - * Global definitions for the Frame relay interface. - * - * Version: @(#)if_ifrad.h 0.20 13 Apr 96 - * - * Author: Mike McLagan - * - * Changes: - * 0.15 Mike McLagan Structure packing - * - * 0.20 Mike McLagan New flags for S508 buffer handling - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - */ - -#ifndef _UAPISDLA_H -#define _UAPISDLA_H - -/* adapter type */ -#define SDLA_TYPES -#define SDLA_S502A 5020 -#define SDLA_S502E 5021 -#define SDLA_S503 5030 -#define SDLA_S507 5070 -#define SDLA_S508 5080 -#define SDLA_S509 5090 -#define SDLA_UNKNOWN -1 - -/* port selection flags for the S508 */ -#define SDLA_S508_PORT_V35 0x00 -#define SDLA_S508_PORT_RS232 0x02 - -/* Z80 CPU speeds */ -#define SDLA_CPU_3M 0x00 -#define SDLA_CPU_5M 0x01 -#define SDLA_CPU_7M 0x02 -#define SDLA_CPU_8M 0x03 -#define SDLA_CPU_10M 0x04 -#define SDLA_CPU_16M 0x05 -#define SDLA_CPU_12M 0x06 - -/* some private IOCTLs */ -#define SDLA_IDENTIFY (FRAD_LAST_IOCTL + 1) -#define SDLA_CPUSPEED (FRAD_LAST_IOCTL + 2) -#define SDLA_PROTOCOL (FRAD_LAST_IOCTL + 3) - -#define SDLA_CLEARMEM (FRAD_LAST_IOCTL + 4) -#define SDLA_WRITEMEM (FRAD_LAST_IOCTL + 5) -#define SDLA_READMEM (FRAD_LAST_IOCTL + 6) - -struct sdla_mem { - int addr; - int len; - void __user *data; -}; - -#define SDLA_START (FRAD_LAST_IOCTL + 7) -#define SDLA_STOP (FRAD_LAST_IOCTL + 8) - -/* some offsets in the Z80's memory space */ -#define SDLA_NMIADDR 0x0000 -#define SDLA_CONF_ADDR 0x0010 -#define SDLA_S502A_NMIADDR 0x0066 -#define SDLA_CODE_BASEADDR 0x0100 -#define SDLA_WINDOW_SIZE 0x2000 -#define SDLA_ADDR_MASK 0x1FFF - -/* largest handleable block of data */ -#define SDLA_MAX_DATA 4080 -#define SDLA_MAX_MTU 4072 /* MAX_DATA - sizeof(fradhdr) */ -#define SDLA_MAX_DLCI 24 - -/* this should be the same as frad_conf */ -struct sdla_conf { - short station; - short config; - short kbaud; - short clocking; - short max_frm; - short T391; - short T392; - short N391; - short N392; - short N393; - short CIR_fwd; - short Bc_fwd; - short Be_fwd; - short CIR_bwd; - short Bc_bwd; - short Be_bwd; -}; - -/* this should be the same as dlci_conf */ -struct sdla_dlci_conf { - short config; - short CIR_fwd; - short Bc_fwd; - short Be_fwd; - short CIR_bwd; - short Bc_bwd; - short Be_bwd; - short Tc_fwd; - short Tc_bwd; - short Tf_max; - short Tb_max; -}; - - -#endif /* _UAPISDLA_H */ diff --git a/net/socket.c b/net/socket.c index 6e6cccc2104f..152b1dcf93c6 100644 --- a/net/socket.c +++ b/net/socket.c @@ -64,7 +64,6 @@ #include #include #include -#include #include #include #include @@ -1027,17 +1026,6 @@ void vlan_ioctl_set(int (*hook) (struct net *, void __user *)) } EXPORT_SYMBOL(vlan_ioctl_set); -static DEFINE_MUTEX(dlci_ioctl_mutex); -static int (*dlci_ioctl_hook) (unsigned int, void __user *); - -void dlci_ioctl_set(int (*hook) (unsigned int, void __user *)) -{ - mutex_lock(&dlci_ioctl_mutex); - dlci_ioctl_hook = hook; - mutex_unlock(&dlci_ioctl_mutex); -} -EXPORT_SYMBOL(dlci_ioctl_set); - static long sock_do_ioctl(struct net *net, struct socket *sock, unsigned int cmd, unsigned long arg) { @@ -1156,17 +1144,6 @@ static long sock_ioctl(struct file *file, unsigned cmd, unsigned long arg) err = vlan_ioctl_hook(net, argp); mutex_unlock(&vlan_ioctl_mutex); break; - case SIOCADDDLCI: - case SIOCDELDLCI: - err = -ENOPKG; - if (!dlci_ioctl_hook) - request_module("dlci"); - - mutex_lock(&dlci_ioctl_mutex); - if (dlci_ioctl_hook) - err = dlci_ioctl_hook(cmd, argp); - mutex_unlock(&dlci_ioctl_mutex); - break; case SIOCGSKNS: err = -EPERM; if (!ns_capable(net->user_ns, CAP_NET_ADMIN)) @@ -3427,8 +3404,6 @@ static int compat_sock_ioctl_trans(struct file *file, struct socket *sock, case SIOCBRDELBR: case SIOCGIFVLAN: case SIOCSIFVLAN: - case SIOCADDDLCI: - case SIOCDELDLCI: case SIOCGSKNS: case SIOCGSTAMP_NEW: case SIOCGSTAMPNS_NEW: -- cgit v1.2.3-59-g8ed1b From feedaacdadfc332e1a6e436f3adfbc67e244db47 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Mon, 9 Nov 2020 18:00:06 -0800 Subject: Input: atmel_mxt_ts - fix up inverted RESET handler This driver uses GPIO descriptors to drive the touchscreen RESET line. In the existing device trees this has in conflict with intution been flagged as GPIO_ACTIVE_HIGH and the driver then applies the reverse action by driving the line low (setting to 0) to enter reset state and driving the line high (setting to 1) to get out of reset state. The correct way to handle active low GPIO lines is to provide the GPIO_ACTIVE_LOW in the device tree (thus properly describing the hardware) and letting the GPIO framework invert the assertion (driving high) to a low level and vice versa. This is considered a bug since the device trees are incorrectly mis-specifying the line as active high. Fix the driver and all device trees specifying a reset line. Signed-off-by: Linus Walleij Reviewed-by: Philippe Schenker Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20201104153032.1387747-1-linus.walleij@linaro.org Signed-off-by: Dmitry Torokhov --- arch/arm/boot/dts/imx53-ppd.dts | 2 +- arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts | 2 +- arch/arm/boot/dts/imx6q-apalis-eval.dts | 2 +- arch/arm/boot/dts/imx6q-apalis-ixora-v1.1.dts | 2 +- arch/arm/boot/dts/imx6q-apalis-ixora.dts | 2 +- arch/arm/boot/dts/imx7-colibri-aster.dtsi | 2 +- arch/arm/boot/dts/imx7-colibri-eval-v3.dtsi | 2 +- arch/arm/boot/dts/motorola-mapphone-common.dtsi | 2 +- arch/arm/boot/dts/s5pv210-aries.dtsi | 2 +- arch/arm/boot/dts/tegra20-acer-a500-picasso.dts | 2 +- drivers/input/touchscreen/atmel_mxt_ts.c | 6 ++++-- 11 files changed, 14 insertions(+), 12 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx53-ppd.dts b/arch/arm/boot/dts/imx53-ppd.dts index f7dcdf96e5c0..8f4a63ea912e 100644 --- a/arch/arm/boot/dts/imx53-ppd.dts +++ b/arch/arm/boot/dts/imx53-ppd.dts @@ -589,7 +589,7 @@ touchscreen@4b { compatible = "atmel,maxtouch"; - reset-gpio = <&gpio5 19 GPIO_ACTIVE_HIGH>; + reset-gpio = <&gpio5 19 GPIO_ACTIVE_LOW>; reg = <0x4b>; interrupt-parent = <&gpio5>; interrupts = <4 IRQ_TYPE_LEVEL_LOW>; diff --git a/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts b/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts index 65359aece950..7da74e6f46d9 100644 --- a/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts +++ b/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts @@ -143,7 +143,7 @@ reg = <0x4a>; interrupt-parent = <&gpio1>; interrupts = <9 IRQ_TYPE_EDGE_FALLING>; /* SODIMM 28 */ - reset-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>; /* SODIMM 30 */ + reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>; /* SODIMM 30 */ status = "disabled"; }; diff --git a/arch/arm/boot/dts/imx6q-apalis-eval.dts b/arch/arm/boot/dts/imx6q-apalis-eval.dts index fab83abb6466..a0683b4aeca1 100644 --- a/arch/arm/boot/dts/imx6q-apalis-eval.dts +++ b/arch/arm/boot/dts/imx6q-apalis-eval.dts @@ -140,7 +140,7 @@ reg = <0x4a>; interrupt-parent = <&gpio6>; interrupts = <10 IRQ_TYPE_EDGE_FALLING>; - reset-gpios = <&gpio6 9 GPIO_ACTIVE_HIGH>; /* SODIMM 13 */ + reset-gpios = <&gpio6 9 GPIO_ACTIVE_LOW>; /* SODIMM 13 */ status = "disabled"; }; diff --git a/arch/arm/boot/dts/imx6q-apalis-ixora-v1.1.dts b/arch/arm/boot/dts/imx6q-apalis-ixora-v1.1.dts index 1614b1ae501d..86e84781cf5d 100644 --- a/arch/arm/boot/dts/imx6q-apalis-ixora-v1.1.dts +++ b/arch/arm/boot/dts/imx6q-apalis-ixora-v1.1.dts @@ -145,7 +145,7 @@ reg = <0x4a>; interrupt-parent = <&gpio6>; interrupts = <10 IRQ_TYPE_EDGE_FALLING>; - reset-gpios = <&gpio6 9 GPIO_ACTIVE_HIGH>; /* SODIMM 13 */ + reset-gpios = <&gpio6 9 GPIO_ACTIVE_LOW>; /* SODIMM 13 */ status = "disabled"; }; diff --git a/arch/arm/boot/dts/imx6q-apalis-ixora.dts b/arch/arm/boot/dts/imx6q-apalis-ixora.dts index fa9f98dd15ac..62e72773e53b 100644 --- a/arch/arm/boot/dts/imx6q-apalis-ixora.dts +++ b/arch/arm/boot/dts/imx6q-apalis-ixora.dts @@ -144,7 +144,7 @@ reg = <0x4a>; interrupt-parent = <&gpio6>; interrupts = <10 IRQ_TYPE_EDGE_FALLING>; - reset-gpios = <&gpio6 9 GPIO_ACTIVE_HIGH>; /* SODIMM 13 */ + reset-gpios = <&gpio6 9 GPIO_ACTIVE_LOW>; /* SODIMM 13 */ status = "disabled"; }; diff --git a/arch/arm/boot/dts/imx7-colibri-aster.dtsi b/arch/arm/boot/dts/imx7-colibri-aster.dtsi index 9fa701bec2ec..139188eb9f40 100644 --- a/arch/arm/boot/dts/imx7-colibri-aster.dtsi +++ b/arch/arm/boot/dts/imx7-colibri-aster.dtsi @@ -99,7 +99,7 @@ reg = <0x4a>; interrupt-parent = <&gpio2>; interrupts = <15 IRQ_TYPE_EDGE_FALLING>; /* SODIMM 107 */ - reset-gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>; /* SODIMM 106 */ + reset-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>; /* SODIMM 106 */ }; /* M41T0M6 real time clock on carrier board */ diff --git a/arch/arm/boot/dts/imx7-colibri-eval-v3.dtsi b/arch/arm/boot/dts/imx7-colibri-eval-v3.dtsi index 97601375f264..3caf450735d7 100644 --- a/arch/arm/boot/dts/imx7-colibri-eval-v3.dtsi +++ b/arch/arm/boot/dts/imx7-colibri-eval-v3.dtsi @@ -124,7 +124,7 @@ reg = <0x4a>; interrupt-parent = <&gpio1>; interrupts = <9 IRQ_TYPE_EDGE_FALLING>; /* SODIMM 28 */ - reset-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; /* SODIMM 30 */ + reset-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; /* SODIMM 30 */ status = "disabled"; }; diff --git a/arch/arm/boot/dts/motorola-mapphone-common.dtsi b/arch/arm/boot/dts/motorola-mapphone-common.dtsi index 1990239cc6af..70fc71cbb945 100644 --- a/arch/arm/boot/dts/motorola-mapphone-common.dtsi +++ b/arch/arm/boot/dts/motorola-mapphone-common.dtsi @@ -428,7 +428,7 @@ pinctrl-names = "default"; pinctrl-0 = <&touchscreen_pins>; - reset-gpios = <&gpio6 13 GPIO_ACTIVE_HIGH>; /* gpio173 */ + reset-gpios = <&gpio6 13 GPIO_ACTIVE_LOW>; /* gpio173 */ /* gpio_183 with sys_nirq2 pad as wakeup */ interrupts-extended = <&gpio6 23 IRQ_TYPE_LEVEL_LOW>, diff --git a/arch/arm/boot/dts/s5pv210-aries.dtsi b/arch/arm/boot/dts/s5pv210-aries.dtsi index 822207f63ee0..96e8c2287d61 100644 --- a/arch/arm/boot/dts/s5pv210-aries.dtsi +++ b/arch/arm/boot/dts/s5pv210-aries.dtsi @@ -620,7 +620,7 @@ interrupts = <5 IRQ_TYPE_EDGE_FALLING>; pinctrl-names = "default"; pinctrl-0 = <&ts_irq>; - reset-gpios = <&gpj1 3 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpj1 3 GPIO_ACTIVE_LOW>; }; }; diff --git a/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts b/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts index 2d683c9a1a5d..a150e3419c8f 100644 --- a/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts +++ b/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts @@ -436,7 +436,7 @@ interrupt-parent = <&gpio>; interrupts = ; - reset-gpios = <&gpio TEGRA_GPIO(Q, 7) GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio TEGRA_GPIO(Q, 7) GPIO_ACTIVE_LOW>; avdd-supply = <&vdd_3v3_sys>; vdd-supply = <&vdd_3v3_sys>; diff --git a/drivers/input/touchscreen/atmel_mxt_ts.c b/drivers/input/touchscreen/atmel_mxt_ts.c index 98f17fa3a892..ef7915400c9f 100644 --- a/drivers/input/touchscreen/atmel_mxt_ts.c +++ b/drivers/input/touchscreen/atmel_mxt_ts.c @@ -3134,8 +3134,9 @@ static int mxt_probe(struct i2c_client *client, const struct i2c_device_id *id) if (error) return error; + /* Request the RESET line as asserted so we go into reset */ data->reset_gpio = devm_gpiod_get_optional(&client->dev, - "reset", GPIOD_OUT_LOW); + "reset", GPIOD_OUT_HIGH); if (IS_ERR(data->reset_gpio)) { error = PTR_ERR(data->reset_gpio); dev_err(&client->dev, "Failed to get reset gpio: %d\n", error); @@ -3153,8 +3154,9 @@ static int mxt_probe(struct i2c_client *client, const struct i2c_device_id *id) disable_irq(client->irq); if (data->reset_gpio) { + /* Wait a while and then de-assert the RESET GPIO line */ msleep(MXT_RESET_GPIO_TIME); - gpiod_set_value(data->reset_gpio, 1); + gpiod_set_value(data->reset_gpio, 0); msleep(MXT_RESET_INVALID_CHG); } -- cgit v1.2.3-59-g8ed1b From 16fee29b07358293f135759d9fdbf1267da57ebd Mon Sep 17 00:00:00 2001 From: Christoph Hellwig Date: Fri, 6 Nov 2020 17:02:17 +0100 Subject: dma-mapping: remove the dma_direct_set_offset export Drop the dma_direct_set_offset export and move the declaration to dma-map-ops.h now that the Allwinner drivers have stopped calling it. Signed-off-by: Christoph Hellwig Signed-off-by: Maxime Ripard --- arch/arm/mach-keystone/keystone.c | 2 +- arch/arm/mach-omap1/usb.c | 2 +- arch/sh/drivers/pci/pcie-sh7786.c | 2 +- arch/x86/pci/sta2x11-fixup.c | 3 ++- include/linux/dma-map-ops.h | 3 +++ include/linux/dma-mapping.h | 7 ------- kernel/dma/direct.c | 1 - 7 files changed, 8 insertions(+), 12 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-keystone/keystone.c b/arch/arm/mach-keystone/keystone.c index 09a65c2dfd73..cd711bfc591f 100644 --- a/arch/arm/mach-keystone/keystone.c +++ b/arch/arm/mach-keystone/keystone.c @@ -8,7 +8,7 @@ */ #include #include -#include +#include #include #include #include diff --git a/arch/arm/mach-omap1/usb.c b/arch/arm/mach-omap1/usb.c index ba8566204ea9..86d3b3c157af 100644 --- a/arch/arm/mach-omap1/usb.c +++ b/arch/arm/mach-omap1/usb.c @@ -9,7 +9,7 @@ #include #include #include -#include +#include #include #include diff --git a/arch/sh/drivers/pci/pcie-sh7786.c b/arch/sh/drivers/pci/pcie-sh7786.c index 4468289ab2ca..4d499476c33a 100644 --- a/arch/sh/drivers/pci/pcie-sh7786.c +++ b/arch/sh/drivers/pci/pcie-sh7786.c @@ -12,7 +12,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/arch/x86/pci/sta2x11-fixup.c b/arch/x86/pci/sta2x11-fixup.c index 5701d5ba3df4..7d2525691854 100644 --- a/arch/x86/pci/sta2x11-fixup.c +++ b/arch/x86/pci/sta2x11-fixup.c @@ -11,7 +11,8 @@ #include #include #include -#include +#include +#include #include #define STA2X11_SWIOTLB_SIZE (4*1024*1024) diff --git a/include/linux/dma-map-ops.h b/include/linux/dma-map-ops.h index a5f89fc4d6df..03925e438ec3 100644 --- a/include/linux/dma-map-ops.h +++ b/include/linux/dma-map-ops.h @@ -226,6 +226,9 @@ struct page *dma_alloc_from_pool(struct device *dev, size_t size, bool (*phys_addr_ok)(struct device *, phys_addr_t, size_t)); bool dma_free_from_pool(struct device *dev, void *start, size_t size); +int dma_direct_set_offset(struct device *dev, phys_addr_t cpu_start, + dma_addr_t dma_start, u64 size); + #ifdef CONFIG_ARCH_HAS_DMA_COHERENCE_H #include #elif defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE) || \ diff --git a/include/linux/dma-mapping.h b/include/linux/dma-mapping.h index 956151052d45..199d85285246 100644 --- a/include/linux/dma-mapping.h +++ b/include/linux/dma-mapping.h @@ -558,13 +558,6 @@ static inline int dma_mmap_wc(struct device *dev, #define dma_unmap_len_set(PTR, LEN_NAME, VAL) do { } while (0) #endif -/* - * Legacy interface to set up the dma offset map. Drivers really should not - * actually use it, but we have a few legacy cases left. - */ -int dma_direct_set_offset(struct device *dev, phys_addr_t cpu_start, - dma_addr_t dma_start, u64 size); - extern const struct dma_map_ops dma_virt_ops; #endif /* _LINUX_DMA_MAPPING_H */ diff --git a/kernel/dma/direct.c b/kernel/dma/direct.c index 06c111544f61..002268262c9a 100644 --- a/kernel/dma/direct.c +++ b/kernel/dma/direct.c @@ -547,4 +547,3 @@ int dma_direct_set_offset(struct device *dev, phys_addr_t cpu_start, dev->dma_range_map = map; return 0; } -EXPORT_SYMBOL_GPL(dma_direct_set_offset); -- cgit v1.2.3-59-g8ed1b From cbee028da69d31cb927142e2828710de55a49f2a Mon Sep 17 00:00:00 2001 From: Andrew Jeffery Date: Thu, 22 Oct 2020 12:17:26 +1030 Subject: ARM: dts: tacoma: Fix node vs reg mismatch for flash memory The mismatch lead to a miscalculation of regions in another patch, and shouldn't be mismatched anyway, so make them consistent. Fixes: 575640201e66 ("ARM: dts: aspeed: tacoma: Use 64MB for firmware memory") Signed-off-by: Andrew Jeffery Reviewed-by: Joel Stanley Link: https://lore.kernel.org/r/20201022014731.2035438-2-andrew@aj.id.au Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts b/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts index 4d070d6ba09f..e86c22ce6d12 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts @@ -26,7 +26,7 @@ #size-cells = <1>; ranges; - flash_memory: region@ba000000 { + flash_memory: region@b8000000 { no-map; reg = <0xb8000000 0x4000000>; /* 64M */ }; -- cgit v1.2.3-59-g8ed1b From c7b74131c755bb73eb836bcb46fcc28fbab39717 Mon Sep 17 00:00:00 2001 From: Andrew Jeffery Date: Thu, 22 Oct 2020 12:17:30 +1030 Subject: ARM: dts: rainier: Add reserved memory for ramoops Reserve a 1.5MiB region of memory to record kmsg dumps, console and userspace message state into 16kiB ring-buffer slots. The sizing allows for up to 16 dumps to be captured and read out. Set max-reason to KMSG_DUMP_EMERG to capture bad-path reboots. Signed-off-by: Andrew Jeffery Reviewed-by: Joel Stanley Link: https://lore.kernel.org/r/20201022014731.2035438-6-andrew@aj.id.au Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts b/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts index ac649fde802e..63123bf137e3 100644 --- a/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts +++ b/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts @@ -52,6 +52,15 @@ reg = <0xB8000000 0x04000000>; /* 64M */ }; + ramoops@bc000000 { + compatible = "ramoops"; + reg = <0xbc000000 0x180000>; /* 16 * (3 * 0x8000) */ + record-size = <0x8000>; + console-size = <0x8000>; + pmsg-size = <0x8000>; + max-reason = <3>; /* KMSG_DUMP_EMERG */ + }; + vga_memory: region@bf000000 { no-map; compatible = "shared-dma-pool"; -- cgit v1.2.3-59-g8ed1b From c1fc133f5bd06949037192c0a48c3dab85a140fd Mon Sep 17 00:00:00 2001 From: Andrew Jeffery Date: Thu, 22 Oct 2020 12:17:31 +1030 Subject: ARM: dts: tacoma: Add reserved memory for ramoops Reserve a 1.5MiB region of memory to record kmsg dumps, console and userspace message state into 16kiB ring-buffer slots. The sizing allows for up to 16 dumps to be captured and read out. Set max-reason to KMSG_DUMP_EMERG to capture bad-path reboots. Signed-off-by: Andrew Jeffery Reviewed-by: Joel Stanley Link: https://lore.kernel.org/r/20201022014731.2035438-7-andrew@aj.id.au Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts b/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts index e86c22ce6d12..c1478d2db602 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts @@ -31,6 +31,15 @@ reg = <0xb8000000 0x4000000>; /* 64M */ }; + ramoops@bc000000 { + compatible = "ramoops"; + reg = <0xbc000000 0x180000>; /* 16 * (3 * 0x8000) */ + record-size = <0x8000>; + console-size = <0x8000>; + pmsg-size = <0x8000>; + max-reason = <3>; /* KMSG_DUMP_EMERG */ + }; + vga_memory: region@bf000000 { no-map; compatible = "shared-dma-pool"; -- cgit v1.2.3-59-g8ed1b From 136b2124d7cbc03a3b8fb88336f6bc1ba75b412f Mon Sep 17 00:00:00 2001 From: Tomer Maimon Date: Wed, 18 Nov 2020 12:03:58 +0200 Subject: ARM: dts: nuvoton: Add Nuvoton NPCM730 device tree The Nuvoton NPCN730 SoC is a part of the Nuvoton NPCM7xx SoCs family. Signed-off-by: Tomer Maimon Signed-off-by: Joel Stanley --- arch/arm/boot/dts/nuvoton-npcm730.dtsi | 44 ++++++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) create mode 100644 arch/arm/boot/dts/nuvoton-npcm730.dtsi (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/nuvoton-npcm730.dtsi b/arch/arm/boot/dts/nuvoton-npcm730.dtsi new file mode 100644 index 000000000000..86ec12ec2b50 --- /dev/null +++ b/arch/arm/boot/dts/nuvoton-npcm730.dtsi @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2020 Nuvoton Technology + +#include "nuvoton-common-npcm7xx.dtsi" + +/ { + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&gic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + enable-method = "nuvoton,npcm750-smp"; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + clocks = <&clk NPCM7XX_CLK_CPU>; + clock-names = "clk_cpu"; + reg = <0>; + next-level-cache = <&l2>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + clocks = <&clk NPCM7XX_CLK_CPU>; + clock-names = "clk_cpu"; + reg = <1>; + next-level-cache = <&l2>; + }; + }; + + soc { + timer@3fe600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0x3fe600 0x20>; + interrupts = ; + clocks = <&clk NPCM7XX_CLK_AHB>; + }; + }; +}; -- cgit v1.2.3-59-g8ed1b From c2a983a7a8861e4d6bfd923ea84c919fd9d5261c Mon Sep 17 00:00:00 2001 From: Fran Hsu Date: Fri, 31 May 2019 21:24:38 +0800 Subject: ARM: dts: nuvoton: Add Quanta GSJ BMC pinctrl Add pinctrl definition for the Quanta GSJ BMC machine. Signed-off-by: Fran Hsu Reviewed-by: Benjamin Fair Signed-off-by: Joel Stanley --- arch/arm/boot/dts/nuvoton-npcm730-gsj-gpio.dtsi | 477 ++++++++++++++++++++++++ 1 file changed, 477 insertions(+) create mode 100644 arch/arm/boot/dts/nuvoton-npcm730-gsj-gpio.dtsi (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/nuvoton-npcm730-gsj-gpio.dtsi b/arch/arm/boot/dts/nuvoton-npcm730-gsj-gpio.dtsi new file mode 100644 index 000000000000..53cfd15fa03f --- /dev/null +++ b/arch/arm/boot/dts/nuvoton-npcm730-gsj-gpio.dtsi @@ -0,0 +1,477 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2018 Nuvoton Technology tomer.maimon@nuvoton.com + +/ { + pinctrl: pinctrl@f0800000 { + gpio0pp_pins: gpio0pp-pins { + pins = "GPIO0/IOX1DI"; + bias-disable; + drive-push-pull; + }; + gpio1pp_pins: gpio1pp-pins { + pins = "GPIO1/IOX1LD"; + bias-disable; + drive-push-pull; + }; + gpio2pp_pins: gpio2pp-pins { + pins = "GPIO2/IOX1CK"; + bias-disable; + drive-push-pull; + }; + gpio3pp_pins: gpio3pp-pins { + pins = "GPIO3/IOX1D0"; + bias-disable; + drive-push-pull; + }; + gpio4pp_pins: gpio4pp-pins { + pins = "GPIO4/IOX2DI/SMB1DSDA"; + bias-disable; + drive-push-pull; + }; + gpio5pp_pins: gpio5pp-pins { + pins = "GPIO5/IOX2LD/SMB1DSCL"; + bias-disable; + drive-push-pull; + }; + gpio6pp_pins: gpio6pp-pins { + pins = "GPIO6/IOX2CK/SMB2DSDA"; + bias-disable; + drive-push-pull; + }; + gpio7pp_pins: gpio7pp-pins { + pins = "GPIO7/IOX2D0/SMB2DSCL"; + bias-disable; + drive-push-pull; + }; + gpio8_pins: gpio8-pins { + pins = "GPIO8/LKGPO1"; + bias-disable; + input-enable; + }; + gpio9_pins: gpio9-pins { + pins = "GPIO9/LKGPO2"; + bias-disable; + input-enable; + }; + gpio10pp_pins: gpio10pp-pins { + pins = "GPIO10/IOXHLD"; + bias-disable; + drive-push-pull; + }; + gpio11pp_pins: gpio11pp-pins { + pins = "GPIO11/IOXHCK"; + bias-disable; + drive-push-pull; + }; + gpio12_pins: gpio12-pins { + pins = "GPIO12/GSPICK/SMB5BSCL"; + bias-disable; + input-enable; + }; + gpio13_pins: gpio13-pins { + pins = "GPIO13/GSPIDO/SMB5BSDA"; + bias-disable; + input-enable; + }; + gpio14_pins: gpio14-pins { + pins = "GPIO14/GSPIDI/SMB5CSCL"; + bias-disable; + input-enable; + }; + gpio15od_pins: gpio15od-pins { + pins = "GPIO15/GSPICS/SMB5CSDA"; + bias-disable; + drive-open-drain; + }; + gpio17pp_pins: gpio17pp-pins { + pins = "GPIO17/PSPI2DI/SMB4DEN"; + bias-disable; + drive-push-pull; + }; + gpio18pp_pins: gpio18pp-pins { + pins = "GPIO18/PSPI2D0/SMB4BSDA"; + bias-disable; + drive-push-pull; + }; + gpio19pp_pins: gpio19pp-pins { + pins = "GPIO19/PSPI2CK/SMB4BSCL"; + bias-disable; + drive-push-pull; + }; + gpio24pp_pins: gpio24pp-pins { + pins = "GPIO24/IOXHDO"; + bias-disable; + drive-push-pull; + }; + gpio25pp_pins: gpio25pp-pins { + pins = "GPIO25/IOXHDI"; + bias-disable; + drive-push-pull; + }; + gpio37od_pins: gpio37od-pins { + pins = "GPIO37/SMB3CSDA"; + bias-disable; + drive-open-drain; + }; + gpio59pp_pins: gpio59pp-pins { + pins = "GPIO59/SMB3DSDA"; + bias-disable; + drive-push-pull; + }; + gpio60_pins: gpio60-pins { + pins = "GPIO60/SMB3DSCL"; + bias-disable; + input-enable; + }; + gpio72od_pins: gpio72od-pins { + pins = "GPIO72/FANIN8"; + bias-disable; + drive-open-drain; + }; + gpio73od_pins: gpio73od-pins { + pins = "GPIO73/FANIN9"; + bias-disable; + drive-open-drain; + }; + gpio74od_pins: gpio74od-pins { + pins = "GPIO74/FANIN10"; + bias-disable; + drive-open-drain; + }; + gpio75od_pins: gpio75od-pins { + pins = "GPIO75/FANIN11"; + bias-disable; + drive-open-drain; + }; + gpio76od_pins: gpio76od-pins { + pins = "GPIO76/FANIN12"; + bias-disable; + drive-open-drain; + }; + gpio77od_pins: gpio77od-pins { + pins = "GPIO77/FANIN13"; + bias-disable; + drive-open-drain; + }; + gpio78od_pins: gpio78od-pins { + pins = "GPIO78/FANIN14"; + bias-disable; + drive-open-drain; + }; + gpio79od_pins: gpio79od-pins { + pins = "GPIO79/FANIN15"; + bias-disable; + drive-open-drain; + }; + gpio83_pins: gpio83-pins { + pins = "GPIO83/PWM3"; + bias-disable; + input-enable; + }; + gpio84pp_pins: gpio84pp-pins { + pins = "GPIO84/R2TXD0"; + bias-disable; + drive-push-pull; + }; + gpio85pp_pins: gpio85pp-pins { + pins = "GPIO85/R2TXD1"; + bias-disable; + drive-push-pull; + }; + gpio86pp_pins: gpio86pp-pins { + pins = "GPIO86/R2TXEN"; + bias-disable; + drive-push-pull; + }; + gpio87pp_pins: gpio87pp-pins { + pins = "GPIO87/R2RXD0"; + bias-disable; + drive-push-pull; + }; + gpio88pp_pins: gpio88pp-pins { + pins = "GPIO88/R2RXD1"; + bias-disable; + drive-push-pull; + }; + gpio89pp_pins: gpio89pp-pins { + pins = "GPIO89/R2CRSDV"; + bias-disable; + drive-push-pull; + }; + gpio90pp_pins: gpio90pp-pins { + pins = "GPIO90/R2RXERR"; + bias-disable; + drive-push-pull; + }; + gpio91_pins: gpio91-pins { + pins = "GPIO91/R2MDC"; + bias-disable; + input-enable; + }; + gpio92_pins: gpio92-pins { + pins = "GPIO92/R2MDIO"; + bias-disable; + input-enable; + }; + gpio93pp_pins: gpio93pp-pins { + pins = "GPIO93/GA20/SMB5DSCL"; + bias-disable; + drive-push-pull; + }; + gpio94pp_pins: gpio94pp-pins { + pins = "GPIO94/nKBRST/SMB5DSDA"; + bias-disable; + drive-push-pull; + }; + gpio95_pins: gpio95-pins { + pins = "GPIO95/nLRESET/nESPIRST"; + bias-disable; + input-enable; + }; + gpio125pp_pins: gpio125pp-pins { + pins = "GPIO125/SMB1CSCL"; + bias-disable; + drive-push-pull; + }; + gpio126od_pins: gpio126od-pins { + pins = "GPIO126/SMB1BSDA"; + bias-disable; + drive-open-drain; + }; + gpio127od_pins: gpio127od-pins { + pins = "GPIO127/SMB1BSCL"; + bias-disable; + drive-open-drain; + }; + gpio136_pins: gpio136-pins { + pins = "GPIO136/SD1DT0"; + bias-disable; + input-enable; + }; + gpio137_pins: gpio137-pins { + pins = "GPIO137/SD1DT1"; + bias-disable; + input-enable; + }; + gpio141_pins: gpio141-pins { + pins = "GPIO141/SD1WP"; + bias-disable; + input-enable; + }; + gpio142od_pins: gpio142od-pins { + pins = "GPIO142/SD1CMD"; + bias-disable; + drive-open-drain; + }; + gpio143ol_pins: gpio143ol-pins { + pins = "GPIO143/SD1CD/SD1PWR"; + bias-disable; + output-low; + }; + gpio144_pins: gpio144-pins { + pins = "GPIO144/PWM4"; + bias-disable; + input-enable; + }; + gpio145_pins: gpio145-pins { + pins = "GPIO145/PWM5"; + bias-disable; + input-enable; + }; + gpio146_pins: gpio146-pins { + pins = "GPIO146/PWM6"; + bias-disable; + input-enable; + }; + gpio147_pins: gpio147-pins { + pins = "GPIO147/PWM7"; + bias-disable; + input-enable; + }; + gpio148_pins: gpio148-pins { + pins = "GPIO148/MMCDT4"; + bias-disable; + input-enable; + }; + gpio149_pins: gpio149-pins { + pins = "GPIO149/MMCDT5"; + bias-disable; + input-enable; + }; + gpio150_pins: gpio150-pins { + pins = "GPIO150/MMCDT6"; + bias-disable; + input-enable; + }; + gpio151_pins: gpio151-pins { + pins = "GPIO151/MMCDT7"; + bias-disable; + input-enable; + }; + gpio152_pins: gpio152-pins { + pins = "GPIO152/MMCCLK"; + bias-disable; + input-enable; + }; + gpio153_pins: gpio153-pins { + pins = "GPIO153/MMCWP"; + bias-disable; + input-enable; + }; + gpio154_pins: gpio154-pins { + pins = "GPIO154/MMCCMD"; + bias-disable; + input-enable; + }; + gpio155_pins: gpio155-pins { + pins = "GPIO155/nMMCCD/nMMCRST"; + bias-disable; + input-enable; + }; + gpio156_pins: gpio156-pins { + pins = "GPIO156/MMCDT0"; + bias-disable; + input-enable; + }; + gpio157_pins: gpio157-pins { + pins = "GPIO157/MMCDT1"; + bias-disable; + input-enable; + }; + gpio158_pins: gpio158-pins { + pins = "GPIO158/MMCDT2"; + bias-disable; + input-enable; + }; + gpio159_pins: gpio159-pins { + pins = "GPIO159/MMCDT3"; + bias-disable; + input-enable; + }; + gpio161_pins: gpio161-pins { + pins = "GPIO161/nLFRAME/nESPICS"; + bias-disable; + input-enable; + }; + gpio162_pins: gpio162-pins { + pins = "GPIO162/SERIRQ"; + bias-disable; + input-enable; + }; + gpio163_pins: gpio163-pins { + pins = "GPIO163/LCLK/ESPICLK"; + bias-disable; + input-enable; + }; + gpio164_pins: gpio164-pins { + pins = "GPIO164/LAD0/ESPI_IO0"; + bias-disable; + input-enable; + }; + gpio165_pins: gpio165-pins { + pins = "GPIO165/LAD1/ESPI_IO1"; + bias-disable; + input-enable; + }; + gpio166_pins: gpio166-pins { + pins = "GPIO166/LAD2/ESPI_IO2"; + bias-disable; + input-enable; + }; + gpio167_pins: gpio167-pins { + pins = "GPIO167/LAD3/ESPI_IO3"; + bias-disable; + input-enable; + }; + gpio168_pins: gpio168-pins { + pins = "GPIO168/nCLKRUN/nESPIALERT"; + bias-disable; + input-enable; + }; + gpio169_pins: gpio169-pins { + pins = "GPIO169/nSCIPME"; + bias-disable; + input-enable; + }; + gpio170_pins: gpio170-pins { + pins = "GPIO170/nSMI"; + bias-disable; + input-enable; + }; + gpio175od_pins: gpio175od-pins { + pins = "GPIO175/PSPI1CK/FANIN19"; + bias-disable; + drive-open-drain; + }; + gpio176od_pins: gpio176od-pins { + pins = "GPIO176/PSPI1DO/FANIN18"; + bias-disable; + drive-open-drain; + }; + gpio177_pins: gpio177-pins { + pins = "GPIO177/PSPI1DI/FANIN17"; + bias-disable; + input-enable; + }; + gpio190od_pins: gpio190od-pins { + pins = "GPIO190/nPRD_SMI"; + bias-disable; + drive-open-drain; + }; + gpio191_pins: gpio191-pins { + pins = "GPIO191"; + bias-disable; + input-enable; + }; + gpio192_pins: gpio192-pins { + pins = "GPIO192"; + bias-disable; + input-enable; + }; + gpio194pp_pins: gpio194pp-pins { + pins = "GPIO194/SMB0BSCL"; + bias-disable; + drive-push-pull; + }; + gpio195od_pins: gpio195od-pins { + pins = "GPIO195/SMB0BSDA"; + bias-disable; + drive-open-drain; + }; + gpio196od_pins: gpio196od-pins { + pins = "GPIO196/SMB0CSCL"; + bias-disable; + drive-open-drain; + }; + gpio197od_pins: gpio197od-pins { + pins = "GPIO197/SMB0DEN"; + bias-disable; + drive-open-drain; + }; + gpio198od_pins: gpio198od-pins { + pins = "GPIO198/SMB0DSDA"; + bias-disable; + drive-open-drain; + }; + gpio199od_pins: gpio199od-pins { + pins = "GPIO199/SMB0DSCL"; + bias-disable; + drive-open-drain; + }; + gpio200pp_pins: gpio200pp-pins { + pins = "GPIO200/R2CK"; + bias-disable; + drive-push-pull; + }; + gpio202od_pins: gpio202od-pins { + pins = "GPIO202/SMB0CSDA"; + bias-disable; + drive-open-drain; + }; + gpio203_pins: gpio203-pins { + pins = "GPIO203/FANIN16"; + bias-disable; + input-enable; + }; + }; +}; -- cgit v1.2.3-59-g8ed1b From 59f5abe09f0a7a20be45003706fa1b0d1a916690 Mon Sep 17 00:00:00 2001 From: Fran Hsu Date: Fri, 31 May 2019 21:24:39 +0800 Subject: ARM: dts: nuvoton: Add Quanta GSJ BMC The Quanta GSJ BMC uses the Nuvoton NPCM730 SoC. Included features: 1. Image partitions 2. PWM fan controller 3. USB device 4. Serial port 5. FIU 6. LEDs and GPIOs Signed-off-by: Fran Hsu Reviewed-by: Benjamin Fair Signed-off-by: Joel Stanley --- arch/arm/boot/dts/Makefile | 3 +- arch/arm/boot/dts/nuvoton-npcm730-gsj.dts | 490 ++++++++++++++++++++++++++++++ 2 files changed, 492 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/nuvoton-npcm730-gsj.dts (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index ce66ffd5a1bb..30bf4b007513 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -339,7 +339,8 @@ dtb-$(CONFIG_ARCH_LPC32XX) += \ lpc3250-ea3250.dtb \ lpc3250-phy3250.dtb dtb-$(CONFIG_ARCH_NPCM7XX) += \ - nuvoton-npcm750-evb.dtb + nuvoton-npcm750-evb.dtb \ + nuvoton-npcm730-gsj.dtb dtb-$(CONFIG_MACH_MESON6) += \ meson6-atv1200.dtb dtb-$(CONFIG_MACH_MESON8) += \ diff --git a/arch/arm/boot/dts/nuvoton-npcm730-gsj.dts b/arch/arm/boot/dts/nuvoton-npcm730-gsj.dts new file mode 100644 index 000000000000..d4ff49939a3d --- /dev/null +++ b/arch/arm/boot/dts/nuvoton-npcm730-gsj.dts @@ -0,0 +1,490 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2019 Quanta Computer lnc. Fran.Hsu@quantatw.com + +/dts-v1/; +#include "nuvoton-npcm730.dtsi" +#include "nuvoton-npcm730-gsj-gpio.dtsi" + +#include + +/ { + model = "Quanta GSJ Board (Device Tree v12)"; + compatible = "nuvoton,npcm750"; + + aliases { + ethernet1 = &gmac0; + serial3 = &serial3; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c8 = &i2c8; + i2c9 = &i2c9; + i2c10 = &i2c10; + i2c11 = &i2c11; + i2c12 = &i2c12; + i2c15 = &i2c15; + fiu0 = &fiu0; + }; + + chosen { + stdout-path = &serial3; + }; + + memory { + reg = <0 0x40000000>; + }; + + leds { + compatible = "gpio-leds"; + + led-bmc-live { + gpios = <&gpio4 15 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + + LED_U2_0_LOCATE { + gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + LED_U2_1_LOCATE { + gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + LED_U2_2_LOCATE { + gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + LED_U2_3_LOCATE { + gpios = <&gpio0 3 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + LED_U2_4_LOCATE { + gpios = <&gpio0 10 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + LED_U2_5_LOCATE { + gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + LED_BMC_TRAY_PWRGD { + gpios = <&gpio0 19 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + LED_U2_7_FAULT { + gpios = <&gpio6 8 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + LED_U2_6_LOCATE { + gpios = <&gpio0 24 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + LED_U2_7_LOCATE { + gpios = <&gpio0 25 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + LED_U2_0_FAULT { + gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + LED_U2_1_FAULT { + gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + LED_U2_2_FAULT { + gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + LED_U2_3_FAULT { + gpios = <&gpio2 23 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + LED_U2_4_FAULT { + gpios = <&gpio2 24 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + LED_U2_5_FAULT { + gpios = <&gpio2 25 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + LED_U2_6_FAULT { + gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; +}; + +&fiu0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0cs1_pins>; + status = "okay"; + + spi-nor@0 { + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0>; + spi-rx-bus-width = <2>; + + partitions@80000000 { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + bmc@0{ + label = "bmc"; + reg = <0x000000 0x2000000>; + }; + u-boot@0 { + label = "u-boot"; + reg = <0x0000000 0x80000>; + read-only; + }; + u-boot-env@100000{ + label = "u-boot-env"; + reg = <0x00100000 0x40000>; + }; + kernel@200000 { + label = "kernel"; + reg = <0x0200000 0x600000>; + }; + rofs@800000 { + label = "rofs"; + reg = <0x800000 0x1400000>; + }; + rwfs@1c00000 { + label = "rwfs"; + reg = <0x1c00000 0x300000>; + }; + reserved@1f00000 { + label = "reserved"; + reg = <0x1f00000 0x100000>; + }; + }; + }; +}; + +&gmac0 { + phy-mode = "rgmii-id"; + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&watchdog1 { + status = "okay"; +}; + +&rng { + status = "okay"; +}; + +&serial0 { + status = "okay"; +}; + +&serial1 { + status = "okay"; +}; + +&serial2 { + status = "okay"; +}; + +&serial3 { + status = "okay"; +}; + +&adc { + status = "okay"; +}; + +&i2c1 { + status = "okay"; + + lm75@5c { + compatible = "maxim,max31725"; + reg = <0x5c>; + status = "okay"; + }; +}; + +&i2c2 { + status = "okay"; + + lm75@5c { + compatible = "maxim,max31725"; + reg = <0x5c>; + status = "okay"; + }; +}; + +&i2c3 { + status = "okay"; + + lm75@5c { + compatible = "maxim,max31725"; + reg = <0x5c>; + }; +}; + +&i2c4 { + status = "okay"; + + lm75@5c { + compatible = "maxim,max31725"; + reg = <0x5c>; + }; +}; + +&i2c8 { + status = "okay"; +}; + +&i2c9 { + status = "okay"; + + eeprom@55 { + compatible = "atmel,24c64"; + reg = <0x55>; + }; +}; + +&i2c10 { + status = "okay"; + + eeprom@55 { + compatible = "atmel,24c64"; + reg = <0x55>; + }; +}; + +&i2c11 { + status = "okay"; + + /* P12V Quarter Brick DC/DC Power Module Q54SH12050 @60 */ + power-brick@36 { + compatible = "delta,dps800"; + reg = <0x36>; + }; + + hotswap@15 { + compatible = "ti,lm5066i"; + reg = <0x15>; + }; +}; + +&i2c12 { + status = "okay"; + + ucd90160@6b { + compatible = "ti,ucd90160"; + reg = <0x6b>; + }; +}; + +&i2c15 { + status = "okay"; + + i2c-switch@75 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x75>; + i2c-mux-idle-disconnect; + + i2c_u20: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + i2c_u21: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + i2c_u22: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + i2c_u23: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + + i2c_u24: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + + i2c_u25: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + + i2c_u26: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + + i2c_u27: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + }; +}; + +&pwm_fan { + pinctrl-names = "default"; + pinctrl-0 = <&pwm0_pins &pwm1_pins &pwm2_pins + &fanin0_pins &fanin1_pins + &fanin2_pins &fanin3_pins + &fanin4_pins &fanin5_pins>; + status = "okay"; + + fan@0 { + reg = <0x00>; + fan-tach-ch = /bits/ 8 <0x00 0x01>; + cooling-levels = <127 255>; + }; + + fan@1 { + reg = <0x01>; + fan-tach-ch = /bits/ 8 <0x02 0x03>; + cooling-levels = /bits/ 8 <127 255>; + }; + + fan@2 { + reg = <0x02>; + fan-tach-ch = /bits/ 8 <0x04 0x05>; + cooling-levels = /bits/ 8 <127 255>; + }; +}; + +&pinctrl { + pinctrl-names = "default"; + pinctrl-0 = < + /* GPI pins*/ + &gpio8_pins + &gpio9_pins + &gpio12_pins + &gpio13_pins + &gpio14_pins + &gpio60_pins + &gpio83_pins + &gpio91_pins + &gpio92_pins + &gpio95_pins + &gpio136_pins + &gpio137_pins + &gpio141_pins + &gpio144_pins + &gpio145_pins + &gpio146_pins + &gpio147_pins + &gpio148_pins + &gpio149_pins + &gpio150_pins + &gpio151_pins + &gpio152_pins + &gpio153_pins + &gpio154_pins + &gpio155_pins + &gpio156_pins + &gpio157_pins + &gpio158_pins + &gpio159_pins + &gpio161_pins + &gpio162_pins + &gpio163_pins + &gpio164_pins + &gpio165_pins + &gpio166_pins + &gpio167_pins + &gpio168_pins + &gpio169_pins + &gpio170_pins + &gpio177_pins + &gpio191_pins + &gpio192_pins + &gpio203_pins + /* GPO pins*/ + &gpio0pp_pins + &gpio1pp_pins + &gpio2pp_pins + &gpio3pp_pins + &gpio4pp_pins + &gpio5pp_pins + &gpio6pp_pins + &gpio7pp_pins + &gpio10pp_pins + &gpio11pp_pins + &gpio15od_pins + &gpio17pp_pins + &gpio18pp_pins + &gpio19pp_pins + &gpio24pp_pins + &gpio25pp_pins + &gpio37od_pins + &gpio59pp_pins + &gpio72od_pins + &gpio73od_pins + &gpio74od_pins + &gpio75od_pins + &gpio76od_pins + &gpio77od_pins + &gpio78od_pins + &gpio79od_pins + &gpio84pp_pins + &gpio85pp_pins + &gpio86pp_pins + &gpio87pp_pins + &gpio88pp_pins + &gpio89pp_pins + &gpio90pp_pins + &gpio93pp_pins + &gpio94pp_pins + &gpio125pp_pins + &gpio126od_pins + &gpio127od_pins + &gpio142od_pins + &gpio143ol_pins + &gpio175od_pins + &gpio176od_pins + &gpio190od_pins + &gpio194pp_pins + &gpio195od_pins + &gpio196od_pins + &gpio197od_pins + &gpio198od_pins + &gpio199od_pins + &gpio200pp_pins + &gpio202od_pins + >; +}; -- cgit v1.2.3-59-g8ed1b From 0e0610d24ee6e661dab5696197f2e68a9b29cd67 Mon Sep 17 00:00:00 2001 From: Tomer Maimon Date: Wed, 25 Sep 2019 15:26:38 +0300 Subject: ARM: dts: nuvoton: Add NPCM7xx RunBMC Olympus Quanta machine Add Nuvoton NPCM7xx RunBMC Olympus Quanta board device tree. Signed-off-by: Tomer Maimon Signed-off-by: Joel Stanley --- arch/arm/boot/dts/Makefile | 3 +- .../dts/nuvoton-npcm750-runbmc-olympus-pincfg.dtsi | 517 ++++++++++ .../boot/dts/nuvoton-npcm750-runbmc-olympus.dts | 1052 ++++++++++++++++++++ 3 files changed, 1571 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/nuvoton-npcm750-runbmc-olympus-pincfg.dtsi create mode 100644 arch/arm/boot/dts/nuvoton-npcm750-runbmc-olympus.dts (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 30bf4b007513..ad2eaf9ed4e4 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -339,8 +339,9 @@ dtb-$(CONFIG_ARCH_LPC32XX) += \ lpc3250-ea3250.dtb \ lpc3250-phy3250.dtb dtb-$(CONFIG_ARCH_NPCM7XX) += \ + nuvoton-npcm730-gsj.dtb \ nuvoton-npcm750-evb.dtb \ - nuvoton-npcm730-gsj.dtb + nuvoton-npcm750-runbmc-olympus.dtb dtb-$(CONFIG_MACH_MESON6) += \ meson6-atv1200.dtb dtb-$(CONFIG_MACH_MESON8) += \ diff --git a/arch/arm/boot/dts/nuvoton-npcm750-runbmc-olympus-pincfg.dtsi b/arch/arm/boot/dts/nuvoton-npcm750-runbmc-olympus-pincfg.dtsi new file mode 100644 index 000000000000..230cb344b2e1 --- /dev/null +++ b/arch/arm/boot/dts/nuvoton-npcm750-runbmc-olympus-pincfg.dtsi @@ -0,0 +1,517 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2019 Quanta Computer Inc. Samuel.Jiang@quantatw.com + +/ { + pinctrl: pinctrl@f0800000 { + gpio0ol_pins: gpio0ol-pins { + pins = "GPIO0/IOX1DI"; + bias-disable; + output-low; + }; + gpio1ol_pins: gpio1ol-pins { + pins = "GPIO1/IOX1LD"; + bias-disable; + output-low; + }; + gpio2ol_pins: gpio2ol-pins { + pins = "GPIO2/IOX1CK"; + bias-disable; + output-low; + }; + gpio3ol_pins: gpio3ol-pins { + pins = "GPIO3/IOX1D0"; + bias-disable; + output-low; + }; + gpio5_pins: gpio5-pins { + pins = "GPIO5/IOX2LD/SMB1DSCL"; + bias-disable; + input-enable; + }; + gpio6_pins: gpio6-pins { + pins = "GPIO6/IOX2CK/SMB2DSDA"; + bias-disable; + input-enable; + }; + gpio7_pins: gpio7-pins { + pins = "GPIO7/IOX2D0/SMB2DSCL"; + bias-disable; + input-enable; + }; + gpio8o_pins: gpio8o-pins { + pins = "GPIO8/LKGPO1"; + bias-disable; + output-high; + }; + gpio9ol_pins: gpio9ol-pins { + pins = "GPIO9/LKGPO2"; + bias-disable; + output-low; + }; + gpio10_pins: gpio10-pins { + pins = "GPIO10/IOXHLD"; + bias-disable; + input-enable; + }; + gpio11_pins: gpio11-pins { + pins = "GPIO11/IOXHCK"; + bias-disable; + input-enable; + }; + gpio12ol_pins: gpio12ol-pins { + pins = "GPIO12/GSPICK/SMB5BSCL"; + bias-disable; + output-low; + }; + gpio13ol_pins: gpio13ol-pins { + pins = "GPIO13/GSPIDO/SMB5BSDA"; + bias-disable; + output-low; + }; + gpio14ol_pins: gpio14ol-pins { + pins = "GPIO14/GSPIDI/SMB5CSCL"; + bias-disable; + output-low; + }; + gpio15ol_pins: gpio15ol-pins { + pins = "GPIO15/GSPICS/SMB5CSDA"; + bias-disable; + output-low; + }; + gpio20_pins: gpio20-pins { + pins = "GPIO20/SMB4CSDA/SMB15SDA"; + bias-disable; + input-enable; + }; + gpio21_pins: gpio21-pins { + pins = "GPIO21/SMB4CSCL/SMB15SCL"; + bias-disable; + input-enable; + }; + gpio22o_pins: gpio22o-pins { + pins = "GPIO22/SMB4DSDA/SMB14SDA"; + bias-disable; + output-high; + }; + gpio23_pins: gpio23-pins { + pins = "GPIO23/SMB4DSCL/SMB14SCL"; + bias-disable; + input-enable; + }; + gpio24_pins: gpio24-pins { + pins = "GPIO24/IOXHDO"; + bias-disable; + input-enable; + }; + gpio25_pins: gpio25-pins { + pins = "GPIO25/IOXHDI"; + bias-disable; + input-enable; + }; + gpio30_pins: gpio30-pins { + pins = "GPIO30/SMB3SDA"; + bias-disable; + input-enable; + }; + gpio31_pins: gpio31-pins { + pins = "GPIO31/SMB3SCL"; + bias-disable; + input-enable; + }; + gpio37o_pins: gpio37o-pins { + pins = "GPIO37/SMB3CSDA"; + bias-disable; + output-high; + }; + gpio38_pins: gpio38-pins { + pins = "GPIO38/SMB3CSCL"; + bias-disable; + input-enable; + }; + gpio39_pins: gpio39-pins { + pins = "GPIO39/SMB3BSDA"; + bias-disable; + input-enable; + }; + gpio40o_pins: gpio40o-pins { + pins = "GPIO40/SMB3BSCL"; + bias-disable; + output-high; + }; + gpio59_pins: gpio59-pins { + pins = "GPIO59/SMB3DSDA"; + bias-disable; + input-enable; + }; + gpio76_pins: gpio76-pins { + pins = "GPIO76/FANIN12"; + bias-disable; + input-enable; + }; + gpio77_pins: gpio77-pins { + pins = "GPIO77/FANIN13"; + bias-disable; + input-enable; + }; + gpio78o_pins: gpio78o-pins { + pins = "GPIO78/FANIN14"; + bias-disable; + output-high; + }; + gpio79_pins: gpio79-pins { + pins = "GPIO79/FANIN15"; + bias-disable; + input-enable; + }; + gpio82_pins: gpio82-pins { + pins = "GPIO82/PWM2"; + bias-disable; + input-enable; + }; + gpio83_pins: gpio83-pins { + pins = "GPIO83/PWM3"; + bias-disable; + input-enable; + }; + gpio84_pins: gpio84-pins { + pins = "GPIO84/R2TXD0"; + bias-disable; + input-enable; + }; + gpio85o_pins: gpio85o-pins { + pins = "GPIO85/R2TXD1"; + bias-disable; + output-high; + }; + gpio86ol_pins: gpio86ol-pins { + pins = "GPIO86/R2TXEN"; + bias-disable; + output-low; + }; + gpio87_pins: gpio87-pins { + pins = "GPIO87/R2RXD0"; + bias-disable; + input-enable; + }; + gpio88_pins: gpio88-pins { + pins = "GPIO88/R2RXD1"; + bias-disable; + input-enable; + }; + gpio89_pins: gpio89-pins { + pins = "GPIO89/R2CRSDV"; + bias-disable; + input-enable; + }; + gpio90_pins: gpio90-pins { + pins = "GPIO90/R2RXERR"; + bias-disable; + input-enable; + }; + gpio93_pins: gpio93-pins { + pins = "GPIO93/GA20/SMB5DSCL"; + bias-disable; + input-enable; + }; + gpio94ol_pins: gpio94ol-pins { + pins = "GPIO94/nKBRST/SMB5DSDA"; + bias-disable; + output-low; + }; + gpio108ol_pins: gpio108ol-pins { + pins = "GPIO108/RG1MDC"; + bias-disable; + output-low; + }; + gpio109ol_pins: gpio109ol-pins { + pins = "GPIO109/RG1MDIO"; + bias-disable; + output-low; + }; + gpio110ol_pins: gpio110ol-pins { + pins = "GPIO110/RG2TXD0/DDRV0"; + bias-disable; + output-low; + }; + gpio111ol_pins: gpio111ol-pins { + pins = "GPIO111/RG2TXD1/DDRV1"; + bias-disable; + output-low; + }; + gpio112ol_pins: gpio112ol-pins { + pins = "GPIO112/RG2TXD2/DDRV2"; + bias-disable; + output-low; + }; + gpio113ol_pins: gpio113ol-pins { + pins = "GPIO113/RG2TXD3/DDRV3"; + bias-disable; + output-low; + }; + gpio114o_pins: gpio114o-pins { + pins = "GPIO114/SMB0SCL"; + bias-disable; + output-high; + }; + gpio115_pins: gpio115-pins { + pins = "GPIO115/SMB0SDA"; + bias-disable; + input-enable; + }; + gpio120_pins: gpio120-pins { + pins = "GPIO120/SMB2CSDA"; + bias-disable; + input-enable; + }; + gpio121_pins: gpio121-pins { + pins = "GPIO121/SMB2CSCL"; + bias-disable; + input-enable; + }; + gpio122_pins: gpio122-pins { + pins = "GPIO122/SMB2BSDA"; + bias-disable; + input-enable; + }; + gpio123_pins: gpio123-pins { + pins = "GPIO123/SMB2BSCL"; + bias-disable; + input-enable; + }; + gpio124_pins: gpio124-pins { + pins = "GPIO124/SMB1CSDA"; + bias-disable; + input-enable; + }; + gpio125_pins: gpio125-pins { + pins = "GPIO125/SMB1CSCL"; + bias-disable; + input-enable; + }; + gpio126_pins: gpio126-pins { + pins = "GPIO126/SMB1BSDA"; + bias-disable; + input-enable; + }; + gpio127o_pins: gpio127o-pins { + pins = "GPIO127/SMB1BSCL"; + bias-disable; + output-high; + }; + gpio136_pins: gpio136-pins { + pins = "GPIO136/SD1DT0"; + bias-disable; + input-enable; + }; + gpio137_pins: gpio137-pins { + pins = "GPIO137/SD1DT1"; + bias-disable; + input-enable; + }; + gpio138_pins: gpio138-pins { + pins = "GPIO138/SD1DT2"; + bias-disable; + input-enable; + }; + gpio139_pins: gpio139-pins { + pins = "GPIO139/SD1DT3"; + bias-disable; + input-enable; + }; + gpio140_pins: gpio140-pins { + pins = "GPIO140/SD1CLK"; + bias-disable; + input-enable; + }; + gpio141_pins: gpio141-pins { + pins = "GPIO141/SD1WP"; + bias-disable; + input-enable; + }; + gpio142_pins: gpio142-pins { + pins = "GPIO142/SD1CMD"; + bias-disable; + input-enable; + }; + gpio143_pins: gpio143-pins { + pins = "GPIO143/SD1CD/SD1PWR"; + bias-disable; + input-enable; + }; + gpio144_pins: gpio144-pins { + pins = "GPIO144/PWM4"; + bias-disable; + input-enable; + }; + gpio145_pins: gpio145-pins { + pins = "GPIO145/PWM5"; + bias-disable; + input-enable; + }; + gpio146_pins: gpio146-pins { + pins = "GPIO146/PWM6"; + bias-disable; + input-enable; + }; + gpio147_pins: gpio147-pins { + pins = "GPIO147/PWM7"; + bias-disable; + input-enable; + }; + gpio153o_pins: gpio153o-pins { + pins = "GPIO153/MMCWP"; + bias-disable; + output-high; + }; + gpio155_pins: gpio155-pins { + pins = "GPIO155/nMMCCD/nMMCRST"; + bias-disable; + input-enable; + }; + gpio160o_pins: gpio160o-pins { + pins = "GPIO160/CLKOUT/RNGOSCOUT"; + bias-disable; + output-high; + }; + gpio169o_pins: gpio169o-pins { + pins = "GPIO169/nSCIPME"; + bias-disable; + output-high; + }; + gpio188o_pins: gpio188o-pins { + pins = "GPIO188/SPI3D2/nSPI3CS2"; + bias-disable; + output-high; + }; + gpio189_pins: gpio189-pins { + pins = "GPIO189/SPI3D3/nSPI3CS3"; + bias-disable; + input-enable; + }; + gpio196_pins: gpio196-pins { + pins = "GPIO196/SMB0CSCL"; + bias-disable; + input-enable; + }; + gpio197_pins: gpio197-pins { + pins = "GPIO197/SMB0DEN"; + bias-disable; + input-enable; + }; + gpio198o_pins: gpio198o-pins { + pins = "GPIO198/SMB0DSDA"; + bias-disable; + output-high; + }; + gpio199o_pins: gpio199o-pins { + pins = "GPIO199/SMB0DSCL"; + bias-disable; + output-high; + }; + gpio200_pins: gpio200-pins { + pins = "GPIO200/R2CK"; + input-enable; + bias-disable; + }; + gpio202_pins: gpio202-pins { + pins = "GPIO202/SMB0CSDA"; + bias-disable; + input-enable; + }; + gpio203o_pins: gpio203o-pins { + pins = "GPIO203/FANIN16"; + bias-disable; + output-high; + }; + gpio208_pins: gpio208-pins { + pins = "GPIO208/RG2TXC/DVCK"; + bias-disable; + input-enable; + }; + gpio209ol_pins: gpio209ol-pins { + pins = "GPIO209/RG2TXCTL/DDRV4"; + bias-disable; + output-low; + }; + gpio210ol_pins: gpio210ol-pins { + pins = "GPIO210/RG2RXD0/DDRV5"; + bias-disable; + output-low; + }; + gpio211ol_pins: gpio211ol-pins { + pins = "GPIO211/RG2RXD1/DDRV6"; + bias-disable; + output-low; + }; + gpio212ol_pins: gpio212ol-pins { + pins = "GPIO212/RG2RXD2/DDRV7"; + bias-disable; + output-low; + }; + gpio213ol_pins: gpio213ol-pins { + pins = "GPIO213/RG2RXD3/DDRV8"; + bias-disable; + output-low; + }; + gpio214ol_pins: gpio214ol-pins { + pins = "GPIO214/RG2RXC/DDRV9"; + bias-disable; + output-low; + }; + gpio215ol_pins: gpio215ol-pins { + pins = "GPIO215/RG2RXCTL/DDRV10"; + bias-disable; + output-low; + }; + gpio216ol_pins: gpio216ol-pins { + pins = "GPIO216/RG2MDC/DDRV11"; + bias-disable; + output-low; + }; + gpio217ol_pins: gpio217ol-pins { + pins = "GPIO217/RG2MDIO/DVHSYNC"; + bias-disable; + output-low; + }; + gpio224_pins: gpio224-pins { + pins = "GPIO224/SPIXCK"; + bias-disable; + input-enable; + }; + gpio225ol_pins: gpio225ol-pins { + pins = "GPO225/SPIXD0/STRAP12"; + bias-disable; + output-low; + }; + gpio226ol_pins: gpio226ol-pins { + pins = "GPO226/SPIXD1/STRAP13"; + bias-disable; + output-low; + }; + gpio227ol_pins: gpio227ol-pins { + pins = "GPIO227/nSPIXCS0"; + bias-disable; + output-low; + }; + gpio228o_pins: gpio228ol-pins { + pins = "GPIO228/nSPIXCS1"; + bias-disable; + output-high; + }; + gpio229o_pins: gpio229o-pins { + pins = "GPO229/SPIXD2/STRAP3"; + bias-disable; + output-high; + }; + gpio230_pins: gpio230-pins { + pins = "GPIO230/SPIXD3"; + bias-disable; + input-enable; + }; + gpio231o_pins: gpio231o-pins { + pins = "GPIO231/nCLKREQ"; + bias-disable; + output-high; + }; + }; +}; diff --git a/arch/arm/boot/dts/nuvoton-npcm750-runbmc-olympus.dts b/arch/arm/boot/dts/nuvoton-npcm750-runbmc-olympus.dts new file mode 100644 index 000000000000..767e0ac0df7c --- /dev/null +++ b/arch/arm/boot/dts/nuvoton-npcm750-runbmc-olympus.dts @@ -0,0 +1,1052 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2019 Nuvoton Technology +// Copyright (c) 2019 Quanta Computer Inc. + +/dts-v1/; +#include "nuvoton-npcm750.dtsi" +#include "nuvoton-npcm750-runbmc-olympus-pincfg.dtsi" + +#include +#include + +/ { + model = "Nuvoton npcm750 RunBMC Olympus"; + compatible = "nuvoton,npcm750"; + + aliases { + ethernet1 = &gmac0; + serial0 = &serial0; + serial1 = &serial1; + serial2 = &serial2; + serial3 = &serial3; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c5; + i2c6 = &i2c6; + i2c7 = &i2c7; + i2c8 = &i2c8; + i2c9 = &i2c9; + i2c10 = &i2c10; + i2c11 = &i2c11; + i2c12 = &i2c12; + i2c13 = &i2c13; + spi0 = &spi0; + spi1 = &spi1; + fiu0 = &fiu0; + fiu1 = &fiu3; + }; + + chosen { + stdout-path = &serial3; + }; + + memory { + reg = <0 0x40000000>; + }; + + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, + <&adc 4>, <&adc 5>, <&adc 6>, <&adc 7>; + }; + + leds { + compatible = "gpio-leds"; + heartbeat { + label = "heartbeat"; + gpios = <&gpio3 14 1>; + }; + + identify { + label = "identify"; + gpios = <&gpio3 15 1>; + }; + }; + + jtag { + compatible = "nuvoton,npcm750-jtag"; + enable_pspi_jtag = <1>; + pspi-index = <2>; + tck { + label = "tck"; + gpios = <&gpio0 19 0>; /* gpio19 */ + regbase = <0xf0010000 0x1000>; + }; + + tdi { + label = "tdi"; + gpios = <&gpio0 18 0>; /* gpio18 */ + regbase = <0xf0010000 0x1000>; + }; + + tdo { + label = "tdo"; + gpios = <&gpio0 17 0>; /* gpio17 */ + regbase = <0xf0010000 0x1000>; + }; + tms { + label = "tms"; + gpios = <&gpio0 16 0>; /* gpio16 */ + regbase = <0xf0010000 0x1000>; + }; + }; +}; + +&fiu0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0cs1_pins>; + status = "okay"; + + spi-nor@0 { + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0>; + spi-rx-bus-width = <2>; + + partitions@80000000 { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + bmc@0{ + label = "bmc"; + reg = <0x000000 0x2000000>; + }; + u-boot@0 { + label = "u-boot"; + reg = <0x0000000 0x80000>; + read-only; + }; + u-boot-env@100000{ + label = "u-boot-env"; + reg = <0x00100000 0x40000>; + }; + kernel@200000 { + label = "kernel"; + reg = <0x0200000 0x600000>; + }; + rofs@800000 { + label = "rofs"; + reg = <0x800000 0x1500000>; + }; + rwfs@1d00000 { + label = "rwfs"; + reg = <0x1d00000 0x300000>; + }; + }; + }; + + spi-nor@1 { + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + reg = <1>; + npcm,fiu-rx-bus-width = <2>; + + partitions@88000000 { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + spare1@0 { + label = "spi0-cs1-spare1"; + reg = <0x0 0x800000>; + }; + spare2@800000 { + label = "spi0-cs1-spare2"; + reg = <0x800000 0x0>; + }; + }; + }; +}; + +&fiu3 { + pinctrl-0 = <&spi3_pins>; + status = "okay"; + + spi-nor@0 { + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0>; + spi-rx-bus-width = <2>; + + partitions@A0000000 { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + system1@0 { + label = "spi3-system1"; + reg = <0x0 0x800000>; + }; + system2@800000 { + label = "spi3-system2"; + reg = <0x800000 0x0>; + }; + }; + }; +}; + +&gcr { + mux-controller { + compatible = "mmio-mux"; + #mux-control-cells = <1>; + + mux-reg-masks = <0x38 0x07>; + idle-states = <6>; + }; +}; + +&gmac0 { + phy-mode = "rgmii-id"; + snps,eee-force-disable; + status = "okay"; +}; + +&i2c1 { + status = "okay"; + + i2c-switch@70 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + i2c-mux-idle-disconnect; + + i2c_slot1a: i2c-bus@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + i2c_slot1b: i2c-bus@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + i2c_slot2a: i2c-bus@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + i2c_slot2b: i2c-bus@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + + i2c_slot3: i2c-bus@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + + i2c_slot4: i2c-bus@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + + i2c_slot5: i2c-bus@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + }; + + i2c-switch@71 { + compatible = "nxp,pca9546"; + reg = <0x71>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + + i2c_m2_s1: i2c-bus@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + i2c_m2_s2: i2c-bus@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + i2c_m2_s3: i2c-bus@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + i2c_m2_s4: i2c-bus@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + }; +}; + +&i2c2 { + status = "okay"; + + tmp421@4c { + compatible = "ti,tmp421"; + reg = <0x4c>; + }; + + power-supply@58 { + compatible = "delta,dps800"; + reg = <0x58>; + }; +}; + +&i2c3 { + status = "okay"; +}; + +&i2c4 { + status = "okay"; + + eeprom@54 { + compatible = "atmel,24c64"; + reg = <0x54>; + }; +}; + +&i2c5 { + status = "okay"; + + i2c-slave-mqueue@10 { + compatible = "i2c-slave-mqueue"; + reg = <(I2C_OWN_SLAVE_ADDRESS | 0x10)>; + }; +}; + +&i2c6 { + status = "okay"; + + ina219@40 { + compatible = "ti,ina219"; + reg = <0x40>; + }; + ina219@41 { + compatible = "ti,ina219"; + reg = <0x41>; + }; + ina219@44 { + compatible = "ti,ina219"; + reg = <0x44>; + }; + ina219@45 { + compatible = "ti,ina219"; + reg = <0x45>; + }; + tps53679@60 { + compatible = "ti,tps53679"; + reg = <0x60>; + }; + tps53659@62 { + compatible = "ti,tps53659"; + reg = <0x62>; + }; + tps53659@64 { + compatible = "ti,tps53659"; + reg = <0x64>; + }; + tps53622@67 { + compatible = "ti,tps53622"; + reg = <0x67>; + }; + tps53622@69 { + compatible = "ti,tps53622"; + reg = <0x69>; + }; + tps53679@70 { + compatible = "ti,tps53679"; + reg = <0x70>; + }; + tps53659@72 { + compatible = "ti,tps53659"; + reg = <0x72>; + }; + tps53659@74 { + compatible = "ti,tps53659"; + reg = <0x74>; + }; + tps53622@77 { + compatible = "ti,tps53622"; + reg = <0x77>; + }; +}; + +&i2c7 { + status = "okay"; + + tmp421@4c { + compatible = "ti,tmp421"; + reg = <0x4c>; + }; +}; + +&i2c8 { + status = "okay"; + + adm1278@11 { + compatible = "adm1278"; + reg = <0x11>; + Rsense = <500>; + }; +}; + +&i2c9 { + status = "okay"; +}; + +&i2c10 { + status = "okay"; + + gpio: pca9555@27 { + compatible = "nxp,pca9555"; + reg = <0x27>; + + gpio-controller; + #gpio-cells = <2>; + }; +}; + +&i2c11 { + status = "okay"; + + pca9539_g1a: pca9539-g1a@74 { + compatible = "nxp,pca9539"; + reg = <0x74>; + gpio-controller; + #gpio-cells = <2>; + reset-gpios = <&gpio7 4 GPIO_ACTIVE_LOW>; + G1A_P0_0 { + gpio-hog; + gpios = <0 0>; + output-high; + line-name = "TPM_BMC_ALERT_N"; + }; + G1A_P0_1 { + gpio-hog; + gpios = <1 0>; + input; + line-name = "FM_BIOS_TOP_SWAP"; + }; + G1A_P0_2 { + gpio-hog; + gpios = <2 0>; + input; + line-name = "FM_BIOS_PREFRB2_GOOD"; + }; + G1A_P0_3 { + gpio-hog; + gpios = <3 0>; + input; + line-name = "BMC_SATAXPCIE_0TO3_SEL"; + }; + G1A_P0_4 { + gpio-hog; + gpios = <4 0>; + input; + line-name = "BMC_SATAXPCIE_4TO7_SEL"; + }; + G1A_P0_5 { + gpio-hog; + gpios = <5 0>; + output-low; + line-name = "FM_UV_ADR_TRIGGER_EN_N"; + }; + G1A_P0_6 { + gpio-hog; + gpios = <6 0>; + input; + line-name = "RM_THROTTLE_EN_N"; + }; + G1A_P1_0 { + gpio-hog; + gpios = <8 0>; + input; + line-name = "FM_BMC_TPM_PRES_N"; + }; + G1A_P1_1 { + gpio-hog; + gpios = <9 0>; + input; + line-name = "FM_CPU0_SKTOCC_LVT3_N"; + }; + G1A_P1_2 { + gpio-hog; + gpios = <10 0>; + input; + line-name = "FM_CPU1_SKTOCC_LVT3_N"; + }; + G1A_P1_3 { + gpio-hog; + gpios = <11 0>; + input; + line-name = "PSU1_ALERT_N"; + }; + G1A_P1_4 { + gpio-hog; + gpios = <12 0>; + input; + line-name = "PSU2_ALERT_N"; + }; + G1A_P1_5 { + gpio-hog; + gpios = <13 0>; + input; + line-name = "H_CPU0_FAST_WAKE_LVT3_N"; + }; + G1A_P1_6 { + gpio-hog; + gpios = <14 0>; + output-high; + line-name = "I2C_MUX1_RESET_N"; + }; + G1A_P1_7 { + gpio-hog; + gpios = <15 0>; + input; + line-name = "FM_CPU_CATERR_LVT3_N"; + }; + }; + + pca9539_g1b: pca9539-g1b@75 { + compatible = "nxp,pca9539"; + reg = <0x75>; + gpio-controller; + #gpio-cells = <2>; + G1B_P0_0 { + gpio-hog; + gpios = <0 0>; + input; + line-name = "PVDDQ_ABC_PINALERT_N"; + }; + G1B_P0_1 { + gpio-hog; + gpios = <1 0>; + input; + line-name = "PVDDQ_DEF_PINALERT_N"; + }; + G1B_P0_2 { + gpio-hog; + gpios = <2 0>; + input; + line-name = "PVDDQ_GHJ_PINALERT_N"; + }; + G1B_P0_3 { + gpio-hog; + gpios = <3 0>; + input; + line-name = "PVDDQ_KLM_PINALERT_N"; + }; + G1B_P0_5 { + gpio-hog; + gpios = <5 0>; + input; + line-name = "FM_BOARD_REV_ID0"; + }; + G1B_P0_6 { + gpio-hog; + gpios = <6 0>; + input; + line-name = "FM_BOARD_REV_ID1"; + }; + G1B_P0_7 { + gpio-hog; + gpios = <7 0>; + input; + line-name = "FM_BOARD_REV_ID2"; + }; + G1B_P1_0 { + gpio-hog; + gpios = <8 0>; + input; + line-name = "FM_OC_DETECT_EN_N"; + }; + G1B_P1_1 { + gpio-hog; + gpios = <9 0>; + input; + line-name = "FM_FLASH_DESC_OVERRIDE"; + }; + G1B_P1_2 { + gpio-hog; + gpios = <10 0>; + output-low; + line-name = "FP_PWR_ID_LED_N"; + }; + G1B_P1_3 { + gpio-hog; + gpios = <11 0>; + output-low; + line-name = "BMC_LED_PWR_GRN"; + }; + G1B_P1_4 { + gpio-hog; + gpios = <12 0>; + output-low; + line-name = "BMC_LED_PWR_AMBER"; + }; + G1B_P1_5 { + gpio-hog; + gpios = <13 0>; + output-high; + line-name = "FM_BMC_FAULT_LED_N"; + }; + G1B_P1_6 { + gpio-hog; + gpios = <14 0>; + output-high; + line-name = "FM_CPLD_BMC_PWRDN_N"; + }; + G1B_P1_7 { + gpio-hog; + gpios = <15 0>; + output-high; + line-name = "BMC_LED_CATERR_N"; + }; + }; +}; + +&i2c12 { + status = "okay"; + + pca9539_g2a: pca9539-g2a@74 { + compatible = "nxp,pca9539"; + reg = <0x74>; + gpio-controller; + #gpio-cells = <2>; + reset-gpios = <&gpio5 28 GPIO_ACTIVE_LOW>; + G2A_P0_0 { + gpio-hog; + gpios = <0 0>; + output-high; + line-name = "BMC_PON_RST_REQ_N"; + }; + G2A_P0_1 { + gpio-hog; + gpios = <1 0>; + output-high; + line-name = "BMC_RST_IND_REQ_N"; + }; + G2A_P0_2 { + gpio-hog; + gpios = <2 0>; + input; + line-name = "RST_BMC_RTCRST"; + }; + G2A_P0_3 { + gpio-hog; + gpios = <3 0>; + output-high; + line-name = "FM_BMC_PWRBTN_OUT_N"; + }; + G2A_P0_4 { + gpio-hog; + gpios = <4 0>; + output-high; + line-name = "RST_BMC_SYSRST_BTN_OUT_N"; + }; + G2A_P0_5 { + gpio-hog; + gpios = <5 0>; + output-high; + line-name = "FM_BATTERY_SENSE_EN_N"; + }; + G2A_P0_6 { + gpio-hog; + gpios = <6 0>; + output-high; + line-name = "FM_BMC_READY_N"; + }; + G2A_P0_7 { + gpio-hog; + gpios = <7 0>; + input; + line-name = "IRQ_BMC_PCH_SMI_LPC_N"; + }; + G2A_P1_0 { + gpio-hog; + gpios = <8 0>; + input; + line-name = "FM_SLOT4_CFG0"; + }; + G2A_P1_1 { + gpio-hog; + gpios = <9 0>; + input; + line-name = "FM_SLOT4_CFG1"; + }; + G2A_P1_2 { + gpio-hog; + gpios = <10 0>; + input; + line-name = "FM_NVDIMM_EVENT_N"; + }; + G2A_P1_3 { + gpio-hog; + gpios = <11 0>; + input; + line-name = "PSU1_BLADE_EN_N"; + }; + G2A_P1_4 { + gpio-hog; + gpios = <12 0>; + input; + line-name = "BMC_PCH_FNM"; + }; + G2A_P1_5 { + gpio-hog; + gpios = <13 0>; + input; + line-name = "FM_SOL_UART_CH_SEL"; + }; + G2A_P1_6 { + gpio-hog; + gpios = <14 0>; + input; + line-name = "FM_BIOS_POST_CMPLT_N"; + }; + }; + + pca9539_g2b: pca9539-g2b@75 { + compatible = "nxp,pca9539"; + reg = <0x75>; + gpio-controller; + #gpio-cells = <2>; + G2B_P0_0 { + gpio-hog; + gpios = <0 0>; + input; + line-name = "FM_CPU_MSMI_LVT3_N"; + }; + G2B_P0_1 { + gpio-hog; + gpios = <1 0>; + input; + line-name = "FM_BIOS_MRC_DEBUG_MSG_DIS"; + }; + G2B_P0_2 { + gpio-hog; + gpios = <2 0>; + input; + line-name = "FM_CPU1_DISABLE_BMC_N"; + }; + G2B_P0_3 { + gpio-hog; + gpios = <3 0>; + output-low; + line-name = "BMC_JTAG_SELECT"; + }; + G2B_P0_4 { + gpio-hog; + gpios = <4 0>; + output-high; + line-name = "PECI_MUX_SELECT"; + }; + G2B_P0_5 { + gpio-hog; + gpios = <5 0>; + output-high; + line-name = "I2C_MUX2_RESET_N"; + }; + G2B_P0_6 { + gpio-hog; + gpios = <6 0>; + input; + line-name = "FM_BMC_CPLD_PSU2_ON"; + }; + G2B_P0_7 { + gpio-hog; + gpios = <7 0>; + output-high; + line-name = "PSU2_ALERT_EN_N"; + }; + G2B_P1_0 { + gpio-hog; + gpios = <8 0>; + output-high; + line-name = "FM_CPU_BMC_INIT"; + }; + G2B_P1_1 { + gpio-hog; + gpios = <9 0>; + output-high; + line-name = "IRQ_BMC_PCH_SCI_LPC_N"; + }; + G2B_P1_2 { + gpio-hog; + gpios = <10 0>; + output-low; + line-name = "PMB_ALERT_EN_N"; + }; + G2B_P1_3 { + gpio-hog; + gpios = <11 0>; + output-high; + line-name = "FM_FAST_PROCHOT_EN_N"; + }; + G2B_P1_4 { + gpio-hog; + gpios = <12 0>; + output-high; + line-name = "BMC_NVDIMM_PRSNT_N"; + }; + G2B_P1_5 { + gpio-hog; + gpios = <13 0>; + output-low; + line-name = "FM_BACKUP_BIOS_SEL_H_BMC"; + }; + G2B_P1_6 { + gpio-hog; + gpios = <14 0>; + output-high; + line-name = "FM_PWRBRK_N"; + }; + }; +}; + +&i2c13 { + status = "okay"; + + tmp75@4a { + compatible = "ti,tmp75"; + reg = <0x4a>; + status = "okay"; + }; + m24128_fru@51 { + compatible = "atmel,24c128"; + reg = <0x51>; + pagesize = <64>; + status = "okay"; + }; +}; + +&pwm_fan { + pinctrl-names = "default"; + pinctrl-0 = < &pwm0_pins &pwm1_pins + &fanin0_pins &fanin1_pins + &fanin2_pins &fanin3_pins + &fanin4_pins &fanin5_pins + &fanin6_pins &fanin7_pins + &fanin8_pins &fanin9_pins + &fanin10_pins &fanin11_pins>; + status = "okay"; + + fan@0 { + reg = <0x00>; + fan-tach-ch = /bits/ 8 <0x00 0x01>; + cooling-levels = <127 255>; + }; + fan@1 { + reg = <0x01>; + fan-tach-ch = /bits/ 8 <0x02 0x03>; + cooling-levels = /bits/ 8 <127 255>; + }; + fan@2 { + reg = <0x02>; + fan-tach-ch = /bits/ 8 <0x04 0x05>; + cooling-levels = /bits/ 8 <127 255>; + }; + fan@3 { + reg = <0x03>; + fan-tach-ch = /bits/ 8 <0x06 0x07>; + cooling-levels = /bits/ 8 <127 255>; + }; + fan@4 { + reg = <0x04>; + fan-tach-ch = /bits/ 8 <0x08 0x09>; + cooling-levels = /bits/ 8 <127 255>; + }; + fan@5 { + reg = <0x05>; + fan-tach-ch = /bits/ 8 <0x0A 0x0B>; + cooling-levels = /bits/ 8 <127 255>; + }; + fan@6 { + reg = <0x06>; + fan-tach-ch = /bits/ 8 <0x0C 0x0D>; + cooling-levels = /bits/ 8 <127 255>; + }; + fan@7 { + reg = <0x07>; + fan-tach-ch = /bits/ 8 <0x0E 0x0F>; + cooling-levels = /bits/ 8 <127 255>; + }; +}; + +&ehci1 { + status = "okay"; +}; + +&watchdog1 { + status = "okay"; +}; + +&rng { + status = "okay"; +}; + +&serial0 { + status = "okay"; +}; + +&serial1 { + status = "okay"; +}; + +&serial2 { + status = "okay"; +}; + +&serial3 { + status = "okay"; +}; + +&adc { + #io-channel-cells = <1>; + status = "okay"; +}; + +&kcs1 { + status = "okay"; +}; + +&kcs2 { + status = "okay"; +}; + +&kcs3 { + status = "okay"; +}; + +&spi0 { + cs-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&spi1 { + status = "okay"; +}; + +&pinctrl { + pinctrl-names = "default"; + pinctrl-0 = < + /******* RunBMC inside Module pins *******/ + &gpio0ol_pins + &gpio1ol_pins + &gpio2ol_pins + &gpio3ol_pins + &gpio8o_pins + &gpio9ol_pins + &gpio12ol_pins + &gpio13ol_pins + &gpio14ol_pins + &gpio15ol_pins + &gpio37o_pins + &gpio38_pins + &gpio39_pins + &gpio94ol_pins + &gpio108ol_pins + &gpio109ol_pins + &gpio111ol_pins + &gpio112ol_pins + &gpio113ol_pins + &gpio208_pins + &gpio209ol_pins + &gpio210ol_pins + &gpio211ol_pins + &gpio212ol_pins + &gpio213ol_pins + &gpio214ol_pins + &gpio215ol_pins + &gpio216ol_pins + &gpio217ol_pins + /******* RunBMC outside Connector pins *******/ + &gpio5_pins + &gpio6_pins + &gpio7_pins + &gpio10_pins + &gpio11_pins + &gpio20_pins + &gpio21_pins + &gpio22o_pins + &gpio23_pins + &gpio24_pins + &gpio25_pins + &gpio30_pins + &gpio31_pins + &gpio40o_pins + &gpio59_pins + &gpio76_pins + &gpio77_pins + &gpio78o_pins + &gpio79_pins + &gpio82_pins + &gpio83_pins + &gpio84_pins + &gpio85o_pins + &gpio86ol_pins + &gpio87_pins + &gpio88_pins + &gpio89_pins + &gpio90_pins + &gpio93_pins + &gpio114o_pins + &gpio115_pins + &gpio120_pins + &gpio121_pins + &gpio122_pins + &gpio123_pins + &gpio124_pins + &gpio125_pins + &gpio126_pins + &gpio127o_pins + &gpio136_pins + &gpio137_pins + &gpio138_pins + &gpio139_pins + &gpio140_pins + &gpio141_pins + &gpio142_pins + &gpio143_pins + &gpio144_pins + &gpio146_pins + &gpio145_pins + &gpio147_pins + &gpio153o_pins + &gpio155_pins + &gpio160o_pins + &gpio169o_pins + &gpio188o_pins + &gpio189_pins + &gpio196_pins + &gpio197_pins + &gpio198o_pins + &gpio199o_pins + &gpio200_pins + &gpio202_pins + &gpio203o_pins + &gpio224_pins + &gpio225ol_pins + &gpio226ol_pins + &gpio227ol_pins + &gpio228o_pins + &gpio229o_pins + &gpio230_pins + &gpio231o_pins + &ddc_pins + &wdog1_pins + &wdog2_pins + >; +}; -- cgit v1.2.3-59-g8ed1b From 14579c76f5ca35dbf119685994aa0a5c5a0d9630 Mon Sep 17 00:00:00 2001 From: Lancelot Kao Date: Mon, 16 Nov 2020 17:21:27 -0600 Subject: ARM: dts: nuvoton: Add Fii Kudo system Add device tree for the Kudo BMC. Kudo is an Ampere (Altra) server platform manufactured by Fii and is based on a Nuvoton NPCM730 SoC. Signed-off-by: Mustatfa Shehabi Signed-off-by: Mohaimen alsmarai Signed-off-by: Lancelot Kao Reviewed-by: Vivekanand Veeracholan Reviewed-by: Benjamin Fair Reviewed-by: Joel Stanley Link: https://lore.kernel.org/r/20201116232127.7066-1-lancelot.kao@fii-usa.com Signed-off-by: Joel Stanley --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/nuvoton-npcm730-kudo.dts | 826 +++++++++++++++++++++++++++++ 2 files changed, 827 insertions(+) create mode 100644 arch/arm/boot/dts/nuvoton-npcm730-kudo.dts (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index ad2eaf9ed4e4..7525d38ea1ab 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -340,6 +340,7 @@ dtb-$(CONFIG_ARCH_LPC32XX) += \ lpc3250-phy3250.dtb dtb-$(CONFIG_ARCH_NPCM7XX) += \ nuvoton-npcm730-gsj.dtb \ + nuvoton-npcm730-kudo.dtb \ nuvoton-npcm750-evb.dtb \ nuvoton-npcm750-runbmc-olympus.dtb dtb-$(CONFIG_MACH_MESON6) += \ diff --git a/arch/arm/boot/dts/nuvoton-npcm730-kudo.dts b/arch/arm/boot/dts/nuvoton-npcm730-kudo.dts new file mode 100644 index 000000000000..82a104b2a65f --- /dev/null +++ b/arch/arm/boot/dts/nuvoton-npcm730-kudo.dts @@ -0,0 +1,826 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2020 Fii USA Inc. + +/dts-v1/; +#include "nuvoton-npcm730.dtsi" + +#include + +/ { + model = "Fii Kudo Board"; + compatible = "fii,kudo", "nuvoton,npcm730"; + + aliases { + ethernet1 = &gmac0; + serial0 = &serial0; + serial1 = &serial1; + serial2 = &serial2; + serial3 = &serial3; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c5; + i2c6 = &i2c6; + i2c7 = &i2c7; + i2c8 = &i2c8; + i2c9 = &i2c9; + i2c10 = &i2c10; + i2c11 = &i2c11; + i2c12 = &i2c12; + i2c13 = &i2c13; + i2c14 = &i2c14; + i2c15 = &i2c15; + spi0 = &spi0; + spi1 = &spi1; + fiu0 = &fiu0; + fiu1 = &fiu3; + }; + + chosen { + stdout-path = &serial3; + }; + + memory { + reg = <0 0x40000000>; + }; + + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, + <&adc 4>, <&adc 5>, <&adc 6>, <&adc 7>; + }; + + jtag_master { + compatible = "nuvoton,npcm750-jtag-master"; + #address-cells = <1>; + #size-cells = <1>; + + // dev/jtag0 + dev-num = <0>; + // pspi or gpio + mode = "pspi"; + + // pspi2 + pspi-controller = <2>; + reg = <0xf0201000 0x1000>; + interrupts = ; + clocks = <&clk NPCM7XX_CLK_APB5>; + + // TCK, TDI, TDO, TMS + jtag-gpios = <&gpio0 19 GPIO_ACTIVE_HIGH>, + <&gpio0 18 GPIO_ACTIVE_HIGH>, + <&gpio0 17 GPIO_ACTIVE_HIGH>, + <&gpio0 16 GPIO_ACTIVE_HIGH>; + }; + + leds { + compatible = "gpio-leds"; + heartbeat { + label = "heartbeat"; + gpios = <&gpio0 14 1>; + }; + }; + + pinctrl: pinctrl@f0800000 { + gpio61oh_pins: gpio61oh-pins { + pins = "GPO61/nDTR1_BOUT1/STRAP6"; + bias-disable; + output-high; + }; + gpio62oh_pins: gpio62oh-pins { + pins = "GPO62/nRTST1/STRAP5"; + bias-disable; + output-high; + }; + gpio161ol_pins: gpio161ol-pins { + pins = "GPIO161/nLFRAME/nESPICS"; + bias-disable; + output-low; + }; + gpio163i_pins: gpio163i-pins { + pins = "GPIO163/LCLK/ESPICLK"; + bias-disable; + input-enable; + }; + gpio167ol_pins: gpio167ol-pins { + pins = "GPIO167/LAD3/ESPI_IO3"; + bias-disable; + output-low; + }; + gpio95i_pins: gpio95i-pins { + pins = "GPIO95/nLRESET/nESPIRST"; + bias-disable; + input-enable; + }; + gpio65ol_pins: gpio65ol-pins { + pins = "GPIO65/FANIN1"; + bias-disable; + output-low; + }; + gpio66oh_pins: gpio66oh-pins { + pins = "GPIO66/FANIN2"; + bias-disable; + output-high; + }; + gpio67oh_pins: gpio67oh-pins { + pins = "GPIO67/FANIN3"; + bias-disable; + output-high; + }; + gpio68ol_pins: gpio68ol-pins { + pins = "GPIO68/FANIN4"; + bias-disable; + output-low; + }; + gpio69i_pins: gpio69i-pins { + pins = "GPIO69/FANIN5"; + bias-disable; + input-enable; + }; + gpio70ol_pins: gpio70ol-pins { + pins = "GPIO70/FANIN6"; + bias-disable; + output-low; + }; + gpio71i_pins: gpio71i-pins { + pins = "GPIO71/FANIN7"; + bias-disable; + input-enable; + }; + gpio72i_pins: gpio72i-pins { + pins = "GPIO72/FANIN8"; + bias-disable; + input-enable; + }; + gpio73i_pins: gpio73i-pins { + pins = "GPIO73/FANIN9"; + bias-disable; + input-enable; + }; + gpio74i_pins: gpio74i-pins { + pins = "GPIO74/FANIN10"; + bias-disable; + input-enable; + }; + gpio75i_pins: gpio75i-pins { + pins = "GPIO75/FANIN11"; + bias-disable; + input-enable; + }; + gpio76i_pins: gpio76i-pins { + pins = "GPIO76/FANIN12"; + bias-disable; + input-enable; + }; + gpio77i_pins: gpio77i-pins { + pins = "GPIO77/FANIN13"; + bias-disable; + input-enable; + }; + gpio78i_pins: gpio78i-pins { + pins = "GPIO78/FANIN14"; + bias-disable; + input-enable; + }; + gpio79ol_pins: gpio79ol-pins { + pins = "GPIO79/FANIN15"; + bias-disable; + output-low; + }; + gpio80oh_pins: gpio80oh-pins { + pins = "GPIO80/PWM0"; + bias-disable; + output-high; + }; + gpio81i_pins: gpio81i-pins { + pins = "GPIO81/PWM1"; + bias-disable; + input-enable; + }; + gpio82i_pins: gpio82i-pins { + pins = "GPIO82/PWM2"; + bias-disable; + input-enable; + }; + gpio83i_pins: gpio83i-pins { + pins = "GPIO83/PWM3"; + bias-disable; + input-enable; + }; + gpio144i_pins: gpio144i-pins { + pins = "GPIO144/PWM4"; + bias-disable; + input-enable; + }; + gpio145i_pins: gpio145i-pins { + pins = "GPIO145/PWM5"; + bias-disable; + input-enable; + }; + gpio146i_pins: gpio146i-pins { + pins = "GPIO146/PWM6"; + bias-disable; + input-enable; + }; + gpio147oh_pins: gpio147oh-pins { + pins = "GPIO147/PWM7"; + bias-disable; + output-high; + }; + gpio168ol_pins: gpio168ol-pins { + pins = "GPIO168/nCLKRUN/nESPIALERT"; + bias-disable; + output-low; + }; + gpio169oh_pins: gpio169oh-pins { + pins = "GPIO169/nSCIPME"; + bias-disable; + output-high; + }; + gpio170ol_pins: gpio170ol-pins { + pins = "GPIO170/nSMI"; + bias-disable; + output-low; + }; + gpio218oh_pins: gpio218oh-pins { + pins = "GPIO218/nWDO1"; + bias-disable; + output-high; + }; + gpio37i_pins: gpio37i-pins { + pins = "GPIO37/SMB3CSDA"; + bias-disable; + input-enable; + }; + gpio38i_pins: gpio38i-pins { + pins = "GPIO38/SMB3CSCL"; + bias-disable; + input-enable; + }; + gpio39i_pins: gpio39i-pins { + pins = "GPIO39/SMB3BSDA"; + bias-disable; + input-enable; + }; + gpio40i_pins: gpio40i-pins { + pins = "GPIO40/SMB3BSCL"; + bias-disable; + input-enable; + }; + gpio121i_pins: gpio121i-pins { + pins = "GPIO121/SMB2CSCL"; + bias-disable; + input-enable; + }; + gpio122i_pins: gpio122i-pins { + pins = "GPIO122/SMB2BSDA"; + bias-disable; + input-enable; + }; + gpio123i_pins: gpio123i-pins { + pins = "GPIO123/SMB2BSCL"; + bias-disable; + input-enable; + }; + gpio124i_pins: gpio124i-pins { + pins = "GPIO124/SMB1CSDA"; + bias-disable; + input-enable; + }; + gpio125i_pins: gpio125i-pins { + pins = "GPIO125/SMB1CSCL"; + bias-disable; + input-enable; + }; + gpio126i_pins: gpio126i-pins { + pins = "GPIO126/SMB1BSDA"; + bias-disable; + input-enable; + }; + gpio127i_pins: gpio127i-pins { + pins = "GPIO127/SMB1BSCL"; + bias-disable; + input-enable; + }; + gpio136i_pins: gpio136i-pins { + pins = "GPIO136/SD1DT0"; + bias-disable; + input-enable; + }; + gpio137oh_pins: gpio137oh-pins { + pins = "GPIO137/SD1DT1"; + bias-disable; + output-high; + }; + gpio138i_pins: gpio138i-pins { + pins = "GPIO138/SD1DT2"; + bias-disable; + input-enable; + }; + gpio139i_pins: gpio139i-pins { + pins = "GPIO139/SD1DT3"; + bias-disable; + input-enable; + }; + gpio140i_pins: gpio140i-pins { + pins = "GPIO140/SD1CLK"; + bias-disable; + input-enable; + }; + gpio141i_pins: gpio141i-pins { + pins = "GPIO141/SD1WP"; + bias-disable; + input-enable; + }; + gpio190oh_pins: gpio190oh-pins { + pins = "GPIO190/nPRD_SMI"; + bias-disable; + output-high; + }; + gpio191oh_pins: gpio191oh-pins { + pins = "GPIO191"; + bias-disable; + output-high; + }; + gpio195ol_pins: gpio195ol-pins { + pins = "GPIO195/SMB0BSDA"; + bias-disable; + output-low; + }; + gpio196ol_pins: gpio196ol-pins { + pins = "GPIO196/SMB0CSCL"; + bias-disable; + output-low; + }; + gpio199i_pins: gpio199i-pins { + pins = "GPIO199/SMB0DSCL"; + bias-disable; + input-enable; + }; + gpio202ol_pins: gpio202ol-pins { + pins = "GPIO202/SMB0CSDA"; + bias-disable; + output-low; + }; + }; +}; + +&gmac0 { + phy-mode = "rgmii-id"; + snps,eee-force-disable; + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&fiu0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0cs1_pins>; + status = "okay"; + spi-nor@0 { + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0>; + spi-max-frequency = <5000000>; + spi-rx-bus-width = <2>; + label = "bmc"; + partitions@80000000 { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + u-boot@0 { + label = "u-boot"; + reg = <0x0000000 0xC0000>; + read-only; + }; + u-boot-env@100000{ + label = "u-boot-env"; + reg = <0x00100000 0x40000>; + }; + kernel@200000 { + label = "kernel"; + reg = <0x0200000 0x600000>; + }; + rofs@800000 { + label = "rofs"; + reg = <0x800000 0x3500000>; + }; + rwfs@3d00000 { + label = "rwfs"; + reg = <0x3d00000 0x300000>; + }; + }; + }; + spi-nor@1 { + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + reg = <1>; + spi-max-frequency = <5000000>; + spi-rx-bus-width = <2>; + partitions@88000000 { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + spare1@0 { + label = "spi0-cs1-spare1"; + reg = <0x0 0x800000>; + }; + spare2@800000 { + label = "spi0-cs1-spare2"; + reg = <0x800000 0x0>; + }; + }; + }; +}; + +&fiu3 { + pinctrl-0 = <&spi3_pins>; + spi-nor@0 { + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0>; + spi-max-frequency = <5000000>; + spi-rx-bus-width = <2>; + partitions@A0000000 { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + system1@0 { + label = "bios"; + reg = <0x0 0x0>; + }; + system2@800000 { + label = "spi3-system2"; + reg = <0x800000 0x0>; + }; + }; + }; +}; + +&watchdog1 { + status = "okay"; +}; + +&rng { + status = "okay"; +}; + +&serial0 { + status = "okay"; +}; + +&serial1 { + status = "okay"; +}; + +&serial2 { + status = "okay"; +}; + +&serial3 { + status = "okay"; +}; + +&adc { + #io-channel-cells = <1>; + status = "okay"; +}; + +&i2c1 { + status = "okay"; + i2c-switch@75 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x75>; + i2c-mux-idle-disconnect; + + i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + + // Rear-Fan + max31790@58 { + compatible = "maxim,max31790"; + reg = <0x58>; + }; + }; + + i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + + // Mid-Fan + max31790@58 { + compatible = "maxim,max31790"; + reg = <0x58>; + }; + }; + + i2c-bus@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + + // INLET1_T + lm75@5c { + compatible = "ti,lm75"; + reg = <0x5c>; + }; + }; + + i2c-bus@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + + // OUTLET1_T + lm75@5c { + compatible = "ti,lm75"; + reg = <0x5c>; + }; + }; + + i2c-bus@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + + // OUTLET2_T + lm75@5c { + compatible = "ti,lm75"; + reg = <0x5c>; + }; + }; + + i2c-bus@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + + // OUTLET3_T + lm75@5c { + compatible = "ti,lm75"; + reg = <0x5c>; + }; + }; + }; + i2c-switch@77 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x77>; + i2c-mux-idle-disconnect; + + i2c-bus@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + + // STB-T + pmbus@74 { + compatible = "pmbus"; + reg = <0x74>; + }; + }; + }; +}; + +&i2c2 { + status = "okay"; + smpro@4f { + compatible = "ampere,smpro"; + reg = <0x4f>; + }; + + smpro@4e { + compatible = "ampere,smpro"; + reg = <0x4e>; + }; +}; + +&i2c3 { + status = "okay"; +}; + +&i2c4 { + status = "okay"; + i2c-switch@77 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x77>; + i2c-mux-idle-disconnect; + + i2c-bus@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + // ADC sensors + adm1266@40 { + compatible = "adi,adm1266"; + reg = <0x40>; + }; + }; + + i2c-bus@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + // ADC sensors + adm1266@41 { + compatible = "adi,adm1266"; + reg = <0x41>; + }; + }; + }; +}; + +&i2c5 { + status = "okay"; +}; + +&i2c6 { + status = "okay"; +}; + +&i2c7 { + status = "okay"; +}; + +&i2c8 { + status = "okay"; +}; + +&i2c9 { + status = "okay"; +}; + +&i2c10 { + status = "okay"; +}; + +&i2c11 { + status = "okay"; +}; + +&i2c12 { + status = "okay"; + ssif-bmc@10 { + compatible = "ssif-bmc"; + reg = <0x10>; + }; +}; + +&i2c13 { + status = "okay"; + i2c-switch@77 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x77>; + i2c-mux-idle-disconnect; + + i2c-bus@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + + // M2_ZONE_T + lm75@28 { + compatible = "ti,lm75"; + reg = <0x28>; + }; + }; + + i2c-bus@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + + // BATT_ZONE_T + lm75@29 { + compatible = "ti,lm75"; + reg = <0x29>; + }; + }; + + i2c-bus@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + + // NBM1_ZONE_T + lm75@28 { + compatible = "ti,lm75"; + reg = <0x28>; + }; + }; + i2c-bus@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + + // NBM2_ZONE_T + lm75@29 { + compatible = "ti,lm75"; + reg = <0x29>; + }; + }; + }; +}; + +&i2c14 { + status = "okay"; +}; + +&i2c15 { + status = "okay"; +}; + +&spi0 { + cs-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&pinctrl { + pinctrl-names = "default"; + pinctrl-0 = < + &gpio61oh_pins + &gpio62oh_pins + &gpio161ol_pins + &gpio163i_pins + &gpio167ol_pins + &gpio95i_pins + &gpio65ol_pins + &gpio66oh_pins + &gpio67oh_pins + &gpio68ol_pins + &gpio69i_pins + &gpio70ol_pins + &gpio71i_pins + &gpio72i_pins + &gpio73i_pins + &gpio74i_pins + &gpio75i_pins + &gpio76i_pins + &gpio77i_pins + &gpio78i_pins + &gpio79ol_pins + &gpio80oh_pins + &gpio81i_pins + &gpio82i_pins + &gpio83i_pins + &gpio144i_pins + &gpio145i_pins + &gpio146i_pins + &gpio147oh_pins + &gpio168ol_pins + &gpio169oh_pins + &gpio170ol_pins + &gpio218oh_pins + &gpio37i_pins + &gpio38i_pins + &gpio39i_pins + &gpio40i_pins + &gpio121i_pins + &gpio122i_pins + &gpio123i_pins + &gpio124i_pins + &gpio125i_pins + &gpio126i_pins + &gpio127i_pins + &gpio136i_pins + &gpio137oh_pins + &gpio138i_pins + &gpio139i_pins + &gpio140i_pins + &gpio141i_pins + &gpio190oh_pins + &gpio191oh_pins + &gpio195ol_pins + &gpio196ol_pins + &gpio199i_pins + &gpio202ol_pins + >; +}; + +&gcr { + serial_port_mux: mux-controller { + compatible = "mmio-mux"; + #mux-control-cells = <1>; + + mux-reg-masks = <0x38 0x07>; + idle-states = <2>; + }; +}; -- cgit v1.2.3-59-g8ed1b From 3c5902d270edb6ccc3049acfe5d3e96653c87dcd Mon Sep 17 00:00:00 2001 From: Youling Tang Date: Sat, 14 Nov 2020 12:06:58 +0800 Subject: ARM: OMAP2+: Fix memleak in omap2xxx_clkt_vps_init If the clk_register fails, we should free hw before function returns to prevent memleak. Signed-off-by: Youling Tang Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c index 2a3e72286d3a..70892b3da28d 100644 --- a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c +++ b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c @@ -244,6 +244,12 @@ void omap2xxx_clkt_vps_init(void) hw->hw.init = &init; clk = clk_register(NULL, &hw->hw); + if (IS_ERR(clk)) { + printk(KERN_ERR "Failed to register clock\n"); + kfree(hw); + return; + } + clkdev_create(clk, "cpufreq_ck", NULL); return; cleanup: -- cgit v1.2.3-59-g8ed1b From c3f244d5776ecd236657fc1c4b7c5d1d4d01ca7e Mon Sep 17 00:00:00 2001 From: Youling Tang Date: Sat, 14 Nov 2020 12:07:20 +0800 Subject: ARM: OMAP2+: Fix kfree NULL pointer in omap2xxx_clkt_vps_init The returns pointer is NULL when kzalloc fails to apply for space, so fix kfree NULL pointer. Signed-off-by: Youling Tang Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c index 70892b3da28d..edf046b470ba 100644 --- a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c +++ b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c @@ -235,7 +235,7 @@ void omap2xxx_clkt_vps_init(void) hw = kzalloc(sizeof(*hw), GFP_KERNEL); if (!hw) - goto cleanup; + return; init.name = "virt_prcm_set"; init.ops = &virt_prcm_set_ops; init.parent_names = &parent_name; @@ -251,8 +251,5 @@ void omap2xxx_clkt_vps_init(void) } clkdev_create(clk, "cpufreq_ck", NULL); - return; -cleanup: - kfree(hw); } #endif -- cgit v1.2.3-59-g8ed1b From 6d9be9376b0e29211b6e6c1775ba6f81fb6c4ea5 Mon Sep 17 00:00:00 2001 From: Jing Xiangfeng Date: Sat, 19 Sep 2020 11:43:31 +0800 Subject: ARM: OMAP2+: Remove redundant assignment to variable ret The variable ret has been initialized with '-ENOMEM'. The assignment in the if branch is redundant. So remove it. Signed-off-by: Jing Xiangfeng Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/omap_device.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-omap2/omap_device.c b/arch/arm/mach-omap2/omap_device.c index fc7bb2ca1672..f3191704cab9 100644 --- a/arch/arm/mach-omap2/omap_device.c +++ b/arch/arm/mach-omap2/omap_device.c @@ -334,10 +334,9 @@ struct omap_device *omap_device_alloc(struct platform_device *pdev, struct omap_hwmod **hwmods; od = kzalloc(sizeof(struct omap_device), GFP_KERNEL); - if (!od) { - ret = -ENOMEM; + if (!od) goto oda_exit1; - } + od->hwmods_cnt = oh_cnt; hwmods = kmemdup(ohs, sizeof(struct omap_hwmod *) * oh_cnt, GFP_KERNEL); -- cgit v1.2.3-59-g8ed1b From e106698cbb901d9b74dea4c9a3b5a7e6598ae481 Mon Sep 17 00:00:00 2001 From: Xu Wang Date: Wed, 4 Nov 2020 06:45:05 +0000 Subject: ARM: OMAP2+: Remove redundant null check before clk_prepare_enable/clk_disable_unprepare Because clk_prepare_enable() and clk_disable_unprepare() already checked NULL clock parameter, so the additional checks are unnecessary, just remove them. Signed-off-by: Xu Wang Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/display.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-omap2/display.c b/arch/arm/mach-omap2/display.c index 2000fca6bd4e..6daaa645ae5d 100644 --- a/arch/arm/mach-omap2/display.c +++ b/arch/arm/mach-omap2/display.c @@ -385,8 +385,7 @@ int omap_dss_reset(struct omap_hwmod *oh) } for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++) - if (oc->_clk) - clk_prepare_enable(oc->_clk); + clk_prepare_enable(oc->_clk); dispc_disable_outputs(); @@ -412,8 +411,7 @@ int omap_dss_reset(struct omap_hwmod *oh) pr_debug("dss_core: softreset done\n"); for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++) - if (oc->_clk) - clk_disable_unprepare(oc->_clk); + clk_disable_unprepare(oc->_clk); r = (c == MAX_MODULE_SOFTRESET_WAIT) ? -ETIMEDOUT : 0; -- cgit v1.2.3-59-g8ed1b From 2e023b938048c9857af09b96ce672e9a31dbfb38 Mon Sep 17 00:00:00 2001 From: Tang Bin Date: Thu, 10 Sep 2020 19:06:40 +0800 Subject: ARM: OMAP1: clock: Use IS_ERR_OR_NULL() to clean code Use IS_ERR_OR_NULL() to make the code cleaner. Signed-off-by: Zhang Shengju Signed-off-by: Tang Bin Signed-off-by: Tony Lindgren --- arch/arm/mach-omap1/clock.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-omap1/clock.c b/arch/arm/mach-omap1/clock.c index bd5be82101f3..9d4a0ab50a46 100644 --- a/arch/arm/mach-omap1/clock.c +++ b/arch/arm/mach-omap1/clock.c @@ -612,7 +612,7 @@ int clk_enable(struct clk *clk) unsigned long flags; int ret; - if (clk == NULL || IS_ERR(clk)) + if (IS_ERR_OR_NULL(clk)) return -EINVAL; spin_lock_irqsave(&clockfw_lock, flags); @@ -627,7 +627,7 @@ void clk_disable(struct clk *clk) { unsigned long flags; - if (clk == NULL || IS_ERR(clk)) + if (IS_ERR_OR_NULL(clk)) return; spin_lock_irqsave(&clockfw_lock, flags); @@ -650,7 +650,7 @@ unsigned long clk_get_rate(struct clk *clk) unsigned long flags; unsigned long ret; - if (clk == NULL || IS_ERR(clk)) + if (IS_ERR_OR_NULL(clk)) return 0; spin_lock_irqsave(&clockfw_lock, flags); @@ -670,7 +670,7 @@ long clk_round_rate(struct clk *clk, unsigned long rate) unsigned long flags; long ret; - if (clk == NULL || IS_ERR(clk)) + if (IS_ERR_OR_NULL(clk)) return 0; spin_lock_irqsave(&clockfw_lock, flags); @@ -686,7 +686,7 @@ int clk_set_rate(struct clk *clk, unsigned long rate) unsigned long flags; int ret = -EINVAL; - if (clk == NULL || IS_ERR(clk)) + if (IS_ERR_OR_NULL(clk)) return ret; spin_lock_irqsave(&clockfw_lock, flags); @@ -791,7 +791,7 @@ void clk_preinit(struct clk *clk) int clk_register(struct clk *clk) { - if (clk == NULL || IS_ERR(clk)) + if (IS_ERR_OR_NULL(clk)) return -EINVAL; /* @@ -817,7 +817,7 @@ EXPORT_SYMBOL(clk_register); void clk_unregister(struct clk *clk) { - if (clk == NULL || IS_ERR(clk)) + if (IS_ERR_OR_NULL(clk)) return; mutex_lock(&clocks_mutex); -- cgit v1.2.3-59-g8ed1b From bb74fdbd8a6c4eb6da18cef9c65da755b4ae5bcb Mon Sep 17 00:00:00 2001 From: Eddie James Date: Mon, 2 Nov 2020 13:47:13 -0600 Subject: ARM: dts: aspeed: rainier: Mark FSI SPI controllers as restricted Some of the FSI-attached SPI controllers can't use the loop command due to security requirements. Indicate this in the devicetree with the restricted compatible string. Signed-off-by: Eddie James Link: https://lore.kernel.org/r/20201102194713.14812-1-eajames@linux.ibm.com Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts b/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts index 63123bf137e3..4985473a3e2d 100644 --- a/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts +++ b/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts @@ -267,6 +267,7 @@ cfam0_spi2: spi@40 { reg = <0x40>; + compatible = "ibm,fsi2spi-restricted"; #address-cells = <1>; #size-cells = <0>; @@ -283,6 +284,7 @@ cfam0_spi3: spi@60 { reg = <0x60>; + compatible = "ibm,fsi2spi-restricted"; #address-cells = <1>; #size-cells = <0>; @@ -379,6 +381,7 @@ cfam1_spi2: spi@40 { reg = <0x40>; + compatible = "ibm,fsi2spi-restricted"; #address-cells = <1>; #size-cells = <0>; @@ -395,6 +398,7 @@ cfam1_spi3: spi@60 { reg = <0x60>; + compatible = "ibm,fsi2spi-restricted"; #address-cells = <1>; #size-cells = <0>; @@ -489,6 +493,7 @@ cfam2_spi2: spi@40 { reg = <0x40>; + compatible = "ibm,fsi2spi-restricted"; #address-cells = <1>; #size-cells = <0>; @@ -505,6 +510,7 @@ cfam2_spi3: spi@60 { reg = <0x60>; + compatible = "ibm,fsi2spi-restricted"; #address-cells = <1>; #size-cells = <0>; -- cgit v1.2.3-59-g8ed1b From c680dd4e60456305434bb6babc36804d1301e0ff Mon Sep 17 00:00:00 2001 From: Andrew Jeffery Date: Fri, 2 Oct 2020 16:04:14 +0930 Subject: ARM: dts: aspeed: rainier: Don't shout addresses Make them lowercase. Signed-off-by: Andrew Jeffery Reviewed-by: Joel Stanley Link: https://lore.kernel.org/r/20201002063414.275161-4-andrew@aj.id.au Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts b/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts index 4985473a3e2d..a4b77aec5424 100644 --- a/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts +++ b/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts @@ -47,9 +47,9 @@ #size-cells = <1>; ranges; - flash_memory: region@B8000000 { + flash_memory: region@b8000000 { no-map; - reg = <0xB8000000 0x04000000>; /* 64M */ + reg = <0xb8000000 0x04000000>; /* 64M */ }; ramoops@bc000000 { -- cgit v1.2.3-59-g8ed1b From 2ba56f464f0c1a7264160f8675063b3df92e7966 Mon Sep 17 00:00:00 2001 From: Joel Stanley Date: Thu, 11 Jun 2020 11:04:33 +0930 Subject: ARM: dts: aspeed: ast2600evb: Add MAC0 MAC0 was not functional in the AST2600A0 SoC. This has been resolved with the A1, so allow use of this port on EVBs with the A1 and subsequent revisions. A0 EVBs will still boot with this change, but the first Ethernet device will not be functional. Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-ast2600-evb.dts | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/aspeed-ast2600-evb.dts b/arch/arm/boot/dts/aspeed-ast2600-evb.dts index 8d0f4656aa05..89be13197780 100644 --- a/arch/arm/boot/dts/aspeed-ast2600-evb.dts +++ b/arch/arm/boot/dts/aspeed-ast2600-evb.dts @@ -23,6 +23,15 @@ }; }; +&mdio0 { + status = "okay"; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; +}; + &mdio1 { status = "okay"; @@ -50,6 +59,17 @@ }; }; +&mac0 { + status = "okay"; + + phy-mode = "rgmii"; + phy-handle = <ðphy0>; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgmii1_default>; +}; + + &mac1 { status = "okay"; -- cgit v1.2.3-59-g8ed1b From 6d4b65e31a3fce0943801248637fd72b14ca6e69 Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Thu, 12 Nov 2020 14:21:52 +0200 Subject: ARM: dts: omap4: add remaining PRM instances Add remaining PRM instances for the omap4 SoC. Additionally enable the genpd support for them. Signed-off-by: Tero Kristo Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap4.dtsi | 63 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 63 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi index d6475cc6a91a..6663c721c4a5 100644 --- a/arch/arm/boot/dts/omap4.dtsi +++ b/arch/arm/boot/dts/omap4.dtsi @@ -658,10 +658,17 @@ #include "omap44xx-clocks.dtsi" &prm { + prm_mpu: prm@300 { + compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst"; + reg = <0x300 0x100>; + #power-domain-cells = <0>; + }; + prm_tesla: prm@400 { compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst"; reg = <0x400 0x100>; #reset-cells = <1>; + #power-domain-cells = <0>; }; prm_abe: prm@500 { @@ -670,16 +677,72 @@ #power-domain-cells = <0>; }; + prm_always_on_core: prm@600 { + compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst"; + reg = <0x600 0x100>; + #power-domain-cells = <0>; + }; + prm_core: prm@700 { compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst"; reg = <0x700 0x100>; #reset-cells = <1>; + #power-domain-cells = <0>; }; prm_ivahd: prm@f00 { compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst"; reg = <0xf00 0x100>; #reset-cells = <1>; + #power-domain-cells = <0>; + }; + + prm_cam: prm@1000 { + compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst"; + reg = <0x1000 0x100>; + #power-domain-cells = <0>; + }; + + prm_dss: prm@1100 { + compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst"; + reg = <0x1100 0x100>; + #power-domain-cells = <0>; + }; + + prm_gfx: prm@1200 { + compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst"; + reg = <0x1200 0x100>; + #power-domain-cells = <0>; + }; + + prm_l3init: prm@1300 { + compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst"; + reg = <0x1300 0x100>; + #power-domain-cells = <0>; + }; + + prm_l4per: prm@1400 { + compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst"; + reg = <0x1400 0x100>; + #power-domain-cells = <0>; + }; + + prm_cefuse: prm@1600 { + compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst"; + reg = <0x1600 0x100>; + #power-domain-cells = <0>; + }; + + prm_wkup: prm@1700 { + compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst"; + reg = <0x1700 0x100>; + #power-domain-cells = <0>; + }; + + prm_emu: prm@1900 { + compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst"; + reg = <0x1900 0x100>; + #power-domain-cells = <0>; }; prm_device: prm@1b00 { -- cgit v1.2.3-59-g8ed1b From 0c7815f306e3f3f836b846976352bd886dfb9fce Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Thu, 19 Nov 2020 14:18:08 +0200 Subject: ARM: dts: Configure power domain for omap4 dss This allows shutting down dss domain when the screen blanks. Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap4.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi index 6663c721c4a5..b5859350660b 100644 --- a/arch/arm/boot/dts/omap4.dtsi +++ b/arch/arm/boot/dts/omap4.dtsi @@ -445,6 +445,7 @@ <0x58000014 4>; reg-names = "rev", "syss"; ti,syss-mask = <1>; + power-domains = <&prm_dss>; clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 0>, <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 9>, <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>, @@ -745,6 +746,12 @@ #power-domain-cells = <0>; }; + prm_dss: prm@1100 { + compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst"; + reg = <0x1100 0x40>; + #power-domain-cells = <0>; + }; + prm_device: prm@1b00 { compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst"; reg = <0x1b00 0x40>; -- cgit v1.2.3-59-g8ed1b From 399882c1997509e2c2dcfe05e3491e2480be3e63 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Thu, 19 Nov 2020 14:18:45 +0200 Subject: ARM: dts: Configure power domain for omap4 dsp This allows shutting down the dsp domain when not in use. Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap4-l4.dtsi | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/omap4-l4.dtsi b/arch/arm/boot/dts/omap4-l4.dtsi index de742bf84efb..e0bb60a30779 100644 --- a/arch/arm/boot/dts/omap4-l4.dtsi +++ b/arch/arm/boot/dts/omap4-l4.dtsi @@ -330,6 +330,7 @@ /* Domains (V, P, C): iva, tesla_pwrdm, tesla_clkdm */ clocks = <&tesla_clkctrl OMAP4_DSP_CLKCTRL 0>; clock-names = "fck"; + power-domains = <&prm_tesla>; resets = <&prm_tesla 1>; reset-names = "rstctrl"; #address-cells = <1>; -- cgit v1.2.3-59-g8ed1b From dfdaf8643e4e24e1876f279c81d9a1baea0af981 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Thu, 19 Nov 2020 14:18:54 +0200 Subject: ARM: OMAP2+: Drop legacy platform data for omap4 iva We can now probe devices with ti-sysc interconnect driver and dts data. Let's drop the related platform data and custom ti,hwmods dts property. Cc: Suman Anna Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap4.dtsi | 31 +++++++++++--- arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 69 ------------------------------ 2 files changed, 26 insertions(+), 74 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi index b5859350660b..402666e19c8d 100644 --- a/arch/arm/boot/dts/omap4.dtsi +++ b/arch/arm/boot/dts/omap4.dtsi @@ -107,11 +107,6 @@ ti,hwmods = "mpu"; sram = <&ocmcram>; }; - - iva { - compatible = "ti,ivahd"; - ti,hwmods = "iva"; - }; }; /* @@ -651,6 +646,32 @@ }; }; }; + + iva_hd_target: target-module@5a000000 { + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x5a05a400 0x4>, + <0x5a05a410 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-midle = , + , + ; + ti,sysc-sidle = , + , + ; + power-domains = <&prm_ivahd>; + resets = <&prm_ivahd 2>; + reset-names = "rstctrl"; + clocks = <&ivahd_clkctrl OMAP4_IVA_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x5a000000 0x5a000000 0x1000000>, + <0x5b000000 0x5b000000 0x1000000>; + + iva { + compatible = "ti,ivahd"; + }; + }; }; }; diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c index 37c59115b353..7162754252e5 100644 --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c @@ -440,39 +440,6 @@ static struct omap_hwmod omap44xx_iss_hwmod = { .opt_clks_cnt = ARRAY_SIZE(iss_opt_clks), }; -/* - * 'iva' class - * multi-standard video encoder/decoder hardware accelerator - */ - -static struct omap_hwmod_class omap44xx_iva_hwmod_class = { - .name = "iva", -}; - -/* iva */ -static struct omap_hwmod_rst_info omap44xx_iva_resets[] = { - { .name = "seq0", .rst_shift = 0 }, - { .name = "seq1", .rst_shift = 1 }, - { .name = "logic", .rst_shift = 2 }, -}; - -static struct omap_hwmod omap44xx_iva_hwmod = { - .name = "iva", - .class = &omap44xx_iva_hwmod_class, - .clkdm_name = "ivahd_clkdm", - .rst_lines = omap44xx_iva_resets, - .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_resets), - .main_clk = "dpll_iva_m5x2_ck", - .prcm = { - .omap4 = { - .clkctrl_offs = OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET, - .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET, - .context_offs = OMAP4_RM_IVAHD_IVAHD_CONTEXT_OFFSET, - .modulemode = MODULEMODE_HWCTRL, - }, - }, -}; - /* * 'mpu' class * mpu sub-system @@ -644,14 +611,6 @@ static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = { .user = OCP_USER_MPU, }; -/* iva -> l3_instr */ -static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = { - .master = &omap44xx_iva_hwmod, - .slave = &omap44xx_l3_instr_hwmod, - .clk = "l3_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - /* l3_main_3 -> l3_instr */ static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = { .master = &omap44xx_l3_main_3_hwmod, @@ -708,14 +667,6 @@ static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2 = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; -/* iva -> l3_main_2 */ -static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = { - .master = &omap44xx_iva_hwmod, - .slave = &omap44xx_l3_main_2_hwmod, - .clk = "l3_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - /* l3_main_1 -> l3_main_2 */ static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = { .master = &omap44xx_l3_main_1_hwmod, @@ -852,22 +803,6 @@ static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; -/* iva -> sl2if */ -static struct omap_hwmod_ocp_if __maybe_unused omap44xx_iva__sl2if = { - .master = &omap44xx_iva_hwmod, - .slave = &omap44xx_sl2if_hwmod, - .clk = "dpll_iva_m5x2_ck", - .user = OCP_USER_IVA, -}; - -/* l3_main_2 -> iva */ -static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = { - .master = &omap44xx_l3_main_2_hwmod, - .slave = &omap44xx_iva_hwmod, - .clk = "l3_div_ck", - .user = OCP_USER_MPU, -}; - /* l3_main_2 -> ocmc_ram */ static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ocmc_ram = { .master = &omap44xx_l3_main_2_hwmod, @@ -943,7 +878,6 @@ static struct omap_hwmod_ocp_if omap44xx_mpu__emif2 = { static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = { &omap44xx_l3_main_1__dmm, &omap44xx_mpu__dmm, - &omap44xx_iva__l3_instr, &omap44xx_l3_main_3__l3_instr, &omap44xx_ocp_wp_noc__l3_instr, &omap44xx_l3_main_2__l3_main_1, @@ -951,7 +885,6 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = { &omap44xx_mpu__l3_main_1, &omap44xx_debugss__l3_main_2, &omap44xx_iss__l3_main_2, - &omap44xx_iva__l3_main_2, &omap44xx_l3_main_1__l3_main_2, &omap44xx_l4_cfg__l3_main_2, &omap44xx_l3_main_1__l3_main_3, @@ -969,8 +902,6 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = { &omap44xx_l3_instr__debugss, &omap44xx_l3_main_2__gpmc, &omap44xx_l3_main_2__iss, - /* &omap44xx_iva__sl2if, */ - &omap44xx_l3_main_2__iva, &omap44xx_l3_main_2__ocmc_ram, &omap44xx_mpu_private__prcm_mpu, &omap44xx_l4_wkup__cm_core_aon, -- cgit v1.2.3-59-g8ed1b From fb0bf6aa8d5bd673d294b0b21b7c871d0308ae87 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Thu, 19 Nov 2020 14:19:01 +0200 Subject: ARM: OMAP2+: Drop legacy platform data for omap4 gpmc We can now probe devices with ti-sysc interconnect driver and dts data. Let's drop the related platform data and custom ti,hwmods dts property. Cc: Roger Quadros Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap4.dtsi | 49 ++++++++++++++++++++---------- arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 45 --------------------------- 2 files changed, 33 insertions(+), 61 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi index 402666e19c8d..72e4f6481776 100644 --- a/arch/arm/boot/dts/omap4.dtsi +++ b/arch/arm/boot/dts/omap4.dtsi @@ -145,24 +145,41 @@ reg = <0x40304000 0xa000>; /* 40k */ }; - gpmc: gpmc@50000000 { - compatible = "ti,omap4430-gpmc"; - reg = <0x50000000 0x1000>; - #address-cells = <2>; - #size-cells = <1>; - interrupts = ; - dmas = <&sdma 4>; - dma-names = "rxtx"; - gpmc,num-cs = <8>; - gpmc,num-waitpins = <4>; - ti,hwmods = "gpmc"; + target-module@50000000 { + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x50000000 4>, + <0x50000010 4>, + <0x50000014 4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-sidle = , + , + ; + ti,syss-mask = <1>; ti,no-idle-on-init; - clocks = <&l3_div_ck>; + clocks = <&l3_2_clkctrl OMAP4_GPMC_CLKCTRL 0>; clock-names = "fck"; - interrupt-controller; - #interrupt-cells = <2>; - gpio-controller; - #gpio-cells = <2>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x50000000 0x50000000 0x00001000>, /* regs */ + <0x00000000 0x00000000 0x40000000>; /* data */ + + gpmc: gpmc@50000000 { + compatible = "ti,omap4430-gpmc"; + reg = <0x50000000 0x1000>; + #address-cells = <2>; + #size-cells = <1>; + interrupts = ; + dmas = <&sdma 4>; + dma-names = "rxtx"; + gpmc,num-cs = <8>; + gpmc,num-waitpins = <4>; + clocks = <&l3_div_ck>; + clock-names = "fck"; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + }; }; target-module@52000000 { diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c index 7162754252e5..6aa3b8e81a0c 100644 --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c @@ -353,42 +353,6 @@ static struct omap_hwmod omap44xx_emif2_hwmod = { }, }; -/* - * 'gpmc' class - * general purpose memory controller - */ - -static struct omap_hwmod_class_sysconfig omap44xx_gpmc_sysc = { - .rev_offs = 0x0000, - .sysc_offs = 0x0010, - .syss_offs = 0x0014, - .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE | - SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), - .sysc_fields = &omap_hwmod_sysc_type1, -}; - -static struct omap_hwmod_class omap44xx_gpmc_hwmod_class = { - .name = "gpmc", - .sysc = &omap44xx_gpmc_sysc, -}; - -/* gpmc */ -static struct omap_hwmod omap44xx_gpmc_hwmod = { - .name = "gpmc", - .class = &omap44xx_gpmc_hwmod_class, - .clkdm_name = "l3_2_clkdm", - /* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */ - .flags = DEBUG_OMAP_GPMC_HWMOD_FLAGS, - .prcm = { - .omap4 = { - .clkctrl_offs = OMAP4_CM_L3_2_GPMC_CLKCTRL_OFFSET, - .context_offs = OMAP4_RM_L3_2_GPMC_CONTEXT_OFFSET, - .modulemode = MODULEMODE_HWCTRL, - }, - }, -}; - /* * 'iss' class * external images sensor pixel data processor @@ -787,14 +751,6 @@ static struct omap_hwmod_ocp_if omap44xx_l3_instr__debugss = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; -/* l3_main_2 -> gpmc */ -static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpmc = { - .master = &omap44xx_l3_main_2_hwmod, - .slave = &omap44xx_gpmc_hwmod, - .clk = "l3_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - /* l3_main_2 -> iss */ static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = { .master = &omap44xx_l3_main_2_hwmod, @@ -900,7 +856,6 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = { &omap44xx_l4_wkup__ctrl_module_wkup, &omap44xx_l4_wkup__ctrl_module_pad_wkup, &omap44xx_l3_instr__debugss, - &omap44xx_l3_main_2__gpmc, &omap44xx_l3_main_2__iss, &omap44xx_l3_main_2__ocmc_ram, &omap44xx_mpu_private__prcm_mpu, -- cgit v1.2.3-59-g8ed1b From 1021b37ecdc83d494846923abe1b381b1f494fa4 Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Wed, 11 Nov 2020 15:57:20 +0200 Subject: ARM: dts: dra7: add remaining PRM instances Add remaining PRM instances for the dra7 SoC. Additionally enable the genpd support for them. Signed-off-by: Tero Kristo Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/dra7.dtsi | 76 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 76 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index 4e1bbc0198eb..07d19bba1443 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -1031,53 +1031,129 @@ #include "dra7xx-clocks.dtsi" &prm { + prm_mpu: prm@300 { + compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; + reg = <0x300 0x100>; + #power-domain-cells = <0>; + }; + prm_dsp1: prm@400 { compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; reg = <0x400 0x100>; #reset-cells = <1>; + #power-domain-cells = <0>; }; prm_ipu: prm@500 { compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; reg = <0x500 0x100>; #reset-cells = <1>; + #power-domain-cells = <0>; + }; + + prm_coreaon: prm@628 { + compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; + reg = <0x628 0xd8>; + #power-domain-cells = <0>; }; prm_core: prm@700 { compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; reg = <0x700 0x100>; #reset-cells = <1>; + #power-domain-cells = <0>; }; prm_iva: prm@f00 { compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; reg = <0xf00 0x100>; + #power-domain-cells = <0>; + }; + + prm_cam: prm@1000 { + compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; + reg = <0x1000 0x100>; + #power-domain-cells = <0>; + }; + + prm_dss: prm@1100 { + compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; + reg = <0x1100 0x100>; + #power-domain-cells = <0>; + }; + + prm_gpu: prm@1200 { + compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; + reg = <0x1200 0x100>; + #power-domain-cells = <0>; + }; + + prm_l3init: prm@1300 { + compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; + reg = <0x1300 0x100>; + #reset-cells = <1>; + #power-domain-cells = <0>; + }; + + prm_l4per: prm@1400 { + compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; + reg = <0x1400 0x100>; + #power-domain-cells = <0>; + }; + + prm_custefuse: prm@1600 { + compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; + reg = <0x1600 0x100>; + #power-domain-cells = <0>; + }; + + prm_wkupaon: prm@1724 { + compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; + reg = <0x1724 0x100>; + #power-domain-cells = <0>; }; prm_dsp2: prm@1b00 { compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; reg = <0x1b00 0x40>; #reset-cells = <1>; + #power-domain-cells = <0>; }; prm_eve1: prm@1b40 { compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; reg = <0x1b40 0x40>; + #power-domain-cells = <0>; }; prm_eve2: prm@1b80 { compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; reg = <0x1b80 0x40>; + #power-domain-cells = <0>; }; prm_eve3: prm@1bc0 { compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; reg = <0x1bc0 0x40>; + #power-domain-cells = <0>; }; prm_eve4: prm@1c00 { compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; reg = <0x1c00 0x60>; + #power-domain-cells = <0>; + }; + + prm_rtc: prm@1c60 { + compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; + reg = <0x1c60 0x20>; + #power-domain-cells = <0>; + }; + + prm_vpe: prm@1c80 { + compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; + reg = <0x1c80 0x80>; + #power-domain-cells = <0>; }; }; -- cgit v1.2.3-59-g8ed1b From ae57d1558908aa797437a45e3c8f91712d2c3114 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Thu, 12 Nov 2020 11:57:03 +0200 Subject: ARM: dts: Configure interconnect target module for dra7 iva We can now probe devices with device tree only configuration using ti-sysc interconnect target module driver. Cc: Suman Anna Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/dra7.dtsi | 27 +++++++++++++++++++++++++++ arch/arm/boot/dts/dra7xx-clocks.dtsi | 14 ++++++++++++++ 2 files changed, 41 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index 07d19bba1443..82e98d4ab1f2 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -962,6 +962,32 @@ }; }; + iva_hd_target: target-module@5a000000 { + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x5a05a400 0x4>, + <0x5a05a410 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-midle = , + , + ; + ti,sysc-sidle = , + , + ; + power-domains = <&prm_iva>; + resets = <&prm_iva 2>; + reset-names = "rstctrl"; + clocks = <&iva_clkctrl DRA7_IVA_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x5a000000 0x5a000000 0x1000000>, + <0x5b000000 0x5b000000 0x1000000>; + + iva { + compatible = "ti,ivahd"; + }; + }; + opp_supply_mpu: opp-supply@4a003b20 { compatible = "ti,omap5-opp-supply"; reg = <0x4a003b20 0xc>; @@ -1067,6 +1093,7 @@ prm_iva: prm@f00 { compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst"; reg = <0xf00 0x100>; + #reset-cells = <1>; #power-domain-cells = <0>; }; diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi index dc0a93bccbf1..2365554eef3c 100644 --- a/arch/arm/boot/dts/dra7xx-clocks.dtsi +++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi @@ -1726,6 +1726,20 @@ }; }; + iva_cm: iva-cm@f00 { + compatible = "ti,omap4-cm"; + reg = <0xf00 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0xf00 0x100>; + + iva_clkctrl: iva-clkctrl@20 { + compatible = "ti,clkctrl"; + reg = <0x20 0xc>; + #clock-cells = <2>; + }; + }; + cam_cm: cam-cm@1000 { compatible = "ti,omap4-cm"; reg = <0x1000 0x100>; -- cgit v1.2.3-59-g8ed1b From 11fdf598d041e86972e4bd5ecef8968ffe641d1c Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Mon, 19 Oct 2020 10:45:58 +0300 Subject: ARM: OMAP2+: Drop legacy platform data for dra7 gpmc We can now probe devices with ti-sysc interconnect driver and dts data. Let's drop the related platform data and custom ti,hwmods dts property. Cc: Roger Quadros Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/dra7.dtsi | 48 ++++++++++++++++++++---------- arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 49 ------------------------------- 2 files changed, 33 insertions(+), 64 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index 82e98d4ab1f2..5508a7ff8f89 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -724,22 +724,40 @@ /* OCP2SCP1 */ /* IRQ for DWC3_3 and DWC3_4 need IRQ crossbar */ - gpmc: gpmc@50000000 { - compatible = "ti,am3352-gpmc"; - ti,hwmods = "gpmc"; - reg = <0x50000000 0x37c>; /* device IO registers */ - interrupts = ; - dmas = <&edma_xbar 4 0>; - dma-names = "rxtx"; - gpmc,num-cs = <8>; - gpmc,num-waitpins = <2>; - #address-cells = <2>; + + target-module@50000000 { + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x50000000 4>, + <0x50000010 4>, + <0x50000014 4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-sidle = , + , + ; + ti,syss-mask = <1>; + clocks = <&l3main1_clkctrl DRA7_L3MAIN1_GPMC_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; #size-cells = <1>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-controller; - #gpio-cells = <2>; - status = "disabled"; + ranges = <0x50000000 0x50000000 0x00001000>, /* regs */ + <0x00000000 0x00000000 0x40000000>; /* data */ + + gpmc: gpmc@50000000 { + compatible = "ti,am3352-gpmc"; + reg = <0x50000000 0x37c>; /* device IO registers */ + interrupts = ; + dmas = <&edma_xbar 4 0>; + dma-names = "rxtx"; + gpmc,num-cs = <8>; + gpmc,num-waitpins = <2>; + #address-cells = <2>; + #size-cells = <1>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + status = "disabled"; + }; }; target-module@56000000 { diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c index 05e163c8337a..48c2a808bd46 100644 --- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c @@ -242,46 +242,6 @@ static struct omap_hwmod dra7xx_ctrl_module_wkup_hwmod = { }, }; -/* - * 'gpmc' class - * - */ - -static struct omap_hwmod_class_sysconfig dra7xx_gpmc_sysc = { - .rev_offs = 0x0000, - .sysc_offs = 0x0010, - .syss_offs = 0x0014, - .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE | - SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), - .sysc_fields = &omap_hwmod_sysc_type1, -}; - -static struct omap_hwmod_class dra7xx_gpmc_hwmod_class = { - .name = "gpmc", - .sysc = &dra7xx_gpmc_sysc, -}; - -/* gpmc */ - -static struct omap_hwmod dra7xx_gpmc_hwmod = { - .name = "gpmc", - .class = &dra7xx_gpmc_hwmod_class, - .clkdm_name = "l3main1_clkdm", - /* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */ - .flags = DEBUG_OMAP_GPMC_HWMOD_FLAGS, - .main_clk = "l3_iclk_div", - .prcm = { - .omap4 = { - .clkctrl_offs = DRA7XX_CM_L3MAIN1_GPMC_CLKCTRL_OFFSET, - .context_offs = DRA7XX_RM_L3MAIN1_GPMC_CONTEXT_OFFSET, - .modulemode = MODULEMODE_HWCTRL, - }, - }, -}; - - - /* * 'mpu' class * @@ -611,14 +571,6 @@ static struct omap_hwmod_ocp_if dra7xx_l4_wkup__ctrl_module_wkup = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; -/* l3_main_1 -> gpmc */ -static struct omap_hwmod_ocp_if dra7xx_l3_main_1__gpmc = { - .master = &dra7xx_l3_main_1_hwmod, - .slave = &dra7xx_gpmc_hwmod, - .clk = "l3_iclk_div", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - /* l4_cfg -> mpu */ static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mpu = { .master = &dra7xx_l4_cfg_hwmod, @@ -722,7 +674,6 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = { &dra7xx_l4_per2__atl, &dra7xx_l3_main_1__bb2d, &dra7xx_l4_wkup__ctrl_module_wkup, - &dra7xx_l3_main_1__gpmc, &dra7xx_l4_cfg__mpu, &dra7xx_l3_main_1__pciess1, &dra7xx_l4_cfg__pciess1, -- cgit v1.2.3-59-g8ed1b From ee9ddfd78150d5af7da2b60fa0e920f1c5851fab Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Thu, 12 Nov 2020 10:59:11 +0200 Subject: ARM: dts: omap5: add remaining PRM instances Add remaining PRM instances for the omap5 SoC. Additionally enable the genpd support for them. Signed-off-by: Tero Kristo Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap5.dtsi | 57 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 57 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi index 2bf2e5839a7f..f8031121d1df 100644 --- a/arch/arm/boot/dts/omap5.dtsi +++ b/arch/arm/boot/dts/omap5.dtsi @@ -670,10 +670,17 @@ #include "omap54xx-clocks.dtsi" &prm { + prm_mpu: prm@300 { + compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst"; + reg = <0x300 0x100>; + #power-domain-cells = <0>; + }; + prm_dsp: prm@400 { compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst"; reg = <0x400 0x100>; #reset-cells = <1>; + #power-domain-cells = <0>; }; prm_abe: prm@500 { @@ -682,16 +689,66 @@ #power-domain-cells = <0>; }; + prm_coreaon: prm@600 { + compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst"; + reg = <0x600 0x100>; + #power-domain-cells = <0>; + }; + prm_core: prm@700 { compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst"; reg = <0x700 0x100>; #reset-cells = <1>; + #power-domain-cells = <0>; }; prm_iva: prm@1200 { compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst"; reg = <0x1200 0x100>; #reset-cells = <1>; + #power-domain-cells = <0>; + }; + + prm_cam: prm@1300 { + compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst"; + reg = <0x1300 0x100>; + #power-domain-cells = <0>; + }; + + prm_dss: prm@1400 { + compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst"; + reg = <0x1400 0x100>; + #power-domain-cells = <0>; + }; + + prm_gpu: prm@1500 { + compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst"; + reg = <0x1500 0x100>; + #power-domain-cells = <0>; + }; + + prm_l3init: prm@1600 { + compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst"; + reg = <0x1600 0x100>; + #power-domain-cells = <0>; + }; + + prm_custefuse: prm@1700 { + compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst"; + reg = <0x1700 0x100>; + #power-domain-cells = <0>; + }; + + prm_wkupaon: prm@1800 { + compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst"; + reg = <0x1800 0x100>; + #power-domain-cells = <0>; + }; + + prm_emu: prm@1a00 { + compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst"; + reg = <0x1a00 0x100>; + #power-domain-cells = <0>; }; prm_device: prm@1c00 { -- cgit v1.2.3-59-g8ed1b From baa2a611762f9ad033392d15efa3b5aeb5c69d50 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Thu, 19 Nov 2020 14:50:46 +0200 Subject: ARM: dts: Configure power domain for omap5 dss This allows shutting down dss domain when the screen blanks. Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap5.dtsi | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi index f8031121d1df..5f1a8bd13880 100644 --- a/arch/arm/boot/dts/omap5.dtsi +++ b/arch/arm/boot/dts/omap5.dtsi @@ -410,6 +410,7 @@ <0x58000014 4>; reg-names = "rev", "syss"; ti,syss-mask = <1>; + power-domains = <&prm_dss>; clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 0>, <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 9>, <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>, -- cgit v1.2.3-59-g8ed1b From a24d22b225ce158651378869a6b88105c4bdb887 Mon Sep 17 00:00:00 2001 From: Eric Biggers Date: Thu, 12 Nov 2020 21:20:21 -0800 Subject: crypto: sha - split sha.h into sha1.h and sha2.h Currently contains declarations for both SHA-1 and SHA-2, and contains declarations for SHA-3. This organization is inconsistent, but more importantly SHA-1 is no longer considered to be cryptographically secure. So to the extent possible, SHA-1 shouldn't be grouped together with any of the other SHA versions, and usage of it should be phased out. Therefore, split into two headers and , and make everyone explicitly specify whether they want the declarations for SHA-1, SHA-2, or both. This avoids making the SHA-1 declarations visible to files that don't want anything to do with SHA-1. It also prepares for potentially moving sha1.h into a new insecure/ or dangerous/ directory. Signed-off-by: Eric Biggers Acked-by: Ard Biesheuvel Acked-by: Jason A. Donenfeld Signed-off-by: Herbert Xu --- arch/arm/crypto/sha1-ce-glue.c | 2 +- arch/arm/crypto/sha1.h | 2 +- arch/arm/crypto/sha1_glue.c | 2 +- arch/arm/crypto/sha1_neon_glue.c | 2 +- arch/arm/crypto/sha2-ce-glue.c | 2 +- arch/arm/crypto/sha256_glue.c | 2 +- arch/arm/crypto/sha256_neon_glue.c | 2 +- arch/arm/crypto/sha512-glue.c | 2 +- arch/arm/crypto/sha512-neon-glue.c | 2 +- arch/arm64/crypto/aes-glue.c | 2 +- arch/arm64/crypto/sha1-ce-glue.c | 2 +- arch/arm64/crypto/sha2-ce-glue.c | 2 +- arch/arm64/crypto/sha256-glue.c | 2 +- arch/arm64/crypto/sha512-ce-glue.c | 2 +- arch/arm64/crypto/sha512-glue.c | 2 +- arch/mips/cavium-octeon/crypto/octeon-sha1.c | 2 +- arch/mips/cavium-octeon/crypto/octeon-sha256.c | 2 +- arch/mips/cavium-octeon/crypto/octeon-sha512.c | 2 +- arch/powerpc/crypto/sha1-spe-glue.c | 2 +- arch/powerpc/crypto/sha1.c | 2 +- arch/powerpc/crypto/sha256-spe-glue.c | 2 +- arch/s390/crypto/sha.h | 3 +- arch/s390/crypto/sha1_s390.c | 2 +- arch/s390/crypto/sha256_s390.c | 2 +- arch/s390/crypto/sha3_256_s390.c | 1 - arch/s390/crypto/sha3_512_s390.c | 1 - arch/s390/crypto/sha512_s390.c | 2 +- arch/s390/purgatory/purgatory.c | 2 +- arch/sparc/crypto/sha1_glue.c | 2 +- arch/sparc/crypto/sha256_glue.c | 2 +- arch/sparc/crypto/sha512_glue.c | 2 +- arch/x86/crypto/sha1_ssse3_glue.c | 2 +- arch/x86/crypto/sha256_ssse3_glue.c | 2 +- arch/x86/crypto/sha512_ssse3_glue.c | 2 +- arch/x86/purgatory/purgatory.c | 2 +- crypto/asymmetric_keys/asym_tpm.c | 2 +- crypto/sha1_generic.c | 2 +- crypto/sha256_generic.c | 2 +- crypto/sha512_generic.c | 2 +- drivers/char/random.c | 2 +- drivers/crypto/allwinner/sun4i-ss/sun4i-ss.h | 2 +- drivers/crypto/allwinner/sun8i-ce/sun8i-ce-hash.c | 3 +- drivers/crypto/allwinner/sun8i-ce/sun8i-ce.h | 3 +- drivers/crypto/allwinner/sun8i-ss/sun8i-ss-hash.c | 3 +- drivers/crypto/allwinner/sun8i-ss/sun8i-ss.h | 3 +- drivers/crypto/amcc/crypto4xx_alg.c | 2 +- drivers/crypto/amcc/crypto4xx_core.c | 2 +- drivers/crypto/atmel-authenc.h | 3 +- drivers/crypto/atmel-sha.c | 3 +- drivers/crypto/axis/artpec6_crypto.c | 3 +- drivers/crypto/bcm/cipher.c | 3 +- drivers/crypto/bcm/cipher.h | 3 +- drivers/crypto/bcm/spu.h | 3 +- drivers/crypto/caam/compat.h | 3 +- drivers/crypto/cavium/nitrox/nitrox_aead.c | 1 - drivers/crypto/ccp/ccp-crypto-sha.c | 3 +- drivers/crypto/ccp/ccp-crypto.h | 3 +- drivers/crypto/ccree/cc_driver.h | 3 +- drivers/crypto/chelsio/chcr_algo.c | 3 +- drivers/crypto/hisilicon/sec2/sec_crypto.c | 3 +- drivers/crypto/img-hash.c | 3 +- drivers/crypto/inside-secure/safexcel.h | 3 +- drivers/crypto/inside-secure/safexcel_cipher.c | 3 +- drivers/crypto/inside-secure/safexcel_hash.c | 3 +- drivers/crypto/ixp4xx_crypto.c | 2 +- drivers/crypto/marvell/cesa/hash.c | 3 +- drivers/crypto/marvell/octeontx/otx_cptvf_algs.c | 3 +- drivers/crypto/mediatek/mtk-sha.c | 3 +- drivers/crypto/mxs-dcp.c | 3 +- drivers/crypto/n2_core.c | 3 +- drivers/crypto/nx/nx-sha256.c | 2 +- drivers/crypto/nx/nx-sha512.c | 2 +- drivers/crypto/nx/nx.c | 2 +- drivers/crypto/omap-sham.c | 3 +- drivers/crypto/padlock-sha.c | 3 +- drivers/crypto/picoxcell_crypto.c | 3 +- drivers/crypto/qat/qat_common/qat_algs.c | 3 +- drivers/crypto/qce/common.c | 3 +- drivers/crypto/qce/core.c | 1 - drivers/crypto/qce/sha.h | 3 +- drivers/crypto/rockchip/rk3288_crypto.h | 3 +- drivers/crypto/s5p-sss.c | 3 +- drivers/crypto/sa2ul.c | 3 +- drivers/crypto/sa2ul.h | 3 +- drivers/crypto/sahara.c | 3 +- drivers/crypto/stm32/stm32-hash.c | 3 +- drivers/crypto/talitos.c | 3 +- drivers/crypto/ux500/hash/hash_core.c | 3 +- drivers/firmware/efi/embedded-firmware.c | 2 +- .../chelsio/inline_crypto/ch_ipsec/chcr_ipsec.c | 3 +- .../ethernet/chelsio/inline_crypto/chtls/chtls.h | 3 +- drivers/nfc/s3fwrn5/firmware.c | 2 +- drivers/tee/tee_core.c | 2 +- fs/crypto/fname.c | 2 +- fs/crypto/hkdf.c | 2 +- fs/ubifs/auth.c | 1 - fs/verity/fsverity_private.h | 2 +- include/crypto/hash_info.h | 3 +- include/crypto/sha.h | 167 --------------------- include/crypto/sha1.h | 46 ++++++ include/crypto/sha1_base.h | 2 +- include/crypto/sha2.h | 134 +++++++++++++++++ include/crypto/sha256_base.h | 2 +- include/crypto/sha512_base.h | 2 +- include/linux/ccp.h | 3 +- include/linux/filter.h | 2 +- include/linux/purgatory.h | 2 +- kernel/crash_core.c | 2 +- kernel/kexec_core.c | 1 - kernel/kexec_file.c | 2 +- lib/crypto/sha256.c | 2 +- lib/digsig.c | 2 +- lib/sha1.c | 2 +- net/ipv6/seg6_hmac.c | 1 - net/mptcp/crypto.c | 2 +- net/mptcp/options.c | 2 +- net/mptcp/subflow.c | 2 +- security/integrity/integrity.h | 2 +- security/keys/encrypted-keys/encrypted.c | 2 +- security/keys/trusted-keys/trusted_tpm1.c | 2 +- sound/soc/codecs/cros_ec_codec.c | 2 +- 121 files changed, 335 insertions(+), 285 deletions(-) delete mode 100644 include/crypto/sha.h create mode 100644 include/crypto/sha1.h create mode 100644 include/crypto/sha2.h (limited to 'arch/arm') diff --git a/arch/arm/crypto/sha1-ce-glue.c b/arch/arm/crypto/sha1-ce-glue.c index e79b1fb4b4dc..de9100c67b37 100644 --- a/arch/arm/crypto/sha1-ce-glue.c +++ b/arch/arm/crypto/sha1-ce-glue.c @@ -7,7 +7,7 @@ #include #include -#include +#include #include #include #include diff --git a/arch/arm/crypto/sha1.h b/arch/arm/crypto/sha1.h index 758db3e9ff0a..b1b7e21da2c3 100644 --- a/arch/arm/crypto/sha1.h +++ b/arch/arm/crypto/sha1.h @@ -3,7 +3,7 @@ #define ASM_ARM_CRYPTO_SHA1_H #include -#include +#include extern int sha1_update_arm(struct shash_desc *desc, const u8 *data, unsigned int len); diff --git a/arch/arm/crypto/sha1_glue.c b/arch/arm/crypto/sha1_glue.c index 4e954b3f7ecd..6c2b849e459d 100644 --- a/arch/arm/crypto/sha1_glue.c +++ b/arch/arm/crypto/sha1_glue.c @@ -15,7 +15,7 @@ #include #include #include -#include +#include #include #include diff --git a/arch/arm/crypto/sha1_neon_glue.c b/arch/arm/crypto/sha1_neon_glue.c index 0071e5e4411a..cfe36ae0f3f5 100644 --- a/arch/arm/crypto/sha1_neon_glue.c +++ b/arch/arm/crypto/sha1_neon_glue.c @@ -19,7 +19,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/arch/arm/crypto/sha2-ce-glue.c b/arch/arm/crypto/sha2-ce-glue.c index 87f0b62386c6..c62ce89dd3e0 100644 --- a/arch/arm/crypto/sha2-ce-glue.c +++ b/arch/arm/crypto/sha2-ce-glue.c @@ -7,7 +7,7 @@ #include #include -#include +#include #include #include #include diff --git a/arch/arm/crypto/sha256_glue.c b/arch/arm/crypto/sha256_glue.c index b8a4f79020cf..433ee4ddce6c 100644 --- a/arch/arm/crypto/sha256_glue.c +++ b/arch/arm/crypto/sha256_glue.c @@ -17,7 +17,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/arch/arm/crypto/sha256_neon_glue.c b/arch/arm/crypto/sha256_neon_glue.c index 79820b9e2541..701706262ef3 100644 --- a/arch/arm/crypto/sha256_neon_glue.c +++ b/arch/arm/crypto/sha256_neon_glue.c @@ -13,7 +13,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/arch/arm/crypto/sha512-glue.c b/arch/arm/crypto/sha512-glue.c index 8775aa42bbbe..0635a65aa488 100644 --- a/arch/arm/crypto/sha512-glue.c +++ b/arch/arm/crypto/sha512-glue.c @@ -6,7 +6,7 @@ */ #include -#include +#include #include #include #include diff --git a/arch/arm/crypto/sha512-neon-glue.c b/arch/arm/crypto/sha512-neon-glue.c index 96cb94403540..c879ad32db51 100644 --- a/arch/arm/crypto/sha512-neon-glue.c +++ b/arch/arm/crypto/sha512-neon-glue.c @@ -7,7 +7,7 @@ #include #include -#include +#include #include #include #include diff --git a/arch/arm64/crypto/aes-glue.c b/arch/arm64/crypto/aes-glue.c index 395bbf64b2ab..34b8a89197be 100644 --- a/arch/arm64/crypto/aes-glue.c +++ b/arch/arm64/crypto/aes-glue.c @@ -10,7 +10,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/arch/arm64/crypto/sha1-ce-glue.c b/arch/arm64/crypto/sha1-ce-glue.c index c63b99211db3..c93121bcfdeb 100644 --- a/arch/arm64/crypto/sha1-ce-glue.c +++ b/arch/arm64/crypto/sha1-ce-glue.c @@ -10,7 +10,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/arch/arm64/crypto/sha2-ce-glue.c b/arch/arm64/crypto/sha2-ce-glue.c index 5e956d7582a5..31ba3da5e61b 100644 --- a/arch/arm64/crypto/sha2-ce-glue.c +++ b/arch/arm64/crypto/sha2-ce-glue.c @@ -10,7 +10,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/arch/arm64/crypto/sha256-glue.c b/arch/arm64/crypto/sha256-glue.c index 77bc6e72abae..9462f6088b3f 100644 --- a/arch/arm64/crypto/sha256-glue.c +++ b/arch/arm64/crypto/sha256-glue.c @@ -10,7 +10,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/arch/arm64/crypto/sha512-ce-glue.c b/arch/arm64/crypto/sha512-ce-glue.c index dc890a719f54..faa83f6cf376 100644 --- a/arch/arm64/crypto/sha512-ce-glue.c +++ b/arch/arm64/crypto/sha512-ce-glue.c @@ -14,7 +14,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/arch/arm64/crypto/sha512-glue.c b/arch/arm64/crypto/sha512-glue.c index 370ccb29602f..2acff1c7df5d 100644 --- a/arch/arm64/crypto/sha512-glue.c +++ b/arch/arm64/crypto/sha512-glue.c @@ -8,7 +8,7 @@ #include #include #include -#include +#include #include #include diff --git a/arch/mips/cavium-octeon/crypto/octeon-sha1.c b/arch/mips/cavium-octeon/crypto/octeon-sha1.c index 75e79b47abfe..30f1d75208a5 100644 --- a/arch/mips/cavium-octeon/crypto/octeon-sha1.c +++ b/arch/mips/cavium-octeon/crypto/octeon-sha1.c @@ -14,7 +14,7 @@ */ #include -#include +#include #include #include #include diff --git a/arch/mips/cavium-octeon/crypto/octeon-sha256.c b/arch/mips/cavium-octeon/crypto/octeon-sha256.c index a682ce76716a..36cb92895d72 100644 --- a/arch/mips/cavium-octeon/crypto/octeon-sha256.c +++ b/arch/mips/cavium-octeon/crypto/octeon-sha256.c @@ -15,7 +15,7 @@ */ #include -#include +#include #include #include #include diff --git a/arch/mips/cavium-octeon/crypto/octeon-sha512.c b/arch/mips/cavium-octeon/crypto/octeon-sha512.c index 50722a0cfb53..359f039820d8 100644 --- a/arch/mips/cavium-octeon/crypto/octeon-sha512.c +++ b/arch/mips/cavium-octeon/crypto/octeon-sha512.c @@ -14,7 +14,7 @@ */ #include -#include +#include #include #include #include diff --git a/arch/powerpc/crypto/sha1-spe-glue.c b/arch/powerpc/crypto/sha1-spe-glue.c index cb57be4ada61..b1e577cbf00c 100644 --- a/arch/powerpc/crypto/sha1-spe-glue.c +++ b/arch/powerpc/crypto/sha1-spe-glue.c @@ -12,7 +12,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/arch/powerpc/crypto/sha1.c b/arch/powerpc/crypto/sha1.c index b40dc50a6908..7a55d790cdb1 100644 --- a/arch/powerpc/crypto/sha1.c +++ b/arch/powerpc/crypto/sha1.c @@ -17,7 +17,7 @@ #include #include #include -#include +#include #include void powerpc_sha_transform(u32 *state, const u8 *src); diff --git a/arch/powerpc/crypto/sha256-spe-glue.c b/arch/powerpc/crypto/sha256-spe-glue.c index ceb0b6c980b3..88530ae0791f 100644 --- a/arch/powerpc/crypto/sha256-spe-glue.c +++ b/arch/powerpc/crypto/sha256-spe-glue.c @@ -13,7 +13,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/arch/s390/crypto/sha.h b/arch/s390/crypto/sha.h index ada2f98c27b7..65ea12fc87a1 100644 --- a/arch/s390/crypto/sha.h +++ b/arch/s390/crypto/sha.h @@ -11,7 +11,8 @@ #define _CRYPTO_ARCH_S390_SHA_H #include -#include +#include +#include #include /* must be big enough for the largest SHA variant */ diff --git a/arch/s390/crypto/sha1_s390.c b/arch/s390/crypto/sha1_s390.c index 698b1e6d3c14..a3fabf310a38 100644 --- a/arch/s390/crypto/sha1_s390.c +++ b/arch/s390/crypto/sha1_s390.c @@ -22,7 +22,7 @@ #include #include #include -#include +#include #include #include "sha.h" diff --git a/arch/s390/crypto/sha256_s390.c b/arch/s390/crypto/sha256_s390.c index b52c87e44939..24983f175676 100644 --- a/arch/s390/crypto/sha256_s390.c +++ b/arch/s390/crypto/sha256_s390.c @@ -12,7 +12,7 @@ #include #include #include -#include +#include #include #include "sha.h" diff --git a/arch/s390/crypto/sha3_256_s390.c b/arch/s390/crypto/sha3_256_s390.c index 460cbbbaa44a..30ac49b635bf 100644 --- a/arch/s390/crypto/sha3_256_s390.c +++ b/arch/s390/crypto/sha3_256_s390.c @@ -12,7 +12,6 @@ #include #include #include -#include #include #include diff --git a/arch/s390/crypto/sha3_512_s390.c b/arch/s390/crypto/sha3_512_s390.c index 72cf460a53e5..e70d50f7620f 100644 --- a/arch/s390/crypto/sha3_512_s390.c +++ b/arch/s390/crypto/sha3_512_s390.c @@ -11,7 +11,6 @@ #include #include #include -#include #include #include diff --git a/arch/s390/crypto/sha512_s390.c b/arch/s390/crypto/sha512_s390.c index ad29db085a18..29a6bd404c59 100644 --- a/arch/s390/crypto/sha512_s390.c +++ b/arch/s390/crypto/sha512_s390.c @@ -8,7 +8,7 @@ * Author(s): Jan Glauber (jang@de.ibm.com) */ #include -#include +#include #include #include #include diff --git a/arch/s390/purgatory/purgatory.c b/arch/s390/purgatory/purgatory.c index 0a423bcf6746..030efda05dbe 100644 --- a/arch/s390/purgatory/purgatory.c +++ b/arch/s390/purgatory/purgatory.c @@ -9,7 +9,7 @@ #include #include -#include +#include #include int verify_sha256_digest(void) diff --git a/arch/sparc/crypto/sha1_glue.c b/arch/sparc/crypto/sha1_glue.c index dc017782be52..86a654cce5ab 100644 --- a/arch/sparc/crypto/sha1_glue.c +++ b/arch/sparc/crypto/sha1_glue.c @@ -16,7 +16,7 @@ #include #include #include -#include +#include #include #include diff --git a/arch/sparc/crypto/sha256_glue.c b/arch/sparc/crypto/sha256_glue.c index ca2547df9652..60ec524cf9ca 100644 --- a/arch/sparc/crypto/sha256_glue.c +++ b/arch/sparc/crypto/sha256_glue.c @@ -16,7 +16,7 @@ #include #include #include -#include +#include #include #include diff --git a/arch/sparc/crypto/sha512_glue.c b/arch/sparc/crypto/sha512_glue.c index 3b2ca732ff7a..273ce21918c1 100644 --- a/arch/sparc/crypto/sha512_glue.c +++ b/arch/sparc/crypto/sha512_glue.c @@ -15,7 +15,7 @@ #include #include #include -#include +#include #include #include diff --git a/arch/x86/crypto/sha1_ssse3_glue.c b/arch/x86/crypto/sha1_ssse3_glue.c index 18200135603f..44340a1139e0 100644 --- a/arch/x86/crypto/sha1_ssse3_glue.c +++ b/arch/x86/crypto/sha1_ssse3_glue.c @@ -22,7 +22,7 @@ #include #include #include -#include +#include #include #include diff --git a/arch/x86/crypto/sha256_ssse3_glue.c b/arch/x86/crypto/sha256_ssse3_glue.c index dd06249229e1..3a5f6be7dbba 100644 --- a/arch/x86/crypto/sha256_ssse3_glue.c +++ b/arch/x86/crypto/sha256_ssse3_glue.c @@ -35,7 +35,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/arch/x86/crypto/sha512_ssse3_glue.c b/arch/x86/crypto/sha512_ssse3_glue.c index b0b05c93409e..30e70f4fe2f7 100644 --- a/arch/x86/crypto/sha512_ssse3_glue.c +++ b/arch/x86/crypto/sha512_ssse3_glue.c @@ -34,7 +34,7 @@ #include #include #include -#include +#include #include #include diff --git a/arch/x86/purgatory/purgatory.c b/arch/x86/purgatory/purgatory.c index 7b37a412f829..f03b64d9cb51 100644 --- a/arch/x86/purgatory/purgatory.c +++ b/arch/x86/purgatory/purgatory.c @@ -9,7 +9,7 @@ */ #include -#include +#include #include #include "../boot/string.h" diff --git a/crypto/asymmetric_keys/asym_tpm.c b/crypto/asymmetric_keys/asym_tpm.c index 378b18b9bc34..511932aa94a6 100644 --- a/crypto/asymmetric_keys/asym_tpm.c +++ b/crypto/asymmetric_keys/asym_tpm.c @@ -10,7 +10,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/crypto/sha1_generic.c b/crypto/sha1_generic.c index 1d43472fecbd..325b57fe28dc 100644 --- a/crypto/sha1_generic.c +++ b/crypto/sha1_generic.c @@ -16,7 +16,7 @@ #include #include #include -#include +#include #include #include diff --git a/crypto/sha256_generic.c b/crypto/sha256_generic.c index 88156e3e2a33..3b377197236e 100644 --- a/crypto/sha256_generic.c +++ b/crypto/sha256_generic.c @@ -12,7 +12,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/crypto/sha512_generic.c b/crypto/sha512_generic.c index e34d09dd9971..c72d72ad828e 100644 --- a/crypto/sha512_generic.c +++ b/crypto/sha512_generic.c @@ -12,7 +12,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/drivers/char/random.c b/drivers/char/random.c index 2a41b21623ae..5f3b8ac9d97b 100644 --- a/drivers/char/random.c +++ b/drivers/char/random.c @@ -336,7 +336,7 @@ #include #include #include -#include +#include #include #include diff --git a/drivers/crypto/allwinner/sun4i-ss/sun4i-ss.h b/drivers/crypto/allwinner/sun4i-ss/sun4i-ss.h index 163962f9e284..5c291e4a6857 100644 --- a/drivers/crypto/allwinner/sun4i-ss/sun4i-ss.h +++ b/drivers/crypto/allwinner/sun4i-ss/sun4i-ss.h @@ -25,7 +25,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/drivers/crypto/allwinner/sun8i-ce/sun8i-ce-hash.c b/drivers/crypto/allwinner/sun8i-ce/sun8i-ce-hash.c index fa2f1b4fad7b..4927a6c82d32 100644 --- a/drivers/crypto/allwinner/sun8i-ce/sun8i-ce-hash.c +++ b/drivers/crypto/allwinner/sun8i-ce/sun8i-ce-hash.c @@ -13,7 +13,8 @@ #include #include #include -#include +#include +#include #include #include "sun8i-ce.h" diff --git a/drivers/crypto/allwinner/sun8i-ce/sun8i-ce.h b/drivers/crypto/allwinner/sun8i-ce/sun8i-ce.h index 558027516aed..cec781d5063c 100644 --- a/drivers/crypto/allwinner/sun8i-ce/sun8i-ce.h +++ b/drivers/crypto/allwinner/sun8i-ce/sun8i-ce.h @@ -16,7 +16,8 @@ #include #include #include -#include +#include +#include /* CE Registers */ #define CE_TDQ 0x00 diff --git a/drivers/crypto/allwinner/sun8i-ss/sun8i-ss-hash.c b/drivers/crypto/allwinner/sun8i-ss/sun8i-ss-hash.c index b6ab2054f217..11cbcbc83a7b 100644 --- a/drivers/crypto/allwinner/sun8i-ss/sun8i-ss-hash.c +++ b/drivers/crypto/allwinner/sun8i-ss/sun8i-ss-hash.c @@ -13,7 +13,8 @@ #include #include #include -#include +#include +#include #include #include "sun8i-ss.h" diff --git a/drivers/crypto/allwinner/sun8i-ss/sun8i-ss.h b/drivers/crypto/allwinner/sun8i-ss/sun8i-ss.h index 1a66457f4a20..28188685b910 100644 --- a/drivers/crypto/allwinner/sun8i-ss/sun8i-ss.h +++ b/drivers/crypto/allwinner/sun8i-ss/sun8i-ss.h @@ -15,7 +15,8 @@ #include #include #include -#include +#include +#include #define SS_START 1 diff --git a/drivers/crypto/amcc/crypto4xx_alg.c b/drivers/crypto/amcc/crypto4xx_alg.c index 7729a637fb02..a3fa849b139a 100644 --- a/drivers/crypto/amcc/crypto4xx_alg.c +++ b/drivers/crypto/amcc/crypto4xx_alg.c @@ -20,7 +20,7 @@ #include #include #include -#include +#include #include #include #include "crypto4xx_reg_def.h" diff --git a/drivers/crypto/amcc/crypto4xx_core.c b/drivers/crypto/amcc/crypto4xx_core.c index 2e3690f65786..8d1b918a0533 100644 --- a/drivers/crypto/amcc/crypto4xx_core.c +++ b/drivers/crypto/amcc/crypto4xx_core.c @@ -30,7 +30,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/drivers/crypto/atmel-authenc.h b/drivers/crypto/atmel-authenc.h index c6530a1c8c20..45171e89a7d2 100644 --- a/drivers/crypto/atmel-authenc.h +++ b/drivers/crypto/atmel-authenc.h @@ -16,7 +16,8 @@ #include #include -#include +#include +#include #include "atmel-sha-regs.h" struct atmel_aes_dev; diff --git a/drivers/crypto/atmel-sha.c b/drivers/crypto/atmel-sha.c index 0eb6f54e3b66..352d80cb5ae9 100644 --- a/drivers/crypto/atmel-sha.c +++ b/drivers/crypto/atmel-sha.c @@ -33,7 +33,8 @@ #include #include #include -#include +#include +#include #include #include #include "atmel-sha-regs.h" diff --git a/drivers/crypto/axis/artpec6_crypto.c b/drivers/crypto/axis/artpec6_crypto.c index 809c3033ca74..9ad188cffd0d 100644 --- a/drivers/crypto/axis/artpec6_crypto.c +++ b/drivers/crypto/axis/artpec6_crypto.c @@ -28,7 +28,8 @@ #include #include #include -#include +#include +#include #include /* Max length of a line in all cache levels for Artpec SoCs. */ diff --git a/drivers/crypto/bcm/cipher.c b/drivers/crypto/bcm/cipher.c index 50d169e61b41..30390a7324b2 100644 --- a/drivers/crypto/bcm/cipher.c +++ b/drivers/crypto/bcm/cipher.c @@ -26,11 +26,12 @@ #include #include #include -#include #include #include #include #include +#include +#include #include #include "util.h" diff --git a/drivers/crypto/bcm/cipher.h b/drivers/crypto/bcm/cipher.h index 035c8389cb3d..0ad5892b445d 100644 --- a/drivers/crypto/bcm/cipher.h +++ b/drivers/crypto/bcm/cipher.h @@ -16,7 +16,8 @@ #include #include #include -#include +#include +#include #include #include "spu.h" diff --git a/drivers/crypto/bcm/spu.h b/drivers/crypto/bcm/spu.h index dd132389bcaa..1c386a2d5506 100644 --- a/drivers/crypto/bcm/spu.h +++ b/drivers/crypto/bcm/spu.h @@ -17,7 +17,8 @@ #include #include -#include +#include +#include enum spu_cipher_alg { CIPHER_ALG_NONE = 0x0, diff --git a/drivers/crypto/caam/compat.h b/drivers/crypto/caam/compat.h index c3c22a8de4c0..c4f79764172b 100644 --- a/drivers/crypto/caam/compat.h +++ b/drivers/crypto/caam/compat.h @@ -34,7 +34,8 @@ #include #include #include -#include +#include +#include #include #include #include diff --git a/drivers/crypto/cavium/nitrox/nitrox_aead.c b/drivers/crypto/cavium/nitrox/nitrox_aead.c index e5d8607ecb1d..c93c4e41d267 100644 --- a/drivers/crypto/cavium/nitrox/nitrox_aead.c +++ b/drivers/crypto/cavium/nitrox/nitrox_aead.c @@ -7,7 +7,6 @@ #include #include #include -#include #include #include #include diff --git a/drivers/crypto/ccp/ccp-crypto-sha.c b/drivers/crypto/ccp/ccp-crypto-sha.c index 8fbfdb9e8cd3..74fa5360e722 100644 --- a/drivers/crypto/ccp/ccp-crypto-sha.c +++ b/drivers/crypto/ccp/ccp-crypto-sha.c @@ -17,7 +17,8 @@ #include #include #include -#include +#include +#include #include #include diff --git a/drivers/crypto/ccp/ccp-crypto.h b/drivers/crypto/ccp/ccp-crypto.h index aed3d2192d01..e42450d07168 100644 --- a/drivers/crypto/ccp/ccp-crypto.h +++ b/drivers/crypto/ccp/ccp-crypto.h @@ -19,7 +19,8 @@ #include #include #include -#include +#include +#include #include #include #include diff --git a/drivers/crypto/ccree/cc_driver.h b/drivers/crypto/ccree/cc_driver.h index af77b2020350..ed2b2f13a256 100644 --- a/drivers/crypto/ccree/cc_driver.h +++ b/drivers/crypto/ccree/cc_driver.h @@ -17,7 +17,8 @@ #include #include #include -#include +#include +#include #include #include #include diff --git a/drivers/crypto/chelsio/chcr_algo.c b/drivers/crypto/chelsio/chcr_algo.c index 13b908ea4873..f5a336634daa 100644 --- a/drivers/crypto/chelsio/chcr_algo.c +++ b/drivers/crypto/chelsio/chcr_algo.c @@ -53,7 +53,8 @@ #include #include #include -#include +#include +#include #include #include #include diff --git a/drivers/crypto/hisilicon/sec2/sec_crypto.c b/drivers/crypto/hisilicon/sec2/sec_crypto.c index 891e04914615..2eaa516b3231 100644 --- a/drivers/crypto/hisilicon/sec2/sec_crypto.c +++ b/drivers/crypto/hisilicon/sec2/sec_crypto.c @@ -7,7 +7,8 @@ #include #include #include -#include +#include +#include #include #include #include diff --git a/drivers/crypto/img-hash.c b/drivers/crypto/img-hash.c index 91f555ccbb31..e813115d5432 100644 --- a/drivers/crypto/img-hash.c +++ b/drivers/crypto/img-hash.c @@ -19,7 +19,8 @@ #include #include -#include +#include +#include #define CR_RESET 0 #define CR_RESET_SET 1 diff --git a/drivers/crypto/inside-secure/safexcel.h b/drivers/crypto/inside-secure/safexcel.h index 9045f2d7f4c6..ce1e611a163e 100644 --- a/drivers/crypto/inside-secure/safexcel.h +++ b/drivers/crypto/inside-secure/safexcel.h @@ -11,7 +11,8 @@ #include #include #include -#include +#include +#include #include #include #include diff --git a/drivers/crypto/inside-secure/safexcel_cipher.c b/drivers/crypto/inside-secure/safexcel_cipher.c index 9bcfb79a030f..d68ef16650d4 100644 --- a/drivers/crypto/inside-secure/safexcel_cipher.c +++ b/drivers/crypto/inside-secure/safexcel_cipher.c @@ -18,7 +18,8 @@ #include #include #include -#include +#include +#include #include #include #include diff --git a/drivers/crypto/inside-secure/safexcel_hash.c b/drivers/crypto/inside-secure/safexcel_hash.c index 56d5ccb5cc00..50fb6d90a2e0 100644 --- a/drivers/crypto/inside-secure/safexcel_hash.c +++ b/drivers/crypto/inside-secure/safexcel_hash.c @@ -8,7 +8,8 @@ #include #include #include -#include +#include +#include #include #include #include diff --git a/drivers/crypto/ixp4xx_crypto.c b/drivers/crypto/ixp4xx_crypto.c index 276012e7c482..8b0f17fc09fb 100644 --- a/drivers/crypto/ixp4xx_crypto.c +++ b/drivers/crypto/ixp4xx_crypto.c @@ -20,7 +20,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/drivers/crypto/marvell/cesa/hash.c b/drivers/crypto/marvell/cesa/hash.c index add7ea011c98..8cf9fd518d86 100644 --- a/drivers/crypto/marvell/cesa/hash.c +++ b/drivers/crypto/marvell/cesa/hash.c @@ -11,7 +11,8 @@ #include #include -#include +#include +#include #include #include diff --git a/drivers/crypto/marvell/octeontx/otx_cptvf_algs.c b/drivers/crypto/marvell/octeontx/otx_cptvf_algs.c index 90bb31329d4b..ccbef01888d4 100644 --- a/drivers/crypto/marvell/octeontx/otx_cptvf_algs.c +++ b/drivers/crypto/marvell/octeontx/otx_cptvf_algs.c @@ -13,7 +13,8 @@ #include #include #include -#include +#include +#include #include #include #include diff --git a/drivers/crypto/mediatek/mtk-sha.c b/drivers/crypto/mediatek/mtk-sha.c index 3d5d7d68b03b..f55aacdafbef 100644 --- a/drivers/crypto/mediatek/mtk-sha.c +++ b/drivers/crypto/mediatek/mtk-sha.c @@ -10,7 +10,8 @@ */ #include -#include +#include +#include #include "mtk-platform.h" #define SHA_ALIGN_MSK (sizeof(u32) - 1) diff --git a/drivers/crypto/mxs-dcp.c b/drivers/crypto/mxs-dcp.c index 909a7eb748e3..d6a7784d2988 100644 --- a/drivers/crypto/mxs-dcp.c +++ b/drivers/crypto/mxs-dcp.c @@ -17,7 +17,8 @@ #include #include -#include +#include +#include #include #include #include diff --git a/drivers/crypto/n2_core.c b/drivers/crypto/n2_core.c index 3642bf83d809..3b0bf6fea491 100644 --- a/drivers/crypto/n2_core.c +++ b/drivers/crypto/n2_core.c @@ -15,7 +15,8 @@ #include #include #include -#include +#include +#include #include #include #include diff --git a/drivers/crypto/nx/nx-sha256.c b/drivers/crypto/nx/nx-sha256.c index 02fb53453195..90d9a37a57f6 100644 --- a/drivers/crypto/nx/nx-sha256.c +++ b/drivers/crypto/nx/nx-sha256.c @@ -8,7 +8,7 @@ */ #include -#include +#include #include #include #include diff --git a/drivers/crypto/nx/nx-sha512.c b/drivers/crypto/nx/nx-sha512.c index 4c7a3e3eeebf..eb8627a0f317 100644 --- a/drivers/crypto/nx/nx-sha512.c +++ b/drivers/crypto/nx/nx-sha512.c @@ -8,7 +8,7 @@ */ #include -#include +#include #include #include diff --git a/drivers/crypto/nx/nx.c b/drivers/crypto/nx/nx.c index 40882d6d52c1..0d2dc5be7f19 100644 --- a/drivers/crypto/nx/nx.c +++ b/drivers/crypto/nx/nx.c @@ -10,7 +10,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/drivers/crypto/omap-sham.c b/drivers/crypto/omap-sham.c index a3b38d2c92e7..ae0d320d3c60 100644 --- a/drivers/crypto/omap-sham.c +++ b/drivers/crypto/omap-sham.c @@ -35,7 +35,8 @@ #include #include #include -#include +#include +#include #include #include #include diff --git a/drivers/crypto/padlock-sha.c b/drivers/crypto/padlock-sha.c index a697a4a3f2d0..6865c7f1fc1a 100644 --- a/drivers/crypto/padlock-sha.c +++ b/drivers/crypto/padlock-sha.c @@ -9,7 +9,8 @@ #include #include -#include +#include +#include #include #include #include diff --git a/drivers/crypto/picoxcell_crypto.c b/drivers/crypto/picoxcell_crypto.c index fb34bf92861d..84f9c16d984c 100644 --- a/drivers/crypto/picoxcell_crypto.c +++ b/drivers/crypto/picoxcell_crypto.c @@ -8,7 +8,8 @@ #include #include #include -#include +#include +#include #include #include #include diff --git a/drivers/crypto/qat/qat_common/qat_algs.c b/drivers/crypto/qat/qat_common/qat_algs.c index 0fab8bb8ca59..b3a68d986417 100644 --- a/drivers/crypto/qat/qat_common/qat_algs.c +++ b/drivers/crypto/qat/qat_common/qat_algs.c @@ -6,7 +6,8 @@ #include #include #include -#include +#include +#include #include #include #include diff --git a/drivers/crypto/qce/common.c b/drivers/crypto/qce/common.c index 5006e74c40cd..a73db2a5637f 100644 --- a/drivers/crypto/qce/common.c +++ b/drivers/crypto/qce/common.c @@ -7,7 +7,8 @@ #include #include #include -#include +#include +#include #include "cipher.h" #include "common.h" diff --git a/drivers/crypto/qce/core.c b/drivers/crypto/qce/core.c index ea616b7259ae..5e6717f9bbda 100644 --- a/drivers/crypto/qce/core.c +++ b/drivers/crypto/qce/core.c @@ -13,7 +13,6 @@ #include #include #include -#include #include "core.h" #include "cipher.h" diff --git a/drivers/crypto/qce/sha.h b/drivers/crypto/qce/sha.h index d63526e3804d..a22695361f16 100644 --- a/drivers/crypto/qce/sha.h +++ b/drivers/crypto/qce/sha.h @@ -7,7 +7,8 @@ #define _SHA_H_ #include -#include +#include +#include #include "common.h" #include "core.h" diff --git a/drivers/crypto/rockchip/rk3288_crypto.h b/drivers/crypto/rockchip/rk3288_crypto.h index 3db595570c9c..97278c2574ff 100644 --- a/drivers/crypto/rockchip/rk3288_crypto.h +++ b/drivers/crypto/rockchip/rk3288_crypto.h @@ -12,7 +12,8 @@ #include #include -#include +#include +#include #define _SBF(v, f) ((v) << (f)) diff --git a/drivers/crypto/s5p-sss.c b/drivers/crypto/s5p-sss.c index 88a6c853ffd7..682c8a450a57 100644 --- a/drivers/crypto/s5p-sss.c +++ b/drivers/crypto/s5p-sss.c @@ -30,7 +30,8 @@ #include #include -#include +#include +#include #include #define _SBF(s, v) ((v) << (s)) diff --git a/drivers/crypto/sa2ul.c b/drivers/crypto/sa2ul.c index c357010a159e..f300b0a5958a 100644 --- a/drivers/crypto/sa2ul.c +++ b/drivers/crypto/sa2ul.c @@ -25,7 +25,8 @@ #include #include #include -#include +#include +#include #include "sa2ul.h" diff --git a/drivers/crypto/sa2ul.h b/drivers/crypto/sa2ul.h index bb40df3876e5..f597ddecde34 100644 --- a/drivers/crypto/sa2ul.h +++ b/drivers/crypto/sa2ul.h @@ -13,7 +13,8 @@ #define _K3_SA2UL_ #include -#include +#include +#include #define SA_ENGINE_ENABLE_CONTROL 0x1000 diff --git a/drivers/crypto/sahara.c b/drivers/crypto/sahara.c index d60679c79822..8b5be29cb4dc 100644 --- a/drivers/crypto/sahara.c +++ b/drivers/crypto/sahara.c @@ -15,7 +15,8 @@ #include #include #include -#include +#include +#include #include #include diff --git a/drivers/crypto/stm32/stm32-hash.c b/drivers/crypto/stm32/stm32-hash.c index e3e25278a970..7ac0573ef663 100644 --- a/drivers/crypto/stm32/stm32-hash.c +++ b/drivers/crypto/stm32/stm32-hash.c @@ -25,7 +25,8 @@ #include #include #include -#include +#include +#include #include #define HASH_CR 0x00 diff --git a/drivers/crypto/talitos.c b/drivers/crypto/talitos.c index a713a35dc502..4fd85f31630a 100644 --- a/drivers/crypto/talitos.c +++ b/drivers/crypto/talitos.c @@ -31,7 +31,8 @@ #include #include #include -#include +#include +#include #include #include #include diff --git a/drivers/crypto/ux500/hash/hash_core.c b/drivers/crypto/ux500/hash/hash_core.c index 3d407eebb2ba..da284b0ea1b2 100644 --- a/drivers/crypto/ux500/hash/hash_core.c +++ b/drivers/crypto/ux500/hash/hash_core.c @@ -31,7 +31,8 @@ #include #include -#include +#include +#include #include #include diff --git a/drivers/firmware/efi/embedded-firmware.c b/drivers/firmware/efi/embedded-firmware.c index 21ae0c48232a..f5be8e22305b 100644 --- a/drivers/firmware/efi/embedded-firmware.c +++ b/drivers/firmware/efi/embedded-firmware.c @@ -12,7 +12,7 @@ #include #include #include -#include +#include /* Exported for use by lib/test_firmware.c only */ LIST_HEAD(efi_embedded_fw_list); diff --git a/drivers/net/ethernet/chelsio/inline_crypto/ch_ipsec/chcr_ipsec.c b/drivers/net/ethernet/chelsio/inline_crypto/ch_ipsec/chcr_ipsec.c index 072299b14b8d..47d9268a7e3c 100644 --- a/drivers/net/ethernet/chelsio/inline_crypto/ch_ipsec/chcr_ipsec.c +++ b/drivers/net/ethernet/chelsio/inline_crypto/ch_ipsec/chcr_ipsec.c @@ -51,7 +51,8 @@ #include #include #include -#include +#include +#include #include #include #include diff --git a/drivers/net/ethernet/chelsio/inline_crypto/chtls/chtls.h b/drivers/net/ethernet/chelsio/inline_crypto/chtls/chtls.h index 2d3dfdd2a716..65617752c630 100644 --- a/drivers/net/ethernet/chelsio/inline_crypto/chtls/chtls.h +++ b/drivers/net/ethernet/chelsio/inline_crypto/chtls/chtls.h @@ -9,7 +9,8 @@ #include #include #include -#include +#include +#include #include #include #include diff --git a/drivers/nfc/s3fwrn5/firmware.c b/drivers/nfc/s3fwrn5/firmware.c index ec930ee2c847..5d5ad8307211 100644 --- a/drivers/nfc/s3fwrn5/firmware.c +++ b/drivers/nfc/s3fwrn5/firmware.c @@ -9,7 +9,7 @@ #include #include #include -#include +#include #include "s3fwrn5.h" #include "firmware.h" diff --git a/drivers/tee/tee_core.c b/drivers/tee/tee_core.c index f53bf336c0a2..d70d4be91096 100644 --- a/drivers/tee/tee_core.c +++ b/drivers/tee/tee_core.c @@ -14,7 +14,7 @@ #include #include #include -#include +#include #include "tee_private.h" #define TEE_NUM_DEVICES 32 diff --git a/fs/crypto/fname.c b/fs/crypto/fname.c index 1fbe6c24d705..cf06ea3870eb 100644 --- a/fs/crypto/fname.c +++ b/fs/crypto/fname.c @@ -14,7 +14,7 @@ #include #include #include -#include +#include #include #include "fscrypt_private.h" diff --git a/fs/crypto/hkdf.c b/fs/crypto/hkdf.c index 0cba7928446d..e0ec21055505 100644 --- a/fs/crypto/hkdf.c +++ b/fs/crypto/hkdf.c @@ -10,7 +10,7 @@ */ #include -#include +#include #include "fscrypt_private.h" diff --git a/fs/ubifs/auth.c b/fs/ubifs/auth.c index b93b3cd10bfd..0886d835f597 100644 --- a/fs/ubifs/auth.c +++ b/fs/ubifs/auth.c @@ -12,7 +12,6 @@ #include #include #include -#include #include #include #include diff --git a/fs/verity/fsverity_private.h b/fs/verity/fsverity_private.h index e96d99d5145e..6a8f2e3cce6c 100644 --- a/fs/verity/fsverity_private.h +++ b/fs/verity/fsverity_private.h @@ -14,7 +14,7 @@ #define pr_fmt(fmt) "fs-verity: " fmt -#include +#include #include #include diff --git a/include/crypto/hash_info.h b/include/crypto/hash_info.h index eb9d2e368969..dd4f06785049 100644 --- a/include/crypto/hash_info.h +++ b/include/crypto/hash_info.h @@ -8,7 +8,8 @@ #ifndef _CRYPTO_HASH_INFO_H #define _CRYPTO_HASH_INFO_H -#include +#include +#include #include #include diff --git a/include/crypto/sha.h b/include/crypto/sha.h deleted file mode 100644 index 4ff3da816630..000000000000 --- a/include/crypto/sha.h +++ /dev/null @@ -1,167 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Common values for SHA algorithms - */ - -#ifndef _CRYPTO_SHA_H -#define _CRYPTO_SHA_H - -#include - -#define SHA1_DIGEST_SIZE 20 -#define SHA1_BLOCK_SIZE 64 - -#define SHA224_DIGEST_SIZE 28 -#define SHA224_BLOCK_SIZE 64 - -#define SHA256_DIGEST_SIZE 32 -#define SHA256_BLOCK_SIZE 64 - -#define SHA384_DIGEST_SIZE 48 -#define SHA384_BLOCK_SIZE 128 - -#define SHA512_DIGEST_SIZE 64 -#define SHA512_BLOCK_SIZE 128 - -#define SHA1_H0 0x67452301UL -#define SHA1_H1 0xefcdab89UL -#define SHA1_H2 0x98badcfeUL -#define SHA1_H3 0x10325476UL -#define SHA1_H4 0xc3d2e1f0UL - -#define SHA224_H0 0xc1059ed8UL -#define SHA224_H1 0x367cd507UL -#define SHA224_H2 0x3070dd17UL -#define SHA224_H3 0xf70e5939UL -#define SHA224_H4 0xffc00b31UL -#define SHA224_H5 0x68581511UL -#define SHA224_H6 0x64f98fa7UL -#define SHA224_H7 0xbefa4fa4UL - -#define SHA256_H0 0x6a09e667UL -#define SHA256_H1 0xbb67ae85UL -#define SHA256_H2 0x3c6ef372UL -#define SHA256_H3 0xa54ff53aUL -#define SHA256_H4 0x510e527fUL -#define SHA256_H5 0x9b05688cUL -#define SHA256_H6 0x1f83d9abUL -#define SHA256_H7 0x5be0cd19UL - -#define SHA384_H0 0xcbbb9d5dc1059ed8ULL -#define SHA384_H1 0x629a292a367cd507ULL -#define SHA384_H2 0x9159015a3070dd17ULL -#define SHA384_H3 0x152fecd8f70e5939ULL -#define SHA384_H4 0x67332667ffc00b31ULL -#define SHA384_H5 0x8eb44a8768581511ULL -#define SHA384_H6 0xdb0c2e0d64f98fa7ULL -#define SHA384_H7 0x47b5481dbefa4fa4ULL - -#define SHA512_H0 0x6a09e667f3bcc908ULL -#define SHA512_H1 0xbb67ae8584caa73bULL -#define SHA512_H2 0x3c6ef372fe94f82bULL -#define SHA512_H3 0xa54ff53a5f1d36f1ULL -#define SHA512_H4 0x510e527fade682d1ULL -#define SHA512_H5 0x9b05688c2b3e6c1fULL -#define SHA512_H6 0x1f83d9abfb41bd6bULL -#define SHA512_H7 0x5be0cd19137e2179ULL - -extern const u8 sha1_zero_message_hash[SHA1_DIGEST_SIZE]; - -extern const u8 sha224_zero_message_hash[SHA224_DIGEST_SIZE]; - -extern const u8 sha256_zero_message_hash[SHA256_DIGEST_SIZE]; - -extern const u8 sha384_zero_message_hash[SHA384_DIGEST_SIZE]; - -extern const u8 sha512_zero_message_hash[SHA512_DIGEST_SIZE]; - -struct sha1_state { - u32 state[SHA1_DIGEST_SIZE / 4]; - u64 count; - u8 buffer[SHA1_BLOCK_SIZE]; -}; - -struct sha256_state { - u32 state[SHA256_DIGEST_SIZE / 4]; - u64 count; - u8 buf[SHA256_BLOCK_SIZE]; -}; - -struct sha512_state { - u64 state[SHA512_DIGEST_SIZE / 8]; - u64 count[2]; - u8 buf[SHA512_BLOCK_SIZE]; -}; - -struct shash_desc; - -extern int crypto_sha1_update(struct shash_desc *desc, const u8 *data, - unsigned int len); - -extern int crypto_sha1_finup(struct shash_desc *desc, const u8 *data, - unsigned int len, u8 *hash); - -extern int crypto_sha256_update(struct shash_desc *desc, const u8 *data, - unsigned int len); - -extern int crypto_sha256_finup(struct shash_desc *desc, const u8 *data, - unsigned int len, u8 *hash); - -extern int crypto_sha512_update(struct shash_desc *desc, const u8 *data, - unsigned int len); - -extern int crypto_sha512_finup(struct shash_desc *desc, const u8 *data, - unsigned int len, u8 *hash); - -/* - * An implementation of SHA-1's compression function. Don't use in new code! - * You shouldn't be using SHA-1, and even if you *have* to use SHA-1, this isn't - * the correct way to hash something with SHA-1 (use crypto_shash instead). - */ -#define SHA1_DIGEST_WORDS (SHA1_DIGEST_SIZE / 4) -#define SHA1_WORKSPACE_WORDS 16 -void sha1_init(__u32 *buf); -void sha1_transform(__u32 *digest, const char *data, __u32 *W); - -/* - * Stand-alone implementation of the SHA256 algorithm. It is designed to - * have as little dependencies as possible so it can be used in the - * kexec_file purgatory. In other cases you should generally use the - * hash APIs from include/crypto/hash.h. Especially when hashing large - * amounts of data as those APIs may be hw-accelerated. - * - * For details see lib/crypto/sha256.c - */ - -static inline void sha256_init(struct sha256_state *sctx) -{ - sctx->state[0] = SHA256_H0; - sctx->state[1] = SHA256_H1; - sctx->state[2] = SHA256_H2; - sctx->state[3] = SHA256_H3; - sctx->state[4] = SHA256_H4; - sctx->state[5] = SHA256_H5; - sctx->state[6] = SHA256_H6; - sctx->state[7] = SHA256_H7; - sctx->count = 0; -} -void sha256_update(struct sha256_state *sctx, const u8 *data, unsigned int len); -void sha256_final(struct sha256_state *sctx, u8 *out); -void sha256(const u8 *data, unsigned int len, u8 *out); - -static inline void sha224_init(struct sha256_state *sctx) -{ - sctx->state[0] = SHA224_H0; - sctx->state[1] = SHA224_H1; - sctx->state[2] = SHA224_H2; - sctx->state[3] = SHA224_H3; - sctx->state[4] = SHA224_H4; - sctx->state[5] = SHA224_H5; - sctx->state[6] = SHA224_H6; - sctx->state[7] = SHA224_H7; - sctx->count = 0; -} -void sha224_update(struct sha256_state *sctx, const u8 *data, unsigned int len); -void sha224_final(struct sha256_state *sctx, u8 *out); - -#endif diff --git a/include/crypto/sha1.h b/include/crypto/sha1.h new file mode 100644 index 000000000000..044ecea60ac8 --- /dev/null +++ b/include/crypto/sha1.h @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Common values for SHA-1 algorithms + */ + +#ifndef _CRYPTO_SHA1_H +#define _CRYPTO_SHA1_H + +#include + +#define SHA1_DIGEST_SIZE 20 +#define SHA1_BLOCK_SIZE 64 + +#define SHA1_H0 0x67452301UL +#define SHA1_H1 0xefcdab89UL +#define SHA1_H2 0x98badcfeUL +#define SHA1_H3 0x10325476UL +#define SHA1_H4 0xc3d2e1f0UL + +extern const u8 sha1_zero_message_hash[SHA1_DIGEST_SIZE]; + +struct sha1_state { + u32 state[SHA1_DIGEST_SIZE / 4]; + u64 count; + u8 buffer[SHA1_BLOCK_SIZE]; +}; + +struct shash_desc; + +extern int crypto_sha1_update(struct shash_desc *desc, const u8 *data, + unsigned int len); + +extern int crypto_sha1_finup(struct shash_desc *desc, const u8 *data, + unsigned int len, u8 *hash); + +/* + * An implementation of SHA-1's compression function. Don't use in new code! + * You shouldn't be using SHA-1, and even if you *have* to use SHA-1, this isn't + * the correct way to hash something with SHA-1 (use crypto_shash instead). + */ +#define SHA1_DIGEST_WORDS (SHA1_DIGEST_SIZE / 4) +#define SHA1_WORKSPACE_WORDS 16 +void sha1_init(__u32 *buf); +void sha1_transform(__u32 *digest, const char *data, __u32 *W); + +#endif /* _CRYPTO_SHA1_H */ diff --git a/include/crypto/sha1_base.h b/include/crypto/sha1_base.h index a5d6033efef7..2e0e7c3827d1 100644 --- a/include/crypto/sha1_base.h +++ b/include/crypto/sha1_base.h @@ -9,7 +9,7 @@ #define _CRYPTO_SHA1_BASE_H #include -#include +#include #include #include #include diff --git a/include/crypto/sha2.h b/include/crypto/sha2.h new file mode 100644 index 000000000000..2838f529f31e --- /dev/null +++ b/include/crypto/sha2.h @@ -0,0 +1,134 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Common values for SHA-2 algorithms + */ + +#ifndef _CRYPTO_SHA2_H +#define _CRYPTO_SHA2_H + +#include + +#define SHA224_DIGEST_SIZE 28 +#define SHA224_BLOCK_SIZE 64 + +#define SHA256_DIGEST_SIZE 32 +#define SHA256_BLOCK_SIZE 64 + +#define SHA384_DIGEST_SIZE 48 +#define SHA384_BLOCK_SIZE 128 + +#define SHA512_DIGEST_SIZE 64 +#define SHA512_BLOCK_SIZE 128 + +#define SHA224_H0 0xc1059ed8UL +#define SHA224_H1 0x367cd507UL +#define SHA224_H2 0x3070dd17UL +#define SHA224_H3 0xf70e5939UL +#define SHA224_H4 0xffc00b31UL +#define SHA224_H5 0x68581511UL +#define SHA224_H6 0x64f98fa7UL +#define SHA224_H7 0xbefa4fa4UL + +#define SHA256_H0 0x6a09e667UL +#define SHA256_H1 0xbb67ae85UL +#define SHA256_H2 0x3c6ef372UL +#define SHA256_H3 0xa54ff53aUL +#define SHA256_H4 0x510e527fUL +#define SHA256_H5 0x9b05688cUL +#define SHA256_H6 0x1f83d9abUL +#define SHA256_H7 0x5be0cd19UL + +#define SHA384_H0 0xcbbb9d5dc1059ed8ULL +#define SHA384_H1 0x629a292a367cd507ULL +#define SHA384_H2 0x9159015a3070dd17ULL +#define SHA384_H3 0x152fecd8f70e5939ULL +#define SHA384_H4 0x67332667ffc00b31ULL +#define SHA384_H5 0x8eb44a8768581511ULL +#define SHA384_H6 0xdb0c2e0d64f98fa7ULL +#define SHA384_H7 0x47b5481dbefa4fa4ULL + +#define SHA512_H0 0x6a09e667f3bcc908ULL +#define SHA512_H1 0xbb67ae8584caa73bULL +#define SHA512_H2 0x3c6ef372fe94f82bULL +#define SHA512_H3 0xa54ff53a5f1d36f1ULL +#define SHA512_H4 0x510e527fade682d1ULL +#define SHA512_H5 0x9b05688c2b3e6c1fULL +#define SHA512_H6 0x1f83d9abfb41bd6bULL +#define SHA512_H7 0x5be0cd19137e2179ULL + +extern const u8 sha224_zero_message_hash[SHA224_DIGEST_SIZE]; + +extern const u8 sha256_zero_message_hash[SHA256_DIGEST_SIZE]; + +extern const u8 sha384_zero_message_hash[SHA384_DIGEST_SIZE]; + +extern const u8 sha512_zero_message_hash[SHA512_DIGEST_SIZE]; + +struct sha256_state { + u32 state[SHA256_DIGEST_SIZE / 4]; + u64 count; + u8 buf[SHA256_BLOCK_SIZE]; +}; + +struct sha512_state { + u64 state[SHA512_DIGEST_SIZE / 8]; + u64 count[2]; + u8 buf[SHA512_BLOCK_SIZE]; +}; + +struct shash_desc; + +extern int crypto_sha256_update(struct shash_desc *desc, const u8 *data, + unsigned int len); + +extern int crypto_sha256_finup(struct shash_desc *desc, const u8 *data, + unsigned int len, u8 *hash); + +extern int crypto_sha512_update(struct shash_desc *desc, const u8 *data, + unsigned int len); + +extern int crypto_sha512_finup(struct shash_desc *desc, const u8 *data, + unsigned int len, u8 *hash); + +/* + * Stand-alone implementation of the SHA256 algorithm. It is designed to + * have as little dependencies as possible so it can be used in the + * kexec_file purgatory. In other cases you should generally use the + * hash APIs from include/crypto/hash.h. Especially when hashing large + * amounts of data as those APIs may be hw-accelerated. + * + * For details see lib/crypto/sha256.c + */ + +static inline void sha256_init(struct sha256_state *sctx) +{ + sctx->state[0] = SHA256_H0; + sctx->state[1] = SHA256_H1; + sctx->state[2] = SHA256_H2; + sctx->state[3] = SHA256_H3; + sctx->state[4] = SHA256_H4; + sctx->state[5] = SHA256_H5; + sctx->state[6] = SHA256_H6; + sctx->state[7] = SHA256_H7; + sctx->count = 0; +} +void sha256_update(struct sha256_state *sctx, const u8 *data, unsigned int len); +void sha256_final(struct sha256_state *sctx, u8 *out); +void sha256(const u8 *data, unsigned int len, u8 *out); + +static inline void sha224_init(struct sha256_state *sctx) +{ + sctx->state[0] = SHA224_H0; + sctx->state[1] = SHA224_H1; + sctx->state[2] = SHA224_H2; + sctx->state[3] = SHA224_H3; + sctx->state[4] = SHA224_H4; + sctx->state[5] = SHA224_H5; + sctx->state[6] = SHA224_H6; + sctx->state[7] = SHA224_H7; + sctx->count = 0; +} +void sha224_update(struct sha256_state *sctx, const u8 *data, unsigned int len); +void sha224_final(struct sha256_state *sctx, u8 *out); + +#endif /* _CRYPTO_SHA2_H */ diff --git a/include/crypto/sha256_base.h b/include/crypto/sha256_base.h index 93f9fd21cc06..76173c613058 100644 --- a/include/crypto/sha256_base.h +++ b/include/crypto/sha256_base.h @@ -9,7 +9,7 @@ #define _CRYPTO_SHA256_BASE_H #include -#include +#include #include #include #include diff --git a/include/crypto/sha512_base.h b/include/crypto/sha512_base.h index 93ab73baa38e..b370b3340b16 100644 --- a/include/crypto/sha512_base.h +++ b/include/crypto/sha512_base.h @@ -9,7 +9,7 @@ #define _CRYPTO_SHA512_BASE_H #include -#include +#include #include #include #include diff --git a/include/linux/ccp.h b/include/linux/ccp.h index a5dfbaf2470d..868924dec5a1 100644 --- a/include/linux/ccp.h +++ b/include/linux/ccp.h @@ -15,7 +15,8 @@ #include #include #include -#include +#include +#include struct ccp_device; struct ccp_cmd; diff --git a/include/linux/filter.h b/include/linux/filter.h index 72d62cbc1578..6c00140538b9 100644 --- a/include/linux/filter.h +++ b/include/linux/filter.h @@ -21,7 +21,7 @@ #include #include #include -#include +#include #include diff --git a/include/linux/purgatory.h b/include/linux/purgatory.h index b950e961cfa8..d7dc1559427f 100644 --- a/include/linux/purgatory.h +++ b/include/linux/purgatory.h @@ -3,7 +3,7 @@ #define _LINUX_PURGATORY_H #include -#include +#include #include struct kexec_sha_region { diff --git a/kernel/crash_core.c b/kernel/crash_core.c index 106e4500fd53..4fcfe0b70c4e 100644 --- a/kernel/crash_core.c +++ b/kernel/crash_core.c @@ -11,7 +11,7 @@ #include #include -#include +#include /* vmcoreinfo stuff */ unsigned char *vmcoreinfo_data; diff --git a/kernel/kexec_core.c b/kernel/kexec_core.c index 8798a8183974..4f8efc278aa7 100644 --- a/kernel/kexec_core.c +++ b/kernel/kexec_core.c @@ -42,7 +42,6 @@ #include #include -#include #include "kexec_internal.h" DEFINE_MUTEX(kexec_mutex); diff --git a/kernel/kexec_file.c b/kernel/kexec_file.c index e21f6b9234f7..b02086d70492 100644 --- a/kernel/kexec_file.c +++ b/kernel/kexec_file.c @@ -20,7 +20,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/lib/crypto/sha256.c b/lib/crypto/sha256.c index cdef37c05972..72a4b0b1df28 100644 --- a/lib/crypto/sha256.c +++ b/lib/crypto/sha256.c @@ -15,7 +15,7 @@ #include #include #include -#include +#include #include static const u32 SHA256_K[] = { diff --git a/lib/digsig.c b/lib/digsig.c index e0627c3e53b2..04b5e55ed95f 100644 --- a/lib/digsig.c +++ b/lib/digsig.c @@ -20,7 +20,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/lib/sha1.c b/lib/sha1.c index 49257a915bb6..9bd1935a1472 100644 --- a/lib/sha1.c +++ b/lib/sha1.c @@ -9,7 +9,7 @@ #include #include #include -#include +#include #include /* diff --git a/net/ipv6/seg6_hmac.c b/net/ipv6/seg6_hmac.c index 85dddfe3a2c6..687d95dce085 100644 --- a/net/ipv6/seg6_hmac.c +++ b/net/ipv6/seg6_hmac.c @@ -35,7 +35,6 @@ #include #include -#include #include #include #include diff --git a/net/mptcp/crypto.c b/net/mptcp/crypto.c index 05d398d3fde4..b472dc149856 100644 --- a/net/mptcp/crypto.c +++ b/net/mptcp/crypto.c @@ -21,7 +21,7 @@ */ #include -#include +#include #include #include "protocol.h" diff --git a/net/mptcp/options.c b/net/mptcp/options.c index a044dd43411d..90cd52df99a6 100644 --- a/net/mptcp/options.c +++ b/net/mptcp/options.c @@ -7,7 +7,7 @@ #define pr_fmt(fmt) "MPTCP: " fmt #include -#include +#include #include #include #include "protocol.h" diff --git a/net/mptcp/subflow.c b/net/mptcp/subflow.c index ac4a1fe3550b..b229ae914d76 100644 --- a/net/mptcp/subflow.c +++ b/net/mptcp/subflow.c @@ -10,7 +10,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/security/integrity/integrity.h b/security/integrity/integrity.h index 413c803c5208..547425c20e11 100644 --- a/security/integrity/integrity.h +++ b/security/integrity/integrity.h @@ -14,7 +14,7 @@ #include #include -#include +#include #include #include diff --git a/security/keys/encrypted-keys/encrypted.c b/security/keys/encrypted-keys/encrypted.c index 192e531c146f..87432b35d771 100644 --- a/security/keys/encrypted-keys/encrypted.c +++ b/security/keys/encrypted-keys/encrypted.c @@ -29,7 +29,7 @@ #include #include #include -#include +#include #include #include "encrypted.h" diff --git a/security/keys/trusted-keys/trusted_tpm1.c b/security/keys/trusted-keys/trusted_tpm1.c index b9fe02e5f84f..74d82093cbaa 100644 --- a/security/keys/trusted-keys/trusted_tpm1.c +++ b/security/keys/trusted-keys/trusted_tpm1.c @@ -22,7 +22,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/sound/soc/codecs/cros_ec_codec.c b/sound/soc/codecs/cros_ec_codec.c index 28f039adfa13..58894bf47514 100644 --- a/sound/soc/codecs/cros_ec_codec.c +++ b/sound/soc/codecs/cros_ec_codec.c @@ -8,7 +8,7 @@ * EC for audio function. */ -#include +#include #include #include #include -- cgit v1.2.3-59-g8ed1b From 358afb8b746d4a7ebaeeeaab7a1523895a8572c2 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Thu, 29 Oct 2020 14:40:18 +0100 Subject: ARM: dts: rpi-4: disable wifi frequencies The RPi4 WiFi chip and HDMI outputs have some frequency overlap with crosstalk around 2.4GHz. Let's mark it as such so we can use some evasive maneuvers. Signed-off-by: Maxime Ripard Signed-off-by: Nicolas Saenz Julienne Link: https://lore.kernel.org/r/20201029134018.1948636-3-maxime@cerno.tech --- arch/arm/boot/dts/bcm2711-rpi-4-b.dts | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/bcm2711-rpi-4-b.dts b/arch/arm/boot/dts/bcm2711-rpi-4-b.dts index 09a1182c2936..403bacf986eb 100644 --- a/arch/arm/boot/dts/bcm2711-rpi-4-b.dts +++ b/arch/arm/boot/dts/bcm2711-rpi-4-b.dts @@ -181,12 +181,14 @@ &hdmi0 { clocks = <&firmware_clocks 13>, <&firmware_clocks 14>, <&dvp 0>, <&clk_27MHz>; clock-names = "hdmi", "bvb", "audio", "cec"; + wifi-2.4ghz-coexistence; status = "okay"; }; &hdmi1 { clocks = <&firmware_clocks 13>, <&firmware_clocks 14>, <&dvp 1>, <&clk_27MHz>; clock-names = "hdmi", "bvb", "audio", "cec"; + wifi-2.4ghz-coexistence; status = "okay"; }; -- cgit v1.2.3-59-g8ed1b From 278407a53c3b33fb820332c4d39eb39316c3879a Mon Sep 17 00:00:00 2001 From: Pavel Hofman Date: Fri, 20 Nov 2020 17:39:20 +0100 Subject: ARM: dts: bcm283x: increase dwc2's RX FIFO size The previous version of the dwc2 overlay set the RX FIFO size to 256 4-byte words. This is not enough for 1024 bytes of the largest isochronous high speed packet allowed, because it doesn't take into account extra space needed by dwc2. RX FIFO's size is calculated based on the following (in 4byte words): - 13 locations for SETUP packets 5*n + 8 for Slave and Buffer DMA mode where n is number of control endpoints which is 1 on the bcm283x core - 1 location for Global OUT NAK - 2 * 257 locations for status information and the received packet. Typically two spaces are recommended so that when the previous packet is being transferred to AHB, the USB can receive the subsequent packet. - 10 * 1 location for transfer complete status for last packet of each endpoint. The bcm283x core has 5 IN and 5 OUT EPs - 10 * 1 additional location for EPDisable status for each endpoint - 5 * 2 additional locations are recommended for each OUT endpoint Total is 558 locations. Signed-off-by: Phil Elwell Signed-off-by: Pavel Hofman Signed-off-by: Nicolas Saenz Julienne Link: https://lore.kernel.org/r/e9e7d070-593c-122f-3a5c-2435bb147ab2@ivitera.com/ --- arch/arm/boot/dts/bcm283x-rpi-usb-otg.dtsi | 2 +- arch/arm/boot/dts/bcm283x-rpi-usb-peripheral.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/bcm283x-rpi-usb-otg.dtsi b/arch/arm/boot/dts/bcm283x-rpi-usb-otg.dtsi index e2fd9610e125..20322de2f8bf 100644 --- a/arch/arm/boot/dts/bcm283x-rpi-usb-otg.dtsi +++ b/arch/arm/boot/dts/bcm283x-rpi-usb-otg.dtsi @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 &usb { dr_mode = "otg"; - g-rx-fifo-size = <256>; + g-rx-fifo-size = <558>; g-np-tx-fifo-size = <32>; /* * According to dwc2 the sum of all device EP diff --git a/arch/arm/boot/dts/bcm283x-rpi-usb-peripheral.dtsi b/arch/arm/boot/dts/bcm283x-rpi-usb-peripheral.dtsi index 0ff0e9e25327..1409d1b559c1 100644 --- a/arch/arm/boot/dts/bcm283x-rpi-usb-peripheral.dtsi +++ b/arch/arm/boot/dts/bcm283x-rpi-usb-peripheral.dtsi @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 &usb { dr_mode = "peripheral"; - g-rx-fifo-size = <256>; + g-rx-fifo-size = <558>; g-np-tx-fifo-size = <32>; g-tx-fifo-size = <256 256 512 512 512 768 768>; }; -- cgit v1.2.3-59-g8ed1b From 424c9102fa7b2a5c15afe47fd14278c849f4eefb Mon Sep 17 00:00:00 2001 From: Kees Cook Date: Tue, 27 Oct 2020 12:26:58 -0700 Subject: arm: Enable seccomp architecture tracking To enable seccomp constant action bitmaps, we need to have a static mapping to the audit architecture and system call table size. Add these for arm. Signed-off-by: Kees Cook --- arch/arm/include/asm/Kbuild | 1 - arch/arm/include/asm/seccomp.h | 11 +++++++++++ 2 files changed, 11 insertions(+), 1 deletion(-) create mode 100644 arch/arm/include/asm/seccomp.h (limited to 'arch/arm') diff --git a/arch/arm/include/asm/Kbuild b/arch/arm/include/asm/Kbuild index 383635b68763..4a0848aef207 100644 --- a/arch/arm/include/asm/Kbuild +++ b/arch/arm/include/asm/Kbuild @@ -4,7 +4,6 @@ generic-y += extable.h generic-y += flat.h generic-y += local64.h generic-y += parport.h -generic-y += seccomp.h generated-y += mach-types.h generated-y += unistd-nr.h diff --git a/arch/arm/include/asm/seccomp.h b/arch/arm/include/asm/seccomp.h new file mode 100644 index 000000000000..e9ad0f37d2ba --- /dev/null +++ b/arch/arm/include/asm/seccomp.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#ifndef _ASM_SECCOMP_H +#define _ASM_SECCOMP_H + +#include + +#define SECCOMP_ARCH_NATIVE AUDIT_ARCH_ARM +#define SECCOMP_ARCH_NATIVE_NR NR_syscalls +#define SECCOMP_ARCH_NATIVE_NAME "arm" + +#endif /* _ASM_SECCOMP_H */ -- cgit v1.2.3-59-g8ed1b From f527cb6f3345f7faa8e61dd9f3c437437327428c Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Mon, 9 Nov 2020 11:41:01 -0800 Subject: ARM: dts: BCM5301X: Update Ethernet switch node name Update the switch unit name from srab to ethernet-switch, allowing us to fix warnings such as: CHECK arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dt.yaml arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dt.yaml: srab@18007000: $nodename:0: 'srab@18007000' does not match '^(ethernet-)?switch(@.*)?$' From schema: Documentation/devicetree/bindings/net/dsa/b53.yaml Reviewed-by: Vladimir Oltean Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm5301x.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/bcm5301x.dtsi b/arch/arm/boot/dts/bcm5301x.dtsi index 90c09c48721b..b8d2e8d28482 100644 --- a/arch/arm/boot/dts/bcm5301x.dtsi +++ b/arch/arm/boot/dts/bcm5301x.dtsi @@ -483,7 +483,7 @@ }; }; - srab: srab@18007000 { + srab: ethernet-switch@18007000 { compatible = "brcm,bcm5301x-srab"; reg = <0x18007000 0x1000>; -- cgit v1.2.3-59-g8ed1b From 953efcb0c0234f8c488ebd4090378e949d6ba78b Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Mon, 9 Nov 2020 16:42:09 -0800 Subject: ARM: dts: BCM5301X: Add a default compatible for switch node MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Provide a default compatible string which is based on the 53011 SRAB compatible by default. The 4709 and 47094 default to the 53012 SRAB compatible. This allows us to have sane defaults and silences the following warnings: arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dt.yaml: ethernet-switch@18007000: compatible: 'oneOf' conditional failed, one must be fixed: ['brcm,bcm5301x-srab'] is too short 'brcm,bcm5325' was expected 'brcm,bcm53115' was expected 'brcm,bcm53125' was expected 'brcm,bcm53128' was expected 'brcm,bcm5365' was expected 'brcm,bcm5395' was expected 'brcm,bcm5389' was expected 'brcm,bcm5397' was expected 'brcm,bcm5398' was expected 'brcm,bcm11360-srab' was expected 'brcm,bcm5301x-srab' is not one of ['brcm,bcm53010-srab', 'brcm,bcm53011-srab', 'brcm,bcm53012-srab', 'brcm,bcm53018-srab', 'brcm,bcm53019-srab'] 'brcm,bcm5301x-srab' is not one of ['brcm,bcm11404-srab', 'brcm,bcm11407-srab', 'brcm,bcm11409-srab', 'brcm,bcm58310-srab', 'brcm,bcm58311-srab', 'brcm,bcm58313-srab'] 'brcm,bcm5301x-srab' is not one of ['brcm,bcm58522-srab', 'brcm,bcm58523-srab', 'brcm,bcm58525-srab', 'brcm,bcm58622-srab', 'brcm,bcm58623-srab', 'brcm,bcm58625-srab', 'brcm,bcm88312-srab'] 'brcm,bcm5301x-srab' is not one of ['brcm,bcm3384-switch', 'brcm,bcm6328-switch', 'brcm,bcm6368-switch'] From schema: Documentation/devicetree/bindings/net/dsa/b53.yaml Acked-by: Rafał Miłecki Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm4709.dtsi | 4 ++++ arch/arm/boot/dts/bcm47094.dtsi | 4 ++++ arch/arm/boot/dts/bcm5301x.dtsi | 2 +- 3 files changed, 9 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/bcm4709.dtsi b/arch/arm/boot/dts/bcm4709.dtsi index e1bb8661955f..cba3d910bed8 100644 --- a/arch/arm/boot/dts/bcm4709.dtsi +++ b/arch/arm/boot/dts/bcm4709.dtsi @@ -9,3 +9,7 @@ clock-frequency = <125000000>; status = "okay"; }; + +&srab { + compatible = "brcm,bcm53012-srab", "brcm,bcm5301x-srab"; +}; diff --git a/arch/arm/boot/dts/bcm47094.dtsi b/arch/arm/boot/dts/bcm47094.dtsi index 747ca030435f..2a8f7312d1be 100644 --- a/arch/arm/boot/dts/bcm47094.dtsi +++ b/arch/arm/boot/dts/bcm47094.dtsi @@ -25,3 +25,7 @@ clock-frequency = <125000000>; status = "okay"; }; + +&srab { + compatible = "brcm,bcm53012-srab", "brcm,bcm5301x-srab"; +}; diff --git a/arch/arm/boot/dts/bcm5301x.dtsi b/arch/arm/boot/dts/bcm5301x.dtsi index b8d2e8d28482..a4ab3aabf8b0 100644 --- a/arch/arm/boot/dts/bcm5301x.dtsi +++ b/arch/arm/boot/dts/bcm5301x.dtsi @@ -484,7 +484,7 @@ }; srab: ethernet-switch@18007000 { - compatible = "brcm,bcm5301x-srab"; + compatible = "brcm,bcm53011-srab", "brcm,bcm5301x-srab"; reg = <0x18007000 0x1000>; status = "disabled"; -- cgit v1.2.3-59-g8ed1b From fd577b41421bc24e2d04cab96d387301b649eb14 Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Mon, 9 Nov 2020 17:20:17 -0800 Subject: ARM: dts: BCM5301X: Provide defaults ports container node MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Provide an empty 'ports' container node with the correct #address-cells and #size-cells properties. This silences the following warning: arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dt.yaml: ethernet-switch@18007000: 'oneOf' conditional failed, one must be fixed: 'ports' is a required property 'ethernet-ports' is a required property From schema: Documentation/devicetree/bindings/net/dsa/b53.yaml Acked-by: Rafał Miłecki Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm4708-luxul-xap-1510.dts | 3 --- arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts | 3 --- arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts | 3 --- arch/arm/boot/dts/bcm47081-luxul-xap-1410.dts | 3 --- arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts | 3 --- arch/arm/boot/dts/bcm47094-linksys-panamera.dts | 3 --- arch/arm/boot/dts/bcm47094-luxul-xap-1610.dts | 3 --- arch/arm/boot/dts/bcm47094-luxul-xwc-2000.dts | 3 --- arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts | 3 --- arch/arm/boot/dts/bcm47094-luxul-xwr-3150-v1.dts | 3 --- arch/arm/boot/dts/bcm5301x.dtsi | 4 ++++ arch/arm/boot/dts/bcm953012er.dts | 3 --- 12 files changed, 4 insertions(+), 33 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/bcm4708-luxul-xap-1510.dts b/arch/arm/boot/dts/bcm4708-luxul-xap-1510.dts index 7f07b78c1ac3..5b4a481be4f4 100644 --- a/arch/arm/boot/dts/bcm4708-luxul-xap-1510.dts +++ b/arch/arm/boot/dts/bcm4708-luxul-xap-1510.dts @@ -61,9 +61,6 @@ status = "okay"; ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { reg = <0>; label = "poe"; diff --git a/arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts b/arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts index 548faa0c44c8..8636600385fd 100644 --- a/arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts +++ b/arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts @@ -68,9 +68,6 @@ status = "okay"; ports { - #address-cells = <1>; - #size-cells = <0>; - port@4 { reg = <4>; label = "lan"; diff --git a/arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts b/arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts index abd35a518046..51c64f0b2560 100644 --- a/arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts +++ b/arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts @@ -122,9 +122,6 @@ status = "okay"; ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { reg = <0>; label = "lan4"; diff --git a/arch/arm/boot/dts/bcm47081-luxul-xap-1410.dts b/arch/arm/boot/dts/bcm47081-luxul-xap-1410.dts index 944e81cab338..68aaf0af3945 100644 --- a/arch/arm/boot/dts/bcm47081-luxul-xap-1410.dts +++ b/arch/arm/boot/dts/bcm47081-luxul-xap-1410.dts @@ -61,9 +61,6 @@ status = "okay"; ports { - #address-cells = <1>; - #size-cells = <0>; - port@4 { reg = <4>; label = "poe"; diff --git a/arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts b/arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts index d1ae7dc10775..432254383769 100644 --- a/arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts +++ b/arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts @@ -109,9 +109,6 @@ status = "okay"; ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { reg = <0>; label = "lan4"; diff --git a/arch/arm/boot/dts/bcm47094-linksys-panamera.dts b/arch/arm/boot/dts/bcm47094-linksys-panamera.dts index 3bb3fe5bfbf8..3725f2b0d60b 100644 --- a/arch/arm/boot/dts/bcm47094-linksys-panamera.dts +++ b/arch/arm/boot/dts/bcm47094-linksys-panamera.dts @@ -201,9 +201,6 @@ dsa,member = <0 0>; ports { - #address-cells = <1>; - #size-cells = <0>; - port@1 { reg = <1>; label = "lan7"; diff --git a/arch/arm/boot/dts/bcm47094-luxul-xap-1610.dts b/arch/arm/boot/dts/bcm47094-luxul-xap-1610.dts index 068e384b8ab7..6fa101f0a90d 100644 --- a/arch/arm/boot/dts/bcm47094-luxul-xap-1610.dts +++ b/arch/arm/boot/dts/bcm47094-luxul-xap-1610.dts @@ -59,9 +59,6 @@ status = "okay"; ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { reg = <0>; label = "poe"; diff --git a/arch/arm/boot/dts/bcm47094-luxul-xwc-2000.dts b/arch/arm/boot/dts/bcm47094-luxul-xwc-2000.dts index 9ae815ddbb4b..4f8d777ae18d 100644 --- a/arch/arm/boot/dts/bcm47094-luxul-xwc-2000.dts +++ b/arch/arm/boot/dts/bcm47094-luxul-xwc-2000.dts @@ -57,9 +57,6 @@ status = "okay"; ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { reg = <0>; label = "lan"; diff --git a/arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts b/arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts index a21b2d185596..e17e9a17fb00 100644 --- a/arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts +++ b/arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts @@ -108,9 +108,6 @@ status = "okay"; ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { reg = <0>; label = "lan4"; diff --git a/arch/arm/boot/dts/bcm47094-luxul-xwr-3150-v1.dts b/arch/arm/boot/dts/bcm47094-luxul-xwr-3150-v1.dts index a361aa8627d3..60cc87ecc7ec 100644 --- a/arch/arm/boot/dts/bcm47094-luxul-xwr-3150-v1.dts +++ b/arch/arm/boot/dts/bcm47094-luxul-xwr-3150-v1.dts @@ -83,9 +83,6 @@ status = "okay"; ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { reg = <0>; label = "lan4"; diff --git a/arch/arm/boot/dts/bcm5301x.dtsi b/arch/arm/boot/dts/bcm5301x.dtsi index a4ab3aabf8b0..7db72a2f1020 100644 --- a/arch/arm/boot/dts/bcm5301x.dtsi +++ b/arch/arm/boot/dts/bcm5301x.dtsi @@ -490,6 +490,10 @@ status = "disabled"; /* ports are defined in board DTS */ + ports { + #address-cells = <1>; + #size-cells = <0>; + }; }; rng: rng@18004000 { diff --git a/arch/arm/boot/dts/bcm953012er.dts b/arch/arm/boot/dts/bcm953012er.dts index 957468224622..52feca0fb906 100644 --- a/arch/arm/boot/dts/bcm953012er.dts +++ b/arch/arm/boot/dts/bcm953012er.dts @@ -69,9 +69,6 @@ status = "okay"; ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { reg = <0>; label = "port0"; -- cgit v1.2.3-59-g8ed1b From fd66cd0d79cb836badecb91fdd19afd32afbb443 Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Mon, 9 Nov 2020 12:02:08 -0800 Subject: ARM: dts: NSP: Update ethernet switch node name Update the switch unit name from srab to ethernet-switch, allowing us to fix warnings such as: CHECK arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dt.yaml arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dt.yaml: srab@18007000: $nodename:0: 'srab@18007000' does not match '^(ethernet-)?switch(@.*)?$' From schema: Documentation/devicetree/bindings/net/dsa/b53.yaml Reviewed-by: Vladimir Oltean Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm-nsp.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/bcm-nsp.dtsi b/arch/arm/boot/dts/bcm-nsp.dtsi index e895f7cb8c9f..e7d08959d5fe 100644 --- a/arch/arm/boot/dts/bcm-nsp.dtsi +++ b/arch/arm/boot/dts/bcm-nsp.dtsi @@ -385,7 +385,7 @@ clock-names = "apb_pclk"; }; - srab: srab@36000 { + srab: ethernet-switch@36000 { compatible = "brcm,nsp-srab"; reg = <0x36000 0x1000>, <0x3f308 0x8>, -- cgit v1.2.3-59-g8ed1b From 8b0235d1deace8f1bd8cdd149d698fee3974fdf4 Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Mon, 9 Nov 2020 12:06:15 -0800 Subject: ARM: dts: NSP: Fix Ethernet switch SGMII register name The register name should be "sgmii_config", not "sgmii", this is not a functional change since no code is currently looking for that register by name (or at all). Reviewed-by: Vladimir Oltean Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm-nsp.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/bcm-nsp.dtsi b/arch/arm/boot/dts/bcm-nsp.dtsi index e7d08959d5fe..09fd7e55c069 100644 --- a/arch/arm/boot/dts/bcm-nsp.dtsi +++ b/arch/arm/boot/dts/bcm-nsp.dtsi @@ -390,7 +390,7 @@ reg = <0x36000 0x1000>, <0x3f308 0x8>, <0x3f410 0xc>; - reg-names = "srab", "mux_config", "sgmii"; + reg-names = "srab", "mux_config", "sgmii_config"; interrupts = , , , -- cgit v1.2.3-59-g8ed1b From 42791b317db4cda36751f57bada27857849811d3 Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Mon, 9 Nov 2020 17:41:32 -0800 Subject: ARM: dts: NSP: Add a SRAB compatible string for each board Provide a valid compatible string for the Ethernet switch node based on the board including the switch. This allows us to have sane defaults and silences the following warnings: arch/arm/boot/dts/bcm958522er.dt.yaml: ethernet-switch@36000: compatible: 'oneOf' conditional failed, one must be fixed: ['brcm,bcm5301x-srab'] is too short 'brcm,bcm5325' was expected 'brcm,bcm53115' was expected 'brcm,bcm53125' was expected 'brcm,bcm53128' was expected 'brcm,bcm5365' was expected 'brcm,bcm5395' was expected 'brcm,bcm5389' was expected 'brcm,bcm5397' was expected 'brcm,bcm5398' was expected 'brcm,bcm11360-srab' was expected 'brcm,bcm5301x-srab' is not one of ['brcm,bcm53010-srab', 'brcm,bcm53011-srab', 'brcm,bcm53012-srab', 'brcm,bcm53018-srab', 'brcm,bcm53019-srab'] 'brcm,bcm5301x-srab' is not one of ['brcm,bcm11404-srab', 'brcm,bcm11407-srab', 'brcm,bcm11409-srab', 'brcm,bcm58310-srab', 'brcm,bcm58311-srab', 'brcm,bcm58313-srab'] 'brcm,bcm5301x-srab' is not one of ['brcm,bcm58522-srab', 'brcm,bcm58523-srab', 'brcm,bcm58525-srab', 'brcm,bcm58622-srab', 'brcm,bcm58623-srab', 'brcm,bcm58625-srab', 'brcm,bcm88312-srab'] 'brcm,bcm5301x-srab' is not one of ['brcm,bcm3384-switch', 'brcm,bcm6328-switch', 'brcm,bcm6368-switch'] From schema: Documentation/devicetree/bindings/net/dsa/b53.yaml Reviewed-by: Vladimir Oltean Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm958522er.dts | 4 ++++ arch/arm/boot/dts/bcm958525er.dts | 4 ++++ arch/arm/boot/dts/bcm958525xmc.dts | 4 ++++ 3 files changed, 12 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/bcm958522er.dts b/arch/arm/boot/dts/bcm958522er.dts index 7be4c4e628e0..5443fc079e6e 100644 --- a/arch/arm/boot/dts/bcm958522er.dts +++ b/arch/arm/boot/dts/bcm958522er.dts @@ -178,3 +178,7 @@ &xhci { status = "okay"; }; + +&srab { + compatible = "brcm,bcm58522-srab", "brcm,nsp-srab"; +}; diff --git a/arch/arm/boot/dts/bcm958525er.dts b/arch/arm/boot/dts/bcm958525er.dts index e58ed7e95346..e1e3c26cef19 100644 --- a/arch/arm/boot/dts/bcm958525er.dts +++ b/arch/arm/boot/dts/bcm958525er.dts @@ -190,3 +190,7 @@ &xhci { status = "okay"; }; + +&srab { + compatible = "brcm,bcm58525-srab", "brcm,nsp-srab"; +}; diff --git a/arch/arm/boot/dts/bcm958525xmc.dts b/arch/arm/boot/dts/bcm958525xmc.dts index 21f922dc6019..f161ba2e7e5e 100644 --- a/arch/arm/boot/dts/bcm958525xmc.dts +++ b/arch/arm/boot/dts/bcm958525xmc.dts @@ -210,3 +210,7 @@ &xhci { status = "okay"; }; + +&srab { + compatible = "brcm,bcm58525-srab", "brcm,nsp-srab"; +}; -- cgit v1.2.3-59-g8ed1b From 51e40c25aa18d926a8eb1c07289d01611b21123a Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Mon, 9 Nov 2020 17:44:33 -0800 Subject: ARM: dts: NSP: Provide defaults ports container node Provide an empty 'ports' container node with the correct #address-cells and #size-cells properties. This silences the following warning: arch/arm/boot/dts/bcm958522er.dt.yaml: ethernet-switch@36000: 'oneOf' conditional failed, one must be fixed: 'ports' is a required property 'ethernet-ports' is a required property From schema: Documentation/devicetree/bindings/net/dsa/b53.yaml Reviewed-by: Vladimir Oltean Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm-nsp.dtsi | 4 ++++ arch/arm/boot/dts/bcm958622hr.dts | 3 --- arch/arm/boot/dts/bcm958623hr.dts | 3 --- arch/arm/boot/dts/bcm958625hr.dts | 3 --- arch/arm/boot/dts/bcm958625k.dts | 3 --- arch/arm/boot/dts/bcm988312hr.dts | 3 --- 6 files changed, 4 insertions(+), 15 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/bcm-nsp.dtsi b/arch/arm/boot/dts/bcm-nsp.dtsi index 09fd7e55c069..b4d2cc70afb1 100644 --- a/arch/arm/boot/dts/bcm-nsp.dtsi +++ b/arch/arm/boot/dts/bcm-nsp.dtsi @@ -420,6 +420,10 @@ status = "disabled"; /* ports are defined in board DTS */ + ports { + #address-cells = <1>; + #size-cells = <0>; + }; }; i2c0: i2c@38000 { diff --git a/arch/arm/boot/dts/bcm958622hr.dts b/arch/arm/boot/dts/bcm958622hr.dts index a49c2fd21f4a..83cb877d63db 100644 --- a/arch/arm/boot/dts/bcm958622hr.dts +++ b/arch/arm/boot/dts/bcm958622hr.dts @@ -176,9 +176,6 @@ status = "okay"; ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { label = "port0"; reg = <0>; diff --git a/arch/arm/boot/dts/bcm958623hr.dts b/arch/arm/boot/dts/bcm958623hr.dts index dd6dff6452b8..4e106ce1384a 100644 --- a/arch/arm/boot/dts/bcm958623hr.dts +++ b/arch/arm/boot/dts/bcm958623hr.dts @@ -180,9 +180,6 @@ status = "okay"; ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { label = "port0"; reg = <0>; diff --git a/arch/arm/boot/dts/bcm958625hr.dts b/arch/arm/boot/dts/bcm958625hr.dts index a71371b4065e..cda6cc281e18 100644 --- a/arch/arm/boot/dts/bcm958625hr.dts +++ b/arch/arm/boot/dts/bcm958625hr.dts @@ -195,9 +195,6 @@ status = "okay"; ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { label = "port0"; reg = <0>; diff --git a/arch/arm/boot/dts/bcm958625k.dts b/arch/arm/boot/dts/bcm958625k.dts index 7782b61c51a1..ffbff0014c65 100644 --- a/arch/arm/boot/dts/bcm958625k.dts +++ b/arch/arm/boot/dts/bcm958625k.dts @@ -216,9 +216,6 @@ status = "okay"; ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { label = "port0"; reg = <0>; diff --git a/arch/arm/boot/dts/bcm988312hr.dts b/arch/arm/boot/dts/bcm988312hr.dts index edd0f630e025..3fd39c479a3c 100644 --- a/arch/arm/boot/dts/bcm988312hr.dts +++ b/arch/arm/boot/dts/bcm988312hr.dts @@ -184,9 +184,6 @@ status = "okay"; ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { label = "port0"; reg = <0>; -- cgit v1.2.3-59-g8ed1b From ea270ef71db64715cb46d15b85f30e77775ff88a Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Sat, 21 Nov 2020 19:26:32 -0800 Subject: ARM: dts: keystone-k2g-evm: add HDMI and analog audio data The board is using McASP2 for both analog (tlv320aic3106) and HDMI (SiI9022) audio. 12.288MHz oscillator provides the MCLK for both aic3106 and SiI9022. Signed-off-by: Peter Ujfalusi Signed-off-by: Santosh Shilimkar --- arch/arm/boot/dts/keystone-k2g-evm.dts | 112 +++++++++++++++++++++++++++++++++ 1 file changed, 112 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/keystone-k2g-evm.dts b/arch/arm/boot/dts/keystone-k2g-evm.dts index 8b3d64c913d8..14e26a4fd62a 100644 --- a/arch/arm/boot/dts/keystone-k2g-evm.dts +++ b/arch/arm/boot/dts/keystone-k2g-evm.dts @@ -46,6 +46,14 @@ regulator-always-on; }; + vcc1v8_ldo2_reg: fixedregulator-vcc1v8-ldo2 { + compatible = "regulator-fixed"; + regulator-name = "ldo2"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + hdmi: connector { compatible = "hdmi-connector"; label = "hdmi"; @@ -58,6 +66,57 @@ }; }; }; + + aud_mclk: aud_mclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <12288000>; + }; + + sound0: sound@0 { + compatible = "simple-audio-card"; + simple-audio-card,name = "K2G-EVM"; + simple-audio-card,widgets = + "Headphone", "Headphone Jack", + "Line", "Line In"; + simple-audio-card,routing = + "Headphone Jack", "HPLOUT", + "Headphone Jack", "HPROUT", + "LINE1L", "Line In", + "LINE1R", "Line In"; + + simple-audio-card,dai-link@0 { + format = "i2s"; + bitclock-master = <&sound0_0_master>; + frame-master = <&sound0_0_master>; + sound0_0_master: cpu { + sound-dai = <&mcasp2>; + clocks = <&k2g_clks 0x6 1>; + system-clock-direction-out; + }; + + codec { + sound-dai = <&tlv320aic3106>; + clocks = <&aud_mclk>; + }; + }; + + simple-audio-card,dai-link@1 { + format = "i2s"; + bitclock-master = <&sound0_1_master>; + frame-master = <&sound0_1_master>; + sound0_1_master: cpu { + sound-dai = <&mcasp2>; + clocks = <&k2g_clks 0x6 1>; + system-clock-direction-out; + }; + + codec { + sound-dai = <&sii9022>; + clocks = <&aud_mclk>; + }; + }; + }; }; &k2g_pinctrl { @@ -214,6 +273,15 @@ K2G_CORE_IOPAD(0x10e8) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssfid.dssfid */ >; }; + + mcasp2_pins: pinmux_mcasp2_pins { + pinctrl-single,pins = < + K2G_CORE_IOPAD(0x1234) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE4) /* pr0_pru_gpo2.mcasp2_axr2 */ + K2G_CORE_IOPAD(0x1238) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE4) /* pr0_pru_gpo3.mcasp2_axr3 */ + K2G_CORE_IOPAD(0x1254) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE4) /* pr0_pru_gpo10.mcasp2_afsx */ + K2G_CORE_IOPAD(0x125c) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE4) /* pr0_pru_gpo12.mcasp2_aclkx */ + >; + }; }; &uart0 { @@ -423,6 +491,10 @@ compatible = "sil,sii9022"; reg = <0x3b>; + sil,i2s-data-lanes = < 0 >; + clocks = <&aud_mclk>; + clock-names = "mclk"; + ports { #address-cells = <1>; #size-cells = <0>; @@ -444,6 +516,19 @@ }; }; }; + + tlv320aic3106: tlv320aic3106@1b { + #sound-dai-cells = <0>; + compatible = "ti,tlv320aic3106"; + reg = <0x1b>; + status = "okay"; + + /* Regulators */ + AVDD-supply = <&vcc3v3_dcin_reg>; + IOVDD-supply = <&vcc3v3_dcin_reg>; + DRVDD-supply = <&vcc3v3_dcin_reg>; + DVDD-supply = <&vcc1v8_ldo2_reg>; + }; }; &dss { @@ -458,3 +543,30 @@ }; }; }; + +&k2g_clks { + /* on the board 22.5792MHz is connected to AUDOSC_IN */ + assigned-clocks = <&k2g_clks 0x4c 2>; + assigned-clock-rates = <22579200>; +}; + +&mcasp2 { + #sound-dai-cells = <0>; + + pinctrl-names = "default"; + pinctrl-0 = <&mcasp2_pins>; + + assigned-clocks = <&k2g_clks 0x6 1>; + assigned-clock-parents = <&k2g_clks 0x6 2>; + + status = "okay"; + + op-mode = <0>; /* MCASP_IIS_MODE */ + tdm-slots = <2>; + /* 6 serializer */ + serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ + 0 0 1 2 0 0 // AXR2: TX, AXR3: rx + >; + tx-num-evt = <32>; + rx-num-evt = <32>; +}; -- cgit v1.2.3-59-g8ed1b From afbd0bdebe0d82c4846dbbce53625110889c5de8 Mon Sep 17 00:00:00 2001 From: Martin Jücker Date: Fri, 20 Nov 2020 17:00:54 +0100 Subject: ARM: dts: exynos: switch Atmel mxt reset GPIO to active low on P4 Note MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The reset GPIO logic of the Atmel maxtouch driver was changed to be active low at around the same time P4 Note device tree was accepted into the kernel. Adjust the configuration so that the touchscreen is in a usable state. Signed-off-by: Martin Jücker Link: https://lore.kernel.org/r/20201120160053.18942-1-martin.juecker@gmail.com Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos4412-p4note.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/exynos4412-p4note.dtsi b/arch/arm/boot/dts/exynos4412-p4note.dtsi index 0f8d4164a977..b2f9d5448a18 100644 --- a/arch/arm/boot/dts/exynos4412-p4note.dtsi +++ b/arch/arm/boot/dts/exynos4412-p4note.dtsi @@ -307,7 +307,7 @@ pinctrl-names = "default"; interrupt-parent = <&gpm2>; interrupts = <3 IRQ_TYPE_LEVEL_LOW>; - reset-gpios = <&gpm0 4 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpm0 4 GPIO_ACTIVE_LOW>; }; }; -- cgit v1.2.3-59-g8ed1b From ae04aad75b3718b84df559bb0352f27695045fe0 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 17 Nov 2020 11:30:16 +0100 Subject: ARM: shmobile: r8a7778: Introduce HPBREG_BASE Replace the hardcoded address of the HPB Register block by a macro. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20201117103022.2136527-2-geert+renesas@glider.be --- arch/arm/mach-shmobile/setup-r8a7778.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-shmobile/setup-r8a7778.c b/arch/arm/mach-shmobile/setup-r8a7778.c index 2bc93f391bcf..819dbda47298 100644 --- a/arch/arm/mach-shmobile/setup-r8a7778.c +++ b/arch/arm/mach-shmobile/setup-r8a7778.c @@ -14,6 +14,8 @@ #include "common.h" +#define HPBREG_BASE 0xfe700000 + #define INT2SMSKCR0 0x82288 /* 0xfe782288 */ #define INT2SMSKCR1 0x8228c /* 0xfe78228c */ @@ -22,7 +24,7 @@ static void __init r8a7778_init_irq_dt(void) { - void __iomem *base = ioremap(0xfe700000, 0x00100000); + void __iomem *base = ioremap(HPBREG_BASE, 0x00100000); BUG_ON(!base); -- cgit v1.2.3-59-g8ed1b From caf67a935740d7a4e9a7b0a3176237ad22a677e8 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 17 Nov 2020 11:30:17 +0100 Subject: ARM: shmobile: r8a7779: Use ioremap() to map INTC2 registers Replace using the legacy IOMEM() macro to map various registers related to INTC2 configuration by ioremap(). Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20201117103022.2136527-3-geert+renesas@glider.be --- arch/arm/mach-shmobile/setup-r8a7779.c | 34 ++++++++++++++++++++-------------- 1 file changed, 20 insertions(+), 14 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-shmobile/setup-r8a7779.c b/arch/arm/mach-shmobile/setup-r8a7779.c index 86406e3f9b22..07c1bc96d4d9 100644 --- a/arch/arm/mach-shmobile/setup-r8a7779.c +++ b/arch/arm/mach-shmobile/setup-r8a7779.c @@ -38,30 +38,36 @@ static void __init r8a7779_map_io(void) iotable_init(r8a7779_io_desc, ARRAY_SIZE(r8a7779_io_desc)); } +#define HPBREG_BASE 0xfe700000 + /* IRQ */ -#define INT2SMSKCR0 IOMEM(0xfe7822a0) -#define INT2SMSKCR1 IOMEM(0xfe7822a4) -#define INT2SMSKCR2 IOMEM(0xfe7822a8) -#define INT2SMSKCR3 IOMEM(0xfe7822ac) -#define INT2SMSKCR4 IOMEM(0xfe7822b0) +#define INT2SMSKCR0 0x822a0 /* Interrupt Submask Clear Register 0 */ +#define INT2SMSKCR1 0x822a4 /* Interrupt Submask Clear Register 1 */ +#define INT2SMSKCR2 0x822a8 /* Interrupt Submask Clear Register 2 */ +#define INT2SMSKCR3 0x822ac /* Interrupt Submask Clear Register 3 */ +#define INT2SMSKCR4 0x822b0 /* Interrupt Submask Clear Register 4 */ -#define INT2NTSR0 IOMEM(0xfe700060) -#define INT2NTSR1 IOMEM(0xfe700064) +#define INT2NTSR0 0x00060 /* Interrupt Notification Select Register 0 */ +#define INT2NTSR1 0x00064 /* Interrupt Notification Select Register 1 */ static void __init r8a7779_init_irq_dt(void) { + void __iomem *base = ioremap(HPBREG_BASE, 0x00100000); + irqchip_init(); /* route all interrupts to ARM */ - __raw_writel(0xffffffff, INT2NTSR0); - __raw_writel(0x3fffffff, INT2NTSR1); + __raw_writel(0xffffffff, base + INT2NTSR0); + __raw_writel(0x3fffffff, base + INT2NTSR1); /* unmask all known interrupts in INTCS2 */ - __raw_writel(0xfffffff0, INT2SMSKCR0); - __raw_writel(0xfff7ffff, INT2SMSKCR1); - __raw_writel(0xfffbffdf, INT2SMSKCR2); - __raw_writel(0xbffffffc, INT2SMSKCR3); - __raw_writel(0x003fee3f, INT2SMSKCR4); + __raw_writel(0xfffffff0, base + INT2SMSKCR0); + __raw_writel(0xfff7ffff, base + INT2SMSKCR1); + __raw_writel(0xfffbffdf, base + INT2SMSKCR2); + __raw_writel(0xbffffffc, base + INT2SMSKCR3); + __raw_writel(0x003fee3f, base + INT2SMSKCR4); + + iounmap(base); } static const char *const r8a7779_compat_dt[] __initconst = { -- cgit v1.2.3-59-g8ed1b From 617ff9e657c4c4a6ffca325740e36d0d5e1f636e Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 17 Nov 2020 11:30:18 +0100 Subject: ARM: shmobile: r8a7779: Use ioremap() to map SMP registers Replace using the legacy IOMEM() macro to map the ARM Reset Vector Address Register (AVECR) by ioremap(). Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20201117103022.2136527-4-geert+renesas@glider.be --- arch/arm/mach-shmobile/smp-r8a7779.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-shmobile/smp-r8a7779.c b/arch/arm/mach-shmobile/smp-r8a7779.c index 0ed73b650c14..f6713886ee16 100644 --- a/arch/arm/mach-shmobile/smp-r8a7779.c +++ b/arch/arm/mach-shmobile/smp-r8a7779.c @@ -20,8 +20,10 @@ #include "common.h" #include "r8a7779.h" -#define AVECR IOMEM(0xfe700040) -#define R8A7779_SCU_BASE 0xf0000000 +#define HPBREG_BASE 0xfe700000 +#define AVECR 0x0040 /* ARM Reset Vector Address Register */ + +#define R8A7779_SCU_BASE 0xf0000000 static int r8a7779_boot_secondary(unsigned int cpu, struct task_struct *idle) { @@ -36,11 +38,15 @@ static int r8a7779_boot_secondary(unsigned int cpu, struct task_struct *idle) static void __init r8a7779_smp_prepare_cpus(unsigned int max_cpus) { + void __iomem *base = ioremap(HPBREG_BASE, 0x1000); + /* Map the reset vector (in headsmp-scu.S, headsmp.S) */ - __raw_writel(__pa(shmobile_boot_vector), AVECR); + __raw_writel(__pa(shmobile_boot_vector), base + AVECR); /* setup r8a7779 specific SCU bits */ shmobile_smp_scu_prepare_cpus(R8A7779_SCU_BASE, max_cpus); + + iounmap(base); } #ifdef CONFIG_HOTPLUG_CPU -- cgit v1.2.3-59-g8ed1b From 5b0480f53dbfe58b6aa291f462a708f178c4bd40 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 17 Nov 2020 11:30:19 +0100 Subject: ARM: shmobile: r8a7779: Remove obsolete static mappings There are no more users of the statically mapped IOMEM regions on R-Car H1. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20201117103022.2136527-5-geert+renesas@glider.be --- arch/arm/mach-shmobile/setup-r8a7779.c | 24 ------------------------ 1 file changed, 24 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-shmobile/setup-r8a7779.c b/arch/arm/mach-shmobile/setup-r8a7779.c index 07c1bc96d4d9..446d40b50b7b 100644 --- a/arch/arm/mach-shmobile/setup-r8a7779.c +++ b/arch/arm/mach-shmobile/setup-r8a7779.c @@ -15,29 +15,6 @@ #include "common.h" #include "r8a7779.h" -static struct map_desc r8a7779_io_desc[] __initdata = { - /* 2M identity mapping for 0xf0000000 (MPCORE) */ - { - .virtual = 0xf0000000, - .pfn = __phys_to_pfn(0xf0000000), - .length = SZ_2M, - .type = MT_DEVICE_NONSHARED - }, - /* 16M identity mapping for 0xfexxxxxx (DMAC-S/HPBREG/INTC2/LRAM/DBSC) */ - { - .virtual = 0xfe000000, - .pfn = __phys_to_pfn(0xfe000000), - .length = SZ_16M, - .type = MT_DEVICE_NONSHARED - }, -}; - -static void __init r8a7779_map_io(void) -{ - debug_ll_io_init(); - iotable_init(r8a7779_io_desc, ARRAY_SIZE(r8a7779_io_desc)); -} - #define HPBREG_BASE 0xfe700000 /* IRQ */ @@ -77,7 +54,6 @@ static const char *const r8a7779_compat_dt[] __initconst = { DT_MACHINE_START(R8A7779_DT, "Generic R8A7779 (Flattened Device Tree)") .smp = smp_ops(r8a7779_smp_ops), - .map_io = r8a7779_map_io, .init_irq = r8a7779_init_irq_dt, .init_late = shmobile_init_late, .dt_compat = r8a7779_compat_dt, -- cgit v1.2.3-59-g8ed1b From cc85e21d6d18ffea52eef061f987978153c2aa0a Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 17 Nov 2020 11:30:20 +0100 Subject: ARM: shmobile: sh73a0: Use ioremap() to map L2C registers Replace using the legacy IOMEM() macro to map the L2C registers by ioremap(). Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20201117103022.2136527-6-geert+renesas@glider.be --- arch/arm/mach-shmobile/setup-sh73a0.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-shmobile/setup-sh73a0.c b/arch/arm/mach-shmobile/setup-sh73a0.c index eb4a62fa4289..e2fcfe1e4f24 100644 --- a/arch/arm/mach-shmobile/setup-sh73a0.c +++ b/arch/arm/mach-shmobile/setup-sh73a0.c @@ -44,7 +44,7 @@ static void __init sh73a0_generic_init(void) { #ifdef CONFIG_CACHE_L2X0 /* Shared attribute override enable, 64K*8way */ - l2x0_init(IOMEM(0xf0100000), 0x00400000, 0xc20f0fff); + l2x0_init(ioremap(0xf0100000, PAGE_SIZE), 0x00400000, 0xc20f0fff); #endif } -- cgit v1.2.3-59-g8ed1b From a0a6624dbec851ab5c136efbecd87a49617a5cc9 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 17 Nov 2020 11:30:21 +0100 Subject: ARM: shmobile: sh73a0: Use ioremap() to map SMP registers Replace using the legacy IOMEM() macro to map various registers related to secondary CPU bringup by ioremap(). Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20201117103022.2136527-7-geert+renesas@glider.be --- arch/arm/mach-shmobile/smp-sh73a0.c | 33 ++++++++++++++++++++++----------- 1 file changed, 22 insertions(+), 11 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-shmobile/smp-sh73a0.c b/arch/arm/mach-shmobile/smp-sh73a0.c index 0403aa8629dd..6d892d11d81c 100644 --- a/arch/arm/mach-shmobile/smp-sh73a0.c +++ b/arch/arm/mach-shmobile/smp-sh73a0.c @@ -16,31 +16,42 @@ #include "common.h" #include "sh73a0.h" -#define WUPCR IOMEM(0xe6151010) -#define SRESCR IOMEM(0xe6151018) -#define PSTR IOMEM(0xe6151040) -#define SBAR IOMEM(0xe6180020) -#define APARMBAREA IOMEM(0xe6f10020) +#define CPG_BASE2 0xe6151000 +#define WUPCR 0x10 /* System-CPU Wake Up Control Register */ +#define SRESCR 0x18 /* System-CPU Software Reset Control Register */ +#define PSTR 0x40 /* System-CPU Power Status Register */ + +#define SYSC_BASE 0xe6180000 +#define SBAR 0x20 /* SYS Boot Address Register */ + +#define AP_BASE 0xe6f10000 +#define APARMBAREA 0x20 /* Address Translation Area Register */ #define SH73A0_SCU_BASE 0xf0000000 static int sh73a0_boot_secondary(unsigned int cpu, struct task_struct *idle) { unsigned int lcpu = cpu_logical_map(cpu); + void __iomem *cpg2 = ioremap(CPG_BASE2, PAGE_SIZE); - if (((__raw_readl(PSTR) >> (4 * lcpu)) & 3) == 3) - __raw_writel(1 << lcpu, WUPCR); /* wake up */ + if (((__raw_readl(cpg2 + PSTR) >> (4 * lcpu)) & 3) == 3) + __raw_writel(1 << lcpu, cpg2 + WUPCR); /* wake up */ else - __raw_writel(1 << lcpu, SRESCR); /* reset */ - + __raw_writel(1 << lcpu, cpg2 + SRESCR); /* reset */ + iounmap(cpg2); return 0; } static void __init sh73a0_smp_prepare_cpus(unsigned int max_cpus) { + void __iomem *ap = ioremap(AP_BASE, PAGE_SIZE); + void __iomem *sysc = ioremap(SYSC_BASE, PAGE_SIZE); + /* Map the reset vector (in headsmp.S) */ - __raw_writel(0, APARMBAREA); /* 4k */ - __raw_writel(__pa(shmobile_boot_vector), SBAR); + __raw_writel(0, ap + APARMBAREA); /* 4k */ + __raw_writel(__pa(shmobile_boot_vector), sysc + SBAR); + iounmap(sysc); + iounmap(ap); /* setup sh73a0 specific SCU bits */ shmobile_smp_scu_prepare_cpus(SH73A0_SCU_BASE, max_cpus); -- cgit v1.2.3-59-g8ed1b From 5705747c0c8f90aee5a433a94f58c9ffad8a5a37 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 17 Nov 2020 11:30:22 +0100 Subject: ARM: shmobile: sh73a0: Remove obsolete static mapping There are no more users of the statically mapped IOMEM region on SH-Mobile AG5. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20201117103022.2136527-8-geert+renesas@glider.be --- arch/arm/mach-shmobile/setup-sh73a0.c | 19 ------------------- 1 file changed, 19 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-shmobile/setup-sh73a0.c b/arch/arm/mach-shmobile/setup-sh73a0.c index e2fcfe1e4f24..890bf537b7de 100644 --- a/arch/arm/mach-shmobile/setup-sh73a0.c +++ b/arch/arm/mach-shmobile/setup-sh73a0.c @@ -22,24 +22,6 @@ #include "common.h" #include "sh73a0.h" -static struct map_desc sh73a0_io_desc[] __initdata = { - /* create a 1:1 identity mapping for 0xe6xxxxxx - * used by CPGA, INTC and PFC. - */ - { - .virtual = 0xe6000000, - .pfn = __phys_to_pfn(0xe6000000), - .length = 256 << 20, - .type = MT_DEVICE_NONSHARED - }, -}; - -static void __init sh73a0_map_io(void) -{ - debug_ll_io_init(); - iotable_init(sh73a0_io_desc, ARRAY_SIZE(sh73a0_io_desc)); -} - static void __init sh73a0_generic_init(void) { #ifdef CONFIG_CACHE_L2X0 @@ -55,7 +37,6 @@ static const char *const sh73a0_boards_compat_dt[] __initconst = { DT_MACHINE_START(SH73A0_DT, "Generic SH73A0 (Flattened Device Tree)") .smp = smp_ops(sh73a0_smp_ops), - .map_io = sh73a0_map_io, .init_machine = sh73a0_generic_init, .init_late = shmobile_init_late, .dt_compat = sh73a0_boards_compat_dt, -- cgit v1.2.3-59-g8ed1b From d4a617c9bbef94e4a776901cf12c95eafd54504a Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 17 Nov 2020 15:24:47 +0100 Subject: ARM: shmobile: Stop using __raw_*() I/O accessors MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit There is no reason to keep on using the __raw_{read,write}l() I/O accessors in Renesas ARM platform code. Switch to using the plain {read,write}l() I/O accessors, to have a chance that this works on big-endian. Suggested-by: Arnd Bergmann Signed-off-by: Geert Uytterhoeven Reviewed-by: Niklas Söderlund Link: https://lore.kernel.org/r/20201117142447.2205664-1-geert+renesas@glider.be --- arch/arm/mach-shmobile/platsmp-scu.c | 2 +- arch/arm/mach-shmobile/setup-r8a7778.c | 8 ++++---- arch/arm/mach-shmobile/setup-r8a7779.c | 14 +++++++------- arch/arm/mach-shmobile/smp-r8a7779.c | 2 +- arch/arm/mach-shmobile/smp-sh73a0.c | 10 +++++----- 5 files changed, 18 insertions(+), 18 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-shmobile/platsmp-scu.c b/arch/arm/mach-shmobile/platsmp-scu.c index fcfcef1d1ae4..3849f71e6e12 100644 --- a/arch/arm/mach-shmobile/platsmp-scu.c +++ b/arch/arm/mach-shmobile/platsmp-scu.c @@ -64,7 +64,7 @@ static int shmobile_smp_scu_psr_core_disabled(int cpu) { unsigned long mask = SCU_PM_POWEROFF << (cpu * 8); - if ((__raw_readl(shmobile_scu_base + 8) & mask) == mask) + if ((readl(shmobile_scu_base + 8) & mask) == mask) return 1; return 0; diff --git a/arch/arm/mach-shmobile/setup-r8a7778.c b/arch/arm/mach-shmobile/setup-r8a7778.c index 819dbda47298..02cda9cada4c 100644 --- a/arch/arm/mach-shmobile/setup-r8a7778.c +++ b/arch/arm/mach-shmobile/setup-r8a7778.c @@ -31,12 +31,12 @@ static void __init r8a7778_init_irq_dt(void) irqchip_init(); /* route all interrupts to ARM */ - __raw_writel(0x73ffffff, base + INT2NTSR0); - __raw_writel(0xffffffff, base + INT2NTSR1); + writel(0x73ffffff, base + INT2NTSR0); + writel(0xffffffff, base + INT2NTSR1); /* unmask all known interrupts in INTCS2 */ - __raw_writel(0x08330773, base + INT2SMSKCR0); - __raw_writel(0x00311110, base + INT2SMSKCR1); + writel(0x08330773, base + INT2SMSKCR0); + writel(0x00311110, base + INT2SMSKCR1); iounmap(base); } diff --git a/arch/arm/mach-shmobile/setup-r8a7779.c b/arch/arm/mach-shmobile/setup-r8a7779.c index 446d40b50b7b..b6e282116d66 100644 --- a/arch/arm/mach-shmobile/setup-r8a7779.c +++ b/arch/arm/mach-shmobile/setup-r8a7779.c @@ -34,15 +34,15 @@ static void __init r8a7779_init_irq_dt(void) irqchip_init(); /* route all interrupts to ARM */ - __raw_writel(0xffffffff, base + INT2NTSR0); - __raw_writel(0x3fffffff, base + INT2NTSR1); + writel(0xffffffff, base + INT2NTSR0); + writel(0x3fffffff, base + INT2NTSR1); /* unmask all known interrupts in INTCS2 */ - __raw_writel(0xfffffff0, base + INT2SMSKCR0); - __raw_writel(0xfff7ffff, base + INT2SMSKCR1); - __raw_writel(0xfffbffdf, base + INT2SMSKCR2); - __raw_writel(0xbffffffc, base + INT2SMSKCR3); - __raw_writel(0x003fee3f, base + INT2SMSKCR4); + writel(0xfffffff0, base + INT2SMSKCR0); + writel(0xfff7ffff, base + INT2SMSKCR1); + writel(0xfffbffdf, base + INT2SMSKCR2); + writel(0xbffffffc, base + INT2SMSKCR3); + writel(0x003fee3f, base + INT2SMSKCR4); iounmap(base); } diff --git a/arch/arm/mach-shmobile/smp-r8a7779.c b/arch/arm/mach-shmobile/smp-r8a7779.c index f6713886ee16..1bc609986c16 100644 --- a/arch/arm/mach-shmobile/smp-r8a7779.c +++ b/arch/arm/mach-shmobile/smp-r8a7779.c @@ -41,7 +41,7 @@ static void __init r8a7779_smp_prepare_cpus(unsigned int max_cpus) void __iomem *base = ioremap(HPBREG_BASE, 0x1000); /* Map the reset vector (in headsmp-scu.S, headsmp.S) */ - __raw_writel(__pa(shmobile_boot_vector), base + AVECR); + writel(__pa(shmobile_boot_vector), base + AVECR); /* setup r8a7779 specific SCU bits */ shmobile_smp_scu_prepare_cpus(R8A7779_SCU_BASE, max_cpus); diff --git a/arch/arm/mach-shmobile/smp-sh73a0.c b/arch/arm/mach-shmobile/smp-sh73a0.c index 6d892d11d81c..453d48865029 100644 --- a/arch/arm/mach-shmobile/smp-sh73a0.c +++ b/arch/arm/mach-shmobile/smp-sh73a0.c @@ -34,10 +34,10 @@ static int sh73a0_boot_secondary(unsigned int cpu, struct task_struct *idle) unsigned int lcpu = cpu_logical_map(cpu); void __iomem *cpg2 = ioremap(CPG_BASE2, PAGE_SIZE); - if (((__raw_readl(cpg2 + PSTR) >> (4 * lcpu)) & 3) == 3) - __raw_writel(1 << lcpu, cpg2 + WUPCR); /* wake up */ + if (((readl(cpg2 + PSTR) >> (4 * lcpu)) & 3) == 3) + writel(1 << lcpu, cpg2 + WUPCR); /* wake up */ else - __raw_writel(1 << lcpu, cpg2 + SRESCR); /* reset */ + writel(1 << lcpu, cpg2 + SRESCR); /* reset */ iounmap(cpg2); return 0; } @@ -48,8 +48,8 @@ static void __init sh73a0_smp_prepare_cpus(unsigned int max_cpus) void __iomem *sysc = ioremap(SYSC_BASE, PAGE_SIZE); /* Map the reset vector (in headsmp.S) */ - __raw_writel(0, ap + APARMBAREA); /* 4k */ - __raw_writel(__pa(shmobile_boot_vector), sysc + SBAR); + writel(0, ap + APARMBAREA); /* 4k */ + writel(__pa(shmobile_boot_vector), sysc + SBAR); iounmap(sysc); iounmap(ap); -- cgit v1.2.3-59-g8ed1b From 7fd70c65faacd39628ba5f670be6490010c8132f Mon Sep 17 00:00:00 2001 From: Thomas Gleixner Date: Fri, 13 Nov 2020 15:02:12 +0100 Subject: ARM: irqstat: Get rid of duplicated declaration irq_cpustat_t is exactly the same as the asm-generic one. Define ack_bad_irq so the generic header does not emit the generic version of it. Signed-off-by: Thomas Gleixner Reviewed-by: Frederic Weisbecker Reviewed-by: Valentin Schneider Link: https://lore.kernel.org/r/20201113141733.276505871@linutronix.de --- arch/arm/include/asm/hardirq.h | 11 +++-------- arch/arm/include/asm/irq.h | 2 ++ 2 files changed, 5 insertions(+), 8 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/include/asm/hardirq.h b/arch/arm/include/asm/hardirq.h index b95848ed2bc7..706efafbf972 100644 --- a/arch/arm/include/asm/hardirq.h +++ b/arch/arm/include/asm/hardirq.h @@ -2,16 +2,11 @@ #ifndef __ASM_HARDIRQ_H #define __ASM_HARDIRQ_H -#include -#include #include -typedef struct { - unsigned int __softirq_pending; -} ____cacheline_aligned irq_cpustat_t; - -#include /* Standard mappings for irq_cpustat_t above */ - #define __ARCH_IRQ_EXIT_IRQS_DISABLED 1 +#define ack_bad_irq ack_bad_irq + +#include #endif /* __ASM_HARDIRQ_H */ diff --git a/arch/arm/include/asm/irq.h b/arch/arm/include/asm/irq.h index 46d41140df27..1cbcc462b07e 100644 --- a/arch/arm/include/asm/irq.h +++ b/arch/arm/include/asm/irq.h @@ -31,6 +31,8 @@ void handle_IRQ(unsigned int, struct pt_regs *); void init_IRQ(void); #ifdef CONFIG_SMP +#include + extern void arch_trigger_cpumask_backtrace(const cpumask_t *mask, bool exclude_self); #define arch_trigger_cpumask_backtrace arch_trigger_cpumask_backtrace -- cgit v1.2.3-59-g8ed1b From ef5704b535194fb98ee1ceb00f6952e2f01e39a6 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Fri, 20 Nov 2020 13:42:12 +0100 Subject: ARM: dts: ux500-golden: Add proper supplies to touchscreen This sets up the Atmel maXTouch touchscreen to use proper VDDA and VDD supplies as now supported by bindings and driver. Cc: Stephan Gerhold Cc: Nick Reitemeyer Cc: Nick Dyer Link: https://lore.kernel.org/r/20201120124212.1086063-1-linus.walleij@linaro.org Signed-off-by: Linus Walleij --- arch/arm/boot/dts/ste-ux500-samsung-golden.dts | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/ste-ux500-samsung-golden.dts b/arch/arm/boot/dts/ste-ux500-samsung-golden.dts index 939360c05713..496f9d3ba7b7 100644 --- a/arch/arm/boot/dts/ste-ux500-samsung-golden.dts +++ b/arch/arm/boot/dts/ste-ux500-samsung-golden.dts @@ -260,6 +260,11 @@ interrupt-parent = <&gpio6>; interrupts = <26 IRQ_TYPE_EDGE_FALLING>; + /* VDDA is "analog supply", 2.57-3.47 V */ + vdda-supply = <&ab8500_ldo_aux2_reg>; + /* VDD is "digital supply" 1.71-3.47V */ + vdd-supply = <&ab8500_ldo_aux5_reg>; + pinctrl-names = "default"; pinctrl-0 = <&tsp_default>; }; @@ -284,7 +289,6 @@ regulator-name = "vreg_tsp_a3v3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; - regulator-always-on; /* FIXME */ }; ab8500_ldo_aux3 { @@ -301,7 +305,6 @@ regulator-name = "vreg_tsp_1v8"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; - regulator-always-on; /* FIXME */ }; ab8500_ldo_aux6 { -- cgit v1.2.3-59-g8ed1b From b2d91953b66c724eaf8d7f84f37c006d966f67ac Mon Sep 17 00:00:00 2001 From: Tomer Maimon Date: Thu, 19 Nov 2020 10:00:02 +0200 Subject: ARM: dts: add Nuvoton NPCM730 device tree Add Nuvoton NPCM730 SoC device tree. The Nuvoton NPCN730 SoC is a part of the Nuvoton NPCM7xx SoCs family. Signed-off-by: Tomer Maimon Reviewed-by: Benjamin Fair Link: https://lore.kernel.org/r/20201119080002.100342-1-tmaimon77@gmail.com' Signed-off-by: Arnd Bergmann --- arch/arm/boot/dts/nuvoton-npcm730.dtsi | 44 ++++++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) create mode 100644 arch/arm/boot/dts/nuvoton-npcm730.dtsi (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/nuvoton-npcm730.dtsi b/arch/arm/boot/dts/nuvoton-npcm730.dtsi new file mode 100644 index 000000000000..86ec12ec2b50 --- /dev/null +++ b/arch/arm/boot/dts/nuvoton-npcm730.dtsi @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2020 Nuvoton Technology + +#include "nuvoton-common-npcm7xx.dtsi" + +/ { + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&gic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + enable-method = "nuvoton,npcm750-smp"; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + clocks = <&clk NPCM7XX_CLK_CPU>; + clock-names = "clk_cpu"; + reg = <0>; + next-level-cache = <&l2>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + clocks = <&clk NPCM7XX_CLK_CPU>; + clock-names = "clk_cpu"; + reg = <1>; + next-level-cache = <&l2>; + }; + }; + + soc { + timer@3fe600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0x3fe600 0x20>; + interrupts = ; + clocks = <&clk NPCM7XX_CLK_AHB>; + }; + }; +}; -- cgit v1.2.3-59-g8ed1b From a65183ff1535ed15c28c526f6b69ed03c21d34b4 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Thu, 5 Nov 2020 14:45:10 +0100 Subject: ARM: config: ux500: Update U8500 defconfig This updates the defconfig for the U8500 platform with some of the changes from the v5.9 and v5.10 kernel cycles: - No need to select the schedutil cpufreq governor because it is the default now. - Enable the CY8CTMA140 touchscreen as used on the Samsung Skomer GT-S7710. - Enable the Samsung S6E63M0 DSI panel as used on the Samsung Golden GT-I8810. - Enable the KTD253 backlight as used on the Samsung Skomer GT-S7710. - Drop CONFIG_USB as we only use the gadget mode of the MUSB driver. - Add selection of the CONFIG_LEDS_LP55XX_COMMON lest the LP5521 LEDs will not work. - Move the config entry for CONFIG_DEBUG_FS. Signed-off-by: Linus Walleij Cc: Stephan Gerhold Link: https://lore.kernel.org/r/20201105134510.1417639-1-linus.walleij@linaro.org' Signed-off-by: Arnd Bergmann --- arch/arm/configs/u8500_defconfig | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/configs/u8500_defconfig b/arch/arm/configs/u8500_defconfig index 28dd7cf56048..bcedfe1422aa 100644 --- a/arch/arm/configs/u8500_defconfig +++ b/arch/arm/configs/u8500_defconfig @@ -12,7 +12,6 @@ CONFIG_ARM_APPENDED_DTB=y CONFIG_ARM_ATAG_DTB_COMPAT=y CONFIG_CMDLINE="root=/dev/ram0 console=ttyAMA2,115200n8" CONFIG_CPU_FREQ=y -CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL=y CONFIG_CPU_FREQ_GOV_ONDEMAND=y CONFIG_CPUFREQ_DT=y CONFIG_CPU_IDLE=y @@ -60,6 +59,7 @@ CONFIG_KEYBOARD_TC3589X=y CONFIG_INPUT_TOUCHSCREEN=y CONFIG_TOUCHSCREEN_ATMEL_MXT=y CONFIG_TOUCHSCREEN_BU21013=y +CONFIG_TOUCHSCREEN_CY8CTMA140=y CONFIG_INPUT_MISC=y CONFIG_INPUT_AB8500_PONKEY=y CONFIG_INPUT_GPIO_VIBRA=y @@ -88,11 +88,13 @@ CONFIG_REGULATOR_GPIO=y CONFIG_DRM=y CONFIG_DRM_PANEL_NOVATEK_NT35510=y CONFIG_DRM_PANEL_SAMSUNG_S6D16D0=y +CONFIG_DRM_PANEL_SAMSUNG_S6E63M0=y +CONFIG_DRM_PANEL_SAMSUNG_S6E63M0_DSI=y CONFIG_DRM_PANEL_SONY_ACX424AKP=y CONFIG_DRM_LIMA=y CONFIG_DRM_MCDE=y CONFIG_BACKLIGHT_CLASS_DEVICE=y -CONFIG_BACKLIGHT_GENERIC=m +CONFIG_BACKLIGHT_KTD253=y CONFIG_BACKLIGHT_GPIO=y CONFIG_LOGO=y CONFIG_SOUND=y @@ -100,7 +102,6 @@ CONFIG_SND=y CONFIG_SND_SOC=y CONFIG_SND_SOC_UX500=y CONFIG_SND_SOC_UX500_MACH_MOP500=y -CONFIG_USB=y CONFIG_USB_MUSB_HDRC=y CONFIG_USB_MUSB_UX500=y CONFIG_MUSB_PIO_ONLY=y @@ -113,6 +114,7 @@ CONFIG_NEW_LEDS=y CONFIG_LEDS_CLASS=y CONFIG_LEDS_LM3530=y CONFIG_LEDS_GPIO=y +CONFIG_LEDS_LP55XX_COMMON=y CONFIG_LEDS_LP5521=y CONFIG_LEDS_TRIGGER_HEARTBEAT=y CONFIG_RTC_CLASS=y @@ -153,8 +155,8 @@ CONFIG_CRYPTO_DEV_UX500_HASH=y CONFIG_CRYPTO_DEV_UX500_DEBUG=y CONFIG_PRINTK_TIME=y CONFIG_DEBUG_INFO=y -CONFIG_DEBUG_FS=y CONFIG_MAGIC_SYSRQ=y +CONFIG_DEBUG_FS=y CONFIG_DEBUG_KERNEL=y # CONFIG_SCHED_DEBUG is not set # CONFIG_FTRACE is not set -- cgit v1.2.3-59-g8ed1b From 8195fceca0316c36c87db25750a5c5db84ded4e7 Mon Sep 17 00:00:00 2001 From: Grygorii Strashko Date: Fri, 30 Oct 2020 14:46:50 +0200 Subject: ARM: multi_v7_defconfig: ti: Enable networking options for nfs boot Enable networking options required for NFS boot on TI platforms, which is widely for automated test systems. - enable new TI CPSW switch driver and related NET_SWITCHDEV config - enable TI DP83867 phy - explicitly enable PTP clock support to ensure dependent networking drivers will stay built-in. vmlinux size changes: - before: text data bss dec hex filename 14703736 8024602 444976 23173314 16198c2 ./omap-arm/vmlinux - after: text data bss dec hex filename 14727271 8029150 444528 23200949 16204b5 ./omap-arm/vmlinux diff: 27635 (dec) Signed-off-by: Grygorii Strashko Reviewed-by: Nishanth Menon Cc: Tony Lindgren Link: https://lore.kernel.org/r/20201030124650.20349-1-grygorii.strashko@ti.com' Signed-off-by: Arnd Bergmann --- arch/arm/configs/multi_v7_defconfig | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig index a611b0c1e540..48a9cdec474a 100644 --- a/arch/arm/configs/multi_v7_defconfig +++ b/arch/arm/configs/multi_v7_defconfig @@ -154,6 +154,7 @@ CONFIG_INET6_IPCOMP=m CONFIG_IPV6_MIP6=m CONFIG_IPV6_TUNNEL=m CONFIG_IPV6_MULTIPLE_TABLES=y +CONFIG_NET_SWITCHDEV=y CONFIG_NET_DSA=m CONFIG_CAN=y CONFIG_CAN_AT91=m @@ -270,9 +271,12 @@ CONFIG_SNI_AVE=y CONFIG_STMMAC_ETH=y CONFIG_DWMAC_DWC_QOS_ETH=y CONFIG_TI_CPSW=y +CONFIG_TI_CPSW_SWITCHDEV=y +CONFIG_TI_CPTS=y CONFIG_XILINX_EMACLITE=y CONFIG_BROADCOM_PHY=y CONFIG_ICPLUS_PHY=y +CONFIG_DP83867_PHY=y CONFIG_MARVELL_PHY=y CONFIG_MICREL_PHY=y CONFIG_AT803X_PHY=y @@ -436,6 +440,7 @@ CONFIG_SPI_TEGRA20_SLINK=y CONFIG_SPI_XILINX=y CONFIG_SPI_SPIDEV=y CONFIG_SPMI=y +CONFIG_PTP_1588_CLOCK=y CONFIG_PINCTRL_AS3722=y CONFIG_PINCTRL_RZA2=y CONFIG_PINCTRL_STMFX=y -- cgit v1.2.3-59-g8ed1b From 1d82b7898f2ad9cc414805aef23b99b742218f10 Mon Sep 17 00:00:00 2001 From: Peter Collingbourne Date: Thu, 12 Nov 2020 18:53:33 -0800 Subject: arch: move SA_* definitions to generic headers Most architectures with the exception of alpha, mips, parisc and sparc use the same values for these flags. Move their definitions into asm-generic/signal-defs.h and allow the architectures with non-standard values to override them. Also, document the non-standard flag values in order to make it easier to add new generic flags in the future. A consequence of this change is that on powerpc and x86, the constants' values aside from SA_RESETHAND change signedness from unsigned to signed. This is not expected to impact realistic use of these constants. In particular the typical use of the constants where they are or'ed together and assigned to sa_flags (or another int variable) would not be affected. Signed-off-by: Peter Collingbourne Acked-by: Geert Uytterhoeven Acked-by: "Eric W. Biederman" Reviewed-by: Dave Martin Link: https://linux-review.googlesource.com/id/Ia3849f18b8009bf41faca374e701cdca36974528 Link: https://lkml.kernel.org/r/b6d0d1ec34f9ee93e1105f14f288fba5f89d1f24.1605235762.git.pcc@google.com Signed-off-by: Eric W. Biederman --- arch/alpha/include/uapi/asm/signal.h | 14 ---------- arch/arm/include/uapi/asm/signal.h | 27 +++---------------- arch/h8300/include/uapi/asm/signal.h | 24 ----------------- arch/ia64/include/uapi/asm/signal.h | 24 ----------------- arch/m68k/include/uapi/asm/signal.h | 24 ----------------- arch/mips/include/uapi/asm/signal.h | 12 --------- arch/parisc/include/uapi/asm/signal.h | 13 ---------- arch/powerpc/include/uapi/asm/signal.h | 24 ----------------- arch/s390/include/uapi/asm/signal.h | 24 ----------------- arch/sparc/include/uapi/asm/signal.h | 4 +-- arch/x86/include/uapi/asm/signal.h | 24 ----------------- arch/xtensa/include/uapi/asm/signal.h | 24 ----------------- include/uapi/asm-generic/signal-defs.h | 47 ++++++++++++++++++++++++++++++++++ include/uapi/asm-generic/signal.h | 29 --------------------- 14 files changed, 51 insertions(+), 263 deletions(-) (limited to 'arch/arm') diff --git a/arch/alpha/include/uapi/asm/signal.h b/arch/alpha/include/uapi/asm/signal.h index 74c750bf1c1a..a69dd8d080a8 100644 --- a/arch/alpha/include/uapi/asm/signal.h +++ b/arch/alpha/include/uapi/asm/signal.h @@ -60,20 +60,6 @@ typedef unsigned long sigset_t; #define SIGRTMIN 32 #define SIGRTMAX _NSIG -/* - * SA_FLAGS values: - * - * SA_ONSTACK indicates that a registered stack_t will be used. - * SA_RESTART flag to get restarting signals (which were the default long ago) - * SA_NOCLDSTOP flag to turn off SIGCHLD when children stop. - * SA_RESETHAND clears the handler when the signal is delivered. - * SA_NOCLDWAIT flag on SIGCHLD to inhibit zombies. - * SA_NODEFER prevents the current signal from being masked in the handler. - * - * SA_ONESHOT and SA_NOMASK are the historical Linux names for the Single - * Unix names RESETHAND and NODEFER respectively. - */ - #define SA_ONSTACK 0x00000001 #define SA_RESTART 0x00000002 #define SA_NOCLDSTOP 0x00000004 diff --git a/arch/arm/include/uapi/asm/signal.h b/arch/arm/include/uapi/asm/signal.h index 9b4185ba4f8a..c9a3ea1d8d41 100644 --- a/arch/arm/include/uapi/asm/signal.h +++ b/arch/arm/include/uapi/asm/signal.h @@ -60,33 +60,12 @@ typedef unsigned long sigset_t; #define SIGSWI 32 /* - * SA_FLAGS values: - * - * SA_NOCLDSTOP flag to turn off SIGCHLD when children stop. - * SA_NOCLDWAIT flag on SIGCHLD to inhibit zombies. - * SA_SIGINFO deliver the signal with SIGINFO structs - * SA_THIRTYTWO delivers the signal in 32-bit mode, even if the task - * is running in 26-bit. - * SA_ONSTACK allows alternate signal stacks (see sigaltstack(2)). - * SA_RESTART flag to get restarting signals (which were the default long ago) - * SA_NODEFER prevents the current signal from being masked in the handler. - * SA_RESETHAND clears the handler when the signal is delivered. - * - * SA_ONESHOT and SA_NOMASK are the historical Linux names for the Single - * Unix names RESETHAND and NODEFER respectively. + * SA_THIRTYTWO historically meant deliver the signal in 32-bit mode, even if + * the task is running in 26-bit. But since the kernel no longer supports + * 26-bit mode, the flag has no effect. */ -#define SA_NOCLDSTOP 0x00000001 -#define SA_NOCLDWAIT 0x00000002 -#define SA_SIGINFO 0x00000004 #define SA_THIRTYTWO 0x02000000 #define SA_RESTORER 0x04000000 -#define SA_ONSTACK 0x08000000 -#define SA_RESTART 0x10000000 -#define SA_NODEFER 0x40000000 -#define SA_RESETHAND 0x80000000 - -#define SA_NOMASK SA_NODEFER -#define SA_ONESHOT SA_RESETHAND #define MINSIGSTKSZ 2048 #define SIGSTKSZ 8192 diff --git a/arch/h8300/include/uapi/asm/signal.h b/arch/h8300/include/uapi/asm/signal.h index e15521037348..2cd0dce2b6a6 100644 --- a/arch/h8300/include/uapi/asm/signal.h +++ b/arch/h8300/include/uapi/asm/signal.h @@ -57,30 +57,6 @@ typedef unsigned long sigset_t; #define SIGRTMIN 32 #define SIGRTMAX _NSIG -/* - * SA_FLAGS values: - * - * SA_ONSTACK indicates that a registered stack_t will be used. - * SA_RESTART flag to get restarting signals (which were the default long ago) - * SA_NOCLDSTOP flag to turn off SIGCHLD when children stop. - * SA_RESETHAND clears the handler when the signal is delivered. - * SA_NOCLDWAIT flag on SIGCHLD to inhibit zombies. - * SA_NODEFER prevents the current signal from being masked in the handler. - * - * SA_ONESHOT and SA_NOMASK are the historical Linux names for the Single - * Unix names RESETHAND and NODEFER respectively. - */ -#define SA_NOCLDSTOP 0x00000001 -#define SA_NOCLDWAIT 0x00000002 /* not supported yet */ -#define SA_SIGINFO 0x00000004 -#define SA_ONSTACK 0x08000000 -#define SA_RESTART 0x10000000 -#define SA_NODEFER 0x40000000 -#define SA_RESETHAND 0x80000000 - -#define SA_NOMASK SA_NODEFER -#define SA_ONESHOT SA_RESETHAND - #define SA_RESTORER 0x04000000 #define MINSIGSTKSZ 2048 diff --git a/arch/ia64/include/uapi/asm/signal.h b/arch/ia64/include/uapi/asm/signal.h index aa98ff1b9e22..38166a88e4c9 100644 --- a/arch/ia64/include/uapi/asm/signal.h +++ b/arch/ia64/include/uapi/asm/signal.h @@ -53,30 +53,6 @@ #define SIGRTMIN 32 #define SIGRTMAX _NSIG -/* - * SA_FLAGS values: - * - * SA_ONSTACK indicates that a registered stack_t will be used. - * SA_RESTART flag to get restarting signals (which were the default long ago) - * SA_NOCLDSTOP flag to turn off SIGCHLD when children stop. - * SA_RESETHAND clears the handler when the signal is delivered. - * SA_NOCLDWAIT flag on SIGCHLD to inhibit zombies. - * SA_NODEFER prevents the current signal from being masked in the handler. - * - * SA_ONESHOT and SA_NOMASK are the historical Linux names for the Single - * Unix names RESETHAND and NODEFER respectively. - */ -#define SA_NOCLDSTOP 0x00000001 -#define SA_NOCLDWAIT 0x00000002 -#define SA_SIGINFO 0x00000004 -#define SA_ONSTACK 0x08000000 -#define SA_RESTART 0x10000000 -#define SA_NODEFER 0x40000000 -#define SA_RESETHAND 0x80000000 - -#define SA_NOMASK SA_NODEFER -#define SA_ONESHOT SA_RESETHAND - #define SA_RESTORER 0x04000000 /* diff --git a/arch/m68k/include/uapi/asm/signal.h b/arch/m68k/include/uapi/asm/signal.h index 915cc755a184..4619291df601 100644 --- a/arch/m68k/include/uapi/asm/signal.h +++ b/arch/m68k/include/uapi/asm/signal.h @@ -57,30 +57,6 @@ typedef unsigned long sigset_t; #define SIGRTMIN 32 #define SIGRTMAX _NSIG -/* - * SA_FLAGS values: - * - * SA_ONSTACK indicates that a registered stack_t will be used. - * SA_RESTART flag to get restarting signals (which were the default long ago) - * SA_NOCLDSTOP flag to turn off SIGCHLD when children stop. - * SA_RESETHAND clears the handler when the signal is delivered. - * SA_NOCLDWAIT flag on SIGCHLD to inhibit zombies. - * SA_NODEFER prevents the current signal from being masked in the handler. - * - * SA_ONESHOT and SA_NOMASK are the historical Linux names for the Single - * Unix names RESETHAND and NODEFER respectively. - */ -#define SA_NOCLDSTOP 0x00000001 -#define SA_NOCLDWAIT 0x00000002 -#define SA_SIGINFO 0x00000004 -#define SA_ONSTACK 0x08000000 -#define SA_RESTART 0x10000000 -#define SA_NODEFER 0x40000000 -#define SA_RESETHAND 0x80000000 - -#define SA_NOMASK SA_NODEFER -#define SA_ONESHOT SA_RESETHAND - #define MINSIGSTKSZ 2048 #define SIGSTKSZ 8192 diff --git a/arch/mips/include/uapi/asm/signal.h b/arch/mips/include/uapi/asm/signal.h index 53104b10aae2..e6c78a15cb2f 100644 --- a/arch/mips/include/uapi/asm/signal.h +++ b/arch/mips/include/uapi/asm/signal.h @@ -62,18 +62,6 @@ typedef unsigned long old_sigset_t; /* at least 32 bits */ #define SIGRTMAX _NSIG /* - * SA_FLAGS values: - * - * SA_ONSTACK indicates that a registered stack_t will be used. - * SA_RESTART flag to get restarting signals (which were the default long ago) - * SA_NOCLDSTOP flag to turn off SIGCHLD when children stop. - * SA_RESETHAND clears the handler when the signal is delivered. - * SA_NOCLDWAIT flag on SIGCHLD to inhibit zombies. - * SA_NODEFER prevents the current signal from being masked in the handler. - * - * SA_ONESHOT and SA_NOMASK are the historical Linux names for the Single - * Unix names RESETHAND and NODEFER respectively. - * * SA_RESTORER used to be defined as 0x04000000 but only the O32 ABI ever * supported its use and no libc was using it, so the entire sa-restorer * functionality was removed with lmo commit 39bffc12c3580ab for 2.5.48 diff --git a/arch/parisc/include/uapi/asm/signal.h b/arch/parisc/include/uapi/asm/signal.h index 9e6f87bc8a73..e5a2657477ac 100644 --- a/arch/parisc/include/uapi/asm/signal.h +++ b/arch/parisc/include/uapi/asm/signal.h @@ -41,19 +41,6 @@ #define SIGRTMIN 32 #define SIGRTMAX _NSIG -/* - * SA_FLAGS values: - * - * SA_ONSTACK indicates that a registered stack_t will be used. - * SA_RESTART flag to get restarting signals (which were the default long ago) - * SA_NOCLDSTOP flag to turn off SIGCHLD when children stop. - * SA_RESETHAND clears the handler when the signal is delivered. - * SA_NOCLDWAIT flag on SIGCHLD to inhibit zombies. - * SA_NODEFER prevents the current signal from being masked in the handler. - * - * SA_ONESHOT and SA_NOMASK are the historical Linux names for the Single - * Unix names RESETHAND and NODEFER respectively. - */ #define SA_ONSTACK 0x00000001 #define SA_RESETHAND 0x00000004 #define SA_NOCLDSTOP 0x00000008 diff --git a/arch/powerpc/include/uapi/asm/signal.h b/arch/powerpc/include/uapi/asm/signal.h index 85b0a7aa43e7..04873dd311c2 100644 --- a/arch/powerpc/include/uapi/asm/signal.h +++ b/arch/powerpc/include/uapi/asm/signal.h @@ -60,30 +60,6 @@ typedef struct { #define SIGRTMIN 32 #define SIGRTMAX _NSIG -/* - * SA_FLAGS values: - * - * SA_ONSTACK is not currently supported, but will allow sigaltstack(2). - * SA_RESTART flag to get restarting signals (which were the default long ago) - * SA_NOCLDSTOP flag to turn off SIGCHLD when children stop. - * SA_RESETHAND clears the handler when the signal is delivered. - * SA_NOCLDWAIT flag on SIGCHLD to inhibit zombies. - * SA_NODEFER prevents the current signal from being masked in the handler. - * - * SA_ONESHOT and SA_NOMASK are the historical Linux names for the Single - * Unix names RESETHAND and NODEFER respectively. - */ -#define SA_NOCLDSTOP 0x00000001U -#define SA_NOCLDWAIT 0x00000002U -#define SA_SIGINFO 0x00000004U -#define SA_ONSTACK 0x08000000U -#define SA_RESTART 0x10000000U -#define SA_NODEFER 0x40000000U -#define SA_RESETHAND 0x80000000U - -#define SA_NOMASK SA_NODEFER -#define SA_ONESHOT SA_RESETHAND - #define SA_RESTORER 0x04000000U #define MINSIGSTKSZ 2048 diff --git a/arch/s390/include/uapi/asm/signal.h b/arch/s390/include/uapi/asm/signal.h index 9a14a611ed82..0189f326aac5 100644 --- a/arch/s390/include/uapi/asm/signal.h +++ b/arch/s390/include/uapi/asm/signal.h @@ -65,30 +65,6 @@ typedef unsigned long sigset_t; #define SIGRTMIN 32 #define SIGRTMAX _NSIG -/* - * SA_FLAGS values: - * - * SA_ONSTACK indicates that a registered stack_t will be used. - * SA_RESTART flag to get restarting signals (which were the default long ago) - * SA_NOCLDSTOP flag to turn off SIGCHLD when children stop. - * SA_RESETHAND clears the handler when the signal is delivered. - * SA_NOCLDWAIT flag on SIGCHLD to inhibit zombies. - * SA_NODEFER prevents the current signal from being masked in the handler. - * - * SA_ONESHOT and SA_NOMASK are the historical Linux names for the Single - * Unix names RESETHAND and NODEFER respectively. - */ -#define SA_NOCLDSTOP 0x00000001 -#define SA_NOCLDWAIT 0x00000002 -#define SA_SIGINFO 0x00000004 -#define SA_ONSTACK 0x08000000 -#define SA_RESTART 0x10000000 -#define SA_NODEFER 0x40000000 -#define SA_RESETHAND 0x80000000 - -#define SA_NOMASK SA_NODEFER -#define SA_ONESHOT SA_RESETHAND - #define SA_RESTORER 0x04000000 #define MINSIGSTKSZ 2048 diff --git a/arch/sparc/include/uapi/asm/signal.h b/arch/sparc/include/uapi/asm/signal.h index ff9505923b9a..53758d53ac0e 100644 --- a/arch/sparc/include/uapi/asm/signal.h +++ b/arch/sparc/include/uapi/asm/signal.h @@ -137,13 +137,11 @@ struct sigstack { #define SA_STACK _SV_SSTACK #define SA_ONSTACK _SV_SSTACK #define SA_RESTART _SV_INTR -#define SA_ONESHOT _SV_RESET +#define SA_RESETHAND _SV_RESET #define SA_NODEFER 0x20u #define SA_NOCLDWAIT 0x100u #define SA_SIGINFO 0x200u -#define SA_NOMASK SA_NODEFER - #define SIG_BLOCK 0x01 /* for blocking signals */ #define SIG_UNBLOCK 0x02 /* for unblocking signals */ #define SIG_SETMASK 0x04 /* for setting the signal mask */ diff --git a/arch/x86/include/uapi/asm/signal.h b/arch/x86/include/uapi/asm/signal.h index e5745d593dc7..164a22a72984 100644 --- a/arch/x86/include/uapi/asm/signal.h +++ b/arch/x86/include/uapi/asm/signal.h @@ -62,30 +62,6 @@ typedef unsigned long sigset_t; #define SIGRTMIN 32 #define SIGRTMAX _NSIG -/* - * SA_FLAGS values: - * - * SA_ONSTACK indicates that a registered stack_t will be used. - * SA_RESTART flag to get restarting signals (which were the default long ago) - * SA_NOCLDSTOP flag to turn off SIGCHLD when children stop. - * SA_RESETHAND clears the handler when the signal is delivered. - * SA_NOCLDWAIT flag on SIGCHLD to inhibit zombies. - * SA_NODEFER prevents the current signal from being masked in the handler. - * - * SA_ONESHOT and SA_NOMASK are the historical Linux names for the Single - * Unix names RESETHAND and NODEFER respectively. - */ -#define SA_NOCLDSTOP 0x00000001u -#define SA_NOCLDWAIT 0x00000002u -#define SA_SIGINFO 0x00000004u -#define SA_ONSTACK 0x08000000u -#define SA_RESTART 0x10000000u -#define SA_NODEFER 0x40000000u -#define SA_RESETHAND 0x80000000u - -#define SA_NOMASK SA_NODEFER -#define SA_ONESHOT SA_RESETHAND - #define SA_RESTORER 0x04000000 #define MINSIGSTKSZ 2048 diff --git a/arch/xtensa/include/uapi/asm/signal.h b/arch/xtensa/include/uapi/asm/signal.h index 005dec5bfde4..79ddabaa4e5d 100644 --- a/arch/xtensa/include/uapi/asm/signal.h +++ b/arch/xtensa/include/uapi/asm/signal.h @@ -72,30 +72,6 @@ typedef struct { #define SIGRTMIN 32 #define SIGRTMAX (_NSIG-1) -/* - * SA_FLAGS values: - * - * SA_ONSTACK indicates that a registered stack_t will be used. - * SA_RESTART flag to get restarting signals (which were the default long ago) - * SA_NOCLDSTOP flag to turn off SIGCHLD when children stop. - * SA_RESETHAND clears the handler when the signal is delivered. - * SA_NOCLDWAIT flag on SIGCHLD to inhibit zombies. - * SA_NODEFER prevents the current signal from being masked in the handler. - * - * SA_ONESHOT and SA_NOMASK are the historical Linux names for the Single - * Unix names RESETHAND and NODEFER respectively. - */ -#define SA_NOCLDSTOP 0x00000001 -#define SA_NOCLDWAIT 0x00000002 /* not supported yet */ -#define SA_SIGINFO 0x00000004 -#define SA_ONSTACK 0x08000000 -#define SA_RESTART 0x10000000 -#define SA_NODEFER 0x40000000 -#define SA_RESETHAND 0x80000000 - -#define SA_NOMASK SA_NODEFER -#define SA_ONESHOT SA_RESETHAND - #define SA_RESTORER 0x04000000 #define MINSIGSTKSZ 2048 diff --git a/include/uapi/asm-generic/signal-defs.h b/include/uapi/asm-generic/signal-defs.h index e9304c95ceea..493953fe319b 100644 --- a/include/uapi/asm-generic/signal-defs.h +++ b/include/uapi/asm-generic/signal-defs.h @@ -4,6 +4,53 @@ #include +/* + * SA_FLAGS values: + * + * SA_NOCLDSTOP flag to turn off SIGCHLD when children stop. + * SA_NOCLDWAIT flag on SIGCHLD to inhibit zombies. + * SA_SIGINFO delivers the signal with SIGINFO structs. + * SA_ONSTACK indicates that a registered stack_t will be used. + * SA_RESTART flag to get restarting signals (which were the default long ago) + * SA_NODEFER prevents the current signal from being masked in the handler. + * SA_RESETHAND clears the handler when the signal is delivered. + * + * SA_ONESHOT and SA_NOMASK are the historical Linux names for the Single + * Unix names RESETHAND and NODEFER respectively. + * + * The following bits are used in architecture-specific SA_* definitions and + * should be avoided for new generic flags: 3, 4, 5, 6, 7, 8, 9, 16, 24, 25, 26. + */ +#ifndef SA_NOCLDSTOP +#define SA_NOCLDSTOP 0x00000001 +#endif +#ifndef SA_NOCLDWAIT +#define SA_NOCLDWAIT 0x00000002 +#endif +#ifndef SA_SIGINFO +#define SA_SIGINFO 0x00000004 +#endif +#ifndef SA_ONSTACK +#define SA_ONSTACK 0x08000000 +#endif +#ifndef SA_RESTART +#define SA_RESTART 0x10000000 +#endif +#ifndef SA_NODEFER +#define SA_NODEFER 0x40000000 +#endif +#ifndef SA_RESETHAND +#define SA_RESETHAND 0x80000000 +#endif + +#define SA_NOMASK SA_NODEFER +#define SA_ONESHOT SA_RESETHAND + +/* + * New architectures should not define the obsolete + * SA_RESTORER 0x04000000 + */ + #ifndef SIG_BLOCK #define SIG_BLOCK 0 /* for blocking signals */ #endif diff --git a/include/uapi/asm-generic/signal.h b/include/uapi/asm-generic/signal.h index 5c716a952cbe..f634822906e4 100644 --- a/include/uapi/asm-generic/signal.h +++ b/include/uapi/asm-generic/signal.h @@ -52,35 +52,6 @@ #define SIGRTMAX _NSIG #endif -/* - * SA_FLAGS values: - * - * SA_ONSTACK indicates that a registered stack_t will be used. - * SA_RESTART flag to get restarting signals (which were the default long ago) - * SA_NOCLDSTOP flag to turn off SIGCHLD when children stop. - * SA_RESETHAND clears the handler when the signal is delivered. - * SA_NOCLDWAIT flag on SIGCHLD to inhibit zombies. - * SA_NODEFER prevents the current signal from being masked in the handler. - * - * SA_ONESHOT and SA_NOMASK are the historical Linux names for the Single - * Unix names RESETHAND and NODEFER respectively. - */ -#define SA_NOCLDSTOP 0x00000001 -#define SA_NOCLDWAIT 0x00000002 -#define SA_SIGINFO 0x00000004 -#define SA_ONSTACK 0x08000000 -#define SA_RESTART 0x10000000 -#define SA_NODEFER 0x40000000 -#define SA_RESETHAND 0x80000000 - -#define SA_NOMASK SA_NODEFER -#define SA_ONESHOT SA_RESETHAND - -/* - * New architectures should not define the obsolete - * SA_RESTORER 0x04000000 - */ - #if !defined MINSIGSTKSZ || !defined SIGSTKSZ #define MINSIGSTKSZ 2048 #define SIGSTKSZ 8192 -- cgit v1.2.3-59-g8ed1b From 23acdc76f1798b090bb9dcc90671cd29d929834e Mon Sep 17 00:00:00 2001 From: Peter Collingbourne Date: Thu, 12 Nov 2020 18:53:34 -0800 Subject: signal: clear non-uapi flag bits when passing/returning sa_flags Previously we were not clearing non-uapi flag bits in sigaction.sa_flags when storing the userspace-provided sa_flags or when returning them via oldact. Start doing so. This allows userspace to detect missing support for flag bits and allows the kernel to use non-uapi bits internally, as we are already doing in arch/x86 for two flag bits. Now that this change is in place, we no longer need the code in arch/x86 that was hiding these bits from userspace, so remove it. This is technically a userspace-visible behavior change for sigaction, as the unknown bits returned via oldact.sa_flags are no longer set. However, we are free to define the behavior for unknown bits exactly because their behavior is currently undefined, so for now we can define the meaning of each of them to be "clear the bit in oldact.sa_flags unless the bit becomes known in the future". Furthermore, this behavior is consistent with OpenBSD [1], illumos [2] and XNU [3] (FreeBSD [4] and NetBSD [5] fail the syscall if unknown bits are set). So there is some precedent for this behavior in other kernels, and in particular in XNU, which is probably the most popular kernel among those that I looked at, which means that this change is less likely to be a compatibility issue. Link: [1] https://github.com/openbsd/src/blob/f634a6a4b5bf832e9c1de77f7894ae2625e74484/sys/kern/kern_sig.c#L278 Link: [2] https://github.com/illumos/illumos-gate/blob/76f19f5fdc974fe5be5c82a556e43a4df93f1de1/usr/src/uts/common/syscall/sigaction.c#L86 Link: [3] https://github.com/apple/darwin-xnu/blob/a449c6a3b8014d9406c2ddbdc81795da24aa7443/bsd/kern/kern_sig.c#L480 Link: [4] https://github.com/freebsd/freebsd/blob/eded70c37057857c6e23fae51f86b8f8f43cd2d0/sys/kern/kern_sig.c#L699 Link: [5] https://github.com/NetBSD/src/blob/3365779becdcedfca206091a645a0e8e22b2946e/sys/kern/sys_sig.c#L473 Signed-off-by: Peter Collingbourne Reviewed-by: Dave Martin Acked-by: "Eric W. Biederman" Link: https://linux-review.googlesource.com/id/I35aab6f5be932505d90f3b3450c083b4db1eca86 Link: https://lkml.kernel.org/r/878dbcb5f47bc9b11881c81f745c0bef5c23f97f.1605235762.git.pcc@google.com Signed-off-by: Eric W. Biederman --- arch/arm/include/asm/signal.h | 2 ++ arch/parisc/include/asm/signal.h | 2 ++ arch/x86/kernel/signal_compat.c | 7 ------- include/linux/signal_types.h | 12 ++++++++++++ kernel/signal.c | 10 ++++++++++ 5 files changed, 26 insertions(+), 7 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/include/asm/signal.h b/arch/arm/include/asm/signal.h index 65530a042009..430be7774402 100644 --- a/arch/arm/include/asm/signal.h +++ b/arch/arm/include/asm/signal.h @@ -17,6 +17,8 @@ typedef struct { unsigned long sig[_NSIG_WORDS]; } sigset_t; +#define __ARCH_UAPI_SA_FLAGS (SA_THIRTYTWO | SA_RESTORER) + #define __ARCH_HAS_SA_RESTORER #include diff --git a/arch/parisc/include/asm/signal.h b/arch/parisc/include/asm/signal.h index 715c96ba2ec8..30dd1e43ef88 100644 --- a/arch/parisc/include/asm/signal.h +++ b/arch/parisc/include/asm/signal.h @@ -21,6 +21,8 @@ typedef struct { unsigned long sig[_NSIG_WORDS]; } sigset_t; +#define __ARCH_UAPI_SA_FLAGS _SA_SIGGFAULT + #include #endif /* !__ASSEMBLY */ diff --git a/arch/x86/kernel/signal_compat.c b/arch/x86/kernel/signal_compat.c index a7f3e12cfbdb..ddfd919be46c 100644 --- a/arch/x86/kernel/signal_compat.c +++ b/arch/x86/kernel/signal_compat.c @@ -165,16 +165,9 @@ void sigaction_compat_abi(struct k_sigaction *act, struct k_sigaction *oact) { signal_compat_build_tests(); - /* Don't leak in-kernel non-uapi flags to user-space */ - if (oact) - oact->sa.sa_flags &= ~(SA_IA32_ABI | SA_X32_ABI); - if (!act) return; - /* Don't let flags to be set from userspace */ - act->sa.sa_flags &= ~(SA_IA32_ABI | SA_X32_ABI); - if (in_ia32_syscall()) act->sa.sa_flags |= SA_IA32_ABI; if (in_x32_syscall()) diff --git a/include/linux/signal_types.h b/include/linux/signal_types.h index f8a90ae9c6ec..a7887ad84d36 100644 --- a/include/linux/signal_types.h +++ b/include/linux/signal_types.h @@ -68,4 +68,16 @@ struct ksignal { int sig; }; +#ifndef __ARCH_UAPI_SA_FLAGS +#ifdef SA_RESTORER +#define __ARCH_UAPI_SA_FLAGS SA_RESTORER +#else +#define __ARCH_UAPI_SA_FLAGS 0 +#endif +#endif + +#define UAPI_SA_FLAGS \ + (SA_NOCLDSTOP | SA_NOCLDWAIT | SA_SIGINFO | SA_ONSTACK | SA_RESTART | \ + SA_NODEFER | SA_RESETHAND | __ARCH_UAPI_SA_FLAGS) + #endif /* _LINUX_SIGNAL_TYPES_H */ diff --git a/kernel/signal.c b/kernel/signal.c index ef8f2a28d37c..8f5bd12ee41b 100644 --- a/kernel/signal.c +++ b/kernel/signal.c @@ -3985,6 +3985,16 @@ int do_sigaction(int sig, struct k_sigaction *act, struct k_sigaction *oact) if (oact) *oact = *k; + /* + * Clear unknown flag bits in order to allow userspace to detect missing + * support for flag bits and to allow the kernel to use non-uapi bits + * internally. + */ + if (act) + act->sa.sa_flags &= UAPI_SA_FLAGS; + if (oact) + oact->sa.sa_flags &= UAPI_SA_FLAGS; + sigaction_compat_abi(act, oact); if (act) { -- cgit v1.2.3-59-g8ed1b From eaf7697b6febe2b086503f525f070d8e3ca1ea0f Mon Sep 17 00:00:00 2001 From: David Lechner Date: Mon, 12 Oct 2020 16:12:29 -0500 Subject: ARM: omap2plus_defconfig: Enable TI eQEP counter driver This enables the TI eQEP counter driver that is used by BeagleBone Blue. Signed-off-by: David Lechner Signed-off-by: Tony Lindgren --- arch/arm/configs/omap2plus_defconfig | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/configs/omap2plus_defconfig b/arch/arm/configs/omap2plus_defconfig index 2ab9024cb6e3..77716f500813 100644 --- a/arch/arm/configs/omap2plus_defconfig +++ b/arch/arm/configs/omap2plus_defconfig @@ -539,6 +539,8 @@ CONFIG_PHY_DM816X_USB=m CONFIG_OMAP_USB2=m CONFIG_TI_PIPE3=y CONFIG_TWL4030_USB=m +CONFIG_COUNTER=m +CONFIG_TI_EQEP=m CONFIG_EXT2_FS=y CONFIG_EXT3_FS=y CONFIG_EXT4_FS_SECURITY=y -- cgit v1.2.3-59-g8ed1b From 5ba6291086d2ae8006be9e0f19bf2001a85c9dc1 Mon Sep 17 00:00:00 2001 From: Cristian Birsan Date: Wed, 18 Nov 2020 14:00:17 +0200 Subject: ARM: dts: at91: sam9x60: add pincontrol for USB Host The pincontrol node is needed for USB Host since Linux v5.7-rc1. Without it the driver probes but VBus is not powered because of wrong pincontrol configuration. Fixes: 1e5f532c2737 ("ARM: dts: at91: sam9x60: add device tree for soc and board") Signed-off-by: Cristian Birsan Signed-off-by: Alexandre Belloni Acked-by: Ludovic Desroches Link: https://lore.kernel.org/r/20201118120019.1257580-2-cristian.birsan@microchip.com --- arch/arm/boot/dts/at91-sam9x60ek.dts | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/at91-sam9x60ek.dts b/arch/arm/boot/dts/at91-sam9x60ek.dts index eae28b82c7fd..0e3b6147069f 100644 --- a/arch/arm/boot/dts/at91-sam9x60ek.dts +++ b/arch/arm/boot/dts/at91-sam9x60ek.dts @@ -569,6 +569,13 @@ atmel,pins = ; }; }; + + usb1 { + pinctrl_usb_default: usb_default { + atmel,pins = ; + }; + }; }; /* pinctrl */ &pmc { @@ -684,6 +691,8 @@ atmel,vbus-gpio = <0 &pioD 15 GPIO_ACTIVE_HIGH &pioD 16 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_default>; status = "okay"; }; -- cgit v1.2.3-59-g8ed1b From be4dd2d448816a27c1446f8f37fce375daf64148 Mon Sep 17 00:00:00 2001 From: Cristian Birsan Date: Wed, 18 Nov 2020 14:00:18 +0200 Subject: ARM: dts: at91: sama5d4_xplained: add pincontrol for USB Host The pincontrol node is needed for USB Host since Linux v5.7-rc1. Without it the driver probes but VBus is not powered because of wrong pincontrol configuration. Fixes: 38153a017896f ("ARM: at91/dt: sama5d4: add dts for sama5d4 xplained board") Signed-off-by: Cristian Birsan Signed-off-by: Alexandre Belloni Acked-by: Ludovic Desroches Link: https://lore.kernel.org/r/20201118120019.1257580-3-cristian.birsan@microchip.com --- arch/arm/boot/dts/at91-sama5d4_xplained.dts | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/at91-sama5d4_xplained.dts b/arch/arm/boot/dts/at91-sama5d4_xplained.dts index e5974a17374c..0b3ad1b580b8 100644 --- a/arch/arm/boot/dts/at91-sama5d4_xplained.dts +++ b/arch/arm/boot/dts/at91-sama5d4_xplained.dts @@ -134,6 +134,11 @@ atmel,pins = ; }; + pinctrl_usb_default: usb_default { + atmel,pins = + ; + }; pinctrl_key_gpio: key_gpio_0 { atmel,pins = ; @@ -159,6 +164,8 @@ &pioE 11 GPIO_ACTIVE_HIGH &pioE 14 GPIO_ACTIVE_HIGH >; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_default>; status = "okay"; }; -- cgit v1.2.3-59-g8ed1b From e1062fa7292f1e3744db0a487c4ac0109e09b03d Mon Sep 17 00:00:00 2001 From: Cristian Birsan Date: Wed, 18 Nov 2020 14:00:19 +0200 Subject: ARM: dts: at91: sama5d3_xplained: add pincontrol for USB Host The pincontrol node is needed for USB Host since Linux v5.7-rc1. Without it the driver probes but VBus is not powered because of wrong pincontrol configuration. Fixes: b7c2b61570798 ("ARM: at91: add Atmel's SAMA5D3 Xplained board") Signed-off-by: Cristian Birsan Signed-off-by: Alexandre Belloni Acked-by: Ludovic Desroches Link: https://lore.kernel.org/r/20201118120019.1257580-4-cristian.birsan@microchip.com --- arch/arm/boot/dts/at91-sama5d3_xplained.dts | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/at91-sama5d3_xplained.dts b/arch/arm/boot/dts/at91-sama5d3_xplained.dts index cf13632edd44..5179258f9247 100644 --- a/arch/arm/boot/dts/at91-sama5d3_xplained.dts +++ b/arch/arm/boot/dts/at91-sama5d3_xplained.dts @@ -242,6 +242,11 @@ atmel,pins = ; /* PE9, conflicts with A9 */ }; + pinctrl_usb_default: usb_default { + atmel,pins = + ; + }; }; }; }; @@ -259,6 +264,8 @@ &pioE 3 GPIO_ACTIVE_LOW &pioE 4 GPIO_ACTIVE_LOW >; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_default>; status = "okay"; }; -- cgit v1.2.3-59-g8ed1b From 30ea026e33c6dda48849d9fe0d15c1d280a92d53 Mon Sep 17 00:00:00 2001 From: Zhen Lei Date: Mon, 12 Oct 2020 14:12:16 +0800 Subject: ARM: dts: hisilicon: fix errors detected by snps-dw-apb-uart.yaml 1. Change node name to match '^serial(@[0-9a-f,]+)*$' 2. Change clock-names to "baudclk", "apb_pclk". Both of them use the same clock. Signed-off-by: Zhen Lei Signed-off-by: Wei Xu --- arch/arm/boot/dts/hip01.dtsi | 24 ++++++++++++------------ arch/arm/boot/dts/hip04-d01.dts | 2 +- arch/arm/boot/dts/hip04.dtsi | 6 +++--- 3 files changed, 16 insertions(+), 16 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/hip01.dtsi b/arch/arm/boot/dts/hip01.dtsi index 975d39828405..fd09e6d9309c 100644 --- a/arch/arm/boot/dts/hip01.dtsi +++ b/arch/arm/boot/dts/hip01.dtsi @@ -41,41 +41,41 @@ compatible = "simple-bus"; ranges; - uart0: uart@10001000 { + uart0: serial@10001000 { compatible = "snps,dw-apb-uart"; reg = <0x10001000 0x1000>; - clocks = <&hisi_refclk144mhz>; - clock-names = "apb_pclk"; + clocks = <&hisi_refclk144mhz>, <&hisi_refclk144mhz>; + clock-names = "baudclk", "apb_pclk"; reg-shift = <2>; interrupts = <0 32 4>; status = "disabled"; }; - uart1: uart@10002000 { + uart1: serial@10002000 { compatible = "snps,dw-apb-uart"; reg = <0x10002000 0x1000>; - clocks = <&hisi_refclk144mhz>; - clock-names = "apb_pclk"; + clocks = <&hisi_refclk144mhz>, <&hisi_refclk144mhz>; + clock-names = "baudclk", "apb_pclk"; reg-shift = <2>; interrupts = <0 33 4>; status = "disabled"; }; - uart2: uart@10003000 { + uart2: serial@10003000 { compatible = "snps,dw-apb-uart"; reg = <0x10003000 0x1000>; - clocks = <&hisi_refclk144mhz>; - clock-names = "apb_pclk"; + clocks = <&hisi_refclk144mhz>, <&hisi_refclk144mhz>; + clock-names = "baudclk", "apb_pclk"; reg-shift = <2>; interrupts = <0 34 4>; status = "disabled"; }; - uart3: uart@10006000 { + uart3: serial@10006000 { compatible = "snps,dw-apb-uart"; reg = <0x10006000 0x1000>; - clocks = <&hisi_refclk144mhz>; - clock-names = "apb_pclk"; + clocks = <&hisi_refclk144mhz>, <&hisi_refclk144mhz>; + clock-names = "baudclk", "apb_pclk"; reg-shift = <2>; interrupts = <0 4 4>; status = "disabled"; diff --git a/arch/arm/boot/dts/hip04-d01.dts b/arch/arm/boot/dts/hip04-d01.dts index 9019e0d2ef60..f5691dbc26d2 100644 --- a/arch/arm/boot/dts/hip04-d01.dts +++ b/arch/arm/boot/dts/hip04-d01.dts @@ -22,7 +22,7 @@ }; soc { - uart0: uart@4007000 { + uart0: serial@4007000 { status = "ok"; }; }; diff --git a/arch/arm/boot/dts/hip04.dtsi b/arch/arm/boot/dts/hip04.dtsi index 555bc6b6720f..bccf5ba3d855 100644 --- a/arch/arm/boot/dts/hip04.dtsi +++ b/arch/arm/boot/dts/hip04.dtsi @@ -250,12 +250,12 @@ <0 79 4>; }; - uart0: uart@4007000 { + uart0: serial@4007000 { compatible = "snps,dw-apb-uart"; reg = <0x4007000 0x1000>; interrupts = <0 381 4>; - clocks = <&clk_168m>; - clock-names = "uartclk"; + clocks = <&clk_168m>, <&clk_168m>; + clock-names = "baudclk", "apb_pclk"; reg-shift = <2>; status = "disabled"; }; -- cgit v1.2.3-59-g8ed1b From e5e225fd495ef1dffc64b81b2094e427f9cc4016 Mon Sep 17 00:00:00 2001 From: Zhen Lei Date: Mon, 12 Oct 2020 14:12:17 +0800 Subject: ARM: dts: hisilicon: fix errors detected by pl011.yaml 1. Change node name to match '^serial(@[0-9a-f,]+)*$' 2. Change clock-names to "uartclk", "apb_pclk". Both of them use the same clock. 3. Change pinctrl-names to "default", "sleep". Signed-off-by: Zhen Lei Signed-off-by: Wei Xu --- arch/arm/boot/dts/hi3519.dtsi | 20 ++++++++++---------- arch/arm/boot/dts/hi3620-hi4511.dts | 20 ++++++++++---------- arch/arm/boot/dts/hi3620.dtsi | 30 +++++++++++++++--------------- arch/arm/boot/dts/hisi-x5hd2.dtsi | 30 +++++++++++++++--------------- 4 files changed, 50 insertions(+), 50 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/hi3519.dtsi b/arch/arm/boot/dts/hi3519.dtsi index 410409a0ed66..630753c0d704 100644 --- a/arch/arm/boot/dts/hi3519.dtsi +++ b/arch/arm/boot/dts/hi3519.dtsi @@ -52,8 +52,8 @@ compatible = "arm,pl011", "arm,primecell"; reg = <0x12100000 0x1000>; interrupts = ; - clocks = <&crg HI3519_UART0_CLK>; - clock-names = "apb_pclk"; + clocks = <&crg HI3519_UART0_CLK>, <&crg HI3519_UART0_CLK>; + clock-names = "uartclk", "apb_pclk"; status = "disable"; }; @@ -61,8 +61,8 @@ compatible = "arm,pl011", "arm,primecell"; reg = <0x12101000 0x1000>; interrupts = ; - clocks = <&crg HI3519_UART1_CLK>; - clock-names = "apb_pclk"; + clocks = <&crg HI3519_UART1_CLK>, <&crg HI3519_UART1_CLK>; + clock-names = "uartclk", "apb_pclk"; status = "disable"; }; @@ -70,8 +70,8 @@ compatible = "arm,pl011", "arm,primecell"; reg = <0x12102000 0x1000>; interrupts = ; - clocks = <&crg HI3519_UART2_CLK>; - clock-names = "apb_pclk"; + clocks = <&crg HI3519_UART2_CLK>, <&crg HI3519_UART2_CLK>; + clock-names = "uartclk", "apb_pclk"; status = "disable"; }; @@ -79,8 +79,8 @@ compatible = "arm,pl011", "arm,primecell"; reg = <0x12103000 0x1000>; interrupts = ; - clocks = <&crg HI3519_UART3_CLK>; - clock-names = "apb_pclk"; + clocks = <&crg HI3519_UART3_CLK>, <&crg HI3519_UART3_CLK>; + clock-names = "uartclk", "apb_pclk"; status = "disable"; }; @@ -88,8 +88,8 @@ compatible = "arm,pl011", "arm,primecell"; reg = <0x12104000 0x1000>; interrupts = ; - clocks = <&crg HI3519_UART4_CLK>; - clock-names = "apb_pclk"; + clocks = <&crg HI3519_UART4_CLK>, <&crg HI3519_UART4_CLK>; + clock-names = "uartclk", "apb_pclk"; status = "disable"; }; diff --git a/arch/arm/boot/dts/hi3620-hi4511.dts b/arch/arm/boot/dts/hi3620-hi4511.dts index 8c703c3f2fe0..1c62bdcca647 100644 --- a/arch/arm/boot/dts/hi3620-hi4511.dts +++ b/arch/arm/boot/dts/hi3620-hi4511.dts @@ -27,36 +27,36 @@ status = "ok"; }; - uart0: uart@b00000 { /* console */ - pinctrl-names = "default", "idle"; + uart0: serial@b00000 { /* console */ + pinctrl-names = "default", "sleep"; pinctrl-0 = <&uart0_pmx_func &uart0_cfg_func>; pinctrl-1 = <&uart0_pmx_idle &uart0_cfg_idle>; status = "ok"; }; - uart1: uart@b01000 { /* modem */ - pinctrl-names = "default", "idle"; + uart1: serial@b01000 { /* modem */ + pinctrl-names = "default", "sleep"; pinctrl-0 = <&uart1_pmx_func &uart1_cfg_func>; pinctrl-1 = <&uart1_pmx_idle &uart1_cfg_idle>; status = "ok"; }; - uart2: uart@b02000 { /* audience */ - pinctrl-names = "default", "idle"; + uart2: serial@b02000 { /* audience */ + pinctrl-names = "default", "sleep"; pinctrl-0 = <&uart2_pmx_func &uart2_cfg_func>; pinctrl-1 = <&uart2_pmx_idle &uart2_cfg_idle>; status = "ok"; }; - uart3: uart@b03000 { - pinctrl-names = "default", "idle"; + uart3: serial@b03000 { + pinctrl-names = "default", "sleep"; pinctrl-0 = <&uart3_pmx_func &uart3_cfg_func>; pinctrl-1 = <&uart3_pmx_idle &uart3_cfg_idle>; status = "ok"; }; - uart4: uart@b04000 { - pinctrl-names = "default", "idle"; + uart4: serial@b04000 { + pinctrl-names = "default", "sleep"; pinctrl-0 = <&uart4_pmx_func &uart4_cfg_func>; pinctrl-1 = <&uart4_pmx_idle &uart4_cfg_func>; status = "ok"; diff --git a/arch/arm/boot/dts/hi3620.dtsi b/arch/arm/boot/dts/hi3620.dtsi index f683440ee569..d41378391e4c 100644 --- a/arch/arm/boot/dts/hi3620.dtsi +++ b/arch/arm/boot/dts/hi3620.dtsi @@ -172,48 +172,48 @@ interrupts = <1 13 0xf01>; }; - uart0: uart@b00000 { + uart0: serial@b00000 { compatible = "arm,pl011", "arm,primecell"; reg = <0xb00000 0x1000>; interrupts = <0 20 4>; - clocks = <&clock HI3620_UARTCLK0>; - clock-names = "apb_pclk"; + clocks = <&clock HI3620_UARTCLK0>, <&clock HI3620_UARTCLK0>; + clock-names = "uartclk", "apb_pclk"; status = "disabled"; }; - uart1: uart@b01000 { + uart1: serial@b01000 { compatible = "arm,pl011", "arm,primecell"; reg = <0xb01000 0x1000>; interrupts = <0 21 4>; - clocks = <&clock HI3620_UARTCLK1>; - clock-names = "apb_pclk"; + clocks = <&clock HI3620_UARTCLK1>, <&clock HI3620_UARTCLK1>; + clock-names = "uartclk", "apb_pclk"; status = "disabled"; }; - uart2: uart@b02000 { + uart2: serial@b02000 { compatible = "arm,pl011", "arm,primecell"; reg = <0xb02000 0x1000>; interrupts = <0 22 4>; - clocks = <&clock HI3620_UARTCLK2>; - clock-names = "apb_pclk"; + clocks = <&clock HI3620_UARTCLK2>, <&clock HI3620_UARTCLK2>; + clock-names = "uartclk", "apb_pclk"; status = "disabled"; }; - uart3: uart@b03000 { + uart3: serial@b03000 { compatible = "arm,pl011", "arm,primecell"; reg = <0xb03000 0x1000>; interrupts = <0 23 4>; - clocks = <&clock HI3620_UARTCLK3>; - clock-names = "apb_pclk"; + clocks = <&clock HI3620_UARTCLK3>, <&clock HI3620_UARTCLK3>; + clock-names = "uartclk", "apb_pclk"; status = "disabled"; }; - uart4: uart@b04000 { + uart4: serial@b04000 { compatible = "arm,pl011", "arm,primecell"; reg = <0xb04000 0x1000>; interrupts = <0 24 4>; - clocks = <&clock HI3620_UARTCLK4>; - clock-names = "apb_pclk"; + clocks = <&clock HI3620_UARTCLK4>, <&clock HI3620_UARTCLK4>; + clock-names = "uartclk", "apb_pclk"; status = "disabled"; }; diff --git a/arch/arm/boot/dts/hisi-x5hd2.dtsi b/arch/arm/boot/dts/hisi-x5hd2.dtsi index e2dbf1d8a67b..f645487402f6 100644 --- a/arch/arm/boot/dts/hisi-x5hd2.dtsi +++ b/arch/arm/boot/dts/hisi-x5hd2.dtsi @@ -86,48 +86,48 @@ status = "disabled"; }; - uart0: uart@b00000 { + uart0: serial@b00000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x00b00000 0x1000>; interrupts = <0 49 4>; - clocks = <&clock HIX5HD2_FIXED_83M>; - clock-names = "apb_pclk"; + clocks = <&clock HIX5HD2_FIXED_83M>, <&clock HIX5HD2_FIXED_83M>; + clock-names = "uartclk", "apb_pclk"; status = "disabled"; }; - uart1: uart@6000 { + uart1: serial@6000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x00006000 0x1000>; interrupts = <0 50 4>; - clocks = <&clock HIX5HD2_FIXED_83M>; - clock-names = "apb_pclk"; + clocks = <&clock HIX5HD2_FIXED_83M>, <&clock HIX5HD2_FIXED_83M>; + clock-names = "uartclk", "apb_pclk"; status = "disabled"; }; - uart2: uart@b02000 { + uart2: serial@b02000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x00b02000 0x1000>; interrupts = <0 51 4>; - clocks = <&clock HIX5HD2_FIXED_83M>; - clock-names = "apb_pclk"; + clocks = <&clock HIX5HD2_FIXED_83M>, <&clock HIX5HD2_FIXED_83M>; + clock-names = "uartclk", "apb_pclk"; status = "disabled"; }; - uart3: uart@b03000 { + uart3: serial@b03000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x00b03000 0x1000>; interrupts = <0 52 4>; - clocks = <&clock HIX5HD2_FIXED_83M>; - clock-names = "apb_pclk"; + clocks = <&clock HIX5HD2_FIXED_83M>, <&clock HIX5HD2_FIXED_83M>; + clock-names = "uartclk", "apb_pclk"; status = "disabled"; }; - uart4: uart@b04000 { + uart4: serial@b04000 { compatible = "arm,pl011", "arm,primecell"; reg = <0xb04000 0x1000>; interrupts = <0 53 4>; - clocks = <&clock HIX5HD2_FIXED_83M>; - clock-names = "apb_pclk"; + clocks = <&clock HIX5HD2_FIXED_83M>, <&clock HIX5HD2_FIXED_83M>; + clock-names = "uartclk", "apb_pclk"; status = "disabled"; }; -- cgit v1.2.3-59-g8ed1b From 64f5b52554a1de47a53972a47b9b58d8d66ee5aa Mon Sep 17 00:00:00 2001 From: Zhen Lei Date: Mon, 12 Oct 2020 14:12:18 +0800 Subject: ARM: dts: hisilicon: fix errors detected by usb yaml 1. Change node name to match '^usb(@.*)?' These errors are detected by generic-ehci.yaml and generic-ohci.yaml. Signed-off-by: Zhen Lei Signed-off-by: Wei Xu --- arch/arm/boot/dts/hisi-x5hd2.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/hisi-x5hd2.dtsi b/arch/arm/boot/dts/hisi-x5hd2.dtsi index f645487402f6..0c1708945813 100644 --- a/arch/arm/boot/dts/hisi-x5hd2.dtsi +++ b/arch/arm/boot/dts/hisi-x5hd2.dtsi @@ -453,14 +453,14 @@ status = "disabled"; }; - usb0: ehci@1890000 { + usb0: usb@1890000 { compatible = "generic-ehci"; reg = <0x1890000 0x1000>; interrupts = <0 66 4>; clocks = <&clock HIX5HD2_USB_CLK>; }; - usb1: ohci@1880000 { + usb1: usb@1880000 { compatible = "generic-ohci"; reg = <0x1880000 0x1000>; interrupts = <0 67 4>; -- cgit v1.2.3-59-g8ed1b From 8e9e8dd7ce093344a89792deaeb6caedde636dcf Mon Sep 17 00:00:00 2001 From: Zhen Lei Date: Mon, 12 Oct 2020 14:12:19 +0800 Subject: ARM: dts: hisilicon: fix errors detected by simple-bus.yaml Change bus node name from "amba" to "amba-bus" to match '^([a-z][a-z0-9\\-]+-bus|bus|soc|axi|ahb|apb)(@[0-9a-f]+)?$' Signed-off-by: Zhen Lei Signed-off-by: Wei Xu --- arch/arm/boot/dts/hi3620-hi4511.dts | 2 +- arch/arm/boot/dts/hi3620.dtsi | 2 +- arch/arm/boot/dts/hip01.dtsi | 2 +- arch/arm/boot/dts/hisi-x5hd2.dtsi | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/hi3620-hi4511.dts b/arch/arm/boot/dts/hi3620-hi4511.dts index 1c62bdcca647..29eedc7fef98 100644 --- a/arch/arm/boot/dts/hi3620-hi4511.dts +++ b/arch/arm/boot/dts/hi3620-hi4511.dts @@ -22,7 +22,7 @@ reg = <0x40000000 0x20000000>; }; - amba { + amba-bus { dual_timer0: dual_timer@800000 { status = "ok"; }; diff --git a/arch/arm/boot/dts/hi3620.dtsi b/arch/arm/boot/dts/hi3620.dtsi index d41378391e4c..905900bf3e82 100644 --- a/arch/arm/boot/dts/hi3620.dtsi +++ b/arch/arm/boot/dts/hi3620.dtsi @@ -63,7 +63,7 @@ }; }; - amba { + amba-bus { #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/hip01.dtsi b/arch/arm/boot/dts/hip01.dtsi index fd09e6d9309c..2a7963605390 100644 --- a/arch/arm/boot/dts/hip01.dtsi +++ b/arch/arm/boot/dts/hip01.dtsi @@ -35,7 +35,7 @@ interrupt-parent = <&gic>; ranges = <0 0x10000000 0x20000000>; - amba { + amba-bus { #address-cells = <1>; #size-cells = <1>; compatible = "simple-bus"; diff --git a/arch/arm/boot/dts/hisi-x5hd2.dtsi b/arch/arm/boot/dts/hisi-x5hd2.dtsi index 0c1708945813..8fdfde492919 100644 --- a/arch/arm/boot/dts/hisi-x5hd2.dtsi +++ b/arch/arm/boot/dts/hisi-x5hd2.dtsi @@ -30,7 +30,7 @@ interrupt-parent = <&gic>; ranges = <0 0xf8000000 0x8000000>; - amba { + amba-bus { #address-cells = <1>; #size-cells = <1>; compatible = "simple-bus"; -- cgit v1.2.3-59-g8ed1b From e0b09c35ae072be666bdd847dddf9a51bd4d57dc Mon Sep 17 00:00:00 2001 From: Zhen Lei Date: Mon, 12 Oct 2020 14:12:20 +0800 Subject: ARM: dts: hisilicon: fix errors detected by root-node.yaml Make the memory node name match the regex "^memory(@[0-9a-f]+)?$" which is described in memory.yaml. Otherwise, it will be treated as root node, and misreported by root-node.yaml. Errors misreported by root-node.yaml: /: memory: False schema does not allow {'device_type': ['memory'], 'reg': Signed-off-by: Zhen Lei Signed-off-by: Wei Xu --- arch/arm/boot/dts/hi3519-demb.dts | 2 +- arch/arm/boot/dts/hi3620-hi4511.dts | 2 +- arch/arm/boot/dts/hip01-ca9x2.dts | 2 +- arch/arm/boot/dts/hisi-x5hd2-dkb.dts | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/hi3519-demb.dts b/arch/arm/boot/dts/hi3519-demb.dts index 64f8ed126931..f473fa22e9ce 100644 --- a/arch/arm/boot/dts/hi3519-demb.dts +++ b/arch/arm/boot/dts/hi3519-demb.dts @@ -14,7 +14,7 @@ serial0 = &uart0; }; - memory { + memory@80000000 { device_type = "memory"; reg = <0x80000000 0x40000000>; }; diff --git a/arch/arm/boot/dts/hi3620-hi4511.dts b/arch/arm/boot/dts/hi3620-hi4511.dts index 29eedc7fef98..ce356c469e1e 100644 --- a/arch/arm/boot/dts/hi3620-hi4511.dts +++ b/arch/arm/boot/dts/hi3620-hi4511.dts @@ -17,7 +17,7 @@ stdout-path = "serial0:115200n8"; }; - memory { + memory@40000000 { device_type = "memory"; reg = <0x40000000 0x20000000>; }; diff --git a/arch/arm/boot/dts/hip01-ca9x2.dts b/arch/arm/boot/dts/hip01-ca9x2.dts index f05e74eacfe0..031476304d94 100644 --- a/arch/arm/boot/dts/hip01-ca9x2.dts +++ b/arch/arm/boot/dts/hip01-ca9x2.dts @@ -37,7 +37,7 @@ }; }; - memory { + memory@80000000 { device_type = "memory"; reg = <0x80000000 0x80000000>; }; diff --git a/arch/arm/boot/dts/hisi-x5hd2-dkb.dts b/arch/arm/boot/dts/hisi-x5hd2-dkb.dts index d55e9cd3b12b..22b122d3f514 100644 --- a/arch/arm/boot/dts/hisi-x5hd2-dkb.dts +++ b/arch/arm/boot/dts/hisi-x5hd2-dkb.dts @@ -35,7 +35,7 @@ }; }; - memory { + memory@0 { device_type = "memory"; reg = <0x00000000 0x80000000>; }; -- cgit v1.2.3-59-g8ed1b From 05484c171d39433daa8b75c0c4c5fb454091e9b7 Mon Sep 17 00:00:00 2001 From: Zhen Lei Date: Mon, 12 Oct 2020 14:12:21 +0800 Subject: ARM: dts: hisilicon: fix errors detected by synopsys-dw-mshc.yaml Look at the clock-names schema defined in synopsys-dw-mshc.yaml: clock-names: items: - const: biu - const: ciu The "biu" needs to be placed before the "ciu". Signed-off-by: Zhen Lei Signed-off-by: Wei Xu --- arch/arm/boot/dts/hisi-x5hd2.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/hisi-x5hd2.dtsi b/arch/arm/boot/dts/hisi-x5hd2.dtsi index 8fdfde492919..9a513893758b 100644 --- a/arch/arm/boot/dts/hisi-x5hd2.dtsi +++ b/arch/arm/boot/dts/hisi-x5hd2.dtsi @@ -423,7 +423,7 @@ interrupts = <0 35 4>; clocks = <&clock HIX5HD2_MMC_CIU_RST>, <&clock HIX5HD2_MMC_BIU_CLK>; - clock-names = "ciu", "biu"; + clock-names = "biu", "ciu"; }; sd: mmc@1820000 { @@ -432,7 +432,7 @@ interrupts = <0 34 4>; clocks = <&clock HIX5HD2_SD_CIU_RST>, <&clock HIX5HD2_SD_BIU_CLK>; - clock-names = "ciu","biu"; + clock-names = "biu", "ciu"; }; gmac0: ethernet@1840000 { -- cgit v1.2.3-59-g8ed1b From 4c246408f0bdbc4100c95a5dad9e0688b4a3cfd0 Mon Sep 17 00:00:00 2001 From: Zhen Lei Date: Mon, 12 Oct 2020 14:12:22 +0800 Subject: ARM: dts: hisilicon: fix errors detected by spi-pl022.yaml 1. Change clock-names to "sspclk", "apb_pclk". Both of them use the same clock. Signed-off-by: Zhen Lei Signed-off-by: Wei Xu --- arch/arm/boot/dts/hi3519.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/hi3519.dtsi b/arch/arm/boot/dts/hi3519.dtsi index 630753c0d704..c524c854d319 100644 --- a/arch/arm/boot/dts/hi3519.dtsi +++ b/arch/arm/boot/dts/hi3519.dtsi @@ -127,8 +127,8 @@ compatible = "arm,pl022", "arm,primecell"; reg = <0x12120000 0x1000>; interrupts = ; - clocks = <&crg HI3519_SPI0_CLK>; - clock-names = "apb_pclk"; + clocks = <&crg HI3519_SPI0_CLK>, <&crg HI3519_SPI0_CLK>; + clock-names = "sspclk", "apb_pclk"; num-cs = <1>; #address-cells = <1>; #size-cells = <0>; @@ -139,8 +139,8 @@ compatible = "arm,pl022", "arm,primecell"; reg = <0x12121000 0x1000>; interrupts = ; - clocks = <&crg HI3519_SPI1_CLK>; - clock-names = "apb_pclk"; + clocks = <&crg HI3519_SPI1_CLK>, <&crg HI3519_SPI1_CLK>; + clock-names = "sspclk", "apb_pclk"; num-cs = <1>; #address-cells = <1>; #size-cells = <0>; @@ -151,8 +151,8 @@ compatible = "arm,pl022", "arm,primecell"; reg = <0x12122000 0x1000>; interrupts = ; - clocks = <&crg HI3519_SPI2_CLK>; - clock-names = "apb_pclk"; + clocks = <&crg HI3519_SPI2_CLK>, <&crg HI3519_SPI2_CLK>; + clock-names = "sspclk", "apb_pclk"; num-cs = <1>; #address-cells = <1>; #size-cells = <0>; -- cgit v1.2.3-59-g8ed1b From d48b6ef74ab06c5b29bd9ee9e830bdc639b196ee Mon Sep 17 00:00:00 2001 From: Zhen Lei Date: Mon, 12 Oct 2020 14:12:23 +0800 Subject: ARM: dts: hisilicon: fix errors detected by syscon.yaml The DT binding for system controller is not allowed to contain only the compatible string "syscon", the Hisilicon peripheral subsystem controller should add compatible string "hisilicon,peri-subctrl". Otherwise, the error "compatible: ['syscon'] is too short" will be reported. Signed-off-by: Zhen Lei Signed-off-by: Wei Xu --- arch/arm/boot/dts/hisi-x5hd2.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/hisi-x5hd2.dtsi b/arch/arm/boot/dts/hisi-x5hd2.dtsi index 9a513893758b..97211385dc89 100644 --- a/arch/arm/boot/dts/hisi-x5hd2.dtsi +++ b/arch/arm/boot/dts/hisi-x5hd2.dtsi @@ -468,7 +468,7 @@ }; peripheral_ctrl: syscon@a20000 { - compatible = "syscon"; + compatible = "hisilicon,peri-subctrl", "syscon"; reg = <0xa20000 0x1000>; }; -- cgit v1.2.3-59-g8ed1b From 036b7334ee6dc10115fbaebd8b04c9e4a17eccb2 Mon Sep 17 00:00:00 2001 From: Michael Klein Date: Mon, 23 Nov 2020 12:45:35 +0100 Subject: ARM: dts: sun8i-h2-plus-bananapi-m2-zero: add gpio-line-names Add gpio-line-names as documented in the Banana Pi wiki [1] and in the schematics [2]. [1]: http://wiki.banana-pi.org/Banana_Pi_BPI-M2_ZERO#GPIO_PIN_define [2]: https://drive.google.com/file/d/0B4PAo2nW2KfnMW5sVkxWSW9qa28/view Signed-off-by: Michael Klein Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20201123114535.1605939-1-michael@fossekall.de --- .../boot/dts/sun8i-h2-plus-bananapi-m2-zero.dts | 64 ++++++++++++++++++++++ 1 file changed, 64 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun8i-h2-plus-bananapi-m2-zero.dts b/arch/arm/boot/dts/sun8i-h2-plus-bananapi-m2-zero.dts index 4c6704e4c57e..e76d56a3df9c 100644 --- a/arch/arm/boot/dts/sun8i-h2-plus-bananapi-m2-zero.dts +++ b/arch/arm/boot/dts/sun8i-h2-plus-bananapi-m2-zero.dts @@ -136,6 +136,70 @@ }; +&pio { + gpio-line-names = + /* PA */ + "CON2-P13", "CON2-P11", "CON2-P22", "CON2-P15", + "CON3-P03", "CON3-P02", "CON2-P07", "CON2-P29", + "CON2-P31", "CON2-P33", "CON2-P35", "CON2-P05", + "CON2-P03", "CON2-P08", "CON2-P10", "CON2-P16", + "CON2-P12", "CON2-P37", "CON2-P28", "CON2-P27", + "CON2-P40", "CON2-P38", "", "", + "", "", "", "", "", "", "", "", + + /* PB */ + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + + /* PC */ + "CON2-P19", "CON2-P21", "CON2-P23", "CON2-P24", + "CON2-P18", "", "", "CON2-P26", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + + /* PD */ + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "CSI-PWR-EN", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + + /* PE */ + "CN3-P17", "CN3-P13", "CN3-P09", "CN3-P07", + "CN3-P19", "CN3-P21", "CN3-P22", "CN3-P20", + "CN3-P18", "CN3-P16", "CN3-P14", "CN3-P12", + "CN3-P05", "CN3-P03", "CN3-P06", "CN3-P08", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + + /* PF */ + "SDC0-D1", "SDC0-D0", "SDC0-CLK", "SDC0-CMD", "SDC0-D3", + "SDC0-D2", "SDC0-DET", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + + /* PG */ + "WL-SDIO-CLK", "WL-SDIO-CMD", "WL-SDIO-D0", "WL-SDIO-D1", + "WL-SDIO-D2", "WL-SDIO-D3", "BT-UART-TX", "BT-UART-RX", + "BT-UART-RTS", "BT-UART-CTS", "WL-WAKE-AP", "BT-WAKE-AP", + "BT-RST-N", "AP-WAKE-BT", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&r_pio { + gpio-line-names = + /* PL */ + "", "CPUX-SET", "CON2-P32", "POWER-KEY", "CON2-P36", + "VCC-IO-EN", "USB0-ID", "WL-PWR-EN", + "PWR-STB", "PWR-DRAM", "PWR-LED", "IR-RX", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + &usb_otg { dr_mode = "otg"; status = "okay"; -- cgit v1.2.3-59-g8ed1b From 225ef3a3e8f48154ca7a4cfe44d3b576aff2f860 Mon Sep 17 00:00:00 2001 From: Marek Szyprowski Date: Tue, 24 Nov 2020 09:33:12 +0100 Subject: ARM: multi_v7_defconfig: make Samsung Exynos EHCI driver a module Exynos EHCI driver is compiled as kernel built-in, but it requires Samsung USB2 Generic PHY driver to operate properly, which is compiled as module. Make the Exynos EHCI driver also a module, because having it built-in makes no sense. Exynos OHCI, which also uses that PHY driver, is already compiled as a module. Signed-off-by: Marek Szyprowski Link: https://lore.kernel.org/r/20201124083312.12356-1-m.szyprowski@samsung.com Signed-off-by: Krzysztof Kozlowski --- arch/arm/configs/multi_v7_defconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig index a33a0b8eda20..95943da93bd3 100644 --- a/arch/arm/configs/multi_v7_defconfig +++ b/arch/arm/configs/multi_v7_defconfig @@ -773,7 +773,7 @@ CONFIG_USB_XHCI_TEGRA=m CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_HCD_STI=y CONFIG_USB_EHCI_TEGRA=y -CONFIG_USB_EHCI_EXYNOS=y +CONFIG_USB_EHCI_EXYNOS=m CONFIG_USB_EHCI_MV=m CONFIG_USB_OHCI_HCD=y CONFIG_USB_OHCI_HCD_STI=y -- cgit v1.2.3-59-g8ed1b From f3ef38160e3dacb490483eb2104b4ce05cd97058 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Mon, 23 Nov 2020 11:23:46 +0100 Subject: usb: isp1301-omap: Convert to use GPIO descriptors This modernized the ISP1301 a bit by switching it to provide a GPIO descriptor from the H2 board if used. Cc: Tony Lindgren Cc: Felipe Balbi Signed-off-by: Linus Walleij Link: https://lore.kernel.org/r/20201123102346.48284-1-linus.walleij@linaro.org Signed-off-by: Greg Kroah-Hartman --- arch/arm/mach-omap1/board-h2.c | 22 ++++++++++++++++++++-- drivers/usb/phy/phy-isp1301-omap.c | 21 +++++++++++++-------- 2 files changed, 33 insertions(+), 10 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-omap1/board-h2.c b/arch/arm/mach-omap1/board-h2.c index cb7ce627ffe8..c40cf5ef8607 100644 --- a/arch/arm/mach-omap1/board-h2.c +++ b/arch/arm/mach-omap1/board-h2.c @@ -16,6 +16,7 @@ * Copyright (C) 2004 Nokia Corporation by Imre Deak */ #include +#include #include #include #include @@ -46,6 +47,9 @@ #include "common.h" #include "board-h2.h" +/* The first 16 SoC GPIO lines are on this GPIO chip */ +#define OMAP_GPIO_LABEL "gpio-0-15" + /* At OMAP1610 Innovator the Ethernet is directly connected to CS1 */ #define OMAP1610_ETHR_START 0x04000300 @@ -334,7 +338,19 @@ static struct i2c_board_info __initdata h2_i2c_board_info[] = { I2C_BOARD_INFO("tps65010", 0x48), .platform_data = &tps_board, }, { - I2C_BOARD_INFO("isp1301_omap", 0x2d), + .type = "isp1301_omap", + .addr = 0x2d, + .dev_name = "isp1301", + }, +}; + +static struct gpiod_lookup_table isp1301_gpiod_table = { + .dev_id = "isp1301", + .table = { + /* Active low since the irq triggers on falling edge */ + GPIO_LOOKUP(OMAP_GPIO_LABEL, 2, + NULL, GPIO_ACTIVE_LOW), + { }, }, }; @@ -406,8 +422,10 @@ static void __init h2_init(void) h2_smc91x_resources[1].end = gpio_to_irq(0); platform_add_devices(h2_devices, ARRAY_SIZE(h2_devices)); omap_serial_init(); + + /* ISP1301 IRQ wired at M14 */ + omap_cfg_reg(M14_1510_GPIO2); h2_i2c_board_info[0].irq = gpio_to_irq(58); - h2_i2c_board_info[1].irq = gpio_to_irq(2); omap_register_i2c_bus(1, 100, h2_i2c_board_info, ARRAY_SIZE(h2_i2c_board_info)); omap1_usb_init(&h2_usb_config); diff --git a/drivers/usb/phy/phy-isp1301-omap.c b/drivers/usb/phy/phy-isp1301-omap.c index 4a6462c92ef2..00506fb01bda 100644 --- a/drivers/usb/phy/phy-isp1301-omap.c +++ b/drivers/usb/phy/phy-isp1301-omap.c @@ -1208,9 +1208,6 @@ static int isp1301_remove(struct i2c_client *i2c) #ifdef CONFIG_USB_OTG otg_unbind(isp); #endif - if (machine_is_omap_h2()) - gpio_free(2); - set_bit(WORK_STOP, &isp->todo); del_timer_sync(&isp->timer); flush_work(&isp->work); @@ -1480,6 +1477,7 @@ isp1301_probe(struct i2c_client *i2c, const struct i2c_device_id *id) { int status; struct isp1301 *isp; + int irq; if (the_transceiver) return 0; @@ -1543,20 +1541,27 @@ isp1301_probe(struct i2c_client *i2c, const struct i2c_device_id *id) #endif if (machine_is_omap_h2()) { + struct gpio_desc *gpiod; + /* full speed signaling by default */ isp1301_set_bits(isp, ISP1301_MODE_CONTROL_1, MC1_SPEED); isp1301_set_bits(isp, ISP1301_MODE_CONTROL_2, MC2_SPD_SUSP_CTRL); - /* IRQ wired at M14 */ - omap_cfg_reg(M14_1510_GPIO2); - if (gpio_request(2, "isp1301") == 0) - gpio_direction_input(2); + gpiod = devm_gpiod_get(&i2c->dev, NULL, GPIOD_IN); + if (IS_ERR(gpiod)) { + dev_err(&i2c->dev, "cannot obtain H2 GPIO\n"); + goto fail; + } + gpiod_set_consumer_name(gpiod, "isp1301"); + irq = gpiod_to_irq(gpiod); isp->irq_type = IRQF_TRIGGER_FALLING; + } else { + irq = i2c->irq; } - status = request_irq(i2c->irq, isp1301_irq, + status = request_irq(irq, isp1301_irq, isp->irq_type, DRIVER_NAME, isp); if (status < 0) { dev_dbg(&i2c->dev, "can't get IRQ %d, err %d\n", -- cgit v1.2.3-59-g8ed1b From 1f4079b626eb6d38cfc638fd88903c1a943d2d2d Mon Sep 17 00:00:00 2001 From: Alexandre GRIVEAUX Date: Thu, 26 Nov 2020 08:05:16 +0100 Subject: ARM: zynq: Add Z-turn board V5 Adding Z-turn board V5 to resolve the change between: "Z-TURNBOARD_schematic.pdf" schematics state version 1 to 4 has Atheros AR8035 "Z-Turn_Board_sch_V15_20160303.pdf" schematics state version 5 has Micrel KSZ9031 Changes v1 -> v2: Instead of using new board, the v2 using a common devicetree for z-turn boards (zynq-zturn-common.dtsi) and for each board a specific DT Signed-off-by: Alexandre GRIVEAUX Link: https://lore.kernel.org/r/20201126070516.85882-1-agriveaux@deutnet.info Signed-off-by: Michal Simek --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/zynq-zturn-common.dtsi | 112 +++++++++++++++++++++++++++++++ arch/arm/boot/dts/zynq-zturn-v5.dts | 15 +++++ arch/arm/boot/dts/zynq-zturn.dts | 101 +--------------------------- 4 files changed, 129 insertions(+), 100 deletions(-) create mode 100644 arch/arm/boot/dts/zynq-zturn-common.dtsi create mode 100644 arch/arm/boot/dts/zynq-zturn-v5.dts (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index ce66ffd5a1bb..3de85fe42f76 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1302,6 +1302,7 @@ dtb-$(CONFIG_ARCH_ZYNQ) += \ zynq-zc770-xm013.dtb \ zynq-zed.dtb \ zynq-zturn.dtb \ + zynq-zturn-v5.dtb \ zynq-zybo.dtb \ zynq-zybo-z7.dtb dtb-$(CONFIG_MACH_ARMADA_370) += \ diff --git a/arch/arm/boot/dts/zynq-zturn-common.dtsi b/arch/arm/boot/dts/zynq-zturn-common.dtsi new file mode 100644 index 000000000000..84f3c85c5bab --- /dev/null +++ b/arch/arm/boot/dts/zynq-zturn-common.dtsi @@ -0,0 +1,112 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2015 Andrea Merello + * Copyright (C) 2017 Alexander Graf + * + * Based on zynq-zed.dts which is: + * Copyright (C) 2011 - 2014 Xilinx + * Copyright (C) 2012 National Instruments Corp. + * + */ + +/dts-v1/; +/include/ "zynq-7000.dtsi" + +/ { + compatible = "xlnx,zynq-7000"; + + aliases { + ethernet0 = &gem0; + serial0 = &uart1; + serial1 = &uart0; + mmc0 = &sdhci0; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x40000000>; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-leds { + compatible = "gpio-leds"; + usr-led1 { + label = "usr-led1"; + gpios = <&gpio0 0x0 0x1>; + default-state = "off"; + }; + + usr-led2 { + label = "usr-led2"; + gpios = <&gpio0 0x9 0x1>; + default-state = "off"; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + autorepeat; + K1 { + label = "K1"; + gpios = <&gpio0 0x32 0x1>; + linux,code = <0x66>; + wakeup-source; + autorepeat; + }; + }; +}; + +&clkc { + ps-clk-frequency = <33333333>; +}; + +&gem0 { + status = "okay"; + phy-mode = "rgmii-id"; + phy-handle = <ðernet_phy>; + + ethernet_phy: ethernet-phy@0 { + }; +}; + +&sdhci0 { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&usb0 { + status = "okay"; + dr_mode = "host"; +}; + +&can0 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + clock-frequency = <400000>; + + stlm75@49 { + status = "okay"; + compatible = "lm75"; + reg = <0x49>; + }; + + accelerometer@53 { + compatible = "adi,adxl345", "adxl345", "adi,adxl34x", "adxl34x"; + reg = <0x53>; + interrupt-parent = <&intc>; + interrupts = <0x0 0x1e 0x4>; + }; +}; diff --git a/arch/arm/boot/dts/zynq-zturn-v5.dts b/arch/arm/boot/dts/zynq-zturn-v5.dts new file mode 100644 index 000000000000..536632a09a25 --- /dev/null +++ b/arch/arm/boot/dts/zynq-zturn-v5.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0 + +/dts-v1/; +/include/ "zynq-zturn-common.dtsi" + +/ { + model = "Zynq Z-Turn MYIR Board V5"; + compatible = "myir,zynq-zturn-v5", "xlnx,zynq-7000"; +}; + +&gem0 { + ethernet_phy: ethernet-phy@0 { + reg = <0x3>; + }; +}; diff --git a/arch/arm/boot/dts/zynq-zturn.dts b/arch/arm/boot/dts/zynq-zturn.dts index 5ec616ebca08..620b24a25e06 100644 --- a/arch/arm/boot/dts/zynq-zturn.dts +++ b/arch/arm/boot/dts/zynq-zturn.dts @@ -1,114 +1,15 @@ // SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2015 Andrea Merello - * Copyright (C) 2017 Alexander Graf - * - * Based on zynq-zed.dts which is: - * Copyright (C) 2011 - 2014 Xilinx - * Copyright (C) 2012 National Instruments Corp. - * - */ /dts-v1/; -/include/ "zynq-7000.dtsi" +/include/ "zynq-zturn-common.dtsi" / { model = "Zynq Z-Turn MYIR Board"; compatible = "myir,zynq-zturn", "xlnx,zynq-7000"; - - aliases { - ethernet0 = &gem0; - serial0 = &uart1; - serial1 = &uart0; - mmc0 = &sdhci0; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x40000000>; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - gpio-leds { - compatible = "gpio-leds"; - usr-led1 { - label = "usr-led1"; - gpios = <&gpio0 0x0 0x1>; - default-state = "off"; - }; - - usr-led2 { - label = "usr-led2"; - gpios = <&gpio0 0x9 0x1>; - default-state = "off"; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - autorepeat; - K1 { - label = "K1"; - gpios = <&gpio0 0x32 0x1>; - linux,code = <0x66>; - wakeup-source; - autorepeat; - }; - }; -}; - -&clkc { - ps-clk-frequency = <33333333>; }; &gem0 { - status = "okay"; - phy-mode = "rgmii-id"; - phy-handle = <ðernet_phy>; - ethernet_phy: ethernet-phy@0 { reg = <0x0>; }; }; - -&sdhci0 { - status = "okay"; -}; - -&uart0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&usb0 { - status = "okay"; - dr_mode = "host"; -}; - -&can0 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - clock-frequency = <400000>; - - stlm75@49 { - status = "okay"; - compatible = "lm75"; - reg = <0x49>; - }; - - accelerometer@53 { - compatible = "adi,adxl345", "adxl345", "adi,adxl34x", "adxl34x"; - reg = <0x53>; - interrupt-parent = <&intc>; - interrupts = <0x0 0x1e 0x4>; - }; -}; -- cgit v1.2.3-59-g8ed1b From 4f551b7bba09114fb33ccfcd18a3874c7fbcebb4 Mon Sep 17 00:00:00 2001 From: Serge Semin Date: Tue, 20 Oct 2020 14:59:38 +0300 Subject: ARM: dts: stm32: Harmonize EHCI/OHCI DT nodes name on stm32mp15 In accordance with the Generic EHCI/OHCI bindings the corresponding node name is suppose to comply with the Generic USB HCD DT schema, which requires the USB nodes to have the name acceptable by the regexp: "^usb(@.*)?" . Make sure the "generic-ehci" and "generic-ohci"-compatible nodes are correctly named. Signed-off-by: Serge Semin Acked-by: Amelie Delaunay Acked-by: Krzysztof Kozlowski Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp151.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/stm32mp151.dtsi b/arch/arm/boot/dts/stm32mp151.dtsi index 00361d9f0187..f0efd51329f6 100644 --- a/arch/arm/boot/dts/stm32mp151.dtsi +++ b/arch/arm/boot/dts/stm32mp151.dtsi @@ -1426,7 +1426,7 @@ status = "disabled"; }; - usbh_ohci: usbh-ohci@5800c000 { + usbh_ohci: usb@5800c000 { compatible = "generic-ohci"; reg = <0x5800c000 0x1000>; clocks = <&rcc USBH>; @@ -1435,7 +1435,7 @@ status = "disabled"; }; - usbh_ehci: usbh-ehci@5800d000 { + usbh_ehci: usb@5800d000 { compatible = "generic-ehci"; reg = <0x5800d000 0x1000>; clocks = <&rcc USBH>; -- cgit v1.2.3-59-g8ed1b From 08f07e9a195adf8ad73a799dc88d47196ac14dea Mon Sep 17 00:00:00 2001 From: Yann Gautier Date: Tue, 20 Oct 2020 16:04:51 +0200 Subject: ARM: dts: stm32: update sdmmc IP version for STM32MP15 Update the IP version to v2.0, which supports linked lists in internal DMA, and is present in STM32MP1 SoCs. The mmci driver supports the v2.0 periph id since 7a2a98be672b ("mmc: mmci: Add support for sdmmc variant revision 2.0"), so it's now Ok to add it into the SoC device tree to benefit from the improved DMA support. Signed-off-by: Ludovic Barre Signed-off-by: Yann Gautier Signed-off-by: Ahmad Fatoum Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp151.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/stm32mp151.dtsi b/arch/arm/boot/dts/stm32mp151.dtsi index f0efd51329f6..6d01b7f8fa51 100644 --- a/arch/arm/boot/dts/stm32mp151.dtsi +++ b/arch/arm/boot/dts/stm32mp151.dtsi @@ -1047,7 +1047,7 @@ sdmmc3: sdmmc@48004000 { compatible = "arm,pl18x", "arm,primecell"; - arm,primecell-periphid = <0x10153180>; + arm,primecell-periphid = <0x00253180>; reg = <0x48004000 0x400>; interrupts = ; interrupt-names = "cmd_irq"; @@ -1360,7 +1360,7 @@ sdmmc1: sdmmc@58005000 { compatible = "arm,pl18x", "arm,primecell"; - arm,primecell-periphid = <0x10153180>; + arm,primecell-periphid = <0x00253180>; reg = <0x58005000 0x1000>; interrupts = ; interrupt-names = "cmd_irq"; @@ -1375,7 +1375,7 @@ sdmmc2: sdmmc@58007000 { compatible = "arm,pl18x", "arm,primecell"; - arm,primecell-periphid = <0x10153180>; + arm,primecell-periphid = <0x00253180>; reg = <0x58007000 0x1000>; interrupts = ; interrupt-names = "cmd_irq"; -- cgit v1.2.3-59-g8ed1b From f885fbca0f53bd6a38183c37518b425f0a6944b4 Mon Sep 17 00:00:00 2001 From: Fabrice Gasnier Date: Fri, 16 Oct 2020 16:40:18 +0200 Subject: ARM: dts: stm32: Add LP timer irqs on stm32mp151 Add all LP timer irqs on stm32mp151. Signed-off-by: Fabrice Gasnier Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp151.dtsi | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/stm32mp151.dtsi b/arch/arm/boot/dts/stm32mp151.dtsi index 6d01b7f8fa51..05a00789e0d6 100644 --- a/arch/arm/boot/dts/stm32mp151.dtsi +++ b/arch/arm/boot/dts/stm32mp151.dtsi @@ -362,6 +362,7 @@ #size-cells = <0>; compatible = "st,stm32-lptimer"; reg = <0x40009000 0x400>; + interrupts-extended = <&exti 47 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc LPTIM1_K>; clock-names = "mux"; status = "disabled"; @@ -1156,6 +1157,7 @@ #size-cells = <0>; compatible = "st,stm32-lptimer"; reg = <0x50021000 0x400>; + interrupts-extended = <&exti 48 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc LPTIM2_K>; clock-names = "mux"; status = "disabled"; @@ -1183,6 +1185,7 @@ #size-cells = <0>; compatible = "st,stm32-lptimer"; reg = <0x50022000 0x400>; + interrupts-extended = <&exti 50 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc LPTIM3_K>; clock-names = "mux"; status = "disabled"; @@ -1203,6 +1206,7 @@ lptimer4: timer@50023000 { compatible = "st,stm32-lptimer"; reg = <0x50023000 0x400>; + interrupts-extended = <&exti 52 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc LPTIM4_K>; clock-names = "mux"; status = "disabled"; @@ -1217,6 +1221,7 @@ lptimer5: timer@50024000 { compatible = "st,stm32-lptimer"; reg = <0x50024000 0x400>; + interrupts-extended = <&exti 53 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc LPTIM5_K>; clock-names = "mux"; status = "disabled"; -- cgit v1.2.3-59-g8ed1b From 928caf877d149318779f3b188e2e2df0725e60e4 Mon Sep 17 00:00:00 2001 From: Fabrice Gasnier Date: Fri, 16 Oct 2020 16:40:19 +0200 Subject: ARM: dts: stm32: Add LP timer wakeup-source on stm32mp151 LP timer can be used to wakeup from stop mode on stm32mp151. Add wakeup-source properties to all LP timer instances. Signed-off-by: Fabrice Gasnier Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp151.dtsi | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/stm32mp151.dtsi b/arch/arm/boot/dts/stm32mp151.dtsi index 05a00789e0d6..6ffcf06dc0e8 100644 --- a/arch/arm/boot/dts/stm32mp151.dtsi +++ b/arch/arm/boot/dts/stm32mp151.dtsi @@ -365,6 +365,7 @@ interrupts-extended = <&exti 47 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc LPTIM1_K>; clock-names = "mux"; + wakeup-source; status = "disabled"; pwm { @@ -1160,6 +1161,7 @@ interrupts-extended = <&exti 48 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc LPTIM2_K>; clock-names = "mux"; + wakeup-source; status = "disabled"; pwm { @@ -1188,6 +1190,7 @@ interrupts-extended = <&exti 50 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc LPTIM3_K>; clock-names = "mux"; + wakeup-source; status = "disabled"; pwm { @@ -1209,6 +1212,7 @@ interrupts-extended = <&exti 52 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc LPTIM4_K>; clock-names = "mux"; + wakeup-source; status = "disabled"; pwm { @@ -1224,6 +1228,7 @@ interrupts-extended = <&exti 53 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc LPTIM5_K>; clock-names = "mux"; + wakeup-source; status = "disabled"; pwm { -- cgit v1.2.3-59-g8ed1b From 304b5691bfd06c94fedff34a08ffbce0bfcfa0cb Mon Sep 17 00:00:00 2001 From: Lionel Debieve Date: Thu, 5 Nov 2020 11:23:29 +0100 Subject: ARM: dts: stm32: enable HASH by default on stm32mp15 Enable HASH1 device for HASH accelerated support on stm32mp15 STMicroelectronics platforms. Signed-off-by: Lionel Debieve Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp157c-ed1.dts | 4 ++++ arch/arm/boot/dts/stm32mp15xx-dkx.dtsi | 4 ++++ 2 files changed, 8 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/stm32mp157c-ed1.dts b/arch/arm/boot/dts/stm32mp157c-ed1.dts index 2e77ccec3fc1..1a98a29b3283 100644 --- a/arch/arm/boot/dts/stm32mp157c-ed1.dts +++ b/arch/arm/boot/dts/stm32mp157c-ed1.dts @@ -136,6 +136,10 @@ contiguous-area = <&gpu_reserved>; }; +&hash1 { + status = "okay"; +}; + &i2c4 { pinctrl-names = "default", "sleep"; pinctrl-0 = <&i2c4_pins_a>; diff --git a/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi b/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi index 93398cfae97e..e92a18542306 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi @@ -151,6 +151,10 @@ contiguous-area = <&gpu_reserved>; }; +&hash1 { + status = "okay"; +}; + &i2c1 { pinctrl-names = "default", "sleep"; pinctrl-0 = <&i2c1_pins_a>; -- cgit v1.2.3-59-g8ed1b From ee0035b23327007c1455f47ab442e591f0eb8afe Mon Sep 17 00:00:00 2001 From: Nicolas Toromanoff Date: Thu, 5 Nov 2020 11:23:30 +0100 Subject: ARM: dts: stm32: enable CRC1 by default on stm32mp15 Enable CRC1 device for CRC-32 accelerated support on stm32mp15 STMicroelectronics platforms. Signed-off-by: Nicolas Toromanoff Signed-off-by: Lionel Debieve Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp157c-ed1.dts | 4 ++++ arch/arm/boot/dts/stm32mp15xx-dkx.dtsi | 4 ++++ 2 files changed, 8 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/stm32mp157c-ed1.dts b/arch/arm/boot/dts/stm32mp157c-ed1.dts index 1a98a29b3283..99796ffa43bf 100644 --- a/arch/arm/boot/dts/stm32mp157c-ed1.dts +++ b/arch/arm/boot/dts/stm32mp157c-ed1.dts @@ -115,6 +115,10 @@ }; }; +&crc1 { + status = "okay"; +}; + &dac { pinctrl-names = "default"; pinctrl-0 = <&dac_ch1_pins_a &dac_ch2_pins_a>; diff --git a/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi b/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi index e92a18542306..4e74e55a4f07 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi @@ -124,6 +124,10 @@ status = "okay"; }; +&crc1 { + status = "okay"; +}; + &dts { status = "okay"; }; -- cgit v1.2.3-59-g8ed1b From b6aa35c7393680ee0a1286ca3b3237fd106ef896 Mon Sep 17 00:00:00 2001 From: Lionel Debieve Date: Thu, 5 Nov 2020 11:23:31 +0100 Subject: ARM: dts: stm32: enable CRYP by default on stm32mp15 Enable CRYP1 device for cryp accelerated support on stm32mp157C-EV1/DK2 STMicroelectronics platforms. Signed-off-by: Nicolas Toromanoff Signed-off-by: Lionel Debieve Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp157c-dk2.dts | 4 ++++ arch/arm/boot/dts/stm32mp157c-ed1.dts | 4 ++++ 2 files changed, 8 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/stm32mp157c-dk2.dts b/arch/arm/boot/dts/stm32mp157c-dk2.dts index 045636555ddd..2bc92ef3aeb9 100644 --- a/arch/arm/boot/dts/stm32mp157c-dk2.dts +++ b/arch/arm/boot/dts/stm32mp157c-dk2.dts @@ -29,6 +29,10 @@ }; }; +&cryp1 { + status = "okay"; +}; + &dsi { status = "okay"; phy-dsi-supply = <®18>; diff --git a/arch/arm/boot/dts/stm32mp157c-ed1.dts b/arch/arm/boot/dts/stm32mp157c-ed1.dts index 99796ffa43bf..81a7d5849db4 100644 --- a/arch/arm/boot/dts/stm32mp157c-ed1.dts +++ b/arch/arm/boot/dts/stm32mp157c-ed1.dts @@ -119,6 +119,10 @@ status = "okay"; }; +&cryp1 { + status = "okay"; +}; + &dac { pinctrl-names = "default"; pinctrl-0 = <&dac_ch1_pins_a &dac_ch2_pins_a>; -- cgit v1.2.3-59-g8ed1b From 07e3454493e26fd5830c66a02eba705115748195 Mon Sep 17 00:00:00 2001 From: Hugues Fruchet Date: Wed, 4 Nov 2020 18:32:11 +0100 Subject: ARM: dts: stm32: set bus-type in DCMI endpoint for stm32mp157c-ev1 board Explicitly set bus-type to parallel mode in DCMI endpoint (bus-type=5). Signed-off-by: Hugues Fruchet Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp157c-ev1.dts | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/stm32mp157c-ev1.dts b/arch/arm/boot/dts/stm32mp157c-ev1.dts index a55e80ce2602..5c5b1ddf7bfd 100644 --- a/arch/arm/boot/dts/stm32mp157c-ev1.dts +++ b/arch/arm/boot/dts/stm32mp157c-ev1.dts @@ -90,6 +90,7 @@ port { dcmi_0: endpoint { remote-endpoint = <&ov5640_0>; + bus-type = <5>; bus-width = <8>; hsync-active = <0>; vsync-active = <0>; -- cgit v1.2.3-59-g8ed1b From 096b0243fae36282bb774421e4bcaeb8387e87e1 Mon Sep 17 00:00:00 2001 From: Hugues Fruchet Date: Wed, 4 Nov 2020 18:32:12 +0100 Subject: ARM: dts: stm32: set bus-type in DCMI endpoint for stm32429i-eval board Explicitly set bus-type to parallel mode in DCMI endpoint (bus-type=5). Signed-off-by: Hugues Fruchet Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32429i-eval.dts | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/stm32429i-eval.dts b/arch/arm/boot/dts/stm32429i-eval.dts index 67e7648de41e..7e10ae744c9d 100644 --- a/arch/arm/boot/dts/stm32429i-eval.dts +++ b/arch/arm/boot/dts/stm32429i-eval.dts @@ -188,6 +188,7 @@ port { dcmi_0: endpoint { remote-endpoint = <&ov2640_0>; + bus-type = <5>; bus-width = <8>; hsync-active = <0>; vsync-active = <0>; -- cgit v1.2.3-59-g8ed1b From dc37a51b258c13bf9dc8f34c5772cb45b93d35ae Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Thu, 22 Oct 2020 19:38:51 +0200 Subject: ARM: dts: stm32: reorder spi4 within stm32mp15-pinctrl Move spi4 at the right alphabetical place within stm32mp15-pinctrl Fixes: 4fe663890ac5 ("ARM: dts: stm32: Fix spi4 pins in stm32mp15-pinctrl") Signed-off-by: Patrick Delaunay Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp15-pinctrl.dtsi | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi index 9dbefa77b03e..e595e103bcbd 100644 --- a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi @@ -1646,6 +1646,20 @@ }; }; + spi4_pins_a: spi4-0 { + pins { + pinmux = , /* SPI4_SCK */ + ; /* SPI4_MOSI */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + pins2 { + pinmux = ; /* SPI4_MISO */ + bias-disable; + }; + }; + uart4_pins_a: uart4-0 { pins1 { pinmux = ; /* UART4_TX */ @@ -1781,20 +1795,6 @@ }; }; - spi4_pins_a: spi4-0 { - pins { - pinmux = , /* SPI4_SCK */ - ; /* SPI4_MOSI */ - bias-disable; - drive-push-pull; - slew-rate = <1>; - }; - pins2 { - pinmux = ; /* SPI4_MISO */ - bias-disable; - }; - }; - usart2_pins_a: usart2-0 { pins1 { pinmux = , /* USART2_TX */ -- cgit v1.2.3-59-g8ed1b From 83686162c0eb9d94dcab5d6a4e34fc545c331c63 Mon Sep 17 00:00:00 2001 From: Amelie Delaunay Date: Fri, 6 Nov 2020 17:58:04 +0100 Subject: ARM: dts: stm32: add STUSB1600 Type-C using I2C4 on stm32mp15xx-dkx This patch adds support for STUSB1600 USB Type-C port controller, used on I2C4 on stm32mp15xx-dkx. The default configuration on this board, on Type-C connector, is: - Dual Power Role (DRP), so set power-role to "dual"; - Vbus limited to 500mA, so set typec-power-opmode to "default" (it means 500mA in USB 2.0). typec-power-opmode is used to reconfigure the STUSB1600 advertising of current capability when its NVM is not in line with the board layout. On stm32mp15xx-dkx, Vbus power source of STUSB1600 is 5V_VIN. So power operation mode depends on the power supply used. To avoid any power issues, it is better to limit Vbus to 500mA on this board. ALERT# is the interrupt pin of STUSB1600. It needs an external pull-up, and signal is active low. USB OTG controller ID and Vbus signals are not connected on stm32mp15xx-dkx boards, so disconnection are not detected. Without DWC2 usb-role-switch: - if you unplug the USB cable from the Type-C port, you have to manually disconnect the USB gadget: echo disconnect > /sys/devices/platform/soc/49000000.usb-otg/udc/49000000.usb-otg/soft_connect - Then you can plug the USB cable again in the Type-C port, and manually reconnect the USB gadget: echo connect > /sys/devices/platform/soc/49000000.usb-otg/udc/49000000.usb-otg/soft_connect With DWC2 usb-role-switch, USB gadget is dynamically disconnected or connected. Signed-off-by: Amelie Delaunay Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp15-pinctrl.dtsi | 7 +++++++ arch/arm/boot/dts/stm32mp15xx-dkx.dtsi | 30 ++++++++++++++++++++++++++++++ 2 files changed, 37 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi index e595e103bcbd..20a59e8f7a33 100644 --- a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi @@ -1660,6 +1660,13 @@ }; }; + stusb1600_pins_a: stusb1600-0 { + pins { + pinmux = ; + bias-pull-up; + }; + }; + uart4_pins_a: uart4-0 { pins1 { pinmux = ; /* UART4_TX */ diff --git a/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi b/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi index 4e74e55a4f07..89c0e1ddc387 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi @@ -246,6 +246,30 @@ /delete-property/dmas; /delete-property/dma-names; + stusb1600@28 { + compatible = "st,stusb1600"; + reg = <0x28>; + interrupts = <11 IRQ_TYPE_EDGE_FALLING>; + interrupt-parent = <&gpioi>; + pinctrl-names = "default"; + pinctrl-0 = <&stusb1600_pins_a>; + status = "okay"; + vdd-supply = <&vin>; + + connector { + compatible = "usb-c-connector"; + label = "USB-C"; + power-role = "dual"; + typec-power-opmode = "default"; + + port { + con_usbotg_hs_ep: endpoint { + remote-endpoint = <&usbotg_hs_ep>; + }; + }; + }; + }; + pmic: stpmic@33 { compatible = "st,stpmic1"; reg = <0x33>; @@ -656,6 +680,12 @@ phy-names = "usb2-phy"; usb-role-switch; status = "okay"; + + port { + usbotg_hs_ep: endpoint { + remote-endpoint = <&con_usbotg_hs_ep>; + }; + }; }; &usbphyc { -- cgit v1.2.3-59-g8ed1b From fc082d2bb2f4860e065ae4d7f50d123bf4861d66 Mon Sep 17 00:00:00 2001 From: Amelie Delaunay Date: Tue, 10 Nov 2020 15:36:41 +0100 Subject: ARM: dts: stm32: fix mdma1 clients channel priority level on stm32mp151 Update mdma1 clients channel priority level following stm32-mdma bindings. Signed-off-by: Amelie Delaunay Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp151.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/stm32mp151.dtsi b/arch/arm/boot/dts/stm32mp151.dtsi index 6ffcf06dc0e8..2ace7d6ef364 100644 --- a/arch/arm/boot/dts/stm32mp151.dtsi +++ b/arch/arm/boot/dts/stm32mp151.dtsi @@ -1294,7 +1294,7 @@ interrupts = ; clocks = <&rcc HASH1>; resets = <&rcc HASH1_R>; - dmas = <&mdma1 31 0x10 0x1000A02 0x0 0x0>; + dmas = <&mdma1 31 0x2 0x1000A02 0x0 0x0>; dma-names = "in"; dma-maxburst = <2>; status = "disabled"; @@ -1358,8 +1358,8 @@ reg = <0x58003000 0x1000>, <0x70000000 0x10000000>; reg-names = "qspi", "qspi_mm"; interrupts = ; - dmas = <&mdma1 22 0x10 0x100002 0x0 0x0>, - <&mdma1 22 0x10 0x100008 0x0 0x0>; + dmas = <&mdma1 22 0x2 0x100002 0x0 0x0>, + <&mdma1 22 0x2 0x100008 0x0 0x0>; dma-names = "tx", "rx"; clocks = <&rcc QSPI_K>; resets = <&rcc QSPI_R>; -- cgit v1.2.3-59-g8ed1b From e3b37ca311bb72411f97d269ee4c6a6738a1e9d9 Mon Sep 17 00:00:00 2001 From: Amelie Delaunay Date: Tue, 10 Nov 2020 15:27:36 +0100 Subject: ARM: dts: stm32: fix dmamux reg property on stm32mp151 Reg property length should cover all DMAMUX_CxCR registers. DMAMUX_CxCR Address offset: 0x000 + 0x04 * x (x = 0 to 15), so latest offset is at 0x3c, so length should be 0x40. Signed-off-by: Amelie Delaunay Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp151.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/stm32mp151.dtsi b/arch/arm/boot/dts/stm32mp151.dtsi index 2ace7d6ef364..7aec02f263ed 100644 --- a/arch/arm/boot/dts/stm32mp151.dtsi +++ b/arch/arm/boot/dts/stm32mp151.dtsi @@ -1001,7 +1001,7 @@ dmamux1: dma-router@48002000 { compatible = "st,stm32h7-dmamux"; - reg = <0x48002000 0x1c>; + reg = <0x48002000 0x40>; #dma-cells = <3>; dma-requests = <128>; dma-masters = <&dma1 &dma2>; -- cgit v1.2.3-59-g8ed1b From 7e4bc946db78ec0311b486fadc929965fda85808 Mon Sep 17 00:00:00 2001 From: Amelie Delaunay Date: Tue, 10 Nov 2020 15:27:37 +0100 Subject: ARM: dts: stm32: fix dmamux reg property on stm32h743 Reg property length should cover all DMAMUX_CxCR registers. DMAMUX_CxCR Address offset: 0x000 + 0x04 * x (x = 0 to 15), so latest offset is at 0x3c, so length should be 0x40. Signed-off-by: Amelie Delaunay Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32h743.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/stm32h743.dtsi b/arch/arm/boot/dts/stm32h743.dtsi index 7febe19e780d..b083afd0ebd6 100644 --- a/arch/arm/boot/dts/stm32h743.dtsi +++ b/arch/arm/boot/dts/stm32h743.dtsi @@ -274,7 +274,7 @@ dmamux1: dma-router@40020800 { compatible = "st,stm32h7-dmamux"; - reg = <0x40020800 0x1c>; + reg = <0x40020800 0x40>; #dma-cells = <3>; dma-channels = <16>; dma-requests = <128>; -- cgit v1.2.3-59-g8ed1b From d27209f04d7f0e388281ba04d3cb97772c0eecff Mon Sep 17 00:00:00 2001 From: Amelie Delaunay Date: Tue, 10 Nov 2020 14:10:59 +0100 Subject: ARM: dts: stm32: adjust USB OTG gadget fifo sizes in stm32mp151 Defaut use case on stm32mp151 USB OTG is ethernet gadget, using EP1 bulk endpoint (MPS=512 bytes) and EP2 interrupt endpoint (MPS=16 bytes). This patch optimizes USB OTG FIFO sizes accordingly. Signed-off-by: Amelie Delaunay Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp151.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/stm32mp151.dtsi b/arch/arm/boot/dts/stm32mp151.dtsi index 7aec02f263ed..b95c46c82223 100644 --- a/arch/arm/boot/dts/stm32mp151.dtsi +++ b/arch/arm/boot/dts/stm32mp151.dtsi @@ -1070,9 +1070,9 @@ resets = <&rcc USBO_R>; reset-names = "dwc2"; interrupts = ; - g-rx-fifo-size = <256>; + g-rx-fifo-size = <512>; g-np-tx-fifo-size = <32>; - g-tx-fifo-size = <128 128 64 64 64 64 32 32>; + g-tx-fifo-size = <256 16 16 16 16 16 16 16>; dr_mode = "otg"; usb33d-supply = <&usb33>; status = "disabled"; -- cgit v1.2.3-59-g8ed1b From 4c903a946404dd96c45947c619c42d03020f9097 Mon Sep 17 00:00:00 2001 From: Arnaud Pouliquen Date: Wed, 14 Oct 2020 14:54:41 +0200 Subject: ARM: dts: stm32: update stm32mp151 for remote proc synchronization support Two backup registers are used to store the Cortex-M4 state and the resource table address. Declare the tamp node and add associated properties in m4_rproc node to allow Linux to attach to a firmware loaded by the first boot stages. Associated driver implementation is available in commit 9276536f455b3 ("remoteproc: stm32: Parse syscon that will manage M4 synchronisation"). Signed-off-by: Arnaud Pouliquen Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp151.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/stm32mp151.dtsi b/arch/arm/boot/dts/stm32mp151.dtsi index b95c46c82223..a333c633a112 100644 --- a/arch/arm/boot/dts/stm32mp151.dtsi +++ b/arch/arm/boot/dts/stm32mp151.dtsi @@ -1573,6 +1573,11 @@ status = "disabled"; }; + tamp: tamp@5c00a000 { + compatible = "st,stm32-tamp", "syscon"; + reg = <0x5c00a000 0x400>; + }; + /* * Break node order to solve dependency probe issue between * pinctrl and exti. @@ -1749,6 +1754,8 @@ st,syscfg-holdboot = <&rcc 0x10C 0x1>; st,syscfg-tz = <&rcc 0x000 0x1>; st,syscfg-pdds = <&pwr_mcu 0x0 0x1>; + st,syscfg-rsc-tbl = <&tamp 0x144 0xFFFFFFFF>; + st,syscfg-m4-state = <&tamp 0x148 0xFFFFFFFF>; status = "disabled"; }; }; -- cgit v1.2.3-59-g8ed1b From b19d3a55d4789a657c3c6b247ab5c9d8611a8a86 Mon Sep 17 00:00:00 2001 From: Ahmad Fatoum Date: Wed, 21 Oct 2020 12:28:56 +0200 Subject: ARM: dts: stm32: support child mfd cells for the stm32mp1 TAMP syscon The stm32mp1 TAMP peripheral has 32 backup registers that survive a warm reset. This makes them suitable for storing a reboot mode, which the vendor's kernel tree is already doing[0]. The actual syscon-reboot-mode child node can be added by a board.dts or fixed up by the bootloader. For the child node to be probed, the compatible needs to include simple-mfd. The binding now specifies this, so have the SoC dtsi adhere to it. [0]: https://github.com/STMicroelectronics/linux/commit/2e9bfc29dd Signed-off-by: Ahmad Fatoum Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp151.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/stm32mp151.dtsi b/arch/arm/boot/dts/stm32mp151.dtsi index a333c633a112..3c75abacb374 100644 --- a/arch/arm/boot/dts/stm32mp151.dtsi +++ b/arch/arm/boot/dts/stm32mp151.dtsi @@ -1574,7 +1574,7 @@ }; tamp: tamp@5c00a000 { - compatible = "st,stm32-tamp", "syscon"; + compatible = "st,stm32-tamp", "syscon", "simple-mfd"; reg = <0x5c00a000 0x400>; }; -- cgit v1.2.3-59-g8ed1b From ac68793f49de74c4046e760b6370f70c51d4aef9 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 3 Nov 2020 19:11:37 +0100 Subject: ARM: dts: stm32: Add DHCOM based PicoITX board Add DT for DH PicoITX unit, which is a bare-bones carrier board for the DHCOM. The board has ethernet port, USB, CAN, LEDs and a custom board-to-board expansion connector. Signed-off-by: Marek Vasut Cc: Alexandre Torgue Cc: Maxime Coquelin Cc: Patrice Chotard Cc: Patrick Delaunay Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/stm32mp157c-dhcom-picoitx.dts | 35 ++++++ arch/arm/boot/dts/stm32mp15xx-dhcom-picoitx.dtsi | 143 +++++++++++++++++++++++ 3 files changed, 179 insertions(+) create mode 100644 arch/arm/boot/dts/stm32mp157c-dhcom-picoitx.dts create mode 100644 arch/arm/boot/dts/stm32mp15xx-dhcom-picoitx.dtsi (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index ce66ffd5a1bb..c236c0f0adf6 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1066,6 +1066,7 @@ dtb-$(CONFIG_ARCH_STM32) += \ stm32mp157a-iot-box.dtb \ stm32mp157a-stinger96.dtb \ stm32mp157c-dhcom-pdk2.dtb \ + stm32mp157c-dhcom-picoitx.dtb \ stm32mp157c-dk2.dtb \ stm32mp157c-ed1.dtb \ stm32mp157c-ev1.dtb \ diff --git a/arch/arm/boot/dts/stm32mp157c-dhcom-picoitx.dts b/arch/arm/boot/dts/stm32mp157c-dhcom-picoitx.dts new file mode 100644 index 000000000000..cfb8f8a0c82d --- /dev/null +++ b/arch/arm/boot/dts/stm32mp157c-dhcom-picoitx.dts @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +/* + * Copyright (C) 2020 Marek Vasut + * + * DHCOM STM32MP1 variant: + * DHCM-STM32MP157C-C065-R102-F0819-SPI-E-CAN2-SD-RTC-T-DSI-I-01D2 + * DHCOM PCB number: 587-200 or newer + * PicoITX PCB number: 487-600 or newer + */ +/dts-v1/; + +#include "stm32mp157.dtsi" +#include "stm32mp15xc.dtsi" +#include "stm32mp15xx-dhcom-som.dtsi" +#include "stm32mp15xx-dhcom-picoitx.dtsi" + +/ { + model = "DH electronics STM32MP157C DHCOM PicoITX"; + compatible = "dh,stm32mp157c-dhcom-picoitx", "dh,stm32mp157c-dhcom-som", + "st,stm32mp157"; +}; + +&m_can1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&m_can1_pins_a>; + pinctrl-1 = <&m_can1_sleep_pins_a>; + status = "okay"; +}; + +&m_can2 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&m_can2_pins_a>; + pinctrl-1 = <&m_can2_sleep_pins_a>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcom-picoitx.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcom-picoitx.dtsi new file mode 100644 index 000000000000..356150d28c42 --- /dev/null +++ b/arch/arm/boot/dts/stm32mp15xx-dhcom-picoitx.dtsi @@ -0,0 +1,143 @@ +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +/* + * Copyright (C) 2020 Marek Vasut + */ + +#include +#include + +/ { + aliases { + serial0 = &uart4; + serial1 = &usart3; + serial2 = &uart8; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + led { + compatible = "gpio-leds"; + + led-0 { + label = "yellow:led"; + gpios = <&gpioi 3 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; +}; + +&adc { + status = "disabled"; +}; + +&dac { + status = "disabled"; +}; + +&gpioa { + /* + * NOTE: The USB Port on the PicoITX needs a PWR_EN signal to enable + * port power. This signal should be handled by USB power sequencing + * in order to turn on port power when USB bus is powered up, but so + * far there is no such functionality. + */ + usb-port-power { + gpio-hog; + gpios = <13 GPIO_ACTIVE_LOW>; + output-low; + line-name = "usb-port-power"; + }; +}; + +&gpioc { + gpio-line-names = "", "", "", "", + "", "", "In1", "", + "", "", "", "", + "", "", "", ""; +}; + +&gpiod { + gpio-line-names = "", "", "", "", + "", "", "", "", + "", "", "", "Out1", + "Out2", "", "", ""; +}; + +&gpiog { + gpio-line-names = "In2", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", ""; +}; + +&i2c2 { /* On board-to-board connector (optional) */ + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins_a>; + i2c-scl-rising-time-ns = <185>; + i2c-scl-falling-time-ns = <20>; + status = "okay"; + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; +}; + +&i2c5 { /* On board-to-board connector */ + pinctrl-names = "default"; + pinctrl-0 = <&i2c5_pins_a>; + i2c-scl-rising-time-ns = <185>; + i2c-scl-falling-time-ns = <20>; + status = "okay"; + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; +}; + +&usart3 { + pinctrl-names = "default"; + pinctrl-0 = <&usart3_pins_a>; + status = "okay"; +}; + +&uart8 { + pinctrl-names = "default"; + pinctrl-0 = <&uart8_pins_a &uart8_rtscts_pins_a>; + status = "okay"; +}; + +&usbh_ehci { + phys = <&usbphyc_port0>; + status = "okay"; +}; + +&usbh_ohci { + phys = <&usbphyc_port0>; + status = "okay"; +}; + +&usbotg_hs { + dr_mode = "otg"; + pinctrl-0 = <&usbotg_hs_pins_a>; + pinctrl-names = "default"; + phy-names = "usb2-phy"; + phys = <&usbphyc_port1 0>; + vbus-supply = <&vbus_otg>; + status = "okay"; +}; + +&usbphyc { + status = "okay"; +}; + +&usbphyc_port0 { + phy-supply = <&vdd_usb>; + vdda1v1-supply = <®11>; + vdda1v8-supply = <®18>; +}; + +&usbphyc_port1 { + phy-supply = <&vdd_usb>; + vdda1v1-supply = <®11>; + vdda1v8-supply = <®18>; +}; -- cgit v1.2.3-59-g8ed1b From 6660e2445523a57410de008a9b137d2c0a66e94a Mon Sep 17 00:00:00 2001 From: Ahmad Fatoum Date: Tue, 10 Nov 2020 11:25:51 +0100 Subject: ARM: dts: stm32: lxa-mc1: add OSD32MP15x to list of compatibles Earlier commit modified the binding, so the SiP is to be specified as well. Adjust the device tree accordingly. Signed-off-by: Ahmad Fatoum Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp157c-lxa-mc1.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/stm32mp157c-lxa-mc1.dts b/arch/arm/boot/dts/stm32mp157c-lxa-mc1.dts index 1e5333fd437f..cda8e871f999 100644 --- a/arch/arm/boot/dts/stm32mp157c-lxa-mc1.dts +++ b/arch/arm/boot/dts/stm32mp157c-lxa-mc1.dts @@ -15,7 +15,7 @@ / { model = "Linux Automation MC-1 board"; - compatible = "lxa,stm32mp157c-mc1", "st,stm32mp157"; + compatible = "lxa,stm32mp157c-mc1", "oct,stm32mp15xx-osd32", "st,stm32mp157"; aliases { ethernet0 = ðernet0; -- cgit v1.2.3-59-g8ed1b From 46957c06d35bb0caf07cc032600f6a3391eb47d1 Mon Sep 17 00:00:00 2001 From: Fabrice Gasnier Date: Fri, 16 Oct 2020 10:00:29 +0200 Subject: ARM: multi_v7_defconfig: enable counter subsystem and stm32 counter drivers This enables the counter subsystem and drivers for the stm32 timer and LP timer. Signed-off-by: Fabrice Gasnier Signed-off-by: Alexandre Torgue --- arch/arm/configs/multi_v7_defconfig | 3 +++ 1 file changed, 3 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig index e731cdf7c88c..54b54107eb29 100644 --- a/arch/arm/configs/multi_v7_defconfig +++ b/arch/arm/configs/multi_v7_defconfig @@ -1095,6 +1095,9 @@ CONFIG_FSI_MASTER_ASPEED=m CONFIG_FSI_SCOM=m CONFIG_FSI_SBEFIFO=m CONFIG_FSI_OCC=m +CONFIG_COUNTER=m +CONFIG_STM32_TIMER_CNT=m +CONFIG_STM32_LPTIMER_CNT=m CONFIG_EXT4_FS=y CONFIG_AUTOFS4_FS=y CONFIG_MSDOS_FS=y -- cgit v1.2.3-59-g8ed1b From 8e4eeb83a692a4d3be60854e9cf7a045e440db78 Mon Sep 17 00:00:00 2001 From: Lionel Debieve Date: Thu, 5 Nov 2020 10:47:30 +0100 Subject: ARM: multi_v7_defconfig: add STM32 crypto support Enable crypto controllers enabling following flags as module: CONFIG_CRYPTO_DEV_STM32_CRC CONFIG_CRYPTO_DEV_STM32_HASH CONFIG_CRYPTO_DEV_STM32_CRYP Signed-off-by: Lionel Debieve Signed-off-by: Alexandre Torgue --- arch/arm/configs/multi_v7_defconfig | 3 +++ 1 file changed, 3 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig index 54b54107eb29..17ff69674c6e 100644 --- a/arch/arm/configs/multi_v7_defconfig +++ b/arch/arm/configs/multi_v7_defconfig @@ -1135,6 +1135,9 @@ CONFIG_CRYPTO_DEV_ATMEL_AES=m CONFIG_CRYPTO_DEV_ATMEL_TDES=m CONFIG_CRYPTO_DEV_ATMEL_SHA=m CONFIG_CRYPTO_DEV_ROCKCHIP=m +CONFIG_CRYPTO_DEV_STM32_CRC=m +CONFIG_CRYPTO_DEV_STM32_HASH=m +CONFIG_CRYPTO_DEV_STM32_CRYP=m CONFIG_CMA_SIZE_MBYTES=64 CONFIG_PRINTK_TIME=y CONFIG_MAGIC_SYSRQ=y -- cgit v1.2.3-59-g8ed1b From 89391783174e12d621d82bc41b4b017363bf2827 Mon Sep 17 00:00:00 2001 From: Amelie Delaunay Date: Fri, 6 Nov 2020 17:58:05 +0100 Subject: ARM: multi_v7_defconfig: enable STUSB160X Type-C port controller support Enable support for the STMicroelectronics STUSB160X USB Type-C port controller driver by turning on CONFIG_TYPEC and CONFIG_TYPEC_STUSB160X as modules. Signed-off-by: Amelie Delaunay Signed-off-by: Alexandre Torgue --- arch/arm/configs/multi_v7_defconfig | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig index 17ff69674c6e..1fff2591e434 100644 --- a/arch/arm/configs/multi_v7_defconfig +++ b/arch/arm/configs/multi_v7_defconfig @@ -828,6 +828,8 @@ CONFIG_USB_CONFIGFS_F_HID=y CONFIG_USB_CONFIGFS_F_UVC=y CONFIG_USB_CONFIGFS_F_PRINTER=y CONFIG_USB_ETH=m +CONFIG_TYPEC=m +CONFIG_TYPEC_STUSB160X=m CONFIG_MMC=y CONFIG_MMC_BLOCK_MINORS=16 CONFIG_MMC_ARMMMCI=y -- cgit v1.2.3-59-g8ed1b From 1c6b157ba6bdfd309ce53819116601da230a1431 Mon Sep 17 00:00:00 2001 From: Olivier Moysan Date: Fri, 20 Nov 2020 10:15:05 +0100 Subject: ARM: multi_v7_defconfig: enable STM32 spdifrx support Add STM32 SPDIFRX support by enabling CONFIG_SND_SOC_STM32_SPDIFRX as module. Signed-off-by: Olivier Moysan Reviewed-by: Krzysztof Kozlowski Signed-off-by: Alexandre Torgue --- arch/arm/configs/multi_v7_defconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm') diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig index 1fff2591e434..b30a3bc6762b 100644 --- a/arch/arm/configs/multi_v7_defconfig +++ b/arch/arm/configs/multi_v7_defconfig @@ -742,6 +742,7 @@ CONFIG_SND_SOC_RCAR=m CONFIG_SND_SOC_STI=m CONFIG_SND_SOC_STM32_SAI=m CONFIG_SND_SOC_STM32_I2S=m +CONFIG_SND_SOC_STM32_SPDIFRX=m CONFIG_SND_SUN4I_CODEC=m CONFIG_SND_SOC_TEGRA=m CONFIG_SND_SOC_TEGRA20_I2S=m -- cgit v1.2.3-59-g8ed1b From 01d13862543d3a017270ad84170579848472589f Mon Sep 17 00:00:00 2001 From: Olivier Moysan Date: Fri, 20 Nov 2020 10:15:06 +0100 Subject: ARM: multi_v7_defconfig: enable STM32 dfsdm audio support Add STM32 DFSDM audio support by enabling CONFIG_SND_SOC_STM32_DFSDM as module. Signed-off-by: Olivier Moysan Reviewed-by: Krzysztof Kozlowski Signed-off-by: Alexandre Torgue --- arch/arm/configs/multi_v7_defconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm') diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig index b30a3bc6762b..083d5f4450f4 100644 --- a/arch/arm/configs/multi_v7_defconfig +++ b/arch/arm/configs/multi_v7_defconfig @@ -743,6 +743,7 @@ CONFIG_SND_SOC_STI=m CONFIG_SND_SOC_STM32_SAI=m CONFIG_SND_SOC_STM32_I2S=m CONFIG_SND_SOC_STM32_SPDIFRX=m +CONFIG_SND_SOC_STM32_DFSDM=m CONFIG_SND_SUN4I_CODEC=m CONFIG_SND_SOC_TEGRA=m CONFIG_SND_SOC_TEGRA20_I2S=m -- cgit v1.2.3-59-g8ed1b From da8d46992e672ec7300b5b6857d0a4eebf0727ac Mon Sep 17 00:00:00 2001 From: Iskren Chernev Date: Thu, 26 Nov 2020 16:11:43 +0200 Subject: ARM: dts: qcom: msm8974-klte: Add fuel gauge The Samsung Galaxy S5 uses a maxim17048 fuelgauge. The maxim,rcomp value is taken from downstream kernel. Model data and temperature-based compensation are not yet supported in the mainline driver, but the readings seem fine nevertheless. Signed-off-by: Iskren Chernev Link: https://lore.kernel.org/r/20201126141144.1763779-1-iskren.chernev@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts | 39 +++++++++++++++++++++++++ 1 file changed, 39 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts b/arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts index b0899107f3ce..97352de91314 100644 --- a/arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts +++ b/arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts @@ -406,6 +406,16 @@ }; }; + i2c12_pins: i2c12 { + mux { + pins = "gpio87", "gpio88"; + function = "blsp_i2c12"; + + drive-strength = <2>; + bias-disable; + }; + }; + i2c_touchkey_pins: i2c-touchkey { mux { pins = "gpio95", "gpio96"; @@ -666,6 +676,27 @@ }; }; }; + + i2c@f9968000 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&i2c12_pins>; + + fuelgauge@36 { + compatible = "maxim,max17048"; + reg = <0x36>; + + maxim,double-soc; + maxim,rcomp = /bits/ 8 <0x56>; + + interrupt-parent = <&pma8084_gpios>; + interrupts = <21 IRQ_TYPE_EDGE_FALLING>; + + pinctrl-names = "default"; + pinctrl-0 = <&fuelgauge_pin>; + }; + }; }; &spmi_bus { @@ -703,6 +734,14 @@ power-source = ; qcom,drive-strength = ; }; + + fuelgauge_pin: fuelgauge-int-pin { + pins = "gpio21"; + function = "normal"; + bias-disable; + input-enable; + power-source = ; + }; }; }; }; -- cgit v1.2.3-59-g8ed1b From 45dfa741df8607ee4a45455c194ce654badb2478 Mon Sep 17 00:00:00 2001 From: Iskren Chernev Date: Thu, 26 Nov 2020 16:11:44 +0200 Subject: ARM: dts: qcom: msm8974-lge-nexus5: Add fuel gauge MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The LG Nexus 5 uses a maxim17048 fuelgauge. The maxim,rcomp value is taken from downstream dt. Temperature-based compensation is not yet supported in the mainline driver, but the readings seem fine nevertheless. Signed-off-by: Iskren Chernev Tested-by: Nícolas F. R. A. Prado Link: https://lore.kernel.org/r/20201126141144.1763779-2-iskren.chernev@gmail.com Signed-off-by: Bjorn Andersson --- .../dts/qcom-msm8974-lge-nexus5-hammerhead.dts | 25 ++++++++++++++++++++++ 1 file changed, 25 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts b/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts index 32b474bfeec3..e769f638f205 100644 --- a/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts +++ b/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts @@ -566,6 +566,22 @@ usb_otg_vbus: usb-otg-vbus { }; }; + + fuelgauge: max17048@36 { + compatible = "maxim,max17048"; + reg = <0x36>; + + maxim,double-soc; + maxim,rcomp = /bits/ 8 <0x4d>; + + interrupt-parent = <&msmgpio>; + interrupts = <9 IRQ_TYPE_EDGE_FALLING>; + + pinctrl-names = "default"; + pinctrl-0 = <&fuelgauge_pin>; + + maxim,alert-low-soc-level = <2>; + }; }; i2c@f9924000 { @@ -706,6 +722,15 @@ power-source = ; }; + fuelgauge_pin: fuelgauge-int { + pins = "gpio9"; + function = "normal"; + + bias-disable; + input-enable; + power-source = ; + }; + wlan_sleep_clk_pin: wl-sleep-clk { pins = "gpio16"; function = "func2"; -- cgit v1.2.3-59-g8ed1b From d7195ac5c9c5356b7cda4668fb64fc537c6be833 Mon Sep 17 00:00:00 2001 From: Peter Geis Date: Sun, 4 Oct 2020 13:31:12 +0000 Subject: ARM: tegra: Add device-tree for Ouya The Ouya was the sole device produced by Ouya Inc in 2013. It was a game console originally running Android 5 on top of Linux 3.1.10. This patch adds the device tree supporting the Ouya. It has been tested on the original variant with Samsung ram. Signed-off-by: Peter Geis Reviewed-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- arch/arm/boot/dts/Makefile | 3 +- arch/arm/boot/dts/tegra30-ouya.dts | 4511 ++++++++++++++++++++++++++++++++++++ 2 files changed, 4513 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/tegra30-ouya.dts (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index ce66ffd5a1bb..10d7da888ebb 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1241,7 +1241,8 @@ dtb-$(CONFIG_ARCH_TEGRA_3x_SOC) += \ tegra30-beaver.dtb \ tegra30-cardhu-a02.dtb \ tegra30-cardhu-a04.dtb \ - tegra30-colibri-eval-v3.dtb + tegra30-colibri-eval-v3.dtb \ + tegra30-ouya.dtb dtb-$(CONFIG_ARCH_TEGRA_114_SOC) += \ tegra114-dalmore.dtb \ tegra114-roth.dtb \ diff --git a/arch/arm/boot/dts/tegra30-ouya.dts b/arch/arm/boot/dts/tegra30-ouya.dts new file mode 100644 index 000000000000..a5f16ad6c8f4 --- /dev/null +++ b/arch/arm/boot/dts/tegra30-ouya.dts @@ -0,0 +1,4511 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include +#include +#include + +#include "tegra30.dtsi" +#include "tegra30-cpu-opp.dtsi" +#include "tegra30-cpu-opp-microvolt.dtsi" + +/ { + model = "Ouya Game Console"; + compatible = "ouya,ouya", "nvidia,tegra30"; + + aliases { + mmc0 = &sdmmc4; /* eMMC */ + mmc1 = &sdmmc3; /* WiFi */ + rtc0 = &pmic; + rtc1 = "/rtc@7000e000"; + serial0 = &uartd; /* Debug Port */ + serial1 = &uartc; /* Bluetooth */ + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@80000000 { + reg = <0x80000000 0x40000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + linux,cma@80000000 { + compatible = "shared-dma-pool"; + alloc-ranges = <0x80000000 0x30000000>; + size = <0x10000000>; /* 256MiB */ + linux,cma-default; + reusable; + }; + + ramoops@bfdf0000 { + compatible = "ramoops"; + reg = <0xbfdf0000 0x10000>; /* 64kB */ + console-size = <0x8000>; /* 32kB */ + record-size = <0x400>; /* 1kB */ + ecc-size = <16>; + }; + + trustzone@bfe00000 { + reg = <0xbfe00000 0x200000>; + no-map; + }; + }; + + host1x@50000000 { + hdmi@54280000 { + status = "okay"; + vdd-supply = <&vdd_vid_reg>; + pll-supply = <&ldo7_reg>; + hdmi-supply = <&sys_3v3_reg>; + nvidia,ddc-i2c-bus = <&hdmi_ddc>; + nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; + }; + }; + + gpio: gpio@6000d000 { + gpio-ranges = <&pinmux 0 0 248>; + #reset-cells = <1>; + }; + + pinmux@70000868 { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + state_default: pinmux { + /* located at $state_default below */ + }; + }; + + uartc: serial@70006200 { + status = "okay"; + compatible = "nvidia,tegra30-hsuart"; + + nvidia,adjust-baud-rates = <0 9600 100>, + <9600 115200 200>, + <1000000 4000000 136>; + + /* Azurewave AW-NH660 BCM4330B1 */ + bluetooth { + compatible = "brcm,bcm4330-bt"; + + max-speed = <4000000>; + + clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>; + clock-names = "txco"; + + vbat-supply = <&sys_3v3_reg>; + vddio-supply = <&vdd_1v8>; + + shutdown-gpios = <&gpio TEGRA_GPIO(U, 0) GPIO_ACTIVE_HIGH>; + device-wakeup-gpios = <&gpio TEGRA_GPIO(U, 1) GPIO_ACTIVE_HIGH>; + host-wakeup-gpios = <&gpio TEGRA_GPIO(U, 6) GPIO_ACTIVE_HIGH>; + }; + }; + + uartd: serial@70006300 { + status = "okay"; + }; + + hdmi_ddc: i2c@7000c700 { + status = "okay"; + clock-frequency = <100000>; + }; + + i2c@7000d000 { + status = "okay"; + clock-frequency = <400000>; + + cpu_temp: nct1008@4c { + compatible = "onnn,nct1008"; + reg = <0x4c>; + vcc-supply = <&sys_3v3_reg>; + #thermal-sensor-cells = <1>; +/* + * The interrupt is bugged, once triggered it never clears. + * interrupt-parent = <&gpio>; + * interrupts = ; + */ + }; + + pmic: pmic@2d { + compatible = "ti,tps65911"; + reg = <0x2d>; + + interrupts = ; + #interrupt-cells = <2>; + interrupt-controller; + + ti,en-gpio-sleep = <0 1 1 1 1 1 0 0 1>; + ti,system-power-controller; + ti,sleep-keep-ck32k; + ti,sleep-enable; + + #gpio-cells = <2>; + gpio-controller; + + vcc1-supply = <&vdd_5v0_reg>; + vcc2-supply = <&vdd_5v0_reg>; + vcc3-supply = <&vdd_1v8>; + vcc4-supply = <&vdd_5v0_reg>; + vcc5-supply = <&vdd_5v0_reg>; + vcc6-supply = <&vdd2_reg>; + vcc7-supply = <&vdd_5v0_reg>; + vccio-supply = <&vdd_5v0_reg>; + + regulators { + vdd1_reg: vdd1 { + regulator-name = "vddio_ddr_1v2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + vdd2_reg: vdd2 { + regulator-name = "vdd_1v5_gen"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + }; + + vdd_cpu: vddctrl { + regulator-name = "vdd_cpu,vdd_sys"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1270000>; + regulator-coupled-with = <&vdd_core>; + regulator-coupled-max-spread = <300000>; + regulator-max-step-microvolt = <100000>; + regulator-always-on; + + nvidia,tegra-cpu-regulator; + }; + + vdd_1v8: vio { + regulator-name = "vdd_1v8_gen"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo1_reg: ldo1 { + regulator-name = "vdd_pexa,vdd_pexb"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + regulator-always-on; + }; + + ldo2_reg: ldo2 { + regulator-name = "vdd_sata,avdd_plle"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + regulator-always-on; + }; + + /* LDO3 is not connected to anything */ + + ldo4_reg: ldo4 { + regulator-name = "vdd_rtc"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + ldo5_reg: ldo5 { + regulator-name = "vddio_sdmmc,avdd_vdac"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + ldo6_reg: ldo6 { + regulator-name = "avdd_dsi_csi,pwrdet_mipi"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + ldo7_reg: ldo7 { + regulator-name = "vdd_pllm,x,u,a_p_c_s"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + ldo8_reg: ldo8 { + regulator-name = "vdd_ddr_hs"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + }; + }; + + vdd_core: tps62361@60 { + compatible = "ti,tps62361"; + reg = <0x60>; + + regulator-name = "vdd_core"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1350000>; + regulator-coupled-with = <&vdd_cpu>; + regulator-coupled-max-spread = <300000>; + regulator-max-step-microvolt = <100000>; + regulator-boot-on; + regulator-always-on; + ti,vsel0-state-high; + ti,vsel1-state-high; + ti,enable-vout-discharge; + + nvidia,tegra-core-regulator; + }; + }; + + pmc@7000e400 { + status = "okay"; + nvidia,invert-interrupt; + nvidia,suspend-mode = <1>; + nvidia,cpu-pwr-good-time = <2000>; + nvidia,cpu-pwr-off-time = <200>; + nvidia,core-pwr-good-time = <3845 3845>; + nvidia,core-pwr-off-time = <458>; + nvidia,core-power-req-active-high; + nvidia,sys-clock-req-active-high; + }; + + mc_timings: memory-controller@7000f000 { + /* timings located at &mc_timings below */ + }; + + emc_timings: memory-controller@7000f400 { + /* timings located at &emc_timings below */ + }; + + hda@70030000 { + status = "okay"; + }; + + wifi_pwrseq: wifi_pwrseq { + compatible = "mmc-pwrseq-simple"; + + clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>; + clock-names = "ext_clock"; + + reset-gpios = <&gpio TEGRA_GPIO(D, 3) GPIO_ACTIVE_LOW>; + post-power-on-delay-ms = <300>; + power-off-delay-us = <300>; + }; + + sdmmc3: mmc@78000400 { + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + + assigned-clocks = <&tegra_car TEGRA30_CLK_SDMMC3>; + assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_C>; + assigned-clock-rates = <50000000>; + + max-frequency = <50000000>; + keep-power-in-suspend; + + bus-width = <4>; + non-removable; + + mmc-pwrseq = <&wifi_pwrseq>; + vmmc-supply = <&sdmmc_3v3_reg>; + vqmmc-supply = <&vdd_1v8>; + + /* Azurewave AW-NH660 BCM4330 */ + brcmf: wifi@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + interrupt-parent = <&gpio>; + interrupts = ; + interrupt-names = "host-wake"; + }; + }; + + sdmmc4: mmc@78000600 { + status = "okay"; + + keep-power-in-suspend; + bus-width = <8>; + non-removable; + vmmc-supply = <&sys_3v3_reg>; + vqmmc-supply = <&vdd_1v8>; + nvidia,default-tap = <0x0F>; + max-frequency = <25500000>; + }; + + usb@7d000000 { + compatible = "nvidia,tegra30-udc"; + status = "okay"; + }; + + usb-phy@7d000000 { + status = "okay"; + dr_mode = "peripheral"; + }; + + usb@7d004000 { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + smsc@2 { /* SMSC 10/100T Ethernet Controller */ + compatible = "usb424,9e00"; + reg = <2>; + local-mac-address = [00 11 22 33 44 55]; + }; + }; + + usb-phy@7d004000 { + vbus-supply = <&vdd_smsc>; + status = "okay"; + }; + + usb@7d008000 { + status = "okay"; + }; + + usb-phy@7d008000 { + vbus-supply = <&usb3_vbus_reg>; + status = "okay"; + }; + + /* PMIC has a built-in 32KHz oscillator which is used by PMC */ + clk32k_in: clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "pmic-oscillator"; + }; + + cpus { + cpu0: cpu@0 { + operating-points-v2 = <&cpu0_opp_table>; + cpu-supply = <&vdd_cpu>; + #cooling-cells = <2>; + }; + cpu@1 { + operating-points-v2 = <&cpu0_opp_table>; + cpu-supply = <&vdd_cpu>; + }; + + cpu@2 { + operating-points-v2 = <&cpu0_opp_table>; + cpu-supply = <&vdd_cpu>; + }; + + cpu@3 { + operating-points-v2 = <&cpu0_opp_table>; + cpu-supply = <&vdd_cpu>; + }; + }; + + firmware { + trusted-foundations { + compatible = "tlm,trusted-foundations"; + tlm,version-major = <0x0>; + tlm,version-minor = <0x0>; + }; + }; + + fan: gpio_fan { + compatible = "gpio-fan"; + gpios = <&gpio TEGRA_GPIO(J, 2) GPIO_ACTIVE_HIGH>; + gpio-fan,speed-map = <0 0 + 4500 1>; + #cooling-cells = <2>; + }; + + thermal-zones { + cpu_thermal: cpu-thermal { + polling-delay = <5000>; + polling-delay-passive = <5000>; + + thermal-sensors = <&cpu_temp 1>; + + trips { + cpu_alert0: cpu-alert0 { + temperature = <50000>; + hysteresis = <10000>; + type = "active"; + }; + cpu_alert1: cpu-alert1 { + temperature = <70000>; + hysteresis = <5000>; + type = "passive"; + }; + cpu_crit: cpu-crit { + temperature = <90000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu_alert0>; + cooling-device = <&fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + map1 { + trip = <&cpu_alert1>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + }; + + vdd_12v_in: vdd_12v_in { + compatible = "regulator-fixed"; + regulator-name = "vdd_12v_in"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + regulator-always-on; + }; + + sdmmc_3v3_reg: sdmmc_3v3_reg { + compatible = "regulator-fixed"; + regulator-name = "sdmmc_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + regulator-always-on; + gpio = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH>; + vin-supply = <&sys_3v3_reg>; + }; + + vdd_fuse_3v3_reg: vdd_fuse_3v3_reg { + compatible = "regulator-fixed"; + regulator-name = "vdd_fuse_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(L, 6) GPIO_ACTIVE_HIGH>; + vin-supply = <&sys_3v3_reg>; + regulator-always-on; + }; + + vdd_vid_reg: vdd_vid_reg { + compatible = "regulator-fixed"; + regulator-name = "vddio_vid"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(T, 0) GPIO_ACTIVE_HIGH>; + vin-supply = <&vdd_5v0_reg>; + regulator-boot-on; + }; + + ddr_reg: ddr_reg { + compatible = "regulator-fixed"; + regulator-name = "vdd_ddr"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + enable-active-high; + gpio = <&pmic 7 GPIO_ACTIVE_HIGH>; + regulator-boot-on; + vin-supply = <&vdd_12v_in>; + }; + + sys_3v3_reg: sys_3v3_reg { + compatible = "regulator-fixed"; + regulator-name = "sys_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&pmic 6 GPIO_ACTIVE_HIGH>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vdd_12v_in>; + }; + + vdd_5v0_reg: vdd_5v0_reg { + compatible = "regulator-fixed"; + regulator-name = "vdd_5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&pmic 0 GPIO_ACTIVE_HIGH>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vdd_12v_in>; + }; + + vdd_smsc: vdd_smsc { + compatible = "regulator-fixed"; + regulator-name = "vdd_smsc"; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(DD, 5) GPIO_ACTIVE_HIGH>; + }; + + usb3_vbus_reg: usb3_vbus_reg { + compatible = "regulator-fixed"; + regulator-name = "usb3_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(DD, 4) GPIO_ACTIVE_HIGH>; + vin-supply = <&vdd_5v0_reg>; + }; + + gpio-keys { + compatible = "gpio-keys"; + + power { + gpios = <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_LOW>; + debounce-interval = <10>; + linux,code = ; + wakeup-event-action = ; + wakeup-source; + }; + }; + + + leds { + compatible = "gpio-leds"; + + led-power { + label = "power-led"; + gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>; + default-state = "on"; + linux,default-trigger = "heartbeat"; + retain-state-suspended; + }; + }; +}; +&mc_timings { + emc-timings-0 { + nvidia,ram-code = <0>; /* Samsung RAM */ + timing-25500000 { + clock-frequency = <25500000>; + nvidia,emem-configuration = < + 0x00030003 /* MC_EMEM_ARB_CFG */ + 0xc0000010 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000001 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */ + 0x75830303 /* MC_EMEM_ARB_MISC0 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + timing-51000000 { + clock-frequency = <51000000>; + nvidia,emem-configuration = < + 0x00010003 /* MC_EMEM_ARB_CFG */ + 0xc0000010 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000001 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */ + 0x74630303 /* MC_EMEM_ARB_MISC0 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + timing-102000000 { + clock-frequency = <102000000>; + nvidia,emem-configuration = < + 0x00000003 /* MC_EMEM_ARB_CFG */ + 0xc0000018 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0503 /* MC_EMEM_ARB_DA_COVERS */ + 0x73c30504 /* MC_EMEM_ARB_MISC0 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + timing-204000000 { + clock-frequency = <204000000>; + nvidia,emem-configuration = < + 0x00000006 /* MC_EMEM_ARB_CFG */ + 0xc0000025 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000005 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000004 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0505 /* MC_EMEM_ARB_DA_COVERS */ + 0x73840a06 /* MC_EMEM_ARB_MISC0 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + timing-400000000 { + clock-frequency = <400000000>; + nvidia,emem-configuration = < + 0x0000000c /* MC_EMEM_ARB_CFG */ + 0xc0000048 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000009 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000005 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000007 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06030202 /* MC_EMEM_ARB_DA_TURNS */ + 0x000d0709 /* MC_EMEM_ARB_DA_COVERS */ + 0x7086120a /* MC_EMEM_ARB_MISC0 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + timing-800000000 { + clock-frequency = <800000000>; + nvidia,emem-configuration = < + 0x00000018 /* MC_EMEM_ARB_CFG */ + 0xc0000090 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000004 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000005 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000013 /* MC_EMEM_ARB_TIMING_RC */ + 0x0000000c /* MC_EMEM_ARB_TIMING_RAS */ + 0x0000000f /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x0000000c /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000008 /* MC_EMEM_ARB_TIMING_W2R */ + 0x08040202 /* MC_EMEM_ARB_DA_TURNS */ + 0x00160d13 /* MC_EMEM_ARB_DA_COVERS */ + 0x712c2414 /* MC_EMEM_ARB_MISC0 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + }; + emc-timings-1 { + nvidia,ram-code = <1>; /* Hynix M RAM */ + timing-25500000 { + clock-frequency = <25500000>; + nvidia,emem-configuration = < + 0x00030003 /* MC_EMEM_ARB_CFG */ + 0xc0000010 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000001 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */ + 0x75830303 /* MC_EMEM_ARB_MISC0 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + timing-51000000 { + clock-frequency = <51000000>; + nvidia,emem-configuration = < + 0x00010003 /* MC_EMEM_ARB_CFG */ + 0xc0000010 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000001 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */ + 0x74630303 /* MC_EMEM_ARB_MISC0 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + timing-102000000 { + clock-frequency = <102000000>; + nvidia,emem-configuration = < + 0x00000003 /* MC_EMEM_ARB_CFG */ + 0xc0000018 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0503 /* MC_EMEM_ARB_DA_COVERS */ + 0x73c30504 /* MC_EMEM_ARB_MISC0 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + timing-204000000 { + clock-frequency = <204000000>; + nvidia,emem-configuration = < + 0x00000006 /* MC_EMEM_ARB_CFG */ + 0xc0000025 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000005 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000004 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0505 /* MC_EMEM_ARB_DA_COVERS */ + 0x73840a06 /* MC_EMEM_ARB_MISC0 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + timing-400000000 { + clock-frequency = <400000000>; + nvidia,emem-configuration = < + 0x0000000c /* MC_EMEM_ARB_CFG */ + 0xc0000048 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000009 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000005 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000007 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06030202 /* MC_EMEM_ARB_DA_TURNS */ + 0x000d0709 /* MC_EMEM_ARB_DA_COVERS */ + 0x7086120a /* MC_EMEM_ARB_MISC0 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + timing-800000000 { + clock-frequency = <800000000>; + nvidia,emem-configuration = < + 0x00000018 /* MC_EMEM_ARB_CFG */ + 0xc0000090 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000004 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000005 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000013 /* MC_EMEM_ARB_TIMING_RC */ + 0x0000000c /* MC_EMEM_ARB_TIMING_RAS */ + 0x0000000f /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x0000000c /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000008 /* MC_EMEM_ARB_TIMING_W2R */ + 0x08040202 /* MC_EMEM_ARB_DA_TURNS */ + 0x00160d13 /* MC_EMEM_ARB_DA_COVERS */ + 0x712c2414 /* MC_EMEM_ARB_MISC0 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + }; + emc-timings-2 { + nvidia,ram-code = <2>; /* Hynix A RAM */ + timing-25500000 { + clock-frequency = <25500000>; + nvidia,emem-configuration = < + 0x00030003 /* MC_EMEM_ARB_CFG */ + 0xc0000010 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000001 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */ + 0x75e30303 /* MC_EMEM_ARB_MISC0 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + timing-51000000 { + clock-frequency = <51000000>; + nvidia,emem-configuration = < + 0x00010003 /* MC_EMEM_ARB_CFG */ + 0xc0000010 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000001 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */ + 0x74e30303 /* MC_EMEM_ARB_MISC0 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + timing-102000000 { + clock-frequency = <102000000>; + nvidia,emem-configuration = < + 0x00000003 /* MC_EMEM_ARB_CFG */ + 0xc0000018 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0503 /* MC_EMEM_ARB_DA_COVERS */ + 0x74430504 /* MC_EMEM_ARB_MISC0 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + timing-204000000 { + clock-frequency = <204000000>; + nvidia,emem-configuration = < + 0x00000006 /* MC_EMEM_ARB_CFG */ + 0xc0000025 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000005 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000004 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0505 /* MC_EMEM_ARB_DA_COVERS */ + 0x74040a06 /* MC_EMEM_ARB_MISC0 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + timing-400000000 { + clock-frequency = <400000000>; + nvidia,emem-configuration = < + 0x0000000c /* MC_EMEM_ARB_CFG */ + 0xc0000048 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000009 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000005 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000007 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06030202 /* MC_EMEM_ARB_DA_TURNS */ + 0x000d0709 /* MC_EMEM_ARB_DA_COVERS */ + 0x7086120a /* MC_EMEM_ARB_MISC0 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + timing-800000000 { + clock-frequency = <800000000>; + nvidia,emem-configuration = < + 0x00000018 /* MC_EMEM_ARB_CFG */ + 0xc0000090 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000004 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000005 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000013 /* MC_EMEM_ARB_TIMING_RC */ + 0x0000000c /* MC_EMEM_ARB_TIMING_RAS */ + 0x0000000f /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x0000000c /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000008 /* MC_EMEM_ARB_TIMING_W2R */ + 0x08040202 /* MC_EMEM_ARB_DA_TURNS */ + 0x00160d13 /* MC_EMEM_ARB_DA_COVERS */ + 0x712c2414 /* MC_EMEM_ARB_MISC0 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + }; +}; +&emc_timings { + emc-timings-0 { + nvidia,ram-code = <0>; /* Samsung RAM */ + timing-25500000 { + clock-frequency = <25500000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-periodic-qrst; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-configuration = < + 0x00000001 /* EMC_RC */ + 0x00000006 /* EMC_RFC */ + 0x00000000 /* EMC_RAS */ + 0x00000000 /* EMC_RP */ + 0x00000002 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000005 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000000 /* EMC_RD_RCD */ + 0x00000000 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000001 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000005 /* EMC_WDV */ + 0x00000005 /* EMC_QUSE */ + 0x00000004 /* EMC_QRST */ + 0x0000000a /* EMC_QSAFE */ + 0x0000000b /* EMC_RDV */ + 0x000000c0 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000030 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000007 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x00000007 /* EMC_TXSR */ + 0x00000007 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000002 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000004 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x000000c7 /* EMC_TREFBW */ + 0x00000006 /* EMC_QUSE_EXTRA */ + 0x00000004 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x00004288 /* EMC_FBIO_CFG5 */ + 0x007800a4 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x000fc000 /* EMC_DLL_XFORM_DQS0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS3 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS4 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS5 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS6 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS7 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0 /* EMC_XM2CMDPADCTRL */ + 0x0800211c /* EMC_XM2DQSPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x77fff884 /* EMC_XM2CLKPADCTRL */ + 0x01f1f108 /* EMC_XM2COMPPADCTRL */ + 0x05057404 /* EMC_XM2VTTGENPADCTRL */ + 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ + 0x08000168 /* EMC_XM2QUSEPADCTRL */ + 0x08000000 /* EMC_XM2DQSPADCTRL3 */ + 0x00000802 /* EMC_CTT_TERM_CTRL */ + 0x00000000 /* EMC_ZCAL_INTERVAL */ + 0x00000040 /* EMC_ZCAL_WAIT_CNT */ + 0x000c000c /* EMC_MRS_WAIT_CNT */ + 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ + 0x00000000 /* EMC_CTT */ + 0x00000000 /* EMC_CTT_DURATION */ + 0x80000287 /* EMC_DYN_SELF_REF_CONTROL */ + 0xe8000000 /* EMC_FBIO_SPARE */ + 0xff00ff00 /* EMC_CFG_RSV */ + >; + }; + timing-51000000 { + clock-frequency = <51000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-periodic-qrst; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-configuration = < + 0x00000002 /* EMC_RC */ + 0x0000000d /* EMC_RFC */ + 0x00000001 /* EMC_RAS */ + 0x00000000 /* EMC_RP */ + 0x00000002 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000005 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000000 /* EMC_RD_RCD */ + 0x00000000 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000001 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000005 /* EMC_WDV */ + 0x00000005 /* EMC_QUSE */ + 0x00000004 /* EMC_QRST */ + 0x0000000a /* EMC_QSAFE */ + 0x0000000b /* EMC_RDV */ + 0x00000181 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000060 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000007 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x0000000e /* EMC_TXSR */ + 0x0000000e /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000003 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000004 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x0000018e /* EMC_TREFBW */ + 0x00000006 /* EMC_QUSE_EXTRA */ + 0x00000004 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x00004288 /* EMC_FBIO_CFG5 */ + 0x007800a4 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x000fc000 /* EMC_DLL_XFORM_DQS0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS3 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS4 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS5 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS6 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS7 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0 /* EMC_XM2CMDPADCTRL */ + 0x0800211c /* EMC_XM2DQSPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x77fff884 /* EMC_XM2CLKPADCTRL */ + 0x01f1f108 /* EMC_XM2COMPPADCTRL */ + 0x05057404 /* EMC_XM2VTTGENPADCTRL */ + 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ + 0x08000168 /* EMC_XM2QUSEPADCTRL */ + 0x08000000 /* EMC_XM2DQSPADCTRL3 */ + 0x00000802 /* EMC_CTT_TERM_CTRL */ + 0x00000000 /* EMC_ZCAL_INTERVAL */ + 0x00000040 /* EMC_ZCAL_WAIT_CNT */ + 0x000c000c /* EMC_MRS_WAIT_CNT */ + 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ + 0x00000000 /* EMC_CTT */ + 0x00000000 /* EMC_CTT_DURATION */ + 0x8000040b /* EMC_DYN_SELF_REF_CONTROL */ + 0xe8000000 /* EMC_FBIO_SPARE */ + 0xff00ff00 /* EMC_CFG_RSV */ + >; + }; + timing-102000000 { + clock-frequency = <102000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-periodic-qrst; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-configuration = < + 0x00000004 /* EMC_RC */ + 0x0000001a /* EMC_RFC */ + 0x00000003 /* EMC_RAS */ + 0x00000001 /* EMC_RP */ + 0x00000002 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000005 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000001 /* EMC_RD_RCD */ + 0x00000001 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000001 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000005 /* EMC_WDV */ + 0x00000005 /* EMC_QUSE */ + 0x00000004 /* EMC_QRST */ + 0x0000000a /* EMC_QSAFE */ + 0x0000000b /* EMC_RDV */ + 0x00000303 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x000000c0 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000007 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x0000001c /* EMC_TXSR */ + 0x0000001c /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000005 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000004 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x0000031c /* EMC_TREFBW */ + 0x00000006 /* EMC_QUSE_EXTRA */ + 0x00000004 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x00004288 /* EMC_FBIO_CFG5 */ + 0x007800a4 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x000fc000 /* EMC_DLL_XFORM_DQS0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS3 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS4 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS5 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS6 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS7 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0 /* EMC_XM2CMDPADCTRL */ + 0x0800211c /* EMC_XM2DQSPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x77fff884 /* EMC_XM2CLKPADCTRL */ + 0x01f1f108 /* EMC_XM2COMPPADCTRL */ + 0x05057404 /* EMC_XM2VTTGENPADCTRL */ + 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ + 0x08000168 /* EMC_XM2QUSEPADCTRL */ + 0x08000000 /* EMC_XM2DQSPADCTRL3 */ + 0x00000802 /* EMC_CTT_TERM_CTRL */ + 0x00000000 /* EMC_ZCAL_INTERVAL */ + 0x00000040 /* EMC_ZCAL_WAIT_CNT */ + 0x000c000c /* EMC_MRS_WAIT_CNT */ + 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ + 0x00000000 /* EMC_CTT */ + 0x00000000 /* EMC_CTT_DURATION */ + 0x80000713 /* EMC_DYN_SELF_REF_CONTROL */ + 0xe8000000 /* EMC_FBIO_SPARE */ + 0xff00ff00 /* EMC_CFG_RSV */ + >; + }; + timing-204000000 { + clock-frequency = <204000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-periodic-qrst; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-configuration = < + 0x00000009 /* EMC_RC */ + 0x00000035 /* EMC_RFC */ + 0x00000007 /* EMC_RAS */ + 0x00000002 /* EMC_RP */ + 0x00000002 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000005 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000002 /* EMC_RD_RCD */ + 0x00000002 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000001 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000005 /* EMC_WDV */ + 0x00000005 /* EMC_QUSE */ + 0x00000004 /* EMC_QRST */ + 0x0000000a /* EMC_QSAFE */ + 0x0000000b /* EMC_RDV */ + 0x00000607 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000181 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000007 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x00000038 /* EMC_TXSR */ + 0x00000038 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000009 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000004 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x00000638 /* EMC_TREFBW */ + 0x00000006 /* EMC_QUSE_EXTRA */ + 0x00000006 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x00004288 /* EMC_FBIO_CFG5 */ + 0x004400a4 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00080000 /* EMC_DLL_XFORM_DQS0 */ + 0x00080000 /* EMC_DLL_XFORM_DQS1 */ + 0x00080000 /* EMC_DLL_XFORM_DQS2 */ + 0x00080000 /* EMC_DLL_XFORM_DQS3 */ + 0x00080000 /* EMC_DLL_XFORM_DQS4 */ + 0x00080000 /* EMC_DLL_XFORM_DQS5 */ + 0x00080000 /* EMC_DLL_XFORM_DQS6 */ + 0x00080000 /* EMC_DLL_XFORM_DQS7 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00080000 /* EMC_DLL_XFORM_DQ0 */ + 0x00080000 /* EMC_DLL_XFORM_DQ1 */ + 0x00080000 /* EMC_DLL_XFORM_DQ2 */ + 0x00080000 /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0 /* EMC_XM2CMDPADCTRL */ + 0x0800211c /* EMC_XM2DQSPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x77fff884 /* EMC_XM2CLKPADCTRL */ + 0x01f1f108 /* EMC_XM2COMPPADCTRL */ + 0x05057404 /* EMC_XM2VTTGENPADCTRL */ + 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ + 0x08000168 /* EMC_XM2QUSEPADCTRL */ + 0x08000000 /* EMC_XM2DQSPADCTRL3 */ + 0x00000802 /* EMC_CTT_TERM_CTRL */ + 0x00020000 /* EMC_ZCAL_INTERVAL */ + 0x00000100 /* EMC_ZCAL_WAIT_CNT */ + 0x000c000c /* EMC_MRS_WAIT_CNT */ + 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ + 0x00000000 /* EMC_CTT */ + 0x00000000 /* EMC_CTT_DURATION */ + 0x80000d22 /* EMC_DYN_SELF_REF_CONTROL */ + 0xe8000000 /* EMC_FBIO_SPARE */ + 0xff00ff00 /* EMC_CFG_RSV */ + >; + }; + timing-400000000 { + clock-frequency = <400000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200000>; + nvidia,emc-mode-reset = <0x80000521>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-configuration = < + 0x00000012 /* EMC_RC */ + 0x00000066 /* EMC_RFC */ + 0x0000000c /* EMC_RAS */ + 0x00000004 /* EMC_RP */ + 0x00000003 /* EMC_R2W */ + 0x00000008 /* EMC_W2R */ + 0x00000002 /* EMC_R2P */ + 0x0000000a /* EMC_W2P */ + 0x00000004 /* EMC_RD_RCD */ + 0x00000004 /* EMC_WR_RCD */ + 0x00000002 /* EMC_RRD */ + 0x00000001 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000004 /* EMC_WDV */ + 0x00000006 /* EMC_QUSE */ + 0x00000004 /* EMC_QRST */ + 0x0000000a /* EMC_QSAFE */ + 0x0000000c /* EMC_RDV */ + 0x00000bf0 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x000002fc /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000001 /* EMC_PDEX2WR */ + 0x00000008 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000008 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x0000006c /* EMC_TXSR */ + 0x00000200 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000010 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000004 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x00000c30 /* EMC_TREFBW */ + 0x00000000 /* EMC_QUSE_EXTRA */ + 0x00000004 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x00007088 /* EMC_FBIO_CFG5 */ + 0x001d0084 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x0003c000 /* EMC_DLL_XFORM_DQS0 */ + 0x0003c000 /* EMC_DLL_XFORM_DQS1 */ + 0x0003c000 /* EMC_DLL_XFORM_DQS2 */ + 0x0003c000 /* EMC_DLL_XFORM_DQS3 */ + 0x0003c000 /* EMC_DLL_XFORM_DQS4 */ + 0x0003c000 /* EMC_DLL_XFORM_DQS5 */ + 0x0003c000 /* EMC_DLL_XFORM_DQS6 */ + 0x0003c000 /* EMC_DLL_XFORM_DQS7 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00048000 /* EMC_DLL_XFORM_DQ0 */ + 0x00048000 /* EMC_DLL_XFORM_DQ1 */ + 0x00048000 /* EMC_DLL_XFORM_DQ2 */ + 0x00048000 /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0 /* EMC_XM2CMDPADCTRL */ + 0x0800013d /* EMC_XM2DQSPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x77fff884 /* EMC_XM2CLKPADCTRL */ + 0x01f1f508 /* EMC_XM2COMPPADCTRL */ + 0x05057404 /* EMC_XM2VTTGENPADCTRL */ + 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ + 0x080001e8 /* EMC_XM2QUSEPADCTRL */ + 0x08000021 /* EMC_XM2DQSPADCTRL3 */ + 0x00000802 /* EMC_CTT_TERM_CTRL */ + 0x00020000 /* EMC_ZCAL_INTERVAL */ + 0x00000100 /* EMC_ZCAL_WAIT_CNT */ + 0x0158000c /* EMC_MRS_WAIT_CNT */ + 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ + 0x00000000 /* EMC_CTT */ + 0x00000000 /* EMC_CTT_DURATION */ + 0x800018c8 /* EMC_DYN_SELF_REF_CONTROL */ + 0xe8000000 /* EMC_FBIO_SPARE */ + 0xff00ff89 /* EMC_CFG_RSV */ + >; + }; + timing-800000000 { + clock-frequency = <800000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200018>; + nvidia,emc-mode-reset = <0x80000d71>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-periodic-qrst; + nvidia,emc-configuration = < + 0x00000025 /* EMC_RC */ + 0x000000ce /* EMC_RFC */ + 0x0000001a /* EMC_RAS */ + 0x00000009 /* EMC_RP */ + 0x00000005 /* EMC_R2W */ + 0x0000000d /* EMC_W2R */ + 0x00000004 /* EMC_R2P */ + 0x00000013 /* EMC_W2P */ + 0x00000009 /* EMC_RD_RCD */ + 0x00000009 /* EMC_WR_RCD */ + 0x00000004 /* EMC_RRD */ + 0x00000001 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000007 /* EMC_WDV */ + 0x0000000a /* EMC_QUSE */ + 0x00000009 /* EMC_QRST */ + 0x0000000b /* EMC_QSAFE */ + 0x00000011 /* EMC_RDV */ + 0x00001820 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000608 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000003 /* EMC_PDEX2WR */ + 0x00000012 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x0000000f /* EMC_AR2PDEN */ + 0x00000018 /* EMC_RW2PDEN */ + 0x000000d8 /* EMC_TXSR */ + 0x00000200 /* EMC_TXSRDLL */ + 0x00000005 /* EMC_TCKE */ + 0x00000020 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000007 /* EMC_TCLKSTABLE */ + 0x00000008 /* EMC_TCLKSTOP */ + 0x00001860 /* EMC_TREFBW */ + 0x0000000b /* EMC_QUSE_EXTRA */ + 0x00000006 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x00005088 /* EMC_FBIO_CFG5 */ + 0xf0070191 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x0000800a /* EMC_DLL_XFORM_DQS0 */ + 0x0000000a /* EMC_DLL_XFORM_DQS1 */ + 0x0000000a /* EMC_DLL_XFORM_DQS2 */ + 0x0000000a /* EMC_DLL_XFORM_DQS3 */ + 0x0000000a /* EMC_DLL_XFORM_DQS4 */ + 0x0000000a /* EMC_DLL_XFORM_DQS5 */ + 0x0000000a /* EMC_DLL_XFORM_DQS6 */ + 0x0000000a /* EMC_DLL_XFORM_DQS7 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x0000000a /* EMC_DLL_XFORM_DQ0 */ + 0x0000000a /* EMC_DLL_XFORM_DQ1 */ + 0x0000000a /* EMC_DLL_XFORM_DQ2 */ + 0x0000000a /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0 /* EMC_XM2CMDPADCTRL */ + 0x0600013d /* EMC_XM2DQSPADCTRL2 */ + 0x22220000 /* EMC_XM2DQPADCTRL2 */ + 0x77fff884 /* EMC_XM2CLKPADCTRL */ + 0x01f1f501 /* EMC_XM2COMPPADCTRL */ + 0x07077404 /* EMC_XM2VTTGENPADCTRL */ + 0x54000000 /* EMC_XM2VTTGENPADCTRL2 */ + 0x080001e8 /* EMC_XM2QUSEPADCTRL */ + 0x08000021 /* EMC_XM2DQSPADCTRL3 */ + 0x00000802 /* EMC_CTT_TERM_CTRL */ + 0x00020000 /* EMC_ZCAL_INTERVAL */ + 0x00000100 /* EMC_ZCAL_WAIT_CNT */ + 0x00f0000c /* EMC_MRS_WAIT_CNT */ + 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ + 0x00000000 /* EMC_CTT */ + 0x00000000 /* EMC_CTT_DURATION */ + 0x8000308c /* EMC_DYN_SELF_REF_CONTROL */ + 0xe8000000 /* EMC_FBIO_SPARE */ + 0xff00ff49 /* EMC_CFG_RSV */ + >; + }; + }; + emc-timings-1 { + nvidia,ram-code = <1>; /* Hynix M RAM */ + timing-25500000 { + clock-frequency = <25500000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-periodic-qrst; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-configuration = < + 0x00000001 /* EMC_RC */ + 0x00000006 /* EMC_RFC */ + 0x00000000 /* EMC_RAS */ + 0x00000000 /* EMC_RP */ + 0x00000002 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000005 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000000 /* EMC_RD_RCD */ + 0x00000000 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000001 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000005 /* EMC_WDV */ + 0x00000005 /* EMC_QUSE */ + 0x00000004 /* EMC_QRST */ + 0x0000000a /* EMC_QSAFE */ + 0x0000000b /* EMC_RDV */ + 0x000000c0 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000030 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000007 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x00000007 /* EMC_TXSR */ + 0x00000007 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000002 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000004 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x000000c7 /* EMC_TREFBW */ + 0x00000006 /* EMC_QUSE_EXTRA */ + 0x00000004 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x00004288 /* EMC_FBIO_CFG5 */ + 0x007800a4 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x000fc000 /* EMC_DLL_XFORM_DQS0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS3 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS4 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS5 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS6 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS7 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0 /* EMC_XM2CMDPADCTRL */ + 0x0800211c /* EMC_XM2DQSPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x77fff884 /* EMC_XM2CLKPADCTRL */ + 0x01f1f108 /* EMC_XM2COMPPADCTRL */ + 0x05057404 /* EMC_XM2VTTGENPADCTRL */ + 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ + 0x08000168 /* EMC_XM2QUSEPADCTRL */ + 0x08000000 /* EMC_XM2DQSPADCTRL3 */ + 0x00000802 /* EMC_CTT_TERM_CTRL */ + 0x00000000 /* EMC_ZCAL_INTERVAL */ + 0x00000040 /* EMC_ZCAL_WAIT_CNT */ + 0x000c000c /* EMC_MRS_WAIT_CNT */ + 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ + 0x00000000 /* EMC_CTT */ + 0x00000000 /* EMC_CTT_DURATION */ + 0x80000287 /* EMC_DYN_SELF_REF_CONTROL */ + 0xe8000000 /* EMC_FBIO_SPARE */ + 0xff00ff00 /* EMC_CFG_RSV */ + >; + }; + timing-51000000 { + clock-frequency = <51000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-periodic-qrst; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-configuration = < + 0x00000002 /* EMC_RC */ + 0x0000000d /* EMC_RFC */ + 0x00000001 /* EMC_RAS */ + 0x00000000 /* EMC_RP */ + 0x00000002 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000005 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000000 /* EMC_RD_RCD */ + 0x00000000 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000001 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000005 /* EMC_WDV */ + 0x00000005 /* EMC_QUSE */ + 0x00000004 /* EMC_QRST */ + 0x0000000a /* EMC_QSAFE */ + 0x0000000b /* EMC_RDV */ + 0x00000181 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000060 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000007 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x0000000e /* EMC_TXSR */ + 0x0000000e /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000003 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000004 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x0000018e /* EMC_TREFBW */ + 0x00000006 /* EMC_QUSE_EXTRA */ + 0x00000004 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x00004288 /* EMC_FBIO_CFG5 */ + 0x007800a4 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x000fc000 /* EMC_DLL_XFORM_DQS0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS3 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS4 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS5 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS6 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS7 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0 /* EMC_XM2CMDPADCTRL */ + 0x0800211c /* EMC_XM2DQSPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x77fff884 /* EMC_XM2CLKPADCTRL */ + 0x01f1f108 /* EMC_XM2COMPPADCTRL */ + 0x05057404 /* EMC_XM2VTTGENPADCTRL */ + 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ + 0x08000168 /* EMC_XM2QUSEPADCTRL */ + 0x08000000 /* EMC_XM2DQSPADCTRL3 */ + 0x00000802 /* EMC_CTT_TERM_CTRL */ + 0x00000000 /* EMC_ZCAL_INTERVAL */ + 0x00000040 /* EMC_ZCAL_WAIT_CNT */ + 0x000c000c /* EMC_MRS_WAIT_CNT */ + 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ + 0x00000000 /* EMC_CTT */ + 0x00000000 /* EMC_CTT_DURATION */ + 0x8000040b /* EMC_DYN_SELF_REF_CONTROL */ + 0xe8000000 /* EMC_FBIO_SPARE */ + 0xff00ff00 /* EMC_CFG_RSV */ + >; + }; + timing-102000000 { + clock-frequency = <102000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-periodic-qrst; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-configuration = < + 0x00000004 /* EMC_RC */ + 0x0000001a /* EMC_RFC */ + 0x00000003 /* EMC_RAS */ + 0x00000001 /* EMC_RP */ + 0x00000002 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000005 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000001 /* EMC_RD_RCD */ + 0x00000001 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000001 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000005 /* EMC_WDV */ + 0x00000005 /* EMC_QUSE */ + 0x00000004 /* EMC_QRST */ + 0x0000000a /* EMC_QSAFE */ + 0x0000000b /* EMC_RDV */ + 0x00000303 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x000000c0 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000007 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x0000001c /* EMC_TXSR */ + 0x0000001c /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000005 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000004 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x0000031c /* EMC_TREFBW */ + 0x00000006 /* EMC_QUSE_EXTRA */ + 0x00000004 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x00004288 /* EMC_FBIO_CFG5 */ + 0x007800a4 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x000fc000 /* EMC_DLL_XFORM_DQS0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS3 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS4 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS5 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS6 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS7 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0 /* EMC_XM2CMDPADCTRL */ + 0x0800211c /* EMC_XM2DQSPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x77fff884 /* EMC_XM2CLKPADCTRL */ + 0x01f1f108 /* EMC_XM2COMPPADCTRL */ + 0x05057404 /* EMC_XM2VTTGENPADCTRL */ + 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ + 0x08000168 /* EMC_XM2QUSEPADCTRL */ + 0x08000000 /* EMC_XM2DQSPADCTRL3 */ + 0x00000802 /* EMC_CTT_TERM_CTRL */ + 0x00000000 /* EMC_ZCAL_INTERVAL */ + 0x00000040 /* EMC_ZCAL_WAIT_CNT */ + 0x000c000c /* EMC_MRS_WAIT_CNT */ + 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ + 0x00000000 /* EMC_CTT */ + 0x00000000 /* EMC_CTT_DURATION */ + 0x80000713 /* EMC_DYN_SELF_REF_CONTROL */ + 0xe8000000 /* EMC_FBIO_SPARE */ + 0xff00ff00 /* EMC_CFG_RSV */ + >; + }; + timing-204000000 { + clock-frequency = <204000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-periodic-qrst; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-configuration = < + 0x00000009 /* EMC_RC */ + 0x00000035 /* EMC_RFC */ + 0x00000007 /* EMC_RAS */ + 0x00000002 /* EMC_RP */ + 0x00000002 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000005 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000002 /* EMC_RD_RCD */ + 0x00000002 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000001 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000005 /* EMC_WDV */ + 0x00000005 /* EMC_QUSE */ + 0x00000004 /* EMC_QRST */ + 0x0000000a /* EMC_QSAFE */ + 0x0000000b /* EMC_RDV */ + 0x00000607 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000181 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000007 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x00000038 /* EMC_TXSR */ + 0x00000038 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000009 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000004 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x00000638 /* EMC_TREFBW */ + 0x00000006 /* EMC_QUSE_EXTRA */ + 0x00000006 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x00004288 /* EMC_FBIO_CFG5 */ + 0x004400a4 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00080000 /* EMC_DLL_XFORM_DQS0 */ + 0x00080000 /* EMC_DLL_XFORM_DQS1 */ + 0x00080000 /* EMC_DLL_XFORM_DQS2 */ + 0x00080000 /* EMC_DLL_XFORM_DQS3 */ + 0x00080000 /* EMC_DLL_XFORM_DQS4 */ + 0x00080000 /* EMC_DLL_XFORM_DQS5 */ + 0x00080000 /* EMC_DLL_XFORM_DQS6 */ + 0x00080000 /* EMC_DLL_XFORM_DQS7 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00080000 /* EMC_DLL_XFORM_DQ0 */ + 0x00080000 /* EMC_DLL_XFORM_DQ1 */ + 0x00080000 /* EMC_DLL_XFORM_DQ2 */ + 0x00080000 /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0 /* EMC_XM2CMDPADCTRL */ + 0x0800211c /* EMC_XM2DQSPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x77fff884 /* EMC_XM2CLKPADCTRL */ + 0x01f1f108 /* EMC_XM2COMPPADCTRL */ + 0x05057404 /* EMC_XM2VTTGENPADCTRL */ + 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ + 0x08000168 /* EMC_XM2QUSEPADCTRL */ + 0x08000000 /* EMC_XM2DQSPADCTRL3 */ + 0x00000802 /* EMC_CTT_TERM_CTRL */ + 0x00020000 /* EMC_ZCAL_INTERVAL */ + 0x00000100 /* EMC_ZCAL_WAIT_CNT */ + 0x000c000c /* EMC_MRS_WAIT_CNT */ + 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ + 0x00000000 /* EMC_CTT */ + 0x00000000 /* EMC_CTT_DURATION */ + 0x80000d22 /* EMC_DYN_SELF_REF_CONTROL */ + 0xe8000000 /* EMC_FBIO_SPARE */ + 0xff00ff00 /* EMC_CFG_RSV */ + >; + }; + timing-400000000 { + clock-frequency = <400000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200000>; + nvidia,emc-mode-reset = <0x80000521>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-configuration = < + 0x00000012 /* EMC_RC */ + 0x00000066 /* EMC_RFC */ + 0x0000000c /* EMC_RAS */ + 0x00000004 /* EMC_RP */ + 0x00000003 /* EMC_R2W */ + 0x00000008 /* EMC_W2R */ + 0x00000002 /* EMC_R2P */ + 0x0000000a /* EMC_W2P */ + 0x00000004 /* EMC_RD_RCD */ + 0x00000004 /* EMC_WR_RCD */ + 0x00000002 /* EMC_RRD */ + 0x00000001 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000004 /* EMC_WDV */ + 0x00000006 /* EMC_QUSE */ + 0x00000004 /* EMC_QRST */ + 0x0000000a /* EMC_QSAFE */ + 0x0000000c /* EMC_RDV */ + 0x00000bf0 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x000002fc /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000001 /* EMC_PDEX2WR */ + 0x00000008 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000008 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x0000006c /* EMC_TXSR */ + 0x00000200 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000010 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000004 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x00000c30 /* EMC_TREFBW */ + 0x00000000 /* EMC_QUSE_EXTRA */ + 0x00000004 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x00007088 /* EMC_FBIO_CFG5 */ + 0x001d0084 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x0003c000 /* EMC_DLL_XFORM_DQS0 */ + 0x0003c000 /* EMC_DLL_XFORM_DQS1 */ + 0x0003c000 /* EMC_DLL_XFORM_DQS2 */ + 0x0003c000 /* EMC_DLL_XFORM_DQS3 */ + 0x0003c000 /* EMC_DLL_XFORM_DQS4 */ + 0x0003c000 /* EMC_DLL_XFORM_DQS5 */ + 0x0003c000 /* EMC_DLL_XFORM_DQS6 */ + 0x0003c000 /* EMC_DLL_XFORM_DQS7 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00048000 /* EMC_DLL_XFORM_DQ0 */ + 0x00048000 /* EMC_DLL_XFORM_DQ1 */ + 0x00048000 /* EMC_DLL_XFORM_DQ2 */ + 0x00048000 /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0 /* EMC_XM2CMDPADCTRL */ + 0x0800013d /* EMC_XM2DQSPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x77fff884 /* EMC_XM2CLKPADCTRL */ + 0x01f1f508 /* EMC_XM2COMPPADCTRL */ + 0x05057404 /* EMC_XM2VTTGENPADCTRL */ + 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ + 0x080001e8 /* EMC_XM2QUSEPADCTRL */ + 0x08000021 /* EMC_XM2DQSPADCTRL3 */ + 0x00000802 /* EMC_CTT_TERM_CTRL */ + 0x00020000 /* EMC_ZCAL_INTERVAL */ + 0x00000100 /* EMC_ZCAL_WAIT_CNT */ + 0x0158000c /* EMC_MRS_WAIT_CNT */ + 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ + 0x00000000 /* EMC_CTT */ + 0x00000000 /* EMC_CTT_DURATION */ + 0x800018c8 /* EMC_DYN_SELF_REF_CONTROL */ + 0xe8000000 /* EMC_FBIO_SPARE */ + 0xff00ff89 /* EMC_CFG_RSV */ + >; + }; + timing-800000000 { + clock-frequency = <800000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200018>; + nvidia,emc-mode-reset = <0x80000d71>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-periodic-qrst; + nvidia,emc-configuration = < + 0x00000025 /* EMC_RC */ + 0x000000ce /* EMC_RFC */ + 0x0000001a /* EMC_RAS */ + 0x00000009 /* EMC_RP */ + 0x00000005 /* EMC_R2W */ + 0x0000000d /* EMC_W2R */ + 0x00000004 /* EMC_R2P */ + 0x00000013 /* EMC_W2P */ + 0x00000009 /* EMC_RD_RCD */ + 0x00000009 /* EMC_WR_RCD */ + 0x00000004 /* EMC_RRD */ + 0x00000001 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000007 /* EMC_WDV */ + 0x0000000a /* EMC_QUSE */ + 0x00000009 /* EMC_QRST */ + 0x0000000b /* EMC_QSAFE */ + 0x00000011 /* EMC_RDV */ + 0x00001820 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000608 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000003 /* EMC_PDEX2WR */ + 0x00000012 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x0000000f /* EMC_AR2PDEN */ + 0x00000018 /* EMC_RW2PDEN */ + 0x000000d8 /* EMC_TXSR */ + 0x00000200 /* EMC_TXSRDLL */ + 0x00000005 /* EMC_TCKE */ + 0x00000020 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000007 /* EMC_TCLKSTABLE */ + 0x00000008 /* EMC_TCLKSTOP */ + 0x00001860 /* EMC_TREFBW */ + 0x0000000b /* EMC_QUSE_EXTRA */ + 0x00000006 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x00005088 /* EMC_FBIO_CFG5 */ + 0xf0070191 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x0000800a /* EMC_DLL_XFORM_DQS0 */ + 0x0000000a /* EMC_DLL_XFORM_DQS1 */ + 0x0000000a /* EMC_DLL_XFORM_DQS2 */ + 0x0000000a /* EMC_DLL_XFORM_DQS3 */ + 0x0000000a /* EMC_DLL_XFORM_DQS4 */ + 0x0000000a /* EMC_DLL_XFORM_DQS5 */ + 0x0000000a /* EMC_DLL_XFORM_DQS6 */ + 0x0000000a /* EMC_DLL_XFORM_DQS7 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x0000000a /* EMC_DLL_XFORM_DQ0 */ + 0x0000000a /* EMC_DLL_XFORM_DQ1 */ + 0x0000000a /* EMC_DLL_XFORM_DQ2 */ + 0x0000000a /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0 /* EMC_XM2CMDPADCTRL */ + 0x0600013d /* EMC_XM2DQSPADCTRL2 */ + 0x22220000 /* EMC_XM2DQPADCTRL2 */ + 0x77fff884 /* EMC_XM2CLKPADCTRL */ + 0x01f1f501 /* EMC_XM2COMPPADCTRL */ + 0x07077404 /* EMC_XM2VTTGENPADCTRL */ + 0x54000000 /* EMC_XM2VTTGENPADCTRL2 */ + 0x080001e8 /* EMC_XM2QUSEPADCTRL */ + 0x08000021 /* EMC_XM2DQSPADCTRL3 */ + 0x00000802 /* EMC_CTT_TERM_CTRL */ + 0x00020000 /* EMC_ZCAL_INTERVAL */ + 0x00000100 /* EMC_ZCAL_WAIT_CNT */ + 0x00f0000c /* EMC_MRS_WAIT_CNT */ + 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ + 0x00000000 /* EMC_CTT */ + 0x00000000 /* EMC_CTT_DURATION */ + 0x8000308c /* EMC_DYN_SELF_REF_CONTROL */ + 0xe8000000 /* EMC_FBIO_SPARE */ + 0xff00ff49 /* EMC_CFG_RSV */ + >; + }; + }; + emc-timings-2 { + nvidia,ram-code = <2>; /* Hynix A RAM */ + timing-25500000 { + clock-frequency = <25500000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-periodic-qrst; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-configuration = < + 0x00000001 /* EMC_RC */ + 0x00000007 /* EMC_RFC */ + 0x00000000 /* EMC_RAS */ + 0x00000000 /* EMC_RP */ + 0x00000002 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000005 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000000 /* EMC_RD_RCD */ + 0x00000000 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000001 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000005 /* EMC_WDV */ + 0x00000005 /* EMC_QUSE */ + 0x00000004 /* EMC_QRST */ + 0x0000000a /* EMC_QSAFE */ + 0x0000000b /* EMC_RDV */ + 0x000000c0 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000030 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000007 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x00000008 /* EMC_TXSR */ + 0x00000008 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000002 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000004 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x000000c7 /* EMC_TREFBW */ + 0x00000006 /* EMC_QUSE_EXTRA */ + 0x00000004 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x00004288 /* EMC_FBIO_CFG5 */ + 0x007800a4 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x000fc000 /* EMC_DLL_XFORM_DQS0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS3 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS4 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS5 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS6 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS7 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0 /* EMC_XM2CMDPADCTRL */ + 0x0800211c /* EMC_XM2DQSPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x77fff884 /* EMC_XM2CLKPADCTRL */ + 0x01f1f108 /* EMC_XM2COMPPADCTRL */ + 0x05057404 /* EMC_XM2VTTGENPADCTRL */ + 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ + 0x08000168 /* EMC_XM2QUSEPADCTRL */ + 0x08000000 /* EMC_XM2DQSPADCTRL3 */ + 0x00000802 /* EMC_CTT_TERM_CTRL */ + 0x00000000 /* EMC_ZCAL_INTERVAL */ + 0x00000040 /* EMC_ZCAL_WAIT_CNT */ + 0x000c000c /* EMC_MRS_WAIT_CNT */ + 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ + 0x00000000 /* EMC_CTT */ + 0x00000000 /* EMC_CTT_DURATION */ + 0x80000287 /* EMC_DYN_SELF_REF_CONTROL */ + 0xe8000000 /* EMC_FBIO_SPARE */ + 0xff00ff00 /* EMC_CFG_RSV */ + >; + }; + timing-51000000 { + clock-frequency = <51000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-periodic-qrst; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-configuration = < + 0x00000002 /* EMC_RC */ + 0x0000000f /* EMC_RFC */ + 0x00000001 /* EMC_RAS */ + 0x00000000 /* EMC_RP */ + 0x00000002 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000005 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000000 /* EMC_RD_RCD */ + 0x00000000 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000001 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000005 /* EMC_WDV */ + 0x00000005 /* EMC_QUSE */ + 0x00000004 /* EMC_QRST */ + 0x0000000a /* EMC_QSAFE */ + 0x0000000b /* EMC_RDV */ + 0x00000181 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000060 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000007 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x00000010 /* EMC_TXSR */ + 0x00000010 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000003 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000004 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x0000018e /* EMC_TREFBW */ + 0x00000006 /* EMC_QUSE_EXTRA */ + 0x00000004 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x00004288 /* EMC_FBIO_CFG5 */ + 0x007800a4 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x000fc000 /* EMC_DLL_XFORM_DQS0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS3 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS4 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS5 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS6 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS7 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0 /* EMC_XM2CMDPADCTRL */ + 0x0800211c /* EMC_XM2DQSPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x77fff884 /* EMC_XM2CLKPADCTRL */ + 0x01f1f108 /* EMC_XM2COMPPADCTRL */ + 0x05057404 /* EMC_XM2VTTGENPADCTRL */ + 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ + 0x08000168 /* EMC_XM2QUSEPADCTRL */ + 0x08000000 /* EMC_XM2DQSPADCTRL3 */ + 0x00000802 /* EMC_CTT_TERM_CTRL */ + 0x00000000 /* EMC_ZCAL_INTERVAL */ + 0x00000040 /* EMC_ZCAL_WAIT_CNT */ + 0x000c000c /* EMC_MRS_WAIT_CNT */ + 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ + 0x00000000 /* EMC_CTT */ + 0x00000000 /* EMC_CTT_DURATION */ + 0x8000040b /* EMC_DYN_SELF_REF_CONTROL */ + 0xe8000000 /* EMC_FBIO_SPARE */ + 0xff00ff00 /* EMC_CFG_RSV */ + >; + }; + timing-102000000 { + clock-frequency = <102000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-periodic-qrst; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-configuration = < + 0x00000004 /* EMC_RC */ + 0x0000001e /* EMC_RFC */ + 0x00000003 /* EMC_RAS */ + 0x00000001 /* EMC_RP */ + 0x00000002 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000005 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000001 /* EMC_RD_RCD */ + 0x00000001 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000001 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000005 /* EMC_WDV */ + 0x00000005 /* EMC_QUSE */ + 0x00000004 /* EMC_QRST */ + 0x0000000a /* EMC_QSAFE */ + 0x0000000b /* EMC_RDV */ + 0x00000303 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x000000c0 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000007 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x00000020 /* EMC_TXSR */ + 0x00000020 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000005 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000004 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x0000031c /* EMC_TREFBW */ + 0x00000006 /* EMC_QUSE_EXTRA */ + 0x00000004 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x00004288 /* EMC_FBIO_CFG5 */ + 0x007800a4 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x000fc000 /* EMC_DLL_XFORM_DQS0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS3 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS4 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS5 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS6 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS7 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0 /* EMC_XM2CMDPADCTRL */ + 0x0800211c /* EMC_XM2DQSPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x77fff884 /* EMC_XM2CLKPADCTRL */ + 0x01f1f108 /* EMC_XM2COMPPADCTRL */ + 0x05057404 /* EMC_XM2VTTGENPADCTRL */ + 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ + 0x08000168 /* EMC_XM2QUSEPADCTRL */ + 0x08000000 /* EMC_XM2DQSPADCTRL3 */ + 0x00000802 /* EMC_CTT_TERM_CTRL */ + 0x00000000 /* EMC_ZCAL_INTERVAL */ + 0x00000040 /* EMC_ZCAL_WAIT_CNT */ + 0x000c000c /* EMC_MRS_WAIT_CNT */ + 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ + 0x00000000 /* EMC_CTT */ + 0x00000000 /* EMC_CTT_DURATION */ + 0x80000713 /* EMC_DYN_SELF_REF_CONTROL */ + 0xe8000000 /* EMC_FBIO_SPARE */ + 0xff00ff00 /* EMC_CFG_RSV */ + >; + }; + timing-204000000 { + clock-frequency = <204000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-periodic-qrst; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-configuration = < + 0x00000009 /* EMC_RC */ + 0x0000003d /* EMC_RFC */ + 0x00000007 /* EMC_RAS */ + 0x00000002 /* EMC_RP */ + 0x00000002 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000005 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000002 /* EMC_RD_RCD */ + 0x00000002 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000001 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000005 /* EMC_WDV */ + 0x00000005 /* EMC_QUSE */ + 0x00000004 /* EMC_QRST */ + 0x0000000a /* EMC_QSAFE */ + 0x0000000b /* EMC_RDV */ + 0x00000607 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000181 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000007 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x00000040 /* EMC_TXSR */ + 0x00000040 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000009 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000004 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x00000638 /* EMC_TREFBW */ + 0x00000006 /* EMC_QUSE_EXTRA */ + 0x00000006 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x00004288 /* EMC_FBIO_CFG5 */ + 0x004400a4 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00080000 /* EMC_DLL_XFORM_DQS0 */ + 0x00080000 /* EMC_DLL_XFORM_DQS1 */ + 0x00080000 /* EMC_DLL_XFORM_DQS2 */ + 0x00080000 /* EMC_DLL_XFORM_DQS3 */ + 0x00080000 /* EMC_DLL_XFORM_DQS4 */ + 0x00080000 /* EMC_DLL_XFORM_DQS5 */ + 0x00080000 /* EMC_DLL_XFORM_DQS6 */ + 0x00080000 /* EMC_DLL_XFORM_DQS7 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00080000 /* EMC_DLL_XFORM_DQ0 */ + 0x00080000 /* EMC_DLL_XFORM_DQ1 */ + 0x00080000 /* EMC_DLL_XFORM_DQ2 */ + 0x00080000 /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0 /* EMC_XM2CMDPADCTRL */ + 0x0800211c /* EMC_XM2DQSPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x77fff884 /* EMC_XM2CLKPADCTRL */ + 0x01f1f108 /* EMC_XM2COMPPADCTRL */ + 0x05057404 /* EMC_XM2VTTGENPADCTRL */ + 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ + 0x08000168 /* EMC_XM2QUSEPADCTRL */ + 0x08000000 /* EMC_XM2DQSPADCTRL3 */ + 0x00000802 /* EMC_CTT_TERM_CTRL */ + 0x00020000 /* EMC_ZCAL_INTERVAL */ + 0x00000100 /* EMC_ZCAL_WAIT_CNT */ + 0x000c000c /* EMC_MRS_WAIT_CNT */ + 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ + 0x00000000 /* EMC_CTT */ + 0x00000000 /* EMC_CTT_DURATION */ + 0x80000d22 /* EMC_DYN_SELF_REF_CONTROL */ + 0xe8000000 /* EMC_FBIO_SPARE */ + 0xff00ff00 /* EMC_CFG_RSV */ + >; + }; + timing-400000000 { + clock-frequency = <400000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200000>; + nvidia,emc-mode-reset = <0x80000521>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-configuration = < + 0x00000012 /* EMC_RC */ + 0x00000076 /* EMC_RFC */ + 0x0000000c /* EMC_RAS */ + 0x00000004 /* EMC_RP */ + 0x00000003 /* EMC_R2W */ + 0x00000008 /* EMC_W2R */ + 0x00000002 /* EMC_R2P */ + 0x0000000a /* EMC_W2P */ + 0x00000004 /* EMC_RD_RCD */ + 0x00000004 /* EMC_WR_RCD */ + 0x00000002 /* EMC_RRD */ + 0x00000001 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000004 /* EMC_WDV */ + 0x00000006 /* EMC_QUSE */ + 0x00000004 /* EMC_QRST */ + 0x0000000a /* EMC_QSAFE */ + 0x0000000c /* EMC_RDV */ + 0x00000bf0 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x000002fc /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000001 /* EMC_PDEX2WR */ + 0x00000008 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000008 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x0000007c /* EMC_TXSR */ + 0x00000200 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000010 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000004 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x00000c30 /* EMC_TREFBW */ + 0x00000000 /* EMC_QUSE_EXTRA */ + 0x00000004 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x00007088 /* EMC_FBIO_CFG5 */ + 0x001d0084 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00044000 /* EMC_DLL_XFORM_DQS0 */ + 0x00044000 /* EMC_DLL_XFORM_DQS1 */ + 0x00044000 /* EMC_DLL_XFORM_DQS2 */ + 0x00044000 /* EMC_DLL_XFORM_DQS3 */ + 0x00044000 /* EMC_DLL_XFORM_DQS4 */ + 0x00044000 /* EMC_DLL_XFORM_DQS5 */ + 0x00044000 /* EMC_DLL_XFORM_DQS6 */ + 0x00044000 /* EMC_DLL_XFORM_DQS7 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00058000 /* EMC_DLL_XFORM_DQ0 */ + 0x00058000 /* EMC_DLL_XFORM_DQ1 */ + 0x00058000 /* EMC_DLL_XFORM_DQ2 */ + 0x00058000 /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0 /* EMC_XM2CMDPADCTRL */ + 0x0800013d /* EMC_XM2DQSPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x77fff884 /* EMC_XM2CLKPADCTRL */ + 0x01f1f508 /* EMC_XM2COMPPADCTRL */ + 0x05057404 /* EMC_XM2VTTGENPADCTRL */ + 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ + 0x080001e8 /* EMC_XM2QUSEPADCTRL */ + 0x08000021 /* EMC_XM2DQSPADCTRL3 */ + 0x00000802 /* EMC_CTT_TERM_CTRL */ + 0x00020000 /* EMC_ZCAL_INTERVAL */ + 0x00000100 /* EMC_ZCAL_WAIT_CNT */ + 0x0148000c /* EMC_MRS_WAIT_CNT */ + 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ + 0x00000000 /* EMC_CTT */ + 0x00000000 /* EMC_CTT_DURATION */ + 0x800018c8 /* EMC_DYN_SELF_REF_CONTROL */ + 0xe8000000 /* EMC_FBIO_SPARE */ + 0xff00ff89 /* EMC_CFG_RSV */ + >; + }; + timing-800000000 { + clock-frequency = <800000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200018>; + nvidia,emc-mode-reset = <0x80000d71>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-periodic-qrst; + nvidia,emc-configuration = < + 0x00000025 /* EMC_RC */ + 0x000000ee /* EMC_RFC */ + 0x0000001a /* EMC_RAS */ + 0x00000009 /* EMC_RP */ + 0x00000005 /* EMC_R2W */ + 0x0000000d /* EMC_W2R */ + 0x00000004 /* EMC_R2P */ + 0x00000013 /* EMC_W2P */ + 0x00000009 /* EMC_RD_RCD */ + 0x00000009 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000001 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000007 /* EMC_WDV */ + 0x0000000a /* EMC_QUSE */ + 0x00000009 /* EMC_QRST */ + 0x0000000b /* EMC_QSAFE */ + 0x00000011 /* EMC_RDV */ + 0x00001820 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000608 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000003 /* EMC_PDEX2WR */ + 0x00000012 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x0000000f /* EMC_AR2PDEN */ + 0x00000018 /* EMC_RW2PDEN */ + 0x000000f8 /* EMC_TXSR */ + 0x00000200 /* EMC_TXSRDLL */ + 0x00000005 /* EMC_TCKE */ + 0x00000020 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000007 /* EMC_TCLKSTABLE */ + 0x00000008 /* EMC_TCLKSTOP */ + 0x00001860 /* EMC_TREFBW */ + 0x0000000b /* EMC_QUSE_EXTRA */ + 0x00000006 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x00005088 /* EMC_FBIO_CFG5 */ + 0xf0070191 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x0000000c /* EMC_DLL_XFORM_DQS0 */ + 0x007fc00a /* EMC_DLL_XFORM_DQS1 */ + 0x00000008 /* EMC_DLL_XFORM_DQS2 */ + 0x0000000a /* EMC_DLL_XFORM_DQS3 */ + 0x0000000a /* EMC_DLL_XFORM_DQS4 */ + 0x0000000a /* EMC_DLL_XFORM_DQS5 */ + 0x0000000a /* EMC_DLL_XFORM_DQS6 */ + 0x0000000a /* EMC_DLL_XFORM_DQS7 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x0000000a /* EMC_DLL_XFORM_DQ0 */ + 0x0000000c /* EMC_DLL_XFORM_DQ1 */ + 0x0000000a /* EMC_DLL_XFORM_DQ2 */ + 0x0000000a /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0 /* EMC_XM2CMDPADCTRL */ + 0x0600013d /* EMC_XM2DQSPADCTRL2 */ + 0x22220000 /* EMC_XM2DQPADCTRL2 */ + 0x77fff884 /* EMC_XM2CLKPADCTRL */ + 0x01f1f501 /* EMC_XM2COMPPADCTRL */ + 0x07077404 /* EMC_XM2VTTGENPADCTRL */ + 0x54000000 /* EMC_XM2VTTGENPADCTRL2 */ + 0x080001e8 /* EMC_XM2QUSEPADCTRL */ + 0x0a000021 /* EMC_XM2DQSPADCTRL3 */ + 0x00000802 /* EMC_CTT_TERM_CTRL */ + 0x00020000 /* EMC_ZCAL_INTERVAL */ + 0x00000100 /* EMC_ZCAL_WAIT_CNT */ + 0x00d0000c /* EMC_MRS_WAIT_CNT */ + 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ + 0x00000000 /* EMC_CTT */ + 0x00000000 /* EMC_CTT_DURATION */ + 0x8000308c /* EMC_DYN_SELF_REF_CONTROL */ + 0xe8000000 /* EMC_FBIO_SPARE */ + 0xff00ff49 /* EMC_CFG_RSV */ + >; + }; + }; +}; +&state_default { + clk_32k_out_pa0 { + nvidia,pins = "clk_32k_out_pa0"; + nvidia,function = "blink"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart3_cts_n_pa1 { + nvidia,pins = "uart3_cts_n_pa1"; + nvidia,function = "uartc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap2_fs_pa2 { + nvidia,pins = "dap2_fs_pa2"; + nvidia,function = "i2s1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap2_sclk_pa3 { + nvidia,pins = "dap2_sclk_pa3"; + nvidia,function = "i2s1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap2_din_pa4 { + nvidia,pins = "dap2_din_pa4"; + nvidia,function = "i2s1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap2_dout_pa5 { + nvidia,pins = "dap2_dout_pa5"; + nvidia,function = "i2s1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc3_clk_pa6 { + nvidia,pins = "sdmmc3_clk_pa6"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc3_cmd_pa7 { + nvidia,pins = "sdmmc3_cmd_pa7"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_a17_pb0 { + nvidia,pins = "gmi_a17_pb0"; + nvidia,function = "spi4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_a18_pb1 { + nvidia,pins = "gmi_a18_pb1"; + nvidia,function = "spi4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_pwr0_pb2 { + nvidia,pins = "lcd_pwr0_pb2"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_pclk_pb3 { + nvidia,pins = "lcd_pclk_pb3"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc3_dat3_pb4 { + nvidia,pins = "sdmmc3_dat3_pb4"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc3_dat2_pb5 { + nvidia,pins = "sdmmc3_dat2_pb5"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc3_dat1_pb6 { + nvidia,pins = "sdmmc3_dat1_pb6"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc3_dat0_pb7 { + nvidia,pins = "sdmmc3_dat0_pb7"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart3_rts_n_pc0 { + nvidia,pins = "uart3_rts_n_pc0"; + nvidia,function = "uartc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_pwr1_pc1 { + nvidia,pins = "lcd_pwr1_pc1"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart2_txd_pc2 { + nvidia,pins = "uart2_txd_pc2"; + nvidia,function = "uartb"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart2_rxd_pc3 { + nvidia,pins = "uart2_rxd_pc3"; + nvidia,function = "uartb"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gen1_i2c_scl_pc4 { + nvidia,pins = "gen1_i2c_scl_pc4"; + nvidia,function = "i2c1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + gen1_i2c_sda_pc5 { + nvidia,pins = "gen1_i2c_sda_pc5"; + nvidia,function = "i2c1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + lcd_pwr2_pc6 { + nvidia,pins = "lcd_pwr2_pc6"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_wp_n_pc7 { + nvidia,pins = "gmi_wp_n_pc7"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc3_dat5_pd0 { + nvidia,pins = "sdmmc3_dat5_pd0"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc3_dat4_pd1 { + nvidia,pins = "sdmmc3_dat4_pd1"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_dc1_pd2 { + nvidia,pins = "lcd_dc1_pd2"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc3_dat6_pd3 { + nvidia,pins = "sdmmc3_dat6_pd3"; + nvidia,function = "spi4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc3_dat7_pd4 { + nvidia,pins = "sdmmc3_dat7_pd4"; + nvidia,function = "spi4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + vi_d1_pd5 { + nvidia,pins = "vi_d1_pd5"; + nvidia,function = "sdmmc2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + vi_vsync_pd6 { + nvidia,pins = "vi_vsync_pd6"; + nvidia,function = "ddr"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + vi_hsync_pd7 { + nvidia,pins = "vi_hsync_pd7"; + nvidia,function = "ddr"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_d0_pe0 { + nvidia,pins = "lcd_d0_pe0"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_d1_pe1 { + nvidia,pins = "lcd_d1_pe1"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_d2_pe2 { + nvidia,pins = "lcd_d2_pe2"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_d3_pe3 { + nvidia,pins = "lcd_d3_pe3"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_d4_pe4 { + nvidia,pins = "lcd_d4_pe4"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_d5_pe5 { + nvidia,pins = "lcd_d5_pe5"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_d6_pe6 { + nvidia,pins = "lcd_d6_pe6"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_d7_pe7 { + nvidia,pins = "lcd_d7_pe7"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_d8_pf0 { + nvidia,pins = "lcd_d8_pf0"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_d9_pf1 { + nvidia,pins = "lcd_d9_pf1"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_d10_pf2 { + nvidia,pins = "lcd_d10_pf2"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_d11_pf3 { + nvidia,pins = "lcd_d11_pf3"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_d12_pf4 { + nvidia,pins = "lcd_d12_pf4"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_d13_pf5 { + nvidia,pins = "lcd_d13_pf5"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_d14_pf6 { + nvidia,pins = "lcd_d14_pf6"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_d15_pf7 { + nvidia,pins = "lcd_d15_pf7"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_ad0_pg0 { + nvidia,pins = "gmi_ad0_pg0"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_ad1_pg1 { + nvidia,pins = "gmi_ad1_pg1"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_ad2_pg2 { + nvidia,pins = "gmi_ad2_pg2"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_ad3_pg3 { + nvidia,pins = "gmi_ad3_pg3"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_ad4_pg4 { + nvidia,pins = "gmi_ad4_pg4"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_ad5_pg5 { + nvidia,pins = "gmi_ad5_pg5"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_ad6_pg6 { + nvidia,pins = "gmi_ad6_pg6"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_ad7_pg7 { + nvidia,pins = "gmi_ad7_pg7"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_ad8_ph0 { + nvidia,pins = "gmi_ad8_ph0"; + nvidia,function = "pwm0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_ad9_ph1 { + nvidia,pins = "gmi_ad9_ph1"; + nvidia,function = "pwm1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_ad10_ph2 { + nvidia,pins = "gmi_ad10_ph2"; + nvidia,function = "pwm2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_ad11_ph3 { + nvidia,pins = "gmi_ad11_ph3"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_ad12_ph4 { + nvidia,pins = "gmi_ad12_ph4"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_ad13_ph5 { + nvidia,pins = "gmi_ad13_ph5"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_ad14_ph6 { + nvidia,pins = "gmi_ad14_ph6"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_wr_n_pi0 { + nvidia,pins = "gmi_wr_n_pi0"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_oe_n_pi1 { + nvidia,pins = "gmi_oe_n_pi1"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_dqs_pi2 { + nvidia,pins = "gmi_dqs_pi2"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_iordy_pi5 { + nvidia,pins = "gmi_iordy_pi5"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_cs7_n_pi6 { + nvidia,pins = "gmi_cs7_n_pi6"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_wait_pi7 { + nvidia,pins = "gmi_wait_pi7"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_de_pj1 { + nvidia,pins = "lcd_de_pj1"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_cs1_n_pj2 { + nvidia,pins = "gmi_cs1_n_pj2"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_hsync_pj3 { + nvidia,pins = "lcd_hsync_pj3"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_vsync_pj4 { + nvidia,pins = "lcd_vsync_pj4"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart2_cts_n_pj5 { + nvidia,pins = "uart2_cts_n_pj5"; + nvidia,function = "uartb"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart2_rts_n_pj6 { + nvidia,pins = "uart2_rts_n_pj6"; + nvidia,function = "uartb"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_a16_pj7 { + nvidia,pins = "gmi_a16_pj7"; + nvidia,function = "spi4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_adv_n_pk0 { + nvidia,pins = "gmi_adv_n_pk0"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_clk_pk1 { + nvidia,pins = "gmi_clk_pk1"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_cs2_n_pk3 { + nvidia,pins = "gmi_cs2_n_pk3"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_cs3_n_pk4 { + nvidia,pins = "gmi_cs3_n_pk4"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + spdif_out_pk5 { + nvidia,pins = "spdif_out_pk5"; + nvidia,function = "spdif"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + spdif_in_pk6 { + nvidia,pins = "spdif_in_pk6"; + nvidia,function = "spdif"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_a19_pk7 { + nvidia,pins = "gmi_a19_pk7"; + nvidia,function = "spi4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + vi_d2_pl0 { + nvidia,pins = "vi_d2_pl0"; + nvidia,function = "sdmmc2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + vi_d3_pl1 { + nvidia,pins = "vi_d3_pl1"; + nvidia,function = "sdmmc2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + vi_d4_pl2 { + nvidia,pins = "vi_d4_pl2"; + nvidia,function = "vi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + vi_d5_pl3 { + nvidia,pins = "vi_d5_pl3"; + nvidia,function = "sdmmc2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + vi_d6_pl4 { + nvidia,pins = "vi_d6_pl4"; + nvidia,function = "vi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + vi_d7_pl5 { + nvidia,pins = "vi_d7_pl5"; + nvidia,function = "sdmmc2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + vi_d8_pl6 { + nvidia,pins = "vi_d8_pl6"; + nvidia,function = "sdmmc2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + vi_d9_pl7 { + nvidia,pins = "vi_d9_pl7"; + nvidia,function = "sdmmc2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_d16_pm0 { + nvidia,pins = "lcd_d16_pm0"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_d17_pm1 { + nvidia,pins = "lcd_d17_pm1"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_d18_pm2 { + nvidia,pins = "lcd_d18_pm2"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_d19_pm3 { + nvidia,pins = "lcd_d19_pm3"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_d20_pm4 { + nvidia,pins = "lcd_d20_pm4"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_d21_pm5 { + nvidia,pins = "lcd_d21_pm5"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_d22_pm6 { + nvidia,pins = "lcd_d22_pm6"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_d23_pm7 { + nvidia,pins = "lcd_d23_pm7"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap1_fs_pn0 { + nvidia,pins = "dap1_fs_pn0"; + nvidia,function = "i2s0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap1_din_pn1 { + nvidia,pins = "dap1_din_pn1"; + nvidia,function = "i2s0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap1_dout_pn2 { + nvidia,pins = "dap1_dout_pn2"; + nvidia,function = "i2s0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap1_sclk_pn3 { + nvidia,pins = "dap1_sclk_pn3"; + nvidia,function = "i2s0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_cs0_n_pn4 { + nvidia,pins = "lcd_cs0_n_pn4"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_sdout_pn5 { + nvidia,pins = "lcd_sdout_pn5"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_dc0_pn6 { + nvidia,pins = "lcd_dc0_pn6"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + hdmi_int_pn7 { + nvidia,pins = "hdmi_int_pn7"; + nvidia,function = "hdmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_data7_po0 { + nvidia,pins = "ulpi_data7_po0"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_data0_po1 { + nvidia,pins = "ulpi_data0_po1"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_data1_po2 { + nvidia,pins = "ulpi_data1_po2"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_data2_po3 { + nvidia,pins = "ulpi_data2_po3"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_data3_po4 { + nvidia,pins = "ulpi_data3_po4"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_data4_po5 { + nvidia,pins = "ulpi_data4_po5"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_data5_po6 { + nvidia,pins = "ulpi_data5_po6"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_data6_po7 { + nvidia,pins = "ulpi_data6_po7"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap3_fs_pp0 { + nvidia,pins = "dap3_fs_pp0"; + nvidia,function = "i2s2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap3_din_pp1 { + nvidia,pins = "dap3_din_pp1"; + nvidia,function = "i2s2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap3_dout_pp2 { + nvidia,pins = "dap3_dout_pp2"; + nvidia,function = "i2s2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap3_sclk_pp3 { + nvidia,pins = "dap3_sclk_pp3"; + nvidia,function = "i2s2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap4_fs_pp4 { + nvidia,pins = "dap4_fs_pp4"; + nvidia,function = "i2s3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap4_din_pp5 { + nvidia,pins = "dap4_din_pp5"; + nvidia,function = "i2s3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap4_dout_pp6 { + nvidia,pins = "dap4_dout_pp6"; + nvidia,function = "i2s3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap4_sclk_pp7 { + nvidia,pins = "dap4_sclk_pp7"; + nvidia,function = "i2s3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_col0_pq0 { + nvidia,pins = "kb_col0_pq0"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_col1_pq1 { + nvidia,pins = "kb_col1_pq1"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_col2_pq2 { + nvidia,pins = "kb_col2_pq2"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_col3_pq3 { + nvidia,pins = "kb_col3_pq3"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_col4_pq4 { + nvidia,pins = "kb_col4_pq4"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_col5_pq5 { + nvidia,pins = "kb_col5_pq5"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_col6_pq6 { + nvidia,pins = "kb_col6_pq6"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_col7_pq7 { + nvidia,pins = "kb_col7_pq7"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row0_pr0 { + nvidia,pins = "kb_row0_pr0"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row1_pr1 { + nvidia,pins = "kb_row1_pr1"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row2_pr2 { + nvidia,pins = "kb_row2_pr2"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row3_pr3 { + nvidia,pins = "kb_row3_pr3"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row4_pr4 { + nvidia,pins = "kb_row4_pr4"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row5_pr5 { + nvidia,pins = "kb_row5_pr5"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row6_pr6 { + nvidia,pins = "kb_row6_pr6"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row7_pr7 { + nvidia,pins = "kb_row7_pr7"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row8_ps0 { + nvidia,pins = "kb_row8_ps0"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row9_ps1 { + nvidia,pins = "kb_row9_ps1"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row10_ps2 { + nvidia,pins = "kb_row10_ps2"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row11_ps3 { + nvidia,pins = "kb_row11_ps3"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row12_ps4 { + nvidia,pins = "kb_row12_ps4"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row13_ps5 { + nvidia,pins = "kb_row13_ps5"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row14_ps6 { + nvidia,pins = "kb_row14_ps6"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row15_ps7 { + nvidia,pins = "kb_row15_ps7"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + vi_pclk_pt0 { + nvidia,pins = "vi_pclk_pt0"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + vi_mclk_pt1 { + nvidia,pins = "vi_mclk_pt1"; + nvidia,function = "vi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + vi_d10_pt2 { + nvidia,pins = "vi_d10_pt2"; + nvidia,function = "ddr"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + vi_d11_pt3 { + nvidia,pins = "vi_d11_pt3"; + nvidia,function = "ddr"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + vi_d0_pt4 { + nvidia,pins = "vi_d0_pt4"; + nvidia,function = "ddr"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gen2_i2c_scl_pt5 { + nvidia,pins = "gen2_i2c_scl_pt5"; + nvidia,function = "i2c2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + gen2_i2c_sda_pt6 { + nvidia,pins = "gen2_i2c_sda_pt6"; + nvidia,function = "i2c2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + sdmmc4_cmd_pt7 { + nvidia,pins = "sdmmc4_cmd_pt7"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-reset = ; + }; + pu0 { + nvidia,pins = "pu0"; + nvidia,function = "owr"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pu1 { + nvidia,pins = "pu1"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pu2 { + nvidia,pins = "pu2"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pu3 { + nvidia,pins = "pu3"; + nvidia,function = "pwm0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pu4 { + nvidia,pins = "pu4"; + nvidia,function = "pwm1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pu5 { + nvidia,pins = "pu5"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pu6 { + nvidia,pins = "pu6"; + nvidia,function = "pwm3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + jtag_rtck_pu7 { + nvidia,pins = "jtag_rtck_pu7"; + nvidia,function = "rtck"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pv0 { + nvidia,pins = "pv0"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pv1 { + nvidia,pins = "pv1"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pv2 { + nvidia,pins = "pv2"; + nvidia,function = "owr"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pv3 { + nvidia,pins = "pv3"; + nvidia,function = "clk_12m_out"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ddc_scl_pv4 { + nvidia,pins = "ddc_scl_pv4"; + nvidia,function = "i2c4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ddc_sda_pv5 { + nvidia,pins = "ddc_sda_pv5"; + nvidia,function = "i2c4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + crt_hsync_pv6 { + nvidia,pins = "crt_hsync_pv6"; + nvidia,function = "crt"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + crt_vsync_pv7 { + nvidia,pins = "crt_vsync_pv7"; + nvidia,function = "crt"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_cs1_n_pw0 { + nvidia,pins = "lcd_cs1_n_pw0"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_m1_pw1 { + nvidia,pins = "lcd_m1_pw1"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + spi2_cs1_n_pw2 { + nvidia,pins = "spi2_cs1_n_pw2"; + nvidia,function = "spi2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + clk1_out_pw4 { + nvidia,pins = "clk1_out_pw4"; + nvidia,function = "extperiph1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + clk2_out_pw5 { + nvidia,pins = "clk2_out_pw5"; + nvidia,function = "extperiph2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart3_txd_pw6 { + nvidia,pins = "uart3_txd_pw6"; + nvidia,function = "uartc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart3_rxd_pw7 { + nvidia,pins = "uart3_rxd_pw7"; + nvidia,function = "uartc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + spi2_sck_px2 { + nvidia,pins = "spi2_sck_px2"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + spi1_mosi_px4 { + nvidia,pins = "spi1_mosi_px4"; + nvidia,function = "spi1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + spi1_sck_px5 { + nvidia,pins = "spi1_sck_px5"; + nvidia,function = "spi1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + spi1_cs0_n_px6 { + nvidia,pins = "spi1_cs0_n_px6"; + nvidia,function = "spi1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + spi1_miso_px7 { + nvidia,pins = "spi1_miso_px7"; + nvidia,function = "spi1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_clk_py0 { + nvidia,pins = "ulpi_clk_py0"; + nvidia,function = "uartd"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_dir_py1 { + nvidia,pins = "ulpi_dir_py1"; + nvidia,function = "uartd"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_nxt_py2 { + nvidia,pins = "ulpi_nxt_py2"; + nvidia,function = "uartd"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_stp_py3 { + nvidia,pins = "ulpi_stp_py3"; + nvidia,function = "uartd"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc1_dat3_py4 { + nvidia,pins = "sdmmc1_dat3_py4"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc1_dat2_py5 { + nvidia,pins = "sdmmc1_dat2_py5"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc1_dat1_py6 { + nvidia,pins = "sdmmc1_dat1_py6"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc1_dat0_py7 { + nvidia,pins = "sdmmc1_dat0_py7"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc1_clk_pz0 { + nvidia,pins = "sdmmc1_clk_pz0"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc1_cmd_pz1 { + nvidia,pins = "sdmmc1_cmd_pz1"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_sdin_pz2 { + nvidia,pins = "lcd_sdin_pz2"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_wr_n_pz3 { + nvidia,pins = "lcd_wr_n_pz3"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_sck_pz4 { + nvidia,pins = "lcd_sck_pz4"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sys_clk_req_pz5 { + nvidia,pins = "sys_clk_req_pz5"; + nvidia,function = "sysclk"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pwr_i2c_scl_pz6 { + nvidia,pins = "pwr_i2c_scl_pz6"; + nvidia,function = "i2cpwr"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + pwr_i2c_sda_pz7 { + nvidia,pins = "pwr_i2c_sda_pz7"; + nvidia,function = "i2cpwr"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + sdmmc4_dat0_paa0 { + nvidia,pins = "sdmmc4_dat0_paa0"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-reset = ; + }; + sdmmc4_dat1_paa1 { + nvidia,pins = "sdmmc4_dat1_paa1"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-reset = ; + }; + sdmmc4_dat2_paa2 { + nvidia,pins = "sdmmc4_dat2_paa2"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-reset = ; + }; + sdmmc4_dat3_paa3 { + nvidia,pins = "sdmmc4_dat3_paa3"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-reset = ; + }; + sdmmc4_dat4_paa4 { + nvidia,pins = "sdmmc4_dat4_paa4"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-reset = ; + }; + sdmmc4_dat5_paa5 { + nvidia,pins = "sdmmc4_dat5_paa5"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-reset = ; + }; + sdmmc4_dat6_paa6 { + nvidia,pins = "sdmmc4_dat6_paa6"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-reset = ; + }; + sdmmc4_dat7_paa7 { + nvidia,pins = "sdmmc4_dat7_paa7"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-reset = ; + }; + pbb0 { + nvidia,pins = "pbb0"; + nvidia,function = "i2s4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + cam_i2c_scl_pbb1 { + nvidia,pins = "cam_i2c_scl_pbb1"; + nvidia,function = "i2c3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + cam_i2c_sda_pbb2 { + nvidia,pins = "cam_i2c_sda_pbb2"; + nvidia,function = "i2c3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + pbb3 { + nvidia,pins = "pbb3"; + nvidia,function = "vgp3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pbb4 { + nvidia,pins = "pbb4"; + nvidia,function = "vgp4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pbb5 { + nvidia,pins = "pbb5"; + nvidia,function = "vgp5"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pbb6 { + nvidia,pins = "pbb6"; + nvidia,function = "vgp6"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pbb7 { + nvidia,pins = "pbb7"; + nvidia,function = "i2s4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + cam_mclk_pcc0 { + nvidia,pins = "cam_mclk_pcc0"; + nvidia,function = "vi_alt3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pcc1 { + nvidia,pins = "pcc1"; + nvidia,function = "i2s4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pcc2 { + nvidia,pins = "pcc2"; + nvidia,function = "i2s4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc4_rst_n_pcc3 { + nvidia,pins = "sdmmc4_rst_n_pcc3"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-reset = ; + }; + sdmmc4_clk_pcc4 { + nvidia,pins = "sdmmc4_clk_pcc4"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-reset = ; + }; + clk2_req_pcc5 { + nvidia,pins = "clk2_req_pcc5"; + nvidia,function = "dap"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pex_l2_rst_n_pcc6 { + nvidia,pins = "pex_l2_rst_n_pcc6"; + nvidia,function = "pcie"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pex_l2_clkreq_n_pcc7 { + nvidia,pins = "pex_l2_clkreq_n_pcc7"; + nvidia,function = "pcie"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pex_l0_prsnt_n_pdd0 { + nvidia,pins = "pex_l0_prsnt_n_pdd0"; + nvidia,function = "pcie"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pex_l0_rst_n_pdd1 { + nvidia,pins = "pex_l0_rst_n_pdd1"; + nvidia,function = "pcie"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pex_l0_clkreq_n_pdd2 { + nvidia,pins = "pex_l0_clkreq_n_pdd2"; + nvidia,function = "pcie"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pex_wake_n_pdd3 { + nvidia,pins = "pex_wake_n_pdd3"; + nvidia,function = "pcie"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pex_l1_prsnt_n_pdd4 { + nvidia,pins = "pex_l1_prsnt_n_pdd4"; + nvidia,function = "pcie"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pex_l1_rst_n_pdd5 { + nvidia,pins = "pex_l1_rst_n_pdd5"; + nvidia,function = "pcie"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pex_l1_clkreq_n_pdd6 { + nvidia,pins = "pex_l1_clkreq_n_pdd6"; + nvidia,function = "pcie"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pex_l2_prsnt_n_pdd7 { + nvidia,pins = "pex_l2_prsnt_n_pdd7"; + nvidia,function = "pcie"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + clk3_out_pee0 { + nvidia,pins = "clk3_out_pee0"; + nvidia,function = "extperiph3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + clk3_req_pee1 { + nvidia,pins = "clk3_req_pee1"; + nvidia,function = "dev3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + clk1_req_pee2 { + nvidia,pins = "clk1_req_pee2"; + nvidia,function = "dap"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + hdmi_cec_pee3 { + nvidia,pins = "hdmi_cec_pee3"; + nvidia,function = "cec"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + owr { + nvidia,pins = "owr"; + nvidia,function = "owr"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + drive_groups { + nvidia,pins = "drive_gma", + "drive_gmb", + "drive_gmc", + "drive_gmd"; + nvidia,pull-down-strength = <9>; + nvidia,pull-up-strength = <9>; + nvidia,slew-rate-rising = ; + nvidia,slew-rate-falling = ; + }; +}; -- cgit v1.2.3-59-g8ed1b From 94f13b9ca38643e1a1acf3b546d70dea24a17981 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Wed, 4 Nov 2020 17:12:44 +0300 Subject: ARM: tegra: acer-a500: Correct thermal zone names Rename thermal zones in order fix dt_binding_check warning telling that names do not match the expected pattern. Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra20-acer-a500-picasso.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts b/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts index a0b829738e8f..372cc1b17eaf 100644 --- a/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts +++ b/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts @@ -1020,14 +1020,14 @@ }; thermal-zones { - nct1008-local { + skin-thermal { polling-delay-passive = <1000>; /* milliseconds */ polling-delay = <0>; /* milliseconds */ thermal-sensors = <&nct1008 0>; }; - nct1008-remote { + cpu-thermal { polling-delay-passive = <1000>; /* milliseconds */ polling-delay = <5000>; /* milliseconds */ -- cgit v1.2.3-59-g8ed1b From 5b0455f82b791de3b76bfd220f63dae1ea6b2747 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Wed, 4 Nov 2020 17:12:45 +0300 Subject: ARM: tegra: acer-a500: Add power-supply to lvds-encoder node The lvds-encoder binding now supports power-supply property, let's specify it in the device-tree for completeness. Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra20-acer-a500-picasso.dts | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts b/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts index 372cc1b17eaf..dd6fb134ee39 100644 --- a/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts +++ b/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts @@ -907,6 +907,7 @@ compatible = "ti,sn75lvds83", "lvds-encoder"; powerdown-gpios = <&gpio TEGRA_GPIO(B, 2) GPIO_ACTIVE_LOW>; + power-supply = <&vdd_3v3_sys>; ports { #address-cells = <1>; -- cgit v1.2.3-59-g8ed1b From 8857779a9faba5789ad30ca1f944a17aaa747056 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Wed, 4 Nov 2020 17:12:46 +0300 Subject: ARM: tegra: nexus7: Correct thermal zone names Rename thermal zones in order fix dt_binding_check warning telling that names do not match the expected pattern. Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi index 88ca03f57b3b..fa6bbec7cbc4 100644 --- a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi +++ b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi @@ -1240,14 +1240,14 @@ }; thermal-zones { - nct72-local { + skin-thermal { polling-delay-passive = <1000>; /* milliseconds */ polling-delay = <0>; /* milliseconds */ thermal-sensors = <&nct72 0>; }; - nct72-remote { + cpu-thermal { polling-delay-passive = <1000>; /* milliseconds */ polling-delay = <5000>; /* milliseconds */ -- cgit v1.2.3-59-g8ed1b From 2b22393b27670b45a2c870bce3df6579efd9a86a Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Wed, 4 Nov 2020 17:12:47 +0300 Subject: ARM: tegra: nexus7: Improve CPU passive-cooling threshold The current CPU thermal limit is a bit inappropriate for Nexus 7 once device is getting used on a daily bases. For example, currently it's may be impossible to watch a hardware accelerated 720p video without hitting a severe CPU throttling, which ruins user experience. This patch improves the thermal throttling thresholds. In my experience setting CPU thermal threshold to 57C provides the most reasonable result, where device is a bit warm under constant load and not getting overly hot, in the same time performance is okay. Let's bump the passive-cooling threshold from 50C to 57C and also lower the thermal hysteresis to 0.2C in order to make throttling more reactive. Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi index fa6bbec7cbc4..8d49860b135b 100644 --- a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi +++ b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi @@ -1255,9 +1255,9 @@ trips { trip0: cpu-alert0 { - /* start throttling at 50C */ - temperature = <50000>; - hysteresis = <3000>; + /* throttle at 57C until temperature drops to 56.8C */ + temperature = <57000>; + hysteresis = <200>; type = "passive"; }; -- cgit v1.2.3-59-g8ed1b From 810719453c623e6393cb0b1ca4e41efa08002c9d Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Wed, 4 Nov 2020 17:12:48 +0300 Subject: ARM: tegra: nexus7: Add power-supply to lvds-encoder node The lvds-encoder binding now supports power-supply property, let's specify it in the device-tree for completeness. Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi index 8d49860b135b..f8a531350998 100644 --- a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi +++ b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi @@ -1145,6 +1145,7 @@ compatible = "ti,sn75lvds83", "lvds-encoder"; powerdown-gpios = <&gpio TEGRA_GPIO(N, 6) GPIO_ACTIVE_LOW>; + power-supply = <&vdd_3v3_sys>; ports { #address-cells = <1>; -- cgit v1.2.3-59-g8ed1b From b8ae17150696a3f0f40c91d61103b74884e7ba0a Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Wed, 4 Nov 2020 17:12:49 +0300 Subject: ARM: tegra: nexus7: Rename gpio-hog nodes Devicetree schema now requires gpio-hog nodes to have a certain naming pattern, like a -hog suffix. This patch fixes dtbs_check warnings about the names. Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi | 4 ++-- arch/arm/boot/dts/tegra30-asus-nexus7-grouper-maxim-pmic.dtsi | 2 +- arch/arm/boot/dts/tegra30-asus-nexus7-tilapia.dtsi | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi index f8a531350998..8def1d2e34f9 100644 --- a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi +++ b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi @@ -75,7 +75,7 @@ }; gpio@6000d000 { - init-mode { + init-mode-hog { gpio-hog; gpios = , , @@ -83,7 +83,7 @@ output-low; }; - init-low-power-mode { + init-low-power-mode-hog { gpio-hog; gpios = ; input; diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-maxim-pmic.dtsi b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-maxim-pmic.dtsi index b25b3fa90ac6..17b6682ffce8 100644 --- a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-maxim-pmic.dtsi +++ b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-maxim-pmic.dtsi @@ -29,7 +29,7 @@ }; }; - cpu-pwr-req { + cpu-pwr-req-hog { gpio-hog; gpios = <6 GPIO_ACTIVE_HIGH>; input; diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-tilapia.dtsi b/arch/arm/boot/dts/tegra30-asus-nexus7-tilapia.dtsi index e3da89f1941a..a681ad51fddd 100644 --- a/arch/arm/boot/dts/tegra30-asus-nexus7-tilapia.dtsi +++ b/arch/arm/boot/dts/tegra30-asus-nexus7-tilapia.dtsi @@ -23,7 +23,7 @@ }; gpio@6000d000 { - init-mode-3g { + init-mode-3g-hog { gpio-hog; gpios = , , -- cgit v1.2.3-59-g8ed1b From a21f18a993c56566db94ba836684bc32c070a82c Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Wed, 4 Nov 2020 17:12:51 +0300 Subject: ARM: tegra: nexus7: Use panel-lvds as the only panel compatible Depending on a driver probe order, panel-simple driver may probe first, which results in this error: panel-simple display-panel: Reject override mode: panel has a fixed mode We don't want to use panel-simple anyways because customized timings are preferred for Nexus 7, hence remove the panel-simple compatibles from the panel node. Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi index 8def1d2e34f9..ac1c1a63eb0e 100644 --- a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi +++ b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi @@ -1073,8 +1073,16 @@ }; display-panel { - compatible = "hydis,hv070wx2-1e0", "chunghwa,claa070wp03xg", - "panel-lvds"; + /* + * Nexus 7 supports two compatible panel models: + * + * 1. hydis,hv070wx2-1e0 + * 2. chunghwa,claa070wp03xg + * + * We want to use timing which is optimized for Nexus 7, + * hence we need to customize the timing. + */ + compatible = "panel-lvds"; power-supply = <&vdd_pnl>; backlight = <&backlight>; -- cgit v1.2.3-59-g8ed1b From bd7cd7e05a42491469ca19861da44abc3168cf5f Mon Sep 17 00:00:00 2001 From: Jon Hunter Date: Wed, 11 Nov 2020 10:38:47 +0000 Subject: ARM: tegra: Populate OPP table for Tegra20 Ventana Commit 9ce274630495 ("cpufreq: tegra20: Use generic cpufreq-dt driver (Tegra30 supported now)") update the Tegra20 CPUFREQ driver to use the generic CPUFREQ device-tree driver. Since this change CPUFREQ support on the Tegra20 Ventana platform has been broken because the necessary device-tree nodes with the operating point information are not populated for this platform. Fix this by updating device-tree for Venata to include the operating point informration for Tegra20. Fixes: 9ce274630495 ("cpufreq: tegra20: Use generic cpufreq-dt driver (Tegra30 supported now)") Cc: stable@vger.kernel.org Signed-off-by: Jon Hunter Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra20-ventana.dts | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/tegra20-ventana.dts b/arch/arm/boot/dts/tegra20-ventana.dts index b158771ac0b7..055334ae3d28 100644 --- a/arch/arm/boot/dts/tegra20-ventana.dts +++ b/arch/arm/boot/dts/tegra20-ventana.dts @@ -3,6 +3,7 @@ #include #include "tegra20.dtsi" +#include "tegra20-cpu-opp.dtsi" / { model = "NVIDIA Tegra20 Ventana evaluation board"; @@ -592,6 +593,16 @@ #clock-cells = <0>; }; + cpus { + cpu0: cpu@0 { + operating-points-v2 = <&cpu0_opp_table>; + }; + + cpu@1 { + operating-points-v2 = <&cpu0_opp_table>; + }; + }; + gpio-keys { compatible = "gpio-keys"; -- cgit v1.2.3-59-g8ed1b From 37ac8c4c04c9441fe05f4215b330775b00df7a99 Mon Sep 17 00:00:00 2001 From: Nicolas Chauvet Date: Sun, 27 Sep 2020 17:09:51 +0200 Subject: ARM: tegra: Add missing gpu-throt-level to Tegra124 soctherm On Jetson TK1 the following message can be seen: tegra_soctherm 700e2000.thermal-sensor: throttle-cfg: heavy: no throt prop or invalid prop This patch will fix the invalid prop issue according to the binding. Signed-off-by: Nicolas Chauvet Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra124.dtsi | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi index 64f488ba1e72..a0fa5821a232 100644 --- a/arch/arm/boot/dts/tegra124.dtsi +++ b/arch/arm/boot/dts/tegra124.dtsi @@ -910,6 +910,7 @@ throttle_heavy: heavy { nvidia,priority = <100>; nvidia,cpu-throt-percent = <85>; + nvidia,gpu-throt-level = ; #cooling-cells = <2>; }; -- cgit v1.2.3-59-g8ed1b From 252cc72af6a2017dae340b4136124d3e625e4e0f Mon Sep 17 00:00:00 2001 From: Nicolas Chauvet Date: Sun, 27 Sep 2020 17:09:52 +0200 Subject: ARM: tegra: Add missing hot temperatures to Tegra124 thermal-zones According to dmesg, thermal-zones for mem and cpu are missing hot temperatures properties. throttrip: pll: missing hot temperature ... throttrip: mem: missing hot temperature ... Adding them will clear the messages. Signed-off-by: Nicolas Chauvet Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra124.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi index a0fa5821a232..c71d597ace01 100644 --- a/arch/arm/boot/dts/tegra124.dtsi +++ b/arch/arm/boot/dts/tegra124.dtsi @@ -1248,6 +1248,11 @@ hysteresis = <0>; type = "critical"; }; + mem-throttle-trip { + temperature = <99000>; + hysteresis = <1000>; + type = "hot"; + }; }; cooling-maps { @@ -1299,6 +1304,11 @@ hysteresis = <0>; type = "critical"; }; + pllx-throttle-trip { + temperature = <99000>; + hysteresis = <1000>; + type = "hot"; + }; }; cooling-maps { -- cgit v1.2.3-59-g8ed1b From 17401ce98ec6105db8e351c12735b6cc20d73d7e Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 20 Nov 2020 16:18:08 +0100 Subject: ARM: tegra: Hook up edp interrupt on Tegra124 SOCTHERM For some reason this was never hooked up. Do it now so that over-current interrupts can be logged. Reported-by: Nicolas Chauvet Suggested-by: Jon Hunter Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra124.dtsi | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi index c71d597ace01..27fb6a49118f 100644 --- a/arch/arm/boot/dts/tegra124.dtsi +++ b/arch/arm/boot/dts/tegra124.dtsi @@ -898,7 +898,9 @@ reg = <0x0 0x700e2000 0x0 0x600>, /* SOC_THERM reg_base */ <0x0 0x60006000 0x0 0x400>; /* CAR reg_base */ reg-names = "soctherm-reg", "car-reg"; - interrupts = ; + interrupts = , + ; + interrupt-names = "thermal", "edp"; clocks = <&tegra_car TEGRA124_CLK_TSENSOR>, <&tegra_car TEGRA124_CLK_SOC_THERM>; clock-names = "tsensor", "soctherm"; -- cgit v1.2.3-59-g8ed1b From 6fb123f1f5a42136161b7782d9635a684f3036d2 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 20 Nov 2020 21:27:12 +0100 Subject: ARM: tegra: Properly align clocks for SOCTHERM Entries on subsequent lines should be aligned with the entry on the first line. Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra124.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi index 27fb6a49118f..d7001b27c3e6 100644 --- a/arch/arm/boot/dts/tegra124.dtsi +++ b/arch/arm/boot/dts/tegra124.dtsi @@ -902,7 +902,7 @@ ; interrupt-names = "thermal", "edp"; clocks = <&tegra_car TEGRA124_CLK_TSENSOR>, - <&tegra_car TEGRA124_CLK_SOC_THERM>; + <&tegra_car TEGRA124_CLK_SOC_THERM>; clock-names = "tsensor", "soctherm"; resets = <&tegra_car 78>; reset-names = "soctherm"; -- cgit v1.2.3-59-g8ed1b From 8b809ba66c29abb0203d43118c31027e43e43648 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Mon, 23 Nov 2020 03:27:16 +0300 Subject: ARM: tegra: Correct EMC registers size in Tegra20 device-tree Fix the size of Tegra20 EMC registers, which should be twice bigger. Acked-by: Krzysztof Kozlowski Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra20.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index 72a4211a618f..9347f7789245 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi @@ -634,7 +634,7 @@ memory-controller@7000f400 { compatible = "nvidia,tegra20-emc"; - reg = <0x7000f400 0x200>; + reg = <0x7000f400 0x400>; interrupts = ; clocks = <&tegra_car TEGRA20_CLK_EMC>; #address-cells = <1>; -- cgit v1.2.3-59-g8ed1b From dd2a21d0930b3f5b8d5643c8d41008f8f2557d73 Mon Sep 17 00:00:00 2001 From: Sowjanya Komatineni Date: Mon, 23 Nov 2020 12:17:20 -0800 Subject: ARM: tegra: Change order of SATA resets for Tegra124 Tegra AHCI dt-binding doc is converted from text based to yaml based. dtbs_check valdiation strictly follows reset-names order specified in yaml dt-binding. Tegra124 thru Tegra210 has 3 resets sata, sata-oob and sata-cold. Tegra186 has 2 resets sata and sata-cold. This patch changes order of SATA resets to maintain proper resets order for commonly available resets across Tegra124 thru Tegra186 for dtbs_check to pass. Signed-off-by: Sowjanya Komatineni Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra124.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi index d7001b27c3e6..e61e68a0bb58 100644 --- a/arch/arm/boot/dts/tegra124.dtsi +++ b/arch/arm/boot/dts/tegra124.dtsi @@ -650,9 +650,9 @@ <&tegra_car TEGRA124_CLK_PLL_E>; clock-names = "sata", "sata-oob", "cml1", "pll_e"; resets = <&tegra_car 124>, - <&tegra_car 123>, - <&tegra_car 129>; - reset-names = "sata", "sata-oob", "sata-cold"; + <&tegra_car 129>, + <&tegra_car 123>; + reset-names = "sata", "sata-cold", "sata-oob"; status = "disabled"; }; -- cgit v1.2.3-59-g8ed1b From d3e815eaab582398ac2257d73399c8cf741bf64b Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Mon, 16 Nov 2020 22:48:27 +0300 Subject: ARM: tegra: acer-a500: Add Embedded Controller This patch adds device-tree node for the Embedded Controller which is found on the Picasso board. The Embedded Controller itself is ENE KB930, it provides functions like battery-gauge/LED/GPIO/etc and it uses firmware that is specifically customized for the Acer A500 device. Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra20-acer-a500-picasso.dts | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts b/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts index dd6fb134ee39..9dafd3d57bf7 100644 --- a/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts +++ b/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts @@ -512,6 +512,16 @@ reg = <1>; #address-cells = <1>; #size-cells = <0>; + + embedded-controller@58 { + compatible = "acer,a500-iconia-ec", "ene,kb930"; + reg = <0x58>; + + system-power-controller; + + monitored-battery = <&bat1010>; + power-supplies = <&mains>; + }; }; }; @@ -794,6 +804,13 @@ default-brightness-level = <20>; }; + bat1010: battery-2s1p { + compatible = "simple-battery"; + charge-full-design-microamp-hours = <3260000>; + energy-full-design-microwatt-hours = <24000000>; + operating-range-celsius = <0 40>; + }; + /* PMIC has a built-in 32KHz oscillator which is used by PMC */ clk32k_in: clock@0 { compatible = "fixed-clock"; -- cgit v1.2.3-59-g8ed1b From 30b81e77a051e50c1b8d5f3bb697e915231d89a8 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Mon, 23 Nov 2020 03:27:17 +0300 Subject: ARM: tegra: Add interconnect properties to Tegra20 device-tree Add interconnect properties to the Memory Controller, External Memory Controller and the Display Controller nodes in order to describe hardware interconnection. Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra20.dtsi | 26 +++++++++++++++++++++++++- 1 file changed, 25 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index 9347f7789245..2e1304493f7d 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi @@ -111,6 +111,17 @@ nvidia,head = <0>; + interconnects = <&mc TEGRA20_MC_DISPLAY0A &emc>, + <&mc TEGRA20_MC_DISPLAY0B &emc>, + <&mc TEGRA20_MC_DISPLAY1B &emc>, + <&mc TEGRA20_MC_DISPLAY0C &emc>, + <&mc TEGRA20_MC_DISPLAYHC &emc>; + interconnect-names = "wina", + "winb", + "winb-vfilter", + "winc", + "cursor"; + rgb { status = "disabled"; }; @@ -128,6 +139,17 @@ nvidia,head = <1>; + interconnects = <&mc TEGRA20_MC_DISPLAY0AB &emc>, + <&mc TEGRA20_MC_DISPLAY0BB &emc>, + <&mc TEGRA20_MC_DISPLAY1BB &emc>, + <&mc TEGRA20_MC_DISPLAY0CB &emc>, + <&mc TEGRA20_MC_DISPLAYHCB &emc>; + interconnect-names = "wina", + "winb", + "winb-vfilter", + "winc", + "cursor"; + rgb { status = "disabled"; }; @@ -630,15 +652,17 @@ interrupts = ; #reset-cells = <1>; #iommu-cells = <0>; + #interconnect-cells = <1>; }; - memory-controller@7000f400 { + emc: memory-controller@7000f400 { compatible = "nvidia,tegra20-emc"; reg = <0x7000f400 0x400>; interrupts = ; clocks = <&tegra_car TEGRA20_CLK_EMC>; #address-cells = <1>; #size-cells = <0>; + #interconnect-cells = <0>; }; fuse@7000f800 { -- cgit v1.2.3-59-g8ed1b From 69ea8fa77f1c0ce2a726ab283db2472d8a4c3cb6 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Mon, 23 Nov 2020 03:27:18 +0300 Subject: ARM: tegra: Add interconnect properties to Tegra30 device-tree Add interconnect properties to the Memory Controller, External Memory Controller and the Display Controller nodes in order to describe hardware interconnection. Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra30.dtsi | 27 ++++++++++++++++++++++++++- 1 file changed, 26 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi index aeae8c092d41..2caf6cc6f4b1 100644 --- a/arch/arm/boot/dts/tegra30.dtsi +++ b/arch/arm/boot/dts/tegra30.dtsi @@ -210,6 +210,17 @@ nvidia,head = <0>; + interconnects = <&mc TEGRA30_MC_DISPLAY0A &emc>, + <&mc TEGRA30_MC_DISPLAY0B &emc>, + <&mc TEGRA30_MC_DISPLAY1B &emc>, + <&mc TEGRA30_MC_DISPLAY0C &emc>, + <&mc TEGRA30_MC_DISPLAYHC &emc>; + interconnect-names = "wina", + "winb", + "winb-vfilter", + "winc", + "cursor"; + rgb { status = "disabled"; }; @@ -229,6 +240,17 @@ nvidia,head = <1>; + interconnects = <&mc TEGRA30_MC_DISPLAY0AB &emc>, + <&mc TEGRA30_MC_DISPLAY0BB &emc>, + <&mc TEGRA30_MC_DISPLAY1BB &emc>, + <&mc TEGRA30_MC_DISPLAY0CB &emc>, + <&mc TEGRA30_MC_DISPLAYHCB &emc>; + interconnect-names = "wina", + "winb", + "winb-vfilter", + "winc", + "cursor"; + rgb { status = "disabled"; }; @@ -748,15 +770,18 @@ #iommu-cells = <1>; #reset-cells = <1>; + #interconnect-cells = <1>; }; - memory-controller@7000f400 { + emc: memory-controller@7000f400 { compatible = "nvidia,tegra30-emc"; reg = <0x7000f400 0x400>; interrupts = ; clocks = <&tegra_car TEGRA30_CLK_EMC>; nvidia,memory-controller = <&mc>; + + #interconnect-cells = <0>; }; fuse@7000f800 { -- cgit v1.2.3-59-g8ed1b From 5cf0cdbd55892d96168016d097e5657eb9af4b1f Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Mon, 23 Nov 2020 03:27:19 +0300 Subject: ARM: tegra: Add interconnect properties to Tegra124 device-tree Add interconnect properties to the Memory Controller, External Memory Controller and the Display Controller nodes in order to describe hardware interconnection. Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra124.dtsi | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi index e61e68a0bb58..bf621f12ffb7 100644 --- a/arch/arm/boot/dts/tegra124.dtsi +++ b/arch/arm/boot/dts/tegra124.dtsi @@ -113,6 +113,19 @@ iommus = <&mc TEGRA_SWGROUP_DC>; nvidia,head = <0>; + + interconnects = <&mc TEGRA124_MC_DISPLAY0A &emc>, + <&mc TEGRA124_MC_DISPLAY0B &emc>, + <&mc TEGRA124_MC_DISPLAY0C &emc>, + <&mc TEGRA124_MC_DISPLAYHC &emc>, + <&mc TEGRA124_MC_DISPLAYD &emc>, + <&mc TEGRA124_MC_DISPLAYT &emc>; + interconnect-names = "wina", + "winb", + "winc", + "cursor", + "wind", + "wint"; }; dc@54240000 { @@ -127,6 +140,15 @@ iommus = <&mc TEGRA_SWGROUP_DCB>; nvidia,head = <1>; + + interconnects = <&mc TEGRA124_MC_DISPLAY0AB &emc>, + <&mc TEGRA124_MC_DISPLAY0BB &emc>, + <&mc TEGRA124_MC_DISPLAY0CB &emc>, + <&mc TEGRA124_MC_DISPLAYHCB &emc>; + interconnect-names = "wina", + "winb", + "winc", + "cursor"; }; hdmi: hdmi@54280000 { @@ -628,6 +650,7 @@ #iommu-cells = <1>; #reset-cells = <1>; + #interconnect-cells = <1>; }; emc: external-memory-controller@7001b000 { @@ -637,6 +660,8 @@ clock-names = "emc"; nvidia,memory-controller = <&mc>; + + #interconnect-cells = <0>; }; sata@70020000 { -- cgit v1.2.3-59-g8ed1b From b97967d7d5b73503c9e19557895281af731cdc6a Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Mon, 23 Nov 2020 03:27:20 +0300 Subject: ARM: tegra: Add nvidia,memory-controller phandle to Tegra20 EMC device-tree Add nvidia,memory-controller to the Tegra20 External Memory Controller node. This allows to perform a direct lookup of the Memory Controller instead of walking up the whole tree. This puts Tegra20 device-tree on par with Tegra30+. Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra20.dtsi | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index 2e1304493f7d..8f8ad81916e7 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi @@ -663,6 +663,8 @@ #address-cells = <1>; #size-cells = <0>; #interconnect-cells = <0>; + + nvidia,memory-controller = <&mc>; }; fuse@7000f800 { -- cgit v1.2.3-59-g8ed1b From f5204ac47b298a94eadf8b6c61b534bd9abe2e41 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Mon, 23 Nov 2020 03:27:21 +0300 Subject: ARM: tegra: Add EMC OPP properties to Tegra20 device-trees Add EMC OPP DVFS tables and update board device-trees by removing unsupported OPPs. Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra20-acer-a500-picasso.dts | 5 ++ arch/arm/boot/dts/tegra20-colibri.dtsi | 4 + arch/arm/boot/dts/tegra20-paz00.dts | 4 + arch/arm/boot/dts/tegra20-peripherals-opp.dtsi | 109 ++++++++++++++++++++++++ arch/arm/boot/dts/tegra20.dtsi | 3 + 5 files changed, 125 insertions(+) create mode 100644 arch/arm/boot/dts/tegra20-peripherals-opp.dtsi (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts b/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts index 9dafd3d57bf7..3287ff8fe4aa 100644 --- a/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts +++ b/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts @@ -1468,3 +1468,8 @@ }; }; }; + +&emc_icc_dvfs_opp_table { + /delete-node/ opp@666000000; + /delete-node/ opp@760000000; +}; diff --git a/arch/arm/boot/dts/tegra20-colibri.dtsi b/arch/arm/boot/dts/tegra20-colibri.dtsi index 6162d193e12c..585a5b441cf6 100644 --- a/arch/arm/boot/dts/tegra20-colibri.dtsi +++ b/arch/arm/boot/dts/tegra20-colibri.dtsi @@ -742,6 +742,10 @@ }; }; +&emc_icc_dvfs_opp_table { + /delete-node/ opp@760000000; +}; + &gpio { lan-reset-n { gpio-hog; diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts index ada2bed8b1b5..7e49112cd9a1 100644 --- a/arch/arm/boot/dts/tegra20-paz00.dts +++ b/arch/arm/boot/dts/tegra20-paz00.dts @@ -662,3 +662,7 @@ }; }; }; + +&emc_icc_dvfs_opp_table { + /delete-node/ opp@760000000; +}; diff --git a/arch/arm/boot/dts/tegra20-peripherals-opp.dtsi b/arch/arm/boot/dts/tegra20-peripherals-opp.dtsi new file mode 100644 index 000000000000..b84afecea154 --- /dev/null +++ b/arch/arm/boot/dts/tegra20-peripherals-opp.dtsi @@ -0,0 +1,109 @@ +// SPDX-License-Identifier: GPL-2.0 + +/ { + emc_icc_dvfs_opp_table: emc-dvfs-opp-table { + compatible = "operating-points-v2"; + + opp@36000000 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <36000000>; + opp-supported-hw = <0x000F>; + }; + + opp@47500000 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <47500000>; + opp-supported-hw = <0x000F>; + }; + + opp@50000000 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <50000000>; + opp-supported-hw = <0x000F>; + }; + + opp@54000000 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <54000000>; + opp-supported-hw = <0x000F>; + }; + + opp@57000000 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <57000000>; + opp-supported-hw = <0x000F>; + }; + + opp@100000000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <100000000>; + opp-supported-hw = <0x000F>; + }; + + opp@108000000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <108000000>; + opp-supported-hw = <0x000F>; + }; + + opp@126666000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <126666000>; + opp-supported-hw = <0x000F>; + }; + + opp@150000000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <150000000>; + opp-supported-hw = <0x000F>; + }; + + opp@190000000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <190000000>; + opp-supported-hw = <0x000F>; + }; + + opp@216000000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <216000000>; + opp-supported-hw = <0x000F>; + }; + + opp@300000000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <300000000>; + opp-supported-hw = <0x000F>; + }; + + opp@333000000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <333000000>; + opp-supported-hw = <0x000F>; + }; + + opp@380000000 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <380000000>; + opp-supported-hw = <0x000F>; + }; + + opp@600000000 { + opp-microvolt = <1200000 1200000 1300000>; + opp-hz = /bits/ 64 <600000000>; + opp-supported-hw = <0x000F>; + }; + + opp@666000000 { + opp-microvolt = <1200000 1200000 1300000>; + opp-hz = /bits/ 64 <666000000>; + opp-supported-hw = <0x000F>; + }; + + opp@760000000 { + opp-microvolt = <1300000 1300000 1300000>; + opp-hz = /bits/ 64 <760000000>; + opp-supported-hw = <0x000F>; + }; + }; +}; diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index 8f8ad81916e7..6ce498178105 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi @@ -6,6 +6,8 @@ #include #include +#include "tegra20-peripherals-opp.dtsi" + / { compatible = "nvidia,tegra20"; interrupt-parent = <&lic>; @@ -664,6 +666,7 @@ #size-cells = <0>; #interconnect-cells = <0>; + operating-points-v2 = <&emc_icc_dvfs_opp_table>; nvidia,memory-controller = <&mc>; }; -- cgit v1.2.3-59-g8ed1b From 881741fa447d56751fe6f5af66a5c3cae4140903 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Mon, 23 Nov 2020 03:27:22 +0300 Subject: ARM: tegra: Add EMC OPP and ICC properties to Tegra30 EMC and ACTMON device-tree nodes Add EMC OPP tables and interconnect paths that will be used for dynamic memory bandwidth scaling based on memory utilization statistics. Update board device-trees by removing unsupported EMC OPPs. Note that ACTMON watches all memory interconnect paths, but we use a single CPU-READ interconnect path for driving memory bandwidth, for simplicity. Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- ...tegra30-asus-nexus7-grouper-memory-timings.dtsi | 12 + arch/arm/boot/dts/tegra30-ouya.dts | 8 + arch/arm/boot/dts/tegra30-peripherals-opp.dtsi | 383 +++++++++++++++++++++ arch/arm/boot/dts/tegra30.dtsi | 6 + 4 files changed, 409 insertions(+) create mode 100644 arch/arm/boot/dts/tegra30-peripherals-opp.dtsi (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-memory-timings.dtsi b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-memory-timings.dtsi index bc0f6f29b956..bcff0997ee51 100644 --- a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-memory-timings.dtsi +++ b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-memory-timings.dtsi @@ -1563,3 +1563,15 @@ }; }; }; + +&emc_icc_dvfs_opp_table { + /delete-node/ opp@750000000,1300; + /delete-node/ opp@800000000,1300; + /delete-node/ opp@900000000,1350; +}; + +&emc_bw_dfs_opp_table { + /delete-node/ opp@750000000; + /delete-node/ opp@800000000; + /delete-node/ opp@900000000; +}; diff --git a/arch/arm/boot/dts/tegra30-ouya.dts b/arch/arm/boot/dts/tegra30-ouya.dts index a5f16ad6c8f4..74da1360d297 100644 --- a/arch/arm/boot/dts/tegra30-ouya.dts +++ b/arch/arm/boot/dts/tegra30-ouya.dts @@ -4509,3 +4509,11 @@ nvidia,slew-rate-falling = ; }; }; + +&emc_icc_dvfs_opp_table { + /delete-node/ opp@900000000,1350; +}; + +&emc_bw_dfs_opp_table { + /delete-node/ opp@900000000; +}; diff --git a/arch/arm/boot/dts/tegra30-peripherals-opp.dtsi b/arch/arm/boot/dts/tegra30-peripherals-opp.dtsi new file mode 100644 index 000000000000..cbe84d25e726 --- /dev/null +++ b/arch/arm/boot/dts/tegra30-peripherals-opp.dtsi @@ -0,0 +1,383 @@ +// SPDX-License-Identifier: GPL-2.0 + +/ { + emc_icc_dvfs_opp_table: emc-dvfs-opp-table { + compatible = "operating-points-v2"; + + opp@12750000,950 { + opp-microvolt = <950000 950000 1350000>; + opp-hz = /bits/ 64 <12750000>; + opp-supported-hw = <0x0006>; + }; + + opp@12750000,1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <12750000>; + opp-supported-hw = <0x0001>; + }; + + opp@12750000,1250 { + opp-microvolt = <1250000 1250000 1350000>; + opp-hz = /bits/ 64 <12750000>; + opp-supported-hw = <0x0008>; + }; + + opp@25500000,950 { + opp-microvolt = <950000 950000 1350000>; + opp-hz = /bits/ 64 <25500000>; + opp-supported-hw = <0x0006>; + }; + + opp@25500000,1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <25500000>; + opp-supported-hw = <0x0001>; + }; + + opp@25500000,1250 { + opp-microvolt = <1250000 1250000 1350000>; + opp-hz = /bits/ 64 <25500000>; + opp-supported-hw = <0x0008>; + }; + + opp@27000000,950 { + opp-microvolt = <950000 950000 1350000>; + opp-hz = /bits/ 64 <27000000>; + opp-supported-hw = <0x0006>; + }; + + opp@27000000,1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <27000000>; + opp-supported-hw = <0x0001>; + }; + + opp@27000000,1250 { + opp-microvolt = <1250000 1250000 1350000>; + opp-hz = /bits/ 64 <27000000>; + opp-supported-hw = <0x0008>; + }; + + opp@51000000,950 { + opp-microvolt = <950000 950000 1350000>; + opp-hz = /bits/ 64 <51000000>; + opp-supported-hw = <0x0006>; + }; + + opp@51000000,1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <51000000>; + opp-supported-hw = <0x0001>; + }; + + opp@51000000,1250 { + opp-microvolt = <1250000 1250000 1350000>; + opp-hz = /bits/ 64 <51000000>; + opp-supported-hw = <0x0008>; + }; + + opp@54000000,950 { + opp-microvolt = <950000 950000 1350000>; + opp-hz = /bits/ 64 <54000000>; + opp-supported-hw = <0x0006>; + }; + + opp@54000000,1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <54000000>; + opp-supported-hw = <0x0001>; + }; + + opp@54000000,1250 { + opp-microvolt = <1250000 1250000 1350000>; + opp-hz = /bits/ 64 <54000000>; + opp-supported-hw = <0x0008>; + }; + + opp@102000000,950 { + opp-microvolt = <950000 950000 1350000>; + opp-hz = /bits/ 64 <102000000>; + opp-supported-hw = <0x0006>; + }; + + opp@102000000,1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <102000000>; + opp-supported-hw = <0x0001>; + }; + + opp@102000000,1250 { + opp-microvolt = <1250000 1250000 1350000>; + opp-hz = /bits/ 64 <102000000>; + opp-supported-hw = <0x0008>; + }; + + opp@108000000,1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <108000000>; + opp-supported-hw = <0x0007>; + }; + + opp@108000000,1250 { + opp-microvolt = <1250000 1250000 1350000>; + opp-hz = /bits/ 64 <108000000>; + opp-supported-hw = <0x0008>; + }; + + opp@204000000,1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <204000000>; + opp-supported-hw = <0x0007>; + }; + + opp@204000000,1250 { + opp-microvolt = <1250000 1250000 1350000>; + opp-hz = /bits/ 64 <204000000>; + opp-supported-hw = <0x0008>; + }; + + opp@333500000,1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <333500000>; + opp-supported-hw = <0x0006>; + }; + + opp@333500000,1200 { + opp-microvolt = <1200000 1200000 1350000>; + opp-hz = /bits/ 64 <333500000>; + opp-supported-hw = <0x0001>; + }; + + opp@333500000,1250 { + opp-microvolt = <1250000 1250000 1350000>; + opp-hz = /bits/ 64 <333500000>; + opp-supported-hw = <0x0008>; + }; + + opp@375000000,1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <375000000>; + opp-supported-hw = <0x0006>; + }; + + opp@375000000,1200 { + opp-microvolt = <1200000 1200000 1350000>; + opp-hz = /bits/ 64 <375000000>; + opp-supported-hw = <0x0001>; + }; + + opp@375000000,1250 { + opp-microvolt = <1250000 1250000 1350000>; + opp-hz = /bits/ 64 <375000000>; + opp-supported-hw = <0x0008>; + }; + + opp@400000000,1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <400000000>; + opp-supported-hw = <0x0006>; + }; + + opp@400000000,1200 { + opp-microvolt = <1200000 1200000 1350000>; + opp-hz = /bits/ 64 <400000000>; + opp-supported-hw = <0x0001>; + }; + + opp@400000000,1250 { + opp-microvolt = <1250000 1250000 1350000>; + opp-hz = /bits/ 64 <400000000>; + opp-supported-hw = <0x0008>; + }; + + opp@416000000,1200 { + opp-microvolt = <1200000 1200000 1350000>; + opp-hz = /bits/ 64 <416000000>; + opp-supported-hw = <0x0007>; + }; + + opp@416000000,1250 { + opp-microvolt = <1250000 1250000 1350000>; + opp-hz = /bits/ 64 <416000000>; + opp-supported-hw = <0x0008>; + }; + + opp@450000000,1200 { + opp-microvolt = <1200000 1200000 1350000>; + opp-hz = /bits/ 64 <450000000>; + opp-supported-hw = <0x0007>; + }; + + opp@450000000,1250 { + opp-microvolt = <1250000 1250000 1350000>; + opp-hz = /bits/ 64 <450000000>; + opp-supported-hw = <0x0008>; + }; + + opp@533000000,1200 { + opp-microvolt = <1200000 1200000 1350000>; + opp-hz = /bits/ 64 <533000000>; + opp-supported-hw = <0x0007>; + }; + + opp@533000000,1250 { + opp-microvolt = <1250000 1250000 1350000>; + opp-hz = /bits/ 64 <533000000>; + opp-supported-hw = <0x0008>; + }; + + opp@625000000,1200 { + opp-microvolt = <1200000 1200000 1350000>; + opp-hz = /bits/ 64 <625000000>; + opp-supported-hw = <0x0006>; + }; + + opp@625000000,1250 { + opp-microvolt = <1250000 1250000 1350000>; + opp-hz = /bits/ 64 <625000000>; + opp-supported-hw = <0x0008>; + }; + + opp@667000000,1200 { + opp-microvolt = <1200000 1200000 1350000>; + opp-hz = /bits/ 64 <667000000>; + opp-supported-hw = <0x0006>; + }; + + opp@750000000,1300 { + opp-microvolt = <1300000 1300000 1350000>; + opp-hz = /bits/ 64 <750000000>; + opp-supported-hw = <0x0004>; + }; + + opp@800000000,1300 { + opp-microvolt = <1300000 1300000 1350000>; + opp-hz = /bits/ 64 <800000000>; + opp-supported-hw = <0x0004>; + }; + + opp@900000000,1350 { + opp-microvolt = <1350000 1350000 1350000>; + opp-hz = /bits/ 64 <900000000>; + opp-supported-hw = <0x0004>; + }; + }; + + emc_bw_dfs_opp_table: emc-bandwidth-opp-table { + compatible = "operating-points-v2"; + + opp@12750000 { + opp-hz = /bits/ 64 <12750000>; + opp-supported-hw = <0x000F>; + opp-peak-kBps = <102000>; + }; + + opp@25500000 { + opp-hz = /bits/ 64 <25500000>; + opp-supported-hw = <0x000F>; + opp-peak-kBps = <204000>; + }; + + opp@27000000 { + opp-hz = /bits/ 64 <27000000>; + opp-supported-hw = <0x000F>; + opp-peak-kBps = <216000>; + }; + + opp@51000000 { + opp-hz = /bits/ 64 <51000000>; + opp-supported-hw = <0x000F>; + opp-peak-kBps = <408000>; + }; + + opp@54000000 { + opp-hz = /bits/ 64 <54000000>; + opp-supported-hw = <0x000F>; + opp-peak-kBps = <432000>; + }; + + opp@102000000 { + opp-hz = /bits/ 64 <102000000>; + opp-supported-hw = <0x000F>; + opp-peak-kBps = <816000>; + }; + + opp@108000000 { + opp-hz = /bits/ 64 <108000000>; + opp-supported-hw = <0x000F>; + opp-peak-kBps = <864000>; + }; + + opp@204000000 { + opp-hz = /bits/ 64 <204000000>; + opp-supported-hw = <0x000F>; + opp-peak-kBps = <1632000>; + }; + + opp@333500000 { + opp-hz = /bits/ 64 <333500000>; + opp-supported-hw = <0x000F>; + opp-peak-kBps = <2668000>; + }; + + opp@375000000 { + opp-hz = /bits/ 64 <375000000>; + opp-supported-hw = <0x000F>; + opp-peak-kBps = <3000000>; + }; + + opp@400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-supported-hw = <0x000F>; + opp-peak-kBps = <3200000>; + }; + + opp@416000000 { + opp-hz = /bits/ 64 <416000000>; + opp-supported-hw = <0x000F>; + opp-peak-kBps = <3328000>; + }; + + opp@450000000 { + opp-hz = /bits/ 64 <450000000>; + opp-supported-hw = <0x000F>; + opp-peak-kBps = <3600000>; + }; + + opp@533000000 { + opp-hz = /bits/ 64 <533000000>; + opp-supported-hw = <0x000F>; + opp-peak-kBps = <4264000>; + }; + + opp@625000000 { + opp-hz = /bits/ 64 <625000000>; + opp-supported-hw = <0x000E>; + opp-peak-kBps = <5000000>; + }; + + opp@667000000 { + opp-hz = /bits/ 64 <667000000>; + opp-supported-hw = <0x0006>; + opp-peak-kBps = <5336000>; + }; + + opp@750000000 { + opp-hz = /bits/ 64 <750000000>; + opp-supported-hw = <0x0004>; + opp-peak-kBps = <6000000>; + }; + + opp@800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-supported-hw = <0x0004>; + opp-peak-kBps = <6400000>; + }; + + opp@900000000 { + opp-hz = /bits/ 64 <900000000>; + opp-supported-hw = <0x0004>; + opp-peak-kBps = <7200000>; + }; + }; +}; diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi index 2caf6cc6f4b1..44a6dbba7081 100644 --- a/arch/arm/boot/dts/tegra30.dtsi +++ b/arch/arm/boot/dts/tegra30.dtsi @@ -6,6 +6,8 @@ #include #include +#include "tegra30-peripherals-opp.dtsi" + / { compatible = "nvidia,tegra30"; interrupt-parent = <&lic>; @@ -417,6 +419,9 @@ clock-names = "actmon", "emc"; resets = <&tegra_car TEGRA30_CLK_ACTMON>; reset-names = "actmon"; + operating-points-v2 = <&emc_bw_dfs_opp_table>; + interconnects = <&mc TEGRA30_MC_MPCORER &emc>; + interconnect-names = "cpu-read"; }; gpio: gpio@6000d000 { @@ -780,6 +785,7 @@ clocks = <&tegra_car TEGRA30_CLK_EMC>; nvidia,memory-controller = <&mc>; + operating-points-v2 = <&emc_icc_dvfs_opp_table>; #interconnect-cells = <0>; }; -- cgit v1.2.3-59-g8ed1b From d63250d7fd49503bac48099fcef24ba7985009a3 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Mon, 23 Nov 2020 03:27:23 +0300 Subject: ARM: tegra: Add EMC OPP and ICC properties to Tegra124 EMC and ACTMON device-tree nodes Add EMC OPP DVFS/DFS tables and interconnect paths that will be used for dynamic memory bandwidth scaling based on memory utilization statistics. Update board device-trees by removing unsupported EMC OPPs. Note that ACTMON watches all memory interconnect paths, but we use a single CPU-READ interconnect path for driving memory bandwidth, for simplicity. Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra124-apalis-emc.dtsi | 8 + arch/arm/boot/dts/tegra124-jetson-tk1-emc.dtsi | 8 + arch/arm/boot/dts/tegra124-nyan-big-emc.dtsi | 10 + arch/arm/boot/dts/tegra124-nyan-blaze-emc.dtsi | 10 + arch/arm/boot/dts/tegra124-peripherals-opp.dtsi | 419 ++++++++++++++++++++++++ arch/arm/boot/dts/tegra124.dtsi | 6 + 6 files changed, 461 insertions(+) create mode 100644 arch/arm/boot/dts/tegra124-peripherals-opp.dtsi (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/tegra124-apalis-emc.dtsi b/arch/arm/boot/dts/tegra124-apalis-emc.dtsi index 32401457ae71..a7ac805eeed5 100644 --- a/arch/arm/boot/dts/tegra124-apalis-emc.dtsi +++ b/arch/arm/boot/dts/tegra124-apalis-emc.dtsi @@ -1465,3 +1465,11 @@ }; }; }; + +&emc_icc_dvfs_opp_table { + /delete-node/ opp@1200000000,1100; +}; + +&emc_bw_dfs_opp_table { + /delete-node/ opp@1200000000; +}; diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1-emc.dtsi b/arch/arm/boot/dts/tegra124-jetson-tk1-emc.dtsi index 861d3f22116b..df4e463afbd1 100644 --- a/arch/arm/boot/dts/tegra124-jetson-tk1-emc.dtsi +++ b/arch/arm/boot/dts/tegra124-jetson-tk1-emc.dtsi @@ -2420,3 +2420,11 @@ }; }; }; + +&emc_icc_dvfs_opp_table { + /delete-node/ opp@1200000000,1100; +}; + +&emc_bw_dfs_opp_table { + /delete-node/ opp@1200000000; +}; diff --git a/arch/arm/boot/dts/tegra124-nyan-big-emc.dtsi b/arch/arm/boot/dts/tegra124-nyan-big-emc.dtsi index c91647d13a50..a0f56cc9da5c 100644 --- a/arch/arm/boot/dts/tegra124-nyan-big-emc.dtsi +++ b/arch/arm/boot/dts/tegra124-nyan-big-emc.dtsi @@ -6649,3 +6649,13 @@ }; }; }; + +&emc_icc_dvfs_opp_table { + /delete-node/ opp@924000000,1100; + /delete-node/ opp@1200000000,1100; +}; + +&emc_bw_dfs_opp_table { + /delete-node/ opp@924000000; + /delete-node/ opp@1200000000; +}; diff --git a/arch/arm/boot/dts/tegra124-nyan-blaze-emc.dtsi b/arch/arm/boot/dts/tegra124-nyan-blaze-emc.dtsi index d2beea0bd15f..35c98734d35f 100644 --- a/arch/arm/boot/dts/tegra124-nyan-blaze-emc.dtsi +++ b/arch/arm/boot/dts/tegra124-nyan-blaze-emc.dtsi @@ -2048,3 +2048,13 @@ }; }; }; + +&emc_icc_dvfs_opp_table { + /delete-node/ opp@924000000,1100; + /delete-node/ opp@1200000000,1100; +}; + +&emc_bw_dfs_opp_table { + /delete-node/ opp@924000000; + /delete-node/ opp@1200000000; +}; diff --git a/arch/arm/boot/dts/tegra124-peripherals-opp.dtsi b/arch/arm/boot/dts/tegra124-peripherals-opp.dtsi new file mode 100644 index 000000000000..49d9420a3289 --- /dev/null +++ b/arch/arm/boot/dts/tegra124-peripherals-opp.dtsi @@ -0,0 +1,419 @@ +// SPDX-License-Identifier: GPL-2.0 + +/ { + emc_icc_dvfs_opp_table: emc-dvfs-opp-table { + compatible = "operating-points-v2"; + + opp@12750000,800 { + opp-microvolt = <800000 800000 1150000>; + opp-hz = /bits/ 64 <12750000>; + opp-supported-hw = <0x0003>; + }; + + opp@12750000,950 { + opp-microvolt = <950000 950000 1150000>; + opp-hz = /bits/ 64 <12750000>; + opp-supported-hw = <0x0008>; + }; + + opp@12750000,1050 { + opp-microvolt = <1050000 1050000 1150000>; + opp-hz = /bits/ 64 <12750000>; + opp-supported-hw = <0x0010>; + }; + + opp@12750000,1110 { + opp-microvolt = <1110000 1110000 1150000>; + opp-hz = /bits/ 64 <12750000>; + opp-supported-hw = <0x0004>; + }; + + opp@20400000,800 { + opp-microvolt = <800000 800000 1150000>; + opp-hz = /bits/ 64 <20400000>; + opp-supported-hw = <0x0003>; + }; + + opp@20400000,950 { + opp-microvolt = <950000 950000 1150000>; + opp-hz = /bits/ 64 <20400000>; + opp-supported-hw = <0x0008>; + }; + + opp@20400000,1050 { + opp-microvolt = <1050000 1050000 1150000>; + opp-hz = /bits/ 64 <20400000>; + opp-supported-hw = <0x0010>; + }; + + opp@20400000,1110 { + opp-microvolt = <1110000 1110000 1150000>; + opp-hz = /bits/ 64 <20400000>; + opp-supported-hw = <0x0004>; + }; + + opp@40800000,800 { + opp-microvolt = <800000 800000 1150000>; + opp-hz = /bits/ 64 <40800000>; + opp-supported-hw = <0x0003>; + }; + + opp@40800000,950 { + opp-microvolt = <950000 950000 1150000>; + opp-hz = /bits/ 64 <40800000>; + opp-supported-hw = <0x0008>; + }; + + opp@40800000,1050 { + opp-microvolt = <1050000 1050000 1150000>; + opp-hz = /bits/ 64 <40800000>; + opp-supported-hw = <0x0010>; + }; + + opp@40800000,1110 { + opp-microvolt = <1110000 1110000 1150000>; + opp-hz = /bits/ 64 <40800000>; + opp-supported-hw = <0x0004>; + }; + + opp@68000000,800 { + opp-microvolt = <800000 800000 1150000>; + opp-hz = /bits/ 64 <68000000>; + opp-supported-hw = <0x0003>; + }; + + opp@68000000,950 { + opp-microvolt = <950000 950000 1150000>; + opp-hz = /bits/ 64 <68000000>; + opp-supported-hw = <0x0008>; + }; + + opp@68000000,1050 { + opp-microvolt = <1050000 1050000 1150000>; + opp-hz = /bits/ 64 <68000000>; + opp-supported-hw = <0x0010>; + }; + + opp@68000000,1110 { + opp-microvolt = <1110000 1110000 1150000>; + opp-hz = /bits/ 64 <68000000>; + opp-supported-hw = <0x0004>; + }; + + opp@102000000,800 { + opp-microvolt = <800000 800000 1150000>; + opp-hz = /bits/ 64 <102000000>; + opp-supported-hw = <0x0003>; + }; + + opp@102000000,950 { + opp-microvolt = <950000 950000 1150000>; + opp-hz = /bits/ 64 <102000000>; + opp-supported-hw = <0x0008>; + }; + + opp@102000000,1050 { + opp-microvolt = <1050000 1050000 1150000>; + opp-hz = /bits/ 64 <102000000>; + opp-supported-hw = <0x0010>; + }; + + opp@102000000,1110 { + opp-microvolt = <1110000 1110000 1150000>; + opp-hz = /bits/ 64 <102000000>; + opp-supported-hw = <0x0004>; + }; + + opp@204000000,800 { + opp-microvolt = <800000 800000 1150000>; + opp-hz = /bits/ 64 <204000000>; + opp-supported-hw = <0x0003>; + }; + + opp@204000000,950 { + opp-microvolt = <950000 950000 1150000>; + opp-hz = /bits/ 64 <204000000>; + opp-supported-hw = <0x0008>; + }; + + opp@204000000,1050 { + opp-microvolt = <1050000 1050000 1150000>; + opp-hz = /bits/ 64 <204000000>; + opp-supported-hw = <0x0010>; + }; + + opp@204000000,1110 { + opp-microvolt = <1110000 1110000 1150000>; + opp-hz = /bits/ 64 <204000000>; + opp-supported-hw = <0x0004>; + }; + + opp@264000000,800 { + opp-microvolt = <800000 800000 1150000>; + opp-hz = /bits/ 64 <264000000>; + opp-supported-hw = <0x0003>; + }; + + opp@264000000,950 { + opp-microvolt = <950000 950000 1150000>; + opp-hz = /bits/ 64 <264000000>; + opp-supported-hw = <0x0008>; + }; + + opp@264000000,1050 { + opp-microvolt = <1050000 1050000 1150000>; + opp-hz = /bits/ 64 <264000000>; + opp-supported-hw = <0x0010>; + }; + + opp@264000000,1110 { + opp-microvolt = <1110000 1110000 1150000>; + opp-hz = /bits/ 64 <264000000>; + opp-supported-hw = <0x0004>; + }; + + opp@300000000,850 { + opp-microvolt = <850000 850000 1150000>; + opp-hz = /bits/ 64 <300000000>; + opp-supported-hw = <0x0003>; + }; + + opp@300000000,950 { + opp-microvolt = <950000 950000 1150000>; + opp-hz = /bits/ 64 <300000000>; + opp-supported-hw = <0x0008>; + }; + + opp@300000000,1050 { + opp-microvolt = <1050000 1050000 1150000>; + opp-hz = /bits/ 64 <300000000>; + opp-supported-hw = <0x0010>; + }; + + opp@300000000,1110 { + opp-microvolt = <1110000 1110000 1150000>; + opp-hz = /bits/ 64 <300000000>; + opp-supported-hw = <0x0004>; + }; + + opp@348000000,850 { + opp-microvolt = <850000 850000 1150000>; + opp-hz = /bits/ 64 <348000000>; + opp-supported-hw = <0x0003>; + }; + + opp@348000000,950 { + opp-microvolt = <950000 950000 1150000>; + opp-hz = /bits/ 64 <348000000>; + opp-supported-hw = <0x0008>; + }; + + opp@348000000,1050 { + opp-microvolt = <1050000 1050000 1150000>; + opp-hz = /bits/ 64 <348000000>; + opp-supported-hw = <0x0010>; + }; + + opp@348000000,1110 { + opp-microvolt = <1110000 1110000 1150000>; + opp-hz = /bits/ 64 <348000000>; + opp-supported-hw = <0x0004>; + }; + + opp@396000000,950 { + opp-microvolt = <950000 950000 1150000>; + opp-hz = /bits/ 64 <396000000>; + opp-supported-hw = <0x0008>; + }; + + opp@396000000,1000 { + opp-microvolt = <1000000 1000000 1150000>; + opp-hz = /bits/ 64 <396000000>; + opp-supported-hw = <0x0003>; + }; + + opp@396000000,1050 { + opp-microvolt = <1050000 1050000 1150000>; + opp-hz = /bits/ 64 <396000000>; + opp-supported-hw = <0x0010>; + }; + + opp@396000000,1110 { + opp-microvolt = <1110000 1110000 1150000>; + opp-hz = /bits/ 64 <396000000>; + opp-supported-hw = <0x0004>; + }; + + opp@528000000,950 { + opp-microvolt = <950000 950000 1150000>; + opp-hz = /bits/ 64 <528000000>; + opp-supported-hw = <0x0008>; + }; + + opp@528000000,1000 { + opp-microvolt = <1000000 1000000 1150000>; + opp-hz = /bits/ 64 <528000000>; + opp-supported-hw = <0x0003>; + }; + + opp@528000000,1050 { + opp-microvolt = <1050000 1050000 1150000>; + opp-hz = /bits/ 64 <528000000>; + opp-supported-hw = <0x0010>; + }; + + opp@528000000,1110 { + opp-microvolt = <1110000 1110000 1150000>; + opp-hz = /bits/ 64 <528000000>; + opp-supported-hw = <0x0004>; + }; + + opp@600000000,950 { + opp-microvolt = <950000 950000 1150000>; + opp-hz = /bits/ 64 <600000000>; + opp-supported-hw = <0x0008>; + }; + + opp@600000000,1000 { + opp-microvolt = <1000000 1000000 1150000>; + opp-hz = /bits/ 64 <600000000>; + opp-supported-hw = <0x0003>; + }; + + opp@600000000,1050 { + opp-microvolt = <1050000 1050000 1150000>; + opp-hz = /bits/ 64 <600000000>; + opp-supported-hw = <0x0010>; + }; + + opp@600000000,1110 { + opp-microvolt = <1110000 1110000 1150000>; + opp-hz = /bits/ 64 <600000000>; + opp-supported-hw = <0x0004>; + }; + + opp@792000000,1000 { + opp-microvolt = <1000000 1000000 1150000>; + opp-hz = /bits/ 64 <792000000>; + opp-supported-hw = <0x000B>; + }; + + opp@792000000,1050 { + opp-microvolt = <1050000 1050000 1150000>; + opp-hz = /bits/ 64 <792000000>; + opp-supported-hw = <0x0010>; + }; + + opp@792000000,1110 { + opp-microvolt = <1110000 1110000 1150000>; + opp-hz = /bits/ 64 <792000000>; + opp-supported-hw = <0x0004>; + }; + + opp@924000000,1100 { + opp-microvolt = <1100000 1100000 1150000>; + opp-hz = /bits/ 64 <924000000>; + opp-supported-hw = <0x0013>; + }; + + opp@1200000000,1100 { + opp-microvolt = <1100000 1100000 1150000>; + opp-hz = /bits/ 64 <1200000000>; + opp-supported-hw = <0x0003>; + }; + }; + + emc_bw_dfs_opp_table: emc-bandwidth-opp-table { + compatible = "operating-points-v2"; + + opp@12750000 { + opp-hz = /bits/ 64 <12750000>; + opp-supported-hw = <0x001F>; + opp-peak-kBps = <204000>; + }; + + opp@20400000 { + opp-hz = /bits/ 64 <20400000>; + opp-supported-hw = <0x001F>; + opp-peak-kBps = <326400>; + }; + + opp@40800000 { + opp-hz = /bits/ 64 <40800000>; + opp-supported-hw = <0x001F>; + opp-peak-kBps = <652800>; + }; + + opp@68000000 { + opp-hz = /bits/ 64 <68000000>; + opp-supported-hw = <0x001F>; + opp-peak-kBps = <1088000>; + }; + + opp@102000000 { + opp-hz = /bits/ 64 <102000000>; + opp-supported-hw = <0x001F>; + opp-peak-kBps = <1632000>; + }; + + opp@204000000 { + opp-hz = /bits/ 64 <204000000>; + opp-supported-hw = <0x001F>; + opp-peak-kBps = <3264000>; + }; + + opp@264000000 { + opp-hz = /bits/ 64 <264000000>; + opp-supported-hw = <0x001F>; + opp-peak-kBps = <4224000>; + }; + + opp@300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-supported-hw = <0x001F>; + opp-peak-kBps = <4800000>; + }; + + opp@348000000 { + opp-hz = /bits/ 64 <348000000>; + opp-supported-hw = <0x001F>; + opp-peak-kBps = <5568000>; + }; + + opp@396000000 { + opp-hz = /bits/ 64 <396000000>; + opp-supported-hw = <0x001F>; + opp-peak-kBps = <6336000>; + }; + + opp@528000000 { + opp-hz = /bits/ 64 <528000000>; + opp-supported-hw = <0x001F>; + opp-peak-kBps = <8448000>; + }; + + opp@600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-supported-hw = <0x001F>; + opp-peak-kBps = <9600000>; + }; + + opp@792000000 { + opp-hz = /bits/ 64 <792000000>; + opp-supported-hw = <0x001F>; + opp-peak-kBps = <12672000>; + }; + + opp@924000000 { + opp-hz = /bits/ 64 <924000000>; + opp-supported-hw = <0x0013>; + opp-peak-kBps = <14784000>; + }; + + opp@1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-supported-hw = <0x0003>; + opp-peak-kBps = <19200000>; + }; + }; +}; diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi index bf621f12ffb7..0b678afb2a5c 100644 --- a/arch/arm/boot/dts/tegra124.dtsi +++ b/arch/arm/boot/dts/tegra124.dtsi @@ -8,6 +8,8 @@ #include #include +#include "tegra124-peripherals-opp.dtsi" + / { compatible = "nvidia,tegra124"; interrupt-parent = <&lic>; @@ -290,6 +292,9 @@ clock-names = "actmon", "emc"; resets = <&tegra_car 119>; reset-names = "actmon"; + operating-points-v2 = <&emc_bw_dfs_opp_table>; + interconnects = <&mc TEGRA124_MC_MPCORER &emc>; + interconnect-names = "cpu-read"; }; gpio: gpio@6000d000 { @@ -660,6 +665,7 @@ clock-names = "emc"; nvidia,memory-controller = <&mc>; + operating-points-v2 = <&emc_icc_dvfs_opp_table>; #interconnect-cells = <0>; }; -- cgit v1.2.3-59-g8ed1b From b62168e516dab1b7cb7bb90976755b08d273cc3a Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Fri, 27 Nov 2020 08:13:25 +0200 Subject: ARM: OMAP2+: Fix am4 only build after genpd changes With commit df6c2ec872a6 ("ARM: OMAP2+: Drop legacy remaining legacy platform data for am4") we moved am4 to boot with simple-pm-bus using genpd and devicetree based data. But I forgot to test am4 only build that still has few references to the old platform data left, and cause undefined reference errors with omap_hwmod_set_postsetup_state and omap_hwmod_for_each. We can just drop the related calls for am4 now, and also drop the references to unused struct wkup_m3_platform_data. Reported-by: Nishanth Menon Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/io.c | 1 - arch/arm/mach-omap2/pdata-quirks.c | 12 ------------ 2 files changed, 13 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c index 6cd99e868556..060ba6957b7c 100644 --- a/arch/arm/mach-omap2/io.c +++ b/arch/arm/mach-omap2/io.c @@ -588,7 +588,6 @@ void __init am43xx_init_early(void) omap2_prcm_base_init(); am43xx_powerdomains_init(); am43xx_clockdomains_init(); - omap_hwmod_init_postsetup(); omap_l2_cache_init(); omap_clk_soc_init = am43xx_dt_clk_init; omap_secure_init(); diff --git a/arch/arm/mach-omap2/pdata-quirks.c b/arch/arm/mach-omap2/pdata-quirks.c index e707d29a5a12..cd38bf07c094 100644 --- a/arch/arm/mach-omap2/pdata-quirks.c +++ b/arch/arm/mach-omap2/pdata-quirks.c @@ -274,14 +274,6 @@ static void __init omap3_pandora_legacy_init(void) } #endif /* CONFIG_ARCH_OMAP3 */ -#if defined(CONFIG_SOC_AM43XX) -static struct wkup_m3_platform_data wkup_m3_data = { - .reset_name = "wkup_m3", - .assert_reset = omap_device_assert_hardreset, - .deassert_reset = omap_device_deassert_hardreset, -}; -#endif - #ifdef CONFIG_SOC_OMAP5 static void __init omap5_uevm_legacy_init(void) { @@ -507,10 +499,6 @@ static struct of_dev_auxdata omap_auxdata_lookup[] = { OF_DEV_AUXDATA("ti,omap3-mcbsp", 0x49024000, "49024000.mcbsp", &mcbsp_pdata), #endif #endif -#ifdef CONFIG_SOC_AM43XX - OF_DEV_AUXDATA("ti,am4372-wkup-m3", 0x44d00000, "44d00000.wkup_m3", - &wkup_m3_data), -#endif #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) OF_DEV_AUXDATA("ti,omap4-smartreflex-iva", 0x4a0db000, "4a0db000.smartreflex", &omap_sr_pdata[OMAP_SR_IVA]), -- cgit v1.2.3-59-g8ed1b From 950be99fccffa920e148fd46e33db4d509e8af63 Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Sun, 8 Nov 2020 20:42:27 -0800 Subject: ARM: multi_v7_defconfig: Enable ARM SCMI protocol and drivers Enable the ARM SCMI protocol and the common clock, cpufreq and sensors drivers. Broadcom STB platforms (ARCH_BRCMSTB) implement SCMI to provide support for CPU frequency scaling, clock configuration and temperature and current sensors. Signed-off-by: Florian Fainelli Acked-by: Sudeep Holla --- arch/arm/configs/multi_v7_defconfig | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig index e731cdf7c88c..f18e8f95c0eb 100644 --- a/arch/arm/configs/multi_v7_defconfig +++ b/arch/arm/configs/multi_v7_defconfig @@ -109,6 +109,7 @@ CONFIG_CPU_FREQ_GOV_CONSERVATIVE=m CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y CONFIG_CPUFREQ_DT=y CONFIG_ARM_IMX6Q_CPUFREQ=y +CONFIG_ARM_SCMI_CPUFREQ=y CONFIG_ARM_RASPBERRYPI_CPUFREQ=y CONFIG_QORIQ_CPUFREQ=y CONFIG_CPU_IDLE=y @@ -117,6 +118,7 @@ CONFIG_ARM_ZYNQ_CPUIDLE=y CONFIG_ARM_EXYNOS_CPUIDLE=y CONFIG_ARM_TEGRA_CPUIDLE=y CONFIG_KERNEL_MODE_NEON=y +CONFIG_ARM_SCMI_PROTOCOL=y CONFIG_RASPBERRYPI_FIRMWARE=y CONFIG_TRUSTED_FOUNDATIONS=y CONFIG_BCM47XX_NVRAM=y @@ -487,6 +489,7 @@ CONFIG_CHARGER_MAX77693=m CONFIG_CHARGER_MAX8997=m CONFIG_CHARGER_MAX8998=m CONFIG_CHARGER_TPS65090=y +CONFIG_SENSORS_ARM_SCMI=y CONFIG_SENSORS_ASPEED=m CONFIG_SENSORS_IIO_HWMON=y CONFIG_SENSORS_LM90=y @@ -958,6 +961,7 @@ CONFIG_CROS_EC_I2C=m CONFIG_CROS_EC_SPI=m CONFIG_COMMON_CLK_MAX77686=y CONFIG_COMMON_CLK_RK808=m +CONFIG_COMMON_CLK_SCMI=y CONFIG_COMMON_CLK_S2MPS11=m CONFIG_CLK_RASPBERRYPI=y CONFIG_COMMON_CLK_QCOM=y -- cgit v1.2.3-59-g8ed1b From fbdb20b1fcb1a252a70f31b35976cf79dc051f19 Mon Sep 17 00:00:00 2001 From: Jonathan Cameron Date: Sun, 15 Nov 2020 19:29:48 +0000 Subject: ARM: dts: qcom-pma8084: Drop incorrect use of io-channel-ranges This property is used by io-channel consumers, not providers so should not present here. Note dt_schema will now detect this error as there is a dependency between this property and io-channels. Signed-off-by: Jonathan Cameron Cc: Andy Gross Cc: Bjorn Andersson Link: https://lore.kernel.org/r/20201115192951.1073632-7-jic23@kernel.org Signed-off-by: Bjorn Andersson --- arch/arm/boot/dts/qcom-pma8084.dtsi | 1 - 1 file changed, 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/qcom-pma8084.dtsi b/arch/arm/boot/dts/qcom-pma8084.dtsi index ea1ca166165c..e921c5e93a5d 100644 --- a/arch/arm/boot/dts/qcom-pma8084.dtsi +++ b/arch/arm/boot/dts/qcom-pma8084.dtsi @@ -68,7 +68,6 @@ #address-cells = <1>; #size-cells = <0>; #io-channel-cells = <1>; - io-channel-ranges; die_temp { reg = ; -- cgit v1.2.3-59-g8ed1b From b08770ff622829285d5b113602b1454910b34044 Mon Sep 17 00:00:00 2001 From: Luka Kovacic Date: Fri, 24 Jul 2020 12:38:37 +0200 Subject: ARM: dts: mvebu: Add CRS326-24G-2S board MikroTik CRS326-24G-2S board has a switch chip with an integrated Marvell Prestera 98DX3236 CPU. This commit includes two board variants, namely the factory default one and a Bit variant. The Bit variant has a bigger Macronix flash. This device tree includes basic Linux support. Signed-off-by: Luka Kovacic Cc: Luka Perkov Cc: Jakov Petrina Reviewed-by: Andrew Lunn Signed-off-by: Gregory CLEMENT --- arch/arm/boot/dts/Makefile | 2 + arch/arm/boot/dts/armada-xp-crs326-24g-2s-bit.dts | 43 +++++++++ arch/arm/boot/dts/armada-xp-crs326-24g-2s.dts | 17 ++++ arch/arm/boot/dts/armada-xp-crs326-24g-2s.dtsi | 104 ++++++++++++++++++++++ 4 files changed, 166 insertions(+) create mode 100644 arch/arm/boot/dts/armada-xp-crs326-24g-2s-bit.dts create mode 100644 arch/arm/boot/dts/armada-xp-crs326-24g-2s.dts create mode 100644 arch/arm/boot/dts/armada-xp-crs326-24g-2s.dtsi (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index ce66ffd5a1bb..dcb1dc357810 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1340,6 +1340,8 @@ dtb-$(CONFIG_MACH_ARMADA_39X) += \ armada-398-db.dtb dtb-$(CONFIG_MACH_ARMADA_XP) += \ armada-xp-axpwifiap.dtb \ + armada-xp-crs326-24g-2s.dtb \ + armada-xp-crs326-24g-2s-bit.dtb \ armada-xp-db.dtb \ armada-xp-db-dxbc2.dtb \ armada-xp-db-xc3-24g4xg.dtb \ diff --git a/arch/arm/boot/dts/armada-xp-crs326-24g-2s-bit.dts b/arch/arm/boot/dts/armada-xp-crs326-24g-2s-bit.dts new file mode 100644 index 000000000000..21f442afab1f --- /dev/null +++ b/arch/arm/boot/dts/armada-xp-crs326-24g-2s-bit.dts @@ -0,0 +1,43 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree file for MikroTik CRS326-24G-2S+ Bit board + * + * Copyright (C) 2020 Sartura Ltd. + * Author: Luka Kovacic + */ + +#include "armada-xp-crs326-24g-2s.dtsi" + +/ { + model = "MikroTik CRS326-24G-2S+ Bit"; +}; + +&spi0 { + status = "okay"; + + spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0>; /* Chip select 0 */ + spi-max-frequency = <108000000>; + m25p,fast-read; + + partition@u-boot { + reg = <0x00000000 0x001f0000>; + label = "u-boot"; + }; + partition@u-boot-env { + reg = <0x001f0000 0x00010000>; + label = "u-boot-env"; + }; + partition@ubi1 { + reg = <0x00200000 0x03f00000>; + label = "ubi1"; + }; + partition@ubi2 { + reg = <0x04100000 0x03f00000>; + label = "ubi2"; + }; + }; +}; diff --git a/arch/arm/boot/dts/armada-xp-crs326-24g-2s.dts b/arch/arm/boot/dts/armada-xp-crs326-24g-2s.dts new file mode 100644 index 000000000000..83aef43f66d5 --- /dev/null +++ b/arch/arm/boot/dts/armada-xp-crs326-24g-2s.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree file for MikroTik CRS326-24G-2S+ board + * + * Copyright (C) 2020 Sartura Ltd. + * Author: Luka Kovacic + */ + +#include "armada-xp-crs326-24g-2s.dtsi" + +/ { + model = "MikroTik CRS326-24G-2S+"; +}; + +&spi0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/armada-xp-crs326-24g-2s.dtsi b/arch/arm/boot/dts/armada-xp-crs326-24g-2s.dtsi new file mode 100644 index 000000000000..f3e1a25ca5f2 --- /dev/null +++ b/arch/arm/boot/dts/armada-xp-crs326-24g-2s.dtsi @@ -0,0 +1,104 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree file for CRS326-24G-2S board + * + * Copyright (C) 2016 Allied Telesis Labs + * Copyright (C) 2020 Sartura Ltd. + * + * Based on armada-xp-db.dts + * + * Note: this Device Tree assumes that the bootloader has remapped the + * internal registers to 0xf1000000 (instead of the default + * 0xd0000000). The 0xf1000000 is the default used by the recent, + * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier + * boards were delivered with an older version of the bootloader that + * left internal registers mapped at 0xd0000000. If you are in this + * situation, you should either update your bootloader (preferred + * solution) or the below Device Tree should be adjusted. + */ + +/dts-v1/; +#include "armada-xp-98dx3236.dtsi" + +/ { + model = "CRS326-24G-2S+"; + compatible = "mikrotik,crs326-24g-2s", "marvell,armadaxp-98dx3236", "marvell,armada-370-xp"; + + chosen { + bootargs = "console=ttyS0,115200 earlyprintk"; + }; + + memory { + device_type = "memory"; + reg = <0 0x00000000 0 0x20000000>; /* 512 MB */ + }; +}; + +&L2 { + arm,parity-enable; + marvell,ecc-enable; +}; + +&devbus_bootcs { + status = "okay"; + + /* Device Bus parameters are required */ + + /* Read parameters */ + devbus,bus-width = <16>; + devbus,turn-off-ps = <60000>; + devbus,badr-skew-ps = <0>; + devbus,acc-first-ps = <124000>; + devbus,acc-next-ps = <248000>; + devbus,rd-setup-ps = <0>; + devbus,rd-hold-ps = <0>; + + /* Write parameters */ + devbus,sync-enable = <0>; + devbus,wr-high-ps = <60000>; + devbus,wr-low-ps = <60000>; + devbus,ale-wr-ps = <60000>; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&i2c0 { + clock-frequency = <100000>; + status = "okay"; +}; + +&usb0 { + status = "okay"; +}; + +&spi0 { + status = "okay"; + + spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0>; /* Chip select 0 */ + spi-max-frequency = <108000000>; + m25p,fast-read; + + partition@u-boot { + reg = <0x00000000 0x001f0000>; + label = "u-boot"; + }; + partition@u-boot-env { + reg = <0x001f0000 0x00010000>; + label = "u-boot-env"; + }; + partition@ubi1 { + reg = <0x00200000 0x00e00000>; + label = "ubi1"; + }; + }; +}; -- cgit v1.2.3-59-g8ed1b From 1b7b86f68c24f372e6cf4af4874dc5df3b8aa61b Mon Sep 17 00:00:00 2001 From: Luka Kovacic Date: Fri, 24 Jul 2020 12:38:38 +0200 Subject: ARM: dts: mvebu: Add CRS305-1G-4S board MikroTik CRS305-1G-4S board has a switch chip with an integrated Marvell Prestera 98DX3236 CPU. This commit includes two board variants, namely the factory default one and a Bit variant. The Bit variant has a bigger Macronix flash. This device tree includes basic Linux support. Signed-off-by: Luka Kovacic Cc: Luka Perkov Cc: Jakov Petrina Reviewed-by: Andrew Lunn Signed-off-by: Gregory CLEMENT --- arch/arm/boot/dts/Makefile | 2 + arch/arm/boot/dts/armada-xp-crs305-1g-4s-bit.dts | 43 ++++++++++ arch/arm/boot/dts/armada-xp-crs305-1g-4s.dts | 17 ++++ arch/arm/boot/dts/armada-xp-crs305-1g-4s.dtsi | 104 +++++++++++++++++++++++ 4 files changed, 166 insertions(+) create mode 100644 arch/arm/boot/dts/armada-xp-crs305-1g-4s-bit.dts create mode 100644 arch/arm/boot/dts/armada-xp-crs305-1g-4s.dts create mode 100644 arch/arm/boot/dts/armada-xp-crs305-1g-4s.dtsi (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index dcb1dc357810..8d171ac51d1a 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1340,6 +1340,8 @@ dtb-$(CONFIG_MACH_ARMADA_39X) += \ armada-398-db.dtb dtb-$(CONFIG_MACH_ARMADA_XP) += \ armada-xp-axpwifiap.dtb \ + armada-xp-crs305-1g-4s.dtb \ + armada-xp-crs305-1g-4s-bit.dtb \ armada-xp-crs326-24g-2s.dtb \ armada-xp-crs326-24g-2s-bit.dtb \ armada-xp-db.dtb \ diff --git a/arch/arm/boot/dts/armada-xp-crs305-1g-4s-bit.dts b/arch/arm/boot/dts/armada-xp-crs305-1g-4s-bit.dts new file mode 100644 index 000000000000..a022c68dc943 --- /dev/null +++ b/arch/arm/boot/dts/armada-xp-crs305-1g-4s-bit.dts @@ -0,0 +1,43 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree file for MikroTik CRS305-1G-4S+ Bit board + * + * Copyright (C) 2020 Sartura Ltd. + * Author: Luka Kovacic + */ + +#include "armada-xp-crs305-1g-4s.dtsi" + +/ { + model = "MikroTik CRS305-1G-4S+ Bit"; +}; + +&spi0 { + status = "okay"; + + spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0>; /* Chip select 0 */ + spi-max-frequency = <108000000>; + m25p,fast-read; + + partition@u-boot { + reg = <0x00000000 0x001f0000>; + label = "u-boot"; + }; + partition@u-boot-env { + reg = <0x001f0000 0x00010000>; + label = "u-boot-env"; + }; + partition@ubi1 { + reg = <0x00200000 0x03f00000>; + label = "ubi1"; + }; + partition@ubi2 { + reg = <0x04100000 0x03f00000>; + label = "ubi2"; + }; + }; +}; diff --git a/arch/arm/boot/dts/armada-xp-crs305-1g-4s.dts b/arch/arm/boot/dts/armada-xp-crs305-1g-4s.dts new file mode 100644 index 000000000000..010b83b54212 --- /dev/null +++ b/arch/arm/boot/dts/armada-xp-crs305-1g-4s.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree file for MikroTik CRS305-1G-4S+ board + * + * Copyright (C) 2020 Sartura Ltd. + * Author: Luka Kovacic + */ + +#include "armada-xp-crs305-1g-4s.dtsi" + +/ { + model = "MikroTik CRS305-1G-4S+"; +}; + +&spi0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/armada-xp-crs305-1g-4s.dtsi b/arch/arm/boot/dts/armada-xp-crs305-1g-4s.dtsi new file mode 100644 index 000000000000..32fb21b2bf6a --- /dev/null +++ b/arch/arm/boot/dts/armada-xp-crs305-1g-4s.dtsi @@ -0,0 +1,104 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree file for CRS305-1G-4S board + * + * Copyright (C) 2016 Allied Telesis Labs + * Copyright (C) 2020 Sartura Ltd. + * + * Based on armada-xp-db.dts + * + * Note: this Device Tree assumes that the bootloader has remapped the + * internal registers to 0xf1000000 (instead of the default + * 0xd0000000). The 0xf1000000 is the default used by the recent, + * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier + * boards were delivered with an older version of the bootloader that + * left internal registers mapped at 0xd0000000. If you are in this + * situation, you should either update your bootloader (preferred + * solution) or the below Device Tree should be adjusted. + */ + +/dts-v1/; +#include "armada-xp-98dx3236.dtsi" + +/ { + model = "CRS305-1G-4S+"; + compatible = "mikrotik,crs305-1g-4s", "marvell,armadaxp-98dx3236", "marvell,armada-370-xp"; + + chosen { + bootargs = "console=ttyS0,115200 earlyprintk"; + }; + + memory { + device_type = "memory"; + reg = <0 0x00000000 0 0x20000000>; /* 512 MB */ + }; +}; + +&L2 { + arm,parity-enable; + marvell,ecc-enable; +}; + +&devbus_bootcs { + status = "okay"; + + /* Device Bus parameters are required */ + + /* Read parameters */ + devbus,bus-width = <16>; + devbus,turn-off-ps = <60000>; + devbus,badr-skew-ps = <0>; + devbus,acc-first-ps = <124000>; + devbus,acc-next-ps = <248000>; + devbus,rd-setup-ps = <0>; + devbus,rd-hold-ps = <0>; + + /* Write parameters */ + devbus,sync-enable = <0>; + devbus,wr-high-ps = <60000>; + devbus,wr-low-ps = <60000>; + devbus,ale-wr-ps = <60000>; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&i2c0 { + clock-frequency = <100000>; + status = "okay"; +}; + +&usb0 { + status = "okay"; +}; + +&spi0 { + status = "okay"; + + spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0>; /* Chip select 0 */ + spi-max-frequency = <108000000>; + m25p,fast-read; + + partition@u-boot { + reg = <0x00000000 0x001f0000>; + label = "u-boot"; + }; + partition@u-boot-env { + reg = <0x001f0000 0x00010000>; + label = "u-boot-env"; + }; + partition@ubi1 { + reg = <0x00200000 0x00e00000>; + label = "ubi1"; + }; + }; +}; -- cgit v1.2.3-59-g8ed1b From d7c51bfa8664e91989f002af9e81983a4fd8326f Mon Sep 17 00:00:00 2001 From: Luka Kovacic Date: Fri, 24 Jul 2020 12:38:39 +0200 Subject: ARM: dts: mvebu: Add CRS328-4C-20S-4S board MikroTik CRS328-4C-20S-4S board has a switch chip with an integrated Marvell Prestera 98DX3236 CPU. This commit includes two board variants, namely the factory default one and a Bit variant. The Bit variant has a bigger Macronix flash. This device tree includes basic Linux support. Signed-off-by: Luka Kovacic Cc: Luka Perkov Cc: Jakov Petrina Reviewed-by: Andrew Lunn Signed-off-by: Gregory CLEMENT --- arch/arm/boot/dts/Makefile | 2 + .../boot/dts/armada-xp-crs328-4c-20s-4s-bit.dts | 43 +++++++++ arch/arm/boot/dts/armada-xp-crs328-4c-20s-4s.dts | 17 ++++ arch/arm/boot/dts/armada-xp-crs328-4c-20s-4s.dtsi | 104 +++++++++++++++++++++ 4 files changed, 166 insertions(+) create mode 100644 arch/arm/boot/dts/armada-xp-crs328-4c-20s-4s-bit.dts create mode 100644 arch/arm/boot/dts/armada-xp-crs328-4c-20s-4s.dts create mode 100644 arch/arm/boot/dts/armada-xp-crs328-4c-20s-4s.dtsi (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 8d171ac51d1a..a89548efdd88 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1344,6 +1344,8 @@ dtb-$(CONFIG_MACH_ARMADA_XP) += \ armada-xp-crs305-1g-4s-bit.dtb \ armada-xp-crs326-24g-2s.dtb \ armada-xp-crs326-24g-2s-bit.dtb \ + armada-xp-crs328-4c-20s-4s.dtb \ + armada-xp-crs328-4c-20s-4s-bit.dtb \ armada-xp-db.dtb \ armada-xp-db-dxbc2.dtb \ armada-xp-db-xc3-24g4xg.dtb \ diff --git a/arch/arm/boot/dts/armada-xp-crs328-4c-20s-4s-bit.dts b/arch/arm/boot/dts/armada-xp-crs328-4c-20s-4s-bit.dts new file mode 100644 index 000000000000..e05aee6cdc04 --- /dev/null +++ b/arch/arm/boot/dts/armada-xp-crs328-4c-20s-4s-bit.dts @@ -0,0 +1,43 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree file for MikroTik CRS328-4C-20S-4S+ Bit board + * + * Copyright (C) 2020 Sartura Ltd. + * Author: Luka Kovacic + */ + +#include "armada-xp-crs328-4c-20s-4s.dtsi" + +/ { + model = "MikroTik CRS328-4C-20S-4S+ Bit"; +}; + +&spi0 { + status = "okay"; + + spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0>; /* Chip select 0 */ + spi-max-frequency = <108000000>; + m25p,fast-read; + + partition@u-boot { + reg = <0x00000000 0x001f0000>; + label = "u-boot"; + }; + partition@u-boot-env { + reg = <0x001f0000 0x00010000>; + label = "u-boot-env"; + }; + partition@ubi1 { + reg = <0x00200000 0x03f00000>; + label = "ubi1"; + }; + partition@ubi2 { + reg = <0x04100000 0x03f00000>; + label = "ubi2"; + }; + }; +}; diff --git a/arch/arm/boot/dts/armada-xp-crs328-4c-20s-4s.dts b/arch/arm/boot/dts/armada-xp-crs328-4c-20s-4s.dts new file mode 100644 index 000000000000..665757f6e18e --- /dev/null +++ b/arch/arm/boot/dts/armada-xp-crs328-4c-20s-4s.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree file for MikroTik CRS328-4C-20S-4S+ board + * + * Copyright (C) 2020 Sartura Ltd. + * Author: Luka Kovacic + */ + +#include "armada-xp-crs328-4c-20s-4s.dtsi" + +/ { + model = "MikroTik CRS328-4C-20S-4S+"; +}; + +&spi0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/armada-xp-crs328-4c-20s-4s.dtsi b/arch/arm/boot/dts/armada-xp-crs328-4c-20s-4s.dtsi new file mode 100644 index 000000000000..c8b1355ce15e --- /dev/null +++ b/arch/arm/boot/dts/armada-xp-crs328-4c-20s-4s.dtsi @@ -0,0 +1,104 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree file for CRS328-4C-20S-4S+ board + * + * Copyright (C) 2016 Allied Telesis Labs + * Copyright (C) 2020 Sartura Ltd. + * + * Based on armada-xp-db.dts + * + * Note: this Device Tree assumes that the bootloader has remapped the + * internal registers to 0xf1000000 (instead of the default + * 0xd0000000). The 0xf1000000 is the default used by the recent, + * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier + * boards were delivered with an older version of the bootloader that + * left internal registers mapped at 0xd0000000. If you are in this + * situation, you should either update your bootloader (preferred + * solution) or the below Device Tree should be adjusted. + */ + +/dts-v1/; +#include "armada-xp-98dx3236.dtsi" + +/ { + model = "CRS328-4C-20S-4S+"; + compatible = "mikrotik,crs328-4c-20s-4s", "marvell,armadaxp-98dx3236", "marvell,armada-370-xp"; + + chosen { + bootargs = "console=ttyS0,115200 earlyprintk"; + }; + + memory { + device_type = "memory"; + reg = <0 0x00000000 0 0x20000000>; /* 512 MB */ + }; +}; + +&L2 { + arm,parity-enable; + marvell,ecc-enable; +}; + +&devbus_bootcs { + status = "okay"; + + /* Device Bus parameters are required */ + + /* Read parameters */ + devbus,bus-width = <16>; + devbus,turn-off-ps = <60000>; + devbus,badr-skew-ps = <0>; + devbus,acc-first-ps = <124000>; + devbus,acc-next-ps = <248000>; + devbus,rd-setup-ps = <0>; + devbus,rd-hold-ps = <0>; + + /* Write parameters */ + devbus,sync-enable = <0>; + devbus,wr-high-ps = <60000>; + devbus,wr-low-ps = <60000>; + devbus,ale-wr-ps = <60000>; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&i2c0 { + clock-frequency = <100000>; + status = "okay"; +}; + +&usb0 { + status = "okay"; +}; + +&spi0 { + status = "okay"; + + spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0>; /* Chip select 0 */ + spi-max-frequency = <108000000>; + m25p,fast-read; + + partition@u-boot { + reg = <0x00000000 0x001f0000>; + label = "u-boot"; + }; + partition@u-boot-env { + reg = <0x001f0000 0x00010000>; + label = "u-boot-env"; + }; + partition@ubi1 { + reg = <0x00200000 0x00e00000>; + label = "ubi1"; + }; + }; +}; -- cgit v1.2.3-59-g8ed1b From 8f32220969109b68d766f9b84a682cf3d07ecd33 Mon Sep 17 00:00:00 2001 From: Adrian Schmutzler Date: Sun, 30 Aug 2020 21:35:43 +0200 Subject: ARM: dts: kirkwood: replace status value "ok" by "okay" While the DT parser recognizes "ok" as a valid value for the "status" property, it is actually mentioned nowhere. Use the proper value "okay" instead, as done in the majority of files already. Signed-off-by: Adrian Schmutzler Reviewed-by: Andrew Lunn Signed-off-by: Gregory CLEMENT --- arch/arm/boot/dts/kirkwood-dockstar.dts | 2 +- arch/arm/boot/dts/kirkwood-dreamplug.dts | 2 +- arch/arm/boot/dts/kirkwood-goflexnet.dts | 2 +- arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts | 2 +- arch/arm/boot/dts/kirkwood-iconnect.dts | 2 +- arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts | 2 +- arch/arm/boot/dts/kirkwood-nsa3x0-common.dtsi | 2 +- arch/arm/boot/dts/kirkwood.dtsi | 4 ++-- 8 files changed, 9 insertions(+), 9 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/kirkwood-dockstar.dts b/arch/arm/boot/dts/kirkwood-dockstar.dts index 6a3f1bf6d9f1..264938dfa4d9 100644 --- a/arch/arm/boot/dts/kirkwood-dockstar.dts +++ b/arch/arm/boot/dts/kirkwood-dockstar.dts @@ -34,7 +34,7 @@ }; }; serial@12000 { - status = "ok"; + status = "okay"; }; }; gpio-leds { diff --git a/arch/arm/boot/dts/kirkwood-dreamplug.dts b/arch/arm/boot/dts/kirkwood-dreamplug.dts index 7f326e267494..328516351e84 100644 --- a/arch/arm/boot/dts/kirkwood-dreamplug.dts +++ b/arch/arm/boot/dts/kirkwood-dreamplug.dts @@ -34,7 +34,7 @@ }; }; serial@12000 { - status = "ok"; + status = "okay"; }; spi@10600 { diff --git a/arch/arm/boot/dts/kirkwood-goflexnet.dts b/arch/arm/boot/dts/kirkwood-goflexnet.dts index 02d87e0a1061..d4cb3cd3e2a2 100644 --- a/arch/arm/boot/dts/kirkwood-goflexnet.dts +++ b/arch/arm/boot/dts/kirkwood-goflexnet.dts @@ -66,7 +66,7 @@ }; }; serial@12000 { - status = "ok"; + status = "okay"; }; sata@80000 { diff --git a/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts b/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts index ff1260ee3fe8..dfb41393941d 100644 --- a/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts +++ b/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts @@ -38,7 +38,7 @@ }; }; serial@12000 { - status = "ok"; + status = "okay"; }; sata@80000 { diff --git a/arch/arm/boot/dts/kirkwood-iconnect.dts b/arch/arm/boot/dts/kirkwood-iconnect.dts index 4a512d80912c..95af7aa1fdcb 100644 --- a/arch/arm/boot/dts/kirkwood-iconnect.dts +++ b/arch/arm/boot/dts/kirkwood-iconnect.dts @@ -72,7 +72,7 @@ }; }; serial@12000 { - status = "ok"; + status = "okay"; }; }; diff --git a/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts b/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts index 62272d58664f..2338f495d517 100644 --- a/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts +++ b/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts @@ -112,7 +112,7 @@ }; serial@12000 { - status = "ok"; + status = "okay"; }; sata@80000 { diff --git a/arch/arm/boot/dts/kirkwood-nsa3x0-common.dtsi b/arch/arm/boot/dts/kirkwood-nsa3x0-common.dtsi index 2c4037b07282..8f73197f251a 100644 --- a/arch/arm/boot/dts/kirkwood-nsa3x0-common.dtsi +++ b/arch/arm/boot/dts/kirkwood-nsa3x0-common.dtsi @@ -45,7 +45,7 @@ }; serial@12000 { - status = "ok"; + status = "okay"; }; sata@80000 { diff --git a/arch/arm/boot/dts/kirkwood.dtsi b/arch/arm/boot/dts/kirkwood.dtsi index 6c8d94beae78..fca31a5d5ac7 100644 --- a/arch/arm/boot/dts/kirkwood.dtsi +++ b/arch/arm/boot/dts/kirkwood.dtsi @@ -369,7 +369,7 @@ clocks = <&gate_clk 14>; clock-names = "sata"; #phy-cells = <0>; - status = "ok"; + status = "okay"; }; sata_phy1: sata-phy@84000 { @@ -378,7 +378,7 @@ clocks = <&gate_clk 15>; clock-names = "sata"; #phy-cells = <0>; - status = "ok"; + status = "okay"; }; audio0: audio-controller@a0000 { -- cgit v1.2.3-59-g8ed1b From 6ac30b5c9956ff03fe8eed0a0ea5430426c99b89 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 16 Sep 2020 17:57:13 +0200 Subject: ARM: dts: dove: fix PCA95xx GPIO expander properties on A510 The PCA95xx GPIO expander requires GPIO controller properties to operate properly. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Linus Walleij Signed-off-by: Gregory CLEMENT --- arch/arm/boot/dts/dove-sbc-a510.dts | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/dove-sbc-a510.dts b/arch/arm/boot/dts/dove-sbc-a510.dts index 2bb85a9b7614..df021f9b0117 100644 --- a/arch/arm/boot/dts/dove-sbc-a510.dts +++ b/arch/arm/boot/dts/dove-sbc-a510.dts @@ -143,6 +143,7 @@ gpio_ext: gpio@20 { compatible = "nxp,pca9555"; reg = <0x20>; + gpio-controller; #gpio-cells = <2>; }; }; -- cgit v1.2.3-59-g8ed1b From 493c6469a6dd911654f04a656ce2d91021e1e915 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 16 Sep 2020 17:57:14 +0200 Subject: ARM: dts: armada: align GPIO hog names with dtschema The convention for node names is to use hyphens, not underscores. dtschema for pca95xx expects GPIO hogs to end with 'hog' prefix. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Gregory CLEMENT --- arch/arm/boot/dts/armada-388-clearfog.dts | 4 ++-- arch/arm/boot/dts/armada-388-clearfog.dtsi | 10 +++++----- arch/arm/boot/dts/armada-388-helios4.dts | 6 +++--- 3 files changed, 10 insertions(+), 10 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/armada-388-clearfog.dts b/arch/arm/boot/dts/armada-388-clearfog.dts index 20f8d4667753..4140a5303b48 100644 --- a/arch/arm/boot/dts/armada-388-clearfog.dts +++ b/arch/arm/boot/dts/armada-388-clearfog.dts @@ -73,13 +73,13 @@ * 14-SFP_TX_DISABLE * 15-SFP_MOD_DEF0 */ - pcie2_0_clkreq { + pcie2-0-clkreq-hog { gpio-hog; gpios = <4 GPIO_ACTIVE_LOW>; input; line-name = "pcie2.0-clkreq"; }; - pcie2_0_w_disable { + pcie2-0-w-disable-hog { gpio-hog; gpios = <7 GPIO_ACTIVE_LOW>; output-low; diff --git a/arch/arm/boot/dts/armada-388-clearfog.dtsi b/arch/arm/boot/dts/armada-388-clearfog.dtsi index a0aa1d188f0c..f8a06ae4a3c9 100644 --- a/arch/arm/boot/dts/armada-388-clearfog.dtsi +++ b/arch/arm/boot/dts/armada-388-clearfog.dtsi @@ -141,31 +141,31 @@ #gpio-cells = <2>; reg = <0x20>; - pcie1_0_clkreq { + pcie1-0-clkreq-hog { gpio-hog; gpios = <0 GPIO_ACTIVE_LOW>; input; line-name = "pcie1.0-clkreq"; }; - pcie1_0_w_disable { + pcie1-0-w-disable-hog { gpio-hog; gpios = <3 GPIO_ACTIVE_LOW>; output-low; line-name = "pcie1.0-w-disable"; }; - usb3_ilimit { + usb3-ilimit-hog { gpio-hog; gpios = <5 GPIO_ACTIVE_LOW>; input; line-name = "usb3-current-limit"; }; - usb3_power { + usb3-power-hog { gpio-hog; gpios = <6 GPIO_ACTIVE_HIGH>; output-high; line-name = "usb3-power"; }; - m2_devslp { + m2-devslp-hog { gpio-hog; gpios = <11 GPIO_ACTIVE_HIGH>; output-low; diff --git a/arch/arm/boot/dts/armada-388-helios4.dts b/arch/arm/boot/dts/armada-388-helios4.dts index fb49df2a3bce..b3728de3bd3f 100644 --- a/arch/arm/boot/dts/armada-388-helios4.dts +++ b/arch/arm/boot/dts/armada-388-helios4.dts @@ -166,19 +166,19 @@ interrupt-controller; #interrupt-cells = <2>; - board_rev_bit_0 { + board-rev-bit-0-hog { gpio-hog; gpios = <0 GPIO_ACTIVE_LOW>; input; line-name = "board-rev-0"; }; - board_rev_bit_1 { + board-rev-bit-1-hog { gpio-hog; gpios = <1 GPIO_ACTIVE_LOW>; input; line-name = "board-rev-1"; }; - usb3_ilimit { + usb3-ilimit-hog { gpio-hog; gpios = <5 GPIO_ACTIVE_HIGH>; input; -- cgit v1.2.3-59-g8ed1b From 7f24479ead579459106bb55c2320a000135731f9 Mon Sep 17 00:00:00 2001 From: Chris Packham Date: Tue, 8 Sep 2020 09:17:11 +1200 Subject: ARM: dts: Remove non-existent i2c1 from 98dx3236 The switches with integrated CPUs have only got a single i2c controller. They incorrectly gained one when they were split from the Armada-XP. Fixes: 43e28ba87708 ("ARM: dts: Use armada-370-xp as a base for armada-xp-98dx3236") Signed-off-by: Chris Packham Reviewed-by: Andrew Lunn Signed-off-by: Gregory CLEMENT --- arch/arm/boot/dts/armada-xp-98dx3236.dtsi | 5 ----- 1 file changed, 5 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/armada-xp-98dx3236.dtsi b/arch/arm/boot/dts/armada-xp-98dx3236.dtsi index 654648b05c7c..aeccedd12574 100644 --- a/arch/arm/boot/dts/armada-xp-98dx3236.dtsi +++ b/arch/arm/boot/dts/armada-xp-98dx3236.dtsi @@ -266,11 +266,6 @@ reg = <0x11000 0x100>; }; -&i2c1 { - compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c"; - reg = <0x11100 0x100>; -}; - &mpic { reg = <0x20a00 0x2d0>, <0x21070 0x58>; }; -- cgit v1.2.3-59-g8ed1b From 44144cc948013a66e3f17269a23653a3d803264a Mon Sep 17 00:00:00 2001 From: Chris Packham Date: Tue, 8 Sep 2020 09:17:12 +1200 Subject: ARM: dts: Add i2c0 pinctrl information for 98dx3236 Add pinctrl information for the 98dx3236 (and variants). There is only one choice for i2c0 MPP14 and MPP15. Signed-off-by: Chris Packham Reviewed-by: Andrew Lunn Signed-off-by: Gregory CLEMENT --- arch/arm/boot/dts/armada-xp-98dx3236.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/armada-xp-98dx3236.dtsi b/arch/arm/boot/dts/armada-xp-98dx3236.dtsi index aeccedd12574..38a052a0312d 100644 --- a/arch/arm/boot/dts/armada-xp-98dx3236.dtsi +++ b/arch/arm/boot/dts/armada-xp-98dx3236.dtsi @@ -264,6 +264,8 @@ &i2c0 { compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c"; reg = <0x11000 0x100>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; }; &mpic { @@ -319,6 +321,11 @@ "mpp2", "mpp3"; marvell,function = "spi0"; }; + + i2c0_pins: i2c-pins-0 { + marvell,pins = "mpp14", "mpp15"; + marvell,function = "i2c0"; + }; }; &spi0 { -- cgit v1.2.3-59-g8ed1b From 7776bcd241e08e13ef009926c6dea84dc3b2f8ff Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Tue, 3 Nov 2020 00:48:44 +0100 Subject: power: supply: s3c-adc-battery: Convert to GPIO descriptors This converts the S3C ADC battery to use GPIO descriptors instead of a global GPIO number for the charging completed GPIO. Using the pattern from the GPIO charger we name this GPIO line "charge-status" in the board file. Cc: linux-samsung-soc@vger.kernel.org Cc: Sergiy Kibrik Signed-off-by: Linus Walleij Signed-off-by: Sebastian Reichel --- arch/arm/mach-s3c/mach-h1940.c | 12 +++++-- arch/arm/mach-s3c/mach-rx1950.c | 11 ++++++- drivers/power/supply/s3c_adc_battery.c | 57 +++++++++++++++++----------------- include/linux/s3c_adc_battery.h | 3 -- 4 files changed, 49 insertions(+), 34 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-s3c/mach-h1940.c b/arch/arm/mach-s3c/mach-h1940.c index 53d51aa83200..8a43ed1c4c4d 100644 --- a/arch/arm/mach-s3c/mach-h1940.c +++ b/arch/arm/mach-s3c/mach-h1940.c @@ -297,6 +297,15 @@ static const struct s3c_adc_bat_thresh bat_lut_acin[] = { { .volt = 3841, .cur = 0, .level = 0}, }; +static struct gpiod_lookup_table h1940_bat_gpio_table = { + .dev_id = "s3c-adc-battery", + .table = { + /* Charge status S3C2410_GPF(3) */ + GPIO_LOOKUP("GPIOF", 3, "charge-status", GPIO_ACTIVE_LOW), + { }, + }, +}; + static int h1940_bat_init(void) { int ret; @@ -330,8 +339,6 @@ static struct s3c_adc_bat_pdata h1940_bat_cfg = { .exit = h1940_bat_exit, .enable_charger = h1940_enable_charger, .disable_charger = h1940_disable_charger, - .gpio_charge_finished = S3C2410_GPF(3), - .gpio_inverted = 1, .lut_noac = bat_lut_noac, .lut_noac_cnt = ARRAY_SIZE(bat_lut_noac), .lut_acin = bat_lut_acin, @@ -720,6 +727,7 @@ static void __init h1940_init(void) s3c24xx_fb_set_platdata(&h1940_fb_info); gpiod_add_lookup_table(&h1940_mmc_gpio_table); gpiod_add_lookup_table(&h1940_audio_gpio_table); + gpiod_add_lookup_table(&h1940_bat_gpio_table); /* Configure the I2S pins (GPE0...GPE4) in correct mode */ s3c_gpio_cfgall_range(S3C2410_GPE(0), 5, S3C_GPIO_SFN(2), S3C_GPIO_PULL_NONE); diff --git a/arch/arm/mach-s3c/mach-rx1950.c b/arch/arm/mach-s3c/mach-rx1950.c index b9758f0a9a14..6e19add158a9 100644 --- a/arch/arm/mach-s3c/mach-rx1950.c +++ b/arch/arm/mach-s3c/mach-rx1950.c @@ -206,6 +206,15 @@ static const struct s3c_adc_bat_thresh bat_lut_acin[] = { { .volt = 3820, .cur = 0, .level = 0}, }; +static struct gpiod_lookup_table rx1950_bat_gpio_table = { + .dev_id = "s3c-adc-battery", + .table = { + /* Charge status S3C2410_GPF(3) */ + GPIO_LOOKUP("GPIOF", 3, "charge-status", GPIO_ACTIVE_HIGH), + { }, + }, +}; + static int rx1950_bat_init(void) { int ret; @@ -331,7 +340,6 @@ static struct s3c_adc_bat_pdata rx1950_bat_cfg = { .exit = rx1950_bat_exit, .enable_charger = rx1950_enable_charger, .disable_charger = rx1950_disable_charger, - .gpio_charge_finished = S3C2410_GPF(3), .lut_noac = bat_lut_noac, .lut_noac_cnt = ARRAY_SIZE(bat_lut_noac), .lut_acin = bat_lut_acin, @@ -840,6 +848,7 @@ static void __init rx1950_init_machine(void) pwm_add_table(rx1950_pwm_lookup, ARRAY_SIZE(rx1950_pwm_lookup)); gpiod_add_lookup_table(&rx1950_audio_gpio_table); + gpiod_add_lookup_table(&rx1950_bat_gpio_table); /* Configure the I2S pins (GPE0...GPE4) in correct mode */ s3c_gpio_cfgall_range(S3C2410_GPE(0), 5, S3C_GPIO_SFN(2), S3C_GPIO_PULL_NONE); diff --git a/drivers/power/supply/s3c_adc_battery.c b/drivers/power/supply/s3c_adc_battery.c index 60b7f41ab063..a2addc24ee8b 100644 --- a/drivers/power/supply/s3c_adc_battery.c +++ b/drivers/power/supply/s3c_adc_battery.c @@ -13,7 +13,7 @@ #include #include #include -#include +#include #include #include #include @@ -31,6 +31,7 @@ struct s3c_adc_bat { struct power_supply *psy; struct s3c_adc_client *client; struct s3c_adc_bat_pdata *pdata; + struct gpio_desc *charge_finished; int volt_value; int cur_value; unsigned int timestamp; @@ -132,9 +133,7 @@ static int calc_full_volt(int volt_val, int cur_val, int impedance) static int charge_finished(struct s3c_adc_bat *bat) { - return bat->pdata->gpio_inverted ? - !gpio_get_value(bat->pdata->gpio_charge_finished) : - gpio_get_value(bat->pdata->gpio_charge_finished); + return gpiod_get_value(bat->charge_finished); } static int s3c_adc_bat_get_property(struct power_supply *psy, @@ -169,7 +168,7 @@ static int s3c_adc_bat_get_property(struct power_supply *psy, } if (bat->cable_plugged && - ((bat->pdata->gpio_charge_finished < 0) || + (!bat->charge_finished || !charge_finished(bat))) { lut = bat->pdata->lut_acin; lut_size = bat->pdata->lut_acin_cnt; @@ -206,7 +205,7 @@ static int s3c_adc_bat_get_property(struct power_supply *psy, switch (psp) { case POWER_SUPPLY_PROP_STATUS: - if (bat->pdata->gpio_charge_finished < 0) + if (!bat->charge_finished) val->intval = bat->level == 100000 ? POWER_SUPPLY_STATUS_FULL : bat->status; else @@ -265,7 +264,7 @@ static void s3c_adc_bat_work(struct work_struct *work) bat->status = POWER_SUPPLY_STATUS_DISCHARGING; } } else { - if ((bat->pdata->gpio_charge_finished >= 0) && is_plugged) { + if (bat->charge_finished && is_plugged) { is_charged = charge_finished(&main_bat); if (is_charged) { if (bat->pdata->disable_charger) @@ -294,6 +293,7 @@ static int s3c_adc_bat_probe(struct platform_device *pdev) struct s3c_adc_client *client; struct s3c_adc_bat_pdata *pdata = pdev->dev.platform_data; struct power_supply_config psy_cfg = {}; + struct gpio_desc *gpiod; int ret; client = s3c_adc_register(pdev, NULL, NULL, 0); @@ -304,8 +304,17 @@ static int s3c_adc_bat_probe(struct platform_device *pdev) platform_set_drvdata(pdev, client); + gpiod = devm_gpiod_get_optional(&pdev->dev, "charge-status", GPIOD_IN); + if (IS_ERR(gpiod)) { + /* Could be probe deferral etc */ + ret = PTR_ERR(gpiod); + dev_err(&pdev->dev, "no GPIO %d\n", ret); + return ret; + } + main_bat.client = client; main_bat.pdata = pdata; + main_bat.charge_finished = gpiod; main_bat.volt_value = -1; main_bat.cur_value = -1; main_bat.cable_plugged = 0; @@ -323,6 +332,7 @@ static int s3c_adc_bat_probe(struct platform_device *pdev) backup_bat.client = client; backup_bat.pdata = pdev->dev.platform_data; + backup_bat.charge_finished = gpiod; backup_bat.volt_value = -1; backup_bat.psy = power_supply_register(&pdev->dev, &backup_bat_desc, @@ -335,12 +345,8 @@ static int s3c_adc_bat_probe(struct platform_device *pdev) INIT_DELAYED_WORK(&bat_work, s3c_adc_bat_work); - if (pdata->gpio_charge_finished >= 0) { - ret = gpio_request(pdata->gpio_charge_finished, "charged"); - if (ret) - goto err_gpio; - - ret = request_irq(gpio_to_irq(pdata->gpio_charge_finished), + if (gpiod) { + ret = request_irq(gpiod_to_irq(gpiod), s3c_adc_bat_charged, IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, "battery charged", NULL); @@ -364,12 +370,9 @@ static int s3c_adc_bat_probe(struct platform_device *pdev) return 0; err_platform: - if (pdata->gpio_charge_finished >= 0) - free_irq(gpio_to_irq(pdata->gpio_charge_finished), NULL); + if (gpiod) + free_irq(gpiod_to_irq(gpiod), NULL); err_irq: - if (pdata->gpio_charge_finished >= 0) - gpio_free(pdata->gpio_charge_finished); -err_gpio: if (pdata->backup_volt_mult) power_supply_unregister(backup_bat.psy); err_reg_backup: @@ -389,10 +392,8 @@ static int s3c_adc_bat_remove(struct platform_device *pdev) s3c_adc_release(client); - if (pdata->gpio_charge_finished >= 0) { - free_irq(gpio_to_irq(pdata->gpio_charge_finished), NULL); - gpio_free(pdata->gpio_charge_finished); - } + if (main_bat.charge_finished) + free_irq(gpiod_to_irq(main_bat.charge_finished), NULL); cancel_delayed_work(&bat_work); @@ -408,12 +409,12 @@ static int s3c_adc_bat_suspend(struct platform_device *pdev, { struct s3c_adc_bat_pdata *pdata = pdev->dev.platform_data; - if (pdata->gpio_charge_finished >= 0) { + if (main_bat.charge_finished) { if (device_may_wakeup(&pdev->dev)) enable_irq_wake( - gpio_to_irq(pdata->gpio_charge_finished)); + gpiod_to_irq(main_bat.charge_finished)); else { - disable_irq(gpio_to_irq(pdata->gpio_charge_finished)); + disable_irq(gpiod_to_irq(main_bat.charge_finished)); main_bat.pdata->disable_charger(); } } @@ -425,12 +426,12 @@ static int s3c_adc_bat_resume(struct platform_device *pdev) { struct s3c_adc_bat_pdata *pdata = pdev->dev.platform_data; - if (pdata->gpio_charge_finished >= 0) { + if (main_bat.charge_finished) { if (device_may_wakeup(&pdev->dev)) disable_irq_wake( - gpio_to_irq(pdata->gpio_charge_finished)); + gpiod_to_irq(main_bat.charge_finished)); else - enable_irq(gpio_to_irq(pdata->gpio_charge_finished)); + enable_irq(gpiod_to_irq(main_bat.charge_finished)); } /* Schedule timer to check current status */ diff --git a/include/linux/s3c_adc_battery.h b/include/linux/s3c_adc_battery.h index 833871dcf6fd..57f982c375f8 100644 --- a/include/linux/s3c_adc_battery.h +++ b/include/linux/s3c_adc_battery.h @@ -14,9 +14,6 @@ struct s3c_adc_bat_pdata { void (*enable_charger)(void); void (*disable_charger)(void); - int gpio_charge_finished; - int gpio_inverted; - const struct s3c_adc_bat_thresh *lut_noac; unsigned int lut_noac_cnt; const struct s3c_adc_bat_thresh *lut_acin; -- cgit v1.2.3-59-g8ed1b From ba940ed83218f034f728184439c7e87795237752 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Fri, 30 Oct 2020 15:34:01 +0100 Subject: power: supply: collie_battery: Convert to GPIO descriptors This converts the Collie battery driver to use GPIO descriptors. We use a mixture of 3 GPIOs defined in the machine and 3 GPIOs requested directly from the ucb1x00 chip. Cc: Robert Jarzmik Cc: Dmitry Eremin-Solenikov Signed-off-by: Linus Walleij Signed-off-by: Sebastian Reichel --- arch/arm/mach-sa1100/collie.c | 21 +++++ drivers/power/supply/collie_battery.c | 151 ++++++++++++++++++++++++---------- 2 files changed, 130 insertions(+), 42 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-sa1100/collie.c b/arch/arm/mach-sa1100/collie.c index bd3a52fd09ce..d4e89a02c8c8 100644 --- a/arch/arm/mach-sa1100/collie.c +++ b/arch/arm/mach-sa1100/collie.c @@ -98,6 +98,26 @@ static struct mcp_plat_data collie_mcp_data = { .codec_pdata = &collie_ucb1x00_data, }; +/* Battery management GPIOs */ +static struct gpiod_lookup_table collie_battery_gpiod_table = { + /* the MCP codec mcp0 has the ucb1x00 as attached device */ + .dev_id = "ucb1x00", + .table = { + /* This is found on the main GPIO on the SA1100 */ + GPIO_LOOKUP("gpio", COLLIE_GPIO_CO, + "main battery full", GPIO_ACTIVE_HIGH), + GPIO_LOOKUP("gpio", COLLIE_GPIO_MAIN_BAT_LOW, + "main battery low", GPIO_ACTIVE_HIGH), + /* + * This is GPIO 0 on the Scoop expander, which is registered + * from common/scoop.c with this gpio chip label. + */ + GPIO_LOOKUP("sharp-scoop", 0, + "main charge on", GPIO_ACTIVE_HIGH), + { }, + }, +}; + static int collie_ir_startup(struct device *dev) { int rc = gpio_request(COLLIE_GPIO_IR_ON, "IrDA"); @@ -395,6 +415,7 @@ static void __init collie_init(void) platform_scoop_config = &collie_pcmcia_config; gpiod_add_lookup_table(&collie_power_gpiod_table); + gpiod_add_lookup_table(&collie_battery_gpiod_table); ret = platform_add_devices(devices, ARRAY_SIZE(devices)); if (ret) { diff --git a/drivers/power/supply/collie_battery.c b/drivers/power/supply/collie_battery.c index cbd588e9e233..7fb9b549f2de 100644 --- a/drivers/power/supply/collie_battery.c +++ b/drivers/power/supply/collie_battery.c @@ -12,7 +12,9 @@ #include #include #include -#include +#include +#include +#include #include #include @@ -31,18 +33,18 @@ struct collie_bat { struct mutex work_lock; /* protects data */ bool (*is_present)(struct collie_bat *bat); - int gpio_full; - int gpio_charge_on; + struct gpio_desc *gpio_full; + struct gpio_desc *gpio_charge_on; int technology; - int gpio_bat; + struct gpio_desc *gpio_bat; int adc_bat; int adc_bat_divider; int bat_max; int bat_min; - int gpio_temp; + struct gpio_desc *gpio_temp; int adc_temp; int adc_temp_divider; }; @@ -53,15 +55,15 @@ static unsigned long collie_read_bat(struct collie_bat *bat) { unsigned long value = 0; - if (bat->gpio_bat < 0 || bat->adc_bat < 0) + if (!bat->gpio_bat || bat->adc_bat < 0) return 0; mutex_lock(&bat_lock); - gpio_set_value(bat->gpio_bat, 1); + gpiod_set_value(bat->gpio_bat, 1); msleep(5); ucb1x00_adc_enable(ucb); value = ucb1x00_adc_read(ucb, bat->adc_bat, UCB_SYNC); ucb1x00_adc_disable(ucb); - gpio_set_value(bat->gpio_bat, 0); + gpiod_set_value(bat->gpio_bat, 0); mutex_unlock(&bat_lock); value = value * 1000000 / bat->adc_bat_divider; @@ -71,16 +73,16 @@ static unsigned long collie_read_bat(struct collie_bat *bat) static unsigned long collie_read_temp(struct collie_bat *bat) { unsigned long value = 0; - if (bat->gpio_temp < 0 || bat->adc_temp < 0) + if (!bat->gpio_temp || bat->adc_temp < 0) return 0; mutex_lock(&bat_lock); - gpio_set_value(bat->gpio_temp, 1); + gpiod_set_value(bat->gpio_temp, 1); msleep(5); ucb1x00_adc_enable(ucb); value = ucb1x00_adc_read(ucb, bat->adc_temp, UCB_SYNC); ucb1x00_adc_disable(ucb); - gpio_set_value(bat->gpio_temp, 0); + gpiod_set_value(bat->gpio_temp, 0); mutex_unlock(&bat_lock); value = value * 10000 / bat->adc_temp_divider; @@ -162,23 +164,23 @@ static void collie_bat_update(struct collie_bat *bat) bat->full_chrg = -1; } else if (power_supply_am_i_supplied(psy)) { if (bat->status == POWER_SUPPLY_STATUS_DISCHARGING) { - gpio_set_value(bat->gpio_charge_on, 1); + gpiod_set_value(bat->gpio_charge_on, 1); mdelay(15); } - if (gpio_get_value(bat->gpio_full)) { + if (gpiod_get_value(bat->gpio_full)) { if (old == POWER_SUPPLY_STATUS_CHARGING || bat->full_chrg == -1) bat->full_chrg = collie_read_bat(bat); - gpio_set_value(bat->gpio_charge_on, 0); + gpiod_set_value(bat->gpio_charge_on, 0); bat->status = POWER_SUPPLY_STATUS_FULL; } else { - gpio_set_value(bat->gpio_charge_on, 1); + gpiod_set_value(bat->gpio_charge_on, 1); bat->status = POWER_SUPPLY_STATUS_CHARGING; } } else { - gpio_set_value(bat->gpio_charge_on, 0); + gpiod_set_value(bat->gpio_charge_on, 0); bat->status = POWER_SUPPLY_STATUS_DISCHARGING; } @@ -230,18 +232,18 @@ static struct collie_bat collie_bat_main = { .full_chrg = -1, .psy = NULL, - .gpio_full = COLLIE_GPIO_CO, - .gpio_charge_on = COLLIE_GPIO_CHARGE_ON, + .gpio_full = NULL, + .gpio_charge_on = NULL, .technology = POWER_SUPPLY_TECHNOLOGY_LIPO, - .gpio_bat = COLLIE_GPIO_MBAT_ON, + .gpio_bat = NULL, .adc_bat = UCB_ADC_INP_AD1, .adc_bat_divider = 155, .bat_max = 4310000, .bat_min = 1551 * 1000000 / 414, - .gpio_temp = COLLIE_GPIO_TMP_ON, + .gpio_temp = NULL, .adc_temp = UCB_ADC_INP_AD0, .adc_temp_divider = 10000, }; @@ -260,30 +262,24 @@ static struct collie_bat collie_bat_bu = { .full_chrg = -1, .psy = NULL, - .gpio_full = -1, - .gpio_charge_on = -1, + .gpio_full = NULL, + .gpio_charge_on = NULL, .technology = POWER_SUPPLY_TECHNOLOGY_LiMn, - .gpio_bat = COLLIE_GPIO_BBAT_ON, + .gpio_bat = NULL, .adc_bat = UCB_ADC_INP_AD1, .adc_bat_divider = 155, .bat_max = 3000000, .bat_min = 1900000, - .gpio_temp = -1, + .gpio_temp = NULL, .adc_temp = -1, .adc_temp_divider = -1, }; -static struct gpio collie_batt_gpios[] = { - { COLLIE_GPIO_CO, GPIOF_IN, "main battery full" }, - { COLLIE_GPIO_MAIN_BAT_LOW, GPIOF_IN, "main battery low" }, - { COLLIE_GPIO_CHARGE_ON, GPIOF_OUT_INIT_LOW, "main charge on" }, - { COLLIE_GPIO_MBAT_ON, GPIOF_OUT_INIT_LOW, "main battery" }, - { COLLIE_GPIO_TMP_ON, GPIOF_OUT_INIT_LOW, "main battery temp" }, - { COLLIE_GPIO_BBAT_ON, GPIOF_OUT_INIT_LOW, "backup battery" }, -}; +/* Obtained but unused GPIO */ +static struct gpio_desc *collie_mbat_low; #ifdef CONFIG_PM static int wakeup_enabled; @@ -295,7 +291,7 @@ static int collie_bat_suspend(struct ucb1x00_dev *dev) if (device_may_wakeup(&dev->ucb->dev) && collie_bat_main.status == POWER_SUPPLY_STATUS_CHARGING) - wakeup_enabled = !enable_irq_wake(gpio_to_irq(COLLIE_GPIO_CO)); + wakeup_enabled = !enable_irq_wake(gpiod_to_irq(collie_bat_main.gpio_full)); else wakeup_enabled = 0; @@ -305,7 +301,7 @@ static int collie_bat_suspend(struct ucb1x00_dev *dev) static int collie_bat_resume(struct ucb1x00_dev *dev) { if (wakeup_enabled) - disable_irq_wake(gpio_to_irq(COLLIE_GPIO_CO)); + disable_irq_wake(gpiod_to_irq(collie_bat_main.gpio_full)); /* things may have changed while we were away */ schedule_work(&bat_work); @@ -320,16 +316,71 @@ static int collie_bat_probe(struct ucb1x00_dev *dev) { int ret; struct power_supply_config psy_main_cfg = {}, psy_bu_cfg = {}; + struct gpio_chip *gc = &dev->ucb->gpio; if (!machine_is_collie()) return -ENODEV; ucb = dev->ucb; - ret = gpio_request_array(collie_batt_gpios, - ARRAY_SIZE(collie_batt_gpios)); - if (ret) - return ret; + /* Obtain all the main battery GPIOs */ + collie_bat_main.gpio_full = gpiod_get(&dev->ucb->dev, + "main battery full", + GPIOD_IN); + if (IS_ERR(collie_bat_main.gpio_full)) + return PTR_ERR(collie_bat_main.gpio_full); + + collie_mbat_low = gpiod_get(&dev->ucb->dev, + "main battery low", + GPIOD_IN); + if (IS_ERR(collie_mbat_low)) { + ret = PTR_ERR(collie_mbat_low); + goto err_put_gpio_full; + } + + collie_bat_main.gpio_charge_on = gpiod_get(&dev->ucb->dev, + "main charge on", + GPIOD_OUT_LOW); + if (IS_ERR(collie_bat_main.gpio_charge_on)) { + ret = PTR_ERR(collie_bat_main.gpio_charge_on); + goto err_put_mbat_low; + } + + /* COLLIE_GPIO_MBAT_ON = GPIO 7 on the UCB (TC35143) */ + collie_bat_main.gpio_bat = gpiochip_request_own_desc(gc, + 7, + "main battery", + GPIO_ACTIVE_HIGH, + GPIOD_OUT_LOW); + if (IS_ERR(collie_bat_main.gpio_bat)) { + ret = PTR_ERR(collie_bat_main.gpio_bat); + goto err_put_gpio_charge_on; + } + + /* COLLIE_GPIO_TMP_ON = GPIO 9 on the UCB (TC35143) */ + collie_bat_main.gpio_temp = gpiochip_request_own_desc(gc, + 9, + "main battery temp", + GPIO_ACTIVE_HIGH, + GPIOD_OUT_LOW); + if (IS_ERR(collie_bat_main.gpio_temp)) { + ret = PTR_ERR(collie_bat_main.gpio_temp); + goto err_free_gpio_bat; + } + + /* + * Obtain the backup battery COLLIE_GPIO_BBAT_ON which is + * GPIO 8 on the UCB (TC35143) + */ + collie_bat_bu.gpio_bat = gpiochip_request_own_desc(gc, + 8, + "backup battery", + GPIO_ACTIVE_HIGH, + GPIOD_OUT_LOW); + if (IS_ERR(collie_bat_bu.gpio_bat)) { + ret = PTR_ERR(collie_bat_bu.gpio_bat); + goto err_free_gpio_temp; + } mutex_init(&collie_bat_main.work_lock); @@ -370,27 +421,43 @@ err_irq: err_psy_reg_bu: power_supply_unregister(collie_bat_main.psy); err_psy_reg_main: - /* see comment in collie_bat_remove */ cancel_work_sync(&bat_work); - gpio_free_array(collie_batt_gpios, ARRAY_SIZE(collie_batt_gpios)); + gpiochip_free_own_desc(collie_bat_bu.gpio_bat); +err_free_gpio_temp: + gpiochip_free_own_desc(collie_bat_main.gpio_temp); +err_free_gpio_bat: + gpiochip_free_own_desc(collie_bat_main.gpio_bat); +err_put_gpio_charge_on: + gpiod_put(collie_bat_main.gpio_charge_on); +err_put_mbat_low: + gpiod_put(collie_mbat_low); +err_put_gpio_full: + gpiod_put(collie_bat_main.gpio_full); + return ret; } static void collie_bat_remove(struct ucb1x00_dev *dev) { free_irq(gpio_to_irq(COLLIE_GPIO_CO), &collie_bat_main); - power_supply_unregister(collie_bat_bu.psy); power_supply_unregister(collie_bat_main.psy); + /* These are obtained from the machine */ + gpiod_put(collie_bat_main.gpio_full); + gpiod_put(collie_mbat_low); + gpiod_put(collie_bat_main.gpio_charge_on); + /* These are directly from the UCB so let's free them */ + gpiochip_free_own_desc(collie_bat_main.gpio_bat); + gpiochip_free_own_desc(collie_bat_main.gpio_temp); + gpiochip_free_own_desc(collie_bat_bu.gpio_bat); /* * Now cancel the bat_work. We won't get any more schedules, * since all sources (isr and external_power_changed) are * unregistered now. */ cancel_work_sync(&bat_work); - gpio_free_array(collie_batt_gpios, ARRAY_SIZE(collie_batt_gpios)); } static struct ucb1x00_driver collie_bat_driver = { -- cgit v1.2.3-59-g8ed1b From 7a1980567fa0b8f37c0fc7d9ca0c7c70724bae3d Mon Sep 17 00:00:00 2001 From: Ran Wang Date: Mon, 2 Nov 2020 15:26:51 +0800 Subject: ARM: dts: ls1021a: fix flextimer failed to wake system The data of property 'fsl,rcpm-wakeup' is not corrcet, which causing RCPM driver incorrectly program register IPPDEXPCR1, then flextimer is wrongly clock gated during system suspend, can't send interrupt to wake. Signed-off-by: Ran Wang Acked-by: Li Yang Signed-off-by: Shawn Guo --- arch/arm/boot/dts/ls1021a.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi index 827373ef1a54..e12809d646a2 100644 --- a/arch/arm/boot/dts/ls1021a.dtsi +++ b/arch/arm/boot/dts/ls1021a.dtsi @@ -1013,7 +1013,7 @@ compatible = "fsl,ls1021a-ftm-alarm"; reg = <0x0 0x29d0000 0x0 0x10000>; reg-names = "ftm"; - fsl,rcpm-wakeup = <&rcpm 0x20000 0x0>; + fsl,rcpm-wakeup = <&rcpm 0x0 0x20000000>; interrupts = ; big-endian; }; -- cgit v1.2.3-59-g8ed1b From 4ebd35bfb1831e549467a0deda99b39acb62cf50 Mon Sep 17 00:00:00 2001 From: Ran Wang Date: Mon, 2 Nov 2020 15:26:52 +0800 Subject: ARM: dts: ls1021a: fix rcpm failed to claim resource The range of dcfg reg is wrong, which overlap with other device, such as rcpm. This issue causing rcpm driver failed to claim reg resource when calling devm_ioremap_resource(). Signed-off-by: Ran Wang Acked-by: Li Yang Signed-off-by: Shawn Guo --- arch/arm/boot/dts/ls1021a.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi index e12809d646a2..16744f64e431 100644 --- a/arch/arm/boot/dts/ls1021a.dtsi +++ b/arch/arm/boot/dts/ls1021a.dtsi @@ -173,7 +173,7 @@ dcfg: dcfg@1ee0000 { compatible = "fsl,ls1021a-dcfg", "syscon"; - reg = <0x0 0x1ee0000 0x0 0x10000>; + reg = <0x0 0x1ee0000 0x0 0x1000>; big-endian; }; -- cgit v1.2.3-59-g8ed1b From 4ba79e25d7f1a7394021ba4c215a7ecdcc270fb6 Mon Sep 17 00:00:00 2001 From: Ivan Zaentsev Date: Mon, 16 Nov 2020 19:58:26 +0300 Subject: ARM: mxs: Add serial number support for i.MX23, i.MX28 SoCs i.MX23 and i.MX28 SoCs unique identifiers are factory-programmed in On-Chip OTP memory. i.MX28's 64-bit unique id is in HW_OCOTP_OPS2:HW_OCOTP_OPS3 (see MCIMX28 Ref. Man., sec. 20.4.22-23). i.MX23 provides 32-bit long unique id in HW_OCOTP_OPS3. Though not clearly documented, there is a clue in sec. 35.9.3. The unique id is reported in /sys/devices/soc0/serial_number and in /proc/cpuinfo Signed-off-by: Ivan Zaentsev Suggested-by: Evgeny Boger Signed-off-by: Shawn Guo --- arch/arm/mach-mxs/mach-mxs.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/mach-mxs/mach-mxs.c b/arch/arm/mach-mxs/mach-mxs.c index c109f47e9cbc..25c9d184fa4c 100644 --- a/arch/arm/mach-mxs/mach-mxs.c +++ b/arch/arm/mach-mxs/mach-mxs.c @@ -22,6 +22,7 @@ #include #include #include +#include #include #include "pm.h" @@ -51,6 +52,9 @@ #define MXS_CLR_ADDR 0x8 #define MXS_TOG_ADDR 0xc +#define HW_OCOTP_OPS2 19 /* offset 0x150 */ +#define HW_OCOTP_OPS3 20 /* offset 0x160 */ + static u32 chipid; static u32 socid; @@ -379,6 +383,8 @@ static void __init mxs_machine_init(void) struct device *parent; struct soc_device *soc_dev; struct soc_device_attribute *soc_dev_attr; + u64 soc_uid = 0; + const u32 *ocotp = mxs_get_ocotp(); int ret; soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL); @@ -394,8 +400,21 @@ static void __init mxs_machine_init(void) soc_dev_attr->soc_id = mxs_get_soc_id(); soc_dev_attr->revision = mxs_get_revision(); + if (socid == HW_DIGCTL_CHIPID_MX23) { + soc_uid = system_serial_low = ocotp[HW_OCOTP_OPS3]; + } else if (socid == HW_DIGCTL_CHIPID_MX28) { + soc_uid = system_serial_high = ocotp[HW_OCOTP_OPS2]; + soc_uid <<= 32; + system_serial_low = ocotp[HW_OCOTP_OPS3]; + soc_uid |= system_serial_low; + } + + if (soc_uid) + soc_dev_attr->serial_number = kasprintf(GFP_KERNEL, "%016llX", soc_uid); + soc_dev = soc_device_register(soc_dev_attr); if (IS_ERR(soc_dev)) { + kfree(soc_dev_attr->serial_number); kfree(soc_dev_attr->revision); kfree(soc_dev_attr); return; -- cgit v1.2.3-59-g8ed1b From b675aaee5464ca8384853145578e662e54debf7a Mon Sep 17 00:00:00 2001 From: Yuantian Tang Date: Tue, 17 Nov 2020 11:43:05 +0800 Subject: ARM: dts: ls1021a: update calibration table for TMU module Update the calibration table to make the temperature more accurate. Signed-off-by: Yuantian Tang Signed-off-by: Shawn Guo --- arch/arm/boot/dts/ls1021a.dtsi | 77 ++++++++++++++++++++---------------------- 1 file changed, 37 insertions(+), 40 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi index 16744f64e431..007dd2bd0595 100644 --- a/arch/arm/boot/dts/ls1021a.dtsi +++ b/arch/arm/boot/dts/ls1021a.dtsi @@ -288,46 +288,43 @@ compatible = "fsl,qoriq-tmu"; reg = <0x0 0x1f00000 0x0 0x10000>; interrupts = ; - fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x30061>; - fsl,tmu-calibration = <0x00000000 0x0000000f - 0x00000001 0x00000017 - 0x00000002 0x0000001e - 0x00000003 0x00000026 - 0x00000004 0x0000002e - 0x00000005 0x00000035 - 0x00000006 0x0000003d - 0x00000007 0x00000044 - 0x00000008 0x0000004c - 0x00000009 0x00000053 - 0x0000000a 0x0000005b - 0x0000000b 0x00000064 - - 0x00010000 0x00000011 - 0x00010001 0x0000001c - 0x00010002 0x00000024 - 0x00010003 0x0000002b - 0x00010004 0x00000034 - 0x00010005 0x00000039 - 0x00010006 0x00000042 - 0x00010007 0x0000004c - 0x00010008 0x00000051 - 0x00010009 0x0000005a - 0x0001000a 0x00000063 - - 0x00020000 0x00000013 - 0x00020001 0x00000019 - 0x00020002 0x00000024 - 0x00020003 0x0000002c - 0x00020004 0x00000035 - 0x00020005 0x0000003d - 0x00020006 0x00000046 - 0x00020007 0x00000050 - 0x00020008 0x00000059 - - 0x00030000 0x00000002 - 0x00030001 0x0000000d - 0x00030002 0x00000019 - 0x00030003 0x00000024>; + fsl,tmu-range = <0xb0000 0x9002c 0x6004e 0x30066>; + fsl,tmu-calibration = <0x00000000 0x00000020 + 0x00000001 0x00000024 + 0x00000002 0x0000002a + 0x00000003 0x00000032 + 0x00000004 0x00000038 + 0x00000005 0x0000003e + 0x00000006 0x00000043 + 0x00000007 0x0000004a + 0x00000008 0x00000050 + 0x00000009 0x00000059 + 0x0000000a 0x0000005f + 0x0000000b 0x00000066 + + 0x00010000 0x00000023 + 0x00010001 0x0000002b + 0x00010002 0x00000033 + 0x00010003 0x0000003a + 0x00010004 0x00000042 + 0x00010005 0x0000004a + 0x00010006 0x00000054 + 0x00010007 0x0000005c + 0x00010008 0x00000065 + 0x00010009 0x0000006f + + 0x00020000 0x00000029 + 0x00020001 0x00000033 + 0x00020002 0x0000003d + 0x00020003 0x00000048 + 0x00020004 0x00000054 + 0x00020005 0x00000060 + 0x00020006 0x0000006c + + 0x00030000 0x00000025 + 0x00030001 0x00000033 + 0x00030002 0x00000043 + 0x00030003 0x00000055>; #thermal-sensor-cells = <1>; }; -- cgit v1.2.3-59-g8ed1b From 1e1a5afde9f79386815233aacf48e188a6710fc2 Mon Sep 17 00:00:00 2001 From: Bruno Thomsen Date: Wed, 18 Nov 2020 11:21:19 +0100 Subject: ARM: dts: imx7: add support for kamstrup flex concentrator This adds support for the OMNIA Flex Concentrator product from Kamstrup A/S. It's providing radio mesh communication infrastructure for smart electricity meters. Kamstrup OMNIA is a modular and scalable smart grid platform. Signed-off-by: Bruno Thomsen Signed-off-by: Shawn Guo --- arch/arm/boot/dts/Makefile | 2 + arch/arm/boot/dts/imx7d-flex-concentrator-mfg.dts | 25 ++ arch/arm/boot/dts/imx7d-flex-concentrator.dts | 314 ++++++++++++++++++++++ 3 files changed, 341 insertions(+) create mode 100644 arch/arm/boot/dts/imx7d-flex-concentrator-mfg.dts create mode 100644 arch/arm/boot/dts/imx7d-flex-concentrator.dts (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index d3275fe3095f..0a7544e01f02 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -644,6 +644,8 @@ dtb-$(CONFIG_SOC_IMX7D) += \ imx7d-colibri-emmc-aster.dtb \ imx7d-colibri-emmc-eval-v3.dtb \ imx7d-colibri-eval-v3.dtb \ + imx7d-flex-concentrator.dtb \ + imx7d-flex-concentrator-mfg.dtb \ imx7d-mba7.dtb \ imx7d-meerkat96.dtb \ imx7d-nitrogen7.dtb \ diff --git a/arch/arm/boot/dts/imx7d-flex-concentrator-mfg.dts b/arch/arm/boot/dts/imx7d-flex-concentrator-mfg.dts new file mode 100644 index 000000000000..a6d68165fb1e --- /dev/null +++ b/arch/arm/boot/dts/imx7d-flex-concentrator-mfg.dts @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for Kamstrup OMNIA Flex Concentrator in + * manufacturing/debugging mode. + * + * Copyright (C) 2020 Kamstrup A/S + * Author: Bruno Thomsen + */ + +/dts-v1/; + +#include "imx7d-flex-concentrator.dts" + +/ { + model = "Kamstrup OMNIA Flex Concentrator - Manufacturing"; + compatible = "kam,imx7d-flex-concentrator-mfg", "fsl,imx7d"; + + chosen { + stdout-path = &uart4; + }; +}; + +&uart4 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx7d-flex-concentrator.dts b/arch/arm/boot/dts/imx7d-flex-concentrator.dts new file mode 100644 index 000000000000..84b095279e65 --- /dev/null +++ b/arch/arm/boot/dts/imx7d-flex-concentrator.dts @@ -0,0 +1,314 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for Kamstrup OMNIA Flex Concentrator. + * + * Copyright (C) 2020 Kamstrup A/S + * Author: Bruno Thomsen + */ + +/dts-v1/; + +#include "imx7d-tqma7.dtsi" + +/* One I2C device on TQMa7 SoM is not mounted */ +/delete-node/ &ds1339; + +/ { + model = "Kamstrup OMNIA Flex Concentrator"; + compatible = "kam,imx7d-flex-concentrator", "fsl,imx7d"; + + memory@80000000 { + device_type = "memory"; + /* 1024 MB - TQMa7D board configuration */ + reg = <0x80000000 0x40000000>; + }; + + reg_usb_otg2_vbus: regulator-usb-otg2-vbus { + compatible = "regulator-fixed"; + regulator-name = "VBUS_USBOTG2"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_vref_1v8: regulator-vref-1v8 { + compatible = "regulator-fixed"; + regulator-name = "VCC1V8_REF"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + vin-supply = <&sw2_reg>; + }; + + /* + * Human Machine Interface consists of 4 dual red/green LEDs. + * hmi-a:green is controlled directly by the switch-mode power supply. + * hmi-a:red is not used. + */ + gpio-leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_leds>; + + led-0 { + label = "hmi-b:red:heartbeat-degraded"; + gpios = <&gpio3 6 GPIO_ACTIVE_HIGH>; + }; + + led-1 { + label = "hmi-b:green:heartbeat-running"; + gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + + led-2 { + label = "hmi-c:red:mesh-error"; + gpios = <&gpio2 29 GPIO_ACTIVE_HIGH>; + }; + + led-3 { + label = "hmi-c:green:mesh-activity"; + gpios = <&gpio2 30 GPIO_ACTIVE_HIGH>; + }; + + led-4 { + label = "hmi-d:red:omnia-error"; + gpios = <&gpio2 31 GPIO_ACTIVE_HIGH>; + }; + + led-5 { + label = "hmi-d:green:omnia-activity"; + gpios = <&gpio4 3 GPIO_ACTIVE_HIGH>; + }; + }; + + /* + * Errata e10574 board restart workaround. + */ + gpio-restart { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_restart>; + compatible = "gpio-restart"; + gpios = <&gpio7 12 GPIO_ACTIVE_LOW>; + priority = <200>; + }; +}; + +/* + * Analog signals + * ADC1_IN0: SMPS - 5V output monitor (voltage divider: 1/0.2806) + */ +&adc1 { + vref-supply = <®_vref_1v8>; + status = "okay"; +}; + +&ecspi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2>; + num-chipselects = <1>; + cs-gpios = <&gpio4 23 GPIO_ACTIVE_LOW>; + status = "okay"; + + pcf2127: rtc@0 { + compatible = "nxp,pcf2127"; + reg = <0>; + spi-max-frequency = <2000000>; + }; +}; + +&ecspi4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi4>; + num-chipselects = <1>; + cs-gpios = <&gpio3 3 GPIO_ACTIVE_LOW>; + status = "okay"; + + /* + * ST chip maximum SPI clock frequency is 33 MHz. + * + * TCG specification - Section 6.4.1 Clocking: + * TPM shall support a SPI clock frequency range of 10-24 MHz. + */ + st33htph: tpm-tis@0 { + compatible = "st,st33htpm-spi", "tcg,tpm_tis-spi"; + reg = <0>; + spi-max-frequency = <24000000>; + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>; + phy-mode = "rmii"; + phy-handle = <ðphy>; + status = "okay"; + + /* + * MDIO bus reset is used to generate PHY device reset before + * Ethernet PHY type ID auto-detection. Otherwise this communication + * fails as device does not answer when recommended reset circuit + * is used. + */ + mdio { + #address-cells = <1>; + #size-cells = <0>; + + reset-delay-us = <100000>; + reset-post-delay-us = <500000>; + reset-gpios = <&gpio7 15 GPIO_ACTIVE_LOW>; + + /* Microchip/Micrel KSZ8081RNB */ + ethphy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + interrupt-parent = <&gpio1>; + interrupts = <9 IRQ_TYPE_LEVEL_LOW>; + reg = <1>; + }; + }; +}; + +/* + * Detection signals for internal USB modules. + * Used for robust USB plug and play handling such as USB downstream port + * power-cycle and USB hub reset in case of misbehaving or crashed modules. + * + * SMPS - AC input monitor based on zero crossing. + * Used for last gasp notification. + */ +&gpio3 { + gpio-line-names = "", "", "", "", "", "", "", "", + "", "", "", "", "smps-ac-monitor", "", "usb-hub-reset", "", + "", "", "", "", "", "", "", "", + "", "module-b-detection", "", "module-a-detection", "", "", "", ""; +}; + +/* + * Tamper IRQ trigger timestamp reading. + * Used for sealed cover opened/closed notification. + */ +&gpio5 { + gpio-line-names = "", "", "", "", "", "", "", "", + "", "", "", "", "rtc-tamper-irq", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_misc>; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX7D_PAD_ECSPI2_MISO__ECSPI2_MISO 0x7c /* X2-15 */ + MX7D_PAD_ECSPI2_MOSI__ECSPI2_MOSI 0x74 /* X2-18 */ + MX7D_PAD_ECSPI2_SCLK__ECSPI2_SCLK 0x74 /* X2-13 */ + MX7D_PAD_ECSPI2_SS0__GPIO4_IO23 0x74 /* X2-20 */ + /* RTC - Tamper IRQ */ + MX7D_PAD_SD2_CLK__GPIO5_IO12 0x3c /* X1-92 */ + >; + }; + + pinctrl_ecspi4: ecspi4grp { + fsl,pins = < + MX7D_PAD_LCD_CLK__ECSPI4_MISO 0x7c /* X2-72 */ + MX7D_PAD_LCD_ENABLE__ECSPI4_MOSI 0x74 /* X2-68 */ + MX7D_PAD_LCD_HSYNC__ECSPI4_SCLK 0x74 /* X2-76 */ + MX7D_PAD_LCD_VSYNC__GPIO3_IO3 0x74 /* X2-78 */ + >; + }; + + pinctrl_enet1: enet1grp { + fsl,pins = < + MX7D_PAD_GPIO1_IO10__ENET1_MDIO 0x03 /* X2-48 */ + MX7D_PAD_GPIO1_IO11__ENET1_MDC 0x03 /* X2-46 */ + MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x71 /* X2-53 */ + MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x71 /* X2-55 */ + MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x71 /* X2-61 */ + MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x79 /* X2-56 */ + MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x79 /* X2-58 */ + MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x79 /* X2-64 */ + MX7D_PAD_ENET1_RGMII_RXC__ENET1_RX_ER 0x73 /* X2-52 */ + /* PHY reset: SRE_FAST, DSE_X1 */ + MX7D_PAD_ENET1_COL__GPIO7_IO15 0x00 /* X1-96 */ + /* Clock from PHY to MAC: 100kPU */ + MX7D_PAD_GPIO1_IO12__CCM_ENET_REF_CLK1 0x70 /* X3-4 */ + /* PHY interrupt: 100kPU, HYS */ + MX7D_PAD_GPIO1_IO09__GPIO1_IO9 0x78 /* X1-80 */ + >; + }; + + pinctrl_leds: ledsgrp { + fsl,pins = < + MX7D_PAD_LCD_DATA01__GPIO3_IO6 0x14 /* X2-82 */ + MX7D_PAD_EPDC_BDR0__GPIO2_IO28 0x14 /* X1-82 */ + MX7D_PAD_EPDC_BDR1__GPIO2_IO29 0x14 /* X1-84 */ + MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30 0x14 /* X1-86 */ + MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 0x14 /* X1-88 */ + MX7D_PAD_UART2_TX_DATA__GPIO4_IO3 0x14 /* X1-90 */ + >; + }; + + pinctrl_misc: miscgrp { + fsl,pins = < + /* Module A detection (low = present) */ + MX7D_PAD_LCD_DATA22__GPIO3_IO27 0x7c /* X2-105 */ + /* Module B detection (low = present) */ + MX7D_PAD_LCD_DATA20__GPIO3_IO25 0x7c /* X2-103 */ + /* SMPS - AC input monitor (high = failure) */ + MX7D_PAD_LCD_DATA07__GPIO3_IO12 0x7c /* X2-88 */ + /* USB - Hub reset */ + MX7D_PAD_LCD_DATA09__GPIO3_IO14 0x74 /* X2-92 */ + >; + }; + + pinctrl_restart: restartgrp { + fsl,pins = < + MX7D_PAD_ENET1_TX_CLK__GPIO7_IO12 0x74 /* X1-94 */ + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX7D_PAD_SAI2_TX_SYNC__UART4_DCE_RX 0x7e /* X3-14 */ + MX7D_PAD_SAI2_TX_BCLK__UART4_DCE_TX 0x76 /* X3-16 */ + >; + }; +}; + +&iomuxc_lpsr { + pinctrl_usbotg2: usbotg2grp { + fsl,pins = < + MX7D_PAD_LPSR_GPIO1_IO06__USB_OTG2_OC 0x5c /* X3-11 */ + MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7 0x59 /* X3-9 */ + >; + }; + +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + assigned-clocks = <&clks IMX7D_UART4_ROOT_SRC>; + assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; +}; + +&usbotg2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg2>; + vbus-supply = <®_usb_otg2_vbus>; + srp-disable; + hnp-disable; + adp-disable; + over-current-active-low; + dr_mode = "host"; + status = "okay"; +}; + +/* + * External watchdog feature provided by pcf2127. + */ +&wdog1 { + status = "disabled"; +}; -- cgit v1.2.3-59-g8ed1b From 018b88eee1a2efda26ed2f09aab33ccdc40ef18f Mon Sep 17 00:00:00 2001 From: Marek Behún Date: Sun, 15 Nov 2020 14:59:17 +0100 Subject: ARM: dts: turris-omnia: enable HW buffer management MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The buffer manager is available on Turris Omnia but needs to be described in device-tree to be used. Signed-off-by: Marek Behún Fixes: 26ca8b52d6e1 ("ARM: dts: add support for Turris Omnia") Cc: linux-arm-kernel@lists.infradead.org Cc: Uwe Kleine-König Cc: Jason Cooper Cc: Gregory CLEMENT Cc: Andreas Färber Cc: Andrew Lunn Cc: Rob Herring Cc: devicetree@vger.kernel.org Signed-off-by: Gregory CLEMENT --- arch/arm/boot/dts/armada-385-turris-omnia.dts | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/armada-385-turris-omnia.dts b/arch/arm/boot/dts/armada-385-turris-omnia.dts index 768b6c5d2129..b6bd73d8f2ba 100644 --- a/arch/arm/boot/dts/armada-385-turris-omnia.dts +++ b/arch/arm/boot/dts/armada-385-turris-omnia.dts @@ -84,12 +84,23 @@ }; }; +&bm { + status = "okay"; +}; + +&bm_bppi { + status = "okay"; +}; + /* Connected to 88E6176 switch, port 6 */ ð0 { pinctrl-names = "default"; pinctrl-0 = <&ge0_rgmii_pins>; status = "okay"; phy-mode = "rgmii"; + buffer-manager = <&bm>; + bm,pool-long = <0>; + bm,pool-short = <3>; fixed-link { speed = <1000>; @@ -103,6 +114,9 @@ pinctrl-0 = <&ge1_rgmii_pins>; status = "okay"; phy-mode = "rgmii"; + buffer-manager = <&bm>; + bm,pool-long = <1>; + bm,pool-short = <3>; fixed-link { speed = <1000>; @@ -115,6 +129,9 @@ status = "okay"; phy-mode = "sgmii"; phy = <&phy1>; + buffer-manager = <&bm>; + bm,pool-long = <2>; + bm,pool-short = <3>; }; &i2c0 { -- cgit v1.2.3-59-g8ed1b From 9ec25ef84832209a8326f9a71fe3ba14f4bcf301 Mon Sep 17 00:00:00 2001 From: Marek Behún Date: Sun, 15 Nov 2020 14:59:18 +0100 Subject: ARM: dts: turris-omnia: add comphy handle to eth2 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The eth2 controller on Turris Omnia is connected to SerDes. For SFP to be able to switch between 1G and 2.5G modes the comphy link has to be defined. Signed-off-by: Marek Behún Fixes: f3a6a9f3704a ("ARM: dts: add description for Armada 38x ...") Reviewed-by: Andrew Lunn Reviewed-by: Andreas Färber Cc: linux-arm-kernel@lists.infradead.org Cc: Uwe Kleine-König Cc: Jason Cooper Cc: Gregory CLEMENT Cc: Rob Herring Cc: devicetree@vger.kernel.org Signed-off-by: Gregory CLEMENT --- arch/arm/boot/dts/armada-385-turris-omnia.dts | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/armada-385-turris-omnia.dts b/arch/arm/boot/dts/armada-385-turris-omnia.dts index b6bd73d8f2ba..9de26c78ec4c 100644 --- a/arch/arm/boot/dts/armada-385-turris-omnia.dts +++ b/arch/arm/boot/dts/armada-385-turris-omnia.dts @@ -129,6 +129,7 @@ status = "okay"; phy-mode = "sgmii"; phy = <&phy1>; + phys = <&comphy5 2>; buffer-manager = <&bm>; bm,pool-long = <2>; bm,pool-short = <3>; -- cgit v1.2.3-59-g8ed1b From d29b67c220caf5f4905e1f1576e71bcb6de4af9e Mon Sep 17 00:00:00 2001 From: Marek Behún Date: Sun, 15 Nov 2020 14:59:19 +0100 Subject: ARM: dts: turris-omnia: describe switch interrupt MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Describe switch interrupt for Turris Omnia so that the CPU does not have to poll the switch. We also need to to set mpp45 pin to gpio function for this. Signed-off-by: Marek Behún Fixes: 26ca8b52d6e1 ("ARM: dts: add support for Turris Omnia") Cc: linux-arm-kernel@lists.infradead.org Cc: Uwe Kleine-König Cc: Jason Cooper Cc: Gregory CLEMENT Cc: Andreas Färber Cc: Andrew Lunn Cc: Rob Herring Cc: devicetree@vger.kernel.org Signed-off-by: Gregory CLEMENT --- arch/arm/boot/dts/armada-385-turris-omnia.dts | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/armada-385-turris-omnia.dts b/arch/arm/boot/dts/armada-385-turris-omnia.dts index 9de26c78ec4c..7ccebf7d1757 100644 --- a/arch/arm/boot/dts/armada-385-turris-omnia.dts +++ b/arch/arm/boot/dts/armada-385-turris-omnia.dts @@ -260,13 +260,18 @@ /* Switch MV88E6176 at address 0x10 */ switch@10 { + pinctrl-names = "default"; + pinctrl-0 = <&swint_pins>; compatible = "marvell,mv88e6085"; #address-cells = <1>; #size-cells = <0>; - dsa,member = <0 0>; + dsa,member = <0 0>; reg = <0x10>; + interrupt-parent = <&gpio1>; + interrupts = <13 IRQ_TYPE_LEVEL_LOW>; + ports { #address-cells = <1>; #size-cells = <0>; @@ -319,6 +324,11 @@ marvell,function = "gpio"; }; + swint_pins: swint-pins { + marvell,pins = "mpp45"; + marvell,function = "gpio"; + }; + spi0cs0_pins: spi0cs0-pins { marvell,pins = "mpp25"; marvell,function = "spi0"; -- cgit v1.2.3-59-g8ed1b From add2d65962977caf23ca2fa21a2457d31b636574 Mon Sep 17 00:00:00 2001 From: Marek Behún Date: Mon, 16 Nov 2020 13:24:22 +0100 Subject: ARM: dts: turris-omnia: add SFP node MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Turris Omnia has an SFP cage that, together with WAN PHY, is connected to eth2 SerDes via a SerDes multiplexor. When a SFP module is present, the multiplexor switches the SerDes signal from PHY to SFP. Describe the SFP cage, but leave it disabled. Until phylink has support for such configuration, we are leaving it to U-Boot to enable SFP and disable WAN PHY at boot time depending on whether a SFP module is present. Signed-off-by: Marek Behún Fixes: 26ca8b52d6e1 ("ARM: dts: add support for Turris Omnia") Reviewed-by: Andrew Lunn Cc: Russell King - ARM Linux admin Cc: linux-arm-kernel@lists.infradead.org Cc: Uwe Kleine-König Cc: Jason Cooper Cc: Gregory CLEMENT Cc: Andreas Färber Cc: Rob Herring Cc: devicetree@vger.kernel.org Signed-off-by: Gregory CLEMENT --- arch/arm/boot/dts/armada-385-turris-omnia.dts | 30 ++++++++++++++++++++++++++- 1 file changed, 29 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/armada-385-turris-omnia.dts b/arch/arm/boot/dts/armada-385-turris-omnia.dts index 7ccebf7d1757..aea07b352d24 100644 --- a/arch/arm/boot/dts/armada-385-turris-omnia.dts +++ b/arch/arm/boot/dts/armada-385-turris-omnia.dts @@ -82,6 +82,24 @@ }; }; }; + + sfp: sfp { + compatible = "sff,sfp"; + i2c-bus = <&sfp_i2c>; + tx-fault-gpios = <&pcawan 0 GPIO_ACTIVE_HIGH>; + tx-disable-gpios = <&pcawan 1 GPIO_ACTIVE_HIGH>; + rate-select0-gpios = <&pcawan 2 GPIO_ACTIVE_HIGH>; + los-gpios = <&pcawan 3 GPIO_ACTIVE_HIGH>; + mod-def0-gpios = <&pcawan 4 GPIO_ACTIVE_LOW>; + maximum-power-milliwatt = <3000>; + + /* + * For now this has to be enabled at boot time by U-Boot when + * a SFP module is present. Read more in the comment in the + * eth2 node below. + */ + status = "disabled"; + }; }; &bm { @@ -126,10 +144,20 @@ /* WAN port */ ð2 { + /* + * eth2 is connected via a multiplexor to both the SFP cage and to + * ethernet-phy@1. The multiplexor switches the signal to SFP cage when + * a SFP module is present, as determined by the mode-def0 GPIO. + * + * Until kernel supports this configuration properly, in case SFP module + * is present, U-Boot has to enable the sfp node above, remove phy + * handle and add managed = "in-band-status" property. + */ status = "okay"; phy-mode = "sgmii"; phy = <&phy1>; phys = <&comphy5 2>; + sfp = <&sfp>; buffer-manager = <&bm>; bm,pool-long = <2>; bm,pool-short = <3>; @@ -195,7 +223,7 @@ /* routed to PCIe2 connector (CN62A) */ }; - i2c@4 { + sfp_i2c: i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; -- cgit v1.2.3-59-g8ed1b From 91dd42d0e30fdbb250c61d1192af569f07e6ada4 Mon Sep 17 00:00:00 2001 From: Marek Behún Date: Sun, 15 Nov 2020 14:59:21 +0100 Subject: ARM: dts: turris-omnia: add LED controller node MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Linux now has incomplete support for the LED controller on Turris Omnia: it can set brightness and colors for each LED. The controller can also put these LEDs into HW controlled mode, in which the LEDs are controlled by HW: for example the WAN LED is connected via MCU to the WAN PHY LED pin. The driver does not support these HW controlled modes yet, and on probe puts the LEDs into SW controlled mode. Add node describing the LED controller, but disable it for now. Signed-off-by: Marek Behún Cc: linux-arm-kernel@lists.infradead.org Cc: Uwe Kleine-König Cc: Jason Cooper Cc: Gregory CLEMENT Cc: Andreas Färber Cc: Rob Herring Cc: devicetree@vger.kernel.org Signed-off-by: Gregory CLEMENT --- arch/arm/boot/dts/armada-385-turris-omnia.dts | 111 +++++++++++++++++++++++++- 1 file changed, 110 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/armada-385-turris-omnia.dts b/arch/arm/boot/dts/armada-385-turris-omnia.dts index aea07b352d24..3c80f0beb09c 100644 --- a/arch/arm/boot/dts/armada-385-turris-omnia.dts +++ b/arch/arm/boot/dts/armada-385-turris-omnia.dts @@ -12,6 +12,7 @@ #include #include +#include #include "armada-385.dtsi" / { @@ -181,7 +182,115 @@ reg = <0>; /* STM32F0 command interface at address 0x2a */ - /* leds device (in STM32F0) at address 0x2b */ + + led-controller@2b { + compatible = "cznic,turris-omnia-leds"; + reg = <0x2b>; + #address-cells = <1>; + #size-cells = <0>; + + /* + * LEDs are controlled by MCU (STM32F0) at + * address 0x2b. + * + * The driver does not support HW control mode + * for the LEDs yet. Disable the LEDs for now. + * + * Also LED functions are not stable yet: + * - there are 3 LEDs connected via MCU to PCIe + * ports. One of these ports supports mSATA. + * There is no mSATA nor PCIe function. + * For now we use LED_FUNCTION_WLAN, since + * in most cases users have wifi cards in + * these slots + * - there are 2 LEDs dedicated for user: A and + * B. Again there is no such function defined. + * For now we use LED_FUNCTION_INDICATOR + */ + status = "disabled"; + + multi-led@0 { + reg = <0x0>; + color = ; + function = LED_FUNCTION_INDICATOR; + function-enumerator = <2>; + }; + + multi-led@1 { + reg = <0x1>; + color = ; + function = LED_FUNCTION_INDICATOR; + function-enumerator = <1>; + }; + + multi-led@2 { + reg = <0x2>; + color = ; + function = LED_FUNCTION_WLAN; + function-enumerator = <3>; + }; + + multi-led@3 { + reg = <0x3>; + color = ; + function = LED_FUNCTION_WLAN; + function-enumerator = <2>; + }; + + multi-led@4 { + reg = <0x4>; + color = ; + function = LED_FUNCTION_WLAN; + function-enumerator = <1>; + }; + + multi-led@5 { + reg = <0x5>; + color = ; + function = LED_FUNCTION_WAN; + }; + + multi-led@6 { + reg = <0x6>; + color = ; + function = LED_FUNCTION_LAN; + function-enumerator = <4>; + }; + + multi-led@7 { + reg = <0x7>; + color = ; + function = LED_FUNCTION_LAN; + function-enumerator = <3>; + }; + + multi-led@8 { + reg = <0x8>; + color = ; + function = LED_FUNCTION_LAN; + function-enumerator = <2>; + }; + + multi-led@9 { + reg = <0x9>; + color = ; + function = LED_FUNCTION_LAN; + function-enumerator = <1>; + }; + + multi-led@a { + reg = <0xa>; + color = ; + function = LED_FUNCTION_LAN; + function-enumerator = <0>; + }; + + multi-led@b { + reg = <0xb>; + color = ; + function = LED_FUNCTION_POWER; + }; + }; eeprom@54 { compatible = "atmel,24c64"; -- cgit v1.2.3-59-g8ed1b From 8ee4a5f4f40da60bb85e13d9dd218a3c9197e3e3 Mon Sep 17 00:00:00 2001 From: Marek Behún Date: Sun, 15 Nov 2020 14:59:22 +0100 Subject: ARM: dts: turris-omnia: update ethernet-phy node and handle name MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Use property name `phy-handle` instead of the deprecated `phy` to connect eth2 to the PHY. Rename the node from "phy@1" to "ethernet-phy@1", since "phy@1" is incorrect according to device-tree bindings documentation. Also remove the "ethernet-phy-id0141.0DD1" compatible string, it is not needed. Kernel can read the PHY identifier itself. Signed-off-by: Marek Behún Reviewed-by: Andrew Lunn Cc: linux-arm-kernel@lists.infradead.org Cc: Uwe Kleine-König Cc: Jason Cooper Cc: Gregory CLEMENT Cc: Andreas Färber Cc: Rob Herring Cc: devicetree@vger.kernel.org Signed-off-by: Gregory CLEMENT --- arch/arm/boot/dts/armada-385-turris-omnia.dts | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/armada-385-turris-omnia.dts b/arch/arm/boot/dts/armada-385-turris-omnia.dts index 3c80f0beb09c..77bbd1ad3328 100644 --- a/arch/arm/boot/dts/armada-385-turris-omnia.dts +++ b/arch/arm/boot/dts/armada-385-turris-omnia.dts @@ -156,7 +156,7 @@ */ status = "okay"; phy-mode = "sgmii"; - phy = <&phy1>; + phy-handle = <&phy1>; phys = <&comphy5 2>; sfp = <&sfp>; buffer-manager = <&bm>; @@ -387,9 +387,9 @@ pinctrl-0 = <&mdio_pins>; status = "okay"; - phy1: phy@1 { + phy1: ethernet-phy@1 { status = "okay"; - compatible = "ethernet-phy-id0141.0DD1", "ethernet-phy-ieee802.3-c22"; + compatible = "ethernet-phy-ieee802.3-c22"; reg = <1>; /* irq is connected to &pcawan pin 7 */ -- cgit v1.2.3-59-g8ed1b From 983b95e9ab76766a5a13ed64b5b0fe716b80e939 Mon Sep 17 00:00:00 2001 From: Marek Behún Date: Sun, 15 Nov 2020 14:59:23 +0100 Subject: ARM: dts: turris-omnia: remove unneeded status = "okay" properties MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Only nodes which have status = "disabled" defined from included files need status = "okay". The ethernet-phy node and the i2cmux node do not need it, since they are wholly defined here. Signed-off-by: Marek Behún Cc: linux-arm-kernel@lists.infradead.org Cc: Uwe Kleine-König Cc: Jason Cooper Cc: Gregory CLEMENT Cc: Andreas Färber Cc: Andrew Lunn Cc: Rob Herring Cc: devicetree@vger.kernel.org Signed-off-by: Gregory CLEMENT --- arch/arm/boot/dts/armada-385-turris-omnia.dts | 2 -- 1 file changed, 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/armada-385-turris-omnia.dts b/arch/arm/boot/dts/armada-385-turris-omnia.dts index 77bbd1ad3328..646a06420c77 100644 --- a/arch/arm/boot/dts/armada-385-turris-omnia.dts +++ b/arch/arm/boot/dts/armada-385-turris-omnia.dts @@ -174,7 +174,6 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x70>; - status = "okay"; i2c@0 { #address-cells = <1>; @@ -388,7 +387,6 @@ status = "okay"; phy1: ethernet-phy@1 { - status = "okay"; compatible = "ethernet-phy-ieee802.3-c22"; reg = <1>; -- cgit v1.2.3-59-g8ed1b From 06bccda2c13c07d4ac7ebfef766a968c788cbdbf Mon Sep 17 00:00:00 2001 From: Johan Jonker Date: Mon, 16 Nov 2020 16:07:56 +0100 Subject: ARM: dts: rockchip: rename wdt nodename to watchdog on rv1108 A test with the command below gives for example this error: /arch/arm/boot/dts/rv1108-evb.dt.yaml: wdt@10360000: $nodename:0: 'wdt@10360000' does not match '^watchdog(@.*|-[0-9a-f])?$' Fix it by renaming the wdt nodename to watchdog in the rv1108.dtsi file. make ARCH=arm dtbs_check DT_SCHEMA_FILES=Documentation/devicetree/bindings/watchdog/snps,dw-wdt.yaml Signed-off-by: Johan Jonker Link: https://lore.kernel.org/r/20201116150756.14265-1-jbx6244@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rv1108.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/rv1108.dtsi b/arch/arm/boot/dts/rv1108.dtsi index a1a08cb9364e..e491964b1c3d 100644 --- a/arch/arm/boot/dts/rv1108.dtsi +++ b/arch/arm/boot/dts/rv1108.dtsi @@ -299,7 +299,7 @@ clock-names = "timer", "pclk"; }; - watchdog: wdt@10360000 { + watchdog: watchdog@10360000 { compatible = "snps,dw-wdt"; reg = <0x10360000 0x100>; interrupts = ; -- cgit v1.2.3-59-g8ed1b From 3f4f3bdadd802dfa1cbb5b905507fdb2e940e830 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Mon, 30 Nov 2020 14:28:14 +0100 Subject: ARM: dts: rockchip: Add rtc node for VMARC SOM Add the hym8563 rtc found on the rk3288 variant of the VMARC SOM. Signed-off-by: Jagan Teki Link: https://lore.kernel.org/r/20201023181814.220974-2-jagan@amarulasolutions.com [split out of the original patch, as it was a change unrelated to the commit description] Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3288-vmarc-som.dtsi | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/rk3288-vmarc-som.dtsi b/arch/arm/boot/dts/rk3288-vmarc-som.dtsi index 4a373f5aa600..da80bfd5f2d5 100644 --- a/arch/arm/boot/dts/rk3288-vmarc-som.dtsi +++ b/arch/arm/boot/dts/rk3288-vmarc-som.dtsi @@ -231,6 +231,23 @@ }; }; +&i2c1 { + clock-frequency = <400000>; + status = "okay"; + + hym8563: rtc@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + interrupt-parent = <&gpio5>; + interrupts = ; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "hym8563"; + pinctrl-names = "default"; + pinctrl-0 = <&hym8563_int>; + }; +}; + &i2c5 { status = "okay"; }; @@ -245,6 +262,12 @@ }; &pinctrl { + hym8563 { + hym8563_int: hym8563-int { + rockchip,pins = <5 RK_PC3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma { drive-strength = <8>; }; -- cgit v1.2.3-59-g8ed1b From 29952fea5e85083374d19cb0a33206962e087d5b Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Fri, 23 Oct 2020 23:48:14 +0530 Subject: ARM: dts: rockchip: Add SDIO0 node for VMARC SOM Rockchip RK3288 and RK3399Pro based VMARC SOM has sdio0 for connecting WiFi/BT devices as a pluggable card via M.2 E-Key. Add associated sdio0 nodes, properties. Signed-off-by: Jagan Teki Link: https://lore.kernel.org/r/20201023181814.220974-2-jagan@amarulasolutions.com [moved the unrelated rtc addition to a separate patch] Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3288-vmarc-som.dtsi | 17 +++++++++++++++++ .../arm/boot/dts/rockchip-radxa-dalang-carrier.dtsi | 21 +++++++++++++++++++++ .../boot/dts/rockchip/rk3399pro-vmarc-som.dtsi | 16 ++++++++++++++++ 3 files changed, 54 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/rk3288-vmarc-som.dtsi b/arch/arm/boot/dts/rk3288-vmarc-som.dtsi index da80bfd5f2d5..0ae2bd150e37 100644 --- a/arch/arm/boot/dts/rk3288-vmarc-som.dtsi +++ b/arch/arm/boot/dts/rk3288-vmarc-som.dtsi @@ -258,6 +258,7 @@ gpio1830-supply = <&vcc_18>; gpio30-supply = <&vcc_io>; sdcard-supply = <&vccio_sd>; + wifi-supply = <&vcc_wl>; status = "okay"; }; @@ -283,6 +284,12 @@ }; }; + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <4 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + sdmmc { sdmmc_bus4: sdmmc-bus4 { rockchip,pins = @@ -314,6 +321,16 @@ }; }; +&sdio_pwrseq { + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + reset-gpios = <&gpio4 RK_PD4 GPIO_ACTIVE_LOW>; /* WIFI_REG_ON */ +}; + &usbphy { status = "okay"; }; diff --git a/arch/arm/boot/dts/rockchip-radxa-dalang-carrier.dtsi b/arch/arm/boot/dts/rockchip-radxa-dalang-carrier.dtsi index 26b53eac4706..da1d548b7330 100644 --- a/arch/arm/boot/dts/rockchip-radxa-dalang-carrier.dtsi +++ b/arch/arm/boot/dts/rockchip-radxa-dalang-carrier.dtsi @@ -15,6 +15,14 @@ #clock-cells = <0>; }; + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&hym8563>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + }; + vcc12v_dcin: vcc12v-dcin-regulator { compatible = "regulator-fixed"; regulator-name = "vcc12v_dcin"; @@ -78,6 +86,19 @@ status = "okay"; }; +&sdio0 { + bus-width = <4>; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; + sd-uhs-sdr104; + status = "okay"; +}; + &sdmmc { bus-width = <4>; cap-mmc-highspeed; diff --git a/arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi b/arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi index 5d087be04af8..7257494d2831 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi @@ -353,6 +353,12 @@ }; }; + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + vbus_host { usb1_en_oc: usb1-en-oc { rockchip,pins = <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_up>; @@ -371,6 +377,16 @@ pmu1830-supply = <&vcc_1v8>; }; +&sdio_pwrseq { + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + reset-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>; +}; + &sdhci { bus-width = <8>; mmc-hs400-1_8v; -- cgit v1.2.3-59-g8ed1b From 98ac141b96034c5d79b512c2db61cd4b0442939d Mon Sep 17 00:00:00 2001 From: Serge Semin Date: Wed, 11 Nov 2020 12:15:46 +0300 Subject: arm: dts: marvell: armada-375: Harmonize DWC USB3 DT nodes name In accordance with the DWC USB3 bindings the corresponding node name is suppose to comply with the Generic USB HCD DT schema, which requires the USB nodes to have the name acceptable by the regexp: "^usb(@.*)?" . Make sure the "snps,dwc3"-compatible nodes are correctly named. Signed-off-by: Serge Semin Acked-by: Krzysztof Kozlowski Signed-off-by: Gregory CLEMENT --- arch/arm/boot/dts/armada-375.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/armada-375.dtsi b/arch/arm/boot/dts/armada-375.dtsi index 9805e507c695..7f2f24a29e6c 100644 --- a/arch/arm/boot/dts/armada-375.dtsi +++ b/arch/arm/boot/dts/armada-375.dtsi @@ -426,7 +426,7 @@ status = "disabled"; }; - usb2: usb3@58000 { + usb2: usb@58000 { compatible = "marvell,armada-375-xhci"; reg = <0x58000 0x20000>,<0x5b880 0x80>; interrupts = ; -- cgit v1.2.3-59-g8ed1b From 51b632c713d50586a844259c56048a280f375406 Mon Sep 17 00:00:00 2001 From: Aryan Srivastava Date: Thu, 26 Nov 2020 17:45:44 +1300 Subject: ARM: dts: mvebu: Add device tree for RD-AC3X-48G4X2XL board Add device tree for RD-AC3X-48G4X2XL board. This has a Armada 382 SoC on a interposer board connected to a baseboard with a Prestera AC3X ASIC connected via PCI. Signed-off-by: Aryan Srivastava Reviewed-by: Chris Packham Reviewed-by: Andrew Lunn Signed-off-by: Gregory CLEMENT --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/armada-382-rd-ac3x-48g4x2xl.dts | 112 ++++++++++++++++++++++ 2 files changed, 113 insertions(+) create mode 100644 arch/arm/boot/dts/armada-382-rd-ac3x-48g4x2xl.dts (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index a89548efdd88..0a68c66f4e38 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1319,6 +1319,7 @@ dtb-$(CONFIG_MACH_ARMADA_370) += \ dtb-$(CONFIG_MACH_ARMADA_375) += \ armada-375-db.dtb dtb-$(CONFIG_MACH_ARMADA_38X) += \ + armada-382-rd-ac3x-48g4x2xl.dtb \ armada-385-clearfog-gtr-s4.dtb \ armada-385-clearfog-gtr-l8.dtb \ armada-385-db-88f6820-amc.dtb \ diff --git a/arch/arm/boot/dts/armada-382-rd-ac3x-48g4x2xl.dts b/arch/arm/boot/dts/armada-382-rd-ac3x-48g4x2xl.dts new file mode 100644 index 000000000000..584f0d0398a5 --- /dev/null +++ b/arch/arm/boot/dts/armada-382-rd-ac3x-48g4x2xl.dts @@ -0,0 +1,112 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Device Tree file for Marvell Armada 382 reference board + * (RD-AC3X-48G4X2XL) + * + * Copyright (C) 2020 Allied Telesis Labs + */ + +/dts-v1/; +#include "armada-385.dtsi" + +#include + +/ { + model = "Marvell Armada 382 RD-AC3X"; + compatible = "marvell,rd-ac3x-48g4x2xl", "marvell,rd-ac3x", + "marvell,armada385", "marvell,armada380"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + aliases { + ethernet0 = ð1; + }; + + memory { + device_type = "memory"; + reg = <0x00000000 0x20000000>; /* 512MB */ + }; + + soc { + ranges = ; + }; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + status = "okay"; + + eeprom@53{ + compatible = "atmel,24c64"; + reg = <0x53>; + }; + + /* CPLD device present at 0x3c. Function unknown */ +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + status = "okay"; +}; + +ð1 { + status = "okay"; + phy = <&phy0>; + phy-mode = "rgmii-id"; +}; + +&mdio { + pinctrl-names = "default"; + pinctrl-0 = <&mdio_pins>; + + phy0: ethernet-phy@0 { + reg = <0>; + }; +}; + +&pciec { + status = "okay"; +}; + +&pcie1 { + /* Port 0, Lane 0 */ + status = "okay"; +}; + +&nand_controller { + status = "okay"; + + nand@0 { + reg = <0>; + label = "pxa3xx_nand-0"; + nand-rb = <0>; + nand-on-flash-bbt; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + partition@0 { + reg = <0x00000000 0x00500000>; + label = "u-boot"; + }; + partition@500000{ + reg = <0x00500000 0x00400000>; + label = "u-boot env"; + }; + partition@900000{ + reg = <0x00900000 0x3F700000>; + label = "user"; + }; + }; + }; +}; + +&refclk { + clock-frequency = <200000000>; +}; -- cgit v1.2.3-59-g8ed1b From 708ed2649ad86dad2284acac6e4e6829a3cfd604 Mon Sep 17 00:00:00 2001 From: Marco Felsch Date: Thu, 26 Nov 2020 20:22:52 +0100 Subject: ARM: dts: imx6qdl-kontron-samx6i: increase i2c-frequency Set it to max. allowed 375kHz for faster transfers. The limit is given by the erratum [1]. [1] https://www.nxp.com/docs/en/errata/IMX6DQCE.pdf Signed-off-by: Marco Felsch Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi b/arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi index 265f5f3dbff6..b6a0b8809e74 100644 --- a/arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi +++ b/arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi @@ -390,21 +390,21 @@ /* I2C_GP */ &i2c1 { - clock-frequency = <100000>; + clock-frequency = <375000>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c1>; }; /* HDMI_CTRL */ &i2c2 { - clock-frequency = <100000>; + clock-frequency = <375000>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c2>; }; /* I2C_PM */ &i2c3 { - clock-frequency = <100000>; + clock-frequency = <375000>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c3>; status = "okay"; -- cgit v1.2.3-59-g8ed1b From 35771b33dd987783171058e7db901f98ddd4c097 Mon Sep 17 00:00:00 2001 From: Oleksij Rempel Date: Tue, 17 Nov 2020 14:13:54 +0100 Subject: ARM: dts: add Protonic WD3 board Protonic WD3 is a proof of concept platform for tractor e-cockpit applications Signed-off-by: Oleksij Rempel Signed-off-by: Shawn Guo --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/imx6qp-prtwd3.dts | 553 ++++++++++++++++++++++++++++++++++++ 2 files changed, 554 insertions(+) create mode 100644 arch/arm/boot/dts/imx6qp-prtwd3.dts (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 0a7544e01f02..3ab9d58428cf 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -583,6 +583,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ imx6qp-nitrogen6_max.dtb \ imx6qp-nitrogen6_som2.dtb \ imx6qp-phytec-mira-rdk-nand.dtb \ + imx6qp-prtwd3.dtb \ imx6qp-sabreauto.dtb \ imx6qp-sabresd.dtb \ imx6qp-tx6qp-8037.dtb \ diff --git a/arch/arm/boot/dts/imx6qp-prtwd3.dts b/arch/arm/boot/dts/imx6qp-prtwd3.dts new file mode 100644 index 000000000000..c42723989bc0 --- /dev/null +++ b/arch/arm/boot/dts/imx6qp-prtwd3.dts @@ -0,0 +1,553 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) 2018 Protonic Holland + * Copyright (c) 2020 Oleksij Rempel , Pengutronix + */ + +/dts-v1/; +#include +#include "imx6qp.dtsi" + +/ { + model = "Protonic WD3 board"; + compatible = "prt,prtwd3", "fsl,imx6qp"; + + chosen { + stdout-path = &uart4; + }; + + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x20000000>; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x20000000>; + }; + + clock_ksz8081: clock-ksz8081 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + }; + + clock_ksz9031: clock-ksz9031 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; + + clock_mcp251xfd: clock-mcp251xfd { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <20000000>; + }; + + clock_sja1105: clock-sja1105 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; + + mdio { + compatible = "virtual,mdio-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mdio>; + + #address-cells = <1>; + #size-cells = <0>; + gpios = <&gpio5 6 GPIO_ACTIVE_HIGH + &gpio5 7 GPIO_ACTIVE_HIGH>; + + /* Microchip KSZ8081 */ + usbeth_phy: ethernet-phy@3 { + reg = <0x3>; + + interrupts-extended = <&gpio5 12 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpio5 11 GPIO_ACTIVE_LOW>; + reset-assert-us = <500>; + reset-deassert-us = <1000>; + clocks = <&clock_ksz8081>; + clock-names = "rmii-ref"; + micrel,led-mode = <0>; + }; + + tja1102_phy0: ethernet-phy@4 { + reg = <0x4>; + + interrupts-extended = <&gpio5 8 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; + reset-assert-us = <20>; + reset-deassert-us = <2000>; + #address-cells = <1>; + #size-cells = <0>; + + tja1102_phy1: ethernet-phy@5 { + reg = <0x5>; + + interrupts-extended = <&gpio5 8 IRQ_TYPE_LEVEL_LOW>; + }; + }; + }; + + reg_5v0: regulator-5v0 { + compatible = "regulator-fixed"; + regulator-name = "5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_otg_vbus: regulator-otg-vbus { + compatible = "regulator-fixed"; + regulator-name = "otg-vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + usdhc2_wifi_pwrseq: usdhc2-wifi-pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wifi_npd>; + reset-gpios = <&gpio6 10 GPIO_ACTIVE_LOW>; + }; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can1>; + xceiver-supply = <®_5v0>; + status = "okay"; +}; + +&ecspi2 { + cs-gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2>; + status = "okay"; + + switch@0 { + compatible = "nxp,sja1105q"; + reg = <0>; + spi-max-frequency = <4000000>; + spi-rx-delay-us = <1>; + spi-tx-delay-us = <1>; + spi-cpha; + + reset-gpios = <&gpio5 5 GPIO_ACTIVE_LOW>; + + clocks = <&clock_sja1105>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "usb"; + phy-handle = <&usbeth_phy>; + phy-mode = "rmii"; + }; + + port@1 { + reg = <1>; + label = "t1slave"; + phy-handle = <&tja1102_phy1>; + phy-mode = "rmii"; + }; + + port@2 { + reg = <2>; + label = "t1master"; + phy-handle = <&tja1102_phy0>; + phy-mode = "rmii"; + + }; + + port@3 { + reg = <3>; + label = "rj45"; + phy-handle = <&rgmii_phy>; + phy-mode = "rgmii-id"; + }; + + port@4 { + reg = <4>; + label = "cpu"; + ethernet = <&fec>; + phy-mode = "rgmii-id"; + + fixed-link { + speed = <100>; + full-duplex; + }; + }; + }; + }; +}; + +&ecspi3 { + cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi3>; + status = "okay"; + + can@0 { + compatible = "microchip,mcp251xfd"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can2>; + reg = <0>; + clocks = <&clock_mcp251xfd>; + spi-max-frequency = <10000000>; + interrupts-extended = <&gpio4 25 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + status = "okay"; + + phy-mode = "rgmii"; + + fixed-link { + speed = <100>; + full-duplex; + }; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + /* Microchip KSZ9031 */ + rgmii_phy: ethernet-phy@2 { + reg = <2>; + + interrupts-extended = <&gpio1 28 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <1000>; + + clocks = <&clock_ksz9031>; + }; + }; +}; + +&gpio1 { + gpio-line-names = + "", "SD1_CD", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "PHY3_RESET", "", "", "PHY3_INT", "", "", ""; +}; + +&gpio2 { + gpio-line-names = + "", "", "", "", "", "", "", "", + "REV_ID0", "REV_ID1", "REV_ID2", "REV_ID3", "BOARD_ID3", + "BOARD_ID0", "BOARD_ID1", "BOARD_ID2", + "", "", "", "", "", "", "", "", + "", "", "ECSPI2_SS0", "", "", "", "", ""; +}; + +&gpio3 { + gpio-line-names = + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "USB_OTG_OC", "USB_OTG_PWR", "", + "", "", "", "", "", "", "", ""; +}; + +&gpio4 { + gpio-line-names = + "", "", "", "", "", "", "", "", + "", "", "", "", "CAN1_SR", "CAN2_SR", "", "", + "", "", "", "", "", "", "", "", + "ECSPI3_SS0", "CANFD_INT", "USB_ETH_RESET", "", "", "", "", ""; +}; + +&gpio5 { + gpio-line-names = + "", "", "", "", "", "SW_RESET", "", "", + "PHY12_INT", "PHY12_RESET", "PHY12_EN", "PHY0_RESET", + "PHY0_INT", "", "", "", + "", "", "DISP1_EN", "DISP1_LR", "DISP1_TS_IRQ", "LVDS1_PD", + "", "", + "", "LVDS1_INT", "", "", "DISP0_LR", "DISP0_TS_IRQ", + "DISP0_EN", "CAM_GPIO0"; +}; + +&gpio6 { + gpio-line-names = + "LVDS0_INT", "LVDS0_PD", "CAM_INT", "CAM_GPIO1", "CAM_PD", + "CAM_LOCK", "", "POWER_TG", + "POWER_VSEL", "", "WLAN_REG_ON", "USB_ETH_CHG", "", "", + "USB_ETH_CHG_ID0", "USB_ETH_CHG_ID1", + "USB_ETH_CHG_ID2", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + /* additional i2c devices are added automatically by the boot loader */ +}; + +&i2c3 { + adc@49 { + compatible = "ti,ads1015"; + reg = <0x49>; + #address-cells = <1>; + #size-cells = <0>; + + /* VIN */ + channel@4 { + reg = <4>; + ti,gain = <1>; + ti,datarate = <3>; + }; + + /* VBUS */ + channel@5 { + reg = <5>; + ti,gain = <1>; + ti,datarate = <3>; + }; + + /* ICHG */ + channel@6 { + reg = <6>; + ti,gain = <1>; + ti,datarate = <3>; + }; + + channel@7 { + reg = <7>; + ti,gain = <1>; + ti,datarate = <3>; + }; + }; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + phy_type = "utmi"; + dr_mode = "host"; + disable-over-current; + status = "okay"; +}; + +&usbphynop1 { + status = "disabled"; +}; + +&usbphynop2 { + status = "disabled"; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; + no-1-8-v; + disable-wp; + cap-sd-highspeed; + no-mmc; + no-sdio; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + no-1-8-v; + non-removable; + mmc-pwrseq = <&usdhc2_wifi_pwrseq>; + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + brcmf: bcrmf@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + }; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + bus-width = <8>; + no-1-8-v; + non-removable; + no-sd; + no-sdio; + status = "okay"; +}; + +&iomuxc { + pinctrl_can1: can1grp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b000 + MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x3008 + /* CAN1_SR */ + MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x13008 + >; + }; + + pinctrl_can2: can2grp { + fsl,pins = < + /* CAN2_nINT */ + MX6QDL_PAD_DISP0_DAT4__GPIO4_IO25 0x1b0b1 + /* CAN2_SR */ + MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x13070 + >; + }; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1 + MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1 + MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1 + MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x000b1 + >; + }; + + pinctrl_ecspi3: ecspi3grp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 + MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 + MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 + /* CS */ + MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x000b1 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x10030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x10030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x10030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x10030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x10030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030 + + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x10030 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x10030 + + /* Configure clock provider for RGMII ref clock */ + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0b0 + /* Configure clock consumer for RGMII ref clock */ + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x10030 + + /* SJA1105Q switch reset */ + MX6QDL_PAD_DISP0_DAT11__GPIO5_IO05 0x10030 + + /* phy3/rgmii_phy reset */ + MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x10030 + /* phy3/rgmii_phy int */ + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x40010000 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001f8b1 + MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001f8b1 + >; + }; + + pinctrl_mdio: mdiogrp { + fsl,pins = < + /* phy0/usbeth_phy reset */ + MX6QDL_PAD_DISP0_DAT17__GPIO5_IO11 0x10030 + /* phy0/usbeth_phy int */ + MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x100b1 + + /* phy12/tja1102_phy0 reset */ + MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09 0x10030 + /* phy12/tja1102_phy0 int */ + MX6QDL_PAD_DISP0_DAT14__GPIO5_IO08 0x100b1 + /* phy12/tja1102_phy0 enable. Set 100K pull-up */ + MX6QDL_PAD_DISP0_DAT16__GPIO5_IO10 0x1f030 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x1b0b0 + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170f9 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100f9 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170f9 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170f9 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170f9 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170f9 + MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x1b0b0 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170b9 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100b9 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170b9 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170b9 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170b9 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17099 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10099 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17099 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17099 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17099 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17099 + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17099 + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17099 + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17099 + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17099 + MX6QDL_PAD_SD3_RST__SD3_RESET 0x1b0b1 + >; + }; + + pinctrl_wifi_npd: wifinpd { + fsl,pins = < + /* WL_REG_ON */ + MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x13069 + >; + }; +}; -- cgit v1.2.3-59-g8ed1b From 327106e4217b8ef4f74640d7de15a0a287690aba Mon Sep 17 00:00:00 2001 From: Lukasz Majewski Date: Wed, 25 Nov 2020 17:18:13 +0100 Subject: ARM: dts: imx28: Fix label name for L2 switch The 'eth_switch' name has been misspelled in the imx28.dtsi file, so this change fixes it. Signed-off-by: Lukasz Majewski Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx28.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi index 94dfbf5b3f34..bbe52150b165 100644 --- a/arch/arm/boot/dts/imx28.dtsi +++ b/arch/arm/boot/dts/imx28.dtsi @@ -1317,7 +1317,7 @@ status = "disabled"; }; - etn_switch: switch@800f8000 { + eth_switch: switch@800f8000 { reg = <0x800f8000 0x8000>; status = "disabled"; }; -- cgit v1.2.3-59-g8ed1b From 8caaf0610fb9948b1f3ad220f83fccfc24e33333 Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Fri, 30 Oct 2020 19:36:58 +0100 Subject: ARM: dts: at91: kizbox: switch to new pwm-atmel-tcb binding Switch to the new pwm-atmel-tcb binding that avoid wasting TCB channels. Signed-off-by: Alexandre Belloni Cc: Antoine Aubert Link: https://lore.kernel.org/r/20201030183658.1007395-5-alexandre.belloni@bootlin.com --- arch/arm/boot/dts/at91-kizbox.dts | 45 ++++++++++++++++++++++++++------------- 1 file changed, 30 insertions(+), 15 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/at91-kizbox.dts b/arch/arm/boot/dts/at91-kizbox.dts index 8b33fe5564fe..3b8812fcd854 100644 --- a/arch/arm/boot/dts/at91-kizbox.dts +++ b/arch/arm/boot/dts/at91-kizbox.dts @@ -53,43 +53,32 @@ led-1 { label = "pwm:green:network"; - pwms = <&tcb_pwm 2 10000000 PWM_POLARITY_INVERTED>; + pwms = <&tcb1_pwm1 0 10000000 PWM_POLARITY_INVERTED>; max-brightness = <255>; linux,default-trigger = "default-on"; }; led-2 { label = "pwm:red:network"; - pwms = <&tcb_pwm 4 10000000 PWM_POLARITY_INVERTED>; + pwms = <&tcb1_pwm2 0 10000000 PWM_POLARITY_INVERTED>; max-brightness = <255>; linux,default-trigger = "default-on"; }; led-3 { label = "pwm:green:user"; - pwms = <&tcb_pwm 0 10000000 PWM_POLARITY_INVERTED>; + pwms = <&tcb1_pwm0 0 10000000 PWM_POLARITY_INVERTED>; max-brightness = <255>; linux,default-trigger = "default-on"; }; led-4 { label = "pwm:red:user"; - pwms = <&tcb_pwm 1 10000000 PWM_POLARITY_INVERTED>; + pwms = <&tcb1_pwm0 1 10000000 PWM_POLARITY_INVERTED>; max-brightness = <255>; linux,default-trigger = "default-on"; }; }; - - tcb_pwm: pwm { - compatible = "atmel,tcb-pwm"; - #pwm-cells = <3>; - tc-block = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_tcb1_tioa0 - &pinctrl_tcb1_tioa1 - &pinctrl_tcb1_tioa2 - &pinctrl_tcb1_tiob0>; - }; }; &tcb0 { @@ -104,6 +93,32 @@ }; }; +&tcb1 { + tcb1_pwm0: pwm@0 { + compatible = "atmel,tcb-pwm"; + reg = <0>; + #pwm-cells = <3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tcb1_tioa0 &pinctrl_tcb1_tiob0>; + }; + + tcb1_pwm1: pwm@1 { + compatible = "atmel,tcb-pwm"; + reg = <1>; + #pwm-cells = <3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tcb1_tioa1>; + }; + + tcb1_pwm2: pwm@2 { + compatible = "atmel,tcb-pwm"; + reg = <2>; + #pwm-cells = <3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tcb1_tioa2>; + }; +}; + &ebi { status = "okay"; }; -- cgit v1.2.3-59-g8ed1b From 53de2d127430d0b5300de5d6ada0f17df0379511 Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Sat, 28 Nov 2020 23:28:16 +0100 Subject: ARM: dts: at91: sama5d3: use proper ADC compatible The ADC is different from the at91sam9x5 ADC. Not only it doesn't have the same resolution but it even has only one and the LOWRES bit doesn't exist. Signed-off-by: Alexandre Belloni Reviewed-by: Ludovic Desroches Link: https://lore.kernel.org/r/20201128222818.1910764-9-alexandre.belloni@bootlin.com --- arch/arm/boot/dts/sama5d3.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi index 86137f8d2b45..bba2a3f41c42 100644 --- a/arch/arm/boot/dts/sama5d3.dtsi +++ b/arch/arm/boot/dts/sama5d3.dtsi @@ -307,7 +307,7 @@ adc0: adc@f8018000 { #address-cells = <1>; #size-cells = <0>; - compatible = "atmel,at91sam9x5-adc"; + compatible = "atmel,sama5d3-adc"; reg = <0xf8018000 0x100>; interrupts = <29 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; -- cgit v1.2.3-59-g8ed1b From 851a95da583c26e2ddeb7281e9b61f0d76ea5aba Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Sat, 28 Nov 2020 23:28:17 +0100 Subject: ARM: dts: at91: at91sam9rl: fix ADC triggers The triggers for the ADC were taken from at91sam9260 dtsi but are not correct. Fixes: a4c1d6c75822 ("ARM: at91/dt: sam9rl: add lcd, adc, usb gadget and pwm support") Signed-off-by: Alexandre Belloni Link: https://lore.kernel.org/r/20201128222818.1910764-10-alexandre.belloni@bootlin.com --- arch/arm/boot/dts/at91sam9rl.dtsi | 19 +++++++++++-------- 1 file changed, 11 insertions(+), 8 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/at91sam9rl.dtsi b/arch/arm/boot/dts/at91sam9rl.dtsi index 5653e70c84b4..36a42a9fe195 100644 --- a/arch/arm/boot/dts/at91sam9rl.dtsi +++ b/arch/arm/boot/dts/at91sam9rl.dtsi @@ -282,23 +282,26 @@ atmel,adc-use-res = "highres"; trigger0 { - trigger-name = "timer-counter-0"; + trigger-name = "external-rising"; trigger-value = <0x1>; + trigger-external; }; + trigger1 { - trigger-name = "timer-counter-1"; - trigger-value = <0x3>; + trigger-name = "external-falling"; + trigger-value = <0x2>; + trigger-external; }; trigger2 { - trigger-name = "timer-counter-2"; - trigger-value = <0x5>; + trigger-name = "external-any"; + trigger-value = <0x3>; + trigger-external; }; trigger3 { - trigger-name = "external"; - trigger-value = <0x13>; - trigger-external; + trigger-name = "continuous"; + trigger-value = <0x6>; }; }; -- cgit v1.2.3-59-g8ed1b From 32b7cfbd4bb2d63fffc34a781e1f3cd911190aef Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Sat, 28 Nov 2020 23:28:18 +0100 Subject: ARM: dts: at91: remove deprecated ADC properties atmel,adc-res, atmel,adc-res-names and the trigger nodes are not parsed by the driver anymore and the information is now defined in the driver data. Also remove the leftover #address-cells and #size-cells that were used when the trigger nodes had a unit-address. Finally, the default is already to use the highest resoution. Remove atmel,adc-use-res from the SoC dtsi. Signed-off-by: Alexandre Belloni Reviewed-by: Ludovic Desroches Link: https://lore.kernel.org/r/20201128222818.1910764-11-alexandre.belloni@bootlin.com --- arch/arm/boot/dts/at91sam9260.dtsi | 25 ------------------------- arch/arm/boot/dts/at91sam9g45.dtsi | 27 --------------------------- arch/arm/boot/dts/at91sam9rl.dtsi | 28 ---------------------------- arch/arm/boot/dts/at91sam9x5.dtsi | 28 ---------------------------- arch/arm/boot/dts/sama5d3.dtsi | 24 ------------------------ arch/arm/boot/dts/sama5d4.dtsi | 22 ---------------------- 6 files changed, 154 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/at91sam9260.dtsi b/arch/arm/boot/dts/at91sam9260.dtsi index 82c5d7fd9811..019f1c3d4d30 100644 --- a/arch/arm/boot/dts/at91sam9260.dtsi +++ b/arch/arm/boot/dts/at91sam9260.dtsi @@ -697,8 +697,6 @@ }; adc0: adc@fffe0000 { - #address-cells = <1>; - #size-cells = <0>; compatible = "atmel,at91sam9260-adc"; reg = <0xfffe0000 0x100>; interrupts = <5 IRQ_TYPE_LEVEL_HIGH 0>; @@ -708,29 +706,6 @@ atmel,adc-channels-used = <0xf>; atmel,adc-vref = <3300>; atmel,adc-startup-time = <15>; - atmel,adc-res = <8 10>; - atmel,adc-res-names = "lowres", "highres"; - atmel,adc-use-res = "highres"; - - trigger0 { - trigger-name = "timer-counter-0"; - trigger-value = <0x1>; - }; - trigger1 { - trigger-name = "timer-counter-1"; - trigger-value = <0x3>; - }; - - trigger2 { - trigger-name = "timer-counter-2"; - trigger-value = <0x5>; - }; - - trigger3 { - trigger-name = "external"; - trigger-value = <0xd>; - trigger-external; - }; }; rtc@fffffd20 { diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi index 19fc748a87c5..2ab730fd6472 100644 --- a/arch/arm/boot/dts/at91sam9g45.dtsi +++ b/arch/arm/boot/dts/at91sam9g45.dtsi @@ -812,8 +812,6 @@ }; adc0: adc@fffb0000 { - #address-cells = <1>; - #size-cells = <0>; compatible = "atmel,at91sam9g45-adc"; reg = <0xfffb0000 0x100>; interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>; @@ -822,31 +820,6 @@ atmel,adc-channels-used = <0xff>; atmel,adc-vref = <3300>; atmel,adc-startup-time = <40>; - atmel,adc-res = <8 10>; - atmel,adc-res-names = "lowres", "highres"; - atmel,adc-use-res = "highres"; - - trigger0 { - trigger-name = "external-rising"; - trigger-value = <0x1>; - trigger-external; - }; - trigger1 { - trigger-name = "external-falling"; - trigger-value = <0x2>; - trigger-external; - }; - - trigger2 { - trigger-name = "external-any"; - trigger-value = <0x3>; - trigger-external; - }; - - trigger3 { - trigger-name = "continuous"; - trigger-value = <0x6>; - }; }; isi@fffb4000 { diff --git a/arch/arm/boot/dts/at91sam9rl.dtsi b/arch/arm/boot/dts/at91sam9rl.dtsi index 36a42a9fe195..730d1182c73e 100644 --- a/arch/arm/boot/dts/at91sam9rl.dtsi +++ b/arch/arm/boot/dts/at91sam9rl.dtsi @@ -266,8 +266,6 @@ }; adc0: adc@fffd0000 { - #address-cells = <1>; - #size-cells = <0>; compatible = "atmel,at91sam9rl-adc"; reg = <0xfffd0000 0x100>; interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>; @@ -277,32 +275,6 @@ atmel,adc-channels-used = <0x3f>; atmel,adc-vref = <3300>; atmel,adc-startup-time = <40>; - atmel,adc-res = <8 10>; - atmel,adc-res-names = "lowres", "highres"; - atmel,adc-use-res = "highres"; - - trigger0 { - trigger-name = "external-rising"; - trigger-value = <0x1>; - trigger-external; - }; - - trigger1 { - trigger-name = "external-falling"; - trigger-value = <0x2>; - trigger-external; - }; - - trigger2 { - trigger-name = "external-any"; - trigger-value = <0x3>; - trigger-external; - }; - - trigger3 { - trigger-name = "continuous"; - trigger-value = <0x6>; - }; }; usb0: gadget@fffd4000 { diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi index 4cdb05079cc7..395e883644cd 100644 --- a/arch/arm/boot/dts/at91sam9x5.dtsi +++ b/arch/arm/boot/dts/at91sam9x5.dtsi @@ -795,8 +795,6 @@ }; adc0: adc@f804c000 { - #address-cells = <1>; - #size-cells = <0>; compatible = "atmel,at91sam9x5-adc"; reg = <0xf804c000 0x100>; interrupts = <19 IRQ_TYPE_LEVEL_HIGH 0>; @@ -808,32 +806,6 @@ atmel,adc-vref = <3300>; atmel,adc-startup-time = <40>; atmel,adc-sample-hold-time = <11>; - atmel,adc-res = <8 10>; - atmel,adc-res-names = "lowres", "highres"; - atmel,adc-use-res = "highres"; - - trigger0 { - trigger-name = "external-rising"; - trigger-value = <0x1>; - trigger-external; - }; - - trigger1 { - trigger-name = "external-falling"; - trigger-value = <0x2>; - trigger-external; - }; - - trigger2 { - trigger-name = "external-any"; - trigger-value = <0x3>; - trigger-external; - }; - - trigger3 { - trigger-name = "continuous"; - trigger-value = <0x6>; - }; }; spi0: spi@f0000000 { diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi index bba2a3f41c42..7c979652f330 100644 --- a/arch/arm/boot/dts/sama5d3.dtsi +++ b/arch/arm/boot/dts/sama5d3.dtsi @@ -305,8 +305,6 @@ }; adc0: adc@f8018000 { - #address-cells = <1>; - #size-cells = <0>; compatible = "atmel,sama5d3-adc"; reg = <0xf8018000 0x100>; interrupts = <29 IRQ_TYPE_LEVEL_HIGH 5>; @@ -333,30 +331,8 @@ atmel,adc-startup-time = <40>; atmel,adc-use-external-triggers; atmel,adc-vref = <3000>; - atmel,adc-res = <10 12>; atmel,adc-sample-hold-time = <11>; - atmel,adc-res-names = "lowres", "highres"; status = "disabled"; - - trigger0 { - trigger-name = "external-rising"; - trigger-value = <0x1>; - trigger-external; - }; - trigger1 { - trigger-name = "external-falling"; - trigger-value = <0x2>; - trigger-external; - }; - trigger2 { - trigger-name = "external-any"; - trigger-value = <0x3>; - trigger-external; - }; - trigger3 { - trigger-name = "continuous"; - trigger-value = <0x6>; - }; }; i2c2: i2c@f801c000 { diff --git a/arch/arm/boot/dts/sama5d4.dtsi b/arch/arm/boot/dts/sama5d4.dtsi index 04f24cf752d3..05c55875835d 100644 --- a/arch/arm/boot/dts/sama5d4.dtsi +++ b/arch/arm/boot/dts/sama5d4.dtsi @@ -661,31 +661,9 @@ atmel,adc-startup-time = <40>; atmel,adc-use-external-triggers; atmel,adc-vref = <3000>; - atmel,adc-res = <8 10>; atmel,adc-sample-hold-time = <11>; - atmel,adc-res-names = "lowres", "highres"; atmel,adc-ts-pressure-threshold = <10000>; status = "disabled"; - - trigger0 { - trigger-name = "external-rising"; - trigger-value = <0x1>; - trigger-external; - }; - trigger1 { - trigger-name = "external-falling"; - trigger-value = <0x2>; - trigger-external; - }; - trigger2 { - trigger-name = "external-any"; - trigger-value = <0x3>; - trigger-external; - }; - trigger3 { - trigger-name = "continuous"; - trigger-value = <0x6>; - }; }; aes@fc044000 { -- cgit v1.2.3-59-g8ed1b From 7dc4c0b42d82d9b633663eadcd821f3a109af4e4 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 17 Nov 2020 21:11:05 +0100 Subject: ARM: dts: s3c24xx: add SMDK2416 board compatible Add a compatible for SMDK2416 board next to the SoC compatible. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20201117201106.128813-3-krzk@kernel.org --- arch/arm/boot/dts/s3c2416-smdk2416.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/s3c2416-smdk2416.dts b/arch/arm/boot/dts/s3c2416-smdk2416.dts index 47626ede6fdd..e7c379a9842e 100644 --- a/arch/arm/boot/dts/s3c2416-smdk2416.dts +++ b/arch/arm/boot/dts/s3c2416-smdk2416.dts @@ -10,7 +10,7 @@ / { model = "SMDK2416"; - compatible = "samsung,s3c2416"; + compatible = "samsung,smdk2416", "samsung,s3c2416"; memory@30000000 { device_type = "memory"; -- cgit v1.2.3-59-g8ed1b From 32ccdde0a794700f29d190eae77eb41f1b8926ce Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 17 Nov 2020 21:11:06 +0100 Subject: ARM: dts: s3c6410: correct SMDK6410 board compatible The SMDK6410 DTS was incorrectly called mini6410, probably copy-paste from FriendlyARM Mini6410 board. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20201117201106.128813-4-krzk@kernel.org --- arch/arm/boot/dts/s3c6410-smdk6410.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/s3c6410-smdk6410.dts b/arch/arm/boot/dts/s3c6410-smdk6410.dts index 69c9ec4cf381..581309e7f15e 100644 --- a/arch/arm/boot/dts/s3c6410-smdk6410.dts +++ b/arch/arm/boot/dts/s3c6410-smdk6410.dts @@ -17,7 +17,7 @@ / { model = "Samsung SMDK6410 board based on S3C6410"; - compatible = "samsung,mini6410", "samsung,s3c6410"; + compatible = "samsung,smdk6410", "samsung,s3c6410"; memory@50000000 { device_type = "memory"; -- cgit v1.2.3-59-g8ed1b From 7995fb896b9637a5f59a56ae0d8f2b7ca71a040d Mon Sep 17 00:00:00 2001 From: Marek Szyprowski Date: Wed, 2 Dec 2020 13:20:29 +0100 Subject: ARM: dts: exynos: Reduce assigned-clocks entries for SPI0 on Artik5 board Commit 2024b130b0c8 ("ARM: dts: exynos: Add Ethernet to Artik 5 board") added ethernet chip on SPI0 bus and the whole bunch of assigned clock entries to ensure proper clock rates and topology. Limit the assigned clock parents only to the direct clocks of the SPI0 device and assume that MPLL clock is already properly configured. The applied clock topology was incorrect as some clocks between were missing, what resulted in the following warning: clk: failed to reparent div_mpll_pre to mout_mpll: -22 Fixes: 2024b130b0c8 ("ARM: dts: exynos: Add Ethernet to Artik 5 board") Signed-off-by: Marek Szyprowski Link: https://lore.kernel.org/r/20201202122029.22198-1-m.szyprowski@samsung.com Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos3250-artik5-eval.dts | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/exynos3250-artik5-eval.dts b/arch/arm/boot/dts/exynos3250-artik5-eval.dts index 5461949d833e..a1e22f630638 100644 --- a/arch/arm/boot/dts/exynos3250-artik5-eval.dts +++ b/arch/arm/boot/dts/exynos3250-artik5-eval.dts @@ -42,12 +42,9 @@ status = "okay"; cs-gpios = <&gpx3 4 GPIO_ACTIVE_LOW>, <0>; - assigned-clocks = <&cmu CLK_MOUT_MPLL>, <&cmu CLK_DIV_MPLL_PRE>, - <&cmu CLK_MOUT_SPI0>, <&cmu CLK_DIV_SPI0>, + assigned-clocks = <&cmu CLK_MOUT_SPI0>, <&cmu CLK_DIV_SPI0>, <&cmu CLK_DIV_SPI0_PRE>, <&cmu CLK_SCLK_SPI0>; - assigned-clock-parents = <&cmu CLK_FOUT_MPLL>, /* for: CLK_MOUT_MPLL */ - <&cmu CLK_MOUT_MPLL>, /* for: CLK_DIV_MPLL_PRE */ - <&cmu CLK_DIV_MPLL_PRE>, /* for: CLK_MOUT_SPI0 */ + assigned-clock-parents = <&cmu CLK_DIV_MPLL_PRE>, /* for: CLK_MOUT_SPI0 */ <&cmu CLK_MOUT_SPI0>, /* for: CLK_DIV_SPI0 */ <&cmu CLK_DIV_SPI0>, /* for: CLK_DIV_SPI0_PRE */ <&cmu CLK_DIV_SPI0_PRE>; /* for: CLK_SCLK_SPI0 */ -- cgit v1.2.3-59-g8ed1b From ab8a9bb41b2c330a0b280280bf37b6f3b1dd1e58 Mon Sep 17 00:00:00 2001 From: Claudiu Beznea Date: Wed, 2 Dec 2020 11:57:04 +0200 Subject: ARM: dts: at91: sam9x60ek: remove bypass property atmel,osc-bypass property sets the bit 1 at main oscillator register. On SAM9X60 this bit is not valid according to datasheet (chapter 28.16.9 PMC Clock Generator Main Oscillator Register). Fixes: 1e5f532c2737 ("ARM: dts: at91: sam9x60: add device tree for soc and board") Signed-off-by: Claudiu Beznea Signed-off-by: Alexandre Belloni Acked-by: Nicolas Ferre Cc: Marco Cardellini Link: https://lore.kernel.org/r/1606903025-14197-2-git-send-email-claudiu.beznea@microchip.com --- arch/arm/boot/dts/at91-sam9x60ek.dts | 4 ---- 1 file changed, 4 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/at91-sam9x60ek.dts b/arch/arm/boot/dts/at91-sam9x60ek.dts index 0e3b6147069f..73b6b1f89de9 100644 --- a/arch/arm/boot/dts/at91-sam9x60ek.dts +++ b/arch/arm/boot/dts/at91-sam9x60ek.dts @@ -578,10 +578,6 @@ }; }; /* pinctrl */ -&pmc { - atmel,osc-bypass; -}; - &pwm0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm0_0 &pinctrl_pwm0_1 &pinctrl_pwm0_2 &pinctrl_pwm0_3>; -- cgit v1.2.3-59-g8ed1b From 9b5dcc8d427e2bcb84c49eb03ffefe11e7537a55 Mon Sep 17 00:00:00 2001 From: Claudiu Beznea Date: Wed, 2 Dec 2020 11:57:05 +0200 Subject: ARM: dts: at91: sama5d2: map securam as device Due to strobe signal not being propagated from CPU to securam the securam needs to be mapped as device or strongly ordered memory to work properly. Otherwise, updating to one offset may affect the adjacent locations in securam. Fixes: d4ce5f44d4409 ("ARM: dts: at91: sama5d2: Add securam node") Signed-off-by: Claudiu Beznea Signed-off-by: Alexandre Belloni Acked-by: Nicolas Ferre Link: https://lore.kernel.org/r/1606903025-14197-3-git-send-email-claudiu.beznea@microchip.com --- arch/arm/boot/dts/sama5d2.dtsi | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sama5d2.dtsi b/arch/arm/boot/dts/sama5d2.dtsi index 2ddc85dff8ce..6d399ac0385d 100644 --- a/arch/arm/boot/dts/sama5d2.dtsi +++ b/arch/arm/boot/dts/sama5d2.dtsi @@ -656,6 +656,7 @@ clocks = <&pmc PMC_TYPE_PERIPHERAL 51>; #address-cells = <1>; #size-cells = <1>; + no-memory-wc; ranges = <0 0xf8044000 0x1420>; }; -- cgit v1.2.3-59-g8ed1b From 85b8350ae99d1300eb6dc072459246c2649a8e50 Mon Sep 17 00:00:00 2001 From: Nicolas Ferre Date: Thu, 3 Dec 2020 10:19:49 +0100 Subject: ARM: dts: at91: sama5d2: fix CAN message ram offset and size CAN0 and CAN1 instances share the same message ram configured at 0x210000 on sama5d2 Linux systems. According to current configuration of CAN0, we need 0x1c00 bytes so that the CAN1 don't overlap its message ram: 64 x RX FIFO0 elements => 64 x 72 bytes 32 x TXE (TX Event FIFO) elements => 32 x 8 bytes 32 x TXB (TX Buffer) elements => 32 x 72 bytes So a total of 7168 bytes (0x1C00). Fix offset to match this needed size. Make the CAN0 message ram ioremap match exactly this size so that is easily understandable. Adapt CAN1 size accordingly. Fixes: bc6d5d7666b7 ("ARM: dts: at91: sama5d2: add m_can nodes") Reported-by: Dan Sneddon Signed-off-by: Nicolas Ferre Signed-off-by: Alexandre Belloni Tested-by: Cristian Birsan Cc: stable@vger.kernel.org # v4.13+ Link: https://lore.kernel.org/r/20201203091949.9015-1-nicolas.ferre@microchip.com --- arch/arm/boot/dts/sama5d2.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sama5d2.dtsi b/arch/arm/boot/dts/sama5d2.dtsi index 6d399ac0385d..2c4952427296 100644 --- a/arch/arm/boot/dts/sama5d2.dtsi +++ b/arch/arm/boot/dts/sama5d2.dtsi @@ -725,7 +725,7 @@ can0: can@f8054000 { compatible = "bosch,m_can"; - reg = <0xf8054000 0x4000>, <0x210000 0x4000>; + reg = <0xf8054000 0x4000>, <0x210000 0x1c00>; reg-names = "m_can", "message_ram"; interrupts = <56 IRQ_TYPE_LEVEL_HIGH 7>, <64 IRQ_TYPE_LEVEL_HIGH 7>; @@ -1131,7 +1131,7 @@ can1: can@fc050000 { compatible = "bosch,m_can"; - reg = <0xfc050000 0x4000>, <0x210000 0x4000>; + reg = <0xfc050000 0x4000>, <0x210000 0x3800>; reg-names = "m_can", "message_ram"; interrupts = <57 IRQ_TYPE_LEVEL_HIGH 7>, <65 IRQ_TYPE_LEVEL_HIGH 7>; @@ -1141,7 +1141,7 @@ assigned-clocks = <&pmc PMC_TYPE_GCK 57>; assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>; assigned-clock-rates = <40000000>; - bosch,mram-cfg = <0x1100 0 0 64 0 0 32 32>; + bosch,mram-cfg = <0x1c00 0 0 64 0 0 32 32>; status = "disabled"; }; -- cgit v1.2.3-59-g8ed1b From f3456b9fd269c6d0c973b136c5449d46b2510f4b Mon Sep 17 00:00:00 2001 From: Ard Biesheuvel Date: Thu, 26 Nov 2020 08:49:07 +0100 Subject: crypto: arm/aes-ce - work around Cortex-A57/A72 silion errata ARM Cortex-A57 and Cortex-A72 cores running in 32-bit mode are affected by silicon errata #1742098 and #1655431, respectively, where the second instruction of a AES instruction pair may execute twice if an interrupt is taken right after the first instruction consumes an input register of which a single 32-bit lane has been updated the last time it was modified. This is not such a rare occurrence as it may seem: in counter mode, only the least significant 32-bit word is incremented in the absence of a carry, which makes our counter mode implementation susceptible to these errata. So let's shuffle the counter assignments around a bit so that the most recent updates when the AES instruction pair executes are 128-bit wide. [0] ARM-EPM-049219 v23 Cortex-A57 MPCore Software Developers Errata Notice [1] ARM-EPM-012079 v11.0 Cortex-A72 MPCore Software Developers Errata Notice Cc: # v5.4+ Signed-off-by: Ard Biesheuvel Signed-off-by: Herbert Xu --- arch/arm/crypto/aes-ce-core.S | 32 ++++++++++++++++++++++---------- 1 file changed, 22 insertions(+), 10 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/crypto/aes-ce-core.S b/arch/arm/crypto/aes-ce-core.S index 4d1707388d94..312428d83eed 100644 --- a/arch/arm/crypto/aes-ce-core.S +++ b/arch/arm/crypto/aes-ce-core.S @@ -386,20 +386,32 @@ ENTRY(ce_aes_ctr_encrypt) .Lctrloop4x: subs r4, r4, #4 bmi .Lctr1x - add r6, r6, #1 + + /* + * NOTE: the sequence below has been carefully tweaked to avoid + * a silicon erratum that exists in Cortex-A57 (#1742098) and + * Cortex-A72 (#1655431) cores, where AESE/AESMC instruction pairs + * may produce an incorrect result if they take their input from a + * register of which a single 32-bit lane has been updated the last + * time it was modified. To work around this, the lanes of registers + * q0-q3 below are not manipulated individually, and the different + * counter values are prepared by successive manipulations of q7. + */ + add ip, r6, #1 vmov q0, q7 + rev ip, ip + add lr, r6, #2 + vmov s31, ip @ set lane 3 of q1 via q7 + add ip, r6, #3 + rev lr, lr vmov q1, q7 - rev ip, r6 - add r6, r6, #1 + vmov s31, lr @ set lane 3 of q2 via q7 + rev ip, ip vmov q2, q7 - vmov s7, ip - rev ip, r6 - add r6, r6, #1 + vmov s31, ip @ set lane 3 of q3 via q7 + add r6, r6, #4 vmov q3, q7 - vmov s11, ip - rev ip, r6 - add r6, r6, #1 - vmov s15, ip + vld1.8 {q4-q5}, [r1]! vld1.8 {q6}, [r1]! vld1.8 {q15}, [r1]! -- cgit v1.2.3-59-g8ed1b From 68061c02bb295da4955f0d309b9459f0a7ba83dd Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Fri, 4 Dec 2020 17:59:22 +0100 Subject: ARM: highmem: Fix cache_is_vivt() reference The reference to cache_is_vivt() was moved into a header file, which now causes a build failure in rare randconfig builds: arch/arm/include/asm/highmem.h:52:43: error: implicit declaration of function 'cache_is_vivt' [-Werror,-Wimplicit-function-declaration] Add an explicit include to make it build reliably. Fixes: 2a15ba82fa6c ("ARM: highmem: Switch to generic kmap atomic") Signed-off-by: Arnd Bergmann Signed-off-by: Thomas Gleixner Cc: Russell King Cc: Andrew Morton Cc: Ira Weiny Cc: linux-arm-kernel@lists.infradead.org Link: https://lore.kernel.org/r/20201204165930.3877571-1-arnd@kernel.org --- arch/arm/include/asm/highmem.h | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm') diff --git a/arch/arm/include/asm/highmem.h b/arch/arm/include/asm/highmem.h index a41de523d053..b4b66220952d 100644 --- a/arch/arm/include/asm/highmem.h +++ b/arch/arm/include/asm/highmem.h @@ -2,6 +2,7 @@ #ifndef _ASM_HIGHMEM_H #define _ASM_HIGHMEM_H +#include #include #define PKMAP_BASE (PAGE_OFFSET - PMD_SIZE) -- cgit v1.2.3-59-g8ed1b From aac82707fa4593b99053fa9ebb2e73d8103130ed Mon Sep 17 00:00:00 2001 From: Troy Lee Date: Mon, 7 Dec 2020 17:00:12 +0800 Subject: ARM: dts: aspeed: Add AST2600 EDAC into common devicetree Add Aspeed AST2600 EDAC node into the common devicetree. Signed-off-by: Troy Lee Signed-off-by: Borislav Petkov Reviewed-by: Joel Stanley Link: https://lkml.kernel.org/r/20201207090013.14145-2-troy_lee@aspeedtech.com --- arch/arm/boot/dts/aspeed-g6.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed-g6.dtsi index b58220a49cbd..74367ee96f20 100644 --- a/arch/arm/boot/dts/aspeed-g6.dtsi +++ b/arch/arm/boot/dts/aspeed-g6.dtsi @@ -69,6 +69,12 @@ always-on; }; + edac: sdram@1e6e0000 { + compatible = "aspeed,ast2600-sdram-edac", "syscon"; + reg = <0x1e6e0000 0x174>; + interrupts = ; + }; + ahb { compatible = "simple-bus"; #address-cells = <1>; -- cgit v1.2.3-59-g8ed1b From 656ab1bdcd2b755dc161a9774201100d5bf74b8d Mon Sep 17 00:00:00 2001 From: Stefan Agner Date: Mon, 7 Dec 2020 18:58:01 +0100 Subject: ARM: dts: meson: fix PHY deassert timing requirements According to the datasheet (Rev. 1.9) the RTL8211F requires at least 72ms "for internal circuits settling time" before accessing the PHY registers. On similar boards with the same PHY this fixes an issue where Ethernet link would not come up when using ip link set down/up. Fixes: a2c6e82e5341 ("ARM: dts: meson: switch to the generic Ethernet PHY reset bindings") Reviewed-by: Martin Blumenstingl Tested-by: Martin Blumenstingl # on Odroid-C1+ Signed-off-by: Stefan Agner Signed-off-by: Kevin Hilman Link: https://lore.kernel.org/r/ff78772b306411e145769c46d4090554344db41e.1607363522.git.stefan@agner.ch --- arch/arm/boot/dts/meson8b-odroidc1.dts | 2 +- arch/arm/boot/dts/meson8m2-mxiii-plus.dts | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/meson8b-odroidc1.dts b/arch/arm/boot/dts/meson8b-odroidc1.dts index 0c26467de4d0..5963566dbcc9 100644 --- a/arch/arm/boot/dts/meson8b-odroidc1.dts +++ b/arch/arm/boot/dts/meson8b-odroidc1.dts @@ -224,7 +224,7 @@ reg = <0>; reset-assert-us = <10000>; - reset-deassert-us = <30000>; + reset-deassert-us = <80000>; reset-gpios = <&gpio GPIOH_4 GPIO_ACTIVE_LOW>; interrupt-parent = <&gpio_intc>; diff --git a/arch/arm/boot/dts/meson8m2-mxiii-plus.dts b/arch/arm/boot/dts/meson8m2-mxiii-plus.dts index cc498191ddd1..8f4eb1ed4581 100644 --- a/arch/arm/boot/dts/meson8m2-mxiii-plus.dts +++ b/arch/arm/boot/dts/meson8m2-mxiii-plus.dts @@ -81,7 +81,7 @@ reg = <0>; reset-assert-us = <10000>; - reset-deassert-us = <30000>; + reset-deassert-us = <80000>; reset-gpios = <&gpio GPIOH_4 GPIO_ACTIVE_LOW>; }; }; -- cgit v1.2.3-59-g8ed1b From 28187dc8ebd938d574edfc6d9e0f9c51c21ff3f4 Mon Sep 17 00:00:00 2001 From: Nick Desaulniers Date: Tue, 17 Nov 2020 00:46:39 +0100 Subject: ARM: 9025/1: Kconfig: CPU_BIG_ENDIAN depends on !LD_IS_LLD LLD does not yet support any big endian architectures. Make this config non-selectable when using LLD until LLD is fixed. Link: https://github.com/ClangBuiltLinux/linux/issues/965 Signed-off-by: Nick Desaulniers Tested-by: Nathan Chancellor Reviewed-by: Nathan Chancellor Reported-by: kbuild test robot Signed-off-by: Russell King --- arch/arm/mm/Kconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm') diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig index 65e4482e3849..02692fbe2db5 100644 --- a/arch/arm/mm/Kconfig +++ b/arch/arm/mm/Kconfig @@ -743,6 +743,7 @@ config SWP_EMULATE config CPU_BIG_ENDIAN bool "Build big-endian kernel" depends on ARCH_SUPPORTS_BIG_ENDIAN + depends on !LD_IS_LLD help Say Y if you plan on running a kernel in big-endian mode. Note that your board must be properly built and your board -- cgit v1.2.3-59-g8ed1b From 331b9d02d77e0e33f273d8328d9f5453efddd926 Mon Sep 17 00:00:00 2001 From: Nick Desaulniers Date: Tue, 17 Nov 2020 00:49:25 +0100 Subject: ARM: 9026/1: unwind: remove old check for GCC <= 4.2 Since commit 0bddd227f3dc ("Documentation: update for gcc 4.9 requirement") the minimum supported version of GCC is gcc-4.9. It's now safe to remove this code. Link: https://github.com/ClangBuiltLinux/linux/issues/427 Signed-off-by: Nick Desaulniers Reviewed-by: Nathan Chancellor Signed-off-by: Russell King --- arch/arm/kernel/unwind.c | 3 --- 1 file changed, 3 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/kernel/unwind.c b/arch/arm/kernel/unwind.c index f35eb584a18a..59fdf257bf8b 100644 --- a/arch/arm/kernel/unwind.c +++ b/arch/arm/kernel/unwind.c @@ -18,9 +18,6 @@ #warning Your compiler does not have EABI support. #warning ARM unwind is known to compile only with EABI compilers. #warning Change compiler or disable ARM_UNWIND option. -#elif (__GNUC__ == 4 && __GNUC_MINOR__ <= 2) && !defined(__clang__) -#warning Your compiler is too buggy; it is known to not compile ARM unwind support. -#warning Change compiler or disable ARM_UNWIND option. #endif #endif /* __CHECKER__ */ -- cgit v1.2.3-59-g8ed1b From 4d576cab16f57e1f87978f6997a725179398341e Mon Sep 17 00:00:00 2001 From: Ard Biesheuvel Date: Tue, 17 Nov 2020 10:23:28 +0100 Subject: ARM: 9028/1: disable KASAN in call stack capturing routines KASAN uses the routines in stacktrace.c to capture the call stack each time memory gets allocated or freed. Some of these routines are also used to log CPU and memory context when exceptions are taken, and so in some cases, memory accesses may be made that are not strictly in line with the KASAN constraints, and may therefore trigger false KASAN positives. So follow the example set by other architectures, and simply disable KASAN instrumentation for these routines. Reviewed-by: Linus Walleij Signed-off-by: Ard Biesheuvel Signed-off-by: Russell King --- arch/arm/kernel/Makefile | 3 +++ 1 file changed, 3 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile index 89e5d864e923..f6431b46866e 100644 --- a/arch/arm/kernel/Makefile +++ b/arch/arm/kernel/Makefile @@ -21,6 +21,9 @@ obj-y := elf.o entry-common.o irq.o opcodes.o \ setup.o signal.o sigreturn_codes.o \ stacktrace.o sys_arm.o time.o traps.o +KASAN_SANITIZE_stacktrace.o := n +KASAN_SANITIZE_traps.o := n + ifneq ($(CONFIG_ARM_UNWIND),y) obj-$(CONFIG_FRAME_POINTER) += return_address.o endif -- cgit v1.2.3-59-g8ed1b From 3c9f5708b7aed6a963e2aefccbd1854802de163e Mon Sep 17 00:00:00 2001 From: Jian Cai Date: Tue, 17 Nov 2020 23:11:36 +0100 Subject: ARM: 9029/1: Make iwmmxt.S support Clang's integrated assembler This patch replaces 6 IWMMXT instructions Clang's integrated assembler does not support in iwmmxt.S using macros, while making sure GNU assembler still emit the same instructions. This should be easier than providing full IWMMXT support in Clang. This is one of the last bits of kernel code that could be compiled but not assembled with clang. Once all of it works with IAS, we no longer need to special-case 32-bit Arm in Kbuild, or turn off CONFIG_IWMMXT when build-testing. "Intel Wireless MMX Technology - Developer Guide - August, 2002" should be referenced for the encoding schemes of these extensions. Link: https://github.com/ClangBuiltLinux/linux/issues/975 Suggested-by: Nick Desaulniers Suggested-by: Ard Biesheuvel Acked-by: Ard Biesheuvel Reviewed-by: Nick Desaulniers Tested-by: Nick Desaulniers Signed-off-by: Jian Cai Signed-off-by: Russell King --- arch/arm/kernel/iwmmxt.S | 89 ++++++++++++++++++++++++------------------------ arch/arm/kernel/iwmmxt.h | 47 +++++++++++++++++++++++++ 2 files changed, 92 insertions(+), 44 deletions(-) create mode 100644 arch/arm/kernel/iwmmxt.h (limited to 'arch/arm') diff --git a/arch/arm/kernel/iwmmxt.S b/arch/arm/kernel/iwmmxt.S index 0dcae787b004..d2b4ac06e4ed 100644 --- a/arch/arm/kernel/iwmmxt.S +++ b/arch/arm/kernel/iwmmxt.S @@ -16,6 +16,7 @@ #include #include #include +#include "iwmmxt.h" #if defined(CONFIG_CPU_PJ4) || defined(CONFIG_CPU_PJ4B) #define PJ4(code...) code @@ -113,33 +114,33 @@ concan_save: concan_dump: - wstrw wCSSF, [r1, #MMX_WCSSF] - wstrw wCASF, [r1, #MMX_WCASF] - wstrw wCGR0, [r1, #MMX_WCGR0] - wstrw wCGR1, [r1, #MMX_WCGR1] - wstrw wCGR2, [r1, #MMX_WCGR2] - wstrw wCGR3, [r1, #MMX_WCGR3] + wstrw wCSSF, r1, MMX_WCSSF + wstrw wCASF, r1, MMX_WCASF + wstrw wCGR0, r1, MMX_WCGR0 + wstrw wCGR1, r1, MMX_WCGR1 + wstrw wCGR2, r1, MMX_WCGR2 + wstrw wCGR3, r1, MMX_WCGR3 1: @ MUP? wRn tst r2, #0x2 beq 2f - wstrd wR0, [r1, #MMX_WR0] - wstrd wR1, [r1, #MMX_WR1] - wstrd wR2, [r1, #MMX_WR2] - wstrd wR3, [r1, #MMX_WR3] - wstrd wR4, [r1, #MMX_WR4] - wstrd wR5, [r1, #MMX_WR5] - wstrd wR6, [r1, #MMX_WR6] - wstrd wR7, [r1, #MMX_WR7] - wstrd wR8, [r1, #MMX_WR8] - wstrd wR9, [r1, #MMX_WR9] - wstrd wR10, [r1, #MMX_WR10] - wstrd wR11, [r1, #MMX_WR11] - wstrd wR12, [r1, #MMX_WR12] - wstrd wR13, [r1, #MMX_WR13] - wstrd wR14, [r1, #MMX_WR14] - wstrd wR15, [r1, #MMX_WR15] + wstrd wR0, r1, MMX_WR0 + wstrd wR1, r1, MMX_WR1 + wstrd wR2, r1, MMX_WR2 + wstrd wR3, r1, MMX_WR3 + wstrd wR4, r1, MMX_WR4 + wstrd wR5, r1, MMX_WR5 + wstrd wR6, r1, MMX_WR6 + wstrd wR7, r1, MMX_WR7 + wstrd wR8, r1, MMX_WR8 + wstrd wR9, r1, MMX_WR9 + wstrd wR10, r1, MMX_WR10 + wstrd wR11, r1, MMX_WR11 + wstrd wR12, r1, MMX_WR12 + wstrd wR13, r1, MMX_WR13 + wstrd wR14, r1, MMX_WR14 + wstrd wR15, r1, MMX_WR15 2: teq r0, #0 @ anything to load? reteq lr @ if not, return @@ -147,30 +148,30 @@ concan_dump: concan_load: @ Load wRn - wldrd wR0, [r0, #MMX_WR0] - wldrd wR1, [r0, #MMX_WR1] - wldrd wR2, [r0, #MMX_WR2] - wldrd wR3, [r0, #MMX_WR3] - wldrd wR4, [r0, #MMX_WR4] - wldrd wR5, [r0, #MMX_WR5] - wldrd wR6, [r0, #MMX_WR6] - wldrd wR7, [r0, #MMX_WR7] - wldrd wR8, [r0, #MMX_WR8] - wldrd wR9, [r0, #MMX_WR9] - wldrd wR10, [r0, #MMX_WR10] - wldrd wR11, [r0, #MMX_WR11] - wldrd wR12, [r0, #MMX_WR12] - wldrd wR13, [r0, #MMX_WR13] - wldrd wR14, [r0, #MMX_WR14] - wldrd wR15, [r0, #MMX_WR15] + wldrd wR0, r0, MMX_WR0 + wldrd wR1, r0, MMX_WR1 + wldrd wR2, r0, MMX_WR2 + wldrd wR3, r0, MMX_WR3 + wldrd wR4, r0, MMX_WR4 + wldrd wR5, r0, MMX_WR5 + wldrd wR6, r0, MMX_WR6 + wldrd wR7, r0, MMX_WR7 + wldrd wR8, r0, MMX_WR8 + wldrd wR9, r0, MMX_WR9 + wldrd wR10, r0, MMX_WR10 + wldrd wR11, r0, MMX_WR11 + wldrd wR12, r0, MMX_WR12 + wldrd wR13, r0, MMX_WR13 + wldrd wR14, r0, MMX_WR14 + wldrd wR15, r0, MMX_WR15 @ Load wCx - wldrw wCSSF, [r0, #MMX_WCSSF] - wldrw wCASF, [r0, #MMX_WCASF] - wldrw wCGR0, [r0, #MMX_WCGR0] - wldrw wCGR1, [r0, #MMX_WCGR1] - wldrw wCGR2, [r0, #MMX_WCGR2] - wldrw wCGR3, [r0, #MMX_WCGR3] + wldrw wCSSF, r0, MMX_WCSSF + wldrw wCASF, r0, MMX_WCASF + wldrw wCGR0, r0, MMX_WCGR0 + wldrw wCGR1, r0, MMX_WCGR1 + wldrw wCGR2, r0, MMX_WCGR2 + wldrw wCGR3, r0, MMX_WCGR3 @ clear CUP/MUP (only if r1 != 0) teq r1, #0 diff --git a/arch/arm/kernel/iwmmxt.h b/arch/arm/kernel/iwmmxt.h new file mode 100644 index 000000000000..fb627286f5bb --- /dev/null +++ b/arch/arm/kernel/iwmmxt.h @@ -0,0 +1,47 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#ifndef __IWMMXT_H__ +#define __IWMMXT_H__ + +.irp b, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 +.set .LwR\b, \b +.set .Lr\b, \b +.endr + +.set .LwCSSF, 0x2 +.set .LwCASF, 0x3 +.set .LwCGR0, 0x8 +.set .LwCGR1, 0x9 +.set .LwCGR2, 0xa +.set .LwCGR3, 0xb + +.macro wldrd, reg:req, base:req, offset:req +.inst 0xedd00100 | (.L\reg << 12) | (.L\base << 16) | (\offset >> 2) +.endm + +.macro wldrw, reg:req, base:req, offset:req +.inst 0xfd900100 | (.L\reg << 12) | (.L\base << 16) | (\offset >> 2) +.endm + +.macro wstrd, reg:req, base:req, offset:req +.inst 0xedc00100 | (.L\reg << 12) | (.L\base << 16) | (\offset >> 2) +.endm + +.macro wstrw, reg:req, base:req, offset:req +.inst 0xfd800100 | (.L\reg << 12) | (.L\base << 16) | (\offset >> 2) +.endm + +#ifdef __clang__ + +#define wCon c1 + +.macro tmrc, dest:req, control:req +mrc p1, 0, \dest, \control, c0, 0 +.endm + +.macro tmcr, control:req, src:req +mcr p1, 0, \src, \control, c0, 0 +.endm +#endif + +#endif -- cgit v1.2.3-59-g8ed1b From f77ac2e378be9dd61eb88728f0840642f045d9d1 Mon Sep 17 00:00:00 2001 From: Ard Biesheuvel Date: Thu, 19 Nov 2020 18:09:16 +0100 Subject: ARM: 9030/1: entry: omit FP emulation for UND exceptions taken in kernel mode There are a couple of problems with the exception entry code that deals with FP exceptions (which are reported as UND exceptions) when building the kernel in Thumb2 mode: - the conditional branch to vfp_kmode_exception in vfp_support_entry() may be out of range for its target, depending on how the linker decides to arrange the sections; - when the UND exception is taken in kernel mode, the emulation handling logic is entered via the 'call_fpe' label, which means we end up using the wrong value/mask pairs to match and detect the NEON opcodes. Since UND exceptions in kernel mode are unlikely to occur on a hot path (as opposed to the user mode version which is invoked for VFP support code and lazy restore), we can use the existing undef hook machinery for any kernel mode instruction emulation that is needed, including calling the existing vfp_kmode_exception() routine for unexpected cases. So drop the call to call_fpe, and instead, install an undef hook that will get called for NEON and VFP instructions that trigger an UND exception in kernel mode. While at it, make sure that the PC correction is accurate for the execution mode where the exception was taken, by checking the PSR Thumb bit. Cc: Dmitry Osipenko Cc: Kees Cook Fixes: eff8728fe698 ("vmlinux.lds.h: Add PGO and AutoFDO input sections") Signed-off-by: Ard Biesheuvel Reviewed-by: Linus Walleij Reviewed-by: Nick Desaulniers Signed-off-by: Russell King --- arch/arm/kernel/entry-armv.S | 25 ++-------------------- arch/arm/vfp/vfphw.S | 5 ----- arch/arm/vfp/vfpmodule.c | 49 ++++++++++++++++++++++++++++++++++++++++++-- 3 files changed, 49 insertions(+), 30 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S index c4220f51fcf3..0ea8529a4872 100644 --- a/arch/arm/kernel/entry-armv.S +++ b/arch/arm/kernel/entry-armv.S @@ -252,31 +252,10 @@ __und_svc: #else svc_entry #endif - @ - @ call emulation code, which returns using r9 if it has emulated - @ the instruction, or the more conventional lr if we are to treat - @ this as a real undefined instruction - @ - @ r0 - instruction - @ -#ifndef CONFIG_THUMB2_KERNEL - ldr r0, [r4, #-4] -#else - mov r1, #2 - ldrh r0, [r4, #-2] @ Thumb instruction at LR - 2 - cmp r0, #0xe800 @ 32-bit instruction if xx >= 0 - blo __und_svc_fault - ldrh r9, [r4] @ bottom 16 bits - add r4, r4, #2 - str r4, [sp, #S_PC] - orr r0, r9, r0, lsl #16 -#endif - badr r9, __und_svc_finish - mov r2, r4 - bl call_fpe mov r1, #4 @ PC correction to apply -__und_svc_fault: + THUMB( tst r5, #PSR_T_BIT ) @ exception taken in Thumb mode? + THUMB( movne r1, #2 ) @ if so, fix up PC correction mov r0, sp @ struct pt_regs *regs bl __und_fault diff --git a/arch/arm/vfp/vfphw.S b/arch/arm/vfp/vfphw.S index 4fcff9f59947..d5837bf05a9a 100644 --- a/arch/arm/vfp/vfphw.S +++ b/arch/arm/vfp/vfphw.S @@ -79,11 +79,6 @@ ENTRY(vfp_support_entry) DBGSTR3 "instr %08x pc %08x state %p", r0, r2, r10 .fpu vfpv2 - ldr r3, [sp, #S_PSR] @ Neither lazy restore nor FP exceptions - and r3, r3, #MODE_MASK @ are supported in kernel mode - teq r3, #USR_MODE - bne vfp_kmode_exception @ Returns through lr - VFPFMRX r1, FPEXC @ Is the VFP enabled? DBGSTR1 "fpexc %08x", r1 tst r1, #FPEXC_EN diff --git a/arch/arm/vfp/vfpmodule.c b/arch/arm/vfp/vfpmodule.c index 8c9e7f9f0277..c3b6451c18bd 100644 --- a/arch/arm/vfp/vfpmodule.c +++ b/arch/arm/vfp/vfpmodule.c @@ -23,6 +23,7 @@ #include #include #include +#include #include #include "vfpinstr.h" @@ -642,7 +643,9 @@ static int vfp_starting_cpu(unsigned int unused) return 0; } -void vfp_kmode_exception(void) +#ifdef CONFIG_KERNEL_MODE_NEON + +static int vfp_kmode_exception(struct pt_regs *regs, unsigned int instr) { /* * If we reach this point, a floating point exception has been raised @@ -660,9 +663,51 @@ void vfp_kmode_exception(void) pr_crit("BUG: unsupported FP instruction in kernel mode\n"); else pr_crit("BUG: FP instruction issued in kernel mode with FP unit disabled\n"); + pr_crit("FPEXC == 0x%08x\n", fmrx(FPEXC)); + return 1; } -#ifdef CONFIG_KERNEL_MODE_NEON +static struct undef_hook vfp_kmode_exception_hook[] = {{ + .instr_mask = 0xfe000000, + .instr_val = 0xf2000000, + .cpsr_mask = MODE_MASK | PSR_T_BIT, + .cpsr_val = SVC_MODE, + .fn = vfp_kmode_exception, +}, { + .instr_mask = 0xff100000, + .instr_val = 0xf4000000, + .cpsr_mask = MODE_MASK | PSR_T_BIT, + .cpsr_val = SVC_MODE, + .fn = vfp_kmode_exception, +}, { + .instr_mask = 0xef000000, + .instr_val = 0xef000000, + .cpsr_mask = MODE_MASK | PSR_T_BIT, + .cpsr_val = SVC_MODE | PSR_T_BIT, + .fn = vfp_kmode_exception, +}, { + .instr_mask = 0xff100000, + .instr_val = 0xf9000000, + .cpsr_mask = MODE_MASK | PSR_T_BIT, + .cpsr_val = SVC_MODE | PSR_T_BIT, + .fn = vfp_kmode_exception, +}, { + .instr_mask = 0x0c000e00, + .instr_val = 0x0c000a00, + .cpsr_mask = MODE_MASK, + .cpsr_val = SVC_MODE, + .fn = vfp_kmode_exception, +}}; + +static int __init vfp_kmode_exception_hook_init(void) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(vfp_kmode_exception_hook); i++) + register_undef_hook(&vfp_kmode_exception_hook[i]); + return 0; +} +core_initcall(vfp_kmode_exception_hook_init); /* * Kernel-side NEON support functions -- cgit v1.2.3-59-g8ed1b From e64ab473dddaffdfc4bd0b385204f472f2cb00d6 Mon Sep 17 00:00:00 2001 From: Nicolas Pitre Date: Mon, 30 Nov 2020 22:42:36 +0100 Subject: ARM: 9034/1: __div64_32(): straighten up inline asm constraints The ARM version of __div64_32() encapsulates a call to __do_div64 with non-standard argument passing. In particular, __n is a 64-bit input argument assigned to r0-r1 and __rem is an output argument sharing half of that r0-r1 register pair. With __n being an input argument, the compiler is in its right to presume that r0-r1 would still hold the value of __n past the inline assembly statement. Normally, the compiler would have assigned non overlapping registers to __n and __rem if the value for __n is needed again. However, here we enforce our own register assignment and gcc fails to notice the conflict. In practice this doesn't cause any problem as __n is considered dead after the asm statement and *n is overwritten. However this is not always guaranteed and clang rightfully complains. Let's fix it properly by making __n into an input-output variable. This makes it clear that those registers representing __n have been modified. Then we can extract __rem as the high part of __n with plain C code. This asm constraint "abuse" was likely relied upon back when gcc didn't handle 64-bit values optimally. Turns out that gcc is now able to optimize things and produces the same code with this patch applied. Reported-by: Antony Yu Signed-off-by: Nicolas Pitre Reviewed-by: Ard Biesheuvel Tested-by: Ard Biesheuvel Signed-off-by: Russell King --- arch/arm/include/asm/div64.h | 21 ++++++--------------- 1 file changed, 6 insertions(+), 15 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/include/asm/div64.h b/arch/arm/include/asm/div64.h index 898e9c78a7e7..595e538f5bfb 100644 --- a/arch/arm/include/asm/div64.h +++ b/arch/arm/include/asm/div64.h @@ -21,29 +21,20 @@ * assembly implementation with completely non standard calling convention * for arguments and results (beware). */ - -#ifdef __ARMEB__ -#define __xh "r0" -#define __xl "r1" -#else -#define __xl "r0" -#define __xh "r1" -#endif - static inline uint32_t __div64_32(uint64_t *n, uint32_t base) { register unsigned int __base asm("r4") = base; register unsigned long long __n asm("r0") = *n; register unsigned long long __res asm("r2"); - register unsigned int __rem asm(__xh); - asm( __asmeq("%0", __xh) + unsigned int __rem; + asm( __asmeq("%0", "r0") __asmeq("%1", "r2") - __asmeq("%2", "r0") - __asmeq("%3", "r4") + __asmeq("%2", "r4") "bl __do_div64" - : "=r" (__rem), "=r" (__res) - : "r" (__n), "r" (__base) + : "+r" (__n), "=r" (__res) + : "r" (__base) : "ip", "lr", "cc"); + __rem = __n >> 32; *n = __res; return __rem; } -- cgit v1.2.3-59-g8ed1b From 0437141b4e2233ae0109a9584e7a003cd05b0a20 Mon Sep 17 00:00:00 2001 From: Andrey Zhizhikin Date: Tue, 1 Dec 2020 22:29:18 +0000 Subject: ARM: configs: drop unused BACKLIGHT_GENERIC option Commit 7ecdea4a0226 ("backlight: generic_bl: Remove this driver as it is unused") removed geenric_bl driver from the tree, together with corresponding config option. Remove BACKLIGHT_GENERIC config item from all ARM configurations. Fixes: 7ecdea4a0226 ("backlight: generic_bl: Remove this driver as it is unused") Signed-off-by: Andrey Zhizhikin Reviewed-by: Krzysztof Kozlowski Acked-by: Alexandre Belloni Acked-by: Daniel Thompson Acked-by: Sam Ravnborg Cc: Sam Ravnborg Link: https://lore.kernel.org/r/20201201222922.3183-2-andrey.zhizhikin@leica-geosystems.com' Signed-off-by: Arnd Bergmann --- arch/arm/configs/at91_dt_defconfig | 1 - arch/arm/configs/cm_x300_defconfig | 1 - arch/arm/configs/colibri_pxa300_defconfig | 1 - arch/arm/configs/jornada720_defconfig | 1 - arch/arm/configs/magician_defconfig | 1 - arch/arm/configs/mini2440_defconfig | 1 - arch/arm/configs/omap2plus_defconfig | 1 - arch/arm/configs/pxa3xx_defconfig | 1 - arch/arm/configs/qcom_defconfig | 1 - arch/arm/configs/sama5_defconfig | 1 - arch/arm/configs/sunxi_defconfig | 1 - arch/arm/configs/tegra_defconfig | 1 - 12 files changed, 12 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/configs/at91_dt_defconfig b/arch/arm/configs/at91_dt_defconfig index 91f0f2c41841..c0c219d53b24 100644 --- a/arch/arm/configs/at91_dt_defconfig +++ b/arch/arm/configs/at91_dt_defconfig @@ -137,7 +137,6 @@ CONFIG_DRM_ATMEL_HLCDC=y CONFIG_DRM_PANEL_SIMPLE=y CONFIG_FB_ATMEL=y CONFIG_BACKLIGHT_ATMEL_LCDC=y -# CONFIG_BACKLIGHT_GENERIC is not set CONFIG_BACKLIGHT_PWM=y CONFIG_FRAMEBUFFER_CONSOLE=y CONFIG_LOGO=y diff --git a/arch/arm/configs/cm_x300_defconfig b/arch/arm/configs/cm_x300_defconfig index 2f7acde2d921..502a9d870ca4 100644 --- a/arch/arm/configs/cm_x300_defconfig +++ b/arch/arm/configs/cm_x300_defconfig @@ -87,7 +87,6 @@ CONFIG_FB=y CONFIG_FB_PXA=y CONFIG_LCD_CLASS_DEVICE=y CONFIG_LCD_TDO24M=y -# CONFIG_BACKLIGHT_GENERIC is not set CONFIG_BACKLIGHT_DA903X=m CONFIG_FRAMEBUFFER_CONSOLE=y CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y diff --git a/arch/arm/configs/colibri_pxa300_defconfig b/arch/arm/configs/colibri_pxa300_defconfig index 0dae3b185284..26e5a67f8e2d 100644 --- a/arch/arm/configs/colibri_pxa300_defconfig +++ b/arch/arm/configs/colibri_pxa300_defconfig @@ -34,7 +34,6 @@ CONFIG_FB=y CONFIG_FB_PXA=y # CONFIG_LCD_CLASS_DEVICE is not set CONFIG_BACKLIGHT_CLASS_DEVICE=y -# CONFIG_BACKLIGHT_GENERIC is not set # CONFIG_VGA_CONSOLE is not set CONFIG_FRAMEBUFFER_CONSOLE=y CONFIG_LOGO=y diff --git a/arch/arm/configs/jornada720_defconfig b/arch/arm/configs/jornada720_defconfig index 9f079be2b84b..069f60ffdcd8 100644 --- a/arch/arm/configs/jornada720_defconfig +++ b/arch/arm/configs/jornada720_defconfig @@ -48,7 +48,6 @@ CONFIG_FB=y CONFIG_FB_S1D13XXX=y CONFIG_LCD_CLASS_DEVICE=y CONFIG_BACKLIGHT_CLASS_DEVICE=y -# CONFIG_BACKLIGHT_GENERIC is not set # CONFIG_VGA_CONSOLE is not set CONFIG_FRAMEBUFFER_CONSOLE=y CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y diff --git a/arch/arm/configs/magician_defconfig b/arch/arm/configs/magician_defconfig index d2e684f6565a..b4670d42f378 100644 --- a/arch/arm/configs/magician_defconfig +++ b/arch/arm/configs/magician_defconfig @@ -95,7 +95,6 @@ CONFIG_FB_PXA_OVERLAY=y CONFIG_FB_W100=y CONFIG_LCD_CLASS_DEVICE=y CONFIG_BACKLIGHT_CLASS_DEVICE=y -# CONFIG_BACKLIGHT_GENERIC is not set CONFIG_BACKLIGHT_PWM=y # CONFIG_VGA_CONSOLE is not set CONFIG_FRAMEBUFFER_CONSOLE=y diff --git a/arch/arm/configs/mini2440_defconfig b/arch/arm/configs/mini2440_defconfig index 301f29a1fcc3..898490aaa39e 100644 --- a/arch/arm/configs/mini2440_defconfig +++ b/arch/arm/configs/mini2440_defconfig @@ -158,7 +158,6 @@ CONFIG_FB_S3C2410=y CONFIG_LCD_CLASS_DEVICE=y CONFIG_LCD_PLATFORM=y CONFIG_BACKLIGHT_CLASS_DEVICE=y -# CONFIG_BACKLIGHT_GENERIC is not set CONFIG_BACKLIGHT_PWM=y CONFIG_FRAMEBUFFER_CONSOLE=y CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y diff --git a/arch/arm/configs/omap2plus_defconfig b/arch/arm/configs/omap2plus_defconfig index 77716f500813..ba2b3f89c0fa 100644 --- a/arch/arm/configs/omap2plus_defconfig +++ b/arch/arm/configs/omap2plus_defconfig @@ -390,7 +390,6 @@ CONFIG_FB_TILEBLITTING=y CONFIG_LCD_CLASS_DEVICE=y CONFIG_LCD_PLATFORM=y CONFIG_BACKLIGHT_CLASS_DEVICE=y -CONFIG_BACKLIGHT_GENERIC=m CONFIG_BACKLIGHT_PWM=m CONFIG_BACKLIGHT_PANDORA=m CONFIG_BACKLIGHT_GPIO=m diff --git a/arch/arm/configs/pxa3xx_defconfig b/arch/arm/configs/pxa3xx_defconfig index 06bbc7a59b60..f0c34017f2aa 100644 --- a/arch/arm/configs/pxa3xx_defconfig +++ b/arch/arm/configs/pxa3xx_defconfig @@ -74,7 +74,6 @@ CONFIG_FB_PXA=y CONFIG_LCD_CLASS_DEVICE=y CONFIG_LCD_TDO24M=y CONFIG_BACKLIGHT_CLASS_DEVICE=y -# CONFIG_BACKLIGHT_GENERIC is not set CONFIG_BACKLIGHT_DA903X=y # CONFIG_VGA_CONSOLE is not set CONFIG_FRAMEBUFFER_CONSOLE=y diff --git a/arch/arm/configs/qcom_defconfig b/arch/arm/configs/qcom_defconfig index c882167e1496..d6733e745b80 100644 --- a/arch/arm/configs/qcom_defconfig +++ b/arch/arm/configs/qcom_defconfig @@ -159,7 +159,6 @@ CONFIG_FB=y CONFIG_FRAMEBUFFER_CONSOLE=y # CONFIG_LCD_CLASS_DEVICE is not set CONFIG_BACKLIGHT_CLASS_DEVICE=y -# CONFIG_BACKLIGHT_GENERIC is not set CONFIG_BACKLIGHT_LM3630A=y CONFIG_BACKLIGHT_LP855X=y CONFIG_SOUND=y diff --git a/arch/arm/configs/sama5_defconfig b/arch/arm/configs/sama5_defconfig index 2c8a621a8f1f..5f6297e6c549 100644 --- a/arch/arm/configs/sama5_defconfig +++ b/arch/arm/configs/sama5_defconfig @@ -170,7 +170,6 @@ CONFIG_DRM_ATMEL_HLCDC=y CONFIG_DRM_PANEL_SIMPLE=y CONFIG_LCD_CLASS_DEVICE=y CONFIG_BACKLIGHT_CLASS_DEVICE=y -# CONFIG_BACKLIGHT_GENERIC is not set CONFIG_BACKLIGHT_PWM=y CONFIG_FRAMEBUFFER_CONSOLE=y CONFIG_SOUND=y diff --git a/arch/arm/configs/sunxi_defconfig b/arch/arm/configs/sunxi_defconfig index 05f7f4ed8ded..a60c134c5e04 100644 --- a/arch/arm/configs/sunxi_defconfig +++ b/arch/arm/configs/sunxi_defconfig @@ -112,7 +112,6 @@ CONFIG_DRM_SIMPLE_BRIDGE=y CONFIG_DRM_LIMA=y CONFIG_FB_SIMPLE=y CONFIG_BACKLIGHT_CLASS_DEVICE=y -# CONFIG_BACKLIGHT_GENERIC is not set CONFIG_BACKLIGHT_PWM=y CONFIG_SOUND=y CONFIG_SND=y diff --git a/arch/arm/configs/tegra_defconfig b/arch/arm/configs/tegra_defconfig index fff5fae0db30..74739a52a8ad 100644 --- a/arch/arm/configs/tegra_defconfig +++ b/arch/arm/configs/tegra_defconfig @@ -205,7 +205,6 @@ CONFIG_DRM_PANEL_SIMPLE=y CONFIG_DRM_LVDS_CODEC=y # CONFIG_LCD_CLASS_DEVICE is not set CONFIG_BACKLIGHT_CLASS_DEVICE=y -# CONFIG_BACKLIGHT_GENERIC is not set CONFIG_BACKLIGHT_PWM=y CONFIG_FRAMEBUFFER_CONSOLE=y CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y -- cgit v1.2.3-59-g8ed1b From 4dbe44fb538c59a4adae5abfa9ded2f310250315 Mon Sep 17 00:00:00 2001 From: Ard Biesheuvel Date: Mon, 7 Dec 2020 18:40:53 +0100 Subject: efi: capsule: clean scatter-gather entries from the D-cache Scatter-gather lists passed to UpdateCapsule() should be cleaned from the D-cache to ensure that they are visible to the CPU after a warm reboot before the MMU is enabled. On ARM and arm64 systems, this implies a D-cache clean by virtual address to the point of coherency. However, due to the fact that the firmware itself is not able to map physical addresses back to virtual addresses when running under the OS, this must be done by the caller. Signed-off-by: Ard Biesheuvel --- arch/arm/include/asm/efi.h | 5 +++++ arch/arm64/include/asm/efi.h | 5 +++++ drivers/firmware/efi/capsule.c | 12 ++++++++++++ 3 files changed, 22 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/include/asm/efi.h b/arch/arm/include/asm/efi.h index 3ee4f4381985..e9a06e164e06 100644 --- a/arch/arm/include/asm/efi.h +++ b/arch/arm/include/asm/efi.h @@ -93,4 +93,9 @@ struct efi_arm_entry_state { u32 sctlr_after_ebs; }; +static inline void efi_capsule_flush_cache_range(void *addr, int size) +{ + __cpuc_flush_dcache_area(addr, size); +} + #endif /* _ASM_ARM_EFI_H */ diff --git a/arch/arm64/include/asm/efi.h b/arch/arm64/include/asm/efi.h index 973b14415271..00bd1e179d36 100644 --- a/arch/arm64/include/asm/efi.h +++ b/arch/arm64/include/asm/efi.h @@ -141,4 +141,9 @@ static inline void efi_set_pgd(struct mm_struct *mm) void efi_virtmap_load(void); void efi_virtmap_unload(void); +static inline void efi_capsule_flush_cache_range(void *addr, int size) +{ + __flush_dcache_area(addr, size); +} + #endif /* _ASM_EFI_H */ diff --git a/drivers/firmware/efi/capsule.c b/drivers/firmware/efi/capsule.c index 43f6fe7bfe80..768430293669 100644 --- a/drivers/firmware/efi/capsule.c +++ b/drivers/firmware/efi/capsule.c @@ -12,6 +12,7 @@ #include #include #include +#include #include typedef struct { @@ -265,6 +266,17 @@ int efi_capsule_update(efi_capsule_header_t *capsule, phys_addr_t *pages) else sglist[j].data = page_to_phys(sg_pages[i + 1]); +#if defined(CONFIG_ARM) || defined(CONFIG_ARM64) + /* + * At runtime, the firmware has no way to find out where the + * sglist elements are mapped, if they are mapped in the first + * place. Therefore, on architectures that can only perform + * cache maintenance by virtual address, the firmware is unable + * to perform this maintenance, and so it is up to the OS to do + * it instead. + */ + efi_capsule_flush_cache_range(sglist, PAGE_SIZE); +#endif kunmap_atomic(sglist); } -- cgit v1.2.3-59-g8ed1b From c0249238feefbbb99d517d06ace4338393901b67 Mon Sep 17 00:00:00 2001 From: Ard Biesheuvel Date: Thu, 12 Nov 2020 15:42:27 +0100 Subject: efi: arm: reduce minimum alignment of uncompressed kernel Now that we reduced the minimum relative alignment between PHYS_OFFSET and PAGE_OFFSET to 2 MiB, we can take this into account when allocating memory for the decompressed kernel when booting via EFI. This minimizes the amount of unusable memory we may end up with due to the base of DRAM being occupied by firmware. Signed-off-by: Ard Biesheuvel --- arch/arm/include/asm/efi.h | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/include/asm/efi.h b/arch/arm/include/asm/efi.h index e9a06e164e06..153680541aea 100644 --- a/arch/arm/include/asm/efi.h +++ b/arch/arm/include/asm/efi.h @@ -66,13 +66,12 @@ static inline void efifb_setup_from_dmi(struct screen_info *si, const char *opt) #define MAX_UNCOMP_KERNEL_SIZE SZ_32M /* - * phys-to-virt patching requires that the physical to virtual offset fits - * into the immediate field of an add/sub instruction, which comes down to the - * 24 least significant bits being zero, and so the offset should be a multiple - * of 16 MB. Since PAGE_OFFSET itself is a multiple of 16 MB, the physical - * base should be aligned to 16 MB as well. + * phys-to-virt patching requires that the physical to virtual offset is a + * multiple of 2 MiB. However, using an alignment smaller than TEXT_OFFSET + * here throws off the memory allocation logic, so let's use the lowest power + * of two greater than 2 MiB and greater than TEXT_OFFSET. */ -#define EFI_PHYS_ALIGN SZ_16M +#define EFI_PHYS_ALIGN max(SZ_2M, roundup_pow_of_two(TEXT_OFFSET)) /* on ARM, the FDT should be located in a lowmem region */ static inline unsigned long efi_get_max_fdt_addr(unsigned long image_addr) @@ -83,7 +82,7 @@ static inline unsigned long efi_get_max_fdt_addr(unsigned long image_addr) /* on ARM, the initrd should be loaded in a lowmem region */ static inline unsigned long efi_get_max_initrd_addr(unsigned long image_addr) { - return round_down(image_addr, EFI_PHYS_ALIGN) + SZ_512M; + return round_down(image_addr, SZ_4M) + SZ_512M; } struct efi_arm_entry_state { -- cgit v1.2.3-59-g8ed1b From 54649911f31b6e7c2a79a1426ca98259139e4c35 Mon Sep 17 00:00:00 2001 From: Ard Biesheuvel Date: Thu, 29 Oct 2020 14:49:01 +0100 Subject: efi: stub: get rid of efi_get_max_fdt_addr() Now that ARM started following the example of arm64 and RISC-V, and no longer imposes any restrictions on the placement of the FDT in memory at boot, we no longer need per-arch implementations of efi_get_max_fdt_addr() to factor out the differences. So get rid of it. Signed-off-by: Ard Biesheuvel Reviewed-by: Atish Patra Link: https://lore.kernel.org/r/20201029134901.9773-1-ardb@kernel.org --- arch/arm/include/asm/efi.h | 6 ------ arch/arm64/include/asm/efi.h | 6 ------ arch/riscv/include/asm/efi.h | 6 ------ drivers/firmware/efi/libstub/efi-stub.c | 1 - drivers/firmware/efi/libstub/efistub.h | 1 - drivers/firmware/efi/libstub/fdt.c | 3 +-- 6 files changed, 1 insertion(+), 22 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/include/asm/efi.h b/arch/arm/include/asm/efi.h index 153680541aea..abae071a02e1 100644 --- a/arch/arm/include/asm/efi.h +++ b/arch/arm/include/asm/efi.h @@ -73,12 +73,6 @@ static inline void efifb_setup_from_dmi(struct screen_info *si, const char *opt) */ #define EFI_PHYS_ALIGN max(SZ_2M, roundup_pow_of_two(TEXT_OFFSET)) -/* on ARM, the FDT should be located in a lowmem region */ -static inline unsigned long efi_get_max_fdt_addr(unsigned long image_addr) -{ - return round_down(image_addr, EFI_PHYS_ALIGN) + SZ_512M; -} - /* on ARM, the initrd should be loaded in a lowmem region */ static inline unsigned long efi_get_max_initrd_addr(unsigned long image_addr) { diff --git a/arch/arm64/include/asm/efi.h b/arch/arm64/include/asm/efi.h index 00bd1e179d36..3578aba9c608 100644 --- a/arch/arm64/include/asm/efi.h +++ b/arch/arm64/include/asm/efi.h @@ -64,12 +64,6 @@ efi_status_t __efi_rt_asm_wrapper(void *, const char *, ...); #define EFI_KIMG_ALIGN \ (SEGMENT_ALIGN > THREAD_ALIGN ? SEGMENT_ALIGN : THREAD_ALIGN) -/* on arm64, the FDT may be located anywhere in system RAM */ -static inline unsigned long efi_get_max_fdt_addr(unsigned long image_addr) -{ - return ULONG_MAX; -} - /* * On arm64, we have to ensure that the initrd ends up in the linear region, * which is a 1 GB aligned region of size '1UL << (VA_BITS_MIN - 1)' that is diff --git a/arch/riscv/include/asm/efi.h b/arch/riscv/include/asm/efi.h index 7542282f1141..6d98cd999680 100644 --- a/arch/riscv/include/asm/efi.h +++ b/arch/riscv/include/asm/efi.h @@ -27,12 +27,6 @@ int efi_set_mapping_permissions(struct mm_struct *mm, efi_memory_desc_t *md); #define ARCH_EFI_IRQ_FLAGS_MASK (SR_IE | SR_SPIE) -/* on RISC-V, the FDT may be located anywhere in system RAM */ -static inline unsigned long efi_get_max_fdt_addr(unsigned long image_addr) -{ - return ULONG_MAX; -} - /* Load initrd at enough distance from DRAM start */ static inline unsigned long efi_get_max_initrd_addr(unsigned long image_addr) { diff --git a/drivers/firmware/efi/libstub/efi-stub.c b/drivers/firmware/efi/libstub/efi-stub.c index 914a343c7785..ec2f3985bef3 100644 --- a/drivers/firmware/efi/libstub/efi-stub.c +++ b/drivers/firmware/efi/libstub/efi-stub.c @@ -273,7 +273,6 @@ efi_status_t __efiapi efi_pe_entry(efi_handle_t handle, install_memreserve_table(); status = allocate_new_fdt_and_exit_boot(handle, &fdt_addr, - efi_get_max_fdt_addr(image_addr), initrd_addr, initrd_size, cmdline_ptr, fdt_addr, fdt_size); if (status != EFI_SUCCESS) diff --git a/drivers/firmware/efi/libstub/efistub.h b/drivers/firmware/efi/libstub/efistub.h index b8ec29d6a74a..b50a6c67d9bd 100644 --- a/drivers/firmware/efi/libstub/efistub.h +++ b/drivers/firmware/efi/libstub/efistub.h @@ -750,7 +750,6 @@ efi_status_t efi_exit_boot_services(void *handle, efi_status_t allocate_new_fdt_and_exit_boot(void *handle, unsigned long *new_fdt_addr, - unsigned long max_addr, u64 initrd_addr, u64 initrd_size, char *cmdline_ptr, unsigned long fdt_addr, diff --git a/drivers/firmware/efi/libstub/fdt.c b/drivers/firmware/efi/libstub/fdt.c index 368cd60000ee..365c3a43a198 100644 --- a/drivers/firmware/efi/libstub/fdt.c +++ b/drivers/firmware/efi/libstub/fdt.c @@ -238,7 +238,6 @@ static efi_status_t exit_boot_func(struct efi_boot_memmap *map, efi_status_t allocate_new_fdt_and_exit_boot(void *handle, unsigned long *new_fdt_addr, - unsigned long max_addr, u64 initrd_addr, u64 initrd_size, char *cmdline_ptr, unsigned long fdt_addr, @@ -275,7 +274,7 @@ efi_status_t allocate_new_fdt_and_exit_boot(void *handle, efi_info("Exiting boot services and installing virtual address map...\n"); map.map = &memory_map; - status = efi_allocate_pages(MAX_FDT_SIZE, new_fdt_addr, max_addr); + status = efi_allocate_pages(MAX_FDT_SIZE, new_fdt_addr, ULONG_MAX); if (status != EFI_SUCCESS) { efi_err("Unable to allocate memory for new device tree.\n"); goto fail; -- cgit v1.2.3-59-g8ed1b From 23ab93a1480002fd289071e08f7b4960fdfa76d8 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 26 Nov 2020 14:25:00 +0100 Subject: ARM: zynq: Fix compatible string for adi,adxl345 chip The commit e359a29225dd ("dt-bindings: iio: accel: adxl345: switch to YAML bindings") switched binding to yaml and the following error pop up: ../zynq-zturn-v5.dt.yaml: accelerometer@53: compatible: 'oneOf' conditional failed, one must be fixed: ['adi,adxl345', 'adxl345', 'adi,adxl34x', 'adxl34x'] is too long Additional items are not allowed ('adi,adxl34x', 'adxl34x' were unexpected) Additional items are not allowed ('adxl345', 'adi,adxl34x', 'adxl34x' were unexpected) 'adi,adxl346' was expected 'adi,adxl345' was expected Use only one compatible string to be aligned with the binding. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/a9075ab54df13461380e46d3002302d3672325b5.1606397101.git.michal.simek@xilinx.com --- arch/arm/boot/dts/zynq-zturn-common.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/zynq-zturn-common.dtsi b/arch/arm/boot/dts/zynq-zturn-common.dtsi index 84f3c85c5bab..bf5d1c4568b0 100644 --- a/arch/arm/boot/dts/zynq-zturn-common.dtsi +++ b/arch/arm/boot/dts/zynq-zturn-common.dtsi @@ -104,7 +104,7 @@ }; accelerometer@53 { - compatible = "adi,adxl345", "adxl345", "adi,adxl34x", "adxl34x"; + compatible = "adi,adxl345"; reg = <0x53>; interrupt-parent = <&intc>; interrupts = <0x0 0x1e 0x4>; -- cgit v1.2.3-59-g8ed1b From 3880c39a80abf6bbbebafa58e69f830bdac1ab3a Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 26 Nov 2020 14:25:01 +0100 Subject: ARM: zynq: Rename bus to be align with simple-bus yaml Rename amba to AXI. Based on Xilinx Zynq TRM (Chapter 5) chip is "AXI point-to-point channels for communicating addresses, data, and response transactions between master and slave clients. This ARM AMBA 3.0..." Issues are reported as: .. amba: $nodename:0: 'amba' does not match '^([a-z][a-z0-9\\-]+-bus|bus|soc|axi|ahb|apb)(@[0-9a-f]+)?$' >From schema: ../github.com/devicetree-org/dt-schema/dtschema/schemas/simple-bus.yaml Similar change has been done for Xilinx ZynqMP SoC. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/8a4bc80debfbb79c296e76fc1e4c173e62657286.1606397101.git.michal.simek@xilinx.com --- arch/arm/boot/dts/zynq-7000.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi index db3899b07992..df9ad831cf05 100644 --- a/arch/arm/boot/dts/zynq-7000.dtsi +++ b/arch/arm/boot/dts/zynq-7000.dtsi @@ -92,7 +92,7 @@ }; }; - amba: amba { + amba: axi { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; -- cgit v1.2.3-59-g8ed1b From 38d1985fdfcf20dc246b552580479ae602f735d1 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 26 Nov 2020 14:25:02 +0100 Subject: ARM: zynq: Fix leds subnode name for zc702/zybo-z7 Fix the leds subnode names to match (^led-[0-9a-f]$|led). Similar change has been also done by commit 9a19a39ee48b ("arm64: dts: zynqmp: Fix leds subnode name for zcu100/ultra96 v1"). The patch is fixing these warnings: .../zynq-zc702.dt.yaml: leds: 'ds23' does not match any of the regexes: '(^led-[0-9a-f]$|led)', 'pinctrl-[0-9]+' >From schema: .../Documentation/devicetree/bindings/leds/leds-gpio.yaml .../zynq-zybo-z7.dt.yaml: gpio-leds: 'ld4' does not match any of the regexes: '(^led-[0-9a-f]$|led)', 'pinctrl-[0-9]+' >From schema: .../Documentation/devicetree/bindings/leds/leds-gpio.yaml Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/607a66783b129294364abf09a6fc8abd241ff4ee.1606397101.git.michal.simek@xilinx.com --- arch/arm/boot/dts/zynq-zc702.dts | 2 +- arch/arm/boot/dts/zynq-zybo-z7.dts | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/zynq-zc702.dts b/arch/arm/boot/dts/zynq-zc702.dts index 27cd6cb52f1b..10a7d0b8cf8b 100644 --- a/arch/arm/boot/dts/zynq-zc702.dts +++ b/arch/arm/boot/dts/zynq-zc702.dts @@ -49,7 +49,7 @@ leds { compatible = "gpio-leds"; - ds23 { + led-ds23 { label = "ds23"; gpios = <&gpio0 10 0>; linux,default-trigger = "heartbeat"; diff --git a/arch/arm/boot/dts/zynq-zybo-z7.dts b/arch/arm/boot/dts/zynq-zybo-z7.dts index 357b78a5c11b..7b87e10d3953 100644 --- a/arch/arm/boot/dts/zynq-zybo-z7.dts +++ b/arch/arm/boot/dts/zynq-zybo-z7.dts @@ -25,7 +25,7 @@ gpio-leds { compatible = "gpio-leds"; - ld4 { + led-ld4 { label = "zynq-zybo-z7:green:ld4"; gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>; }; -- cgit v1.2.3-59-g8ed1b From 225c13237732bba4b6714b43a3c4fe803da3166c Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 26 Nov 2020 14:25:03 +0100 Subject: ARM: zynq: Fix OCM mapping to be aligned with binding on zc702 The commit f69629919942 ("dt-bindings: sram: Convert SRAM bindings to json-schema") converted binding to yaml and some missing required properties started to be reported. Align binding based on it. The patch is fixing these warnings: .../zynq-zc702.dt.yaml: sram@fffc0000: '#address-cells' is a required property .../zynq-zc702.dt.yaml: sram@fffc0000: '#size-cells' is a required property .../zynq-zc702.dt.yaml: sram@fffc0000: 'ranges' is a required property >From schema: .../Documentation/devicetree/bindings/sram/sram.yaml Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/87c02786ccd8d7827827a9d95a8737bb300caeb0.1606397101.git.michal.simek@xilinx.com --- arch/arm/boot/dts/zynq-zc702.dts | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/zynq-zc702.dts b/arch/arm/boot/dts/zynq-zc702.dts index 10a7d0b8cf8b..cf70aff26c66 100644 --- a/arch/arm/boot/dts/zynq-zc702.dts +++ b/arch/arm/boot/dts/zynq-zc702.dts @@ -66,6 +66,12 @@ ocm: sram@fffc0000 { compatible = "mmio-sram"; reg = <0xfffc0000 0x10000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0xfffc0000 0x10000>; + ocm-sram@0 { + reg = <0x0 0x10000>; + }; }; }; -- cgit v1.2.3-59-g8ed1b From 536fada0cc72c6eb6082bbfbbd90127e8ab9b40c Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 26 Nov 2020 14:25:04 +0100 Subject: ARM: zynq: Convert at25 binding to new description on zc770-xm013 The commit f8f79fa6bb25 ("dt-bindings: at25: convert the binding document to yaml") converted binding to yaml and 3 deprecated properties pop up. The patch is fixing these warnings: .../zynq-zc770-xm013.dt.yaml: eeprom@2: 'pagesize' is a required property .../zynq-zc770-xm013.dt.yaml: eeprom@2: 'size' is a required property .../zynq-zc770-xm013.dt.yaml: eeprom@2: 'address-width' is a required property >From schema: .../Documentation/devicetree/bindings/eeprom/at25.yaml by converting them to new binding. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/be2c1125d98386033e182012eb08986924707a76.1606397101.git.michal.simek@xilinx.com --- arch/arm/boot/dts/zynq-zc770-xm013.dts | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/zynq-zc770-xm013.dts b/arch/arm/boot/dts/zynq-zc770-xm013.dts index 4ae2c85df3a0..38d96adc870c 100644 --- a/arch/arm/boot/dts/zynq-zc770-xm013.dts +++ b/arch/arm/boot/dts/zynq-zc770-xm013.dts @@ -63,13 +63,12 @@ num-cs = <4>; is-decoded-cs = <0>; eeprom: eeprom@2 { - at25,byte-len = <8192>; - at25,addr-mode = <2>; - at25,page-size = <32>; - compatible = "atmel,at25"; reg = <2>; spi-max-frequency = <1000000>; + size = <8192>; + address-width = <16>; + pagesize = <32>; }; }; -- cgit v1.2.3-59-g8ed1b From a508f620b5a6e9b359a2baa46ec9a714c3e2f420 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 26 Nov 2020 15:05:02 +0100 Subject: ARM: zynq: Fix incorrect reference to XM013 instead of XM011 Fix comment about targeted extension card. It was likely just c&p error. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/39e16e667aa8f132496092d4fa554935ddd5a55f.1606399500.git.michal.simek@xilinx.com --- arch/arm/boot/dts/zynq-zc770-xm011.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/zynq-zc770-xm011.dts b/arch/arm/boot/dts/zynq-zc770-xm011.dts index b7f65862c022..56732e8f6ca1 100644 --- a/arch/arm/boot/dts/zynq-zc770-xm011.dts +++ b/arch/arm/boot/dts/zynq-zc770-xm011.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Xilinx ZC770 XM013 board DTS + * Xilinx ZC770 XM011 board DTS * * Copyright (C) 2013-2018 Xilinx, Inc. */ -- cgit v1.2.3-59-g8ed1b From 74530d645126c2934b16db135edaef16eff9e35b Mon Sep 17 00:00:00 2001 From: Daniel Palmer Date: Sun, 29 Nov 2020 20:08:01 +0900 Subject: ARM: mstar: Add gpio controller to MStar base dtsi The GPIO controller is at the same address in all of the currently known chips so create a node for it in the base dtsi. Some extra properties are needed to actually use it so disable it by default. Signed-off-by: Daniel Palmer Acked-by: Linus Walleij Link: https://lore.kernel.org/r/20201129110803.2461700-5-daniel@0x0f.com' Signed-off-by: Arnd Bergmann --- arch/arm/boot/dts/mstar-v7.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/mstar-v7.dtsi b/arch/arm/boot/dts/mstar-v7.dtsi index f07880561e11..81369bc07f78 100644 --- a/arch/arm/boot/dts/mstar-v7.dtsi +++ b/arch/arm/boot/dts/mstar-v7.dtsi @@ -109,6 +109,16 @@ reg = <0x204400 0x200>; }; + gpio: gpio@207800 { + #gpio-cells = <2>; + reg = <0x207800 0x200>; + gpio-controller; + #interrupt-cells = <2>; + interrupt-controller; + interrupt-parent = <&intc_fiq>; + status = "disabled"; + }; + pm_uart: uart@221000 { compatible = "ns16550a"; reg = <0x221000 0x100>; -- cgit v1.2.3-59-g8ed1b From 5b8a05b9e8d10c8df29bb719e73ea8ed916a1eea Mon Sep 17 00:00:00 2001 From: Daniel Palmer Date: Sun, 29 Nov 2020 20:08:02 +0900 Subject: ARM: mstar: Fill in GPIO controller properties for infinity Fill in the properties needed to use the GPIO controller in the infinity and infinity3 chips. Signed-off-by: Daniel Palmer Acked-by: Linus Walleij Link: https://lore.kernel.org/r/20201129110803.2461700-6-daniel@0x0f.com' Signed-off-by: Arnd Bergmann --- arch/arm/boot/dts/mstar-infinity.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/mstar-infinity.dtsi b/arch/arm/boot/dts/mstar-infinity.dtsi index cd911adef014..0bee517797f4 100644 --- a/arch/arm/boot/dts/mstar-infinity.dtsi +++ b/arch/arm/boot/dts/mstar-infinity.dtsi @@ -6,6 +6,13 @@ #include "mstar-v7.dtsi" +#include + &imi { reg = <0xa0000000 0x16000>; }; + +&gpio { + compatible = "mstar,msc313-gpio"; + status = "okay"; +}; -- cgit v1.2.3-59-g8ed1b From ba2290b1b7505b28912092a0976e071a447ee18c Mon Sep 17 00:00:00 2001 From: Daniel Palmer Date: Tue, 1 Dec 2020 22:43:24 +0900 Subject: ARM: mstar: Add infinity2m support The infinity2m series of chips are like the other Mstar/Sigmastar chips in that they have a Cortex A7 system with DDR memory integrated in a single package. The infinity2m chips are intended for recording the incoming streams from IP cameras. So instead of video encoders they have video decoders, instead of a camera interface they have display hardware and so on. Aside from the above points the big difference about these chips is that they include a second Cortex A7 core. Signed-off-by: Daniel Palmer Link: https://lore.kernel.org/r/20201201134330.3037007-5-daniel@0x0f.com' Signed-off-by: Arnd Bergmann --- arch/arm/boot/dts/mstar-infinity2m.dtsi | 15 +++++++++++++++ arch/arm/boot/dts/mstar-v7.dtsi | 2 +- arch/arm/mach-mstar/mstarv7.c | 1 + 3 files changed, 17 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/mstar-infinity2m.dtsi (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/mstar-infinity2m.dtsi b/arch/arm/boot/dts/mstar-infinity2m.dtsi new file mode 100644 index 000000000000..02adb9fe9d3c --- /dev/null +++ b/arch/arm/boot/dts/mstar-infinity2m.dtsi @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2020 thingy.jp. + * Author: Daniel Palmer + */ + +#include "mstar-infinity.dtsi" + +&cpus { + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x1>; + }; +}; diff --git a/arch/arm/boot/dts/mstar-v7.dtsi b/arch/arm/boot/dts/mstar-v7.dtsi index 81369bc07f78..b0a21b0b731f 100644 --- a/arch/arm/boot/dts/mstar-v7.dtsi +++ b/arch/arm/boot/dts/mstar-v7.dtsi @@ -12,7 +12,7 @@ #size-cells = <1>; interrupt-parent = <&gic>; - cpus { + cpus: cpus { #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/mach-mstar/mstarv7.c b/arch/arm/mach-mstar/mstarv7.c index 81a4cbcab206..1aa748fa006e 100644 --- a/arch/arm/mach-mstar/mstarv7.c +++ b/arch/arm/mach-mstar/mstarv7.c @@ -35,6 +35,7 @@ static void __iomem *l3bridge; static const char * const mstarv7_board_dt_compat[] __initconst = { "mstar,infinity", + "mstar,infinity2m", "mstar,infinity3", "mstar,mercury5", NULL, -- cgit v1.2.3-59-g8ed1b From 572ef97bc7341b45c721d79f98262c4adb25919c Mon Sep 17 00:00:00 2001 From: Daniel Palmer Date: Tue, 1 Dec 2020 22:43:25 +0900 Subject: ARM: mstar: Add common dtsi for SSD201/SSD202D The SSD201 and SSD202D are basically the same chip with a different DDR die packaged (64MB DDR2 or 128MB DDR3). This patch adds a shared dtsi for the common parts of these chips like gpio, pinctrl etc. Signed-off-by: Daniel Palmer Link: https://lore.kernel.org/r/20201201134330.3037007-6-daniel@0x0f.com' Signed-off-by: Arnd Bergmann --- arch/arm/boot/dts/mstar-infinity2m-ssd20xd.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) create mode 100644 arch/arm/boot/dts/mstar-infinity2m-ssd20xd.dtsi (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/mstar-infinity2m-ssd20xd.dtsi b/arch/arm/boot/dts/mstar-infinity2m-ssd20xd.dtsi new file mode 100644 index 000000000000..0811220f0a79 --- /dev/null +++ b/arch/arm/boot/dts/mstar-infinity2m-ssd20xd.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2020 thingy.jp. + * Author: Daniel Palmer + */ + +#include "mstar-infinity2m.dtsi" -- cgit v1.2.3-59-g8ed1b From dbbaf35d589e554d5956780282feb5d62d7f2af6 Mon Sep 17 00:00:00 2001 From: Daniel Palmer Date: Tue, 1 Dec 2020 22:43:26 +0900 Subject: ARM: mstar: Add chip level dtsi for SSD202D Add a chip level dtsi for the SigmaStar SSD202D Signed-off-by: Daniel Palmer Link: https://lore.kernel.org/r/20201201134330.3037007-7-daniel@0x0f.com' Signed-off-by: Arnd Bergmann --- arch/arm/boot/dts/mstar-infinity2m-ssd202d.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) create mode 100644 arch/arm/boot/dts/mstar-infinity2m-ssd202d.dtsi (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/mstar-infinity2m-ssd202d.dtsi b/arch/arm/boot/dts/mstar-infinity2m-ssd202d.dtsi new file mode 100644 index 000000000000..176e10a29896 --- /dev/null +++ b/arch/arm/boot/dts/mstar-infinity2m-ssd202d.dtsi @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2020 thingy.jp. + * Author: Daniel Palmer + */ + +#include "mstar-infinity2m-ssd20xd.dtsi" + +/ { + memory { + device_type = "memory"; + reg = <0x20000000 0x8000000>; + }; +}; -- cgit v1.2.3-59-g8ed1b From 418cb58b45661724ba145bd769e53910ad9324b0 Mon Sep 17 00:00:00 2001 From: Daniel Palmer Date: Tue, 1 Dec 2020 22:43:27 +0900 Subject: ARM: mstar: Add dts for Honestar ssd201htv2 Add a dts for the Honestar ssd201htv2 devkit. This is for the board populated with a SSD202D. Signed-off-by: Daniel Palmer Link: https://lore.kernel.org/r/20201201134330.3037007-8-daniel@0x0f.com' Signed-off-by: Arnd Bergmann --- arch/arm/boot/dts/Makefile | 1 + .../dts/mstar-infinity2m-ssd202d-ssd201htv2.dts | 25 ++++++++++++++++++++++ 2 files changed, 26 insertions(+) create mode 100644 arch/arm/boot/dts/mstar-infinity2m-ssd202d-ssd201htv2.dts (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index ef2be2390c75..9a6ffef1b651 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1394,6 +1394,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \ dtb-$(CONFIG_ARCH_MILBEAUT) += milbeaut-m10v-evb.dtb dtb-$(CONFIG_ARCH_MSTARV7) += \ mstar-infinity-msc313-breadbee_crust.dtb \ + mstar-infinity2m-ssd202d-ssd201htv2.dtb \ mstar-infinity3-msc313e-breadbee.dtb \ mstar-mercury5-ssc8336n-midrived08.dtb dtb-$(CONFIG_ARCH_ZX) += zx296702-ad1.dtb diff --git a/arch/arm/boot/dts/mstar-infinity2m-ssd202d-ssd201htv2.dts b/arch/arm/boot/dts/mstar-infinity2m-ssd202d-ssd201htv2.dts new file mode 100644 index 000000000000..5d81641414a2 --- /dev/null +++ b/arch/arm/boot/dts/mstar-infinity2m-ssd202d-ssd201htv2.dts @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2020 thingy.jp. + * Author: Daniel Palmer + */ + +/dts-v1/; +#include "mstar-infinity2m-ssd202d.dtsi" + +/ { + model = "SSD201_HT_V2"; + compatible = "honestar,ssd201htv2", "mstar,infinity2m"; + + aliases { + serial0 = &pm_uart; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&pm_uart { + status = "okay"; +}; -- cgit v1.2.3-59-g8ed1b From 570e471ce0540165aed5bc638e462de7c1110a28 Mon Sep 17 00:00:00 2001 From: Daniel Palmer Date: Tue, 1 Dec 2020 22:43:28 +0900 Subject: ARM: mstar: Add smp ctrl registers to infinity2m dtsi Add the smpctrl registers to the infinity2m dtsi so that the second CPU can be enabled on chips in this family. Signed-off-by: Daniel Palmer Link: https://lore.kernel.org/r/20201201134330.3037007-9-daniel@0x0f.com' Signed-off-by: Arnd Bergmann --- arch/arm/boot/dts/mstar-infinity2m.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/mstar-infinity2m.dtsi b/arch/arm/boot/dts/mstar-infinity2m.dtsi index 02adb9fe9d3c..6d4d1d224e96 100644 --- a/arch/arm/boot/dts/mstar-infinity2m.dtsi +++ b/arch/arm/boot/dts/mstar-infinity2m.dtsi @@ -13,3 +13,10 @@ reg = <0x1>; }; }; + +&riu { + smpctrl: smpctrl@204000 { + reg = <0x204000 0x200>; + status = "disabled"; + }; +}; -- cgit v1.2.3-59-g8ed1b From ecaafac1eb73de8209680ec030769a2def4801e5 Mon Sep 17 00:00:00 2001 From: Daniel Palmer Date: Tue, 1 Dec 2020 22:43:29 +0900 Subject: ARM: mstar: Wire up smpctrl for SSD201/SSD202D Add the specific compat string for the smpctrl registers to the SSD201/SSD202D common dtsi. Signed-off-by: Daniel Palmer Link: https://lore.kernel.org/r/20201201134330.3037007-10-daniel@0x0f.com' Signed-off-by: Arnd Bergmann --- arch/arm/boot/dts/mstar-infinity2m-ssd20xd.dtsi | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/mstar-infinity2m-ssd20xd.dtsi b/arch/arm/boot/dts/mstar-infinity2m-ssd20xd.dtsi index 0811220f0a79..7a5e28b33f96 100644 --- a/arch/arm/boot/dts/mstar-infinity2m-ssd20xd.dtsi +++ b/arch/arm/boot/dts/mstar-infinity2m-ssd20xd.dtsi @@ -5,3 +5,8 @@ */ #include "mstar-infinity2m.dtsi" + +&smpctrl { + compatible = "sstar,ssd201-smpctrl", "mstar,smpctrl"; + status = "okay"; +}; -- cgit v1.2.3-59-g8ed1b From 5919eec0f09214901b09faeaf6341addebc57a89 Mon Sep 17 00:00:00 2001 From: Daniel Palmer Date: Tue, 1 Dec 2020 22:43:30 +0900 Subject: ARM: mstar: SMP support This patch adds SMP support for MStar/Sigmastar chips that have a second core like those in the infinity2m family. So far only single and dual core chips have been found so this does the bare minimum to boot the second core. From what I can tell not having the "holding pen" code to handle multiple cores is fine if there is only one core the will get booted. This might need to be reconsidered if chips with more cores turn up. Signed-off-by: Daniel Palmer Link: https://lore.kernel.org/r/20201201134330.3037007-11-daniel@0x0f.com' Signed-off-by: Arnd Bergmann --- arch/arm/mach-mstar/mstarv7.c | 48 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 48 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/mach-mstar/mstarv7.c b/arch/arm/mach-mstar/mstarv7.c index 1aa748fa006e..274c4f0df270 100644 --- a/arch/arm/mach-mstar/mstarv7.c +++ b/arch/arm/mach-mstar/mstarv7.c @@ -31,6 +31,13 @@ #define MSTARV7_L3BRIDGE_FLUSH_TRIGGER BIT(0) #define MSTARV7_L3BRIDGE_STATUS_DONE BIT(12) +#ifdef CONFIG_SMP +#define MSTARV7_CPU1_BOOT_ADDR_HIGH 0x4c +#define MSTARV7_CPU1_BOOT_ADDR_LOW 0x50 +#define MSTARV7_CPU1_UNLOCK 0x58 +#define MSTARV7_CPU1_UNLOCK_MAGIC 0xbabe +#endif + static void __iomem *l3bridge; static const char * const mstarv7_board_dt_compat[] __initconst = { @@ -63,6 +70,46 @@ static void mstarv7_mb(void) } } +#ifdef CONFIG_SMP +static int mstarv7_boot_secondary(unsigned int cpu, struct task_struct *idle) +{ + struct device_node *np; + u32 bootaddr = (u32) __pa_symbol(secondary_startup_arm); + void __iomem *smpctrl; + + /* + * right now we don't know how to boot anything except + * cpu 1. + */ + if (cpu != 1) + return -EINVAL; + + np = of_find_compatible_node(NULL, NULL, "mstar,smpctrl"); + smpctrl = of_iomap(np, 0); + + if (!smpctrl) + return -ENODEV; + + /* set the boot address for the second cpu */ + writew(bootaddr & 0xffff, smpctrl + MSTARV7_CPU1_BOOT_ADDR_LOW); + writew((bootaddr >> 16) & 0xffff, smpctrl + MSTARV7_CPU1_BOOT_ADDR_HIGH); + + /* unlock the second cpu */ + writew(MSTARV7_CPU1_UNLOCK_MAGIC, smpctrl + MSTARV7_CPU1_UNLOCK); + + /* and away we go...*/ + arch_send_wakeup_ipi_mask(cpumask_of(cpu)); + + iounmap(smpctrl); + + return 0; +} + +static const struct smp_operations __initdata mstarv7_smp_ops = { + .smp_boot_secondary = mstarv7_boot_secondary, +}; +#endif + static void __init mstarv7_init(void) { struct device_node *np; @@ -78,4 +125,5 @@ static void __init mstarv7_init(void) DT_MACHINE_START(MSTARV7_DT, "MStar/Sigmastar Armv7 (Device Tree)") .dt_compat = mstarv7_board_dt_compat, .init_machine = mstarv7_init, + .smp = smp_ops(mstarv7_smp_ops), MACHINE_END -- cgit v1.2.3-59-g8ed1b From e5acf9c862974041f7b2f581d1a40ccd29769add Mon Sep 17 00:00:00 2001 From: Miquel Raynal Date: Wed, 30 Sep 2020 01:01:15 +0200 Subject: mtd: nand: ecc-hamming: Move Hamming code to the generic NAND layer Hamming ECC code might be later re-used by the SPI NAND layer. Signed-off-by: Miquel Raynal Link: https://lore.kernel.org/linux-mtd/20200929230124.31491-12-miquel.raynal@bootlin.com --- arch/arm/mach-s3c/common-smdk-s3c24xx.c | 2 +- arch/arm/mach-s3c/mach-anubis.c | 2 +- arch/arm/mach-s3c/mach-at2440evb.c | 2 +- arch/arm/mach-s3c/mach-bast.c | 2 +- arch/arm/mach-s3c/mach-gta02.c | 2 +- arch/arm/mach-s3c/mach-jive.c | 2 +- arch/arm/mach-s3c/mach-mini2440.c | 2 +- arch/arm/mach-s3c/mach-osiris.c | 2 +- arch/arm/mach-s3c/mach-qt2410.c | 2 +- arch/arm/mach-s3c/mach-rx3715.c | 2 +- arch/arm/mach-s3c/mach-vstms.c | 2 +- drivers/mtd/Kconfig | 1 + drivers/mtd/nand/Kconfig | 11 + drivers/mtd/nand/Makefile | 1 + drivers/mtd/nand/ecc-sw-hamming.c | 484 ++++++++++++++++++++++++++++++++ drivers/mtd/nand/raw/Kconfig | 11 - drivers/mtd/nand/raw/Makefile | 1 - drivers/mtd/nand/raw/cs553x_nand.c | 2 +- drivers/mtd/nand/raw/fsl_elbc_nand.c | 2 +- drivers/mtd/nand/raw/fsl_ifc_nand.c | 2 +- drivers/mtd/nand/raw/fsl_upm.c | 2 +- drivers/mtd/nand/raw/fsmc_nand.c | 2 +- drivers/mtd/nand/raw/lpc32xx_mlc.c | 2 +- drivers/mtd/nand/raw/lpc32xx_slc.c | 2 +- drivers/mtd/nand/raw/mxic_nand.c | 2 +- drivers/mtd/nand/raw/nand_base.c | 2 +- drivers/mtd/nand/raw/nand_ecc.c | 484 -------------------------------- drivers/mtd/nand/raw/ndfc.c | 2 +- drivers/mtd/nand/raw/pasemi_nand.c | 2 +- drivers/mtd/nand/raw/s3c2410.c | 2 +- drivers/mtd/nand/raw/sharpsl.c | 2 +- drivers/mtd/nand/raw/tmio_nand.c | 2 +- drivers/mtd/nand/raw/txx9ndfmc.c | 2 +- drivers/mtd/sm_ftl.c | 2 +- drivers/mtd/tests/mtd_nandecctest.c | 2 +- include/linux/mtd/nand-ecc-sw-hamming.h | 39 +++ include/linux/mtd/nand_ecc.h | 39 --- include/linux/mtd/sharpsl.h | 2 +- 38 files changed, 565 insertions(+), 564 deletions(-) create mode 100644 drivers/mtd/nand/ecc-sw-hamming.c delete mode 100644 drivers/mtd/nand/raw/nand_ecc.c create mode 100644 include/linux/mtd/nand-ecc-sw-hamming.h delete mode 100644 include/linux/mtd/nand_ecc.h (limited to 'arch/arm') diff --git a/arch/arm/mach-s3c/common-smdk-s3c24xx.c b/arch/arm/mach-s3c/common-smdk-s3c24xx.c index f860d8bcba0e..6d124bbd384c 100644 --- a/arch/arm/mach-s3c/common-smdk-s3c24xx.c +++ b/arch/arm/mach-s3c/common-smdk-s3c24xx.c @@ -20,7 +20,7 @@ #include #include -#include +#include #include #include diff --git a/arch/arm/mach-s3c/mach-anubis.c b/arch/arm/mach-s3c/mach-anubis.c index 90e3fd98a3ac..04147cc0adcc 100644 --- a/arch/arm/mach-s3c/mach-anubis.c +++ b/arch/arm/mach-s3c/mach-anubis.c @@ -34,7 +34,7 @@ #include #include -#include +#include #include #include diff --git a/arch/arm/mach-s3c/mach-at2440evb.c b/arch/arm/mach-s3c/mach-at2440evb.c index 5fa49d4e2650..c6a5a51d84aa 100644 --- a/arch/arm/mach-s3c/mach-at2440evb.c +++ b/arch/arm/mach-s3c/mach-at2440evb.c @@ -35,7 +35,7 @@ #include #include -#include +#include #include #include "devs.h" diff --git a/arch/arm/mach-s3c/mach-bast.c b/arch/arm/mach-s3c/mach-bast.c index 328f5d9ae9f9..27e8d5950228 100644 --- a/arch/arm/mach-s3c/mach-bast.c +++ b/arch/arm/mach-s3c/mach-bast.c @@ -24,7 +24,7 @@ #include #include -#include +#include #include #include diff --git a/arch/arm/mach-s3c/mach-gta02.c b/arch/arm/mach-s3c/mach-gta02.c index 3c75c7d112ea..aec8b451c016 100644 --- a/arch/arm/mach-s3c/mach-gta02.c +++ b/arch/arm/mach-s3c/mach-gta02.c @@ -37,7 +37,7 @@ #include #include -#include +#include #include #include diff --git a/arch/arm/mach-s3c/mach-jive.c b/arch/arm/mach-s3c/mach-jive.c index 2a29c3eca559..0785638a9069 100644 --- a/arch/arm/mach-s3c/mach-jive.c +++ b/arch/arm/mach-s3c/mach-jive.c @@ -40,7 +40,7 @@ #include #include -#include +#include #include #include "gpio-cfg.h" diff --git a/arch/arm/mach-s3c/mach-mini2440.c b/arch/arm/mach-s3c/mach-mini2440.c index dc22ab839b95..4100905dfbd0 100644 --- a/arch/arm/mach-s3c/mach-mini2440.c +++ b/arch/arm/mach-s3c/mach-mini2440.c @@ -44,7 +44,7 @@ #include #include -#include +#include #include #include "gpio-cfg.h" diff --git a/arch/arm/mach-s3c/mach-osiris.c b/arch/arm/mach-s3c/mach-osiris.c index 81744ca67d1d..3aefb9d22340 100644 --- a/arch/arm/mach-s3c/mach-osiris.c +++ b/arch/arm/mach-s3c/mach-osiris.c @@ -33,7 +33,7 @@ #include #include -#include +#include #include #include "cpu.h" diff --git a/arch/arm/mach-s3c/mach-qt2410.c b/arch/arm/mach-s3c/mach-qt2410.c index 151e8e373d40..f88b961798fd 100644 --- a/arch/arm/mach-s3c/mach-qt2410.c +++ b/arch/arm/mach-s3c/mach-qt2410.c @@ -21,7 +21,7 @@ #include #include #include -#include +#include #include #include diff --git a/arch/arm/mach-s3c/mach-rx3715.c b/arch/arm/mach-s3c/mach-rx3715.c index a03662a47b38..9fd2d9dc3689 100644 --- a/arch/arm/mach-s3c/mach-rx3715.c +++ b/arch/arm/mach-s3c/mach-rx3715.c @@ -22,7 +22,7 @@ #include #include #include -#include +#include #include #include diff --git a/arch/arm/mach-s3c/mach-vstms.c b/arch/arm/mach-s3c/mach-vstms.c index 05f19f5ffabb..ec024af7b0ce 100644 --- a/arch/arm/mach-s3c/mach-vstms.c +++ b/arch/arm/mach-s3c/mach-vstms.c @@ -16,7 +16,7 @@ #include #include #include -#include +#include #include #include diff --git a/drivers/mtd/Kconfig b/drivers/mtd/Kconfig index 6ddab796216d..8bab6f8718a9 100644 --- a/drivers/mtd/Kconfig +++ b/drivers/mtd/Kconfig @@ -152,6 +152,7 @@ config SM_FTL tristate "SmartMedia/xD new translation layer" depends on BLOCK select MTD_BLKDEVS + select MTD_NAND_CORE select MTD_NAND_ECC_SW_HAMMING help This enables EXPERIMENTAL R/W support for SmartMedia/xD diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig index 55c17fb0dee1..306c33ca3448 100644 --- a/drivers/mtd/nand/Kconfig +++ b/drivers/mtd/nand/Kconfig @@ -15,6 +15,17 @@ config MTD_NAND_ECC bool depends on MTD_NAND_CORE +config MTD_NAND_ECC_SW_HAMMING + bool + +config MTD_NAND_ECC_SW_HAMMING_SMC + bool "NAND ECC Smart Media byte order" + depends on MTD_NAND_ECC_SW_HAMMING + default n + help + Software ECC according to the Smart Media Specification. + The original Linux implementation had byte 0 and 1 swapped. + config MTD_NAND_ECC_SW_BCH bool "Software BCH ECC engine" select BCH diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile index c7179ff23753..1c0b46960eb1 100644 --- a/drivers/mtd/nand/Makefile +++ b/drivers/mtd/nand/Makefile @@ -8,4 +8,5 @@ obj-y += raw/ obj-y += spi/ nandcore-$(CONFIG_MTD_NAND_ECC) += ecc.o +nandcore-$(CONFIG_MTD_NAND_ECC_SW_HAMMING) += ecc-sw-hamming.o nandcore-$(CONFIG_MTD_NAND_ECC_SW_BCH) += ecc-sw-bch.o diff --git a/drivers/mtd/nand/ecc-sw-hamming.c b/drivers/mtd/nand/ecc-sw-hamming.c new file mode 100644 index 000000000000..76966f5ff13f --- /dev/null +++ b/drivers/mtd/nand/ecc-sw-hamming.c @@ -0,0 +1,484 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * This file contains an ECC algorithm that detects and corrects 1 bit + * errors in a 256 byte block of data. + * + * Copyright © 2008 Koninklijke Philips Electronics NV. + * Author: Frans Meulenbroeks + * + * Completely replaces the previous ECC implementation which was written by: + * Steven J. Hill (sjhill@realitydiluted.com) + * Thomas Gleixner (tglx@linutronix.de) + * + * Information on how this algorithm works and how it was developed + * can be found in Documentation/driver-api/mtd/nand_ecc.rst + */ + +#include +#include +#include +#include +#include +#include +#include + +/* + * invparity is a 256 byte table that contains the odd parity + * for each byte. So if the number of bits in a byte is even, + * the array element is 1, and when the number of bits is odd + * the array eleemnt is 0. + */ +static const char invparity[256] = { + 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1, + 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0, + 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0, + 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1, + 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0, + 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1, + 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1, + 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0, + 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0, + 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1, + 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1, + 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0, + 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1, + 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0, + 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0, + 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1 +}; + +/* + * bitsperbyte contains the number of bits per byte + * this is only used for testing and repairing parity + * (a precalculated value slightly improves performance) + */ +static const char bitsperbyte[256] = { + 0, 1, 1, 2, 1, 2, 2, 3, 1, 2, 2, 3, 2, 3, 3, 4, + 1, 2, 2, 3, 2, 3, 3, 4, 2, 3, 3, 4, 3, 4, 4, 5, + 1, 2, 2, 3, 2, 3, 3, 4, 2, 3, 3, 4, 3, 4, 4, 5, + 2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6, + 1, 2, 2, 3, 2, 3, 3, 4, 2, 3, 3, 4, 3, 4, 4, 5, + 2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6, + 2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6, + 3, 4, 4, 5, 4, 5, 5, 6, 4, 5, 5, 6, 5, 6, 6, 7, + 1, 2, 2, 3, 2, 3, 3, 4, 2, 3, 3, 4, 3, 4, 4, 5, + 2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6, + 2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6, + 3, 4, 4, 5, 4, 5, 5, 6, 4, 5, 5, 6, 5, 6, 6, 7, + 2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6, + 3, 4, 4, 5, 4, 5, 5, 6, 4, 5, 5, 6, 5, 6, 6, 7, + 3, 4, 4, 5, 4, 5, 5, 6, 4, 5, 5, 6, 5, 6, 6, 7, + 4, 5, 5, 6, 5, 6, 6, 7, 5, 6, 6, 7, 6, 7, 7, 8, +}; + +/* + * addressbits is a lookup table to filter out the bits from the xor-ed + * ECC data that identify the faulty location. + * this is only used for repairing parity + * see the comments in nand_correct_data for more details + */ +static const char addressbits[256] = { + 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x01, 0x01, + 0x02, 0x02, 0x03, 0x03, 0x02, 0x02, 0x03, 0x03, + 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x01, 0x01, + 0x02, 0x02, 0x03, 0x03, 0x02, 0x02, 0x03, 0x03, + 0x04, 0x04, 0x05, 0x05, 0x04, 0x04, 0x05, 0x05, + 0x06, 0x06, 0x07, 0x07, 0x06, 0x06, 0x07, 0x07, + 0x04, 0x04, 0x05, 0x05, 0x04, 0x04, 0x05, 0x05, + 0x06, 0x06, 0x07, 0x07, 0x06, 0x06, 0x07, 0x07, + 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x01, 0x01, + 0x02, 0x02, 0x03, 0x03, 0x02, 0x02, 0x03, 0x03, + 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x01, 0x01, + 0x02, 0x02, 0x03, 0x03, 0x02, 0x02, 0x03, 0x03, + 0x04, 0x04, 0x05, 0x05, 0x04, 0x04, 0x05, 0x05, + 0x06, 0x06, 0x07, 0x07, 0x06, 0x06, 0x07, 0x07, + 0x04, 0x04, 0x05, 0x05, 0x04, 0x04, 0x05, 0x05, + 0x06, 0x06, 0x07, 0x07, 0x06, 0x06, 0x07, 0x07, + 0x08, 0x08, 0x09, 0x09, 0x08, 0x08, 0x09, 0x09, + 0x0a, 0x0a, 0x0b, 0x0b, 0x0a, 0x0a, 0x0b, 0x0b, + 0x08, 0x08, 0x09, 0x09, 0x08, 0x08, 0x09, 0x09, + 0x0a, 0x0a, 0x0b, 0x0b, 0x0a, 0x0a, 0x0b, 0x0b, + 0x0c, 0x0c, 0x0d, 0x0d, 0x0c, 0x0c, 0x0d, 0x0d, + 0x0e, 0x0e, 0x0f, 0x0f, 0x0e, 0x0e, 0x0f, 0x0f, + 0x0c, 0x0c, 0x0d, 0x0d, 0x0c, 0x0c, 0x0d, 0x0d, + 0x0e, 0x0e, 0x0f, 0x0f, 0x0e, 0x0e, 0x0f, 0x0f, + 0x08, 0x08, 0x09, 0x09, 0x08, 0x08, 0x09, 0x09, + 0x0a, 0x0a, 0x0b, 0x0b, 0x0a, 0x0a, 0x0b, 0x0b, + 0x08, 0x08, 0x09, 0x09, 0x08, 0x08, 0x09, 0x09, + 0x0a, 0x0a, 0x0b, 0x0b, 0x0a, 0x0a, 0x0b, 0x0b, + 0x0c, 0x0c, 0x0d, 0x0d, 0x0c, 0x0c, 0x0d, 0x0d, + 0x0e, 0x0e, 0x0f, 0x0f, 0x0e, 0x0e, 0x0f, 0x0f, + 0x0c, 0x0c, 0x0d, 0x0d, 0x0c, 0x0c, 0x0d, 0x0d, + 0x0e, 0x0e, 0x0f, 0x0f, 0x0e, 0x0e, 0x0f, 0x0f +}; + +/** + * __nand_calculate_ecc - [NAND Interface] Calculate 3-byte ECC for 256/512-byte + * block + * @buf: input buffer with raw data + * @eccsize: data bytes per ECC step (256 or 512) + * @code: output buffer with ECC + * @sm_order: Smart Media byte ordering + */ +void __nand_calculate_ecc(const unsigned char *buf, unsigned int eccsize, + unsigned char *code, bool sm_order) +{ + int i; + const uint32_t *bp = (uint32_t *)buf; + /* 256 or 512 bytes/ecc */ + const uint32_t eccsize_mult = eccsize >> 8; + uint32_t cur; /* current value in buffer */ + /* rp0..rp15..rp17 are the various accumulated parities (per byte) */ + uint32_t rp0, rp1, rp2, rp3, rp4, rp5, rp6, rp7; + uint32_t rp8, rp9, rp10, rp11, rp12, rp13, rp14, rp15, rp16; + uint32_t rp17; + uint32_t par; /* the cumulative parity for all data */ + uint32_t tmppar; /* the cumulative parity for this iteration; + for rp12, rp14 and rp16 at the end of the + loop */ + + par = 0; + rp4 = 0; + rp6 = 0; + rp8 = 0; + rp10 = 0; + rp12 = 0; + rp14 = 0; + rp16 = 0; + + /* + * The loop is unrolled a number of times; + * This avoids if statements to decide on which rp value to update + * Also we process the data by longwords. + * Note: passing unaligned data might give a performance penalty. + * It is assumed that the buffers are aligned. + * tmppar is the cumulative sum of this iteration. + * needed for calculating rp12, rp14, rp16 and par + * also used as a performance improvement for rp6, rp8 and rp10 + */ + for (i = 0; i < eccsize_mult << 2; i++) { + cur = *bp++; + tmppar = cur; + rp4 ^= cur; + cur = *bp++; + tmppar ^= cur; + rp6 ^= tmppar; + cur = *bp++; + tmppar ^= cur; + rp4 ^= cur; + cur = *bp++; + tmppar ^= cur; + rp8 ^= tmppar; + + cur = *bp++; + tmppar ^= cur; + rp4 ^= cur; + rp6 ^= cur; + cur = *bp++; + tmppar ^= cur; + rp6 ^= cur; + cur = *bp++; + tmppar ^= cur; + rp4 ^= cur; + cur = *bp++; + tmppar ^= cur; + rp10 ^= tmppar; + + cur = *bp++; + tmppar ^= cur; + rp4 ^= cur; + rp6 ^= cur; + rp8 ^= cur; + cur = *bp++; + tmppar ^= cur; + rp6 ^= cur; + rp8 ^= cur; + cur = *bp++; + tmppar ^= cur; + rp4 ^= cur; + rp8 ^= cur; + cur = *bp++; + tmppar ^= cur; + rp8 ^= cur; + + cur = *bp++; + tmppar ^= cur; + rp4 ^= cur; + rp6 ^= cur; + cur = *bp++; + tmppar ^= cur; + rp6 ^= cur; + cur = *bp++; + tmppar ^= cur; + rp4 ^= cur; + cur = *bp++; + tmppar ^= cur; + + par ^= tmppar; + if ((i & 0x1) == 0) + rp12 ^= tmppar; + if ((i & 0x2) == 0) + rp14 ^= tmppar; + if (eccsize_mult == 2 && (i & 0x4) == 0) + rp16 ^= tmppar; + } + + /* + * handle the fact that we use longword operations + * we'll bring rp4..rp14..rp16 back to single byte entities by + * shifting and xoring first fold the upper and lower 16 bits, + * then the upper and lower 8 bits. + */ + rp4 ^= (rp4 >> 16); + rp4 ^= (rp4 >> 8); + rp4 &= 0xff; + rp6 ^= (rp6 >> 16); + rp6 ^= (rp6 >> 8); + rp6 &= 0xff; + rp8 ^= (rp8 >> 16); + rp8 ^= (rp8 >> 8); + rp8 &= 0xff; + rp10 ^= (rp10 >> 16); + rp10 ^= (rp10 >> 8); + rp10 &= 0xff; + rp12 ^= (rp12 >> 16); + rp12 ^= (rp12 >> 8); + rp12 &= 0xff; + rp14 ^= (rp14 >> 16); + rp14 ^= (rp14 >> 8); + rp14 &= 0xff; + if (eccsize_mult == 2) { + rp16 ^= (rp16 >> 16); + rp16 ^= (rp16 >> 8); + rp16 &= 0xff; + } + + /* + * we also need to calculate the row parity for rp0..rp3 + * This is present in par, because par is now + * rp3 rp3 rp2 rp2 in little endian and + * rp2 rp2 rp3 rp3 in big endian + * as well as + * rp1 rp0 rp1 rp0 in little endian and + * rp0 rp1 rp0 rp1 in big endian + * First calculate rp2 and rp3 + */ +#ifdef __BIG_ENDIAN + rp2 = (par >> 16); + rp2 ^= (rp2 >> 8); + rp2 &= 0xff; + rp3 = par & 0xffff; + rp3 ^= (rp3 >> 8); + rp3 &= 0xff; +#else + rp3 = (par >> 16); + rp3 ^= (rp3 >> 8); + rp3 &= 0xff; + rp2 = par & 0xffff; + rp2 ^= (rp2 >> 8); + rp2 &= 0xff; +#endif + + /* reduce par to 16 bits then calculate rp1 and rp0 */ + par ^= (par >> 16); +#ifdef __BIG_ENDIAN + rp0 = (par >> 8) & 0xff; + rp1 = (par & 0xff); +#else + rp1 = (par >> 8) & 0xff; + rp0 = (par & 0xff); +#endif + + /* finally reduce par to 8 bits */ + par ^= (par >> 8); + par &= 0xff; + + /* + * and calculate rp5..rp15..rp17 + * note that par = rp4 ^ rp5 and due to the commutative property + * of the ^ operator we can say: + * rp5 = (par ^ rp4); + * The & 0xff seems superfluous, but benchmarking learned that + * leaving it out gives slightly worse results. No idea why, probably + * it has to do with the way the pipeline in pentium is organized. + */ + rp5 = (par ^ rp4) & 0xff; + rp7 = (par ^ rp6) & 0xff; + rp9 = (par ^ rp8) & 0xff; + rp11 = (par ^ rp10) & 0xff; + rp13 = (par ^ rp12) & 0xff; + rp15 = (par ^ rp14) & 0xff; + if (eccsize_mult == 2) + rp17 = (par ^ rp16) & 0xff; + + /* + * Finally calculate the ECC bits. + * Again here it might seem that there are performance optimisations + * possible, but benchmarks showed that on the system this is developed + * the code below is the fastest + */ + if (sm_order) { + code[0] = (invparity[rp7] << 7) | (invparity[rp6] << 6) | + (invparity[rp5] << 5) | (invparity[rp4] << 4) | + (invparity[rp3] << 3) | (invparity[rp2] << 2) | + (invparity[rp1] << 1) | (invparity[rp0]); + code[1] = (invparity[rp15] << 7) | (invparity[rp14] << 6) | + (invparity[rp13] << 5) | (invparity[rp12] << 4) | + (invparity[rp11] << 3) | (invparity[rp10] << 2) | + (invparity[rp9] << 1) | (invparity[rp8]); + } else { + code[1] = (invparity[rp7] << 7) | (invparity[rp6] << 6) | + (invparity[rp5] << 5) | (invparity[rp4] << 4) | + (invparity[rp3] << 3) | (invparity[rp2] << 2) | + (invparity[rp1] << 1) | (invparity[rp0]); + code[0] = (invparity[rp15] << 7) | (invparity[rp14] << 6) | + (invparity[rp13] << 5) | (invparity[rp12] << 4) | + (invparity[rp11] << 3) | (invparity[rp10] << 2) | + (invparity[rp9] << 1) | (invparity[rp8]); + } + + if (eccsize_mult == 1) + code[2] = + (invparity[par & 0xf0] << 7) | + (invparity[par & 0x0f] << 6) | + (invparity[par & 0xcc] << 5) | + (invparity[par & 0x33] << 4) | + (invparity[par & 0xaa] << 3) | + (invparity[par & 0x55] << 2) | + 3; + else + code[2] = + (invparity[par & 0xf0] << 7) | + (invparity[par & 0x0f] << 6) | + (invparity[par & 0xcc] << 5) | + (invparity[par & 0x33] << 4) | + (invparity[par & 0xaa] << 3) | + (invparity[par & 0x55] << 2) | + (invparity[rp17] << 1) | + (invparity[rp16] << 0); +} +EXPORT_SYMBOL(__nand_calculate_ecc); + +/** + * nand_calculate_ecc - [NAND Interface] Calculate 3-byte ECC for 256/512-byte + * block + * @chip: NAND chip object + * @buf: input buffer with raw data + * @code: output buffer with ECC + */ +int nand_calculate_ecc(struct nand_chip *chip, const unsigned char *buf, + unsigned char *code) +{ + bool sm_order = chip->ecc.options & NAND_ECC_SOFT_HAMMING_SM_ORDER; + + __nand_calculate_ecc(buf, chip->ecc.size, code, sm_order); + + return 0; +} +EXPORT_SYMBOL(nand_calculate_ecc); + +/** + * __nand_correct_data - [NAND Interface] Detect and correct bit error(s) + * @buf: raw data read from the chip + * @read_ecc: ECC from the chip + * @calc_ecc: the ECC calculated from raw data + * @eccsize: data bytes per ECC step (256 or 512) + * @sm_order: Smart Media byte order + * + * Detect and correct a 1 bit error for eccsize byte block + */ +int __nand_correct_data(unsigned char *buf, + unsigned char *read_ecc, unsigned char *calc_ecc, + unsigned int eccsize, bool sm_order) +{ + unsigned char b0, b1, b2, bit_addr; + unsigned int byte_addr; + /* 256 or 512 bytes/ecc */ + const uint32_t eccsize_mult = eccsize >> 8; + + /* + * b0 to b2 indicate which bit is faulty (if any) + * we might need the xor result more than once, + * so keep them in a local var + */ + if (sm_order) { + b0 = read_ecc[0] ^ calc_ecc[0]; + b1 = read_ecc[1] ^ calc_ecc[1]; + } else { + b0 = read_ecc[1] ^ calc_ecc[1]; + b1 = read_ecc[0] ^ calc_ecc[0]; + } + + b2 = read_ecc[2] ^ calc_ecc[2]; + + /* check if there are any bitfaults */ + + /* repeated if statements are slightly more efficient than switch ... */ + /* ordered in order of likelihood */ + + if ((b0 | b1 | b2) == 0) + return 0; /* no error */ + + if ((((b0 ^ (b0 >> 1)) & 0x55) == 0x55) && + (((b1 ^ (b1 >> 1)) & 0x55) == 0x55) && + ((eccsize_mult == 1 && ((b2 ^ (b2 >> 1)) & 0x54) == 0x54) || + (eccsize_mult == 2 && ((b2 ^ (b2 >> 1)) & 0x55) == 0x55))) { + /* single bit error */ + /* + * rp17/rp15/13/11/9/7/5/3/1 indicate which byte is the faulty + * byte, cp 5/3/1 indicate the faulty bit. + * A lookup table (called addressbits) is used to filter + * the bits from the byte they are in. + * A marginal optimisation is possible by having three + * different lookup tables. + * One as we have now (for b0), one for b2 + * (that would avoid the >> 1), and one for b1 (with all values + * << 4). However it was felt that introducing two more tables + * hardly justify the gain. + * + * The b2 shift is there to get rid of the lowest two bits. + * We could also do addressbits[b2] >> 1 but for the + * performance it does not make any difference + */ + if (eccsize_mult == 1) + byte_addr = (addressbits[b1] << 4) + addressbits[b0]; + else + byte_addr = (addressbits[b2 & 0x3] << 8) + + (addressbits[b1] << 4) + addressbits[b0]; + bit_addr = addressbits[b2 >> 2]; + /* flip the bit */ + buf[byte_addr] ^= (1 << bit_addr); + return 1; + + } + /* count nr of bits; use table lookup, faster than calculating it */ + if ((bitsperbyte[b0] + bitsperbyte[b1] + bitsperbyte[b2]) == 1) + return 1; /* error in ECC data; no action needed */ + + pr_err("%s: uncorrectable ECC error\n", __func__); + return -EBADMSG; +} +EXPORT_SYMBOL(__nand_correct_data); + +/** + * nand_correct_data - [NAND Interface] Detect and correct bit error(s) + * @chip: NAND chip object + * @buf: raw data read from the chip + * @read_ecc: ECC from the chip + * @calc_ecc: the ECC calculated from raw data + * + * Detect and correct a 1 bit error for 256/512 byte block + */ +int nand_correct_data(struct nand_chip *chip, unsigned char *buf, + unsigned char *read_ecc, unsigned char *calc_ecc) +{ + bool sm_order = chip->ecc.options & NAND_ECC_SOFT_HAMMING_SM_ORDER; + + return __nand_correct_data(buf, read_ecc, calc_ecc, chip->ecc.size, + sm_order); +} +EXPORT_SYMBOL(nand_correct_data); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Frans Meulenbroeks "); +MODULE_DESCRIPTION("Generic NAND ECC support"); diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig index b73860aa77c6..6149096e32cb 100644 --- a/drivers/mtd/nand/raw/Kconfig +++ b/drivers/mtd/nand/raw/Kconfig @@ -1,15 +1,4 @@ # SPDX-License-Identifier: GPL-2.0-only -config MTD_NAND_ECC_SW_HAMMING - tristate - -config MTD_NAND_ECC_SW_HAMMING_SMC - bool "NAND ECC Smart Media byte order" - depends on MTD_NAND_ECC_SW_HAMMING - default n - help - Software ECC according to the Smart Media Specification. - The original Linux implementation had byte 0 and 1 swapped. - menuconfig MTD_RAW_NAND tristate "Raw/Parallel NAND Device Support" select MTD_NAND_CORE diff --git a/drivers/mtd/nand/raw/Makefile b/drivers/mtd/nand/raw/Makefile index 76904305d091..dc38c087c693 100644 --- a/drivers/mtd/nand/raw/Makefile +++ b/drivers/mtd/nand/raw/Makefile @@ -1,7 +1,6 @@ # SPDX-License-Identifier: GPL-2.0 obj-$(CONFIG_MTD_RAW_NAND) += nand.o -obj-$(CONFIG_MTD_NAND_ECC_SW_HAMMING) += nand_ecc.o obj-$(CONFIG_MTD_SM_COMMON) += sm_common.o obj-$(CONFIG_MTD_NAND_CAFE) += cafe_nand.o diff --git a/drivers/mtd/nand/raw/cs553x_nand.c b/drivers/mtd/nand/raw/cs553x_nand.c index 282203debd0c..9a2bdb45a771 100644 --- a/drivers/mtd/nand/raw/cs553x_nand.c +++ b/drivers/mtd/nand/raw/cs553x_nand.c @@ -19,7 +19,7 @@ #include #include #include -#include +#include #include #include diff --git a/drivers/mtd/nand/raw/fsl_elbc_nand.c b/drivers/mtd/nand/raw/fsl_elbc_nand.c index b2af7f81fdf8..eb255cf83e32 100644 --- a/drivers/mtd/nand/raw/fsl_elbc_nand.c +++ b/drivers/mtd/nand/raw/fsl_elbc_nand.c @@ -22,7 +22,7 @@ #include #include -#include +#include #include #include diff --git a/drivers/mtd/nand/raw/fsl_ifc_nand.c b/drivers/mtd/nand/raw/fsl_ifc_nand.c index e345f9d9f8e8..d2f84917fa8b 100644 --- a/drivers/mtd/nand/raw/fsl_ifc_nand.c +++ b/drivers/mtd/nand/raw/fsl_ifc_nand.c @@ -15,7 +15,7 @@ #include #include #include -#include +#include #include #include diff --git a/drivers/mtd/nand/raw/fsl_upm.c b/drivers/mtd/nand/raw/fsl_upm.c index d5813b9abc8e..3824361928a1 100644 --- a/drivers/mtd/nand/raw/fsl_upm.c +++ b/drivers/mtd/nand/raw/fsl_upm.c @@ -11,7 +11,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/drivers/mtd/nand/raw/fsmc_nand.c b/drivers/mtd/nand/raw/fsmc_nand.c index 984b05e6bd38..e880db5852d8 100644 --- a/drivers/mtd/nand/raw/fsmc_nand.c +++ b/drivers/mtd/nand/raw/fsmc_nand.c @@ -26,7 +26,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/drivers/mtd/nand/raw/lpc32xx_mlc.c b/drivers/mtd/nand/raw/lpc32xx_mlc.c index 9e728c731795..885b03b7af52 100644 --- a/drivers/mtd/nand/raw/lpc32xx_mlc.c +++ b/drivers/mtd/nand/raw/lpc32xx_mlc.c @@ -31,7 +31,7 @@ #include #include #include -#include +#include #define DRV_NAME "lpc32xx_mlc" diff --git a/drivers/mtd/nand/raw/lpc32xx_slc.c b/drivers/mtd/nand/raw/lpc32xx_slc.c index dc7785e30d2f..0bf9c3fbcd82 100644 --- a/drivers/mtd/nand/raw/lpc32xx_slc.c +++ b/drivers/mtd/nand/raw/lpc32xx_slc.c @@ -23,7 +23,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/drivers/mtd/nand/raw/mxic_nand.c b/drivers/mtd/nand/raw/mxic_nand.c index d66b5b0971fa..da1070993994 100644 --- a/drivers/mtd/nand/raw/mxic_nand.c +++ b/drivers/mtd/nand/raw/mxic_nand.c @@ -12,8 +12,8 @@ #include #include #include +#include #include -#include #include #include "internals.h" diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c index ebaf3bbfc1b2..bee7c64a0a4e 100644 --- a/drivers/mtd/nand/raw/nand_base.c +++ b/drivers/mtd/nand/raw/nand_base.c @@ -35,7 +35,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/drivers/mtd/nand/raw/nand_ecc.c b/drivers/mtd/nand/raw/nand_ecc.c deleted file mode 100644 index b6a46b1b7781..000000000000 --- a/drivers/mtd/nand/raw/nand_ecc.c +++ /dev/null @@ -1,484 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * This file contains an ECC algorithm that detects and corrects 1 bit - * errors in a 256 byte block of data. - * - * Copyright © 2008 Koninklijke Philips Electronics NV. - * Author: Frans Meulenbroeks - * - * Completely replaces the previous ECC implementation which was written by: - * Steven J. Hill (sjhill@realitydiluted.com) - * Thomas Gleixner (tglx@linutronix.de) - * - * Information on how this algorithm works and how it was developed - * can be found in Documentation/driver-api/mtd/nand_ecc.rst - */ - -#include -#include -#include -#include -#include -#include -#include - -/* - * invparity is a 256 byte table that contains the odd parity - * for each byte. So if the number of bits in a byte is even, - * the array element is 1, and when the number of bits is odd - * the array eleemnt is 0. - */ -static const char invparity[256] = { - 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1, - 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0, - 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0, - 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1, - 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0, - 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1, - 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1, - 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0, - 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0, - 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1, - 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1, - 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0, - 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1, - 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0, - 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0, - 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1 -}; - -/* - * bitsperbyte contains the number of bits per byte - * this is only used for testing and repairing parity - * (a precalculated value slightly improves performance) - */ -static const char bitsperbyte[256] = { - 0, 1, 1, 2, 1, 2, 2, 3, 1, 2, 2, 3, 2, 3, 3, 4, - 1, 2, 2, 3, 2, 3, 3, 4, 2, 3, 3, 4, 3, 4, 4, 5, - 1, 2, 2, 3, 2, 3, 3, 4, 2, 3, 3, 4, 3, 4, 4, 5, - 2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6, - 1, 2, 2, 3, 2, 3, 3, 4, 2, 3, 3, 4, 3, 4, 4, 5, - 2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6, - 2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6, - 3, 4, 4, 5, 4, 5, 5, 6, 4, 5, 5, 6, 5, 6, 6, 7, - 1, 2, 2, 3, 2, 3, 3, 4, 2, 3, 3, 4, 3, 4, 4, 5, - 2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6, - 2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6, - 3, 4, 4, 5, 4, 5, 5, 6, 4, 5, 5, 6, 5, 6, 6, 7, - 2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6, - 3, 4, 4, 5, 4, 5, 5, 6, 4, 5, 5, 6, 5, 6, 6, 7, - 3, 4, 4, 5, 4, 5, 5, 6, 4, 5, 5, 6, 5, 6, 6, 7, - 4, 5, 5, 6, 5, 6, 6, 7, 5, 6, 6, 7, 6, 7, 7, 8, -}; - -/* - * addressbits is a lookup table to filter out the bits from the xor-ed - * ECC data that identify the faulty location. - * this is only used for repairing parity - * see the comments in nand_correct_data for more details - */ -static const char addressbits[256] = { - 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x01, 0x01, - 0x02, 0x02, 0x03, 0x03, 0x02, 0x02, 0x03, 0x03, - 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x01, 0x01, - 0x02, 0x02, 0x03, 0x03, 0x02, 0x02, 0x03, 0x03, - 0x04, 0x04, 0x05, 0x05, 0x04, 0x04, 0x05, 0x05, - 0x06, 0x06, 0x07, 0x07, 0x06, 0x06, 0x07, 0x07, - 0x04, 0x04, 0x05, 0x05, 0x04, 0x04, 0x05, 0x05, - 0x06, 0x06, 0x07, 0x07, 0x06, 0x06, 0x07, 0x07, - 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x01, 0x01, - 0x02, 0x02, 0x03, 0x03, 0x02, 0x02, 0x03, 0x03, - 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x01, 0x01, - 0x02, 0x02, 0x03, 0x03, 0x02, 0x02, 0x03, 0x03, - 0x04, 0x04, 0x05, 0x05, 0x04, 0x04, 0x05, 0x05, - 0x06, 0x06, 0x07, 0x07, 0x06, 0x06, 0x07, 0x07, - 0x04, 0x04, 0x05, 0x05, 0x04, 0x04, 0x05, 0x05, - 0x06, 0x06, 0x07, 0x07, 0x06, 0x06, 0x07, 0x07, - 0x08, 0x08, 0x09, 0x09, 0x08, 0x08, 0x09, 0x09, - 0x0a, 0x0a, 0x0b, 0x0b, 0x0a, 0x0a, 0x0b, 0x0b, - 0x08, 0x08, 0x09, 0x09, 0x08, 0x08, 0x09, 0x09, - 0x0a, 0x0a, 0x0b, 0x0b, 0x0a, 0x0a, 0x0b, 0x0b, - 0x0c, 0x0c, 0x0d, 0x0d, 0x0c, 0x0c, 0x0d, 0x0d, - 0x0e, 0x0e, 0x0f, 0x0f, 0x0e, 0x0e, 0x0f, 0x0f, - 0x0c, 0x0c, 0x0d, 0x0d, 0x0c, 0x0c, 0x0d, 0x0d, - 0x0e, 0x0e, 0x0f, 0x0f, 0x0e, 0x0e, 0x0f, 0x0f, - 0x08, 0x08, 0x09, 0x09, 0x08, 0x08, 0x09, 0x09, - 0x0a, 0x0a, 0x0b, 0x0b, 0x0a, 0x0a, 0x0b, 0x0b, - 0x08, 0x08, 0x09, 0x09, 0x08, 0x08, 0x09, 0x09, - 0x0a, 0x0a, 0x0b, 0x0b, 0x0a, 0x0a, 0x0b, 0x0b, - 0x0c, 0x0c, 0x0d, 0x0d, 0x0c, 0x0c, 0x0d, 0x0d, - 0x0e, 0x0e, 0x0f, 0x0f, 0x0e, 0x0e, 0x0f, 0x0f, - 0x0c, 0x0c, 0x0d, 0x0d, 0x0c, 0x0c, 0x0d, 0x0d, - 0x0e, 0x0e, 0x0f, 0x0f, 0x0e, 0x0e, 0x0f, 0x0f -}; - -/** - * __nand_calculate_ecc - [NAND Interface] Calculate 3-byte ECC for 256/512-byte - * block - * @buf: input buffer with raw data - * @eccsize: data bytes per ECC step (256 or 512) - * @code: output buffer with ECC - * @sm_order: Smart Media byte ordering - */ -void __nand_calculate_ecc(const unsigned char *buf, unsigned int eccsize, - unsigned char *code, bool sm_order) -{ - int i; - const uint32_t *bp = (uint32_t *)buf; - /* 256 or 512 bytes/ecc */ - const uint32_t eccsize_mult = eccsize >> 8; - uint32_t cur; /* current value in buffer */ - /* rp0..rp15..rp17 are the various accumulated parities (per byte) */ - uint32_t rp0, rp1, rp2, rp3, rp4, rp5, rp6, rp7; - uint32_t rp8, rp9, rp10, rp11, rp12, rp13, rp14, rp15, rp16; - uint32_t rp17; - uint32_t par; /* the cumulative parity for all data */ - uint32_t tmppar; /* the cumulative parity for this iteration; - for rp12, rp14 and rp16 at the end of the - loop */ - - par = 0; - rp4 = 0; - rp6 = 0; - rp8 = 0; - rp10 = 0; - rp12 = 0; - rp14 = 0; - rp16 = 0; - - /* - * The loop is unrolled a number of times; - * This avoids if statements to decide on which rp value to update - * Also we process the data by longwords. - * Note: passing unaligned data might give a performance penalty. - * It is assumed that the buffers are aligned. - * tmppar is the cumulative sum of this iteration. - * needed for calculating rp12, rp14, rp16 and par - * also used as a performance improvement for rp6, rp8 and rp10 - */ - for (i = 0; i < eccsize_mult << 2; i++) { - cur = *bp++; - tmppar = cur; - rp4 ^= cur; - cur = *bp++; - tmppar ^= cur; - rp6 ^= tmppar; - cur = *bp++; - tmppar ^= cur; - rp4 ^= cur; - cur = *bp++; - tmppar ^= cur; - rp8 ^= tmppar; - - cur = *bp++; - tmppar ^= cur; - rp4 ^= cur; - rp6 ^= cur; - cur = *bp++; - tmppar ^= cur; - rp6 ^= cur; - cur = *bp++; - tmppar ^= cur; - rp4 ^= cur; - cur = *bp++; - tmppar ^= cur; - rp10 ^= tmppar; - - cur = *bp++; - tmppar ^= cur; - rp4 ^= cur; - rp6 ^= cur; - rp8 ^= cur; - cur = *bp++; - tmppar ^= cur; - rp6 ^= cur; - rp8 ^= cur; - cur = *bp++; - tmppar ^= cur; - rp4 ^= cur; - rp8 ^= cur; - cur = *bp++; - tmppar ^= cur; - rp8 ^= cur; - - cur = *bp++; - tmppar ^= cur; - rp4 ^= cur; - rp6 ^= cur; - cur = *bp++; - tmppar ^= cur; - rp6 ^= cur; - cur = *bp++; - tmppar ^= cur; - rp4 ^= cur; - cur = *bp++; - tmppar ^= cur; - - par ^= tmppar; - if ((i & 0x1) == 0) - rp12 ^= tmppar; - if ((i & 0x2) == 0) - rp14 ^= tmppar; - if (eccsize_mult == 2 && (i & 0x4) == 0) - rp16 ^= tmppar; - } - - /* - * handle the fact that we use longword operations - * we'll bring rp4..rp14..rp16 back to single byte entities by - * shifting and xoring first fold the upper and lower 16 bits, - * then the upper and lower 8 bits. - */ - rp4 ^= (rp4 >> 16); - rp4 ^= (rp4 >> 8); - rp4 &= 0xff; - rp6 ^= (rp6 >> 16); - rp6 ^= (rp6 >> 8); - rp6 &= 0xff; - rp8 ^= (rp8 >> 16); - rp8 ^= (rp8 >> 8); - rp8 &= 0xff; - rp10 ^= (rp10 >> 16); - rp10 ^= (rp10 >> 8); - rp10 &= 0xff; - rp12 ^= (rp12 >> 16); - rp12 ^= (rp12 >> 8); - rp12 &= 0xff; - rp14 ^= (rp14 >> 16); - rp14 ^= (rp14 >> 8); - rp14 &= 0xff; - if (eccsize_mult == 2) { - rp16 ^= (rp16 >> 16); - rp16 ^= (rp16 >> 8); - rp16 &= 0xff; - } - - /* - * we also need to calculate the row parity for rp0..rp3 - * This is present in par, because par is now - * rp3 rp3 rp2 rp2 in little endian and - * rp2 rp2 rp3 rp3 in big endian - * as well as - * rp1 rp0 rp1 rp0 in little endian and - * rp0 rp1 rp0 rp1 in big endian - * First calculate rp2 and rp3 - */ -#ifdef __BIG_ENDIAN - rp2 = (par >> 16); - rp2 ^= (rp2 >> 8); - rp2 &= 0xff; - rp3 = par & 0xffff; - rp3 ^= (rp3 >> 8); - rp3 &= 0xff; -#else - rp3 = (par >> 16); - rp3 ^= (rp3 >> 8); - rp3 &= 0xff; - rp2 = par & 0xffff; - rp2 ^= (rp2 >> 8); - rp2 &= 0xff; -#endif - - /* reduce par to 16 bits then calculate rp1 and rp0 */ - par ^= (par >> 16); -#ifdef __BIG_ENDIAN - rp0 = (par >> 8) & 0xff; - rp1 = (par & 0xff); -#else - rp1 = (par >> 8) & 0xff; - rp0 = (par & 0xff); -#endif - - /* finally reduce par to 8 bits */ - par ^= (par >> 8); - par &= 0xff; - - /* - * and calculate rp5..rp15..rp17 - * note that par = rp4 ^ rp5 and due to the commutative property - * of the ^ operator we can say: - * rp5 = (par ^ rp4); - * The & 0xff seems superfluous, but benchmarking learned that - * leaving it out gives slightly worse results. No idea why, probably - * it has to do with the way the pipeline in pentium is organized. - */ - rp5 = (par ^ rp4) & 0xff; - rp7 = (par ^ rp6) & 0xff; - rp9 = (par ^ rp8) & 0xff; - rp11 = (par ^ rp10) & 0xff; - rp13 = (par ^ rp12) & 0xff; - rp15 = (par ^ rp14) & 0xff; - if (eccsize_mult == 2) - rp17 = (par ^ rp16) & 0xff; - - /* - * Finally calculate the ECC bits. - * Again here it might seem that there are performance optimisations - * possible, but benchmarks showed that on the system this is developed - * the code below is the fastest - */ - if (sm_order) { - code[0] = (invparity[rp7] << 7) | (invparity[rp6] << 6) | - (invparity[rp5] << 5) | (invparity[rp4] << 4) | - (invparity[rp3] << 3) | (invparity[rp2] << 2) | - (invparity[rp1] << 1) | (invparity[rp0]); - code[1] = (invparity[rp15] << 7) | (invparity[rp14] << 6) | - (invparity[rp13] << 5) | (invparity[rp12] << 4) | - (invparity[rp11] << 3) | (invparity[rp10] << 2) | - (invparity[rp9] << 1) | (invparity[rp8]); - } else { - code[1] = (invparity[rp7] << 7) | (invparity[rp6] << 6) | - (invparity[rp5] << 5) | (invparity[rp4] << 4) | - (invparity[rp3] << 3) | (invparity[rp2] << 2) | - (invparity[rp1] << 1) | (invparity[rp0]); - code[0] = (invparity[rp15] << 7) | (invparity[rp14] << 6) | - (invparity[rp13] << 5) | (invparity[rp12] << 4) | - (invparity[rp11] << 3) | (invparity[rp10] << 2) | - (invparity[rp9] << 1) | (invparity[rp8]); - } - - if (eccsize_mult == 1) - code[2] = - (invparity[par & 0xf0] << 7) | - (invparity[par & 0x0f] << 6) | - (invparity[par & 0xcc] << 5) | - (invparity[par & 0x33] << 4) | - (invparity[par & 0xaa] << 3) | - (invparity[par & 0x55] << 2) | - 3; - else - code[2] = - (invparity[par & 0xf0] << 7) | - (invparity[par & 0x0f] << 6) | - (invparity[par & 0xcc] << 5) | - (invparity[par & 0x33] << 4) | - (invparity[par & 0xaa] << 3) | - (invparity[par & 0x55] << 2) | - (invparity[rp17] << 1) | - (invparity[rp16] << 0); -} -EXPORT_SYMBOL(__nand_calculate_ecc); - -/** - * nand_calculate_ecc - [NAND Interface] Calculate 3-byte ECC for 256/512-byte - * block - * @chip: NAND chip object - * @buf: input buffer with raw data - * @code: output buffer with ECC - */ -int nand_calculate_ecc(struct nand_chip *chip, const unsigned char *buf, - unsigned char *code) -{ - bool sm_order = chip->ecc.options & NAND_ECC_SOFT_HAMMING_SM_ORDER; - - __nand_calculate_ecc(buf, chip->ecc.size, code, sm_order); - - return 0; -} -EXPORT_SYMBOL(nand_calculate_ecc); - -/** - * __nand_correct_data - [NAND Interface] Detect and correct bit error(s) - * @buf: raw data read from the chip - * @read_ecc: ECC from the chip - * @calc_ecc: the ECC calculated from raw data - * @eccsize: data bytes per ECC step (256 or 512) - * @sm_order: Smart Media byte order - * - * Detect and correct a 1 bit error for eccsize byte block - */ -int __nand_correct_data(unsigned char *buf, - unsigned char *read_ecc, unsigned char *calc_ecc, - unsigned int eccsize, bool sm_order) -{ - unsigned char b0, b1, b2, bit_addr; - unsigned int byte_addr; - /* 256 or 512 bytes/ecc */ - const uint32_t eccsize_mult = eccsize >> 8; - - /* - * b0 to b2 indicate which bit is faulty (if any) - * we might need the xor result more than once, - * so keep them in a local var - */ - if (sm_order) { - b0 = read_ecc[0] ^ calc_ecc[0]; - b1 = read_ecc[1] ^ calc_ecc[1]; - } else { - b0 = read_ecc[1] ^ calc_ecc[1]; - b1 = read_ecc[0] ^ calc_ecc[0]; - } - - b2 = read_ecc[2] ^ calc_ecc[2]; - - /* check if there are any bitfaults */ - - /* repeated if statements are slightly more efficient than switch ... */ - /* ordered in order of likelihood */ - - if ((b0 | b1 | b2) == 0) - return 0; /* no error */ - - if ((((b0 ^ (b0 >> 1)) & 0x55) == 0x55) && - (((b1 ^ (b1 >> 1)) & 0x55) == 0x55) && - ((eccsize_mult == 1 && ((b2 ^ (b2 >> 1)) & 0x54) == 0x54) || - (eccsize_mult == 2 && ((b2 ^ (b2 >> 1)) & 0x55) == 0x55))) { - /* single bit error */ - /* - * rp17/rp15/13/11/9/7/5/3/1 indicate which byte is the faulty - * byte, cp 5/3/1 indicate the faulty bit. - * A lookup table (called addressbits) is used to filter - * the bits from the byte they are in. - * A marginal optimisation is possible by having three - * different lookup tables. - * One as we have now (for b0), one for b2 - * (that would avoid the >> 1), and one for b1 (with all values - * << 4). However it was felt that introducing two more tables - * hardly justify the gain. - * - * The b2 shift is there to get rid of the lowest two bits. - * We could also do addressbits[b2] >> 1 but for the - * performance it does not make any difference - */ - if (eccsize_mult == 1) - byte_addr = (addressbits[b1] << 4) + addressbits[b0]; - else - byte_addr = (addressbits[b2 & 0x3] << 8) + - (addressbits[b1] << 4) + addressbits[b0]; - bit_addr = addressbits[b2 >> 2]; - /* flip the bit */ - buf[byte_addr] ^= (1 << bit_addr); - return 1; - - } - /* count nr of bits; use table lookup, faster than calculating it */ - if ((bitsperbyte[b0] + bitsperbyte[b1] + bitsperbyte[b2]) == 1) - return 1; /* error in ECC data; no action needed */ - - pr_err("%s: uncorrectable ECC error\n", __func__); - return -EBADMSG; -} -EXPORT_SYMBOL(__nand_correct_data); - -/** - * nand_correct_data - [NAND Interface] Detect and correct bit error(s) - * @chip: NAND chip object - * @buf: raw data read from the chip - * @read_ecc: ECC from the chip - * @calc_ecc: the ECC calculated from raw data - * - * Detect and correct a 1 bit error for 256/512 byte block - */ -int nand_correct_data(struct nand_chip *chip, unsigned char *buf, - unsigned char *read_ecc, unsigned char *calc_ecc) -{ - bool sm_order = chip->ecc.options & NAND_ECC_SOFT_HAMMING_SM_ORDER; - - return __nand_correct_data(buf, read_ecc, calc_ecc, chip->ecc.size, - sm_order); -} -EXPORT_SYMBOL(nand_correct_data); - -MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Frans Meulenbroeks "); -MODULE_DESCRIPTION("Generic NAND ECC support"); diff --git a/drivers/mtd/nand/raw/ndfc.c b/drivers/mtd/nand/raw/ndfc.c index 0fb4ba93c41e..8cda6633280b 100644 --- a/drivers/mtd/nand/raw/ndfc.c +++ b/drivers/mtd/nand/raw/ndfc.c @@ -18,7 +18,7 @@ */ #include #include -#include +#include #include #include #include diff --git a/drivers/mtd/nand/raw/pasemi_nand.c b/drivers/mtd/nand/raw/pasemi_nand.c index 4dfff34800f4..2dddbdca9e94 100644 --- a/drivers/mtd/nand/raw/pasemi_nand.c +++ b/drivers/mtd/nand/raw/pasemi_nand.c @@ -14,7 +14,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/drivers/mtd/nand/raw/s3c2410.c b/drivers/mtd/nand/raw/s3c2410.c index fbd0fa48e063..f7eb3b5fa792 100644 --- a/drivers/mtd/nand/raw/s3c2410.c +++ b/drivers/mtd/nand/raw/s3c2410.c @@ -30,7 +30,7 @@ #include #include -#include +#include #include #include diff --git a/drivers/mtd/nand/raw/sharpsl.c b/drivers/mtd/nand/raw/sharpsl.c index af98bcc9d689..2fae6ade8b13 100644 --- a/drivers/mtd/nand/raw/sharpsl.c +++ b/drivers/mtd/nand/raw/sharpsl.c @@ -12,7 +12,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/drivers/mtd/nand/raw/tmio_nand.c b/drivers/mtd/nand/raw/tmio_nand.c index aa6c7e7bbf1b..fadca0b9e21f 100644 --- a/drivers/mtd/nand/raw/tmio_nand.c +++ b/drivers/mtd/nand/raw/tmio_nand.c @@ -35,7 +35,7 @@ #include #include #include -#include +#include #include #include diff --git a/drivers/mtd/nand/raw/txx9ndfmc.c b/drivers/mtd/nand/raw/txx9ndfmc.c index fe8ed2441588..68b920eab6c8 100644 --- a/drivers/mtd/nand/raw/txx9ndfmc.c +++ b/drivers/mtd/nand/raw/txx9ndfmc.c @@ -14,7 +14,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/drivers/mtd/sm_ftl.c b/drivers/mtd/sm_ftl.c index b9f272408c4d..db430ae6a1a2 100644 --- a/drivers/mtd/sm_ftl.c +++ b/drivers/mtd/sm_ftl.c @@ -13,7 +13,7 @@ #include #include #include -#include +#include #include "nand/raw/sm_common.h" #include "sm_ftl.h" diff --git a/drivers/mtd/tests/mtd_nandecctest.c b/drivers/mtd/tests/mtd_nandecctest.c index 13bca9ea0cae..e92e3fb287b6 100644 --- a/drivers/mtd/tests/mtd_nandecctest.c +++ b/drivers/mtd/tests/mtd_nandecctest.c @@ -8,7 +8,7 @@ #include #include #include -#include +#include #include "mtd_test.h" diff --git a/include/linux/mtd/nand-ecc-sw-hamming.h b/include/linux/mtd/nand-ecc-sw-hamming.h new file mode 100644 index 000000000000..30a0cfa50eed --- /dev/null +++ b/include/linux/mtd/nand-ecc-sw-hamming.h @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2000-2010 Steven J. Hill + * David Woodhouse + * Thomas Gleixner + * + * This file is the header for the ECC algorithm. + */ + +#ifndef __MTD_NAND_ECC_SW_HAMMING_H__ +#define __MTD_NAND_ECC_SW_HAMMING_H__ + +struct nand_chip; + +/* + * Calculate 3 byte ECC code for eccsize byte block + */ +void __nand_calculate_ecc(const u_char *dat, unsigned int eccsize, + u_char *ecc_code, bool sm_order); + +/* + * Calculate 3 byte ECC code for 256/512 byte block + */ +int nand_calculate_ecc(struct nand_chip *chip, const u_char *dat, + u_char *ecc_code); + +/* + * Detect and correct a 1 bit error for eccsize byte block + */ +int __nand_correct_data(u_char *dat, u_char *read_ecc, u_char *calc_ecc, + unsigned int eccsize, bool sm_order); + +/* + * Detect and correct a 1 bit error for 256/512 byte block + */ +int nand_correct_data(struct nand_chip *chip, u_char *dat, u_char *read_ecc, + u_char *calc_ecc); + +#endif /* __MTD_NAND_ECC_SW_HAMMING_H__ */ diff --git a/include/linux/mtd/nand_ecc.h b/include/linux/mtd/nand_ecc.h deleted file mode 100644 index d423916b94f0..000000000000 --- a/include/linux/mtd/nand_ecc.h +++ /dev/null @@ -1,39 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (C) 2000-2010 Steven J. Hill - * David Woodhouse - * Thomas Gleixner - * - * This file is the header for the ECC algorithm. - */ - -#ifndef __MTD_NAND_ECC_H__ -#define __MTD_NAND_ECC_H__ - -struct nand_chip; - -/* - * Calculate 3 byte ECC code for eccsize byte block - */ -void __nand_calculate_ecc(const u_char *dat, unsigned int eccsize, - u_char *ecc_code, bool sm_order); - -/* - * Calculate 3 byte ECC code for 256/512 byte block - */ -int nand_calculate_ecc(struct nand_chip *chip, const u_char *dat, - u_char *ecc_code); - -/* - * Detect and correct a 1 bit error for eccsize byte block - */ -int __nand_correct_data(u_char *dat, u_char *read_ecc, u_char *calc_ecc, - unsigned int eccsize, bool sm_order); - -/* - * Detect and correct a 1 bit error for 256/512 byte block - */ -int nand_correct_data(struct nand_chip *chip, u_char *dat, u_char *read_ecc, - u_char *calc_ecc); - -#endif /* __MTD_NAND_ECC_H__ */ diff --git a/include/linux/mtd/sharpsl.h b/include/linux/mtd/sharpsl.h index d2c3cf29e0d1..3762a90077d6 100644 --- a/include/linux/mtd/sharpsl.h +++ b/include/linux/mtd/sharpsl.h @@ -9,7 +9,7 @@ #define _MTD_SHARPSL_H #include -#include +#include #include struct sharpsl_nand_platform_data { -- cgit v1.2.3-59-g8ed1b From 914ee96654d87abc548bdd44ad9e4b3a14173cac Mon Sep 17 00:00:00 2001 From: Palmer Dabbelt Date: Thu, 9 Jul 2020 12:00:10 -0700 Subject: arm: Use the generic devmem_is_allowed() This is exactly the same as the arm64 version, which I recently copied into lib/ for use by the RISC-V port. Reviewed-by: Luis Chamberlain Signed-off-by: Palmer Dabbelt --- arch/arm/Kconfig | 2 +- arch/arm/include/asm/io.h | 1 - arch/arm/mm/mmap.c | 22 ---------------------- 3 files changed, 1 insertion(+), 24 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index e00d94b16658..16095d3ab453 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -5,7 +5,6 @@ config ARM select ARCH_32BIT_OFF_T select ARCH_HAS_BINFMT_FLAT select ARCH_HAS_DEBUG_VIRTUAL if MMU - select ARCH_HAS_DEVMEM_IS_ALLOWED select ARCH_HAS_DMA_WRITE_COMBINE if !ARM_DMA_MEM_BUFFERABLE select ARCH_HAS_ELF_RANDOMIZE select ARCH_HAS_FORTIFY_SOURCE @@ -55,6 +54,7 @@ config ARM select GENERIC_IRQ_PROBE select GENERIC_IRQ_SHOW select GENERIC_IRQ_SHOW_LEVEL + select GENERIC_LIB_DEVMEM_IS_ALLOWED select GENERIC_PCI_IOMAP select GENERIC_SCHED_CLOCK select GENERIC_SMP_IDLE_THREAD diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h index ab2b654084fa..fc748122f1e0 100644 --- a/arch/arm/include/asm/io.h +++ b/arch/arm/include/asm/io.h @@ -441,7 +441,6 @@ extern void pci_iounmap(struct pci_dev *dev, void __iomem *addr); #define ARCH_HAS_VALID_PHYS_ADDR_RANGE extern int valid_phys_addr_range(phys_addr_t addr, size_t size); extern int valid_mmap_phys_addr_range(unsigned long pfn, size_t size); -extern int devmem_is_allowed(unsigned long pfn); #endif /* diff --git a/arch/arm/mm/mmap.c b/arch/arm/mm/mmap.c index b8d912ac9e61..a0f8a0ca0788 100644 --- a/arch/arm/mm/mmap.c +++ b/arch/arm/mm/mmap.c @@ -165,25 +165,3 @@ int valid_mmap_phys_addr_range(unsigned long pfn, size_t size) { return (pfn + (size >> PAGE_SHIFT)) <= (1 + (PHYS_MASK >> PAGE_SHIFT)); } - -#ifdef CONFIG_STRICT_DEVMEM - -#include - -/* - * devmem_is_allowed() checks to see if /dev/mem access to a certain - * address is valid. The argument is a physical page number. - * We mimic x86 here by disallowing access to system RAM as well as - * device-exclusive MMIO regions. This effectively disable read()/write() - * on /dev/mem. - */ -int devmem_is_allowed(unsigned long pfn) -{ - if (iomem_is_exclusive(pfn << PAGE_SHIFT)) - return 0; - if (!page_is_ram(pfn)) - return 1; - return 0; -} - -#endif -- cgit v1.2.3-59-g8ed1b From 18ce7f4fde3149c729f53a987dbbbba92e08ae24 Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Thu, 10 Dec 2020 10:29:03 -0600 Subject: ARM: dts: lpc32xx: Remove unused and undocumented 'pnx,timeout' 'pnx,timeout' is unused, undocumented and 'pnx' is not a vendor prefix, so let's remove it. Acked-by: Vladimir Zapolskiy Cc: Sylvain Lemieux Link: https://lore.kernel.org/r/20201210175238.2721550-1-robh@kernel.org Signed-off-by: Rob Herring --- arch/arm/boot/dts/lpc32xx.dtsi | 3 --- 1 file changed, 3 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/lpc32xx.dtsi b/arch/arm/boot/dts/lpc32xx.dtsi index 7b7ec7b1217b..3a5cfb0ddb20 100644 --- a/arch/arm/boot/dts/lpc32xx.dtsi +++ b/arch/arm/boot/dts/lpc32xx.dtsi @@ -123,7 +123,6 @@ clocks = <&usbclk LPC32XX_USB_CLK_I2C>; #address-cells = <1>; #size-cells = <0>; - pnx,timeout = <0x64>; }; usbclk: clock-controller@f00 { @@ -286,7 +285,6 @@ interrupts = <19 IRQ_TYPE_LEVEL_LOW>; #address-cells = <1>; #size-cells = <0>; - pnx,timeout = <0x64>; clocks = <&clk LPC32XX_CLK_I2C1>; }; @@ -297,7 +295,6 @@ interrupts = <18 IRQ_TYPE_LEVEL_LOW>; #address-cells = <1>; #size-cells = <0>; - pnx,timeout = <0x64>; clocks = <&clk LPC32XX_CLK_I2C2>; }; -- cgit v1.2.3-59-g8ed1b From d72c8b0e1cacc39495cd413433d260e8ae59374a Mon Sep 17 00:00:00 2001 From: Ard Biesheuvel Date: Sun, 13 Dec 2020 16:07:03 +0100 Subject: efi: arm: force use of unsigned type for EFI_PHYS_ALIGN Ensure that EFI_PHYS_ALIGN is an unsigned type, to prevent spurious warnings from the type checks in the definition of the max() macro. Link: https://lore.kernel.org/linux-efi/20201213151306.73558-1-ardb@kernel.org Signed-off-by: Ard Biesheuvel --- arch/arm/include/asm/efi.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/include/asm/efi.h b/arch/arm/include/asm/efi.h index abae071a02e1..9de7ab2ce05d 100644 --- a/arch/arm/include/asm/efi.h +++ b/arch/arm/include/asm/efi.h @@ -71,7 +71,7 @@ static inline void efifb_setup_from_dmi(struct screen_info *si, const char *opt) * here throws off the memory allocation logic, so let's use the lowest power * of two greater than 2 MiB and greater than TEXT_OFFSET. */ -#define EFI_PHYS_ALIGN max(SZ_2M, roundup_pow_of_two(TEXT_OFFSET)) +#define EFI_PHYS_ALIGN max(UL(SZ_2M), roundup_pow_of_two(TEXT_OFFSET)) /* on ARM, the initrd should be loaded in a lowmem region */ static inline unsigned long efi_get_max_initrd_addr(unsigned long image_addr) -- cgit v1.2.3-59-g8ed1b From 88c637748e3176dcfaa36185e5eaafe6098d43e0 Mon Sep 17 00:00:00 2001 From: Thomas Gleixner Date: Thu, 10 Dec 2020 20:25:45 +0100 Subject: ARM: smp: Use irq_desc_kstat_cpu() in show_ipi_list() The irq descriptor is already there, no need to look it up again. Signed-off-by: Thomas Gleixner Acked-by: Marc Zyngier Link: https://lore.kernel.org/r/20201210194043.454288890@linutronix.de --- arch/arm/kernel/smp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c index 48099c6e1e4a..e66c46aba5b4 100644 --- a/arch/arm/kernel/smp.c +++ b/arch/arm/kernel/smp.c @@ -550,7 +550,7 @@ void show_ipi_list(struct seq_file *p, int prec) seq_printf(p, "%*s%u: ", prec - 1, "IPI", i); for_each_online_cpu(cpu) - seq_printf(p, "%10u ", kstat_irqs_cpu(irq, cpu)); + seq_printf(p, "%10u ", irq_desc_kstat_cpu(ipi_desc[i], cpu)); seq_printf(p, " %s\n", ipi_types[i]); } -- cgit v1.2.3-59-g8ed1b From 871402e05b24cb56bc69df47cff960d0e0d24267 Mon Sep 17 00:00:00 2001 From: Dmitry Safonov Date: Mon, 14 Dec 2020 19:08:25 -0800 Subject: mm: forbid splitting special mappings Don't allow splitting of vm_special_mapping's. It affects vdso/vvar areas. Uprobes have only one page in xol_area so they aren't affected. Those restrictions were enforced by checks in .mremap() callbacks. Restrict resizing with generic .split() callback. Link: https://lkml.kernel.org/r/20201013013416.390574-7-dima@arista.com Signed-off-by: Dmitry Safonov Cc: Alexander Viro Cc: Andy Lutomirski Cc: Brian Geffon Cc: Catalin Marinas Cc: Dan Carpenter Cc: Dan Williams Cc: Dave Jiang Cc: Hugh Dickins Cc: Ingo Molnar Cc: Jason Gunthorpe Cc: John Hubbard Cc: "Kirill A. Shutemov" Cc: Mike Kravetz Cc: Minchan Kim Cc: Ralph Campbell Cc: Russell King Cc: Thomas Bogendoerfer Cc: Thomas Gleixner Cc: Vishal Verma Cc: Vlastimil Babka Cc: Will Deacon Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- arch/arm/kernel/vdso.c | 9 --------- arch/arm64/kernel/vdso.c | 39 +++------------------------------------ arch/mips/vdso/genvdso.c | 4 ---- arch/s390/kernel/vdso.c | 11 +---------- arch/x86/entry/vdso/vma.c | 17 ----------------- mm/mmap.c | 12 ++++++++++++ 6 files changed, 16 insertions(+), 76 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/kernel/vdso.c b/arch/arm/kernel/vdso.c index fddd08a6e063..3408269d19c7 100644 --- a/arch/arm/kernel/vdso.c +++ b/arch/arm/kernel/vdso.c @@ -50,15 +50,6 @@ static const struct vm_special_mapping vdso_data_mapping = { static int vdso_mremap(const struct vm_special_mapping *sm, struct vm_area_struct *new_vma) { - unsigned long new_size = new_vma->vm_end - new_vma->vm_start; - unsigned long vdso_size; - - /* without VVAR page */ - vdso_size = (vdso_total_pages - 1) << PAGE_SHIFT; - - if (vdso_size != new_size) - return -EINVAL; - current->mm->context.vdso = new_vma->vm_start; return 0; diff --git a/arch/arm64/kernel/vdso.c b/arch/arm64/kernel/vdso.c index debb8995d57f..cee5d04ea9ad 100644 --- a/arch/arm64/kernel/vdso.c +++ b/arch/arm64/kernel/vdso.c @@ -78,17 +78,9 @@ static union { } vdso_data_store __page_aligned_data; struct vdso_data *vdso_data = vdso_data_store.data; -static int __vdso_remap(enum vdso_abi abi, - const struct vm_special_mapping *sm, - struct vm_area_struct *new_vma) +static int vdso_mremap(const struct vm_special_mapping *sm, + struct vm_area_struct *new_vma) { - unsigned long new_size = new_vma->vm_end - new_vma->vm_start; - unsigned long vdso_size = vdso_info[abi].vdso_code_end - - vdso_info[abi].vdso_code_start; - - if (vdso_size != new_size) - return -EINVAL; - current->mm->context.vdso = (void *)new_vma->vm_start; return 0; @@ -219,17 +211,6 @@ static vm_fault_t vvar_fault(const struct vm_special_mapping *sm, return vmf_insert_pfn(vma, vmf->address, pfn); } -static int vvar_mremap(const struct vm_special_mapping *sm, - struct vm_area_struct *new_vma) -{ - unsigned long new_size = new_vma->vm_end - new_vma->vm_start; - - if (new_size != VVAR_NR_PAGES * PAGE_SIZE) - return -EINVAL; - - return 0; -} - static int __setup_additional_pages(enum vdso_abi abi, struct mm_struct *mm, struct linux_binprm *bprm, @@ -280,12 +261,6 @@ up_fail: /* * Create and map the vectors page for AArch32 tasks. */ -static int aarch32_vdso_mremap(const struct vm_special_mapping *sm, - struct vm_area_struct *new_vma) -{ - return __vdso_remap(VDSO_ABI_AA32, sm, new_vma); -} - enum aarch32_map { AA32_MAP_VECTORS, /* kuser helpers */ AA32_MAP_SIGPAGE, @@ -308,11 +283,10 @@ static struct vm_special_mapping aarch32_vdso_maps[] = { [AA32_MAP_VVAR] = { .name = "[vvar]", .fault = vvar_fault, - .mremap = vvar_mremap, }, [AA32_MAP_VDSO] = { .name = "[vdso]", - .mremap = aarch32_vdso_mremap, + .mremap = vdso_mremap, }, }; @@ -453,12 +427,6 @@ out: } #endif /* CONFIG_COMPAT */ -static int vdso_mremap(const struct vm_special_mapping *sm, - struct vm_area_struct *new_vma) -{ - return __vdso_remap(VDSO_ABI_AA64, sm, new_vma); -} - enum aarch64_map { AA64_MAP_VVAR, AA64_MAP_VDSO, @@ -468,7 +436,6 @@ static struct vm_special_mapping aarch64_vdso_maps[] __ro_after_init = { [AA64_MAP_VVAR] = { .name = "[vvar]", .fault = vvar_fault, - .mremap = vvar_mremap, }, [AA64_MAP_VDSO] = { .name = "[vdso]", diff --git a/arch/mips/vdso/genvdso.c b/arch/mips/vdso/genvdso.c index abb06ae04b40..09e30eb4be86 100644 --- a/arch/mips/vdso/genvdso.c +++ b/arch/mips/vdso/genvdso.c @@ -263,10 +263,6 @@ int main(int argc, char **argv) fprintf(out_file, " const struct vm_special_mapping *sm,\n"); fprintf(out_file, " struct vm_area_struct *new_vma)\n"); fprintf(out_file, "{\n"); - fprintf(out_file, " unsigned long new_size =\n"); - fprintf(out_file, " new_vma->vm_end - new_vma->vm_start;\n"); - fprintf(out_file, " if (vdso_image.size != new_size)\n"); - fprintf(out_file, " return -EINVAL;\n"); fprintf(out_file, " current->mm->context.vdso =\n"); fprintf(out_file, " (void *)(new_vma->vm_start);\n"); fprintf(out_file, " return 0;\n"); diff --git a/arch/s390/kernel/vdso.c b/arch/s390/kernel/vdso.c index f9da5b149141..6c9ec9521203 100644 --- a/arch/s390/kernel/vdso.c +++ b/arch/s390/kernel/vdso.c @@ -61,17 +61,8 @@ static vm_fault_t vdso_fault(const struct vm_special_mapping *sm, static int vdso_mremap(const struct vm_special_mapping *sm, struct vm_area_struct *vma) { - unsigned long vdso_pages; - - vdso_pages = vdso64_pages; - - if ((vdso_pages << PAGE_SHIFT) != vma->vm_end - vma->vm_start) - return -EINVAL; - - if (WARN_ON_ONCE(current->mm != vma->vm_mm)) - return -EFAULT; - current->mm->context.vdso_base = vma->vm_start; + return 0; } diff --git a/arch/x86/entry/vdso/vma.c b/arch/x86/entry/vdso/vma.c index 9185cb1d13b9..0c942b31825d 100644 --- a/arch/x86/entry/vdso/vma.c +++ b/arch/x86/entry/vdso/vma.c @@ -89,30 +89,14 @@ static void vdso_fix_landing(const struct vdso_image *image, static int vdso_mremap(const struct vm_special_mapping *sm, struct vm_area_struct *new_vma) { - unsigned long new_size = new_vma->vm_end - new_vma->vm_start; const struct vdso_image *image = current->mm->context.vdso_image; - if (image->size != new_size) - return -EINVAL; - vdso_fix_landing(image, new_vma); current->mm->context.vdso = (void __user *)new_vma->vm_start; return 0; } -static int vvar_mremap(const struct vm_special_mapping *sm, - struct vm_area_struct *new_vma) -{ - const struct vdso_image *image = new_vma->vm_mm->context.vdso_image; - unsigned long new_size = new_vma->vm_end - new_vma->vm_start; - - if (new_size != -image->sym_vvar_start) - return -EINVAL; - - return 0; -} - #ifdef CONFIG_TIME_NS static struct page *find_timens_vvar_page(struct vm_area_struct *vma) { @@ -252,7 +236,6 @@ static const struct vm_special_mapping vdso_mapping = { static const struct vm_special_mapping vvar_mapping = { .name = "[vvar]", .fault = vvar_fault, - .mremap = vvar_mremap, }; /* diff --git a/mm/mmap.c b/mm/mmap.c index 886de799e7d2..10598e5d4757 100644 --- a/mm/mmap.c +++ b/mm/mmap.c @@ -3422,6 +3422,17 @@ static int special_mapping_mremap(struct vm_area_struct *new_vma, return 0; } +static int special_mapping_split(struct vm_area_struct *vma, unsigned long addr) +{ + /* + * Forbid splitting special mappings - kernel has expectations over + * the number of pages in mapping. Together with VM_DONTEXPAND + * the size of vma should stay the same over the special mapping's + * lifetime. + */ + return -EINVAL; +} + static const struct vm_operations_struct special_mapping_vmops = { .close = special_mapping_close, .fault = special_mapping_fault, @@ -3429,6 +3440,7 @@ static const struct vm_operations_struct special_mapping_vmops = { .name = special_mapping_name, /* vDSO code relies that VVAR can't be accessed remotely */ .access = NULL, + .may_split = special_mapping_split, }; static const struct vm_operations_struct legacy_special_mapping_vmops = { -- cgit v1.2.3-59-g8ed1b From 5e545df3292fbd3d5963c68980f1527ead2a2b3f Mon Sep 17 00:00:00 2001 From: Mike Rapoport Date: Mon, 14 Dec 2020 19:09:55 -0800 Subject: arm: remove CONFIG_ARCH_HAS_HOLES_MEMORYMODEL ARM is the only architecture that defines CONFIG_ARCH_HAS_HOLES_MEMORYMODEL which in turn enables memmap_valid_within() function that is intended to verify existence of struct page associated with a pfn when there are holes in the memory map. However, the ARCH_HAS_HOLES_MEMORYMODEL also enables HAVE_ARCH_PFN_VALID and arch-specific pfn_valid() implementation that also deals with the holes in the memory map. The only two users of memmap_valid_within() call this function after a call to pfn_valid() so the memmap_valid_within() check becomes redundant. Remove CONFIG_ARCH_HAS_HOLES_MEMORYMODEL and memmap_valid_within() and rely entirely on ARM's implementation of pfn_valid() that is now enabled unconditionally. Link: https://lkml.kernel.org/r/20201101170454.9567-9-rppt@kernel.org Signed-off-by: Mike Rapoport Cc: Alexey Dobriyan Cc: Catalin Marinas Cc: Geert Uytterhoeven Cc: Greg Ungerer Cc: John Paul Adrian Glaubitz Cc: Jonathan Corbet Cc: Matt Turner Cc: Meelis Roos Cc: Michael Schmitz Cc: Russell King Cc: Tony Luck Cc: Vineet Gupta Cc: Will Deacon Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- Documentation/vm/memory-model.rst | 3 +-- arch/arm/Kconfig | 8 ++------ arch/arm/mach-bcm/Kconfig | 1 - arch/arm/mach-davinci/Kconfig | 1 - arch/arm/mach-exynos/Kconfig | 1 - arch/arm/mach-highbank/Kconfig | 1 - arch/arm/mach-omap2/Kconfig | 1 - arch/arm/mach-s5pv210/Kconfig | 1 - arch/arm/mach-tango/Kconfig | 1 - fs/proc/kcore.c | 2 -- include/linux/mmzone.h | 31 ------------------------------- mm/mmzone.c | 14 -------------- mm/vmstat.c | 4 ---- 13 files changed, 3 insertions(+), 66 deletions(-) (limited to 'arch/arm') diff --git a/Documentation/vm/memory-model.rst b/Documentation/vm/memory-model.rst index 9daadf9faba1..ce398a7dc6cd 100644 --- a/Documentation/vm/memory-model.rst +++ b/Documentation/vm/memory-model.rst @@ -51,8 +51,7 @@ call :c:func:`free_area_init` function. Yet, the mappings array is not usable until the call to :c:func:`memblock_free_all` that hands all the memory to the page allocator. -If an architecture enables `CONFIG_ARCH_HAS_HOLES_MEMORYMODEL` option, -it may free parts of the `mem_map` array that do not cover the +An architecture may free parts of the `mem_map` array that do not cover the actual physical pages. In such case, the architecture specific :c:func:`pfn_valid` implementation should take the holes in the `mem_map` into account. diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 002e0cf025f5..353c3979a2d5 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -25,7 +25,7 @@ config ARM select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST select ARCH_HAVE_CUSTOM_GPIO_H select ARCH_HAS_GCOV_PROFILE_ALL - select ARCH_KEEP_MEMBLOCK if HAVE_ARCH_PFN_VALID || KEXEC + select ARCH_KEEP_MEMBLOCK select ARCH_MIGHT_HAVE_PC_PARPORT select ARCH_NO_SG_CHAIN if !ARM_HAS_SG_CHAIN select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX @@ -520,7 +520,6 @@ config ARCH_S3C24XX config ARCH_OMAP1 bool "TI OMAP1" depends on MMU - select ARCH_HAS_HOLES_MEMORYMODEL select ARCH_OMAP select CLKDEV_LOOKUP select CLKSRC_MMIO @@ -1480,9 +1479,6 @@ config OABI_COMPAT UNPREDICTABLE (in fact it can be predicted that it won't work at all). If in doubt say N. -config ARCH_HAS_HOLES_MEMORYMODEL - bool - config ARCH_SELECT_MEMORY_MODEL bool @@ -1494,7 +1490,7 @@ config ARCH_SPARSEMEM_ENABLE select SPARSEMEM_STATIC if SPARSEMEM config HAVE_ARCH_PFN_VALID - def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM + def_bool y config HIGHMEM bool "High Memory Support" diff --git a/arch/arm/mach-bcm/Kconfig b/arch/arm/mach-bcm/Kconfig index ae790908fc74..9b594ae98153 100644 --- a/arch/arm/mach-bcm/Kconfig +++ b/arch/arm/mach-bcm/Kconfig @@ -211,7 +211,6 @@ config ARCH_BRCMSTB select BCM7038_L1_IRQ select BRCMSTB_L2_IRQ select BCM7120_L2_IRQ - select ARCH_HAS_HOLES_MEMORYMODEL select ZONE_DMA if ARM_LPAE select SOC_BRCMSTB select SOC_BUS diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig index f56ff8c24043..de11030748d0 100644 --- a/arch/arm/mach-davinci/Kconfig +++ b/arch/arm/mach-davinci/Kconfig @@ -5,7 +5,6 @@ menuconfig ARCH_DAVINCI depends on ARCH_MULTI_V5 select DAVINCI_TIMER select ZONE_DMA - select ARCH_HAS_HOLES_MEMORYMODEL select PM_GENERIC_DOMAINS if PM select PM_GENERIC_DOMAINS_OF if PM && OF select REGMAP_MMIO diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig index d2d249706ebb..56d272967fc0 100644 --- a/arch/arm/mach-exynos/Kconfig +++ b/arch/arm/mach-exynos/Kconfig @@ -8,7 +8,6 @@ menuconfig ARCH_EXYNOS bool "Samsung Exynos" depends on ARCH_MULTI_V7 - select ARCH_HAS_HOLES_MEMORYMODEL select ARCH_SUPPORTS_BIG_ENDIAN select ARM_AMBA select ARM_GIC diff --git a/arch/arm/mach-highbank/Kconfig b/arch/arm/mach-highbank/Kconfig index 1bc68913d62c..9de38ce8124f 100644 --- a/arch/arm/mach-highbank/Kconfig +++ b/arch/arm/mach-highbank/Kconfig @@ -2,7 +2,6 @@ config ARCH_HIGHBANK bool "Calxeda ECX-1000/2000 (Highbank/Midway)" depends on ARCH_MULTI_V7 - select ARCH_HAS_HOLES_MEMORYMODEL select ARCH_SUPPORTS_BIG_ENDIAN select ARM_AMBA select ARM_ERRATA_764369 if SMP diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index 3f62a0c9450d..164985505f9e 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig @@ -93,7 +93,6 @@ config SOC_DRA7XX config ARCH_OMAP2PLUS bool select ARCH_HAS_BANDGAP - select ARCH_HAS_HOLES_MEMORYMODEL select ARCH_HAS_RESET_CONTROLLER select ARCH_OMAP select CLKSRC_MMIO diff --git a/arch/arm/mach-s5pv210/Kconfig b/arch/arm/mach-s5pv210/Kconfig index 95d4e8284866..d644b45bc29d 100644 --- a/arch/arm/mach-s5pv210/Kconfig +++ b/arch/arm/mach-s5pv210/Kconfig @@ -8,7 +8,6 @@ config ARCH_S5PV210 bool "Samsung S5PV210/S5PC110" depends on ARCH_MULTI_V7 - select ARCH_HAS_HOLES_MEMORYMODEL select ARM_VIC select CLKSRC_SAMSUNG_PWM select COMMON_CLK_SAMSUNG diff --git a/arch/arm/mach-tango/Kconfig b/arch/arm/mach-tango/Kconfig index 25b2fd434861..a9eeda36aeb1 100644 --- a/arch/arm/mach-tango/Kconfig +++ b/arch/arm/mach-tango/Kconfig @@ -3,7 +3,6 @@ config ARCH_TANGO bool "Sigma Designs Tango4 (SMP87xx)" depends on ARCH_MULTI_V7 # Cortex-A9 MPCore r3p0, PL310 r3p2 - select ARCH_HAS_HOLES_MEMORYMODEL select ARM_ERRATA_754322 select ARM_ERRATA_764369 if SMP select ARM_ERRATA_775420 diff --git a/fs/proc/kcore.c b/fs/proc/kcore.c index e502414b3556..4d2e64e9016c 100644 --- a/fs/proc/kcore.c +++ b/fs/proc/kcore.c @@ -193,8 +193,6 @@ kclist_add_private(unsigned long pfn, unsigned long nr_pages, void *arg) return 1; p = pfn_to_page(pfn); - if (!memmap_valid_within(pfn, p, page_zone(p))) - return 1; ent = kmalloc(sizeof(*ent), GFP_KERNEL); if (!ent) diff --git a/include/linux/mmzone.h b/include/linux/mmzone.h index 16fb5522a74f..6e0025b5a88f 100644 --- a/include/linux/mmzone.h +++ b/include/linux/mmzone.h @@ -1440,37 +1440,6 @@ void sparse_init(void); #define pfn_valid_within(pfn) (1) #endif -#ifdef CONFIG_ARCH_HAS_HOLES_MEMORYMODEL -/* - * pfn_valid() is meant to be able to tell if a given PFN has valid memmap - * associated with it or not. This means that a struct page exists for this - * pfn. The caller cannot assume the page is fully initialized in general. - * Hotplugable pages might not have been onlined yet. pfn_to_online_page() - * will ensure the struct page is fully online and initialized. Special pages - * (e.g. ZONE_DEVICE) are never onlined and should be treated accordingly. - * - * In FLATMEM, it is expected that holes always have valid memmap as long as - * there is valid PFNs either side of the hole. In SPARSEMEM, it is assumed - * that a valid section has a memmap for the entire section. - * - * However, an ARM, and maybe other embedded architectures in the future - * free memmap backing holes to save memory on the assumption the memmap is - * never used. The page_zone linkages are then broken even though pfn_valid() - * returns true. A walker of the full memmap must then do this additional - * check to ensure the memmap they are looking at is sane by making sure - * the zone and PFN linkages are still valid. This is expensive, but walkers - * of the full memmap are extremely rare. - */ -bool memmap_valid_within(unsigned long pfn, - struct page *page, struct zone *zone); -#else -static inline bool memmap_valid_within(unsigned long pfn, - struct page *page, struct zone *zone) -{ - return true; -} -#endif /* CONFIG_ARCH_HAS_HOLES_MEMORYMODEL */ - #endif /* !__GENERATING_BOUNDS.H */ #endif /* !__ASSEMBLY__ */ #endif /* _LINUX_MMZONE_H */ diff --git a/mm/mmzone.c b/mm/mmzone.c index 4686fdc23bb9..f337831affc2 100644 --- a/mm/mmzone.c +++ b/mm/mmzone.c @@ -72,20 +72,6 @@ struct zoneref *__next_zones_zonelist(struct zoneref *z, return z; } -#ifdef CONFIG_ARCH_HAS_HOLES_MEMORYMODEL -bool memmap_valid_within(unsigned long pfn, - struct page *page, struct zone *zone) -{ - if (page_to_pfn(page) != pfn) - return false; - - if (page_zone(page) != zone) - return false; - - return true; -} -#endif /* CONFIG_ARCH_HAS_HOLES_MEMORYMODEL */ - void lruvec_init(struct lruvec *lruvec) { enum lru_list lru; diff --git a/mm/vmstat.c b/mm/vmstat.c index da36e3b0aab2..f8942160fc95 100644 --- a/mm/vmstat.c +++ b/mm/vmstat.c @@ -1503,10 +1503,6 @@ static void pagetypeinfo_showblockcount_print(struct seq_file *m, if (!page) continue; - /* Watch for unexpected holes punched in the memmap */ - if (!memmap_valid_within(pfn, page, zone)) - continue; - if (page_zone(page) != zone) continue; -- cgit v1.2.3-59-g8ed1b From 4f5b0c1789963477cc9a4d45b4b62d694665cceb Mon Sep 17 00:00:00 2001 From: Mike Rapoport Date: Mon, 14 Dec 2020 19:09:59 -0800 Subject: arm, arm64: move free_unused_memmap() to generic mm ARM and ARM64 free unused parts of the memory map just before the initialization of the page allocator. To allow holes in the memory map both architectures overload pfn_valid() and define HAVE_ARCH_PFN_VALID. Allowing holes in the memory map for FLATMEM may be useful for small machines, such as ARC and m68k and will enable those architectures to cease using DISCONTIGMEM and still support more than one memory bank. Move the functions that free unused memory map to generic mm and enable them in case HAVE_ARCH_PFN_VALID=y. Link: https://lkml.kernel.org/r/20201101170454.9567-10-rppt@kernel.org Signed-off-by: Mike Rapoport Acked-by: Catalin Marinas [arm64] Cc: Alexey Dobriyan Cc: Geert Uytterhoeven Cc: Greg Ungerer Cc: John Paul Adrian Glaubitz Cc: Jonathan Corbet Cc: Matt Turner Cc: Meelis Roos Cc: Michael Schmitz Cc: Russell King Cc: Tony Luck Cc: Vineet Gupta Cc: Will Deacon Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- arch/Kconfig | 3 ++ arch/arm/Kconfig | 4 +-- arch/arm/mm/init.c | 78 -------------------------------------------------- arch/arm64/Kconfig | 4 +-- arch/arm64/mm/init.c | 68 -------------------------------------------- mm/memblock.c | 80 ++++++++++++++++++++++++++++++++++++++++++++++++++++ 6 files changed, 85 insertions(+), 152 deletions(-) (limited to 'arch/arm') diff --git a/arch/Kconfig b/arch/Kconfig index 54a240b61f56..8d5efff59cd8 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -1044,6 +1044,9 @@ config ARCH_WANT_LD_ORPHAN_WARN by the linker, since the locations of such sections can change between linker versions. +config HAVE_ARCH_PFN_VALID + bool + source "kernel/gcov/Kconfig" source "scripts/gcc-plugins/Kconfig" diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 353c3979a2d5..03602e8fe16d 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -69,6 +69,7 @@ config ARM select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU select HAVE_ARCH_MMAP_RND_BITS if MMU + select HAVE_ARCH_PFN_VALID select HAVE_ARCH_SECCOMP select HAVE_ARCH_SECCOMP_FILTER if AEABI && !OABI_COMPAT select HAVE_ARCH_THREAD_STRUCT_WHITELIST @@ -1489,9 +1490,6 @@ config ARCH_SPARSEMEM_ENABLE bool select SPARSEMEM_STATIC if SPARSEMEM -config HAVE_ARCH_PFN_VALID - def_bool y - config HIGHMEM bool "High Memory Support" depends on MMU diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c index c23dbf8bebee..db623d7c30de 100644 --- a/arch/arm/mm/init.c +++ b/arch/arm/mm/init.c @@ -267,83 +267,6 @@ static inline void poison_init_mem(void *s, size_t count) *p++ = 0xe7fddef0; } -static inline void __init -free_memmap(unsigned long start_pfn, unsigned long end_pfn) -{ - struct page *start_pg, *end_pg; - phys_addr_t pg, pgend; - - /* - * Convert start_pfn/end_pfn to a struct page pointer. - */ - start_pg = pfn_to_page(start_pfn - 1) + 1; - end_pg = pfn_to_page(end_pfn - 1) + 1; - - /* - * Convert to physical addresses, and - * round start upwards and end downwards. - */ - pg = PAGE_ALIGN(__pa(start_pg)); - pgend = __pa(end_pg) & PAGE_MASK; - - /* - * If there are free pages between these, - * free the section of the memmap array. - */ - if (pg < pgend) - memblock_free_early(pg, pgend - pg); -} - -/* - * The mem_map array can get very big. Free the unused area of the memory map. - */ -static void __init free_unused_memmap(void) -{ - unsigned long start, end, prev_end = 0; - int i; - - /* - * This relies on each bank being in address order. - * The banks are sorted previously in bootmem_init(). - */ - for_each_mem_pfn_range(i, MAX_NUMNODES, &start, &end, NULL) { -#ifdef CONFIG_SPARSEMEM - /* - * Take care not to free memmap entries that don't exist - * due to SPARSEMEM sections which aren't present. - */ - start = min(start, - ALIGN(prev_end, PAGES_PER_SECTION)); -#else - /* - * Align down here since the VM subsystem insists that the - * memmap entries are valid from the bank start aligned to - * MAX_ORDER_NR_PAGES. - */ - start = round_down(start, MAX_ORDER_NR_PAGES); -#endif - /* - * If we had a previous bank, and there is a space - * between the current bank and the previous, free it. - */ - if (prev_end && prev_end < start) - free_memmap(prev_end, start); - - /* - * Align up here since the VM subsystem insists that the - * memmap entries are valid from the bank end aligned to - * MAX_ORDER_NR_PAGES. - */ - prev_end = ALIGN(end, MAX_ORDER_NR_PAGES); - } - -#ifdef CONFIG_SPARSEMEM - if (!IS_ALIGNED(prev_end, PAGES_PER_SECTION)) - free_memmap(prev_end, - ALIGN(prev_end, PAGES_PER_SECTION)); -#endif -} - static void __init free_highpages(void) { #ifdef CONFIG_HIGHMEM @@ -385,7 +308,6 @@ void __init mem_init(void) set_max_mapnr(pfn_to_page(max_pfn) - mem_map); /* this will put all unused low memory onto the freelists */ - free_unused_memmap(); memblock_free_all(); #ifdef CONFIG_SA1111 diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 15bb857e42e1..6f0751631ef1 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -140,6 +140,7 @@ config ARM64 select HAVE_ARCH_KGDB select HAVE_ARCH_MMAP_RND_BITS select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT + select HAVE_ARCH_PFN_VALID select HAVE_ARCH_PREL32_RELOCATIONS select HAVE_ARCH_SECCOMP_FILTER select HAVE_ARCH_STACKLEAK @@ -1043,9 +1044,6 @@ config ARCH_SELECT_MEMORY_MODEL config ARCH_FLATMEM_ENABLE def_bool !NUMA -config HAVE_ARCH_PFN_VALID - def_bool y - config HW_PERF_EVENTS def_bool y depends on ARM_PMU diff --git a/arch/arm64/mm/init.c b/arch/arm64/mm/init.c index 095540667f0f..3d8328277bec 100644 --- a/arch/arm64/mm/init.c +++ b/arch/arm64/mm/init.c @@ -430,71 +430,6 @@ void __init bootmem_init(void) memblock_dump_all(); } -#ifndef CONFIG_SPARSEMEM_VMEMMAP -static inline void free_memmap(unsigned long start_pfn, unsigned long end_pfn) -{ - struct page *start_pg, *end_pg; - unsigned long pg, pgend; - - /* - * Convert start_pfn/end_pfn to a struct page pointer. - */ - start_pg = pfn_to_page(start_pfn - 1) + 1; - end_pg = pfn_to_page(end_pfn - 1) + 1; - - /* - * Convert to physical addresses, and round start upwards and end - * downwards. - */ - pg = (unsigned long)PAGE_ALIGN(__pa(start_pg)); - pgend = (unsigned long)__pa(end_pg) & PAGE_MASK; - - /* - * If there are free pages between these, free the section of the - * memmap array. - */ - if (pg < pgend) - memblock_free(pg, pgend - pg); -} - -/* - * The mem_map array can get very big. Free the unused area of the memory map. - */ -static void __init free_unused_memmap(void) -{ - unsigned long start, end, prev_end = 0; - int i; - - for_each_mem_pfn_range(i, MAX_NUMNODES, &start, &end, NULL) { -#ifdef CONFIG_SPARSEMEM - /* - * Take care not to free memmap entries that don't exist due - * to SPARSEMEM sections which aren't present. - */ - start = min(start, ALIGN(prev_end, PAGES_PER_SECTION)); -#endif - /* - * If we had a previous bank, and there is a space between the - * current bank and the previous, free it. - */ - if (prev_end && prev_end < start) - free_memmap(prev_end, start); - - /* - * Align up here since the VM subsystem insists that the - * memmap entries are valid from the bank end aligned to - * MAX_ORDER_NR_PAGES. - */ - prev_end = ALIGN(end, MAX_ORDER_NR_PAGES); - } - -#ifdef CONFIG_SPARSEMEM - if (!IS_ALIGNED(prev_end, PAGES_PER_SECTION)) - free_memmap(prev_end, ALIGN(prev_end, PAGES_PER_SECTION)); -#endif -} -#endif /* !CONFIG_SPARSEMEM_VMEMMAP */ - /* * mem_init() marks the free areas in the mem_map and tells us how much memory * is free. This is done after various parts of the system have claimed their @@ -510,9 +445,6 @@ void __init mem_init(void) set_max_mapnr(max_pfn - PHYS_PFN_OFFSET); -#ifndef CONFIG_SPARSEMEM_VMEMMAP - free_unused_memmap(); -#endif /* this will put all unused low memory onto the freelists */ memblock_free_all(); diff --git a/mm/memblock.c b/mm/memblock.c index b68ee86788af..049df4163a97 100644 --- a/mm/memblock.c +++ b/mm/memblock.c @@ -1926,6 +1926,85 @@ static int __init early_memblock(char *p) } early_param("memblock", early_memblock); +static void __init free_memmap(unsigned long start_pfn, unsigned long end_pfn) +{ + struct page *start_pg, *end_pg; + phys_addr_t pg, pgend; + + /* + * Convert start_pfn/end_pfn to a struct page pointer. + */ + start_pg = pfn_to_page(start_pfn - 1) + 1; + end_pg = pfn_to_page(end_pfn - 1) + 1; + + /* + * Convert to physical addresses, and round start upwards and end + * downwards. + */ + pg = PAGE_ALIGN(__pa(start_pg)); + pgend = __pa(end_pg) & PAGE_MASK; + + /* + * If there are free pages between these, free the section of the + * memmap array. + */ + if (pg < pgend) + memblock_free(pg, pgend - pg); +} + +/* + * The mem_map array can get very big. Free the unused area of the memory map. + */ +static void __init free_unused_memmap(void) +{ + unsigned long start, end, prev_end = 0; + int i; + + if (!IS_ENABLED(CONFIG_HAVE_ARCH_PFN_VALID) || + IS_ENABLED(CONFIG_SPARSEMEM_VMEMMAP)) + return; + + /* + * This relies on each bank being in address order. + * The banks are sorted previously in bootmem_init(). + */ + for_each_mem_pfn_range(i, MAX_NUMNODES, &start, &end, NULL) { +#ifdef CONFIG_SPARSEMEM + /* + * Take care not to free memmap entries that don't exist + * due to SPARSEMEM sections which aren't present. + */ + start = min(start, ALIGN(prev_end, PAGES_PER_SECTION)); +#else + /* + * Align down here since the VM subsystem insists that the + * memmap entries are valid from the bank start aligned to + * MAX_ORDER_NR_PAGES. + */ + start = round_down(start, MAX_ORDER_NR_PAGES); +#endif + + /* + * If we had a previous bank, and there is a space + * between the current bank and the previous, free it. + */ + if (prev_end && prev_end < start) + free_memmap(prev_end, start); + + /* + * Align up here since the VM subsystem insists that the + * memmap entries are valid from the bank end aligned to + * MAX_ORDER_NR_PAGES. + */ + prev_end = ALIGN(end, MAX_ORDER_NR_PAGES); + } + +#ifdef CONFIG_SPARSEMEM + if (!IS_ALIGNED(prev_end, PAGES_PER_SECTION)) + free_memmap(prev_end, ALIGN(prev_end, PAGES_PER_SECTION)); +#endif +} + static void __init __free_pages_memory(unsigned long start, unsigned long end) { int order; @@ -2012,6 +2091,7 @@ unsigned long __init memblock_free_all(void) { unsigned long pages; + free_unused_memmap(); reset_all_zones_managed_pages(); pages = free_low_memory_core_early(); -- cgit v1.2.3-59-g8ed1b From b0a0c2615f6f199a656ed8549d7dce625d77aa77 Mon Sep 17 00:00:00 2001 From: Willem de Bruijn Date: Fri, 18 Dec 2020 14:05:41 -0800 Subject: epoll: wire up syscall epoll_pwait2 Split off from prev patch in the series that implements the syscall. Link: https://lkml.kernel.org/r/20201121144401.3727659-4-willemdebruijn.kernel@gmail.com Signed-off-by: Willem de Bruijn Cc: Al Viro Cc: Arnd Bergmann Cc: Matthew Wilcox (Oracle) Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- arch/alpha/kernel/syscalls/syscall.tbl | 1 + arch/arm/tools/syscall.tbl | 1 + arch/arm64/include/asm/unistd.h | 2 +- arch/arm64/include/asm/unistd32.h | 2 ++ arch/ia64/kernel/syscalls/syscall.tbl | 1 + arch/m68k/kernel/syscalls/syscall.tbl | 1 + arch/microblaze/kernel/syscalls/syscall.tbl | 1 + arch/mips/kernel/syscalls/syscall_n32.tbl | 1 + arch/mips/kernel/syscalls/syscall_n64.tbl | 1 + arch/mips/kernel/syscalls/syscall_o32.tbl | 1 + arch/parisc/kernel/syscalls/syscall.tbl | 1 + arch/powerpc/kernel/syscalls/syscall.tbl | 1 + arch/s390/kernel/syscalls/syscall.tbl | 1 + arch/sh/kernel/syscalls/syscall.tbl | 1 + arch/sparc/kernel/syscalls/syscall.tbl | 1 + arch/x86/entry/syscalls/syscall_32.tbl | 1 + arch/x86/entry/syscalls/syscall_64.tbl | 1 + arch/xtensa/kernel/syscalls/syscall.tbl | 1 + include/linux/compat.h | 6 ++++++ include/linux/syscalls.h | 5 +++++ include/uapi/asm-generic/unistd.h | 4 +++- kernel/sys_ni.c | 2 ++ 22 files changed, 35 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/alpha/kernel/syscalls/syscall.tbl b/arch/alpha/kernel/syscalls/syscall.tbl index ee7b01bb7346..a6617067dbe6 100644 --- a/arch/alpha/kernel/syscalls/syscall.tbl +++ b/arch/alpha/kernel/syscalls/syscall.tbl @@ -480,3 +480,4 @@ 548 common pidfd_getfd sys_pidfd_getfd 549 common faccessat2 sys_faccessat2 550 common process_madvise sys_process_madvise +551 common epoll_pwait2 sys_epoll_pwait2 diff --git a/arch/arm/tools/syscall.tbl b/arch/arm/tools/syscall.tbl index d056a548358e..20e1170e2e0a 100644 --- a/arch/arm/tools/syscall.tbl +++ b/arch/arm/tools/syscall.tbl @@ -454,3 +454,4 @@ 438 common pidfd_getfd sys_pidfd_getfd 439 common faccessat2 sys_faccessat2 440 common process_madvise sys_process_madvise +441 common epoll_pwait2 sys_epoll_pwait2 diff --git a/arch/arm64/include/asm/unistd.h b/arch/arm64/include/asm/unistd.h index b3b2019f8d16..86a9d7b3eabe 100644 --- a/arch/arm64/include/asm/unistd.h +++ b/arch/arm64/include/asm/unistd.h @@ -38,7 +38,7 @@ #define __ARM_NR_compat_set_tls (__ARM_NR_COMPAT_BASE + 5) #define __ARM_NR_COMPAT_END (__ARM_NR_COMPAT_BASE + 0x800) -#define __NR_compat_syscalls 441 +#define __NR_compat_syscalls 442 #endif #define __ARCH_WANT_SYS_CLONE diff --git a/arch/arm64/include/asm/unistd32.h b/arch/arm64/include/asm/unistd32.h index 107f08e03b9f..f4bca2b90218 100644 --- a/arch/arm64/include/asm/unistd32.h +++ b/arch/arm64/include/asm/unistd32.h @@ -889,6 +889,8 @@ __SYSCALL(__NR_pidfd_getfd, sys_pidfd_getfd) __SYSCALL(__NR_faccessat2, sys_faccessat2) #define __NR_process_madvise 440 __SYSCALL(__NR_process_madvise, sys_process_madvise) +#define __NR_epoll_pwait2 441 +__SYSCALL(__NR_epoll_pwait2, sys_epoll_pwait2) /* * Please add new compat syscalls above this comment and update diff --git a/arch/ia64/kernel/syscalls/syscall.tbl b/arch/ia64/kernel/syscalls/syscall.tbl index b96ed8b8a508..bfc00f2bd437 100644 --- a/arch/ia64/kernel/syscalls/syscall.tbl +++ b/arch/ia64/kernel/syscalls/syscall.tbl @@ -361,3 +361,4 @@ 438 common pidfd_getfd sys_pidfd_getfd 439 common faccessat2 sys_faccessat2 440 common process_madvise sys_process_madvise +441 common epoll_pwait2 sys_epoll_pwait2 diff --git a/arch/m68k/kernel/syscalls/syscall.tbl b/arch/m68k/kernel/syscalls/syscall.tbl index 625fb6d32842..7fe4e45c864c 100644 --- a/arch/m68k/kernel/syscalls/syscall.tbl +++ b/arch/m68k/kernel/syscalls/syscall.tbl @@ -440,3 +440,4 @@ 438 common pidfd_getfd sys_pidfd_getfd 439 common faccessat2 sys_faccessat2 440 common process_madvise sys_process_madvise +441 common epoll_pwait2 sys_epoll_pwait2 diff --git a/arch/microblaze/kernel/syscalls/syscall.tbl b/arch/microblaze/kernel/syscalls/syscall.tbl index aae729c95cf9..a522adf194ab 100644 --- a/arch/microblaze/kernel/syscalls/syscall.tbl +++ b/arch/microblaze/kernel/syscalls/syscall.tbl @@ -446,3 +446,4 @@ 438 common pidfd_getfd sys_pidfd_getfd 439 common faccessat2 sys_faccessat2 440 common process_madvise sys_process_madvise +441 common epoll_pwait2 sys_epoll_pwait2 diff --git a/arch/mips/kernel/syscalls/syscall_n32.tbl b/arch/mips/kernel/syscalls/syscall_n32.tbl index 32817c954435..ad9c3dd0ab1f 100644 --- a/arch/mips/kernel/syscalls/syscall_n32.tbl +++ b/arch/mips/kernel/syscalls/syscall_n32.tbl @@ -379,3 +379,4 @@ 438 n32 pidfd_getfd sys_pidfd_getfd 439 n32 faccessat2 sys_faccessat2 440 n32 process_madvise sys_process_madvise +441 n32 epoll_pwait2 sys_epoll_pwait2 diff --git a/arch/mips/kernel/syscalls/syscall_n64.tbl b/arch/mips/kernel/syscalls/syscall_n64.tbl index 9e4ea3c31b1c..91649690b52f 100644 --- a/arch/mips/kernel/syscalls/syscall_n64.tbl +++ b/arch/mips/kernel/syscalls/syscall_n64.tbl @@ -355,3 +355,4 @@ 438 n64 pidfd_getfd sys_pidfd_getfd 439 n64 faccessat2 sys_faccessat2 440 n64 process_madvise sys_process_madvise +441 n64 epoll_pwait2 sys_epoll_pwait2 diff --git a/arch/mips/kernel/syscalls/syscall_o32.tbl b/arch/mips/kernel/syscalls/syscall_o32.tbl index 29f5f28cf5ce..4bad0c40aed6 100644 --- a/arch/mips/kernel/syscalls/syscall_o32.tbl +++ b/arch/mips/kernel/syscalls/syscall_o32.tbl @@ -428,3 +428,4 @@ 438 o32 pidfd_getfd sys_pidfd_getfd 439 o32 faccessat2 sys_faccessat2 440 o32 process_madvise sys_process_madvise +441 o32 epoll_pwait2 sys_epoll_pwait2 compat_sys_epoll_pwait2 diff --git a/arch/parisc/kernel/syscalls/syscall.tbl b/arch/parisc/kernel/syscalls/syscall.tbl index f375ea528e59..6bcc31966b44 100644 --- a/arch/parisc/kernel/syscalls/syscall.tbl +++ b/arch/parisc/kernel/syscalls/syscall.tbl @@ -438,3 +438,4 @@ 438 common pidfd_getfd sys_pidfd_getfd 439 common faccessat2 sys_faccessat2 440 common process_madvise sys_process_madvise +441 common epoll_pwait2 sys_epoll_pwait2 compat_sys_epoll_pwait2 diff --git a/arch/powerpc/kernel/syscalls/syscall.tbl b/arch/powerpc/kernel/syscalls/syscall.tbl index 1275daec7fec..f744eb5cba88 100644 --- a/arch/powerpc/kernel/syscalls/syscall.tbl +++ b/arch/powerpc/kernel/syscalls/syscall.tbl @@ -530,3 +530,4 @@ 438 common pidfd_getfd sys_pidfd_getfd 439 common faccessat2 sys_faccessat2 440 common process_madvise sys_process_madvise +441 common epoll_pwait2 sys_epoll_pwait2 compat_sys_epoll_pwait2 diff --git a/arch/s390/kernel/syscalls/syscall.tbl b/arch/s390/kernel/syscalls/syscall.tbl index 28c168000483..14f6525886a8 100644 --- a/arch/s390/kernel/syscalls/syscall.tbl +++ b/arch/s390/kernel/syscalls/syscall.tbl @@ -443,3 +443,4 @@ 438 common pidfd_getfd sys_pidfd_getfd sys_pidfd_getfd 439 common faccessat2 sys_faccessat2 sys_faccessat2 440 common process_madvise sys_process_madvise sys_process_madvise +441 common epoll_pwait2 sys_epoll_pwait2 sys_epoll_pwait2 diff --git a/arch/sh/kernel/syscalls/syscall.tbl b/arch/sh/kernel/syscalls/syscall.tbl index 783738448ff5..9df40ac0ebc0 100644 --- a/arch/sh/kernel/syscalls/syscall.tbl +++ b/arch/sh/kernel/syscalls/syscall.tbl @@ -443,3 +443,4 @@ 438 common pidfd_getfd sys_pidfd_getfd 439 common faccessat2 sys_faccessat2 440 common process_madvise sys_process_madvise +441 common epoll_pwait2 sys_epoll_pwait2 diff --git a/arch/sparc/kernel/syscalls/syscall.tbl b/arch/sparc/kernel/syscalls/syscall.tbl index 78160260991b..c7da4c3271e6 100644 --- a/arch/sparc/kernel/syscalls/syscall.tbl +++ b/arch/sparc/kernel/syscalls/syscall.tbl @@ -486,3 +486,4 @@ 438 common pidfd_getfd sys_pidfd_getfd 439 common faccessat2 sys_faccessat2 440 common process_madvise sys_process_madvise +441 common epoll_pwait2 sys_epoll_pwait2 diff --git a/arch/x86/entry/syscalls/syscall_32.tbl b/arch/x86/entry/syscalls/syscall_32.tbl index 0d0667a9fbd7..874aeacde2dd 100644 --- a/arch/x86/entry/syscalls/syscall_32.tbl +++ b/arch/x86/entry/syscalls/syscall_32.tbl @@ -445,3 +445,4 @@ 438 i386 pidfd_getfd sys_pidfd_getfd 439 i386 faccessat2 sys_faccessat2 440 i386 process_madvise sys_process_madvise +441 i386 epoll_pwait2 sys_epoll_pwait2 compat_sys_epoll_pwait2 diff --git a/arch/x86/entry/syscalls/syscall_64.tbl b/arch/x86/entry/syscalls/syscall_64.tbl index 379819244b91..78672124d28b 100644 --- a/arch/x86/entry/syscalls/syscall_64.tbl +++ b/arch/x86/entry/syscalls/syscall_64.tbl @@ -362,6 +362,7 @@ 438 common pidfd_getfd sys_pidfd_getfd 439 common faccessat2 sys_faccessat2 440 common process_madvise sys_process_madvise +441 common epoll_pwait2 sys_epoll_pwait2 # # Due to a historical design error, certain syscalls are numbered differently diff --git a/arch/xtensa/kernel/syscalls/syscall.tbl b/arch/xtensa/kernel/syscalls/syscall.tbl index b070f272995d..46116a28eeed 100644 --- a/arch/xtensa/kernel/syscalls/syscall.tbl +++ b/arch/xtensa/kernel/syscalls/syscall.tbl @@ -411,3 +411,4 @@ 438 common pidfd_getfd sys_pidfd_getfd 439 common faccessat2 sys_faccessat2 440 common process_madvise sys_process_madvise +441 common epoll_pwait2 sys_epoll_pwait2 diff --git a/include/linux/compat.h b/include/linux/compat.h index 400c0941c8af..6e65be753603 100644 --- a/include/linux/compat.h +++ b/include/linux/compat.h @@ -537,6 +537,12 @@ asmlinkage long compat_sys_epoll_pwait(int epfd, int maxevents, int timeout, const compat_sigset_t __user *sigmask, compat_size_t sigsetsize); +asmlinkage long compat_sys_epoll_pwait2(int epfd, + struct epoll_event __user *events, + int maxevents, + const struct __kernel_timespec __user *timeout, + const compat_sigset_t __user *sigmask, + compat_size_t sigsetsize); /* fs/fcntl.c */ asmlinkage long compat_sys_fcntl(unsigned int fd, unsigned int cmd, diff --git a/include/linux/syscalls.h b/include/linux/syscalls.h index df0c3c74609e..f3929aff39cf 100644 --- a/include/linux/syscalls.h +++ b/include/linux/syscalls.h @@ -362,6 +362,11 @@ asmlinkage long sys_epoll_pwait(int epfd, struct epoll_event __user *events, int maxevents, int timeout, const sigset_t __user *sigmask, size_t sigsetsize); +asmlinkage long sys_epoll_pwait2(int epfd, struct epoll_event __user *events, + int maxevents, + const struct __kernel_timespec __user *timeout, + const sigset_t __user *sigmask, + size_t sigsetsize); /* fs/fcntl.c */ asmlinkage long sys_dup(unsigned int fildes); diff --git a/include/uapi/asm-generic/unistd.h b/include/uapi/asm-generic/unistd.h index fc48c64700eb..728752917785 100644 --- a/include/uapi/asm-generic/unistd.h +++ b/include/uapi/asm-generic/unistd.h @@ -859,9 +859,11 @@ __SYSCALL(__NR_pidfd_getfd, sys_pidfd_getfd) __SYSCALL(__NR_faccessat2, sys_faccessat2) #define __NR_process_madvise 440 __SYSCALL(__NR_process_madvise, sys_process_madvise) +#define __NR_epoll_pwait2 441 +__SC_COMP(__NR_epoll_pwait2, sys_epoll_pwait2, compat_sys_epoll_pwait2) #undef __NR_syscalls -#define __NR_syscalls 441 +#define __NR_syscalls 442 /* * 32 bit systems traditionally used different diff --git a/kernel/sys_ni.c b/kernel/sys_ni.c index f27ac94d5fa7..19aa806890d5 100644 --- a/kernel/sys_ni.c +++ b/kernel/sys_ni.c @@ -68,6 +68,8 @@ COND_SYSCALL(epoll_create1); COND_SYSCALL(epoll_ctl); COND_SYSCALL(epoll_pwait); COND_SYSCALL_COMPAT(epoll_pwait); +COND_SYSCALL(epoll_pwait2); +COND_SYSCALL_COMPAT(epoll_pwait2); /* fs/fcntl.c */ -- cgit v1.2.3-59-g8ed1b From 3cce9d44321e460e7c88cdec4e4537a6e9ad7c0d Mon Sep 17 00:00:00 2001 From: Ard Biesheuvel Date: Sat, 19 Dec 2020 16:29:58 +0100 Subject: ARM: 9044/1: vfp: use undef hook for VFP support detection Commit f77ac2e378be9dd6 ("ARM: 9030/1: entry: omit FP emulation for UND exceptions taken in kernel mode") failed to take into account that there is in fact a case where we relied on this code path: during boot, the VFP detection code issues a read of FPSID, which will trigger an undef exception on cores that lack VFP support. So let's reinstate this logic using an undef hook which is registered only for the duration of the initcall to vpf_init(), and which sets VFP_arch to a non-zero value - as before - if no VFP support is present. Fixes: f77ac2e378be9dd6 ("ARM: 9030/1: entry: omit FP emulation for UND ...") Reported-by: "kernelci.org bot" Signed-off-by: Ard Biesheuvel Signed-off-by: Russell King --- arch/arm/vfp/entry.S | 17 ----------------- arch/arm/vfp/vfpmodule.c | 25 ++++++++++++++++++++----- 2 files changed, 20 insertions(+), 22 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/vfp/entry.S b/arch/arm/vfp/entry.S index 0186cf9da890..27b0a1f27fbd 100644 --- a/arch/arm/vfp/entry.S +++ b/arch/arm/vfp/entry.S @@ -37,20 +37,3 @@ ENDPROC(vfp_null_entry) .align 2 .LCvfp: .word vfp_vector - -@ This code is called if the VFP does not exist. It needs to flag the -@ failure to the VFP initialisation code. - - __INIT -ENTRY(vfp_testing_entry) - dec_preempt_count_ti r10, r4 - ldr r0, VFP_arch_address - str r0, [r0] @ set to non-zero value - ret r9 @ we have handled the fault -ENDPROC(vfp_testing_entry) - - .align 2 -VFP_arch_address: - .word VFP_arch - - __FINIT diff --git a/arch/arm/vfp/vfpmodule.c b/arch/arm/vfp/vfpmodule.c index c3b6451c18bd..2cb355c1b5b7 100644 --- a/arch/arm/vfp/vfpmodule.c +++ b/arch/arm/vfp/vfpmodule.c @@ -32,7 +32,6 @@ /* * Our undef handlers (in entry.S) */ -asmlinkage void vfp_testing_entry(void); asmlinkage void vfp_support_entry(void); asmlinkage void vfp_null_entry(void); @@ -43,7 +42,7 @@ asmlinkage void (*vfp_vector)(void) = vfp_null_entry; * Used in startup: set to non-zero if VFP checks fail * After startup, holds VFP architecture */ -unsigned int VFP_arch; +static unsigned int __initdata VFP_arch; /* * The pointer to the vfpstate structure of the thread which currently @@ -437,7 +436,7 @@ static void vfp_enable(void *unused) * present on all CPUs within a SMP complex. Needs to be called prior to * vfp_init(). */ -void vfp_disable(void) +void __init vfp_disable(void) { if (VFP_arch) { pr_debug("%s: should be called prior to vfp_init\n", __func__); @@ -707,7 +706,7 @@ static int __init vfp_kmode_exception_hook_init(void) register_undef_hook(&vfp_kmode_exception_hook[i]); return 0; } -core_initcall(vfp_kmode_exception_hook_init); +subsys_initcall(vfp_kmode_exception_hook_init); /* * Kernel-side NEON support functions @@ -753,6 +752,21 @@ EXPORT_SYMBOL(kernel_neon_end); #endif /* CONFIG_KERNEL_MODE_NEON */ +static int __init vfp_detect(struct pt_regs *regs, unsigned int instr) +{ + VFP_arch = UINT_MAX; /* mark as not present */ + regs->ARM_pc += 4; + return 0; +} + +static struct undef_hook vfp_detect_hook __initdata = { + .instr_mask = 0x0c000e00, + .instr_val = 0x0c000a00, + .cpsr_mask = MODE_MASK, + .cpsr_val = SVC_MODE, + .fn = vfp_detect, +}; + /* * VFP support code initialisation. */ @@ -773,10 +787,11 @@ static int __init vfp_init(void) * The handler is already setup to just log calls, so * we just need to read the VFPSID register. */ - vfp_vector = vfp_testing_entry; + register_undef_hook(&vfp_detect_hook); barrier(); vfpsid = fmrx(FPSID); barrier(); + unregister_undef_hook(&vfp_detect_hook); vfp_vector = vfp_null_entry; pr_info("VFP support v0.3: "); -- cgit v1.2.3-59-g8ed1b From 6c7a6d22fcef9181239ea7248c6b0c4117b9325e Mon Sep 17 00:00:00 2001 From: Ard Biesheuvel Date: Fri, 27 Nov 2020 13:07:22 +0100 Subject: ARM: 9031/1: hyp-stub: remove unused .L__boot_cpu_mode_offset symbol Commit aaac3733171fca94 ("ARM: kvm: replace open coded VA->PA calculations with adr_l call") removed all uses of .L__boot_cpu_mode_offset, so there is no longer a need to define it. Signed-off-by: Ard Biesheuvel Reviewed-by: Linus Walleij Signed-off-by: Russell King --- arch/arm/kernel/hyp-stub.S | 6 ------ 1 file changed, 6 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/kernel/hyp-stub.S b/arch/arm/kernel/hyp-stub.S index 26d8e03b1dd3..327f63ec42c6 100644 --- a/arch/arm/kernel/hyp-stub.S +++ b/arch/arm/kernel/hyp-stub.S @@ -228,12 +228,6 @@ ENTRY(__hyp_soft_restart) ret lr ENDPROC(__hyp_soft_restart) -#ifndef ZIMAGE -.align 2 -.L__boot_cpu_mode_offset: - .long __boot_cpu_mode - . -#endif - .align 5 ENTRY(__hyp_stub_vectors) __hyp_stub_reset: W(b) . -- cgit v1.2.3-59-g8ed1b From 76460d613d9b4096f3567bd444e3fc275db1b96b Mon Sep 17 00:00:00 2001 From: Anshuman Khandual Date: Mon, 30 Nov 2020 10:28:20 +0100 Subject: ARM: 9032/1: arm/mm: Convert PUD level pgtable helper macros into functions Macros used as functions can be problematic from the compiler perspective. There was a build failure report caused primarily because of non reference of an argument variable. Hence convert PUD level pgtable helper macros into functions in order to avoid such problems in the future. In the process, it fixes the argument variables sequence in set_pud() which probably remained hidden for being a macro. https://lore.kernel.org/linux-mm/202011020749.5XQ3Hfzc-lkp@intel.com/ https://lore.kernel.org/linux-mm/5fa49698.Vu2O3r+dU20UoEJ+%25lkp@intel.com/ Cc: Andrew Morton Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Reviewed-by: Linus Walleij Signed-off-by: Anshuman Khandual Signed-off-by: Russell King --- arch/arm/include/asm/pgtable-2level.h | 27 ++++++++++++++++++++++----- 1 file changed, 22 insertions(+), 5 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/include/asm/pgtable-2level.h b/arch/arm/include/asm/pgtable-2level.h index 3502c2f746ca..9d4f5eef410b 100644 --- a/arch/arm/include/asm/pgtable-2level.h +++ b/arch/arm/include/asm/pgtable-2level.h @@ -177,11 +177,28 @@ * the pud: the pud entry is never bad, always exists, and can't be set or * cleared. */ -#define pud_none(pud) (0) -#define pud_bad(pud) (0) -#define pud_present(pud) (1) -#define pud_clear(pudp) do { } while (0) -#define set_pud(pud,pudp) do { } while (0) +static inline int pud_none(pud_t pud) +{ + return 0; +} + +static inline int pud_bad(pud_t pud) +{ + return 0; +} + +static inline int pud_present(pud_t pud) +{ + return 1; +} + +static inline void pud_clear(pud_t *pudp) +{ +} + +static inline void set_pud(pud_t *pudp, pud_t pud) +{ +} static inline pmd_t *pmd_offset(pud_t *pud, unsigned long addr) { -- cgit v1.2.3-59-g8ed1b From 27bde183b0d3b0e8e84c80db1864a5c7bd20b5e7 Mon Sep 17 00:00:00 2001 From: Anshuman Khandual Date: Mon, 30 Nov 2020 11:24:09 +0100 Subject: ARM: 9033/1: arm/smp: Drop the macro S(x,s) Mapping between IPI type index and its string is direct without requiring an additional offset. Hence the existing macro S(x, s) is now redundant and can just be dropped. This also makes the code clean and simple. Cc: Marc Zyngier Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual Signed-off-by: Russell King --- arch/arm/kernel/smp.c | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c index 48099c6e1e4a..6ab2b0ad5f40 100644 --- a/arch/arm/kernel/smp.c +++ b/arch/arm/kernel/smp.c @@ -524,14 +524,13 @@ void __init smp_prepare_cpus(unsigned int max_cpus) } static const char *ipi_types[NR_IPI] __tracepoint_string = { -#define S(x,s) [x] = s - S(IPI_WAKEUP, "CPU wakeup interrupts"), - S(IPI_TIMER, "Timer broadcast interrupts"), - S(IPI_RESCHEDULE, "Rescheduling interrupts"), - S(IPI_CALL_FUNC, "Function call interrupts"), - S(IPI_CPU_STOP, "CPU stop interrupts"), - S(IPI_IRQ_WORK, "IRQ work interrupts"), - S(IPI_COMPLETION, "completion interrupts"), + [IPI_WAKEUP] = "CPU wakeup interrupts", + [IPI_TIMER] = "Timer broadcast interrupts", + [IPI_RESCHEDULE] = "Rescheduling interrupts", + [IPI_CALL_FUNC] = "Function call interrupts", + [IPI_CPU_STOP] = "CPU stop interrupts", + [IPI_IRQ_WORK] = "IRQ work interrupts", + [IPI_COMPLETION] = "completion interrupts", }; static void smp_cross_call(const struct cpumask *target, unsigned int ipinr); -- cgit v1.2.3-59-g8ed1b From 0557ac83fd1a0a7cd6909665bad50006507115a0 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 4 Dec 2020 10:37:47 +0100 Subject: ARM: 9035/1: uncompress: Add be32tocpu macro DTB stores all values as 32-bit big-endian integers. Add a macro to convert such values to native CPU endianness, to reduce duplication. Signed-off-by: Geert Uytterhoeven Reviewed-by: Ard Biesheuvel Reviewed-by: Nicolas Pitre Signed-off-by: Russell King --- arch/arm/boot/compressed/head.S | 26 ++++++++++++-------------- 1 file changed, 12 insertions(+), 14 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S index 2e04ec5b5446..14d1995106c2 100644 --- a/arch/arm/boot/compressed/head.S +++ b/arch/arm/boot/compressed/head.S @@ -165,6 +165,16 @@ orr \res, \res, \tmp1, lsl #24 .endm + .macro be32tocpu, val, tmp +#ifndef __ARMEB__ + /* convert to little endian */ + eor \tmp, \val, \val, ror #16 + bic \tmp, \tmp, #0x00ff0000 + mov \val, \val, ror #8 + eor \val, \val, \tmp, lsr #8 +#endif + .endm + .section ".start", "ax" /* * sort out different calling conventions @@ -345,13 +355,7 @@ restart: adr r0, LC1 /* Get the initial DTB size */ ldr r5, [r6, #4] -#ifndef __ARMEB__ - /* convert to little endian */ - eor r1, r5, r5, ror #16 - bic r1, r1, #0x00ff0000 - mov r5, r5, ror #8 - eor r5, r5, r1, lsr #8 -#endif + be32tocpu r5, r1 dbgadtb r6, r5 /* 50% DTB growth should be good enough */ add r5, r5, r5, lsr #1 @@ -403,13 +407,7 @@ restart: adr r0, LC1 /* Get the current DTB size */ ldr r5, [r6, #4] -#ifndef __ARMEB__ - /* convert r5 (dtb size) to little endian */ - eor r1, r5, r5, ror #16 - bic r1, r1, #0x00ff0000 - mov r5, r5, ror #8 - eor r5, r5, r1, lsr #8 -#endif + be32tocpu r5, r1 /* preserve 64-bit alignment */ add r5, r5, #7 -- cgit v1.2.3-59-g8ed1b From 1ecec38547d415054fdb63a231234f44396b6d06 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 4 Dec 2020 10:37:14 +0100 Subject: ARM: 9036/1: uncompress: Fix dbgadtb size parameter name The dbgadtb macro is passed the size of the appended DTB, not the end address. Fixes: c03e41470e901123 ("ARM: 9010/1: uncompress: Print the location of appended DTB") Signed-off-by: Geert Uytterhoeven Reviewed-by: Linus Walleij Signed-off-by: Russell King --- arch/arm/boot/compressed/head.S | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S index 14d1995106c2..4fb699769e6a 100644 --- a/arch/arm/boot/compressed/head.S +++ b/arch/arm/boot/compressed/head.S @@ -116,7 +116,7 @@ /* * Debug print of the final appended DTB location */ - .macro dbgadtb, begin, end + .macro dbgadtb, begin, size #ifdef DEBUG kputc #'D' kputc #'T' @@ -129,7 +129,7 @@ kputc #'(' kputc #'0' kputc #'x' - kphex \end, 8 /* End of appended DTB */ + kphex \size, 8 /* Size of appended DTB */ kputc #')' kputc #'\n' #endif -- cgit v1.2.3-59-g8ed1b From 551b39efc6ffdc7a881122fbac0caa2a27a464d8 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 4 Dec 2020 10:39:10 +0100 Subject: ARM: 9037/1: uncompress: Add OF_DT_MAGIC macro The DTB magic marker is stored as a 32-bit big-endian value, and thus depends on the CPU's endianness. Add a macro to define this value in native endianness, to reduce #ifdef clutter and (future) duplication. Signed-off-by: Geert Uytterhoeven Reviewed-by: Ard Biesheuvel Reviewed-by: Nicolas Pitre Signed-off-by: Russell King --- arch/arm/boot/compressed/head.S | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S index 4fb699769e6a..8d546cb10921 100644 --- a/arch/arm/boot/compressed/head.S +++ b/arch/arm/boot/compressed/head.S @@ -11,6 +11,12 @@ #include "efi-header.S" +#ifdef __ARMEB__ +#define OF_DT_MAGIC 0xd00dfeed +#else +#define OF_DT_MAGIC 0xedfe0dd0 +#endif + AR_CLASS( .arch armv7-a ) M_CLASS( .arch armv7-m ) @@ -335,11 +341,7 @@ restart: adr r0, LC1 */ ldr lr, [r6, #0] -#ifndef __ARMEB__ - ldr r1, =0xedfe0dd0 @ sig is 0xd00dfeed big endian -#else - ldr r1, =0xd00dfeed -#endif + ldr r1, =OF_DT_MAGIC cmp lr, r1 bne dtb_check_done @ not found -- cgit v1.2.3-59-g8ed1b From 0cda9bc15dfc459bd178d6ba93389df52dd57957 Mon Sep 17 00:00:00 2001 From: Nathan Chancellor Date: Tue, 8 Dec 2020 01:34:16 +0100 Subject: ARM: 9038/1: Link with '-z norelro' When linking a multi_v7_defconfig + CONFIG_KASAN=y kernel with LD=ld.lld, the following error occurs: $ make ARCH=arm CROSS_COMPILE=arm-linux-gnueabi- LLVM=1 zImage ld.lld: error: section: .exit.data is not contiguous with other relro sections LLD defaults to '-z relro', which is unneeded for the kernel because program headers are not used nor is there any position independent code generation or linking for ARM. Add '-z norelro' to LDFLAGS_vmlinux to avoid this error. Link: https://github.com/ClangBuiltLinux/linux/issues/1189 Reviewed-by: Nick Desaulniers Tested-by: Nick Desaulniers Signed-off-by: Nathan Chancellor Signed-off-by: Russell King --- arch/arm/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 4d76eab2b22d..3c0a64cefe52 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -10,7 +10,7 @@ # # Copyright (C) 1995-2001 by Russell King -LDFLAGS_vmlinux := --no-undefined -X --pic-veneer +LDFLAGS_vmlinux := --no-undefined -X --pic-veneer -z norelro ifeq ($(CONFIG_CPU_ENDIAN_BE8),y) LDFLAGS_vmlinux += --be8 KBUILD_LDFLAGS_MODULE += --be8 -- cgit v1.2.3-59-g8ed1b From 10fce53c0ef8f6e79115c3d9e0d7ea1338c3fa37 Mon Sep 17 00:00:00 2001 From: Ard Biesheuvel Date: Tue, 17 Nov 2020 08:41:01 +0100 Subject: ARM: 9027/1: head.S: explicitly map DT even if it lives in the first physical section The early ATAGS/DT mapping code uses SECTION_SHIFT to mask low order bits of R2, and decides that no ATAGS/DTB were provided if the resulting value is 0x0. This means that on systems where DRAM starts at 0x0 (such as Raspberry Pi), no explicit mapping of the DT will be created if R2 points into the first 1 MB section of memory. This was not a problem before, because the decompressed kernel is loaded at the base of DRAM and mapped using sections as well, and so as long as the DT is referenced via a virtual address that uses the same translation (the linear map, in this case), things work fine. However, commit 7a1be318f579 ("9012/1: move device tree mapping out of linear region") changes this, and now the DT is referenced via a virtual address that is disjoint from the linear mapping of DRAM, and so we need the early code to create the DT mapping unconditionally. So let's create the early DT mapping for any value of R2 != 0x0. Reported-by: "kernelci.org bot" Reviewed-by: Linus Walleij Signed-off-by: Ard Biesheuvel Signed-off-by: Russell King --- arch/arm/kernel/head.S | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S index 9b18d8c66129..26ffd462a975 100644 --- a/arch/arm/kernel/head.S +++ b/arch/arm/kernel/head.S @@ -274,10 +274,10 @@ __create_page_tables: * We map 2 sections in case the ATAGs/DTB crosses a section boundary. */ mov r0, r2, lsr #SECTION_SHIFT - movs r0, r0, lsl #SECTION_SHIFT + cmp r2, #0 ldrne r3, =FDT_FIXED_BASE >> (SECTION_SHIFT - PMD_ORDER) addne r3, r3, r4 - orrne r6, r7, r0 + orrne r6, r7, r0, lsl #SECTION_SHIFT strne r6, [r3], #1 << PMD_ORDER addne r6, r6, #1 << SECTION_SHIFT strne r6, [r3] -- cgit v1.2.3-59-g8ed1b From 06862d789ddde8a99c1e579e934ca17c15a84755 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Sun, 10 Jan 2021 21:09:11 +0200 Subject: ARM: OMAP2+: Fix suspcious RCU usage splats for omap_enter_idle_coupled We get suspcious RCU usage splats with cpuidle in several places in omap_enter_idle_coupled() with the kernel debug options enabled: RCU used illegally from extended quiescent state! ... (_raw_spin_lock_irqsave) (omap_enter_idle_coupled+0x17c/0x2d8) (omap_enter_idle_coupled) (cpuidle_enter_state) (cpuidle_enter_state_coupled) (cpuidle_enter) Let's use RCU_NONIDLE to suppress these splats. Things got changed around with commit 1098582a0f6c ("sched,idle,rcu: Push rcu_idle deeper into the idle path") that started triggering these warnings. For the tick_broadcast related calls, ideally we'd just switch over to using CPUIDLE_FLAG_TIMER_STOP for omap_enter_idle_coupled() to have the generic cpuidle code handle the tick_broadcast related calls for us and then just drop the tick_broadcast calls here. But we're currently missing the call in the common cpuidle code for tick_broadcast_enable() that CPU1 hotplug needs as described in earlier commit 50d6b3cf9403 ("ARM: OMAP2+: fix lack of timer interrupts on CPU1 after hotplug"). Cc: Daniel Lezcano Cc: Paul E. McKenney Cc: Russell King Acked-by: Paul E. McKenney Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/cpuidle44xx.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-omap2/cpuidle44xx.c b/arch/arm/mach-omap2/cpuidle44xx.c index c8d317fafe2e..de37027ad758 100644 --- a/arch/arm/mach-omap2/cpuidle44xx.c +++ b/arch/arm/mach-omap2/cpuidle44xx.c @@ -151,10 +151,10 @@ static int omap_enter_idle_coupled(struct cpuidle_device *dev, (cx->mpu_logic_state == PWRDM_POWER_OFF); /* Enter broadcast mode for periodic timers */ - tick_broadcast_enable(); + RCU_NONIDLE(tick_broadcast_enable()); /* Enter broadcast mode for one-shot timers */ - tick_broadcast_enter(); + RCU_NONIDLE(tick_broadcast_enter()); /* * Call idle CPU PM enter notifier chain so that @@ -166,7 +166,7 @@ static int omap_enter_idle_coupled(struct cpuidle_device *dev, if (dev->cpu == 0) { pwrdm_set_logic_retst(mpu_pd, cx->mpu_logic_state); - omap_set_pwrdm_state(mpu_pd, cx->mpu_state); + RCU_NONIDLE(omap_set_pwrdm_state(mpu_pd, cx->mpu_state)); /* * Call idle CPU cluster PM enter notifier chain @@ -178,7 +178,7 @@ static int omap_enter_idle_coupled(struct cpuidle_device *dev, index = 0; cx = state_ptr + index; pwrdm_set_logic_retst(mpu_pd, cx->mpu_logic_state); - omap_set_pwrdm_state(mpu_pd, cx->mpu_state); + RCU_NONIDLE(omap_set_pwrdm_state(mpu_pd, cx->mpu_state)); mpuss_can_lose_context = 0; } } @@ -194,9 +194,9 @@ static int omap_enter_idle_coupled(struct cpuidle_device *dev, mpuss_can_lose_context) gic_dist_disable(); - clkdm_deny_idle(cpu_clkdm[1]); - omap_set_pwrdm_state(cpu_pd[1], PWRDM_POWER_ON); - clkdm_allow_idle(cpu_clkdm[1]); + RCU_NONIDLE(clkdm_deny_idle(cpu_clkdm[1])); + RCU_NONIDLE(omap_set_pwrdm_state(cpu_pd[1], PWRDM_POWER_ON)); + RCU_NONIDLE(clkdm_allow_idle(cpu_clkdm[1])); if (IS_PM44XX_ERRATUM(PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD) && mpuss_can_lose_context) { @@ -222,7 +222,7 @@ static int omap_enter_idle_coupled(struct cpuidle_device *dev, cpu_pm_exit(); cpu_pm_out: - tick_broadcast_exit(); + RCU_NONIDLE(tick_broadcast_exit()); fail: cpuidle_coupled_parallel_barrier(dev, &abort_barrier); -- cgit v1.2.3-59-g8ed1b