From 68e2fc78e5055740126df8eab0d31005495756c9 Mon Sep 17 00:00:00 2001 From: Michael Hennerich Date: Mon, 14 Jul 2008 16:51:57 +0800 Subject: Blackfin arch: Fix bug - Kernel does not boot if re-program clocks Don't write conflicting data to EBIU_SDBCTL after the SDRAM is configured. This can cause data corruption, since we might change SDRAM row and column addressing modes. Signed-off-by: Michael Hennerich Signed-off-by: Bryan Wu --- arch/blackfin/mach-bf527/head.S | 12 +++--------- 1 file changed, 3 insertions(+), 9 deletions(-) (limited to 'arch/blackfin/mach-bf527/head.S') diff --git a/arch/blackfin/mach-bf527/head.S b/arch/blackfin/mach-bf527/head.S index 57bdb3ba2fed..fe05cc1ef174 100644 --- a/arch/blackfin/mach-bf527/head.S +++ b/arch/blackfin/mach-bf527/head.S @@ -32,7 +32,7 @@ #include #include -#if CONFIG_BFIN_KERNEL_CLOCK +#ifdef CONFIG_BFIN_KERNEL_CLOCK #include #include #endif @@ -185,7 +185,7 @@ ENTRY(__start) /* Put The Code for PLL Programming and SDRAM Programming in L1 ISRAM */ call _bf53x_relocate_l1_mem; -#if CONFIG_BFIN_KERNEL_CLOCK +#ifdef CONFIG_BFIN_KERNEL_CLOCK call _start_dma_code; #endif @@ -318,7 +318,7 @@ ENDPROC(_real_start) __FINIT .section .l1.text -#if CONFIG_BFIN_KERNEL_CLOCK +#ifdef CONFIG_BFIN_KERNEL_CLOCK ENTRY(_start_dma_code) /* Enable PHY CLK buffer output */ @@ -398,12 +398,6 @@ ENTRY(_start_dma_code) w[p0] = r0.l; ssync; - p0.l = LO(EBIU_SDBCTL); - p0.h = HI(EBIU_SDBCTL); /* SDRAM Memory Bank Control Register */ - r0 = mem_SDBCTL; - w[p0] = r0.l; - ssync; - P2.H = hi(EBIU_SDGCTL); P2.L = lo(EBIU_SDGCTL); R0 = [P2]; -- cgit v1.2.3-59-g8ed1b