From 4ba66a9760722ccbb691b8f7116cad2f791cca7b Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Wed, 7 Mar 2018 22:23:24 +0100 Subject: arch: remove blackfin port The Analog Devices Blackfin port was added in 2007 and was rather active for a while, but all work on it has come to a standstill over time, as Analog have changed their product line-up. Aaron Wu confirmed that the architecture port is no longer relevant, and multiple people suggested removing blackfin independently because of some of its oddities like a non-working SMP port, and the amount of duplication between the chip variants, which cause extra work when doing cross-architecture changes. Link: https://docs.blackfin.uclinux.org/ Acked-by: Aaron Wu Acked-by: Bryan Wu Cc: Steven Miao Cc: Mike Frysinger Signed-off-by: Arnd Bergmann --- arch/blackfin/mach-bf533/ints-priority.c | 44 -------------------------------- 1 file changed, 44 deletions(-) delete mode 100644 arch/blackfin/mach-bf533/ints-priority.c (limited to 'arch/blackfin/mach-bf533/ints-priority.c') diff --git a/arch/blackfin/mach-bf533/ints-priority.c b/arch/blackfin/mach-bf533/ints-priority.c deleted file mode 100644 index 8f714cf8135b..000000000000 --- a/arch/blackfin/mach-bf533/ints-priority.c +++ /dev/null @@ -1,44 +0,0 @@ -/* - * Set up the interrupt priorities - * - * Copyright 2005-2009 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#include -#include -#include - -void __init program_IAR(void) -{ - /* Program the IAR0 Register with the configured priority */ - bfin_write_SIC_IAR0(((CONFIG_PLLWAKE_ERROR - 7) << PLLWAKE_ERROR_POS) | - ((CONFIG_DMA_ERROR - 7) << DMA_ERROR_POS) | - ((CONFIG_PPI_ERROR - 7) << PPI_ERROR_POS) | - ((CONFIG_SPORT0_ERROR - 7) << SPORT0_ERROR_POS) | - ((CONFIG_SPI_ERROR - 7) << SPI_ERROR_POS) | - ((CONFIG_SPORT1_ERROR - 7) << SPORT1_ERROR_POS) | - ((CONFIG_UART_ERROR - 7) << UART_ERROR_POS) | - ((CONFIG_RTC_ERROR - 7) << RTC_ERROR_POS)); - - bfin_write_SIC_IAR1(((CONFIG_DMA0_PPI - 7) << DMA0_PPI_POS) | - ((CONFIG_DMA1_SPORT0RX - 7) << DMA1_SPORT0RX_POS) | - ((CONFIG_DMA2_SPORT0TX - 7) << DMA2_SPORT0TX_POS) | - ((CONFIG_DMA3_SPORT1RX - 7) << DMA3_SPORT1RX_POS) | - ((CONFIG_DMA4_SPORT1TX - 7) << DMA4_SPORT1TX_POS) | - ((CONFIG_DMA5_SPI - 7) << DMA5_SPI_POS) | - ((CONFIG_DMA6_UARTRX - 7) << DMA6_UARTRX_POS) | - ((CONFIG_DMA7_UARTTX - 7) << DMA7_UARTTX_POS)); - - bfin_write_SIC_IAR2(((CONFIG_TIMER0 - 7) << TIMER0_POS) | - ((CONFIG_TIMER1 - 7) << TIMER1_POS) | - ((CONFIG_TIMER2 - 7) << TIMER2_POS) | - ((CONFIG_PFA - 7) << PFA_POS) | - ((CONFIG_PFB - 7) << PFB_POS) | - ((CONFIG_MEMDMA0 - 7) << MEMDMA0_POS) | - ((CONFIG_MEMDMA1 - 7) << MEMDMA1_POS) | - ((CONFIG_WDTIMER - 7) << WDTIMER_POS)); - - SSYNC(); -} -- cgit v1.2.3-59-g8ed1b