From 071d2f0b5419d3cf80cc8ba73ec8fe2cedc4cc0c Mon Sep 17 00:00:00 2001 From: Paul Burton Date: Tue, 1 Oct 2019 23:04:32 +0000 Subject: MIPS: r4k-bugs64: Limit R4k bug checks to affected systems Only build the checks for R4k errata workarounds if we expect that the kernel might actually run on a system with an R4k CPU - ie. CONFIG_SYS_HAS_CPU_R4X00=y & we're targeting a pre-MIPSr1 ISA revision. Rename cpu-bugs64.c to r4k-bugs64.c to indicate the fact that the code is specific to R4k CPUs. Signed-off-by: Paul Burton Cc: linux-mips@vger.kernel.org --- arch/mips/kernel/genex.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/mips/kernel/genex.S') diff --git a/arch/mips/kernel/genex.S b/arch/mips/kernel/genex.S index efde27c99414..d586cdac9605 100644 --- a/arch/mips/kernel/genex.S +++ b/arch/mips/kernel/genex.S @@ -657,7 +657,7 @@ isrdhwr: .set pop END(handle_ri_rdhwr) -#ifdef CONFIG_64BIT +#ifdef CONFIG_CPU_R4X00_BUGS64 /* A temporary overflow handler used by check_daddi(). */ __INIT -- cgit v1.2.3-59-g8ed1b From 12dbb04f2ac1fcbef0d6463abb3071ce8d8fe45f Mon Sep 17 00:00:00 2001 From: Paul Burton Date: Tue, 1 Oct 2019 21:53:42 +0000 Subject: MIPS: genex: Add Loongson3 LL/SC workaround to ejtag_debug_handler In ejtag_debug_handler we use LL & SC instructions to acquire & release an open-coded spinlock. For Loongson3 systems affected by LL/SC errata this requires that we insert a sync instruction prior to the LL in order to ensure correct behavior of the LL/SC loop. Signed-off-by: Paul Burton Cc: linux-mips@vger.kernel.org Cc: Huacai Chen Cc: Jiaxun Yang Cc: linux-kernel@vger.kernel.org --- arch/mips/kernel/genex.S | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/mips/kernel/genex.S') diff --git a/arch/mips/kernel/genex.S b/arch/mips/kernel/genex.S index d586cdac9605..637048ec2acb 100644 --- a/arch/mips/kernel/genex.S +++ b/arch/mips/kernel/genex.S @@ -18,6 +18,7 @@ #include #include #include +#include #include #include @@ -353,6 +354,7 @@ NESTED(ejtag_debug_handler, PT_SIZE, sp) #ifdef CONFIG_SMP 1: PTR_LA k0, ejtag_debug_buffer_spinlock + __SYNC(full, loongson3_war) ll k0, 0(k0) bnez k0, 1b PTR_LA k0, ejtag_debug_buffer_spinlock -- cgit v1.2.3-59-g8ed1b From 4dee90d7b5796692e8da78c7b64cf42d5e4c1b09 Mon Sep 17 00:00:00 2001 From: Paul Burton Date: Tue, 1 Oct 2019 21:53:43 +0000 Subject: MIPS: genex: Don't reload address unnecessarily In ejtag_debug_handler() we must reload the address of ejtag_debug_buffer_spinlock if an sc fails, since the address in k0 will have been clobbered by the result of the sc instruction. In the case where we simply load a non-zero value (ie. there's contention for the lock) the address will not be clobbered & we can simply branch back to repeat the load from memory without reloading the address into k0. The primary motivation for this change is that it moves the target of the bnez instruction to an instruction within the LL/SC loop (the LL itself), which we know contains no other memory accesses & therefore isn't affected by Loongson3 LL/SC errata. Signed-off-by: Paul Burton Cc: linux-mips@vger.kernel.org Cc: Huacai Chen Cc: Jiaxun Yang Cc: linux-kernel@vger.kernel.org --- arch/mips/kernel/genex.S | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/mips/kernel/genex.S') diff --git a/arch/mips/kernel/genex.S b/arch/mips/kernel/genex.S index 637048ec2acb..0a43c9125267 100644 --- a/arch/mips/kernel/genex.S +++ b/arch/mips/kernel/genex.S @@ -355,8 +355,8 @@ NESTED(ejtag_debug_handler, PT_SIZE, sp) #ifdef CONFIG_SMP 1: PTR_LA k0, ejtag_debug_buffer_spinlock __SYNC(full, loongson3_war) - ll k0, 0(k0) - bnez k0, 1b +2: ll k0, 0(k0) + bnez k0, 2b PTR_LA k0, ejtag_debug_buffer_spinlock sc k0, 0(k0) beqz k0, 1b -- cgit v1.2.3-59-g8ed1b