From a4b5bd9abcf5b0586de68722ff8e9b91020279bf Mon Sep 17 00:00:00 2001 From: Andrew Isaacson Date: Wed, 19 Oct 2005 23:57:40 -0700 Subject: SB1 cache exception handling. Expand SB1 cache error handling by adding SB1_CEX_ALWAYS_FATAL and SB1_CEX_STALL, allowing configurable behavior on cache errors. Signed-Off-By: Andy Isaacson Signed-off-by: Ralf Baechle --- arch/mips/mm/cex-sb1.S | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/mips/mm/cex-sb1.S') diff --git a/arch/mips/mm/cex-sb1.S b/arch/mips/mm/cex-sb1.S index 2c3a23aa88c3..0e71580774ff 100644 --- a/arch/mips/mm/cex-sb1.S +++ b/arch/mips/mm/cex-sb1.S @@ -64,6 +64,10 @@ LEAF(except_vec2_sb1) sd k0,0x170($0) sd k1,0x178($0) +#if CONFIG_SB1_CEX_ALWAYS_FATAL + j handle_vec2_sb1 + nop +#else /* * M_ERRCTL_RECOVERABLE is bit 31, which makes it easy to tell * if we can fast-path out of here for a h/w-recovered error. @@ -134,6 +138,7 @@ unrecoverable: /* Unrecoverable Icache or Dcache error; log it and/or fail */ j handle_vec2_sb1 nop +#endif END(except_vec2_sb1) -- cgit v1.2.3-59-g8ed1b