From ba5187dbb4b2eac99d6fa1d6bbece67e0066bf51 Mon Sep 17 00:00:00 2001 From: Thiemo Seufer Date: Mon, 25 Apr 2005 16:36:23 +0000 Subject: Better interface to run uncached cache setup code. Signed-off-by: Thiemo Seufer Signed-off-by: Ralf Baechle --- arch/mips/mm/sc-rm7k.c | 29 ++++++++--------------------- 1 file changed, 8 insertions(+), 21 deletions(-) (limited to 'arch/mips/mm/sc-rm7k.c') diff --git a/arch/mips/mm/sc-rm7k.c b/arch/mips/mm/sc-rm7k.c index 4e92f931aaba..1df5aab82c13 100644 --- a/arch/mips/mm/sc-rm7k.c +++ b/arch/mips/mm/sc-rm7k.c @@ -15,6 +15,7 @@ #include #include #include +#include /* for run_uncached() */ /* Primary cache parameters. */ #define sc_lsize 32 @@ -96,25 +97,13 @@ static void rm7k_sc_inv(unsigned long addr, unsigned long size) } /* - * This function is executed in the uncached segment CKSEG1. - * It must not touch the stack, because the stack pointer still points - * into CKSEG0. - * - * Three options: - * - Write it in assembly and guarantee that we don't use the stack. - * - Disable caching for CKSEG0 before calling it. - * - Pray that GCC doesn't randomly start using the stack. - * - * This being Linux, we obviously take the least sane of those options - - * following DaveM's lead in c-r4k.c - * - * It seems we get our kicks from relying on unguaranteed behaviour in GCC + * This function is executed in uncached address space. */ static __init void __rm7k_sc_enable(void) { int i; - set_c0_config(1 << 3); /* CONF_SE */ + set_c0_config(R7K_CONF_SE); write_c0_taglo(0); write_c0_taghi(0); @@ -127,24 +116,22 @@ static __init void __rm7k_sc_enable(void) ".set mips0\n\t" ".set reorder" : - : "r" (KSEG0ADDR(i)), "i" (Index_Store_Tag_SD)); + : "r" (CKSEG0ADDR(i)), "i" (Index_Store_Tag_SD)); } } static __init void rm7k_sc_enable(void) { - void (*func)(void) = (void *) KSEG1ADDR(&__rm7k_sc_enable); - - if (read_c0_config() & 0x08) /* CONF_SE */ + if (read_c0_config() & R7K_CONF_SE) return; printk(KERN_INFO "Enabling secondary cache..."); - func(); + run_uncached(__rm7k_sc_enable); } static void rm7k_sc_disable(void) { - clear_c0_config(1<<3); /* CONF_SE */ + clear_c0_config(R7K_CONF_SE); } struct bcache_ops rm7k_sc_ops = { @@ -164,7 +151,7 @@ void __init rm7k_sc_init(void) printk(KERN_INFO "Secondary cache size %dK, linesize %d bytes.\n", (scache_size >> 10), sc_lsize); - if (!((config >> 3) & 1)) /* CONF_SE */ + if (!(config & R7K_CONF_SE)) rm7k_sc_enable(); /* -- cgit v1.2.3-59-g8ed1b From c6ad7b7d3cd7883810c05fad9d30303cf9368f63 Mon Sep 17 00:00:00 2001 From: "Maciej W. Rozycki" Date: Mon, 20 Jun 2005 13:09:49 +0000 Subject: Use macros for the RM7k cp0.config bits instead of magic numbers. Minor clean-ups. Signed-off-by: Ralf Baechle --- arch/mips/mm/sc-rm7k.c | 18 +++++++++--------- include/asm-mips/mipsregs.h | 9 +++++++-- 2 files changed, 16 insertions(+), 11 deletions(-) (limited to 'arch/mips/mm/sc-rm7k.c') diff --git a/arch/mips/mm/sc-rm7k.c b/arch/mips/mm/sc-rm7k.c index 1df5aab82c13..9e8ff8badb19 100644 --- a/arch/mips/mm/sc-rm7k.c +++ b/arch/mips/mm/sc-rm7k.c @@ -103,7 +103,7 @@ static __init void __rm7k_sc_enable(void) { int i; - set_c0_config(R7K_CONF_SE); + set_c0_config(RM7K_CONF_SE); write_c0_taglo(0); write_c0_taghi(0); @@ -122,16 +122,16 @@ static __init void __rm7k_sc_enable(void) static __init void rm7k_sc_enable(void) { - if (read_c0_config() & R7K_CONF_SE) + if (read_c0_config() & RM7K_CONF_SE) return; - printk(KERN_INFO "Enabling secondary cache..."); + printk(KERN_INFO "Enabling secondary cache...\n"); run_uncached(__rm7k_sc_enable); } static void rm7k_sc_disable(void) { - clear_c0_config(R7K_CONF_SE); + clear_c0_config(RM7K_CONF_SE); } struct bcache_ops rm7k_sc_ops = { @@ -145,19 +145,19 @@ void __init rm7k_sc_init(void) { unsigned int config = read_c0_config(); - if ((config >> 31) & 1) /* Bit 31 set -> no S-Cache */ + if ((config & RM7K_CONF_SC)) return; printk(KERN_INFO "Secondary cache size %dK, linesize %d bytes.\n", (scache_size >> 10), sc_lsize); - if (!(config & R7K_CONF_SE)) + if (!(config & RM7K_CONF_SE)) rm7k_sc_enable(); /* * While we're at it let's deal with the tertiary cache. */ - if (!((config >> 17) & 1)) { + if (!(config & RM7K_CONF_TC)) { /* * We can't enable the L3 cache yet. There may be board-specific @@ -170,9 +170,9 @@ void __init rm7k_sc_init(void) * to probe it. */ printk(KERN_INFO "Tertiary cache present, %s enabled\n", - config&(1<<12) ? "already" : "not (yet)"); + (config & RM7K_CONF_TE) ? "already" : "not (yet)"); - if ((config >> 12) & 1) + if ((config & RM7K_CONF_TE)) rm7k_tcache_enabled = 1; } diff --git a/include/asm-mips/mipsregs.h b/include/asm-mips/mipsregs.h index 870717391a93..dd494cae4a44 100644 --- a/include/asm-mips/mipsregs.h +++ b/include/asm-mips/mipsregs.h @@ -425,6 +425,7 @@ #define CONF_SM (_ULCAST_(1) << 16) #define CONF_SC (_ULCAST_(1) << 17) #define CONF_EW (_ULCAST_(3) << 18) +#define CONF_SB (_ULCAST_(3) << 22) #define CONF_EP (_ULCAST_(15)<< 24) #define CONF_EC (_ULCAST_(7) << 28) #define CONF_CM (_ULCAST_(1) << 31) @@ -432,14 +433,18 @@ /* Bits specific to the R4xx0. */ #define R4K_CONF_SW (_ULCAST_(1) << 20) #define R4K_CONF_SS (_ULCAST_(1) << 21) -#define R4K_CONF_SB (_ULCAST_(3) << 22) /* Bits specific to the R5000. */ #define R5K_CONF_SE (_ULCAST_(1) << 12) #define R5K_CONF_SS (_ULCAST_(3) << 20) /* Bits specific to the RM7000. */ -#define R7K_CONF_SE (_ULCAST_(1) << 3) +#define RM7K_CONF_SE (_ULCAST_(1) << 3) +#define RM7K_CONF_TE (_ULCAST_(1) << 12) +#define RM7K_CONF_CLK (_ULCAST_(1) << 16) +#define RM7K_CONF_TC (_ULCAST_(1) << 17) +#define RM7K_CONF_SI (_ULCAST_(3) << 20) +#define RM7K_CONF_SC (_ULCAST_(1) << 31) /* Bits specific to the R10000. */ #define R10K_CONF_DN (_ULCAST_(3) << 3) -- cgit v1.2.3-59-g8ed1b