From 6e61e85b0980f7b88cd5c4b822386ed00dd7e295 Mon Sep 17 00:00:00 2001 From: Thiemo Seufer Date: Wed, 5 Jul 2006 14:26:38 +0100 Subject: [MIPS] Sibyte: Improve interrupt latency again for sb1250/bcm1480 this patch restores the behaviour of the old (assembly-written) interrupt handler, the handler is left as soon as a single interrupt cause is handled. Signed-off-by: Thiemo Seufer Signed-off-by: Ralf Baechle --- arch/mips/sibyte/bcm1480/irq.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) (limited to 'arch/mips/sibyte/bcm1480/irq.c') diff --git a/arch/mips/sibyte/bcm1480/irq.c b/arch/mips/sibyte/bcm1480/irq.c index 2c5afb4c2ef3..cab78fb5a9ac 100644 --- a/arch/mips/sibyte/bcm1480/irq.c +++ b/arch/mips/sibyte/bcm1480/irq.c @@ -502,22 +502,23 @@ asmlinkage void plat_irq_dispatch(struct pt_regs *regs) #ifdef CONFIG_SIBYTE_BCM1480_PROF if (pending & CAUSEF_IP7) /* Cpu performance counter interrupt */ sbprof_cpu_intr(exception_epc(regs)); + else #endif if (pending & CAUSEF_IP4) bcm1480_timer_interrupt(regs); #ifdef CONFIG_SMP - if (pending & CAUSEF_IP3) + else if (pending & CAUSEF_IP3) bcm1480_mailbox_interrupt(regs); #endif #ifdef CONFIG_KGDB - if (pending & CAUSEF_IP6) + else if (pending & CAUSEF_IP6) bcm1480_kgdb_interrupt(regs); /* KGDB (uart 1) */ #endif - if (pending & CAUSEF_IP2) { + else if (pending & CAUSEF_IP2) { unsigned long long mask_h, mask_l; unsigned long base; -- cgit v1.2.3-59-g8ed1b