From c51e078f82096a7d35ac8ec2416272e843a0e1c4 Mon Sep 17 00:00:00 2001 From: Marcelo Tosatti Date: Fri, 5 May 2006 17:09:29 -0300 Subject: [PATCH] ppc32/8xx: Fix r3 trashing due to 8MB TLB page instantiation Instantiation of 8MB pages on the TLB cache for the kernel static mapping trashes r3 register on !CONFIG_8xx_CPU6 configurations. This ensures r3 gets saved and restored. Signed-off-by: Marcelo Tosatti Signed-off-by: Paul Mackerras --- arch/ppc/kernel/head_8xx.S | 4 ---- 1 file changed, 4 deletions(-) (limited to 'arch/ppc/kernel') diff --git a/arch/ppc/kernel/head_8xx.S b/arch/ppc/kernel/head_8xx.S index ec53c7d65f2b..7a2f20583be4 100644 --- a/arch/ppc/kernel/head_8xx.S +++ b/arch/ppc/kernel/head_8xx.S @@ -355,9 +355,7 @@ InstructionTLBMiss: . = 0x1200 DataStoreTLBMiss: -#ifdef CONFIG_8xx_CPU6 stw r3, 8(r0) -#endif DO_8xx_CPU6(0x3f80, r3) mtspr SPRN_M_TW, r10 /* Save a couple of working registers */ mfcr r10 @@ -417,9 +415,7 @@ DataStoreTLBMiss: lwz r11, 0(r0) mtcr r11 lwz r11, 4(r0) -#ifdef CONFIG_8xx_CPU6 lwz r3, 8(r0) -#endif rfi /* This is an instruction TLB error on the MPC8xx. This could be due -- cgit v1.2.3-59-g8ed1b