From 1823f6d5e6b81cca6542ed2e5f30d2556aad0f67 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Thu, 28 May 2009 12:06:17 +0000 Subject: sh: sh7785 pll configuration from mode pin This patch modifies the sh7785 clock code to use the MODE4 value to switch between 72x and 36x PLL multiplication. Signed-off-by: Magnus Damm Signed-off-by: Paul Mundt --- arch/sh/kernel/cpu/sh4a/clock-sh7785.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'arch/sh/kernel/cpu') diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7785.c b/arch/sh/kernel/cpu/sh4a/clock-sh7785.c index a4a9bcbec664..705b023f8220 100644 --- a/arch/sh/kernel/cpu/sh4a/clock-sh7785.c +++ b/arch/sh/kernel/cpu/sh4a/clock-sh7785.c @@ -16,6 +16,7 @@ #include #include #include +#include static unsigned int div2[] = { 1, 2, 4, 6, 8, 12, 16, 18, 24, 32, 36, 48 }; @@ -80,12 +81,11 @@ static struct clk_ops frqmr_clk_ops = { static unsigned long pll_recalc(struct clk *clk) { - /* - * XXX: PLL1 multiplier is locked for the default clock mode, - * when mode pin detection and configuration support is added, - * select the multiplier dynamically. - */ - return clk->parent->rate * 36; + int multiplier; + + multiplier = test_mode_pin(MODE_PIN_MODE4) ? 36 : 72; + + return clk->parent->rate * multiplier; } static struct clk_ops pll_clk_ops = { -- cgit v1.2.3-59-g8ed1b