From d1b6886502160eb771aefe21c1f891597138ddfe Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 14 Sep 2012 16:14:25 +0800 Subject: unicore32: pwm: Properly remap memory-mapped registers Instead of writing to the timer controller registers by dereferencing a pointer to the memory location, properly remap the memory region with a call to ioremap_nocache() and access the registers using writel(). Signed-off-by: Thierry Reding Signed-off-by: Guan Xuetao Tested-by: Qin Rui --- arch/unicore32/include/mach/regs-ost.h | 18 ++++++++---------- 1 file changed, 8 insertions(+), 10 deletions(-) (limited to 'arch/unicore32/include/mach') diff --git a/arch/unicore32/include/mach/regs-ost.h b/arch/unicore32/include/mach/regs-ost.h index 7b91fe698eed..4a85fb463848 100644 --- a/arch/unicore32/include/mach/regs-ost.h +++ b/arch/unicore32/include/mach/regs-ost.h @@ -33,18 +33,16 @@ * Interrupt Enable Reg OST_OIER */ #define OST_OIER (PKUNITY_OST_BASE + 0x001C) + /* - * PWM Pulse Width Control Reg OST_PWMPWCR - */ -#define OST_PWMPWCR (PKUNITY_OST_BASE + 0x0080) -/* - * PWM Duty Cycle Control Reg OST_PWMDCCR - */ -#define OST_PWMDCCR (PKUNITY_OST_BASE + 0x0084) -/* - * PWM Period Control Reg OST_PWMPCR + * PWM Registers: IO base address: PKUNITY_OST_BASE + 0x80 + * PWCR: Pulse Width Control Reg + * DCCR: Duty Cycle Control Reg + * PCR: Period Control Reg */ -#define OST_PWMPCR (PKUNITY_OST_BASE + 0x0088) +#define OST_PWM_PWCR (0x00) +#define OST_PWM_DCCR (0x04) +#define OST_PWM_PCR (0x08) /* * Match detected 0 OST_OSSR_M0 -- cgit v1.2.3-59-g8ed1b